[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_i2c.c

/*
 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
 * Copyright © 2006-2008,2010 Intel Corporation
 *   Jesse Barnes <jesse.barnes@intel.com>
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice (including the next
 * paragraph) shall be included in all copies or substantial portions of the
 * Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
 * DEALINGS IN THE SOFTWARE.
 *
 * Authors:
 *	Eric Anholt <eric@anholt.net>
 *	Chris Wilson <chris@chris-wilson.co.uk>
 */
#include <linux/i2c.h>
#include <linux/i2c-algo-bit.h>
#include <linux/export.h>
#include "drmP.h"
#include "drm.h"
#include "intel_drv.h"
#include "i915_drm.h"
#include "i915_drv.h"

/* Intel GPIO access functions */

#define I2C_RISEFALL_TIME 10

static inline struct intel_gmbus *
to_intel_gmbus(struct i2c_adapter *i2c)
{
	return container_of(i2c, struct intel_gmbus, adapter);
}

void
intel_i2c_reset(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	if (HAS_PCH_SPLIT(dev))
		I915_WRITE(PCH_GMBUS0, 0);
	else
		I915_WRITE(GMBUS0, 0);
}

static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
{
	u32 val;

	/* When using bit bashing for I2C, this bit needs to be set to 1 */
	if (!IS_PINEVIEW(dev_priv->dev))
		return;

	val = I915_READ(DSPCLK_GATE_D);
	if (enable)
		val |= DPCUNIT_CLOCK_GATE_DISABLE;
	else
		val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
	I915_WRITE(DSPCLK_GATE_D, val);
}

static u32 get_reserved(struct intel_gmbus *bus)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	struct drm_device *dev = dev_priv->dev;
	u32 reserved = 0;

	/* On most chips, these bits must be preserved in software. */
	if (!IS_I830(dev) && !IS_845G(dev))
		reserved = I915_READ_NOTRACE(bus->gpio_reg) &
					     (GPIO_DATA_PULLUP_DISABLE |
					      GPIO_CLOCK_PULLUP_DISABLE);

	return reserved;
}

static int get_clock(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_CLOCK_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
}

static int get_data(void *data)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | GPIO_DATA_DIR_MASK);
	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
}

static void set_clock(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 clock_bits;

	if (state_high)
		clock_bits = GPIO_CLOCK_DIR_IN | GPIO_CLOCK_DIR_MASK;
	else
		clock_bits = GPIO_CLOCK_DIR_OUT | GPIO_CLOCK_DIR_MASK |
			GPIO_CLOCK_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | clock_bits);
	POSTING_READ(bus->gpio_reg);
}

static void set_data(void *data, int state_high)
{
	struct intel_gmbus *bus = data;
	struct drm_i915_private *dev_priv = bus->dev_priv;
	u32 reserved = get_reserved(bus);
	u32 data_bits;

	if (state_high)
		data_bits = GPIO_DATA_DIR_IN | GPIO_DATA_DIR_MASK;
	else
		data_bits = GPIO_DATA_DIR_OUT | GPIO_DATA_DIR_MASK |
			GPIO_DATA_VAL_MASK;

	I915_WRITE_NOTRACE(bus->gpio_reg, reserved | data_bits);
	POSTING_READ(bus->gpio_reg);
}

static bool
intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	static const int map_pin_to_reg[] = {
		0,
		GPIOB,
		GPIOA,
		GPIOC,
		GPIOD,
		GPIOE,
		0,
		GPIOF,
	};
	struct i2c_algo_bit_data *algo;

	if (pin >= ARRAY_SIZE(map_pin_to_reg) || !map_pin_to_reg[pin])
		return false;

	algo = &bus->bit_algo;

	bus->gpio_reg = map_pin_to_reg[pin];
	if (HAS_PCH_SPLIT(dev_priv->dev))
		bus->gpio_reg += PCH_GPIOA - GPIOA;

	bus->adapter.algo_data = algo;
	algo->setsda = set_data;
	algo->setscl = set_clock;
	algo->getsda = get_data;
	algo->getscl = get_clock;
	algo->udelay = I2C_RISEFALL_TIME;
	algo->timeout = usecs_to_jiffies(2200);
	algo->data = bus;

	return true;
}

static int
intel_i2c_quirk_xfer(struct intel_gmbus *bus,
		     struct i2c_msg *msgs,
		     int num)
{
	struct drm_i915_private *dev_priv = bus->dev_priv;
	int ret;

	intel_i2c_reset(dev_priv->dev);

	intel_i2c_quirk_set(dev_priv, true);
	set_data(bus, 1);
	set_clock(bus, 1);
	udelay(I2C_RISEFALL_TIME);

	ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);

	set_data(bus, 1);
	set_clock(bus, 1);
	intel_i2c_quirk_set(dev_priv, false);

	return ret;
}

static int
gmbus_xfer(struct i2c_adapter *adapter,
	   struct i2c_msg *msgs,
	   int num)
{
	struct intel_gmbus *bus = container_of(adapter,
					       struct intel_gmbus,
					       adapter);
	struct drm_i915_private *dev_priv = bus->dev_priv;
	int i, reg_offset, ret;

	mutex_lock(&dev_priv->gmbus_mutex);

	if (bus->force_bit) {
		ret = intel_i2c_quirk_xfer(bus, msgs, num);
		goto out;
	}

	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;

	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);

	for (i = 0; i < num; i++) {
		u16 len = msgs[i].len;
		u8 *buf = msgs[i].buf;

		if (msgs[i].flags & I2C_M_RD) {
			I915_WRITE(GMBUS1 + reg_offset,
				   GMBUS_CYCLE_WAIT |
				   (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
				   (len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_READ | GMBUS_SW_RDY);
			POSTING_READ(GMBUS2+reg_offset);
			do {
				u32 val, loop = 0;

				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					goto clear_err;

				val = I915_READ(GMBUS3 + reg_offset);
				do {
					*buf++ = val & 0xff;
					val >>= 8;
				} while (--len && ++loop < 4);
			} while (len);
		} else {
			u32 val, loop;

			val = loop = 0;
			do {
				val |= *buf++ << (8 * loop);
			} while (--len && ++loop < 4);

			I915_WRITE(GMBUS3 + reg_offset, val);
			I915_WRITE(GMBUS1 + reg_offset,
				   GMBUS_CYCLE_WAIT |
				   (i + 1 == num ? GMBUS_CYCLE_STOP : 0) |
				   (msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) |
				   (msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) |
				   GMBUS_SLAVE_WRITE | GMBUS_SW_RDY);
			POSTING_READ(GMBUS2+reg_offset);

			while (len) {
				if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_RDY), 50))
					goto timeout;
				if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
					goto clear_err;

				val = loop = 0;
				do {
					val |= *buf++ << (8 * loop);
				} while (--len && ++loop < 4);

				I915_WRITE(GMBUS3 + reg_offset, val);
				POSTING_READ(GMBUS2+reg_offset);
			}
		}

		if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER | GMBUS_HW_WAIT_PHASE), 50))
			goto timeout;
		if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
			goto clear_err;
	}

	goto done;

clear_err:
	/* Toggle the Software Clear Interrupt bit. This has the effect
	 * of resetting the GMBUS controller and so clearing the
	 * BUS_ERROR raised by the slave's NAK.
	 */
	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	I915_WRITE(GMBUS1 + reg_offset, 0);

done:
	/* Mark the GMBUS interface as disabled after waiting for idle.
	 * We will re-enable it at the start of the next xfer,
	 * till then let it sleep.
	 */
	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
		DRM_INFO("GMBUS timed out waiting for idle\n");
	I915_WRITE(GMBUS0 + reg_offset, 0);
	ret = i;
	goto out;

timeout:
	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
		 bus->reg0 & 0xff, bus->adapter.name);
	I915_WRITE(GMBUS0 + reg_offset, 0);

	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
	if (!bus->has_gpio) {
		ret = -EIO;
	} else {
		bus->force_bit = true;
		ret = intel_i2c_quirk_xfer(bus, msgs, num);
	}
out:
	mutex_unlock(&dev_priv->gmbus_mutex);
	return ret;
}

static u32 gmbus_func(struct i2c_adapter *adapter)
{
	return i2c_bit_algo.functionality(adapter) &
		(I2C_FUNC_I2C | I2C_FUNC_SMBUS_EMUL |
		/* I2C_FUNC_10BIT_ADDR | */
		I2C_FUNC_SMBUS_READ_BLOCK_DATA |
		I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
}

static const struct i2c_algorithm gmbus_algorithm = {
	.master_xfer	= gmbus_xfer,
	.functionality	= gmbus_func
};

/**
 * intel_gmbus_setup - instantiate all Intel i2c GMBuses
 * @dev: DRM device
 */
int intel_setup_gmbus(struct drm_device *dev)
{
	static const char *names[GMBUS_NUM_PORTS] = {
		"disabled",
		"ssc",
		"vga",
		"panel",
		"dpc",
		"dpb",
		"reserved",
		"dpd",
	};
	struct drm_i915_private *dev_priv = dev->dev_private;
	int ret, i;

	dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
				  GFP_KERNEL);
	if (dev_priv->gmbus == NULL)
		return -ENOMEM;

	mutex_init(&dev_priv->gmbus_mutex);

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];

		bus->adapter.owner = THIS_MODULE;
		bus->adapter.class = I2C_CLASS_DDC;
		snprintf(bus->adapter.name,
			 sizeof(bus->adapter.name),
			 "i915 gmbus %s",
			 names[i]);

		bus->adapter.dev.parent = &dev->pdev->dev;
		bus->dev_priv = dev_priv;

		bus->adapter.algo = &gmbus_algorithm;
		ret = i2c_add_adapter(&bus->adapter);
		if (ret)
			goto err;

		/* By default use a conservative clock rate */
		bus->reg0 = i | GMBUS_RATE_100KHZ;

		bus->has_gpio = intel_gpio_setup(bus, i);

		/* XXX force bit banging until GMBUS is fully debugged */
		if (bus->has_gpio)
			bus->force_bit = true;
	}

	intel_i2c_reset(dev_priv->dev);

	return 0;

err:
	while (--i) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}
	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
	return ret;
}

void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) | speed;
}

void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
{
	struct intel_gmbus *bus = to_intel_gmbus(adapter);

	if (bus->has_gpio)
		bus->force_bit = force_bit;
}

void intel_teardown_gmbus(struct drm_device *dev)
{
	struct drm_i915_private *dev_priv = dev->dev_private;
	int i;

	if (dev_priv->gmbus == NULL)
		return;

	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
		struct intel_gmbus *bus = &dev_priv->gmbus[i];
		i2c_del_adapter(&bus->adapter);
	}

	kfree(dev_priv->gmbus);
	dev_priv->gmbus = NULL;
}
Commit	Line	Data
79e53945 JB	1	/*
79e53945 JB	2	* Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
f899fc64	3	* Copyright © 2006-2008,2010 Intel Corporation
79e53945 JB	4	* Jesse Barnes <jesse.barnes@intel.com>
	5	*
	6	* Permission is hereby granted, free of charge, to any person obtaining a
	7	* copy of this software and associated documentation files (the "Software"),
	8	* to deal in the Software without restriction, including without limitation
	9	* the rights to use, copy, modify, merge, publish, distribute, sublicense,
	10	* and/or sell copies of the Software, and to permit persons to whom the
	11	* Software is furnished to do so, subject to the following conditions:
	12	*
	13	* The above copyright notice and this permission notice (including the next
	14	* paragraph) shall be included in all copies or substantial portions of the
	15	* Software.
	16	*
	17	* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
	18	* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
	19	* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
	20	* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
	21	* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
	22	* FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
	23	* DEALINGS IN THE SOFTWARE.
	24	*
	25	* Authors:
	26	* Eric Anholt <eric@anholt.net>
f899fc64	27	* Chris Wilson <chris@chris-wilson.co.uk>
79e53945 JB	28	*/
79e53945 JB	29	#include <linux/i2c.h>
79e53945	30	#include <linux/i2c-algo-bit.h>
2d1a8a48	31	#include <linux/export.h>
79e53945 JB	32	#include "drmP.h"
	33	#include "drm.h"
	34	#include "intel_drv.h"
	35	#include "i915_drm.h"
	36	#include "i915_drv.h"
	37
f899fc64 CW	38	/* Intel GPIO access functions */
f899fc64 CW	39
1849ecb2	40	#define I2C_RISEFALL_TIME 10
f899fc64	41
e957d772 CW	42	static inline struct intel_gmbus *
	43	to_intel_gmbus(struct i2c_adapter *i2c)
	44	{
	45	return container_of(i2c, struct intel_gmbus, adapter);
	46	}
	47
f899fc64 CW	48	void
f899fc64 CW	49	intel_i2c_reset(struct drm_device *dev)
0ba0e9e1 SL	50	{
0ba0e9e1 SL	51	struct drm_i915_private *dev_priv = dev->dev_private;
f899fc64 CW	52	if (HAS_PCH_SPLIT(dev))
	53	I915_WRITE(PCH_GMBUS0, 0);
	54	else
	55	I915_WRITE(GMBUS0, 0);
	56	}
	57
	58	static void intel_i2c_quirk_set(struct drm_i915_private *dev_priv, bool enable)
	59	{
b222f267	60	u32 val;
0ba0e9e1 SL	61
0ba0e9e1 SL	62	/* When using bit bashing for I2C, this bit needs to be set to 1 */
f899fc64	63	if (!IS_PINEVIEW(dev_priv->dev))
0ba0e9e1	64	return;
b222f267 CW	65
b222f267 CW	66	val = I915_READ(DSPCLK_GATE_D);
0ba0e9e1	67	if (enable)
b222f267	68	val \|= DPCUNIT_CLOCK_GATE_DISABLE;
0ba0e9e1	69	else
b222f267 CW	70	val &= ~DPCUNIT_CLOCK_GATE_DISABLE;
b222f267 CW	71	I915_WRITE(DSPCLK_GATE_D, val);
0ba0e9e1 SL	72	}
0ba0e9e1 SL	73
36c785f0	74	static u32 get_reserved(struct intel_gmbus *bus)
e957d772	75	{
36c785f0	76	struct drm_i915_private *dev_priv = bus->dev_priv;
e957d772 CW	77	struct drm_device *dev = dev_priv->dev;
	78	u32 reserved = 0;
	79
	80	/* On most chips, these bits must be preserved in software. */
	81	if (!IS_I830(dev) && !IS_845G(dev))
36c785f0	82	reserved = I915_READ_NOTRACE(bus->gpio_reg) &
db5e4172 YL	83	(GPIO_DATA_PULLUP_DISABLE \|
db5e4172 YL	84	GPIO_CLOCK_PULLUP_DISABLE);
e957d772 CW	85
	86	return reserved;
	87	}
	88
79e53945 JB	89	static int get_clock(void *data)
79e53945 JB	90	{
36c785f0 DV	91	struct intel_gmbus *bus = data;
	92	struct drm_i915_private *dev_priv = bus->dev_priv;
	93	u32 reserved = get_reserved(bus);
	94	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_CLOCK_DIR_MASK);
	95	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	96	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_CLOCK_VAL_IN) != 0;
79e53945 JB	97	}
	98
	99	static int get_data(void *data)
	100	{
36c785f0 DV	101	struct intel_gmbus *bus = data;
	102	struct drm_i915_private *dev_priv = bus->dev_priv;
	103	u32 reserved = get_reserved(bus);
	104	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| GPIO_DATA_DIR_MASK);
	105	I915_WRITE_NOTRACE(bus->gpio_reg, reserved);
	106	return (I915_READ_NOTRACE(bus->gpio_reg) & GPIO_DATA_VAL_IN) != 0;
79e53945 JB	107	}
	108
	109	static void set_clock(void *data, int state_high)
	110	{
36c785f0 DV	111	struct intel_gmbus *bus = data;
	112	struct drm_i915_private *dev_priv = bus->dev_priv;
	113	u32 reserved = get_reserved(bus);
e957d772	114	u32 clock_bits;
79e53945 JB	115
	116	if (state_high)
	117	clock_bits = GPIO_CLOCK_DIR_IN \| GPIO_CLOCK_DIR_MASK;
	118	else
	119	clock_bits = GPIO_CLOCK_DIR_OUT \| GPIO_CLOCK_DIR_MASK \|
	120	GPIO_CLOCK_VAL_MASK;
f899fc64	121
36c785f0 DV	122	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| clock_bits);
36c785f0 DV	123	POSTING_READ(bus->gpio_reg);
79e53945 JB	124	}
	125
	126	static void set_data(void *data, int state_high)
	127	{
36c785f0 DV	128	struct intel_gmbus *bus = data;
	129	struct drm_i915_private *dev_priv = bus->dev_priv;
	130	u32 reserved = get_reserved(bus);
e957d772	131	u32 data_bits;
79e53945 JB	132
	133	if (state_high)
	134	data_bits = GPIO_DATA_DIR_IN \| GPIO_DATA_DIR_MASK;
	135	else
	136	data_bits = GPIO_DATA_DIR_OUT \| GPIO_DATA_DIR_MASK \|
	137	GPIO_DATA_VAL_MASK;
	138
36c785f0 DV	139	I915_WRITE_NOTRACE(bus->gpio_reg, reserved \| data_bits);
36c785f0 DV	140	POSTING_READ(bus->gpio_reg);
79e53945 JB	141	}
79e53945 JB	142
f6f808c8 DV	143	static bool
f6f808c8 DV	144	intel_gpio_setup(struct intel_gmbus *bus, u32 pin)
f0217c42	145	{
36c785f0	146	struct drm_i915_private *dev_priv = bus->dev_priv;
f899fc64 CW	147	static const int map_pin_to_reg[] = {
	148	0,
	149	GPIOB,
	150	GPIOA,
	151	GPIOC,
	152	GPIOD,
	153	GPIOE,
7b5337dd	154	0,
f899fc64 CW	155	GPIOF,
f899fc64 CW	156	};
36c785f0	157	struct i2c_algo_bit_data *algo;
f0217c42	158
69669455	159	if (pin >= ARRAY_SIZE(map_pin_to_reg) \|\| !map_pin_to_reg[pin])
f6f808c8	160	return false;
f0217c42	161
c167a6fc	162	algo = &bus->bit_algo;
36c785f0 DV	163
36c785f0 DV	164	bus->gpio_reg = map_pin_to_reg[pin];
f899fc64	165	if (HAS_PCH_SPLIT(dev_priv->dev))
36c785f0	166	bus->gpio_reg += PCH_GPIOA - GPIOA;
79e53945	167
c167a6fc	168	bus->adapter.algo_data = algo;
36c785f0 DV	169	algo->setsda = set_data;
	170	algo->setscl = set_clock;
	171	algo->getsda = get_data;
	172	algo->getscl = get_clock;
	173	algo->udelay = I2C_RISEFALL_TIME;
	174	algo->timeout = usecs_to_jiffies(2200);
	175	algo->data = bus;
	176
f6f808c8	177	return true;
79e53945 JB	178	}
79e53945 JB	179
f899fc64	180	static int
36c785f0	181	intel_i2c_quirk_xfer(struct intel_gmbus *bus,
e957d772 CW	182	struct i2c_msg *msgs,
e957d772 CW	183	int num)
f899fc64	184	{
36c785f0	185	struct drm_i915_private *dev_priv = bus->dev_priv;
f899fc64 CW	186	int ret;
	187
	188	intel_i2c_reset(dev_priv->dev);
	189
	190	intel_i2c_quirk_set(dev_priv, true);
36c785f0 DV	191	set_data(bus, 1);
36c785f0 DV	192	set_clock(bus, 1);
e957d772 CW	193	udelay(I2C_RISEFALL_TIME);
e957d772 CW	194
f6f808c8	195	ret = i2c_bit_algo.master_xfer(&bus->adapter, msgs, num);
e957d772	196
36c785f0 DV	197	set_data(bus, 1);
36c785f0 DV	198	set_clock(bus, 1);
f899fc64 CW	199	intel_i2c_quirk_set(dev_priv, false);
	200
	201	return ret;
	202	}
	203
	204	static int
	205	gmbus_xfer(struct i2c_adapter *adapter,
	206	struct i2c_msg *msgs,
	207	int num)
	208	{
	209	struct intel_gmbus *bus = container_of(adapter,
	210	struct intel_gmbus,
	211	adapter);
c2b9152f	212	struct drm_i915_private *dev_priv = bus->dev_priv;
8a8ed1f5	213	int i, reg_offset, ret;
f899fc64	214
8a8ed1f5 YS	215	mutex_lock(&dev_priv->gmbus_mutex);
	216
	217	if (bus->force_bit) {
f6f808c8	218	ret = intel_i2c_quirk_xfer(bus, msgs, num);
8a8ed1f5 YS	219	goto out;
8a8ed1f5 YS	220	}
f899fc64 CW	221
	222	reg_offset = HAS_PCH_SPLIT(dev_priv->dev) ? PCH_GMBUS0 - GMBUS0 : 0;
	223
e957d772	224	I915_WRITE(GMBUS0 + reg_offset, bus->reg0);
f899fc64 CW	225
	226	for (i = 0; i < num; i++) {
	227	u16 len = msgs[i].len;
	228	u8 *buf = msgs[i].buf;
	229
	230	if (msgs[i].flags & I2C_M_RD) {
	231	I915_WRITE(GMBUS1 + reg_offset,
caae745a BL	232	GMBUS_CYCLE_WAIT \|
caae745a BL	233	(i + 1 == num ? GMBUS_CYCLE_STOP : 0) \|
f899fc64 CW	234	(len << GMBUS_BYTE_COUNT_SHIFT) \|
	235	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	236	GMBUS_SLAVE_READ \| GMBUS_SW_RDY);
e957d772	237	POSTING_READ(GMBUS2+reg_offset);
f899fc64 CW	238	do {
	239	u32 val, loop = 0;
	240
	241	if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
	242	goto timeout;
	243	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
7f58aabc	244	goto clear_err;
f899fc64 CW	245
	246	val = I915_READ(GMBUS3 + reg_offset);
	247	do {
	248	*buf++ = val & 0xff;
	249	val >>= 8;
	250	} while (--len && ++loop < 4);
	251	} while (len);
	252	} else {
e957d772	253	u32 val, loop;
f899fc64	254
e957d772	255	val = loop = 0;
f899fc64	256	do {
e957d772 CW	257	val \|= buf++ << (8 loop);
e957d772 CW	258	} while (--len && ++loop < 4);
f899fc64 CW	259
	260	I915_WRITE(GMBUS3 + reg_offset, val);
	261	I915_WRITE(GMBUS1 + reg_offset,
caae745a BL	262	GMBUS_CYCLE_WAIT \|
caae745a BL	263	(i + 1 == num ? GMBUS_CYCLE_STOP : 0) \|
f899fc64 CW	264	(msgs[i].len << GMBUS_BYTE_COUNT_SHIFT) \|
	265	(msgs[i].addr << GMBUS_SLAVE_ADDR_SHIFT) \|
	266	GMBUS_SLAVE_WRITE \| GMBUS_SW_RDY);
e957d772 CW	267	POSTING_READ(GMBUS2+reg_offset);
	268
	269	while (len) {
	270	if (wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_RDY), 50))
	271	goto timeout;
	272	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
7f58aabc	273	goto clear_err;
e957d772 CW	274
	275	val = loop = 0;
	276	do {
	277	val \|= buf++ << (8 loop);
	278	} while (--len && ++loop < 4);
	279
	280	I915_WRITE(GMBUS3 + reg_offset, val);
	281	POSTING_READ(GMBUS2+reg_offset);
	282	}
f899fc64 CW	283	}
	284
	285	if (i + 1 < num && wait_for(I915_READ(GMBUS2 + reg_offset) & (GMBUS_SATOER \| GMBUS_HW_WAIT_PHASE), 50))
	286	goto timeout;
	287	if (I915_READ(GMBUS2 + reg_offset) & GMBUS_SATOER)
7f58aabc	288	goto clear_err;
f899fc64 CW	289	}
f899fc64 CW	290
7f58aabc CW	291	goto done;
	292
	293	clear_err:
	294	/* Toggle the Software Clear Interrupt bit. This has the effect
	295	* of resetting the GMBUS controller and so clearing the
	296	* BUS_ERROR raised by the slave's NAK.
	297	*/
	298	I915_WRITE(GMBUS1 + reg_offset, GMBUS_SW_CLR_INT);
	299	I915_WRITE(GMBUS1 + reg_offset, 0);
	300
	301	done:
caae745a BL	302	/* Mark the GMBUS interface as disabled after waiting for idle.
	303	* We will re-enable it at the start of the next xfer,
	304	* till then let it sleep.
7f58aabc	305	*/
caae745a BL	306	if (wait_for((I915_READ(GMBUS2 + reg_offset) & GMBUS_ACTIVE) == 0, 10))
caae745a BL	307	DRM_INFO("GMBUS timed out waiting for idle\n");
7f58aabc	308	I915_WRITE(GMBUS0 + reg_offset, 0);
8a8ed1f5 YS	309	ret = i;
8a8ed1f5 YS	310	goto out;
f899fc64 CW	311
f899fc64 CW	312	timeout:
e957d772 CW	313	DRM_INFO("GMBUS timed out, falling back to bit banging on pin %d [%s]\n",
e957d772 CW	314	bus->reg0 & 0xff, bus->adapter.name);
7f58aabc CW	315	I915_WRITE(GMBUS0 + reg_offset, 0);
7f58aabc CW	316
f899fc64	317	/* Hardware may not support GMBUS over these pins? Try GPIO bitbanging instead. */
f6f808c8 DV	318	if (!bus->has_gpio) {
	319	ret = -EIO;
	320	} else {
	321	bus->force_bit = true;
	322	ret = intel_i2c_quirk_xfer(bus, msgs, num);
	323	}
8a8ed1f5 YS	324	out:
	325	mutex_unlock(&dev_priv->gmbus_mutex);
	326	return ret;
f899fc64 CW	327	}
	328
	329	static u32 gmbus_func(struct i2c_adapter *adapter)
	330	{
f6f808c8 DV	331	return i2c_bit_algo.functionality(adapter) &
f6f808c8 DV	332	(I2C_FUNC_I2C \| I2C_FUNC_SMBUS_EMUL \|
f899fc64 CW	333	/* I2C_FUNC_10BIT_ADDR \| */
	334	I2C_FUNC_SMBUS_READ_BLOCK_DATA \|
	335	I2C_FUNC_SMBUS_BLOCK_PROC_CALL);
	336	}
	337
	338	static const struct i2c_algorithm gmbus_algorithm = {
	339	.master_xfer = gmbus_xfer,
	340	.functionality = gmbus_func
	341	};
	342
79e53945	343	/**
f899fc64 CW	344	* intel_gmbus_setup - instantiate all Intel i2c GMBuses
f899fc64 CW	345	* @dev: DRM device
79e53945	346	*/
f899fc64 CW	347	int intel_setup_gmbus(struct drm_device *dev)
f899fc64 CW	348	{
e957d772	349	static const char *names[GMBUS_NUM_PORTS] = {
f899fc64 CW	350	"disabled",
	351	"ssc",
	352	"vga",
	353	"panel",
	354	"dpc",
	355	"dpb",
69669455	356	"reserved",
e957d772	357	"dpd",
f899fc64 CW	358	};
	359	struct drm_i915_private *dev_priv = dev->dev_private;
	360	int ret, i;
	361
51a59ac8	362	dev_priv->gmbus = kcalloc(GMBUS_NUM_PORTS, sizeof(struct intel_gmbus),
f899fc64 CW	363	GFP_KERNEL);
	364	if (dev_priv->gmbus == NULL)
	365	return -ENOMEM;
	366
8a8ed1f5 YS	367	mutex_init(&dev_priv->gmbus_mutex);
8a8ed1f5 YS	368
f899fc64 CW	369	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
	370	struct intel_gmbus *bus = &dev_priv->gmbus[i];
	371
	372	bus->adapter.owner = THIS_MODULE;
	373	bus->adapter.class = I2C_CLASS_DDC;
	374	snprintf(bus->adapter.name,
69669455 JD	375	sizeof(bus->adapter.name),
69669455 JD	376	"i915 gmbus %s",
f899fc64 CW	377	names[i]);
	378
	379	bus->adapter.dev.parent = &dev->pdev->dev;
c2b9152f	380	bus->dev_priv = dev_priv;
f899fc64 CW	381
	382	bus->adapter.algo = &gmbus_algorithm;
	383	ret = i2c_add_adapter(&bus->adapter);
	384	if (ret)
	385	goto err;
	386
e957d772 CW	387	/* By default use a conservative clock rate */
e957d772 CW	388	bus->reg0 = i \| GMBUS_RATE_100KHZ;
cb8ea752	389
f6f808c8 DV	390	bus->has_gpio = intel_gpio_setup(bus, i);
f6f808c8 DV	391
cb8ea752	392	/* XXX force bit banging until GMBUS is fully debugged */
f6f808c8 DV	393	if (bus->has_gpio)
f6f808c8 DV	394	bus->force_bit = true;
f899fc64 CW	395	}
	396
	397	intel_i2c_reset(dev_priv->dev);
	398
	399	return 0;
	400
	401	err:
	402	while (--i) {
	403	struct intel_gmbus *bus = &dev_priv->gmbus[i];
	404	i2c_del_adapter(&bus->adapter);
	405	}
	406	kfree(dev_priv->gmbus);
	407	dev_priv->gmbus = NULL;
	408	return ret;
	409	}
	410
e957d772 CW	411	void intel_gmbus_set_speed(struct i2c_adapter *adapter, int speed)
	412	{
	413	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	414
d5090b96	415	bus->reg0 = (bus->reg0 & ~(0x3 << 8)) \| speed;
e957d772 CW	416	}
	417
	418	void intel_gmbus_force_bit(struct i2c_adapter *adapter, bool force_bit)
	419	{
	420	struct intel_gmbus *bus = to_intel_gmbus(adapter);
	421
f6f808c8 DV	422	if (bus->has_gpio)
f6f808c8 DV	423	bus->force_bit = force_bit;
e957d772 CW	424	}
e957d772 CW	425
f899fc64	426	void intel_teardown_gmbus(struct drm_device *dev)
79e53945	427	{
f899fc64 CW	428	struct drm_i915_private *dev_priv = dev->dev_private;
f899fc64 CW	429	int i;
f9c10a9b	430
f899fc64	431	if (dev_priv->gmbus == NULL)
79e53945 JB	432	return;
79e53945 JB	433
f899fc64 CW	434	for (i = 0; i < GMBUS_NUM_PORTS; i++) {
f899fc64 CW	435	struct intel_gmbus *bus = &dev_priv->gmbus[i];
f899fc64 CW	436	i2c_del_adapter(&bus->adapter);
	437	}
	438
	439	kfree(dev_priv->gmbus);
	440	dev_priv->gmbus = NULL;
79e53945	441	}