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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
e981e7b1 TD |
141 | #define RING_EXECLIST_QFULL (1 << 0x2) |
142 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
143 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
144 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
145 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
146 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
147 | ||
148 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
149 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
150 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
151 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
152 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
153 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 154 | |
70c2a24d CW |
155 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
156 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
157 | GEN8_CTX_STATUS_PREEMPTED | \ | |
158 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
159 | ||
8670d6f9 OM |
160 | #define CTX_LRI_HEADER_0 0x01 |
161 | #define CTX_CONTEXT_CONTROL 0x02 | |
162 | #define CTX_RING_HEAD 0x04 | |
163 | #define CTX_RING_TAIL 0x06 | |
164 | #define CTX_RING_BUFFER_START 0x08 | |
165 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
166 | #define CTX_BB_HEAD_U 0x0c | |
167 | #define CTX_BB_HEAD_L 0x0e | |
168 | #define CTX_BB_STATE 0x10 | |
169 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
170 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
171 | #define CTX_SECOND_BB_STATE 0x16 | |
172 | #define CTX_BB_PER_CTX_PTR 0x18 | |
173 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
174 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
175 | #define CTX_LRI_HEADER_1 0x21 | |
176 | #define CTX_CTX_TIMESTAMP 0x22 | |
177 | #define CTX_PDP3_UDW 0x24 | |
178 | #define CTX_PDP3_LDW 0x26 | |
179 | #define CTX_PDP2_UDW 0x28 | |
180 | #define CTX_PDP2_LDW 0x2a | |
181 | #define CTX_PDP1_UDW 0x2c | |
182 | #define CTX_PDP1_LDW 0x2e | |
183 | #define CTX_PDP0_UDW 0x30 | |
184 | #define CTX_PDP0_LDW 0x32 | |
185 | #define CTX_LRI_HEADER_2 0x41 | |
186 | #define CTX_R_PWR_CLK_STATE 0x42 | |
187 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
188 | ||
56e51bf0 | 189 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 190 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
191 | (reg_state)[(pos)+1] = (val); \ |
192 | } while (0) | |
193 | ||
194 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 195 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 198 | } while (0) |
e5815a2e | 199 | |
9244a817 | 200 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
201 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
202 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 203 | } while (0) |
2dba3239 | 204 | |
71562919 MT |
205 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
206 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
7bd0a2c6 | 207 | #define GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x19 |
84b790f8 | 208 | |
0e93cdd4 CW |
209 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
210 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
a3aabe86 | 211 | #define WA_TAIL_DWORDS 2 |
7e4992ac | 212 | #define WA_TAIL_BYTES (sizeof(u32) * WA_TAIL_DWORDS) |
beecec90 | 213 | #define PREEMPT_ID 0x1 |
a3aabe86 | 214 | |
e2efd130 | 215 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 216 | struct intel_engine_cs *engine); |
a3aabe86 CW |
217 | static void execlists_init_reg_state(u32 *reg_state, |
218 | struct i915_gem_context *ctx, | |
219 | struct intel_engine_cs *engine, | |
220 | struct intel_ring *ring); | |
7ba717cf | 221 | |
73e4d07f OM |
222 | /** |
223 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 224 | * @dev_priv: i915 device private |
73e4d07f OM |
225 | * @enable_execlists: value of i915.enable_execlists module parameter. |
226 | * | |
227 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 228 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
229 | * |
230 | * Return: 1 if Execlists is supported and has to be enabled. | |
231 | */ | |
c033666a | 232 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 233 | { |
a0bd6c31 ZL |
234 | /* On platforms with execlist available, vGPU will only |
235 | * support execlist mode, no ring buffer mode. | |
236 | */ | |
c033666a | 237 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
238 | return 1; |
239 | ||
c033666a | 240 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
241 | return 1; |
242 | ||
127f1003 OM |
243 | if (enable_execlists == 0) |
244 | return 0; | |
245 | ||
5a21b665 | 246 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
8279aaf5 | 247 | USES_PPGTT(dev_priv)) |
127f1003 OM |
248 | return 1; |
249 | ||
250 | return 0; | |
251 | } | |
ede7d42b | 252 | |
73e4d07f | 253 | /** |
ca82580c TU |
254 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
255 | * descriptor for a pinned context | |
ca82580c | 256 | * @ctx: Context to work on |
9021ad03 | 257 | * @engine: Engine the descriptor will be used with |
73e4d07f | 258 | * |
ca82580c TU |
259 | * The context descriptor encodes various attributes of a context, |
260 | * including its GTT address and some flags. Because it's fairly | |
261 | * expensive to calculate, we'll just do it once and cache the result, | |
262 | * which remains valid until the context is unpinned. | |
263 | * | |
6e5248b5 DV |
264 | * This is what a descriptor looks like, from LSB to MSB:: |
265 | * | |
2355cf08 | 266 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
267 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
268 | * bits 32-52: ctx ID, a globally unique tag | |
269 | * bits 53-54: mbz, reserved for use by hardware | |
270 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 271 | */ |
ca82580c | 272 | static void |
e2efd130 | 273 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 274 | struct intel_engine_cs *engine) |
84b790f8 | 275 | { |
9021ad03 | 276 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 277 | u64 desc; |
84b790f8 | 278 | |
7069b144 | 279 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 280 | |
2355cf08 | 281 | desc = ctx->desc_template; /* bits 0-11 */ |
0b29c75a | 282 | desc |= i915_ggtt_offset(ce->state) + LRC_HEADER_PAGES * PAGE_SIZE; |
9021ad03 | 283 | /* bits 12-31 */ |
7069b144 | 284 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 285 | |
9021ad03 | 286 | ce->lrc_desc = desc; |
5af05fef MT |
287 | } |
288 | ||
27606fd8 CW |
289 | static struct i915_priolist * |
290 | lookup_priolist(struct intel_engine_cs *engine, | |
291 | struct i915_priotree *pt, | |
292 | int prio) | |
08dd3e1a | 293 | { |
b620e870 | 294 | struct intel_engine_execlists * const execlists = &engine->execlists; |
08dd3e1a CW |
295 | struct i915_priolist *p; |
296 | struct rb_node **parent, *rb; | |
297 | bool first = true; | |
298 | ||
b620e870 | 299 | if (unlikely(execlists->no_priolist)) |
08dd3e1a CW |
300 | prio = I915_PRIORITY_NORMAL; |
301 | ||
302 | find_priolist: | |
303 | /* most positive priority is scheduled first, equal priorities fifo */ | |
304 | rb = NULL; | |
b620e870 | 305 | parent = &execlists->queue.rb_node; |
08dd3e1a CW |
306 | while (*parent) { |
307 | rb = *parent; | |
308 | p = rb_entry(rb, typeof(*p), node); | |
309 | if (prio > p->priority) { | |
310 | parent = &rb->rb_left; | |
311 | } else if (prio < p->priority) { | |
312 | parent = &rb->rb_right; | |
313 | first = false; | |
314 | } else { | |
27606fd8 | 315 | return p; |
08dd3e1a CW |
316 | } |
317 | } | |
318 | ||
319 | if (prio == I915_PRIORITY_NORMAL) { | |
b620e870 | 320 | p = &execlists->default_priolist; |
08dd3e1a CW |
321 | } else { |
322 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); | |
323 | /* Convert an allocation failure to a priority bump */ | |
324 | if (unlikely(!p)) { | |
325 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
326 | ||
327 | /* To maintain ordering with all rendering, after an | |
328 | * allocation failure we have to disable all scheduling. | |
329 | * Requests will then be executed in fifo, and schedule | |
330 | * will ensure that dependencies are emitted in fifo. | |
331 | * There will be still some reordering with existing | |
332 | * requests, so if userspace lied about their | |
333 | * dependencies that reordering may be visible. | |
334 | */ | |
b620e870 | 335 | execlists->no_priolist = true; |
08dd3e1a CW |
336 | goto find_priolist; |
337 | } | |
338 | } | |
339 | ||
340 | p->priority = prio; | |
27606fd8 | 341 | INIT_LIST_HEAD(&p->requests); |
08dd3e1a | 342 | rb_link_node(&p->node, rb, parent); |
b620e870 | 343 | rb_insert_color(&p->node, &execlists->queue); |
08dd3e1a | 344 | |
08dd3e1a | 345 | if (first) |
b620e870 | 346 | execlists->first = &p->node; |
08dd3e1a | 347 | |
27606fd8 | 348 | return ptr_pack_bits(p, first, 1); |
08dd3e1a CW |
349 | } |
350 | ||
7e4992ac CW |
351 | static void unwind_wa_tail(struct drm_i915_gem_request *rq) |
352 | { | |
353 | rq->tail = intel_ring_wrap(rq->ring, rq->wa_tail - WA_TAIL_BYTES); | |
354 | assert_ring_tail_valid(rq->ring, rq->tail); | |
355 | } | |
356 | ||
357 | static void unwind_incomplete_requests(struct intel_engine_cs *engine) | |
358 | { | |
359 | struct drm_i915_gem_request *rq, *rn; | |
097a9481 MW |
360 | struct i915_priolist *uninitialized_var(p); |
361 | int last_prio = I915_PRIORITY_INVALID; | |
7e4992ac CW |
362 | |
363 | lockdep_assert_held(&engine->timeline->lock); | |
364 | ||
365 | list_for_each_entry_safe_reverse(rq, rn, | |
366 | &engine->timeline->requests, | |
367 | link) { | |
7e4992ac CW |
368 | if (i915_gem_request_completed(rq)) |
369 | return; | |
370 | ||
371 | __i915_gem_request_unsubmit(rq); | |
372 | unwind_wa_tail(rq); | |
373 | ||
097a9481 MW |
374 | GEM_BUG_ON(rq->priotree.priority == I915_PRIORITY_INVALID); |
375 | if (rq->priotree.priority != last_prio) { | |
376 | p = lookup_priolist(engine, | |
377 | &rq->priotree, | |
378 | rq->priotree.priority); | |
379 | p = ptr_mask_bits(p, 1); | |
380 | ||
381 | last_prio = rq->priotree.priority; | |
382 | } | |
383 | ||
384 | list_add(&rq->priotree.link, &p->requests); | |
7e4992ac CW |
385 | } |
386 | } | |
387 | ||
bbd6c47e CW |
388 | static inline void |
389 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
390 | unsigned long status) | |
84b790f8 | 391 | { |
bbd6c47e CW |
392 | /* |
393 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
394 | * The compiler should eliminate this function as dead-code. | |
395 | */ | |
396 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
397 | return; | |
6daccb0b | 398 | |
3fc03069 CD |
399 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
400 | status, rq); | |
84b790f8 BW |
401 | } |
402 | ||
c6a2ac71 TU |
403 | static void |
404 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
405 | { | |
406 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
407 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
408 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
409 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
410 | } | |
411 | ||
70c2a24d | 412 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 413 | { |
70c2a24d | 414 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
415 | struct i915_hw_ppgtt *ppgtt = |
416 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 417 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 418 | |
e6ba9992 | 419 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 420 | |
c6a2ac71 TU |
421 | /* True 32b PPGTT with dynamic page allocation: update PDP |
422 | * registers and point the unallocated PDPs to scratch page. | |
423 | * PML4 is allocated during ppgtt init, so this is not needed | |
424 | * in 48-bit mode. | |
425 | */ | |
949e8ab3 | 426 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 427 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
428 | |
429 | return ce->lrc_desc; | |
ae1250b9 OM |
430 | } |
431 | ||
beecec90 CW |
432 | static inline void elsp_write(u64 desc, u32 __iomem *elsp) |
433 | { | |
434 | writel(upper_32_bits(desc), elsp); | |
435 | writel(lower_32_bits(desc), elsp); | |
436 | } | |
437 | ||
70c2a24d | 438 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 439 | { |
b620e870 | 440 | struct execlist_port *port = engine->execlists.port; |
bbd6c47e | 441 | u32 __iomem *elsp = |
77f0d0e9 CW |
442 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); |
443 | unsigned int n; | |
bbd6c47e | 444 | |
76e70087 | 445 | for (n = execlists_num_ports(&engine->execlists); n--; ) { |
77f0d0e9 CW |
446 | struct drm_i915_gem_request *rq; |
447 | unsigned int count; | |
448 | u64 desc; | |
449 | ||
450 | rq = port_unpack(&port[n], &count); | |
451 | if (rq) { | |
452 | GEM_BUG_ON(count > !n); | |
453 | if (!count++) | |
454 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
455 | port_set(&port[n], port_pack(rq, count)); | |
456 | desc = execlists_update_context(rq); | |
457 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
458 | } else { | |
459 | GEM_BUG_ON(!n); | |
460 | desc = 0; | |
461 | } | |
bbd6c47e | 462 | |
beecec90 | 463 | elsp_write(desc, elsp); |
77f0d0e9 | 464 | } |
bbd6c47e CW |
465 | } |
466 | ||
70c2a24d | 467 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 468 | { |
70c2a24d | 469 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 470 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 471 | } |
84b790f8 | 472 | |
70c2a24d CW |
473 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
474 | const struct i915_gem_context *next) | |
475 | { | |
476 | if (prev != next) | |
477 | return false; | |
26720ab9 | 478 | |
70c2a24d CW |
479 | if (ctx_single_port_submission(prev)) |
480 | return false; | |
26720ab9 | 481 | |
70c2a24d | 482 | return true; |
84b790f8 BW |
483 | } |
484 | ||
77f0d0e9 CW |
485 | static void port_assign(struct execlist_port *port, |
486 | struct drm_i915_gem_request *rq) | |
487 | { | |
488 | GEM_BUG_ON(rq == port_request(port)); | |
489 | ||
490 | if (port_isset(port)) | |
491 | i915_gem_request_put(port_request(port)); | |
492 | ||
493 | port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); | |
494 | } | |
495 | ||
beecec90 CW |
496 | static void inject_preempt_context(struct intel_engine_cs *engine) |
497 | { | |
498 | struct intel_context *ce = | |
499 | &engine->i915->preempt_context->engine[engine->id]; | |
500 | u32 __iomem *elsp = | |
501 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
502 | unsigned int n; | |
503 | ||
504 | GEM_BUG_ON(engine->i915->preempt_context->hw_id != PREEMPT_ID); | |
505 | GEM_BUG_ON(!IS_ALIGNED(ce->ring->size, WA_TAIL_BYTES)); | |
506 | ||
507 | memset(ce->ring->vaddr + ce->ring->tail, 0, WA_TAIL_BYTES); | |
508 | ce->ring->tail += WA_TAIL_BYTES; | |
509 | ce->ring->tail &= (ce->ring->size - 1); | |
510 | ce->lrc_reg_state[CTX_RING_TAIL+1] = ce->ring->tail; | |
511 | ||
512 | for (n = execlists_num_ports(&engine->execlists); --n; ) | |
513 | elsp_write(0, elsp); | |
514 | ||
515 | elsp_write(ce->lrc_desc, elsp); | |
516 | } | |
517 | ||
518 | static bool can_preempt(struct intel_engine_cs *engine) | |
519 | { | |
520 | return INTEL_INFO(engine->i915)->has_logical_ring_preemption; | |
521 | } | |
522 | ||
70c2a24d | 523 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 524 | { |
7a62cc61 MK |
525 | struct intel_engine_execlists * const execlists = &engine->execlists; |
526 | struct execlist_port *port = execlists->port; | |
76e70087 MK |
527 | const struct execlist_port * const last_port = |
528 | &execlists->port[execlists->port_mask]; | |
beecec90 | 529 | struct drm_i915_gem_request *last = port_request(port); |
20311bd3 | 530 | struct rb_node *rb; |
70c2a24d CW |
531 | bool submit = false; |
532 | ||
70c2a24d CW |
533 | /* Hardware submission is through 2 ports. Conceptually each port |
534 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
535 | * static for a context, and unique to each, so we only execute | |
536 | * requests belonging to a single context from each ring. RING_HEAD | |
537 | * is maintained by the CS in the context image, it marks the place | |
538 | * where it got up to last time, and through RING_TAIL we tell the CS | |
539 | * where we want to execute up to this time. | |
540 | * | |
541 | * In this list the requests are in order of execution. Consecutive | |
542 | * requests from the same context are adjacent in the ringbuffer. We | |
543 | * can combine these requests into a single RING_TAIL update: | |
544 | * | |
545 | * RING_HEAD...req1...req2 | |
546 | * ^- RING_TAIL | |
547 | * since to execute req2 the CS must first execute req1. | |
548 | * | |
549 | * Our goal then is to point each port to the end of a consecutive | |
550 | * sequence of requests as being the most optimal (fewest wake ups | |
551 | * and context switches) submission. | |
779949f4 | 552 | */ |
acdd884a | 553 | |
9f7886d0 | 554 | spin_lock_irq(&engine->timeline->lock); |
7a62cc61 MK |
555 | rb = execlists->first; |
556 | GEM_BUG_ON(rb_first(&execlists->queue) != rb); | |
beecec90 CW |
557 | if (!rb) |
558 | goto unlock; | |
559 | ||
560 | if (last) { | |
561 | /* | |
562 | * Don't resubmit or switch until all outstanding | |
563 | * preemptions (lite-restore) are seen. Then we | |
564 | * know the next preemption status we see corresponds | |
565 | * to this ELSP update. | |
566 | */ | |
567 | if (port_count(&port[0]) > 1) | |
568 | goto unlock; | |
569 | ||
570 | if (can_preempt(engine) && | |
571 | rb_entry(rb, struct i915_priolist, node)->priority > | |
572 | max(last->priotree.priority, 0)) { | |
573 | /* | |
574 | * Switch to our empty preempt context so | |
575 | * the state of the GPU is known (idle). | |
576 | */ | |
577 | inject_preempt_context(engine); | |
578 | execlists->preempt = true; | |
579 | goto unlock; | |
580 | } else { | |
581 | /* | |
582 | * In theory, we could coalesce more requests onto | |
583 | * the second port (the first port is active, with | |
584 | * no preemptions pending). However, that means we | |
585 | * then have to deal with the possible lite-restore | |
586 | * of the second port (as we submit the ELSP, there | |
587 | * may be a context-switch) but also we may complete | |
588 | * the resubmission before the context-switch. Ergo, | |
589 | * coalescing onto the second port will cause a | |
590 | * preemption event, but we cannot predict whether | |
591 | * that will affect port[0] or port[1]. | |
592 | * | |
593 | * If the second port is already active, we can wait | |
594 | * until the next context-switch before contemplating | |
595 | * new requests. The GPU will be busy and we should be | |
596 | * able to resubmit the new ELSP before it idles, | |
597 | * avoiding pipeline bubbles (momentary pauses where | |
598 | * the driver is unable to keep up the supply of new | |
599 | * work). | |
600 | */ | |
601 | if (port_count(&port[1])) | |
602 | goto unlock; | |
603 | ||
604 | /* WaIdleLiteRestore:bdw,skl | |
605 | * Apply the wa NOOPs to prevent | |
606 | * ring:HEAD == req:TAIL as we resubmit the | |
607 | * request. See gen8_emit_breadcrumb() for | |
608 | * where we prepare the padding after the | |
609 | * end of the request. | |
610 | */ | |
611 | last->tail = last->wa_tail; | |
612 | } | |
613 | } | |
614 | ||
615 | do { | |
6c067579 CW |
616 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); |
617 | struct drm_i915_gem_request *rq, *rn; | |
618 | ||
619 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
620 | /* | |
621 | * Can we combine this request with the current port? | |
622 | * It has to be the same context/ringbuffer and not | |
623 | * have any exceptions (e.g. GVT saying never to | |
624 | * combine contexts). | |
625 | * | |
626 | * If we can combine the requests, we can execute both | |
627 | * by updating the RING_TAIL to point to the end of the | |
628 | * second request, and so we never need to tell the | |
629 | * hardware about the first. | |
70c2a24d | 630 | */ |
6c067579 CW |
631 | if (last && !can_merge_ctx(rq->ctx, last->ctx)) { |
632 | /* | |
633 | * If we are on the second port and cannot | |
634 | * combine this request with the last, then we | |
635 | * are done. | |
636 | */ | |
76e70087 | 637 | if (port == last_port) { |
6c067579 CW |
638 | __list_del_many(&p->requests, |
639 | &rq->priotree.link); | |
640 | goto done; | |
641 | } | |
642 | ||
643 | /* | |
644 | * If GVT overrides us we only ever submit | |
645 | * port[0], leaving port[1] empty. Note that we | |
646 | * also have to be careful that we don't queue | |
647 | * the same context (even though a different | |
648 | * request) to the second port. | |
649 | */ | |
650 | if (ctx_single_port_submission(last->ctx) || | |
651 | ctx_single_port_submission(rq->ctx)) { | |
652 | __list_del_many(&p->requests, | |
653 | &rq->priotree.link); | |
654 | goto done; | |
655 | } | |
656 | ||
657 | GEM_BUG_ON(last->ctx == rq->ctx); | |
658 | ||
659 | if (submit) | |
660 | port_assign(port, last); | |
661 | port++; | |
7a62cc61 MK |
662 | |
663 | GEM_BUG_ON(port_isset(port)); | |
6c067579 | 664 | } |
70c2a24d | 665 | |
6c067579 | 666 | INIT_LIST_HEAD(&rq->priotree.link); |
6c067579 | 667 | __i915_gem_request_submit(rq); |
7a62cc61 | 668 | trace_i915_gem_request_in(rq, port_index(port, execlists)); |
6c067579 CW |
669 | last = rq; |
670 | submit = true; | |
70c2a24d | 671 | } |
d55ac5bf | 672 | |
20311bd3 | 673 | rb = rb_next(rb); |
7a62cc61 | 674 | rb_erase(&p->node, &execlists->queue); |
6c067579 CW |
675 | INIT_LIST_HEAD(&p->requests); |
676 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 677 | kmem_cache_free(engine->i915->priorities, p); |
beecec90 | 678 | } while (rb); |
6c067579 | 679 | done: |
7a62cc61 | 680 | execlists->first = rb; |
6c067579 | 681 | if (submit) |
77f0d0e9 | 682 | port_assign(port, last); |
beecec90 | 683 | unlock: |
9f7886d0 | 684 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 685 | |
70c2a24d CW |
686 | if (submit) |
687 | execlists_submit_ports(engine); | |
acdd884a MT |
688 | } |
689 | ||
3f9e6cd8 CW |
690 | static void |
691 | execlist_cancel_port_requests(struct intel_engine_execlists *execlists) | |
cf4591d1 | 692 | { |
3f9e6cd8 | 693 | struct execlist_port *port = execlists->port; |
dc2279e1 | 694 | unsigned int num_ports = execlists_num_ports(execlists); |
cf4591d1 | 695 | |
3f9e6cd8 | 696 | while (num_ports-- && port_isset(port)) { |
7e44fc28 CW |
697 | struct drm_i915_gem_request *rq = port_request(port); |
698 | ||
d6c05113 | 699 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_PREEMPTED); |
7e44fc28 CW |
700 | i915_gem_request_put(rq); |
701 | ||
3f9e6cd8 CW |
702 | memset(port, 0, sizeof(*port)); |
703 | port++; | |
704 | } | |
cf4591d1 MK |
705 | } |
706 | ||
27a5f61b CW |
707 | static void execlists_cancel_requests(struct intel_engine_cs *engine) |
708 | { | |
b620e870 | 709 | struct intel_engine_execlists * const execlists = &engine->execlists; |
27a5f61b CW |
710 | struct drm_i915_gem_request *rq, *rn; |
711 | struct rb_node *rb; | |
712 | unsigned long flags; | |
27a5f61b CW |
713 | |
714 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
715 | ||
716 | /* Cancel the requests on the HW and clear the ELSP tracker. */ | |
cf4591d1 | 717 | execlist_cancel_port_requests(execlists); |
27a5f61b CW |
718 | |
719 | /* Mark all executing requests as skipped. */ | |
720 | list_for_each_entry(rq, &engine->timeline->requests, link) { | |
721 | GEM_BUG_ON(!rq->global_seqno); | |
722 | if (!i915_gem_request_completed(rq)) | |
723 | dma_fence_set_error(&rq->fence, -EIO); | |
724 | } | |
725 | ||
726 | /* Flush the queued requests to the timeline list (for retiring). */ | |
b620e870 | 727 | rb = execlists->first; |
27a5f61b CW |
728 | while (rb) { |
729 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); | |
730 | ||
731 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
732 | INIT_LIST_HEAD(&rq->priotree.link); | |
733 | rq->priotree.priority = INT_MAX; | |
734 | ||
735 | dma_fence_set_error(&rq->fence, -EIO); | |
736 | __i915_gem_request_submit(rq); | |
737 | } | |
738 | ||
739 | rb = rb_next(rb); | |
b620e870 | 740 | rb_erase(&p->node, &execlists->queue); |
27a5f61b CW |
741 | INIT_LIST_HEAD(&p->requests); |
742 | if (p->priority != I915_PRIORITY_NORMAL) | |
743 | kmem_cache_free(engine->i915->priorities, p); | |
744 | } | |
745 | ||
746 | /* Remaining _unready_ requests will be nop'ed when submitted */ | |
747 | ||
cf4591d1 | 748 | |
b620e870 MK |
749 | execlists->queue = RB_ROOT; |
750 | execlists->first = NULL; | |
3f9e6cd8 | 751 | GEM_BUG_ON(port_isset(execlists->port)); |
27a5f61b CW |
752 | |
753 | /* | |
754 | * The port is checked prior to scheduling a tasklet, but | |
755 | * just in case we have suspended the tasklet to do the | |
756 | * wedging make sure that when it wakes, it decides there | |
757 | * is no work to do by clearing the irq_posted bit. | |
758 | */ | |
759 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
760 | ||
761 | spin_unlock_irqrestore(&engine->timeline->lock, flags); | |
762 | } | |
763 | ||
6e5248b5 | 764 | /* |
73e4d07f OM |
765 | * Check the unread Context Status Buffers and manage the submission of new |
766 | * contexts to the ELSP accordingly. | |
767 | */ | |
27af5eea | 768 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 769 | { |
b620e870 MK |
770 | struct intel_engine_cs * const engine = (struct intel_engine_cs *)data; |
771 | struct intel_engine_execlists * const execlists = &engine->execlists; | |
beecec90 | 772 | struct execlist_port * const port = execlists->port; |
c033666a | 773 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 774 | |
48921260 CW |
775 | /* We can skip acquiring intel_runtime_pm_get() here as it was taken |
776 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
777 | * not be relinquished until the device is idle (see | |
778 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
779 | * that all ELSP are drained i.e. we have processed the CSB, | |
780 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
781 | */ | |
782 | GEM_BUG_ON(!dev_priv->gt.awake); | |
783 | ||
b620e870 | 784 | intel_uncore_forcewake_get(dev_priv, execlists->fw_domains); |
c6a2ac71 | 785 | |
899f6204 CW |
786 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
787 | * imposing the cost of a locked atomic transaction when submitting a | |
788 | * new request (outside of the context-switch interrupt). | |
789 | */ | |
790 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
6d2cb5aa CW |
791 | /* The HWSP contains a (cacheable) mirror of the CSB */ |
792 | const u32 *buf = | |
793 | &engine->status_page.page_addr[I915_HWS_CSB_BUF0_INDEX]; | |
4af0d727 | 794 | unsigned int head, tail; |
70c2a24d | 795 | |
6d2cb5aa | 796 | /* However GVT emulation depends upon intercepting CSB mmio */ |
b620e870 | 797 | if (unlikely(execlists->csb_use_mmio)) { |
6d2cb5aa CW |
798 | buf = (u32 * __force) |
799 | (dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0))); | |
b620e870 | 800 | execlists->csb_head = -1; /* force mmio read of CSB ptrs */ |
6d2cb5aa CW |
801 | } |
802 | ||
2e70b8c6 CW |
803 | /* The write will be ordered by the uncached read (itself |
804 | * a memory barrier), so we do not need another in the form | |
805 | * of a locked instruction. The race between the interrupt | |
806 | * handler and the split test/clear is harmless as we order | |
807 | * our clear before the CSB read. If the interrupt arrived | |
808 | * first between the test and the clear, we read the updated | |
809 | * CSB and clear the bit. If the interrupt arrives as we read | |
810 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
811 | * is set and we do a new loop. | |
812 | */ | |
813 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
b620e870 | 814 | if (unlikely(execlists->csb_head == -1)) { /* following a reset */ |
767a983a CW |
815 | head = readl(dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); |
816 | tail = GEN8_CSB_WRITE_PTR(head); | |
817 | head = GEN8_CSB_READ_PTR(head); | |
b620e870 | 818 | execlists->csb_head = head; |
767a983a CW |
819 | } else { |
820 | const int write_idx = | |
821 | intel_hws_csb_write_index(dev_priv) - | |
822 | I915_HWS_CSB_BUF0_INDEX; | |
823 | ||
b620e870 | 824 | head = execlists->csb_head; |
767a983a CW |
825 | tail = READ_ONCE(buf[write_idx]); |
826 | } | |
b620e870 | 827 | |
4af0d727 | 828 | while (head != tail) { |
77f0d0e9 | 829 | struct drm_i915_gem_request *rq; |
4af0d727 | 830 | unsigned int status; |
77f0d0e9 | 831 | unsigned int count; |
4af0d727 CW |
832 | |
833 | if (++head == GEN8_CSB_ENTRIES) | |
834 | head = 0; | |
70c2a24d | 835 | |
2ffe80aa CW |
836 | /* We are flying near dragons again. |
837 | * | |
838 | * We hold a reference to the request in execlist_port[] | |
839 | * but no more than that. We are operating in softirq | |
840 | * context and so cannot hold any mutex or sleep. That | |
841 | * prevents us stopping the requests we are processing | |
842 | * in port[] from being retired simultaneously (the | |
843 | * breadcrumb will be complete before we see the | |
844 | * context-switch). As we only hold the reference to the | |
845 | * request, any pointer chasing underneath the request | |
846 | * is subject to a potential use-after-free. Thus we | |
847 | * store all of the bookkeeping within port[] as | |
848 | * required, and avoid using unguarded pointers beneath | |
849 | * request itself. The same applies to the atomic | |
850 | * status notifier. | |
851 | */ | |
852 | ||
6d2cb5aa | 853 | status = READ_ONCE(buf[2 * head]); /* maybe mmio! */ |
70c2a24d CW |
854 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
855 | continue; | |
856 | ||
beecec90 CW |
857 | if (status & GEN8_CTX_STATUS_ACTIVE_IDLE && |
858 | buf[2*head + 1] == PREEMPT_ID) { | |
859 | execlist_cancel_port_requests(execlists); | |
860 | ||
861 | spin_lock_irq(&engine->timeline->lock); | |
862 | unwind_incomplete_requests(engine); | |
863 | spin_unlock_irq(&engine->timeline->lock); | |
864 | ||
865 | GEM_BUG_ON(!execlists->preempt); | |
866 | execlists->preempt = false; | |
867 | continue; | |
868 | } | |
869 | ||
870 | if (status & GEN8_CTX_STATUS_PREEMPTED && | |
871 | execlists->preempt) | |
872 | continue; | |
873 | ||
86aa7e76 | 874 | /* Check the context/desc id for this event matches */ |
6d2cb5aa | 875 | GEM_DEBUG_BUG_ON(buf[2 * head + 1] != port->context_id); |
86aa7e76 | 876 | |
77f0d0e9 CW |
877 | rq = port_unpack(port, &count); |
878 | GEM_BUG_ON(count == 0); | |
879 | if (--count == 0) { | |
70c2a24d | 880 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
77f0d0e9 CW |
881 | GEM_BUG_ON(!i915_gem_request_completed(rq)); |
882 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); | |
883 | ||
884 | trace_i915_gem_request_out(rq); | |
1f181225 | 885 | rq->priotree.priority = INT_MAX; |
77f0d0e9 | 886 | i915_gem_request_put(rq); |
70c2a24d | 887 | |
7a62cc61 | 888 | execlists_port_complete(execlists, port); |
77f0d0e9 CW |
889 | } else { |
890 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 891 | } |
26720ab9 | 892 | |
77f0d0e9 CW |
893 | /* After the final element, the hw should be idle */ |
894 | GEM_BUG_ON(port_count(port) == 0 && | |
70c2a24d | 895 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); |
4af0d727 | 896 | } |
e1fee72c | 897 | |
b620e870 MK |
898 | if (head != execlists->csb_head) { |
899 | execlists->csb_head = head; | |
767a983a CW |
900 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
901 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine))); | |
902 | } | |
e981e7b1 TD |
903 | } |
904 | ||
beecec90 | 905 | if (!execlists->preempt) |
70c2a24d | 906 | execlists_dequeue(engine); |
c6a2ac71 | 907 | |
b620e870 | 908 | intel_uncore_forcewake_put(dev_priv, execlists->fw_domains); |
e981e7b1 TD |
909 | } |
910 | ||
27606fd8 CW |
911 | static void insert_request(struct intel_engine_cs *engine, |
912 | struct i915_priotree *pt, | |
913 | int prio) | |
914 | { | |
915 | struct i915_priolist *p = lookup_priolist(engine, pt, prio); | |
916 | ||
917 | list_add_tail(&pt->link, &ptr_mask_bits(p, 1)->requests); | |
beecec90 | 918 | if (ptr_unmask_bits(p, 1)) |
b620e870 | 919 | tasklet_hi_schedule(&engine->execlists.irq_tasklet); |
27606fd8 CW |
920 | } |
921 | ||
f4ea6bdd | 922 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 923 | { |
4a570db5 | 924 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 925 | unsigned long flags; |
acdd884a | 926 | |
663f71e7 CW |
927 | /* Will be called from irq-context when using foreign fences. */ |
928 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 929 | |
27606fd8 | 930 | insert_request(engine, &request->priotree, request->priotree.priority); |
acdd884a | 931 | |
b620e870 | 932 | GEM_BUG_ON(!engine->execlists.first); |
6c067579 CW |
933 | GEM_BUG_ON(list_empty(&request->priotree.link)); |
934 | ||
663f71e7 | 935 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
936 | } |
937 | ||
1f181225 CW |
938 | static struct drm_i915_gem_request *pt_to_request(struct i915_priotree *pt) |
939 | { | |
940 | return container_of(pt, struct drm_i915_gem_request, priotree); | |
941 | } | |
942 | ||
20311bd3 CW |
943 | static struct intel_engine_cs * |
944 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
945 | { | |
1f181225 | 946 | struct intel_engine_cs *engine = pt_to_request(pt)->engine; |
a79a524e CW |
947 | |
948 | GEM_BUG_ON(!locked); | |
20311bd3 | 949 | |
20311bd3 | 950 | if (engine != locked) { |
a79a524e CW |
951 | spin_unlock(&locked->timeline->lock); |
952 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
953 | } |
954 | ||
955 | return engine; | |
956 | } | |
957 | ||
958 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
959 | { | |
a79a524e | 960 | struct intel_engine_cs *engine; |
20311bd3 CW |
961 | struct i915_dependency *dep, *p; |
962 | struct i915_dependency stack; | |
963 | LIST_HEAD(dfs); | |
964 | ||
7d1ea609 CW |
965 | GEM_BUG_ON(prio == I915_PRIORITY_INVALID); |
966 | ||
20311bd3 CW |
967 | if (prio <= READ_ONCE(request->priotree.priority)) |
968 | return; | |
969 | ||
70cd1476 CW |
970 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
971 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
972 | |
973 | stack.signaler = &request->priotree; | |
974 | list_add(&stack.dfs_link, &dfs); | |
975 | ||
976 | /* Recursively bump all dependent priorities to match the new request. | |
977 | * | |
978 | * A naive approach would be to use recursion: | |
979 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
980 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
981 | * update_priorities(dep->signal, prio) | |
982 | * insert_request(pt); | |
983 | * } | |
984 | * but that may have unlimited recursion depth and so runs a very | |
985 | * real risk of overunning the kernel stack. Instead, we build | |
986 | * a flat list of all dependencies starting with the current request. | |
987 | * As we walk the list of dependencies, we add all of its dependencies | |
988 | * to the end of the list (this may include an already visited | |
989 | * request) and continue to walk onwards onto the new dependencies. The | |
990 | * end result is a topological list of requests in reverse order, the | |
991 | * last element in the list is the request we must execute first. | |
992 | */ | |
993 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
994 | struct i915_priotree *pt = dep->signaler; | |
995 | ||
a79a524e CW |
996 | /* Within an engine, there can be no cycle, but we may |
997 | * refer to the same dependency chain multiple times | |
998 | * (redundant dependencies are not eliminated) and across | |
999 | * engines. | |
1000 | */ | |
1001 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
1f181225 CW |
1002 | if (i915_gem_request_completed(pt_to_request(p->signaler))) |
1003 | continue; | |
1004 | ||
a79a524e | 1005 | GEM_BUG_ON(p->signaler->priority < pt->priority); |
20311bd3 CW |
1006 | if (prio > READ_ONCE(p->signaler->priority)) |
1007 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 1008 | } |
20311bd3 | 1009 | |
0798cff4 | 1010 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
1011 | } |
1012 | ||
349bdb68 CW |
1013 | /* If we didn't need to bump any existing priorities, and we haven't |
1014 | * yet submitted this request (i.e. there is no potential race with | |
1015 | * execlists_submit_request()), we can set our own priority and skip | |
1016 | * acquiring the engine locks. | |
1017 | */ | |
7d1ea609 | 1018 | if (request->priotree.priority == I915_PRIORITY_INVALID) { |
349bdb68 CW |
1019 | GEM_BUG_ON(!list_empty(&request->priotree.link)); |
1020 | request->priotree.priority = prio; | |
1021 | if (stack.dfs_link.next == stack.dfs_link.prev) | |
1022 | return; | |
1023 | __list_del_entry(&stack.dfs_link); | |
1024 | } | |
1025 | ||
a79a524e CW |
1026 | engine = request->engine; |
1027 | spin_lock_irq(&engine->timeline->lock); | |
1028 | ||
20311bd3 CW |
1029 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
1030 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
1031 | struct i915_priotree *pt = dep->signaler; | |
1032 | ||
1033 | INIT_LIST_HEAD(&dep->dfs_link); | |
1034 | ||
1035 | engine = pt_lock_engine(pt, engine); | |
1036 | ||
1037 | if (prio <= pt->priority) | |
1038 | continue; | |
1039 | ||
20311bd3 | 1040 | pt->priority = prio; |
6c067579 CW |
1041 | if (!list_empty(&pt->link)) { |
1042 | __list_del_entry(&pt->link); | |
1043 | insert_request(engine, pt, prio); | |
a79a524e | 1044 | } |
20311bd3 CW |
1045 | } |
1046 | ||
a79a524e | 1047 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
1048 | } |
1049 | ||
266a240b CW |
1050 | static struct intel_ring * |
1051 | execlists_context_pin(struct intel_engine_cs *engine, | |
1052 | struct i915_gem_context *ctx) | |
dcb4c12a | 1053 | { |
9021ad03 | 1054 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 1055 | unsigned int flags; |
7d774cac | 1056 | void *vaddr; |
ca82580c | 1057 | int ret; |
dcb4c12a | 1058 | |
91c8a326 | 1059 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 1060 | |
266a240b CW |
1061 | if (likely(ce->pin_count++)) |
1062 | goto out; | |
a533b4ba | 1063 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 1064 | |
e8a9c58f CW |
1065 | if (!ce->state) { |
1066 | ret = execlists_context_deferred_alloc(ctx, engine); | |
1067 | if (ret) | |
1068 | goto err; | |
1069 | } | |
56f6e0a7 | 1070 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 1071 | |
72b72ae4 | 1072 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
1073 | if (ctx->ggtt_offset_bias) |
1074 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
1075 | |
1076 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 1077 | if (ret) |
24f1d3cc | 1078 | goto err; |
7ba717cf | 1079 | |
bf3783e5 | 1080 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
1081 | if (IS_ERR(vaddr)) { |
1082 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 1083 | goto unpin_vma; |
82352e90 TU |
1084 | } |
1085 | ||
d822bb18 | 1086 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 1087 | if (ret) |
7d774cac | 1088 | goto unpin_map; |
d1675198 | 1089 | |
0bc40be8 | 1090 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 1091 | |
a3aabe86 CW |
1092 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
1093 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 1094 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 1095 | |
a4f5ea64 | 1096 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 1097 | |
9a6feaf0 | 1098 | i915_gem_context_get(ctx); |
266a240b CW |
1099 | out: |
1100 | return ce->ring; | |
7ba717cf | 1101 | |
7d774cac | 1102 | unpin_map: |
bf3783e5 CW |
1103 | i915_gem_object_unpin_map(ce->state->obj); |
1104 | unpin_vma: | |
1105 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 1106 | err: |
9021ad03 | 1107 | ce->pin_count = 0; |
266a240b | 1108 | return ERR_PTR(ret); |
e84fe803 NH |
1109 | } |
1110 | ||
e8a9c58f CW |
1111 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
1112 | struct i915_gem_context *ctx) | |
e84fe803 | 1113 | { |
9021ad03 | 1114 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 1115 | |
91c8a326 | 1116 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 1117 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 1118 | |
9021ad03 | 1119 | if (--ce->pin_count) |
24f1d3cc | 1120 | return; |
e84fe803 | 1121 | |
aad29fbb | 1122 | intel_ring_unpin(ce->ring); |
dcb4c12a | 1123 | |
bf3783e5 CW |
1124 | i915_gem_object_unpin_map(ce->state->obj); |
1125 | i915_vma_unpin(ce->state); | |
321fe304 | 1126 | |
9a6feaf0 | 1127 | i915_gem_context_put(ctx); |
dcb4c12a OM |
1128 | } |
1129 | ||
f73e7399 | 1130 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
1131 | { |
1132 | struct intel_engine_cs *engine = request->engine; | |
1133 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 1134 | u32 *cs; |
ef11c01d CW |
1135 | int ret; |
1136 | ||
e8a9c58f CW |
1137 | GEM_BUG_ON(!ce->pin_count); |
1138 | ||
ef11c01d CW |
1139 | /* Flush enough space to reduce the likelihood of waiting after |
1140 | * we start building the request - in which case we will just | |
1141 | * have to repeat work. | |
1142 | */ | |
1143 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
1144 | ||
73dec95e | 1145 | cs = intel_ring_begin(request, 0); |
85e2fe67 MW |
1146 | if (IS_ERR(cs)) |
1147 | return PTR_ERR(cs); | |
ef11c01d CW |
1148 | |
1149 | if (!ce->initialised) { | |
1150 | ret = engine->init_context(request); | |
1151 | if (ret) | |
85e2fe67 | 1152 | return ret; |
ef11c01d CW |
1153 | |
1154 | ce->initialised = true; | |
1155 | } | |
1156 | ||
1157 | /* Note that after this point, we have committed to using | |
1158 | * this request as it is being used to both track the | |
1159 | * state of engine initialisation and liveness of the | |
1160 | * golden renderstate above. Think twice before you try | |
1161 | * to cancel/unwind this request now. | |
1162 | */ | |
1163 | ||
1164 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
1165 | return 0; | |
ef11c01d CW |
1166 | } |
1167 | ||
9e000847 AS |
1168 | /* |
1169 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1170 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1171 | * but there is a slight complication as this is applied in WA batch where the | |
1172 | * values are only initialized once so we cannot take register value at the | |
1173 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1174 | * constant value with bit21 set and then we restore it back with the saved value. | |
1175 | * To simplify the WA, a constant value is formed by using the default value | |
1176 | * of this register. This shouldn't be a problem because we are only modifying | |
1177 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1178 | * use additional instructions that read the actual value of the register | |
1179 | * at that time and set our bit of interest but it makes the WA complicated. | |
1180 | * | |
1181 | * This WA is also required for Gen9 so extracting as a function avoids | |
1182 | * code duplication. | |
1183 | */ | |
097d4f1c TU |
1184 | static u32 * |
1185 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 1186 | { |
097d4f1c TU |
1187 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
1188 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1189 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1190 | *batch++ = 0; | |
1191 | ||
1192 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
1193 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1194 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
1195 | ||
9f235dfa TU |
1196 | batch = gen8_emit_pipe_control(batch, |
1197 | PIPE_CONTROL_CS_STALL | | |
1198 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1199 | 0); | |
097d4f1c TU |
1200 | |
1201 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
1202 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
1203 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
1204 | *batch++ = 0; | |
1205 | ||
1206 | return batch; | |
17ee950d AS |
1207 | } |
1208 | ||
6e5248b5 DV |
1209 | /* |
1210 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1211 | * initialized at the beginning and shared across all contexts but this field | |
1212 | * helps us to have multiple batches at different offsets and select them based | |
1213 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1214 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 1215 | * |
6e5248b5 DV |
1216 | * The number of WA applied are not known at the beginning; we use this field |
1217 | * to return the no of DWORDS written. | |
17ee950d | 1218 | * |
6e5248b5 DV |
1219 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1220 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1221 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1222 | * makes a complete batch buffer. | |
17ee950d | 1223 | */ |
097d4f1c | 1224 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1225 | { |
7ad00d1a | 1226 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1227 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1228 | |
c82435bb | 1229 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1230 | if (IS_BROADWELL(engine->i915)) |
1231 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1232 | |
0160f055 AS |
1233 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1234 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1235 | batch = gen8_emit_pipe_control(batch, |
1236 | PIPE_CONTROL_FLUSH_L3 | | |
1237 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1238 | PIPE_CONTROL_CS_STALL | | |
1239 | PIPE_CONTROL_QW_WRITE, | |
1240 | i915_ggtt_offset(engine->scratch) + | |
1241 | 2 * CACHELINE_BYTES); | |
0160f055 | 1242 | |
beecec90 CW |
1243 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1244 | ||
17ee950d | 1245 | /* Pad to end of cacheline */ |
097d4f1c TU |
1246 | while ((unsigned long)batch % CACHELINE_BYTES) |
1247 | *batch++ = MI_NOOP; | |
17ee950d AS |
1248 | |
1249 | /* | |
1250 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1251 | * execution depends on the length specified in terms of cache lines | |
1252 | * in the register CTX_RCS_INDIRECT_CTX | |
1253 | */ | |
1254 | ||
097d4f1c | 1255 | return batch; |
17ee950d AS |
1256 | } |
1257 | ||
097d4f1c | 1258 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1259 | { |
beecec90 CW |
1260 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
1261 | ||
9fb5026f | 1262 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 1263 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 1264 | |
9fb5026f | 1265 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1266 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1267 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1268 | *batch++ = _MASKED_BIT_DISABLE( | |
1269 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1270 | *batch++ = MI_NOOP; | |
873e8171 | 1271 | |
066d4628 MK |
1272 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1273 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1274 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1275 | batch = gen8_emit_pipe_control(batch, |
1276 | PIPE_CONTROL_FLUSH_L3 | | |
1277 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1278 | PIPE_CONTROL_CS_STALL | | |
1279 | PIPE_CONTROL_QW_WRITE, | |
1280 | i915_ggtt_offset(engine->scratch) | |
1281 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1282 | } |
3485d99e | 1283 | |
9fb5026f | 1284 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1285 | if (HAS_POOLED_EU(engine->i915)) { |
1286 | /* | |
1287 | * EU pool configuration is setup along with golden context | |
1288 | * during context initialization. This value depends on | |
1289 | * device type (2x6 or 3x6) and needs to be updated based | |
1290 | * on which subslice is disabled especially for 2x6 | |
1291 | * devices, however it is safe to load default | |
1292 | * configuration of 3x6 device instead of masking off | |
1293 | * corresponding bits because HW ignores bits of a disabled | |
1294 | * subslice and drops down to appropriate config. Please | |
1295 | * see render_state_setup() in i915_gem_render_state.c for | |
1296 | * possible configurations, to avoid duplication they are | |
1297 | * not shown here again. | |
1298 | */ | |
097d4f1c TU |
1299 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1300 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1301 | *batch++ = 0x00777000; | |
1302 | *batch++ = 0; | |
1303 | *batch++ = 0; | |
1304 | *batch++ = 0; | |
3485d99e TG |
1305 | } |
1306 | ||
beecec90 CW |
1307 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1308 | ||
0504cffc | 1309 | /* Pad to end of cacheline */ |
097d4f1c TU |
1310 | while ((unsigned long)batch % CACHELINE_BYTES) |
1311 | *batch++ = MI_NOOP; | |
0504cffc | 1312 | |
097d4f1c | 1313 | return batch; |
0504cffc AS |
1314 | } |
1315 | ||
097d4f1c TU |
1316 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1317 | ||
1318 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1319 | { |
48bb74e4 CW |
1320 | struct drm_i915_gem_object *obj; |
1321 | struct i915_vma *vma; | |
1322 | int err; | |
17ee950d | 1323 | |
097d4f1c | 1324 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1325 | if (IS_ERR(obj)) |
1326 | return PTR_ERR(obj); | |
17ee950d | 1327 | |
a01cb37a | 1328 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1329 | if (IS_ERR(vma)) { |
1330 | err = PTR_ERR(vma); | |
1331 | goto err; | |
17ee950d AS |
1332 | } |
1333 | ||
48bb74e4 CW |
1334 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1335 | if (err) | |
1336 | goto err; | |
1337 | ||
1338 | engine->wa_ctx.vma = vma; | |
17ee950d | 1339 | return 0; |
48bb74e4 CW |
1340 | |
1341 | err: | |
1342 | i915_gem_object_put(obj); | |
1343 | return err; | |
17ee950d AS |
1344 | } |
1345 | ||
097d4f1c | 1346 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1347 | { |
19880c4a | 1348 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1349 | } |
1350 | ||
097d4f1c TU |
1351 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1352 | ||
0bc40be8 | 1353 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1354 | { |
48bb74e4 | 1355 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1356 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1357 | &wa_ctx->per_ctx }; | |
1358 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1359 | struct page *page; |
097d4f1c TU |
1360 | void *batch, *batch_ptr; |
1361 | unsigned int i; | |
48bb74e4 | 1362 | int ret; |
17ee950d | 1363 | |
097d4f1c TU |
1364 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1365 | return -EINVAL; | |
17ee950d | 1366 | |
097d4f1c | 1367 | switch (INTEL_GEN(engine->i915)) { |
90007bca RV |
1368 | case 10: |
1369 | return 0; | |
097d4f1c TU |
1370 | case 9: |
1371 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
b8aa2233 | 1372 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1373 | break; |
1374 | case 8: | |
1375 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
3ad7b52d | 1376 | wa_bb_fn[1] = NULL; |
097d4f1c TU |
1377 | break; |
1378 | default: | |
1379 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1380 | return 0; |
0504cffc | 1381 | } |
5e60d790 | 1382 | |
097d4f1c | 1383 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1384 | if (ret) { |
1385 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1386 | return ret; | |
1387 | } | |
1388 | ||
48bb74e4 | 1389 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1390 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1391 | |
097d4f1c TU |
1392 | /* |
1393 | * Emit the two workaround batch buffers, recording the offset from the | |
1394 | * start of the workaround batch buffer object for each and their | |
1395 | * respective sizes. | |
1396 | */ | |
1397 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1398 | wa_bb[i]->offset = batch_ptr - batch; | |
1399 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1400 | ret = -EINVAL; | |
1401 | break; | |
1402 | } | |
604a8f6f CW |
1403 | if (wa_bb_fn[i]) |
1404 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
097d4f1c | 1405 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); |
17ee950d AS |
1406 | } |
1407 | ||
097d4f1c TU |
1408 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1409 | ||
17ee950d AS |
1410 | kunmap_atomic(batch); |
1411 | if (ret) | |
097d4f1c | 1412 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1413 | |
1414 | return ret; | |
1415 | } | |
1416 | ||
64f09f00 CW |
1417 | static u8 gtiir[] = { |
1418 | [RCS] = 0, | |
1419 | [BCS] = 0, | |
1420 | [VCS] = 1, | |
1421 | [VCS2] = 1, | |
1422 | [VECS] = 3, | |
1423 | }; | |
1424 | ||
0bc40be8 | 1425 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1426 | { |
c033666a | 1427 | struct drm_i915_private *dev_priv = engine->i915; |
b620e870 | 1428 | struct intel_engine_execlists * const execlists = &engine->execlists; |
821ed7df CW |
1429 | int ret; |
1430 | ||
1431 | ret = intel_mocs_init_engine(engine); | |
1432 | if (ret) | |
1433 | return ret; | |
9b1136d5 | 1434 | |
ad07dfcd | 1435 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1436 | intel_engine_init_hangcheck(engine); |
821ed7df | 1437 | |
0bc40be8 | 1438 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1439 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1440 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1441 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1442 | engine->status_page.ggtt_offset); | |
1443 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1444 | |
0bc40be8 | 1445 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1446 | |
64f09f00 CW |
1447 | GEM_BUG_ON(engine->id >= ARRAY_SIZE(gtiir)); |
1448 | ||
1449 | /* | |
1450 | * Clear any pending interrupt state. | |
1451 | * | |
1452 | * We do it twice out of paranoia that some of the IIR are double | |
1453 | * buffered, and if we only reset it once there may still be | |
1454 | * an interrupt pending. | |
1455 | */ | |
1456 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1457 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
1458 | I915_WRITE(GEN8_GT_IIR(gtiir[engine->id]), | |
1459 | GT_CONTEXT_SWITCH_INTERRUPT << engine->irq_shift); | |
f747026c | 1460 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
b620e870 | 1461 | execlists->csb_head = -1; |
beecec90 | 1462 | execlists->preempt = false; |
6b764a59 | 1463 | |
64f09f00 | 1464 | /* After a GPU reset, we may have requests to replay */ |
b620e870 MK |
1465 | if (!i915_modparams.enable_guc_submission && execlists->first) |
1466 | tasklet_schedule(&execlists->irq_tasklet); | |
6b764a59 | 1467 | |
821ed7df | 1468 | return 0; |
9b1136d5 OM |
1469 | } |
1470 | ||
0bc40be8 | 1471 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1472 | { |
c033666a | 1473 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1474 | int ret; |
1475 | ||
0bc40be8 | 1476 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1477 | if (ret) |
1478 | return ret; | |
1479 | ||
1480 | /* We need to disable the AsyncFlip performance optimisations in order | |
1481 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1482 | * programmed to '1' on all products. | |
1483 | * | |
1484 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1485 | */ | |
1486 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1487 | ||
9b1136d5 OM |
1488 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1489 | ||
0bc40be8 | 1490 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1491 | } |
1492 | ||
0bc40be8 | 1493 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1494 | { |
1495 | int ret; | |
1496 | ||
0bc40be8 | 1497 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1498 | if (ret) |
1499 | return ret; | |
1500 | ||
0bc40be8 | 1501 | return init_workarounds_ring(engine); |
82ef822e DL |
1502 | } |
1503 | ||
821ed7df CW |
1504 | static void reset_common_ring(struct intel_engine_cs *engine, |
1505 | struct drm_i915_gem_request *request) | |
1506 | { | |
b620e870 | 1507 | struct intel_engine_execlists * const execlists = &engine->execlists; |
c0dcb203 | 1508 | struct intel_context *ce; |
221ab971 | 1509 | unsigned long flags; |
cdb6ded4 | 1510 | |
221ab971 CW |
1511 | spin_lock_irqsave(&engine->timeline->lock, flags); |
1512 | ||
cdb6ded4 CW |
1513 | /* |
1514 | * Catch up with any missed context-switch interrupts. | |
1515 | * | |
1516 | * Ideally we would just read the remaining CSB entries now that we | |
1517 | * know the gpu is idle. However, the CSB registers are sometimes^W | |
1518 | * often trashed across a GPU reset! Instead we have to rely on | |
1519 | * guessing the missed context-switch events by looking at what | |
1520 | * requests were completed. | |
1521 | */ | |
cf4591d1 | 1522 | execlist_cancel_port_requests(execlists); |
cdb6ded4 | 1523 | |
221ab971 | 1524 | /* Push back any incomplete requests for replay after the reset. */ |
7e4992ac | 1525 | unwind_incomplete_requests(engine); |
cdb6ded4 | 1526 | |
221ab971 | 1527 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
c0dcb203 CW |
1528 | |
1529 | /* If the request was innocent, we leave the request in the ELSP | |
1530 | * and will try to replay it on restarting. The context image may | |
1531 | * have been corrupted by the reset, in which case we may have | |
1532 | * to service a new GPU hang, but more likely we can continue on | |
1533 | * without impact. | |
1534 | * | |
1535 | * If the request was guilty, we presume the context is corrupt | |
1536 | * and have to at least restore the RING register in the context | |
1537 | * image back to the expected values to skip over the guilty request. | |
1538 | */ | |
221ab971 | 1539 | if (!request || request->fence.error != -EIO) |
c0dcb203 | 1540 | return; |
821ed7df | 1541 | |
a3aabe86 CW |
1542 | /* We want a simple context + ring to execute the breadcrumb update. |
1543 | * We cannot rely on the context being intact across the GPU hang, | |
1544 | * so clear it and rebuild just what we need for the breadcrumb. | |
1545 | * All pending requests for this context will be zapped, and any | |
1546 | * future request will be after userspace has had the opportunity | |
1547 | * to recreate its own state. | |
1548 | */ | |
c0dcb203 | 1549 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1550 | execlists_init_reg_state(ce->lrc_reg_state, |
1551 | request->ctx, engine, ce->ring); | |
1552 | ||
821ed7df | 1553 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1554 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1555 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1556 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1557 | |
821ed7df | 1558 | request->ring->head = request->postfix; |
821ed7df CW |
1559 | intel_ring_update_space(request->ring); |
1560 | ||
a3aabe86 | 1561 | /* Reset WaIdleLiteRestore:bdw,skl as well */ |
7e4992ac | 1562 | unwind_wa_tail(request); |
821ed7df CW |
1563 | } |
1564 | ||
7a01a0a2 MT |
1565 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1566 | { | |
1567 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1568 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1569 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1570 | u32 *cs; |
1571 | int i; | |
7a01a0a2 | 1572 | |
73dec95e TU |
1573 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1574 | if (IS_ERR(cs)) | |
1575 | return PTR_ERR(cs); | |
7a01a0a2 | 1576 | |
73dec95e | 1577 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1578 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1579 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1580 | ||
73dec95e TU |
1581 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1582 | *cs++ = upper_32_bits(pd_daddr); | |
1583 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1584 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1585 | } |
1586 | ||
73dec95e TU |
1587 | *cs++ = MI_NOOP; |
1588 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1589 | |
1590 | return 0; | |
1591 | } | |
1592 | ||
be795fc1 | 1593 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1594 | u64 offset, u32 len, |
54af56db | 1595 | const unsigned int flags) |
15648585 | 1596 | { |
73dec95e | 1597 | u32 *cs; |
15648585 OM |
1598 | int ret; |
1599 | ||
7a01a0a2 MT |
1600 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1601 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1602 | * but we can't. Force Restore would be a second option, but | |
1603 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1604 | * not idle). PML4 is allocated during ppgtt init so this is |
1605 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1606 | if (req->ctx->ppgtt && |
54af56db MK |
1607 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1608 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1609 | !intel_vgpu_active(req->i915)) { | |
1610 | ret = intel_logical_ring_emit_pdps(req); | |
1611 | if (ret) | |
1612 | return ret; | |
7a01a0a2 | 1613 | |
666796da | 1614 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1615 | } |
1616 | ||
73dec95e TU |
1617 | cs = intel_ring_begin(req, 4); |
1618 | if (IS_ERR(cs)) | |
1619 | return PTR_ERR(cs); | |
15648585 | 1620 | |
279f5a00 CW |
1621 | /* |
1622 | * WaDisableCtxRestoreArbitration:bdw,chv | |
1623 | * | |
1624 | * We don't need to perform MI_ARB_ENABLE as often as we do (in | |
1625 | * particular all the gen that do not need the w/a at all!), if we | |
1626 | * took care to make sure that on every switch into this context | |
1627 | * (both ordinary and for preemption) that arbitrartion was enabled | |
1628 | * we would be fine. However, there doesn't seem to be a downside to | |
1629 | * being paranoid and making sure it is set before each batch and | |
1630 | * every context-switch. | |
1631 | * | |
1632 | * Note that if we fail to enable arbitration before the request | |
1633 | * is complete, then we do not see the context-switch interrupt and | |
1634 | * the engine hangs (with RING_HEAD == RING_TAIL). | |
1635 | * | |
1636 | * That satisfies both the GPGPU w/a and our heavy-handed paranoia. | |
1637 | */ | |
3ad7b52d CW |
1638 | *cs++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1639 | ||
15648585 | 1640 | /* FIXME(BDW): Address space and security selectors. */ |
54af56db MK |
1641 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1642 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1643 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1644 | *cs++ = lower_32_bits(offset); |
1645 | *cs++ = upper_32_bits(offset); | |
73dec95e | 1646 | intel_ring_advance(req, cs); |
15648585 OM |
1647 | |
1648 | return 0; | |
1649 | } | |
1650 | ||
31bb59cc | 1651 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1652 | { |
c033666a | 1653 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1654 | I915_WRITE_IMR(engine, |
1655 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1656 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1657 | } |
1658 | ||
31bb59cc | 1659 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1660 | { |
c033666a | 1661 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1662 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1663 | } |
1664 | ||
7c9cf4e3 | 1665 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1666 | { |
73dec95e | 1667 | u32 cmd, *cs; |
4712274c | 1668 | |
73dec95e TU |
1669 | cs = intel_ring_begin(request, 4); |
1670 | if (IS_ERR(cs)) | |
1671 | return PTR_ERR(cs); | |
4712274c OM |
1672 | |
1673 | cmd = MI_FLUSH_DW + 1; | |
1674 | ||
f0a1fb10 CW |
1675 | /* We always require a command barrier so that subsequent |
1676 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1677 | * wrt the contents of the write cache being flushed to memory | |
1678 | * (and thus being coherent from the CPU). | |
1679 | */ | |
1680 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1681 | ||
7c9cf4e3 | 1682 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1683 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1684 | if (request->engine->id == VCS) |
f0a1fb10 | 1685 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1686 | } |
1687 | ||
73dec95e TU |
1688 | *cs++ = cmd; |
1689 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1690 | *cs++ = 0; /* upper addr */ | |
1691 | *cs++ = 0; /* value */ | |
1692 | intel_ring_advance(request, cs); | |
4712274c OM |
1693 | |
1694 | return 0; | |
1695 | } | |
1696 | ||
7deb4d39 | 1697 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1698 | u32 mode) |
4712274c | 1699 | { |
b5321f30 | 1700 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1701 | u32 scratch_addr = |
1702 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1703 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1704 | u32 *cs, flags = 0; |
0b2d0934 | 1705 | int len; |
4712274c OM |
1706 | |
1707 | flags |= PIPE_CONTROL_CS_STALL; | |
1708 | ||
7c9cf4e3 | 1709 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1710 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1711 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1712 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1713 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1714 | } |
1715 | ||
7c9cf4e3 | 1716 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1717 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1718 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1719 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1720 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1721 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1722 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1723 | flags |= PIPE_CONTROL_QW_WRITE; | |
1724 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1725 | |
1a5a9ce7 BW |
1726 | /* |
1727 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1728 | * pipe control. | |
1729 | */ | |
c033666a | 1730 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1731 | vf_flush_wa = true; |
0b2d0934 MK |
1732 | |
1733 | /* WaForGAMHang:kbl */ | |
1734 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1735 | dc_flush_wa = true; | |
1a5a9ce7 | 1736 | } |
9647ff36 | 1737 | |
0b2d0934 MK |
1738 | len = 6; |
1739 | ||
1740 | if (vf_flush_wa) | |
1741 | len += 6; | |
1742 | ||
1743 | if (dc_flush_wa) | |
1744 | len += 12; | |
1745 | ||
73dec95e TU |
1746 | cs = intel_ring_begin(request, len); |
1747 | if (IS_ERR(cs)) | |
1748 | return PTR_ERR(cs); | |
4712274c | 1749 | |
9f235dfa TU |
1750 | if (vf_flush_wa) |
1751 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1752 | |
9f235dfa TU |
1753 | if (dc_flush_wa) |
1754 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1755 | 0); | |
0b2d0934 | 1756 | |
9f235dfa | 1757 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1758 | |
9f235dfa TU |
1759 | if (dc_flush_wa) |
1760 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1761 | |
73dec95e | 1762 | intel_ring_advance(request, cs); |
4712274c OM |
1763 | |
1764 | return 0; | |
1765 | } | |
1766 | ||
7c17d377 CW |
1767 | /* |
1768 | * Reserve space for 2 NOOPs at the end of each request to be | |
1769 | * used as a workaround for not being allowed to do lite | |
1770 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1771 | */ | |
73dec95e | 1772 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1773 | { |
beecec90 CW |
1774 | /* Ensure there's always at least one preemption point per-request. */ |
1775 | *cs++ = MI_ARB_CHECK; | |
73dec95e TU |
1776 | *cs++ = MI_NOOP; |
1777 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1778 | } |
4da46e1e | 1779 | |
73dec95e | 1780 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1781 | { |
7c17d377 CW |
1782 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1783 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1784 | |
73dec95e TU |
1785 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1786 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1787 | *cs++ = 0; | |
1788 | *cs++ = request->global_seqno; | |
1789 | *cs++ = MI_USER_INTERRUPT; | |
1790 | *cs++ = MI_NOOP; | |
1791 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1792 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1793 | |
73dec95e | 1794 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1795 | } |
98f29e8d CW |
1796 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1797 | ||
caddfe71 | 1798 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1799 | u32 *cs) |
7c17d377 | 1800 | { |
ce81a65c MW |
1801 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1802 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1803 | ||
7c17d377 CW |
1804 | /* w/a for post sync ops following a GPGPU operation we |
1805 | * need a prior CS_STALL, which is emitted by the flush | |
1806 | * following the batch. | |
1807 | */ | |
73dec95e TU |
1808 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1809 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1810 | PIPE_CONTROL_QW_WRITE; | |
1811 | *cs++ = intel_hws_seqno_address(request->engine); | |
1812 | *cs++ = 0; | |
1813 | *cs++ = request->global_seqno; | |
ce81a65c | 1814 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1815 | *cs++ = 0; |
1816 | *cs++ = MI_USER_INTERRUPT; | |
1817 | *cs++ = MI_NOOP; | |
1818 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1819 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1820 | |
73dec95e | 1821 | gen8_emit_wa_tail(request, cs); |
4da46e1e | 1822 | } |
98f29e8d CW |
1823 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1824 | ||
8753181e | 1825 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1826 | { |
1827 | int ret; | |
1828 | ||
4ac9659e | 1829 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1830 | if (ret) |
1831 | return ret; | |
1832 | ||
3bbaba0c PA |
1833 | ret = intel_rcs_context_init_mocs(req); |
1834 | /* | |
1835 | * Failing to program the MOCS is non-fatal.The system will not | |
1836 | * run at peak performance. So generate an error and carry on. | |
1837 | */ | |
1838 | if (ret) | |
1839 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1840 | ||
4e50f082 | 1841 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1842 | } |
1843 | ||
73e4d07f OM |
1844 | /** |
1845 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1846 | * @engine: Engine Command Streamer. |
73e4d07f | 1847 | */ |
0bc40be8 | 1848 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1849 | { |
6402c330 | 1850 | struct drm_i915_private *dev_priv; |
9832b9da | 1851 | |
27af5eea TU |
1852 | /* |
1853 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1854 | * so this is just for documentation. | |
1855 | */ | |
b620e870 MK |
1856 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->execlists.irq_tasklet.state))) |
1857 | tasklet_kill(&engine->execlists.irq_tasklet); | |
27af5eea | 1858 | |
c033666a | 1859 | dev_priv = engine->i915; |
6402c330 | 1860 | |
0bc40be8 | 1861 | if (engine->buffer) { |
0bc40be8 | 1862 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1863 | } |
48d82387 | 1864 | |
0bc40be8 TU |
1865 | if (engine->cleanup) |
1866 | engine->cleanup(engine); | |
48d82387 | 1867 | |
e8a9c58f | 1868 | intel_engine_cleanup_common(engine); |
17ee950d | 1869 | |
097d4f1c | 1870 | lrc_destroy_wa_ctx(engine); |
c033666a | 1871 | engine->i915 = NULL; |
3b3f1650 AG |
1872 | dev_priv->engine[engine->id] = NULL; |
1873 | kfree(engine); | |
454afebd OM |
1874 | } |
1875 | ||
ff44ad51 | 1876 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1877 | { |
ff44ad51 | 1878 | engine->submit_request = execlists_submit_request; |
27a5f61b | 1879 | engine->cancel_requests = execlists_cancel_requests; |
ff44ad51 | 1880 | engine->schedule = execlists_schedule; |
b620e870 | 1881 | engine->execlists.irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1882 | } |
1883 | ||
c9cacf93 | 1884 | static void |
e1382efb | 1885 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1886 | { |
1887 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1888 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1889 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1890 | |
1891 | engine->context_pin = execlists_context_pin; | |
1892 | engine->context_unpin = execlists_context_unpin; | |
1893 | ||
f73e7399 CW |
1894 | engine->request_alloc = execlists_request_alloc; |
1895 | ||
0bc40be8 | 1896 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1897 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1898 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1899 | |
1900 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1901 | |
31bb59cc CW |
1902 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1903 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1904 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1905 | } |
1906 | ||
d9f3af96 | 1907 | static inline void |
c2c7f240 | 1908 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1909 | { |
c2c7f240 | 1910 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1911 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1912 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1913 | } |
1914 | ||
bb45438f TU |
1915 | static void |
1916 | logical_ring_setup(struct intel_engine_cs *engine) | |
1917 | { | |
1918 | struct drm_i915_private *dev_priv = engine->i915; | |
1919 | enum forcewake_domains fw_domains; | |
1920 | ||
019bf277 TU |
1921 | intel_engine_setup_common(engine); |
1922 | ||
bb45438f TU |
1923 | /* Intentionally left blank. */ |
1924 | engine->buffer = NULL; | |
1925 | ||
1926 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1927 | RING_ELSP(engine), | |
1928 | FW_REG_WRITE); | |
1929 | ||
1930 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1931 | RING_CONTEXT_STATUS_PTR(engine), | |
1932 | FW_REG_READ | FW_REG_WRITE); | |
1933 | ||
1934 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1935 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1936 | FW_REG_READ); | |
1937 | ||
b620e870 | 1938 | engine->execlists.fw_domains = fw_domains; |
bb45438f | 1939 | |
b620e870 | 1940 | tasklet_init(&engine->execlists.irq_tasklet, |
bb45438f TU |
1941 | intel_lrc_irq_handler, (unsigned long)engine); |
1942 | ||
bb45438f TU |
1943 | logical_ring_default_vfuncs(engine); |
1944 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1945 | } |
1946 | ||
486e93f7 | 1947 | static int logical_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 | 1948 | { |
a19d6ff2 TU |
1949 | int ret; |
1950 | ||
019bf277 | 1951 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1952 | if (ret) |
1953 | goto error; | |
1954 | ||
a19d6ff2 TU |
1955 | return 0; |
1956 | ||
1957 | error: | |
1958 | intel_logical_ring_cleanup(engine); | |
1959 | return ret; | |
1960 | } | |
1961 | ||
88d2ba2e | 1962 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1963 | { |
1964 | struct drm_i915_private *dev_priv = engine->i915; | |
1965 | int ret; | |
1966 | ||
bb45438f TU |
1967 | logical_ring_setup(engine); |
1968 | ||
a19d6ff2 TU |
1969 | if (HAS_L3_DPF(dev_priv)) |
1970 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1971 | ||
1972 | /* Override some for render ring. */ | |
1973 | if (INTEL_GEN(dev_priv) >= 9) | |
1974 | engine->init_hw = gen9_init_render_ring; | |
1975 | else | |
1976 | engine->init_hw = gen8_init_render_ring; | |
1977 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1978 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1979 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1980 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1981 | |
f51455d4 | 1982 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1983 | if (ret) |
1984 | return ret; | |
1985 | ||
1986 | ret = intel_init_workaround_bb(engine); | |
1987 | if (ret) { | |
1988 | /* | |
1989 | * We continue even if we fail to initialize WA batch | |
1990 | * because we only expect rare glitches but nothing | |
1991 | * critical to prevent us from using GPU | |
1992 | */ | |
1993 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1994 | ret); | |
1995 | } | |
1996 | ||
d038fc7e | 1997 | return logical_ring_init(engine); |
a19d6ff2 TU |
1998 | } |
1999 | ||
88d2ba2e | 2000 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
2001 | { |
2002 | logical_ring_setup(engine); | |
2003 | ||
2004 | return logical_ring_init(engine); | |
454afebd OM |
2005 | } |
2006 | ||
0cea6502 | 2007 | static u32 |
c033666a | 2008 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
2009 | { |
2010 | u32 rpcs = 0; | |
2011 | ||
2012 | /* | |
2013 | * No explicit RPCS request is needed to ensure full | |
2014 | * slice/subslice/EU enablement prior to Gen9. | |
2015 | */ | |
c033666a | 2016 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
2017 | return 0; |
2018 | ||
2019 | /* | |
2020 | * Starting in Gen9, render power gating can leave | |
2021 | * slice/subslice/EU in a partially enabled state. We | |
2022 | * must make an explicit request through RPCS for full | |
2023 | * enablement. | |
2024 | */ | |
43b67998 | 2025 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 2026 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 2027 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
2028 | GEN8_RPCS_S_CNT_SHIFT; |
2029 | rpcs |= GEN8_RPCS_ENABLE; | |
2030 | } | |
2031 | ||
43b67998 | 2032 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 2033 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 2034 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
2035 | GEN8_RPCS_SS_CNT_SHIFT; |
2036 | rpcs |= GEN8_RPCS_ENABLE; | |
2037 | } | |
2038 | ||
43b67998 ID |
2039 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
2040 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 2041 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 2042 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
2043 | GEN8_RPCS_EU_MAX_SHIFT; |
2044 | rpcs |= GEN8_RPCS_ENABLE; | |
2045 | } | |
2046 | ||
2047 | return rpcs; | |
2048 | } | |
2049 | ||
0bc40be8 | 2050 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
2051 | { |
2052 | u32 indirect_ctx_offset; | |
2053 | ||
c033666a | 2054 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 2055 | default: |
c033666a | 2056 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 | 2057 | /* fall through */ |
7bd0a2c6 MT |
2058 | case 10: |
2059 | indirect_ctx_offset = | |
2060 | GEN10_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2061 | break; | |
71562919 MT |
2062 | case 9: |
2063 | indirect_ctx_offset = | |
2064 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2065 | break; | |
2066 | case 8: | |
2067 | indirect_ctx_offset = | |
2068 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
2069 | break; | |
2070 | } | |
2071 | ||
2072 | return indirect_ctx_offset; | |
2073 | } | |
2074 | ||
56e51bf0 | 2075 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
2076 | struct i915_gem_context *ctx, |
2077 | struct intel_engine_cs *engine, | |
2078 | struct intel_ring *ring) | |
8670d6f9 | 2079 | { |
a3aabe86 CW |
2080 | struct drm_i915_private *dev_priv = engine->i915; |
2081 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
2082 | u32 base = engine->mmio_base; |
2083 | bool rcs = engine->id == RCS; | |
2084 | ||
2085 | /* A context is actually a big batch buffer with several | |
2086 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
2087 | * values we are setting here are only for the first context restore: | |
2088 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
2089 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
2090 | * we are not initializing here). | |
2091 | */ | |
2092 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
2093 | MI_LRI_FORCE_POSTED; | |
2094 | ||
2095 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
2096 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
2097 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
2098 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
2099 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
2100 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
2101 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
2102 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
2103 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
2104 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
2105 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
2106 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
2107 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
2108 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
2109 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
2110 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
2111 | if (rcs) { | |
604a8f6f CW |
2112 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
2113 | ||
56e51bf0 TU |
2114 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); |
2115 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
2116 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
604a8f6f | 2117 | if (wa_ctx->indirect_ctx.size) { |
bde13ebd | 2118 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 2119 | |
56e51bf0 | 2120 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
2121 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
2122 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 2123 | |
56e51bf0 | 2124 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 2125 | intel_lr_indirect_ctx_offset(engine) << 6; |
604a8f6f CW |
2126 | } |
2127 | ||
2128 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
2129 | if (wa_ctx->per_ctx.size) { | |
2130 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); | |
17ee950d | 2131 | |
56e51bf0 | 2132 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 2133 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 2134 | } |
8670d6f9 | 2135 | } |
56e51bf0 TU |
2136 | |
2137 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
2138 | ||
2139 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 2140 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
2141 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
2142 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
2143 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
2144 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
2145 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
2146 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
2147 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
2148 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 2149 | |
949e8ab3 | 2150 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
2151 | /* 64b PPGTT (48bit canonical) |
2152 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2153 | * other PDP Descriptors are ignored. | |
2154 | */ | |
56e51bf0 | 2155 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
2156 | } |
2157 | ||
56e51bf0 TU |
2158 | if (rcs) { |
2159 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
2160 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
2161 | make_rpcs(dev_priv)); | |
19f81df2 RB |
2162 | |
2163 | i915_oa_init_reg_state(engine, ctx, regs); | |
8670d6f9 | 2164 | } |
a3aabe86 CW |
2165 | } |
2166 | ||
2167 | static int | |
2168 | populate_lr_context(struct i915_gem_context *ctx, | |
2169 | struct drm_i915_gem_object *ctx_obj, | |
2170 | struct intel_engine_cs *engine, | |
2171 | struct intel_ring *ring) | |
2172 | { | |
2173 | void *vaddr; | |
2174 | int ret; | |
2175 | ||
2176 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
2177 | if (ret) { | |
2178 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2179 | return ret; | |
2180 | } | |
2181 | ||
2182 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
2183 | if (IS_ERR(vaddr)) { | |
2184 | ret = PTR_ERR(vaddr); | |
2185 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
2186 | return ret; | |
2187 | } | |
a4f5ea64 | 2188 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
2189 | |
2190 | /* The second page of the context object contains some fields which must | |
2191 | * be set up prior to the first execution. */ | |
2192 | ||
2193 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
2194 | ctx, engine, ring); | |
8670d6f9 | 2195 | |
7d774cac | 2196 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2197 | |
2198 | return 0; | |
2199 | } | |
2200 | ||
e2efd130 | 2201 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2202 | struct intel_engine_cs *engine) |
ede7d42b | 2203 | { |
8c857917 | 2204 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2205 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2206 | struct i915_vma *vma; |
8c857917 | 2207 | uint32_t context_size; |
7e37f889 | 2208 | struct intel_ring *ring; |
8c857917 OM |
2209 | int ret; |
2210 | ||
9021ad03 | 2211 | WARN_ON(ce->state); |
ede7d42b | 2212 | |
63ffbcda | 2213 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 2214 | |
0b29c75a MT |
2215 | /* |
2216 | * Before the actual start of the context image, we insert a few pages | |
2217 | * for our own use and for sharing with the GuC. | |
2218 | */ | |
2219 | context_size += LRC_HEADER_PAGES * PAGE_SIZE; | |
d1675198 | 2220 | |
12d79d78 | 2221 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2222 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2223 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2224 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2225 | } |
2226 | ||
a01cb37a | 2227 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2228 | if (IS_ERR(vma)) { |
2229 | ret = PTR_ERR(vma); | |
2230 | goto error_deref_obj; | |
2231 | } | |
2232 | ||
7e37f889 | 2233 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2234 | if (IS_ERR(ring)) { |
2235 | ret = PTR_ERR(ring); | |
e84fe803 | 2236 | goto error_deref_obj; |
8670d6f9 OM |
2237 | } |
2238 | ||
dca33ecc | 2239 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2240 | if (ret) { |
2241 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2242 | goto error_ring_free; |
84c2377f OM |
2243 | } |
2244 | ||
dca33ecc | 2245 | ce->ring = ring; |
bf3783e5 | 2246 | ce->state = vma; |
0d402a24 | 2247 | ce->initialised |= engine->init_context == NULL; |
ede7d42b OM |
2248 | |
2249 | return 0; | |
8670d6f9 | 2250 | |
dca33ecc | 2251 | error_ring_free: |
7e37f889 | 2252 | intel_ring_free(ring); |
e84fe803 | 2253 | error_deref_obj: |
f8c417cd | 2254 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2255 | return ret; |
ede7d42b | 2256 | } |
3e5b6f05 | 2257 | |
821ed7df | 2258 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2259 | { |
e2f80391 | 2260 | struct intel_engine_cs *engine; |
bafb2f7d | 2261 | struct i915_gem_context *ctx; |
3b3f1650 | 2262 | enum intel_engine_id id; |
bafb2f7d CW |
2263 | |
2264 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2265 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2266 | * that stored in context. As we only write new commands from | |
2267 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2268 | * starts reading from its RING_HEAD from the context, it may try to | |
2269 | * execute that junk and die. | |
2270 | * | |
2271 | * So to avoid that we reset the context images upon resume. For | |
2272 | * simplicity, we just zero everything out. | |
2273 | */ | |
829a0af2 | 2274 | list_for_each_entry(ctx, &dev_priv->contexts.list, link) { |
3b3f1650 | 2275 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2276 | struct intel_context *ce = &ctx->engine[engine->id]; |
2277 | u32 *reg; | |
3e5b6f05 | 2278 | |
bafb2f7d CW |
2279 | if (!ce->state) |
2280 | continue; | |
7d774cac | 2281 | |
bafb2f7d CW |
2282 | reg = i915_gem_object_pin_map(ce->state->obj, |
2283 | I915_MAP_WB); | |
2284 | if (WARN_ON(IS_ERR(reg))) | |
2285 | continue; | |
3e5b6f05 | 2286 | |
bafb2f7d CW |
2287 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2288 | reg[CTX_RING_HEAD+1] = 0; | |
2289 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2290 | |
a4f5ea64 | 2291 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2292 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2293 | |
e6ba9992 | 2294 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2295 | } |
3e5b6f05 TD |
2296 | } |
2297 | } |