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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d CW |
159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
160 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
161 | GEN8_CTX_STATUS_PREEMPTED | \ | |
162 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
163 | ||
8670d6f9 OM |
164 | #define CTX_LRI_HEADER_0 0x01 |
165 | #define CTX_CONTEXT_CONTROL 0x02 | |
166 | #define CTX_RING_HEAD 0x04 | |
167 | #define CTX_RING_TAIL 0x06 | |
168 | #define CTX_RING_BUFFER_START 0x08 | |
169 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
170 | #define CTX_BB_HEAD_U 0x0c | |
171 | #define CTX_BB_HEAD_L 0x0e | |
172 | #define CTX_BB_STATE 0x10 | |
173 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
174 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
175 | #define CTX_SECOND_BB_STATE 0x16 | |
176 | #define CTX_BB_PER_CTX_PTR 0x18 | |
177 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
178 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
179 | #define CTX_LRI_HEADER_1 0x21 | |
180 | #define CTX_CTX_TIMESTAMP 0x22 | |
181 | #define CTX_PDP3_UDW 0x24 | |
182 | #define CTX_PDP3_LDW 0x26 | |
183 | #define CTX_PDP2_UDW 0x28 | |
184 | #define CTX_PDP2_LDW 0x2a | |
185 | #define CTX_PDP1_UDW 0x2c | |
186 | #define CTX_PDP1_LDW 0x2e | |
187 | #define CTX_PDP0_UDW 0x30 | |
188 | #define CTX_PDP0_LDW 0x32 | |
189 | #define CTX_LRI_HEADER_2 0x41 | |
190 | #define CTX_R_PWR_CLK_STATE 0x42 | |
191 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
192 | ||
84b790f8 BW |
193 | #define GEN8_CTX_VALID (1<<0) |
194 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
195 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
196 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
197 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e | 198 | |
0d925ea0 | 199 | #define ASSIGN_CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 200 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
201 | (reg_state)[(pos)+1] = (val); \ |
202 | } while (0) | |
203 | ||
204 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 205 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
206 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
207 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 208 | } while (0) |
e5815a2e | 209 | |
9244a817 | 210 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
211 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
212 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 213 | } while (0) |
2dba3239 | 214 | |
84b790f8 BW |
215 | enum { |
216 | FAULT_AND_HANG = 0, | |
217 | FAULT_AND_HALT, /* Debug only */ | |
218 | FAULT_AND_STREAM, | |
219 | FAULT_AND_CONTINUE /* Unsupported */ | |
220 | }; | |
221 | #define GEN8_CTX_ID_SHIFT 32 | |
7069b144 | 222 | #define GEN8_CTX_ID_WIDTH 21 |
71562919 MT |
223 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
224 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 225 | |
0e93cdd4 CW |
226 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
227 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
228 | ||
e2efd130 | 229 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 230 | struct intel_engine_cs *engine); |
e2efd130 | 231 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
e5292823 | 232 | struct intel_engine_cs *engine); |
7ba717cf | 233 | |
73e4d07f OM |
234 | /** |
235 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 236 | * @dev_priv: i915 device private |
73e4d07f OM |
237 | * @enable_execlists: value of i915.enable_execlists module parameter. |
238 | * | |
239 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 240 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
241 | * |
242 | * Return: 1 if Execlists is supported and has to be enabled. | |
243 | */ | |
c033666a | 244 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 245 | { |
a0bd6c31 ZL |
246 | /* On platforms with execlist available, vGPU will only |
247 | * support execlist mode, no ring buffer mode. | |
248 | */ | |
c033666a | 249 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
250 | return 1; |
251 | ||
c033666a | 252 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
253 | return 1; |
254 | ||
127f1003 OM |
255 | if (enable_execlists == 0) |
256 | return 0; | |
257 | ||
5a21b665 DV |
258 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
259 | USES_PPGTT(dev_priv) && | |
260 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
261 | return 1; |
262 | ||
263 | return 0; | |
264 | } | |
ede7d42b | 265 | |
ca82580c | 266 | static void |
0bc40be8 | 267 | logical_ring_init_platform_invariants(struct intel_engine_cs *engine) |
ca82580c | 268 | { |
c033666a | 269 | struct drm_i915_private *dev_priv = engine->i915; |
ca82580c | 270 | |
70c2a24d CW |
271 | engine->disable_lite_restore_wa = |
272 | (IS_SKL_REVID(dev_priv, 0, SKL_REVID_B0) || | |
273 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) && | |
274 | (engine->id == VCS || engine->id == VCS2); | |
ca82580c | 275 | |
0bc40be8 | 276 | engine->ctx_desc_template = GEN8_CTX_VALID; |
c033666a | 277 | if (IS_GEN8(dev_priv)) |
0bc40be8 TU |
278 | engine->ctx_desc_template |= GEN8_CTX_L3LLC_COHERENT; |
279 | engine->ctx_desc_template |= GEN8_CTX_PRIVILEGE; | |
ca82580c TU |
280 | |
281 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
282 | * signalling between Command Streamers */ | |
283 | /* ring->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; */ | |
284 | ||
285 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ | |
286 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ | |
0bc40be8 TU |
287 | if (engine->disable_lite_restore_wa) |
288 | engine->ctx_desc_template |= GEN8_CTX_FORCE_RESTORE; | |
ca82580c TU |
289 | } |
290 | ||
73e4d07f | 291 | /** |
ca82580c TU |
292 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
293 | * descriptor for a pinned context | |
ca82580c | 294 | * @ctx: Context to work on |
9021ad03 | 295 | * @engine: Engine the descriptor will be used with |
73e4d07f | 296 | * |
ca82580c TU |
297 | * The context descriptor encodes various attributes of a context, |
298 | * including its GTT address and some flags. Because it's fairly | |
299 | * expensive to calculate, we'll just do it once and cache the result, | |
300 | * which remains valid until the context is unpinned. | |
301 | * | |
6e5248b5 DV |
302 | * This is what a descriptor looks like, from LSB to MSB:: |
303 | * | |
304 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx_desc_template) | |
305 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context | |
306 | * bits 32-52: ctx ID, a globally unique tag | |
307 | * bits 53-54: mbz, reserved for use by hardware | |
308 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 309 | */ |
ca82580c | 310 | static void |
e2efd130 | 311 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 312 | struct intel_engine_cs *engine) |
84b790f8 | 313 | { |
9021ad03 | 314 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 315 | u64 desc; |
84b790f8 | 316 | |
7069b144 | 317 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 318 | |
c01fc532 ZW |
319 | desc = ctx->desc_template; /* bits 3-4 */ |
320 | desc |= engine->ctx_desc_template; /* bits 0-11 */ | |
bde13ebd | 321 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 322 | /* bits 12-31 */ |
7069b144 | 323 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 324 | |
9021ad03 | 325 | ce->lrc_desc = desc; |
5af05fef MT |
326 | } |
327 | ||
e2efd130 | 328 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 329 | struct intel_engine_cs *engine) |
84b790f8 | 330 | { |
0bc40be8 | 331 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 332 | } |
203a571b | 333 | |
bbd6c47e CW |
334 | static inline void |
335 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
336 | unsigned long status) | |
84b790f8 | 337 | { |
bbd6c47e CW |
338 | /* |
339 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
340 | * The compiler should eliminate this function as dead-code. | |
341 | */ | |
342 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
343 | return; | |
6daccb0b | 344 | |
bbd6c47e | 345 | atomic_notifier_call_chain(&rq->ctx->status_notifier, status, rq); |
84b790f8 BW |
346 | } |
347 | ||
c6a2ac71 TU |
348 | static void |
349 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
350 | { | |
351 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
352 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
353 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
354 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
355 | } | |
356 | ||
70c2a24d | 357 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 358 | { |
70c2a24d | 359 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
05d9824b | 360 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; |
70c2a24d | 361 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 362 | |
8f942018 | 363 | reg_state[CTX_RING_TAIL+1] = intel_ring_offset(rq->ring, rq->tail); |
ae1250b9 | 364 | |
c6a2ac71 TU |
365 | /* True 32b PPGTT with dynamic page allocation: update PDP |
366 | * registers and point the unallocated PDPs to scratch page. | |
367 | * PML4 is allocated during ppgtt init, so this is not needed | |
368 | * in 48-bit mode. | |
369 | */ | |
370 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) | |
371 | execlists_update_context_pdps(ppgtt, reg_state); | |
70c2a24d CW |
372 | |
373 | return ce->lrc_desc; | |
ae1250b9 OM |
374 | } |
375 | ||
70c2a24d | 376 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 377 | { |
70c2a24d CW |
378 | struct drm_i915_private *dev_priv = engine->i915; |
379 | struct execlist_port *port = engine->execlist_port; | |
bbd6c47e CW |
380 | u32 __iomem *elsp = |
381 | dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
382 | u64 desc[2]; | |
383 | ||
70c2a24d CW |
384 | if (!port[0].count) |
385 | execlists_context_status_change(port[0].request, | |
386 | INTEL_CONTEXT_SCHEDULE_IN); | |
387 | desc[0] = execlists_update_context(port[0].request); | |
388 | engine->preempt_wa = port[0].count++; /* bdw only? fixed on skl? */ | |
389 | ||
390 | if (port[1].request) { | |
391 | GEM_BUG_ON(port[1].count); | |
392 | execlists_context_status_change(port[1].request, | |
393 | INTEL_CONTEXT_SCHEDULE_IN); | |
394 | desc[1] = execlists_update_context(port[1].request); | |
395 | port[1].count = 1; | |
bbd6c47e CW |
396 | } else { |
397 | desc[1] = 0; | |
398 | } | |
70c2a24d | 399 | GEM_BUG_ON(desc[0] == desc[1]); |
bbd6c47e CW |
400 | |
401 | /* You must always write both descriptors in the order below. */ | |
402 | writel(upper_32_bits(desc[1]), elsp); | |
403 | writel(lower_32_bits(desc[1]), elsp); | |
404 | ||
405 | writel(upper_32_bits(desc[0]), elsp); | |
406 | /* The context is automatically loaded after the following */ | |
407 | writel(lower_32_bits(desc[0]), elsp); | |
408 | } | |
409 | ||
70c2a24d | 410 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 411 | { |
70c2a24d CW |
412 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
413 | ctx->execlists_force_single_submission); | |
414 | } | |
84b790f8 | 415 | |
70c2a24d CW |
416 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
417 | const struct i915_gem_context *next) | |
418 | { | |
419 | if (prev != next) | |
420 | return false; | |
26720ab9 | 421 | |
70c2a24d CW |
422 | if (ctx_single_port_submission(prev)) |
423 | return false; | |
26720ab9 | 424 | |
70c2a24d | 425 | return true; |
84b790f8 BW |
426 | } |
427 | ||
70c2a24d | 428 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 429 | { |
70c2a24d CW |
430 | struct drm_i915_gem_request *cursor, *last; |
431 | struct execlist_port *port = engine->execlist_port; | |
432 | bool submit = false; | |
433 | ||
434 | last = port->request; | |
435 | if (last) | |
436 | /* WaIdleLiteRestore:bdw,skl | |
437 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
438 | * as we resubmit the request. See gen8_emit_request() | |
439 | * for where we prepare the padding after the end of the | |
440 | * request. | |
441 | */ | |
442 | last->tail = last->wa_tail; | |
e981e7b1 | 443 | |
70c2a24d | 444 | GEM_BUG_ON(port[1].request); |
acdd884a | 445 | |
70c2a24d CW |
446 | /* Hardware submission is through 2 ports. Conceptually each port |
447 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
448 | * static for a context, and unique to each, so we only execute | |
449 | * requests belonging to a single context from each ring. RING_HEAD | |
450 | * is maintained by the CS in the context image, it marks the place | |
451 | * where it got up to last time, and through RING_TAIL we tell the CS | |
452 | * where we want to execute up to this time. | |
453 | * | |
454 | * In this list the requests are in order of execution. Consecutive | |
455 | * requests from the same context are adjacent in the ringbuffer. We | |
456 | * can combine these requests into a single RING_TAIL update: | |
457 | * | |
458 | * RING_HEAD...req1...req2 | |
459 | * ^- RING_TAIL | |
460 | * since to execute req2 the CS must first execute req1. | |
461 | * | |
462 | * Our goal then is to point each port to the end of a consecutive | |
463 | * sequence of requests as being the most optimal (fewest wake ups | |
464 | * and context switches) submission. | |
779949f4 | 465 | */ |
acdd884a | 466 | |
70c2a24d CW |
467 | spin_lock(&engine->execlist_lock); |
468 | list_for_each_entry(cursor, &engine->execlist_queue, execlist_link) { | |
469 | /* Can we combine this request with the current port? It has to | |
470 | * be the same context/ringbuffer and not have any exceptions | |
471 | * (e.g. GVT saying never to combine contexts). | |
c6a2ac71 | 472 | * |
70c2a24d CW |
473 | * If we can combine the requests, we can execute both by |
474 | * updating the RING_TAIL to point to the end of the second | |
475 | * request, and so we never need to tell the hardware about | |
476 | * the first. | |
53292cdb | 477 | */ |
70c2a24d CW |
478 | if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { |
479 | /* If we are on the second port and cannot combine | |
480 | * this request with the last, then we are done. | |
481 | */ | |
482 | if (port != engine->execlist_port) | |
483 | break; | |
484 | ||
485 | /* If GVT overrides us we only ever submit port[0], | |
486 | * leaving port[1] empty. Note that we also have | |
487 | * to be careful that we don't queue the same | |
488 | * context (even though a different request) to | |
489 | * the second port. | |
490 | */ | |
491 | if (ctx_single_port_submission(cursor->ctx)) | |
492 | break; | |
493 | ||
494 | GEM_BUG_ON(last->ctx == cursor->ctx); | |
495 | ||
496 | i915_gem_request_assign(&port->request, last); | |
497 | port++; | |
498 | } | |
499 | last = cursor; | |
500 | submit = true; | |
501 | } | |
502 | if (submit) { | |
503 | /* Decouple all the requests submitted from the queue */ | |
504 | engine->execlist_queue.next = &cursor->execlist_link; | |
505 | cursor->execlist_link.prev = &engine->execlist_queue; | |
506 | ||
507 | i915_gem_request_assign(&port->request, last); | |
53292cdb | 508 | } |
70c2a24d | 509 | spin_unlock(&engine->execlist_lock); |
53292cdb | 510 | |
70c2a24d CW |
511 | if (submit) |
512 | execlists_submit_ports(engine); | |
acdd884a MT |
513 | } |
514 | ||
70c2a24d | 515 | static bool execlists_elsp_idle(struct intel_engine_cs *engine) |
e981e7b1 | 516 | { |
70c2a24d | 517 | return !engine->execlist_port[0].request; |
e981e7b1 TD |
518 | } |
519 | ||
70c2a24d | 520 | static bool execlists_elsp_ready(struct intel_engine_cs *engine) |
91a41032 | 521 | { |
70c2a24d | 522 | int port; |
91a41032 | 523 | |
70c2a24d CW |
524 | port = 1; /* wait for a free slot */ |
525 | if (engine->disable_lite_restore_wa || engine->preempt_wa) | |
526 | port = 0; /* wait for GPU to be idle before continuing */ | |
c6a2ac71 | 527 | |
70c2a24d | 528 | return !engine->execlist_port[port].request; |
91a41032 BW |
529 | } |
530 | ||
6e5248b5 | 531 | /* |
73e4d07f OM |
532 | * Check the unread Context Status Buffers and manage the submission of new |
533 | * contexts to the ELSP accordingly. | |
534 | */ | |
27af5eea | 535 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 536 | { |
27af5eea | 537 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 538 | struct execlist_port *port = engine->execlist_port; |
c033666a | 539 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 540 | |
3756685a | 541 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 542 | |
70c2a24d CW |
543 | if (!execlists_elsp_idle(engine)) { |
544 | u32 __iomem *csb_mmio = | |
545 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
546 | u32 __iomem *buf = | |
547 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
548 | unsigned int csb, head, tail; | |
549 | ||
550 | csb = readl(csb_mmio); | |
551 | head = GEN8_CSB_READ_PTR(csb); | |
552 | tail = GEN8_CSB_WRITE_PTR(csb); | |
553 | if (tail < head) | |
554 | tail += GEN8_CSB_ENTRIES; | |
555 | while (head < tail) { | |
556 | unsigned int idx = ++head % GEN8_CSB_ENTRIES; | |
557 | unsigned int status = readl(buf + 2 * idx); | |
558 | ||
559 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) | |
560 | continue; | |
561 | ||
562 | GEM_BUG_ON(port[0].count == 0); | |
563 | if (--port[0].count == 0) { | |
564 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); | |
565 | execlists_context_status_change(port[0].request, | |
566 | INTEL_CONTEXT_SCHEDULE_OUT); | |
567 | ||
568 | i915_gem_request_put(port[0].request); | |
569 | port[0] = port[1]; | |
570 | memset(&port[1], 0, sizeof(port[1])); | |
571 | ||
572 | engine->preempt_wa = false; | |
573 | } | |
26720ab9 | 574 | |
70c2a24d CW |
575 | GEM_BUG_ON(port[0].count == 0 && |
576 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
e1fee72c OM |
577 | } |
578 | ||
70c2a24d CW |
579 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, |
580 | GEN8_CSB_WRITE_PTR(csb) << 8), | |
581 | csb_mmio); | |
e981e7b1 TD |
582 | } |
583 | ||
70c2a24d CW |
584 | if (execlists_elsp_ready(engine)) |
585 | execlists_dequeue(engine); | |
c6a2ac71 | 586 | |
70c2a24d | 587 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
588 | } |
589 | ||
f4ea6bdd | 590 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 591 | { |
4a570db5 | 592 | struct intel_engine_cs *engine = request->engine; |
acdd884a | 593 | |
27af5eea | 594 | spin_lock_bh(&engine->execlist_lock); |
acdd884a | 595 | |
ba49b2f8 | 596 | list_add_tail(&request->execlist_link, &engine->execlist_queue); |
70c2a24d CW |
597 | if (execlists_elsp_idle(engine)) |
598 | tasklet_hi_schedule(&engine->irq_tasklet); | |
acdd884a | 599 | |
27af5eea | 600 | spin_unlock_bh(&engine->execlist_lock); |
acdd884a MT |
601 | } |
602 | ||
40e895ce | 603 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 604 | { |
24f1d3cc | 605 | struct intel_engine_cs *engine = request->engine; |
9021ad03 | 606 | struct intel_context *ce = &request->ctx->engine[engine->id]; |
bfa01200 | 607 | int ret; |
bc0dce3f | 608 | |
6310346e CW |
609 | /* Flush enough space to reduce the likelihood of waiting after |
610 | * we start building the request - in which case we will just | |
611 | * have to repeat work. | |
612 | */ | |
0e93cdd4 | 613 | request->reserved_space += EXECLISTS_REQUEST_SIZE; |
6310346e | 614 | |
9021ad03 | 615 | if (!ce->state) { |
978f1e09 CW |
616 | ret = execlists_context_deferred_alloc(request->ctx, engine); |
617 | if (ret) | |
618 | return ret; | |
619 | } | |
620 | ||
dca33ecc | 621 | request->ring = ce->ring; |
f3cc01f0 | 622 | |
a7e02199 AD |
623 | if (i915.enable_guc_submission) { |
624 | /* | |
625 | * Check that the GuC has space for the request before | |
626 | * going any further, as the i915_add_request() call | |
627 | * later on mustn't fail ... | |
628 | */ | |
7c2c270d | 629 | ret = i915_guc_wq_check_space(request); |
a7e02199 AD |
630 | if (ret) |
631 | return ret; | |
632 | } | |
633 | ||
24f1d3cc CW |
634 | ret = intel_lr_context_pin(request->ctx, engine); |
635 | if (ret) | |
636 | return ret; | |
e28e404c | 637 | |
bfa01200 CW |
638 | ret = intel_ring_begin(request, 0); |
639 | if (ret) | |
640 | goto err_unpin; | |
641 | ||
9021ad03 | 642 | if (!ce->initialised) { |
24f1d3cc CW |
643 | ret = engine->init_context(request); |
644 | if (ret) | |
645 | goto err_unpin; | |
646 | ||
9021ad03 | 647 | ce->initialised = true; |
24f1d3cc CW |
648 | } |
649 | ||
650 | /* Note that after this point, we have committed to using | |
651 | * this request as it is being used to both track the | |
652 | * state of engine initialisation and liveness of the | |
653 | * golden renderstate above. Think twice before you try | |
654 | * to cancel/unwind this request now. | |
655 | */ | |
656 | ||
0e93cdd4 | 657 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; |
bfa01200 CW |
658 | return 0; |
659 | ||
660 | err_unpin: | |
24f1d3cc | 661 | intel_lr_context_unpin(request->ctx, engine); |
e28e404c | 662 | return ret; |
bc0dce3f JH |
663 | } |
664 | ||
bc0dce3f | 665 | /* |
ddd66c51 | 666 | * intel_logical_ring_advance() - advance the tail and prepare for submission |
ae70797d | 667 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
668 | * |
669 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
670 | * really happens during submission is that the context and current tail will be placed | |
671 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
672 | * point, the tail *inside* the context is updated and the ELSP written to. | |
673 | */ | |
7c17d377 | 674 | static int |
ddd66c51 | 675 | intel_logical_ring_advance(struct drm_i915_gem_request *request) |
bc0dce3f | 676 | { |
7e37f889 | 677 | struct intel_ring *ring = request->ring; |
4a570db5 | 678 | struct intel_engine_cs *engine = request->engine; |
bc0dce3f | 679 | |
1dae2dfb CW |
680 | intel_ring_advance(ring); |
681 | request->tail = ring->tail; | |
bc0dce3f | 682 | |
7c17d377 CW |
683 | /* |
684 | * Here we add two extra NOOPs as padding to avoid | |
685 | * lite restore of a context with HEAD==TAIL. | |
686 | * | |
687 | * Caller must reserve WA_TAIL_DWORDS for us! | |
688 | */ | |
1dae2dfb CW |
689 | intel_ring_emit(ring, MI_NOOP); |
690 | intel_ring_emit(ring, MI_NOOP); | |
691 | intel_ring_advance(ring); | |
a52abd2f | 692 | request->wa_tail = ring->tail; |
d1675198 | 693 | |
a16a4052 CW |
694 | /* We keep the previous context alive until we retire the following |
695 | * request. This ensures that any the context object is still pinned | |
696 | * for any residual writes the HW makes into it on the context switch | |
697 | * into the next object following the breadcrumb. Otherwise, we may | |
698 | * retire the context too early. | |
699 | */ | |
700 | request->previous_context = engine->last_context; | |
701 | engine->last_context = request->ctx; | |
7c17d377 | 702 | return 0; |
bc0dce3f JH |
703 | } |
704 | ||
e2efd130 | 705 | static int intel_lr_context_pin(struct i915_gem_context *ctx, |
24f1d3cc | 706 | struct intel_engine_cs *engine) |
dcb4c12a | 707 | { |
9021ad03 | 708 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac TU |
709 | void *vaddr; |
710 | u32 *lrc_reg_state; | |
ca82580c | 711 | int ret; |
dcb4c12a | 712 | |
91c8a326 | 713 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 714 | |
9021ad03 | 715 | if (ce->pin_count++) |
24f1d3cc CW |
716 | return 0; |
717 | ||
bf3783e5 CW |
718 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, |
719 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP | PIN_GLOBAL); | |
e84fe803 | 720 | if (ret) |
24f1d3cc | 721 | goto err; |
7ba717cf | 722 | |
bf3783e5 | 723 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
724 | if (IS_ERR(vaddr)) { |
725 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 726 | goto unpin_vma; |
82352e90 TU |
727 | } |
728 | ||
7d774cac TU |
729 | lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
730 | ||
aad29fbb | 731 | ret = intel_ring_pin(ce->ring); |
e84fe803 | 732 | if (ret) |
7d774cac | 733 | goto unpin_map; |
d1675198 | 734 | |
0bc40be8 | 735 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 736 | |
bde13ebd CW |
737 | lrc_reg_state[CTX_RING_BUFFER_START+1] = |
738 | i915_ggtt_offset(ce->ring->vma); | |
9021ad03 | 739 | ce->lrc_reg_state = lrc_reg_state; |
bf3783e5 | 740 | ce->state->obj->dirty = true; |
e93c28f3 | 741 | |
e84fe803 | 742 | /* Invalidate GuC TLB. */ |
bf3783e5 CW |
743 | if (i915.enable_guc_submission) { |
744 | struct drm_i915_private *dev_priv = ctx->i915; | |
e84fe803 | 745 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); |
bf3783e5 | 746 | } |
dcb4c12a | 747 | |
9a6feaf0 | 748 | i915_gem_context_get(ctx); |
24f1d3cc | 749 | return 0; |
7ba717cf | 750 | |
7d774cac | 751 | unpin_map: |
bf3783e5 CW |
752 | i915_gem_object_unpin_map(ce->state->obj); |
753 | unpin_vma: | |
754 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 755 | err: |
9021ad03 | 756 | ce->pin_count = 0; |
e84fe803 NH |
757 | return ret; |
758 | } | |
759 | ||
e2efd130 | 760 | void intel_lr_context_unpin(struct i915_gem_context *ctx, |
24f1d3cc | 761 | struct intel_engine_cs *engine) |
e84fe803 | 762 | { |
9021ad03 | 763 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 764 | |
91c8a326 | 765 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 766 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 767 | |
9021ad03 | 768 | if (--ce->pin_count) |
24f1d3cc | 769 | return; |
e84fe803 | 770 | |
aad29fbb | 771 | intel_ring_unpin(ce->ring); |
dcb4c12a | 772 | |
bf3783e5 CW |
773 | i915_gem_object_unpin_map(ce->state->obj); |
774 | i915_vma_unpin(ce->state); | |
321fe304 | 775 | |
9a6feaf0 | 776 | i915_gem_context_put(ctx); |
dcb4c12a OM |
777 | } |
778 | ||
e2be4faf | 779 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
780 | { |
781 | int ret, i; | |
7e37f889 | 782 | struct intel_ring *ring = req->ring; |
c033666a | 783 | struct i915_workarounds *w = &req->i915->workarounds; |
771b9a53 | 784 | |
cd7feaaa | 785 | if (w->count == 0) |
771b9a53 MT |
786 | return 0; |
787 | ||
7c9cf4e3 | 788 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
789 | if (ret) |
790 | return ret; | |
791 | ||
987046ad | 792 | ret = intel_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
793 | if (ret) |
794 | return ret; | |
795 | ||
1dae2dfb | 796 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(w->count)); |
771b9a53 | 797 | for (i = 0; i < w->count; i++) { |
1dae2dfb CW |
798 | intel_ring_emit_reg(ring, w->reg[i].addr); |
799 | intel_ring_emit(ring, w->reg[i].value); | |
771b9a53 | 800 | } |
1dae2dfb | 801 | intel_ring_emit(ring, MI_NOOP); |
771b9a53 | 802 | |
1dae2dfb | 803 | intel_ring_advance(ring); |
771b9a53 | 804 | |
7c9cf4e3 | 805 | ret = req->engine->emit_flush(req, EMIT_BARRIER); |
771b9a53 MT |
806 | if (ret) |
807 | return ret; | |
808 | ||
809 | return 0; | |
810 | } | |
811 | ||
83b8a982 | 812 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 813 | do { \ |
83b8a982 AS |
814 | int __index = (index)++; \ |
815 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
816 | return -ENOSPC; \ |
817 | } \ | |
83b8a982 | 818 | batch[__index] = (cmd); \ |
17ee950d AS |
819 | } while (0) |
820 | ||
8f40db77 | 821 | #define wa_ctx_emit_reg(batch, index, reg) \ |
f0f59a00 | 822 | wa_ctx_emit((batch), (index), i915_mmio_reg_offset(reg)) |
9e000847 AS |
823 | |
824 | /* | |
825 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
826 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
827 | * but there is a slight complication as this is applied in WA batch where the | |
828 | * values are only initialized once so we cannot take register value at the | |
829 | * beginning and reuse it further; hence we save its value to memory, upload a | |
830 | * constant value with bit21 set and then we restore it back with the saved value. | |
831 | * To simplify the WA, a constant value is formed by using the default value | |
832 | * of this register. This shouldn't be a problem because we are only modifying | |
833 | * it for a short period and this batch in non-premptible. We can ofcourse | |
834 | * use additional instructions that read the actual value of the register | |
835 | * at that time and set our bit of interest but it makes the WA complicated. | |
836 | * | |
837 | * This WA is also required for Gen9 so extracting as a function avoids | |
838 | * code duplication. | |
839 | */ | |
0bc40be8 | 840 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, |
6e5248b5 | 841 | uint32_t *batch, |
9e000847 AS |
842 | uint32_t index) |
843 | { | |
5e580523 | 844 | struct drm_i915_private *dev_priv = engine->i915; |
9e000847 AS |
845 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); |
846 | ||
a4106a78 | 847 | /* |
fe905819 | 848 | * WaDisableLSQCROPERFforOCL:skl,kbl |
a4106a78 AS |
849 | * This WA is implemented in skl_init_clock_gating() but since |
850 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
851 | * set this bit here to retain the WA during flush. | |
852 | */ | |
738fa1b3 MK |
853 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_E0) || |
854 | IS_KBL_REVID(dev_priv, 0, KBL_REVID_E0)) | |
a4106a78 AS |
855 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; |
856 | ||
f1afe24f | 857 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 | 858 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 859 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 860 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 AS |
861 | wa_ctx_emit(batch, index, 0); |
862 | ||
863 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
8f40db77 | 864 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
83b8a982 AS |
865 | wa_ctx_emit(batch, index, l3sqc4_flush); |
866 | ||
867 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
868 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
869 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
870 | wa_ctx_emit(batch, index, 0); | |
871 | wa_ctx_emit(batch, index, 0); | |
872 | wa_ctx_emit(batch, index, 0); | |
873 | wa_ctx_emit(batch, index, 0); | |
874 | ||
f1afe24f | 875 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 | 876 | MI_SRM_LRM_GLOBAL_GTT)); |
8f40db77 | 877 | wa_ctx_emit_reg(batch, index, GEN8_L3SQCREG4); |
bde13ebd | 878 | wa_ctx_emit(batch, index, i915_ggtt_offset(engine->scratch) + 256); |
83b8a982 | 879 | wa_ctx_emit(batch, index, 0); |
9e000847 AS |
880 | |
881 | return index; | |
882 | } | |
883 | ||
17ee950d AS |
884 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
885 | uint32_t offset, | |
886 | uint32_t start_alignment) | |
887 | { | |
888 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
889 | } | |
890 | ||
891 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
892 | uint32_t offset, | |
893 | uint32_t size_alignment) | |
894 | { | |
895 | wa_ctx->size = offset - wa_ctx->offset; | |
896 | ||
897 | WARN(wa_ctx->size % size_alignment, | |
898 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
899 | wa_ctx->size, size_alignment); | |
900 | return 0; | |
901 | } | |
902 | ||
6e5248b5 DV |
903 | /* |
904 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
905 | * initialized at the beginning and shared across all contexts but this field | |
906 | * helps us to have multiple batches at different offsets and select them based | |
907 | * on a criteria. At the moment this batch always start at the beginning of the page | |
908 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 909 | * |
6e5248b5 DV |
910 | * The number of WA applied are not known at the beginning; we use this field |
911 | * to return the no of DWORDS written. | |
17ee950d | 912 | * |
6e5248b5 DV |
913 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
914 | * so it adds NOOPs as padding to make it cacheline aligned. | |
915 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
916 | * makes a complete batch buffer. | |
17ee950d | 917 | */ |
0bc40be8 | 918 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *engine, |
17ee950d | 919 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 920 | uint32_t *batch, |
17ee950d AS |
921 | uint32_t *offset) |
922 | { | |
0160f055 | 923 | uint32_t scratch_addr; |
17ee950d AS |
924 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
925 | ||
7ad00d1a | 926 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 927 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 928 | |
c82435bb | 929 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
c033666a | 930 | if (IS_BROADWELL(engine->i915)) { |
0bc40be8 | 931 | int rc = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
604ef734 AH |
932 | if (rc < 0) |
933 | return rc; | |
934 | index = rc; | |
c82435bb AS |
935 | } |
936 | ||
0160f055 AS |
937 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
938 | /* Actual scratch location is at 128 bytes offset */ | |
bde13ebd | 939 | scratch_addr = i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
0160f055 | 940 | |
83b8a982 AS |
941 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
942 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
943 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
944 | PIPE_CONTROL_CS_STALL | | |
945 | PIPE_CONTROL_QW_WRITE)); | |
946 | wa_ctx_emit(batch, index, scratch_addr); | |
947 | wa_ctx_emit(batch, index, 0); | |
948 | wa_ctx_emit(batch, index, 0); | |
949 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 950 | |
17ee950d AS |
951 | /* Pad to end of cacheline */ |
952 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 953 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
954 | |
955 | /* | |
956 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
957 | * execution depends on the length specified in terms of cache lines | |
958 | * in the register CTX_RCS_INDIRECT_CTX | |
959 | */ | |
960 | ||
961 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
962 | } | |
963 | ||
6e5248b5 DV |
964 | /* |
965 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
966 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 967 | * |
6e5248b5 | 968 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
969 | * |
970 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
971 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
972 | */ | |
0bc40be8 | 973 | static int gen8_init_perctx_bb(struct intel_engine_cs *engine, |
17ee950d | 974 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 975 | uint32_t *batch, |
17ee950d AS |
976 | uint32_t *offset) |
977 | { | |
978 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
979 | ||
7ad00d1a | 980 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 981 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 982 | |
83b8a982 | 983 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
984 | |
985 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
986 | } | |
987 | ||
0bc40be8 | 988 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *engine, |
0504cffc | 989 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 990 | uint32_t *batch, |
0504cffc AS |
991 | uint32_t *offset) |
992 | { | |
a4106a78 | 993 | int ret; |
5e580523 | 994 | struct drm_i915_private *dev_priv = engine->i915; |
0504cffc AS |
995 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
996 | ||
0907c8f7 | 997 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
5e580523 DA |
998 | if (IS_SKL_REVID(dev_priv, 0, SKL_REVID_D0) || |
999 | IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) | |
0907c8f7 | 1000 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
0504cffc | 1001 | |
a4106a78 | 1002 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
0bc40be8 | 1003 | ret = gen8_emit_flush_coherentl3_wa(engine, batch, index); |
a4106a78 AS |
1004 | if (ret < 0) |
1005 | return ret; | |
1006 | index = ret; | |
1007 | ||
873e8171 MK |
1008 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl */ |
1009 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1010 | wa_ctx_emit_reg(batch, index, COMMON_SLICE_CHICKEN2); | |
1011 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE( | |
1012 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE)); | |
1013 | wa_ctx_emit(batch, index, MI_NOOP); | |
1014 | ||
066d4628 MK |
1015 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1016 | /* Actual scratch location is at 128 bytes offset */ | |
703d1282 | 1017 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_A0)) { |
56c0f1a7 | 1018 | u32 scratch_addr = |
bde13ebd | 1019 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; |
066d4628 MK |
1020 | |
1021 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1022 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1023 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1024 | PIPE_CONTROL_CS_STALL | | |
1025 | PIPE_CONTROL_QW_WRITE)); | |
1026 | wa_ctx_emit(batch, index, scratch_addr); | |
1027 | wa_ctx_emit(batch, index, 0); | |
1028 | wa_ctx_emit(batch, index, 0); | |
1029 | wa_ctx_emit(batch, index, 0); | |
1030 | } | |
3485d99e TG |
1031 | |
1032 | /* WaMediaPoolStateCmdInWABB:bxt */ | |
1033 | if (HAS_POOLED_EU(engine->i915)) { | |
1034 | /* | |
1035 | * EU pool configuration is setup along with golden context | |
1036 | * during context initialization. This value depends on | |
1037 | * device type (2x6 or 3x6) and needs to be updated based | |
1038 | * on which subslice is disabled especially for 2x6 | |
1039 | * devices, however it is safe to load default | |
1040 | * configuration of 3x6 device instead of masking off | |
1041 | * corresponding bits because HW ignores bits of a disabled | |
1042 | * subslice and drops down to appropriate config. Please | |
1043 | * see render_state_setup() in i915_gem_render_state.c for | |
1044 | * possible configurations, to avoid duplication they are | |
1045 | * not shown here again. | |
1046 | */ | |
1047 | u32 eu_pool_config = 0x00777000; | |
1048 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_STATE); | |
1049 | wa_ctx_emit(batch, index, GEN9_MEDIA_POOL_ENABLE); | |
1050 | wa_ctx_emit(batch, index, eu_pool_config); | |
1051 | wa_ctx_emit(batch, index, 0); | |
1052 | wa_ctx_emit(batch, index, 0); | |
1053 | wa_ctx_emit(batch, index, 0); | |
1054 | } | |
1055 | ||
0504cffc AS |
1056 | /* Pad to end of cacheline */ |
1057 | while (index % CACHELINE_DWORDS) | |
1058 | wa_ctx_emit(batch, index, MI_NOOP); | |
1059 | ||
1060 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1061 | } | |
1062 | ||
0bc40be8 | 1063 | static int gen9_init_perctx_bb(struct intel_engine_cs *engine, |
0504cffc | 1064 | struct i915_wa_ctx_bb *wa_ctx, |
6e5248b5 | 1065 | uint32_t *batch, |
0504cffc AS |
1066 | uint32_t *offset) |
1067 | { | |
1068 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1069 | ||
9b01435d | 1070 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
c033666a CW |
1071 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_B0) || |
1072 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) { | |
9b01435d | 1073 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); |
8f40db77 | 1074 | wa_ctx_emit_reg(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); |
9b01435d AS |
1075 | wa_ctx_emit(batch, index, |
1076 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1077 | wa_ctx_emit(batch, index, MI_NOOP); | |
1078 | } | |
1079 | ||
b1e429fe | 1080 | /* WaClearTdlStateAckDirtyBits:bxt */ |
c033666a | 1081 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_B0)) { |
b1e429fe TG |
1082 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(4)); |
1083 | ||
1084 | wa_ctx_emit_reg(batch, index, GEN8_STATE_ACK); | |
1085 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1086 | ||
1087 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE1); | |
1088 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1089 | ||
1090 | wa_ctx_emit_reg(batch, index, GEN9_STATE_ACK_SLICE2); | |
1091 | wa_ctx_emit(batch, index, _MASKED_BIT_DISABLE(GEN9_SUBSLICE_TDL_ACK_BITS)); | |
1092 | ||
1093 | wa_ctx_emit_reg(batch, index, GEN7_ROW_CHICKEN2); | |
1094 | /* dummy write to CS, mask bits are 0 to ensure the register is not modified */ | |
1095 | wa_ctx_emit(batch, index, 0x0); | |
1096 | wa_ctx_emit(batch, index, MI_NOOP); | |
1097 | } | |
1098 | ||
0907c8f7 | 1099 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
c033666a CW |
1100 | if (IS_SKL_REVID(engine->i915, 0, SKL_REVID_D0) || |
1101 | IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) | |
0907c8f7 AS |
1102 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
1103 | ||
0504cffc AS |
1104 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1105 | ||
1106 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1107 | } | |
1108 | ||
0bc40be8 | 1109 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *engine, u32 size) |
17ee950d | 1110 | { |
48bb74e4 CW |
1111 | struct drm_i915_gem_object *obj; |
1112 | struct i915_vma *vma; | |
1113 | int err; | |
17ee950d | 1114 | |
48bb74e4 CW |
1115 | obj = i915_gem_object_create(&engine->i915->drm, PAGE_ALIGN(size)); |
1116 | if (IS_ERR(obj)) | |
1117 | return PTR_ERR(obj); | |
17ee950d | 1118 | |
48bb74e4 CW |
1119 | vma = i915_vma_create(obj, &engine->i915->ggtt.base, NULL); |
1120 | if (IS_ERR(vma)) { | |
1121 | err = PTR_ERR(vma); | |
1122 | goto err; | |
17ee950d AS |
1123 | } |
1124 | ||
48bb74e4 CW |
1125 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1126 | if (err) | |
1127 | goto err; | |
1128 | ||
1129 | engine->wa_ctx.vma = vma; | |
17ee950d | 1130 | return 0; |
48bb74e4 CW |
1131 | |
1132 | err: | |
1133 | i915_gem_object_put(obj); | |
1134 | return err; | |
17ee950d AS |
1135 | } |
1136 | ||
0bc40be8 | 1137 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *engine) |
17ee950d | 1138 | { |
19880c4a | 1139 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1140 | } |
1141 | ||
0bc40be8 | 1142 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1143 | { |
48bb74e4 | 1144 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
17ee950d AS |
1145 | uint32_t *batch; |
1146 | uint32_t offset; | |
1147 | struct page *page; | |
48bb74e4 | 1148 | int ret; |
17ee950d | 1149 | |
0bc40be8 | 1150 | WARN_ON(engine->id != RCS); |
17ee950d | 1151 | |
5e60d790 | 1152 | /* update this when WA for higher Gen are added */ |
c033666a | 1153 | if (INTEL_GEN(engine->i915) > 9) { |
0504cffc | 1154 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", |
c033666a | 1155 | INTEL_GEN(engine->i915)); |
5e60d790 | 1156 | return 0; |
0504cffc | 1157 | } |
5e60d790 | 1158 | |
c4db7599 | 1159 | /* some WA perform writes to scratch page, ensure it is valid */ |
56c0f1a7 | 1160 | if (!engine->scratch) { |
0bc40be8 | 1161 | DRM_ERROR("scratch page not allocated for %s\n", engine->name); |
c4db7599 AS |
1162 | return -EINVAL; |
1163 | } | |
1164 | ||
0bc40be8 | 1165 | ret = lrc_setup_wa_ctx_obj(engine, PAGE_SIZE); |
17ee950d AS |
1166 | if (ret) { |
1167 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1168 | return ret; | |
1169 | } | |
1170 | ||
48bb74e4 | 1171 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
17ee950d AS |
1172 | batch = kmap_atomic(page); |
1173 | offset = 0; | |
1174 | ||
c033666a | 1175 | if (IS_GEN8(engine->i915)) { |
0bc40be8 | 1176 | ret = gen8_init_indirectctx_bb(engine, |
17ee950d AS |
1177 | &wa_ctx->indirect_ctx, |
1178 | batch, | |
1179 | &offset); | |
1180 | if (ret) | |
1181 | goto out; | |
1182 | ||
0bc40be8 | 1183 | ret = gen8_init_perctx_bb(engine, |
17ee950d AS |
1184 | &wa_ctx->per_ctx, |
1185 | batch, | |
1186 | &offset); | |
1187 | if (ret) | |
1188 | goto out; | |
c033666a | 1189 | } else if (IS_GEN9(engine->i915)) { |
0bc40be8 | 1190 | ret = gen9_init_indirectctx_bb(engine, |
0504cffc AS |
1191 | &wa_ctx->indirect_ctx, |
1192 | batch, | |
1193 | &offset); | |
1194 | if (ret) | |
1195 | goto out; | |
1196 | ||
0bc40be8 | 1197 | ret = gen9_init_perctx_bb(engine, |
0504cffc AS |
1198 | &wa_ctx->per_ctx, |
1199 | batch, | |
1200 | &offset); | |
1201 | if (ret) | |
1202 | goto out; | |
17ee950d AS |
1203 | } |
1204 | ||
1205 | out: | |
1206 | kunmap_atomic(batch); | |
1207 | if (ret) | |
0bc40be8 | 1208 | lrc_destroy_wa_ctx_obj(engine); |
17ee950d AS |
1209 | |
1210 | return ret; | |
1211 | } | |
1212 | ||
04794adb TU |
1213 | static void lrc_init_hws(struct intel_engine_cs *engine) |
1214 | { | |
c033666a | 1215 | struct drm_i915_private *dev_priv = engine->i915; |
04794adb TU |
1216 | |
1217 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), | |
57e88531 | 1218 | engine->status_page.ggtt_offset); |
04794adb TU |
1219 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); |
1220 | } | |
1221 | ||
0bc40be8 | 1222 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1223 | { |
c033666a | 1224 | struct drm_i915_private *dev_priv = engine->i915; |
821ed7df CW |
1225 | int ret; |
1226 | ||
1227 | ret = intel_mocs_init_engine(engine); | |
1228 | if (ret) | |
1229 | return ret; | |
9b1136d5 | 1230 | |
04794adb | 1231 | lrc_init_hws(engine); |
e84fe803 | 1232 | |
821ed7df CW |
1233 | intel_engine_reset_irq(engine); |
1234 | ||
0bc40be8 | 1235 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
73d477f6 | 1236 | |
0bc40be8 | 1237 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 OM |
1238 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | |
1239 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
dfc53c5e | 1240 | |
0bc40be8 | 1241 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1242 | |
fc0768ce | 1243 | intel_engine_init_hangcheck(engine); |
9b1136d5 | 1244 | |
821ed7df CW |
1245 | if (!execlists_elsp_idle(engine)) |
1246 | execlists_submit_ports(engine); | |
1247 | ||
1248 | return 0; | |
9b1136d5 OM |
1249 | } |
1250 | ||
0bc40be8 | 1251 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1252 | { |
c033666a | 1253 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1254 | int ret; |
1255 | ||
0bc40be8 | 1256 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1257 | if (ret) |
1258 | return ret; | |
1259 | ||
1260 | /* We need to disable the AsyncFlip performance optimisations in order | |
1261 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1262 | * programmed to '1' on all products. | |
1263 | * | |
1264 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1265 | */ | |
1266 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1267 | ||
9b1136d5 OM |
1268 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1269 | ||
0bc40be8 | 1270 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1271 | } |
1272 | ||
0bc40be8 | 1273 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1274 | { |
1275 | int ret; | |
1276 | ||
0bc40be8 | 1277 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1278 | if (ret) |
1279 | return ret; | |
1280 | ||
0bc40be8 | 1281 | return init_workarounds_ring(engine); |
82ef822e DL |
1282 | } |
1283 | ||
821ed7df CW |
1284 | static void reset_common_ring(struct intel_engine_cs *engine, |
1285 | struct drm_i915_gem_request *request) | |
1286 | { | |
1287 | struct drm_i915_private *dev_priv = engine->i915; | |
1288 | struct execlist_port *port = engine->execlist_port; | |
1289 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
1290 | ||
1291 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ | |
1292 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; | |
1293 | request->ring->head = request->postfix; | |
1294 | request->ring->last_retired_head = -1; | |
1295 | intel_ring_update_space(request->ring); | |
1296 | ||
1297 | if (i915.enable_guc_submission) | |
1298 | return; | |
1299 | ||
1300 | /* Catch up with any missed context-switch interrupts */ | |
1301 | I915_WRITE(RING_CONTEXT_STATUS_PTR(engine), _MASKED_FIELD(0xffff, 0)); | |
1302 | if (request->ctx != port[0].request->ctx) { | |
1303 | i915_gem_request_put(port[0].request); | |
1304 | port[0] = port[1]; | |
1305 | memset(&port[1], 0, sizeof(port[1])); | |
1306 | } | |
1307 | ||
1308 | /* CS is stopped, and we will resubmit both ports on resume */ | |
1309 | GEM_BUG_ON(request->ctx != port[0].request->ctx); | |
1310 | port[0].count = 0; | |
1311 | port[1].count = 0; | |
1312 | } | |
1313 | ||
7a01a0a2 MT |
1314 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1315 | { | |
1316 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
7e37f889 | 1317 | struct intel_ring *ring = req->ring; |
4a570db5 | 1318 | struct intel_engine_cs *engine = req->engine; |
7a01a0a2 MT |
1319 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; |
1320 | int i, ret; | |
1321 | ||
987046ad | 1322 | ret = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
7a01a0a2 MT |
1323 | if (ret) |
1324 | return ret; | |
1325 | ||
b5321f30 | 1326 | intel_ring_emit(ring, MI_LOAD_REGISTER_IMM(num_lri_cmds)); |
7a01a0a2 MT |
1327 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { |
1328 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1329 | ||
b5321f30 CW |
1330 | intel_ring_emit_reg(ring, GEN8_RING_PDP_UDW(engine, i)); |
1331 | intel_ring_emit(ring, upper_32_bits(pd_daddr)); | |
1332 | intel_ring_emit_reg(ring, GEN8_RING_PDP_LDW(engine, i)); | |
1333 | intel_ring_emit(ring, lower_32_bits(pd_daddr)); | |
7a01a0a2 MT |
1334 | } |
1335 | ||
b5321f30 CW |
1336 | intel_ring_emit(ring, MI_NOOP); |
1337 | intel_ring_advance(ring); | |
7a01a0a2 MT |
1338 | |
1339 | return 0; | |
1340 | } | |
1341 | ||
be795fc1 | 1342 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba CW |
1343 | u64 offset, u32 len, |
1344 | unsigned int dispatch_flags) | |
15648585 | 1345 | { |
7e37f889 | 1346 | struct intel_ring *ring = req->ring; |
8e004efc | 1347 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1348 | int ret; |
1349 | ||
7a01a0a2 MT |
1350 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1351 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1352 | * but we can't. Force Restore would be a second option, but | |
1353 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1354 | * not idle). PML4 is allocated during ppgtt init so this is |
1355 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1356 | if (req->ctx->ppgtt && |
666796da | 1357 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings)) { |
331f38e7 | 1358 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
c033666a | 1359 | !intel_vgpu_active(req->i915)) { |
2dba3239 MT |
1360 | ret = intel_logical_ring_emit_pdps(req); |
1361 | if (ret) | |
1362 | return ret; | |
1363 | } | |
7a01a0a2 | 1364 | |
666796da | 1365 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1366 | } |
1367 | ||
987046ad | 1368 | ret = intel_ring_begin(req, 4); |
15648585 OM |
1369 | if (ret) |
1370 | return ret; | |
1371 | ||
1372 | /* FIXME(BDW): Address space and security selectors. */ | |
b5321f30 CW |
1373 | intel_ring_emit(ring, MI_BATCH_BUFFER_START_GEN8 | |
1374 | (ppgtt<<8) | | |
1375 | (dispatch_flags & I915_DISPATCH_RS ? | |
1376 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
1377 | intel_ring_emit(ring, lower_32_bits(offset)); | |
1378 | intel_ring_emit(ring, upper_32_bits(offset)); | |
1379 | intel_ring_emit(ring, MI_NOOP); | |
1380 | intel_ring_advance(ring); | |
15648585 OM |
1381 | |
1382 | return 0; | |
1383 | } | |
1384 | ||
31bb59cc | 1385 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1386 | { |
c033666a | 1387 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1388 | I915_WRITE_IMR(engine, |
1389 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1390 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1391 | } |
1392 | ||
31bb59cc | 1393 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1394 | { |
c033666a | 1395 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1396 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1397 | } |
1398 | ||
7c9cf4e3 | 1399 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1400 | { |
7e37f889 CW |
1401 | struct intel_ring *ring = request->ring; |
1402 | u32 cmd; | |
4712274c OM |
1403 | int ret; |
1404 | ||
987046ad | 1405 | ret = intel_ring_begin(request, 4); |
4712274c OM |
1406 | if (ret) |
1407 | return ret; | |
1408 | ||
1409 | cmd = MI_FLUSH_DW + 1; | |
1410 | ||
f0a1fb10 CW |
1411 | /* We always require a command barrier so that subsequent |
1412 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1413 | * wrt the contents of the write cache being flushed to memory | |
1414 | * (and thus being coherent from the CPU). | |
1415 | */ | |
1416 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1417 | ||
7c9cf4e3 | 1418 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1419 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1420 | if (request->engine->id == VCS) |
f0a1fb10 | 1421 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1422 | } |
1423 | ||
b5321f30 CW |
1424 | intel_ring_emit(ring, cmd); |
1425 | intel_ring_emit(ring, | |
1426 | I915_GEM_HWS_SCRATCH_ADDR | | |
1427 | MI_FLUSH_DW_USE_GTT); | |
1428 | intel_ring_emit(ring, 0); /* upper addr */ | |
1429 | intel_ring_emit(ring, 0); /* value */ | |
1430 | intel_ring_advance(ring); | |
4712274c OM |
1431 | |
1432 | return 0; | |
1433 | } | |
1434 | ||
7deb4d39 | 1435 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1436 | u32 mode) |
4712274c | 1437 | { |
7e37f889 | 1438 | struct intel_ring *ring = request->ring; |
b5321f30 | 1439 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1440 | u32 scratch_addr = |
1441 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1442 | bool vf_flush_wa = false, dc_flush_wa = false; |
4712274c OM |
1443 | u32 flags = 0; |
1444 | int ret; | |
0b2d0934 | 1445 | int len; |
4712274c OM |
1446 | |
1447 | flags |= PIPE_CONTROL_CS_STALL; | |
1448 | ||
7c9cf4e3 | 1449 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1450 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1451 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1452 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1453 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1454 | } |
1455 | ||
7c9cf4e3 | 1456 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1457 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1458 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1459 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1460 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1461 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1462 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1463 | flags |= PIPE_CONTROL_QW_WRITE; | |
1464 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1465 | |
1a5a9ce7 BW |
1466 | /* |
1467 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1468 | * pipe control. | |
1469 | */ | |
c033666a | 1470 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1471 | vf_flush_wa = true; |
0b2d0934 MK |
1472 | |
1473 | /* WaForGAMHang:kbl */ | |
1474 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1475 | dc_flush_wa = true; | |
1a5a9ce7 | 1476 | } |
9647ff36 | 1477 | |
0b2d0934 MK |
1478 | len = 6; |
1479 | ||
1480 | if (vf_flush_wa) | |
1481 | len += 6; | |
1482 | ||
1483 | if (dc_flush_wa) | |
1484 | len += 12; | |
1485 | ||
1486 | ret = intel_ring_begin(request, len); | |
4712274c OM |
1487 | if (ret) |
1488 | return ret; | |
1489 | ||
9647ff36 | 1490 | if (vf_flush_wa) { |
b5321f30 CW |
1491 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1492 | intel_ring_emit(ring, 0); | |
1493 | intel_ring_emit(ring, 0); | |
1494 | intel_ring_emit(ring, 0); | |
1495 | intel_ring_emit(ring, 0); | |
1496 | intel_ring_emit(ring, 0); | |
9647ff36 ID |
1497 | } |
1498 | ||
0b2d0934 | 1499 | if (dc_flush_wa) { |
b5321f30 CW |
1500 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1501 | intel_ring_emit(ring, PIPE_CONTROL_DC_FLUSH_ENABLE); | |
1502 | intel_ring_emit(ring, 0); | |
1503 | intel_ring_emit(ring, 0); | |
1504 | intel_ring_emit(ring, 0); | |
1505 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1506 | } |
1507 | ||
b5321f30 CW |
1508 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1509 | intel_ring_emit(ring, flags); | |
1510 | intel_ring_emit(ring, scratch_addr); | |
1511 | intel_ring_emit(ring, 0); | |
1512 | intel_ring_emit(ring, 0); | |
1513 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1514 | |
1515 | if (dc_flush_wa) { | |
b5321f30 CW |
1516 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1517 | intel_ring_emit(ring, PIPE_CONTROL_CS_STALL); | |
1518 | intel_ring_emit(ring, 0); | |
1519 | intel_ring_emit(ring, 0); | |
1520 | intel_ring_emit(ring, 0); | |
1521 | intel_ring_emit(ring, 0); | |
0b2d0934 MK |
1522 | } |
1523 | ||
b5321f30 | 1524 | intel_ring_advance(ring); |
4712274c OM |
1525 | |
1526 | return 0; | |
1527 | } | |
1528 | ||
c04e0f3b | 1529 | static void bxt_a_seqno_barrier(struct intel_engine_cs *engine) |
319404df | 1530 | { |
319404df ID |
1531 | /* |
1532 | * On BXT A steppings there is a HW coherency issue whereby the | |
1533 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1534 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1535 | * clflushing the corresponding cacheline whenever the caller wants | |
1536 | * the coherency to be guaranteed. Note that this cacheline is known | |
1537 | * to be clean at this point, since we only write it in | |
1538 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1539 | * this clflush in practice becomes an invalidate operation. | |
1540 | */ | |
c04e0f3b | 1541 | intel_flush_status_page(engine, I915_GEM_HWS_INDEX); |
319404df ID |
1542 | } |
1543 | ||
7c17d377 CW |
1544 | /* |
1545 | * Reserve space for 2 NOOPs at the end of each request to be | |
1546 | * used as a workaround for not being allowed to do lite | |
1547 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1548 | */ | |
1549 | #define WA_TAIL_DWORDS 2 | |
1550 | ||
c4e76638 | 1551 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1552 | { |
7e37f889 | 1553 | struct intel_ring *ring = request->ring; |
4da46e1e OM |
1554 | int ret; |
1555 | ||
987046ad | 1556 | ret = intel_ring_begin(request, 6 + WA_TAIL_DWORDS); |
4da46e1e OM |
1557 | if (ret) |
1558 | return ret; | |
1559 | ||
7c17d377 CW |
1560 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1561 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1562 | |
b5321f30 CW |
1563 | intel_ring_emit(ring, (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW); |
1564 | intel_ring_emit(ring, | |
1565 | intel_hws_seqno_address(request->engine) | | |
1566 | MI_FLUSH_DW_USE_GTT); | |
1567 | intel_ring_emit(ring, 0); | |
1568 | intel_ring_emit(ring, request->fence.seqno); | |
1569 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1570 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1571 | return intel_logical_ring_advance(request); |
7c17d377 | 1572 | } |
4da46e1e | 1573 | |
7c17d377 CW |
1574 | static int gen8_emit_request_render(struct drm_i915_gem_request *request) |
1575 | { | |
7e37f889 | 1576 | struct intel_ring *ring = request->ring; |
7c17d377 | 1577 | int ret; |
53292cdb | 1578 | |
987046ad | 1579 | ret = intel_ring_begin(request, 8 + WA_TAIL_DWORDS); |
7c17d377 CW |
1580 | if (ret) |
1581 | return ret; | |
1582 | ||
ce81a65c MW |
1583 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1584 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1585 | ||
7c17d377 CW |
1586 | /* w/a for post sync ops following a GPGPU operation we |
1587 | * need a prior CS_STALL, which is emitted by the flush | |
1588 | * following the batch. | |
1589 | */ | |
b5321f30 CW |
1590 | intel_ring_emit(ring, GFX_OP_PIPE_CONTROL(6)); |
1591 | intel_ring_emit(ring, | |
1592 | (PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1593 | PIPE_CONTROL_CS_STALL | | |
1594 | PIPE_CONTROL_QW_WRITE)); | |
1595 | intel_ring_emit(ring, intel_hws_seqno_address(request->engine)); | |
1596 | intel_ring_emit(ring, 0); | |
1597 | intel_ring_emit(ring, i915_gem_request_get_seqno(request)); | |
ce81a65c | 1598 | /* We're thrashing one dword of HWS. */ |
b5321f30 CW |
1599 | intel_ring_emit(ring, 0); |
1600 | intel_ring_emit(ring, MI_USER_INTERRUPT); | |
1601 | intel_ring_emit(ring, MI_NOOP); | |
ddd66c51 | 1602 | return intel_logical_ring_advance(request); |
4da46e1e OM |
1603 | } |
1604 | ||
8753181e | 1605 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1606 | { |
1607 | int ret; | |
1608 | ||
e2be4faf | 1609 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1610 | if (ret) |
1611 | return ret; | |
1612 | ||
3bbaba0c PA |
1613 | ret = intel_rcs_context_init_mocs(req); |
1614 | /* | |
1615 | * Failing to program the MOCS is non-fatal.The system will not | |
1616 | * run at peak performance. So generate an error and carry on. | |
1617 | */ | |
1618 | if (ret) | |
1619 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1620 | ||
e40f9ee6 | 1621 | return i915_gem_render_state_init(req); |
e7778be1 TD |
1622 | } |
1623 | ||
73e4d07f OM |
1624 | /** |
1625 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1626 | * @engine: Engine Command Streamer. |
73e4d07f | 1627 | */ |
0bc40be8 | 1628 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1629 | { |
6402c330 | 1630 | struct drm_i915_private *dev_priv; |
9832b9da | 1631 | |
117897f4 | 1632 | if (!intel_engine_initialized(engine)) |
48d82387 OM |
1633 | return; |
1634 | ||
27af5eea TU |
1635 | /* |
1636 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1637 | * so this is just for documentation. | |
1638 | */ | |
1639 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1640 | tasklet_kill(&engine->irq_tasklet); | |
1641 | ||
c033666a | 1642 | dev_priv = engine->i915; |
6402c330 | 1643 | |
0bc40be8 | 1644 | if (engine->buffer) { |
0bc40be8 | 1645 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1646 | } |
48d82387 | 1647 | |
0bc40be8 TU |
1648 | if (engine->cleanup) |
1649 | engine->cleanup(engine); | |
48d82387 | 1650 | |
96a945aa | 1651 | intel_engine_cleanup_common(engine); |
688e6c72 | 1652 | |
57e88531 CW |
1653 | if (engine->status_page.vma) { |
1654 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1655 | engine->status_page.vma = NULL; | |
48d82387 | 1656 | } |
24f1d3cc | 1657 | intel_lr_context_unpin(dev_priv->kernel_context, engine); |
17ee950d | 1658 | |
0bc40be8 | 1659 | lrc_destroy_wa_ctx_obj(engine); |
c033666a | 1660 | engine->i915 = NULL; |
454afebd OM |
1661 | } |
1662 | ||
ddd66c51 CW |
1663 | void intel_execlists_enable_submission(struct drm_i915_private *dev_priv) |
1664 | { | |
1665 | struct intel_engine_cs *engine; | |
1666 | ||
1667 | for_each_engine(engine, dev_priv) | |
f4ea6bdd | 1668 | engine->submit_request = execlists_submit_request; |
ddd66c51 CW |
1669 | } |
1670 | ||
c9cacf93 | 1671 | static void |
e1382efb | 1672 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1673 | { |
1674 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1675 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1676 | engine->reset_hw = reset_common_ring; |
0bc40be8 | 1677 | engine->emit_flush = gen8_emit_flush; |
ddd66c51 | 1678 | engine->emit_request = gen8_emit_request; |
f4ea6bdd | 1679 | engine->submit_request = execlists_submit_request; |
ddd66c51 | 1680 | |
31bb59cc CW |
1681 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1682 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1683 | engine->emit_bb_start = gen8_emit_bb_start; |
1b7744e7 | 1684 | if (IS_BXT_REVID(engine->i915, 0, BXT_REVID_A1)) |
c04e0f3b | 1685 | engine->irq_seqno_barrier = bxt_a_seqno_barrier; |
c9cacf93 TU |
1686 | } |
1687 | ||
d9f3af96 | 1688 | static inline void |
c2c7f240 | 1689 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1690 | { |
c2c7f240 | 1691 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1692 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1693 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1694 | } |
1695 | ||
7d774cac | 1696 | static int |
bf3783e5 | 1697 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1698 | { |
57e88531 | 1699 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1700 | void *hws; |
04794adb TU |
1701 | |
1702 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1703 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1704 | if (IS_ERR(hws)) |
1705 | return PTR_ERR(hws); | |
57e88531 CW |
1706 | |
1707 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1708 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1709 | engine->status_page.vma = vma; |
7d774cac TU |
1710 | |
1711 | return 0; | |
04794adb TU |
1712 | } |
1713 | ||
bb45438f TU |
1714 | static void |
1715 | logical_ring_setup(struct intel_engine_cs *engine) | |
1716 | { | |
1717 | struct drm_i915_private *dev_priv = engine->i915; | |
1718 | enum forcewake_domains fw_domains; | |
1719 | ||
019bf277 TU |
1720 | intel_engine_setup_common(engine); |
1721 | ||
bb45438f TU |
1722 | /* Intentionally left blank. */ |
1723 | engine->buffer = NULL; | |
1724 | ||
1725 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1726 | RING_ELSP(engine), | |
1727 | FW_REG_WRITE); | |
1728 | ||
1729 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1730 | RING_CONTEXT_STATUS_PTR(engine), | |
1731 | FW_REG_READ | FW_REG_WRITE); | |
1732 | ||
1733 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1734 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1735 | FW_REG_READ); | |
1736 | ||
1737 | engine->fw_domains = fw_domains; | |
1738 | ||
bb45438f TU |
1739 | tasklet_init(&engine->irq_tasklet, |
1740 | intel_lrc_irq_handler, (unsigned long)engine); | |
1741 | ||
1742 | logical_ring_init_platform_invariants(engine); | |
1743 | logical_ring_default_vfuncs(engine); | |
1744 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1745 | } |
1746 | ||
a19d6ff2 TU |
1747 | static int |
1748 | logical_ring_init(struct intel_engine_cs *engine) | |
1749 | { | |
1750 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1751 | int ret; | |
1752 | ||
019bf277 | 1753 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1754 | if (ret) |
1755 | goto error; | |
1756 | ||
1757 | ret = execlists_context_deferred_alloc(dctx, engine); | |
1758 | if (ret) | |
1759 | goto error; | |
1760 | ||
1761 | /* As this is the default context, always pin it */ | |
1762 | ret = intel_lr_context_pin(dctx, engine); | |
1763 | if (ret) { | |
1764 | DRM_ERROR("Failed to pin context for %s: %d\n", | |
1765 | engine->name, ret); | |
1766 | goto error; | |
1767 | } | |
1768 | ||
1769 | /* And setup the hardware status page. */ | |
1770 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1771 | if (ret) { | |
1772 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1773 | goto error; | |
1774 | } | |
1775 | ||
1776 | return 0; | |
1777 | ||
1778 | error: | |
1779 | intel_logical_ring_cleanup(engine); | |
1780 | return ret; | |
1781 | } | |
1782 | ||
88d2ba2e | 1783 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1784 | { |
1785 | struct drm_i915_private *dev_priv = engine->i915; | |
1786 | int ret; | |
1787 | ||
bb45438f TU |
1788 | logical_ring_setup(engine); |
1789 | ||
a19d6ff2 TU |
1790 | if (HAS_L3_DPF(dev_priv)) |
1791 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1792 | ||
1793 | /* Override some for render ring. */ | |
1794 | if (INTEL_GEN(dev_priv) >= 9) | |
1795 | engine->init_hw = gen9_init_render_ring; | |
1796 | else | |
1797 | engine->init_hw = gen8_init_render_ring; | |
1798 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 TU |
1799 | engine->emit_flush = gen8_emit_flush_render; |
1800 | engine->emit_request = gen8_emit_request_render; | |
1801 | ||
56c0f1a7 | 1802 | ret = intel_engine_create_scratch(engine, 4096); |
a19d6ff2 TU |
1803 | if (ret) |
1804 | return ret; | |
1805 | ||
1806 | ret = intel_init_workaround_bb(engine); | |
1807 | if (ret) { | |
1808 | /* | |
1809 | * We continue even if we fail to initialize WA batch | |
1810 | * because we only expect rare glitches but nothing | |
1811 | * critical to prevent us from using GPU | |
1812 | */ | |
1813 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1814 | ret); | |
1815 | } | |
1816 | ||
1817 | ret = logical_ring_init(engine); | |
1818 | if (ret) { | |
1819 | lrc_destroy_wa_ctx_obj(engine); | |
1820 | } | |
1821 | ||
1822 | return ret; | |
1823 | } | |
1824 | ||
88d2ba2e | 1825 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1826 | { |
1827 | logical_ring_setup(engine); | |
1828 | ||
1829 | return logical_ring_init(engine); | |
454afebd OM |
1830 | } |
1831 | ||
0cea6502 | 1832 | static u32 |
c033666a | 1833 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1834 | { |
1835 | u32 rpcs = 0; | |
1836 | ||
1837 | /* | |
1838 | * No explicit RPCS request is needed to ensure full | |
1839 | * slice/subslice/EU enablement prior to Gen9. | |
1840 | */ | |
c033666a | 1841 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1842 | return 0; |
1843 | ||
1844 | /* | |
1845 | * Starting in Gen9, render power gating can leave | |
1846 | * slice/subslice/EU in a partially enabled state. We | |
1847 | * must make an explicit request through RPCS for full | |
1848 | * enablement. | |
1849 | */ | |
43b67998 | 1850 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1851 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1852 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1853 | GEN8_RPCS_S_CNT_SHIFT; |
1854 | rpcs |= GEN8_RPCS_ENABLE; | |
1855 | } | |
1856 | ||
43b67998 | 1857 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1858 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1859 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1860 | GEN8_RPCS_SS_CNT_SHIFT; |
1861 | rpcs |= GEN8_RPCS_ENABLE; | |
1862 | } | |
1863 | ||
43b67998 ID |
1864 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1865 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1866 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1867 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1868 | GEN8_RPCS_EU_MAX_SHIFT; |
1869 | rpcs |= GEN8_RPCS_ENABLE; | |
1870 | } | |
1871 | ||
1872 | return rpcs; | |
1873 | } | |
1874 | ||
0bc40be8 | 1875 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1876 | { |
1877 | u32 indirect_ctx_offset; | |
1878 | ||
c033666a | 1879 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1880 | default: |
c033666a | 1881 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1882 | /* fall through */ |
1883 | case 9: | |
1884 | indirect_ctx_offset = | |
1885 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1886 | break; | |
1887 | case 8: | |
1888 | indirect_ctx_offset = | |
1889 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1890 | break; | |
1891 | } | |
1892 | ||
1893 | return indirect_ctx_offset; | |
1894 | } | |
1895 | ||
8670d6f9 | 1896 | static int |
e2efd130 | 1897 | populate_lr_context(struct i915_gem_context *ctx, |
7d774cac | 1898 | struct drm_i915_gem_object *ctx_obj, |
0bc40be8 | 1899 | struct intel_engine_cs *engine, |
7e37f889 | 1900 | struct intel_ring *ring) |
8670d6f9 | 1901 | { |
c033666a | 1902 | struct drm_i915_private *dev_priv = ctx->i915; |
ae6c4806 | 1903 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
7d774cac TU |
1904 | void *vaddr; |
1905 | u32 *reg_state; | |
8670d6f9 OM |
1906 | int ret; |
1907 | ||
2d965536 TD |
1908 | if (!ppgtt) |
1909 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
1910 | ||
8670d6f9 OM |
1911 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
1912 | if (ret) { | |
1913 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1914 | return ret; | |
1915 | } | |
1916 | ||
d31d7cb1 | 1917 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); |
7d774cac TU |
1918 | if (IS_ERR(vaddr)) { |
1919 | ret = PTR_ERR(vaddr); | |
1920 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
8670d6f9 OM |
1921 | return ret; |
1922 | } | |
7d774cac | 1923 | ctx_obj->dirty = true; |
8670d6f9 OM |
1924 | |
1925 | /* The second page of the context object contains some fields which must | |
1926 | * be set up prior to the first execution. */ | |
7d774cac | 1927 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
8670d6f9 OM |
1928 | |
1929 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
1930 | * commands followed by (reg, value) pairs. The values we are setting here are | |
1931 | * only for the first context restore: on a subsequent save, the GPU will | |
1932 | * recreate this batchbuffer with new values (including all the missing | |
1933 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
0d925ea0 | 1934 | reg_state[CTX_LRI_HEADER_0] = |
0bc40be8 TU |
1935 | MI_LOAD_REGISTER_IMM(engine->id == RCS ? 14 : 11) | MI_LRI_FORCE_POSTED; |
1936 | ASSIGN_CTX_REG(reg_state, CTX_CONTEXT_CONTROL, | |
1937 | RING_CONTEXT_CONTROL(engine), | |
0d925ea0 VS |
1938 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
1939 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
c033666a | 1940 | (HAS_RESOURCE_STREAMER(dev_priv) ? |
99cf8ea1 | 1941 | CTX_CTRL_RS_CTX_ENABLE : 0))); |
0bc40be8 TU |
1942 | ASSIGN_CTX_REG(reg_state, CTX_RING_HEAD, RING_HEAD(engine->mmio_base), |
1943 | 0); | |
1944 | ASSIGN_CTX_REG(reg_state, CTX_RING_TAIL, RING_TAIL(engine->mmio_base), | |
1945 | 0); | |
7ba717cf TD |
1946 | /* Ring buffer start address is not known until the buffer is pinned. |
1947 | * It is written to the context image in execlists_update_context() | |
1948 | */ | |
0bc40be8 TU |
1949 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_START, |
1950 | RING_START(engine->mmio_base), 0); | |
1951 | ASSIGN_CTX_REG(reg_state, CTX_RING_BUFFER_CONTROL, | |
1952 | RING_CTL(engine->mmio_base), | |
7e37f889 | 1953 | ((ring->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID); |
0bc40be8 TU |
1954 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_U, |
1955 | RING_BBADDR_UDW(engine->mmio_base), 0); | |
1956 | ASSIGN_CTX_REG(reg_state, CTX_BB_HEAD_L, | |
1957 | RING_BBADDR(engine->mmio_base), 0); | |
1958 | ASSIGN_CTX_REG(reg_state, CTX_BB_STATE, | |
1959 | RING_BBSTATE(engine->mmio_base), | |
0d925ea0 | 1960 | RING_BB_PPGTT); |
0bc40be8 TU |
1961 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_U, |
1962 | RING_SBBADDR_UDW(engine->mmio_base), 0); | |
1963 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_HEAD_L, | |
1964 | RING_SBBADDR(engine->mmio_base), 0); | |
1965 | ASSIGN_CTX_REG(reg_state, CTX_SECOND_BB_STATE, | |
1966 | RING_SBBSTATE(engine->mmio_base), 0); | |
1967 | if (engine->id == RCS) { | |
1968 | ASSIGN_CTX_REG(reg_state, CTX_BB_PER_CTX_PTR, | |
1969 | RING_BB_PER_CTX_PTR(engine->mmio_base), 0); | |
1970 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX, | |
1971 | RING_INDIRECT_CTX(engine->mmio_base), 0); | |
1972 | ASSIGN_CTX_REG(reg_state, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1973 | RING_INDIRECT_CTX_OFFSET(engine->mmio_base), 0); | |
48bb74e4 | 1974 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1975 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1976 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d AS |
1977 | |
1978 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
1979 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
1980 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
1981 | ||
1982 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
0bc40be8 | 1983 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d AS |
1984 | |
1985 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
1986 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
1987 | 0x01; | |
1988 | } | |
8670d6f9 | 1989 | } |
0d925ea0 | 1990 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; |
0bc40be8 TU |
1991 | ASSIGN_CTX_REG(reg_state, CTX_CTX_TIMESTAMP, |
1992 | RING_CTX_TIMESTAMP(engine->mmio_base), 0); | |
0d925ea0 | 1993 | /* PDP values well be assigned later if needed */ |
0bc40be8 TU |
1994 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), |
1995 | 0); | |
1996 | ASSIGN_CTX_REG(reg_state, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), | |
1997 | 0); | |
1998 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), | |
1999 | 0); | |
2000 | ASSIGN_CTX_REG(reg_state, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), | |
2001 | 0); | |
2002 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), | |
2003 | 0); | |
2004 | ASSIGN_CTX_REG(reg_state, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), | |
2005 | 0); | |
2006 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), | |
2007 | 0); | |
2008 | ASSIGN_CTX_REG(reg_state, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), | |
2009 | 0); | |
d7b2633d | 2010 | |
2dba3239 MT |
2011 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2012 | /* 64b PPGTT (48bit canonical) | |
2013 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2014 | * other PDP Descriptors are ignored. | |
2015 | */ | |
2016 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2017 | } else { | |
2018 | /* 32b PPGTT | |
2019 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2020 | * With dynamic page allocation, PDPs may not be allocated at | |
2021 | * this point. Point the unallocated PDPs to the scratch page | |
2022 | */ | |
c6a2ac71 | 2023 | execlists_update_context_pdps(ppgtt, reg_state); |
2dba3239 MT |
2024 | } |
2025 | ||
0bc40be8 | 2026 | if (engine->id == RCS) { |
8670d6f9 | 2027 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); |
0d925ea0 | 2028 | ASSIGN_CTX_REG(reg_state, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, |
c033666a | 2029 | make_rpcs(dev_priv)); |
8670d6f9 OM |
2030 | } |
2031 | ||
7d774cac | 2032 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
2033 | |
2034 | return 0; | |
2035 | } | |
2036 | ||
c5d46ee2 DG |
2037 | /** |
2038 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 2039 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
2040 | * |
2041 | * Each engine may require a different amount of space for a context image, | |
2042 | * so when allocating (or copying) an image, this function can be used to | |
2043 | * find the right size for the specific engine. | |
2044 | * | |
2045 | * Return: size (in bytes) of an engine-specific context image | |
2046 | * | |
2047 | * Note: this size includes the HWSP, which is part of the context image | |
2048 | * in LRC mode, but does not include the "shared data page" used with | |
2049 | * GuC submission. The caller should account for this if using the GuC. | |
2050 | */ | |
0bc40be8 | 2051 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
2052 | { |
2053 | int ret = 0; | |
2054 | ||
c033666a | 2055 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 2056 | |
0bc40be8 | 2057 | switch (engine->id) { |
8c857917 | 2058 | case RCS: |
c033666a | 2059 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
2060 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
2061 | else | |
2062 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2063 | break; |
2064 | case VCS: | |
2065 | case BCS: | |
2066 | case VECS: | |
2067 | case VCS2: | |
2068 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2069 | break; | |
2070 | } | |
2071 | ||
2072 | return ret; | |
ede7d42b OM |
2073 | } |
2074 | ||
e2efd130 | 2075 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 2076 | struct intel_engine_cs *engine) |
ede7d42b | 2077 | { |
8c857917 | 2078 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 2079 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 2080 | struct i915_vma *vma; |
8c857917 | 2081 | uint32_t context_size; |
7e37f889 | 2082 | struct intel_ring *ring; |
8c857917 OM |
2083 | int ret; |
2084 | ||
9021ad03 | 2085 | WARN_ON(ce->state); |
ede7d42b | 2086 | |
0bc40be8 | 2087 | context_size = round_up(intel_lr_context_size(engine), 4096); |
8c857917 | 2088 | |
d1675198 AD |
2089 | /* One extra page as the sharing data between driver and GuC */ |
2090 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2091 | ||
91c8a326 | 2092 | ctx_obj = i915_gem_object_create(&ctx->i915->drm, context_size); |
fe3db79b | 2093 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2094 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2095 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2096 | } |
2097 | ||
bf3783e5 CW |
2098 | vma = i915_vma_create(ctx_obj, &ctx->i915->ggtt.base, NULL); |
2099 | if (IS_ERR(vma)) { | |
2100 | ret = PTR_ERR(vma); | |
2101 | goto error_deref_obj; | |
2102 | } | |
2103 | ||
7e37f889 | 2104 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2105 | if (IS_ERR(ring)) { |
2106 | ret = PTR_ERR(ring); | |
e84fe803 | 2107 | goto error_deref_obj; |
8670d6f9 OM |
2108 | } |
2109 | ||
dca33ecc | 2110 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2111 | if (ret) { |
2112 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2113 | goto error_ring_free; |
84c2377f OM |
2114 | } |
2115 | ||
dca33ecc | 2116 | ce->ring = ring; |
bf3783e5 | 2117 | ce->state = vma; |
9021ad03 | 2118 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2119 | |
2120 | return 0; | |
8670d6f9 | 2121 | |
dca33ecc | 2122 | error_ring_free: |
7e37f889 | 2123 | intel_ring_free(ring); |
e84fe803 | 2124 | error_deref_obj: |
f8c417cd | 2125 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2126 | return ret; |
ede7d42b | 2127 | } |
3e5b6f05 | 2128 | |
821ed7df | 2129 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2130 | { |
821ed7df | 2131 | struct i915_gem_context *ctx = dev_priv->kernel_context; |
e2f80391 | 2132 | struct intel_engine_cs *engine; |
3e5b6f05 | 2133 | |
b4ac5afc | 2134 | for_each_engine(engine, dev_priv) { |
9021ad03 | 2135 | struct intel_context *ce = &ctx->engine[engine->id]; |
7d774cac | 2136 | void *vaddr; |
3e5b6f05 | 2137 | uint32_t *reg_state; |
3e5b6f05 | 2138 | |
bf3783e5 | 2139 | if (!ce->state) |
3e5b6f05 TD |
2140 | continue; |
2141 | ||
bf3783e5 | 2142 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac | 2143 | if (WARN_ON(IS_ERR(vaddr))) |
3e5b6f05 | 2144 | continue; |
7d774cac TU |
2145 | |
2146 | reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; | |
3e5b6f05 TD |
2147 | |
2148 | reg_state[CTX_RING_HEAD+1] = 0; | |
2149 | reg_state[CTX_RING_TAIL+1] = 0; | |
2150 | ||
bf3783e5 CW |
2151 | ce->state->obj->dirty = true; |
2152 | i915_gem_object_unpin_map(ce->state->obj); | |
3e5b6f05 | 2153 | |
dca33ecc CW |
2154 | ce->ring->head = 0; |
2155 | ce->ring->tail = 0; | |
3e5b6f05 TD |
2156 | } |
2157 | } |