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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
468c6816 | 141 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
142 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
143 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
144 | ||
e981e7b1 TD |
145 | #define RING_EXECLIST_QFULL (1 << 0x2) |
146 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
147 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
148 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
149 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
150 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
151 | ||
152 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
153 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
154 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
155 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
156 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
157 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 158 | |
70c2a24d CW |
159 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
160 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
161 | GEN8_CTX_STATUS_PREEMPTED | \ | |
162 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
163 | ||
8670d6f9 OM |
164 | #define CTX_LRI_HEADER_0 0x01 |
165 | #define CTX_CONTEXT_CONTROL 0x02 | |
166 | #define CTX_RING_HEAD 0x04 | |
167 | #define CTX_RING_TAIL 0x06 | |
168 | #define CTX_RING_BUFFER_START 0x08 | |
169 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
170 | #define CTX_BB_HEAD_U 0x0c | |
171 | #define CTX_BB_HEAD_L 0x0e | |
172 | #define CTX_BB_STATE 0x10 | |
173 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
174 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
175 | #define CTX_SECOND_BB_STATE 0x16 | |
176 | #define CTX_BB_PER_CTX_PTR 0x18 | |
177 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
178 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
179 | #define CTX_LRI_HEADER_1 0x21 | |
180 | #define CTX_CTX_TIMESTAMP 0x22 | |
181 | #define CTX_PDP3_UDW 0x24 | |
182 | #define CTX_PDP3_LDW 0x26 | |
183 | #define CTX_PDP2_UDW 0x28 | |
184 | #define CTX_PDP2_LDW 0x2a | |
185 | #define CTX_PDP1_UDW 0x2c | |
186 | #define CTX_PDP1_LDW 0x2e | |
187 | #define CTX_PDP0_UDW 0x30 | |
188 | #define CTX_PDP0_LDW 0x32 | |
189 | #define CTX_LRI_HEADER_2 0x41 | |
190 | #define CTX_R_PWR_CLK_STATE 0x42 | |
191 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
192 | ||
56e51bf0 | 193 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 194 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
195 | (reg_state)[(pos)+1] = (val); \ |
196 | } while (0) | |
197 | ||
198 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 199 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
200 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
201 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 202 | } while (0) |
e5815a2e | 203 | |
9244a817 | 204 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
205 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
206 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 207 | } while (0) |
2dba3239 | 208 | |
71562919 MT |
209 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
210 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 211 | |
0e93cdd4 CW |
212 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
213 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
214 | ||
a3aabe86 CW |
215 | #define WA_TAIL_DWORDS 2 |
216 | ||
e2efd130 | 217 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 218 | struct intel_engine_cs *engine); |
a3aabe86 CW |
219 | static void execlists_init_reg_state(u32 *reg_state, |
220 | struct i915_gem_context *ctx, | |
221 | struct intel_engine_cs *engine, | |
222 | struct intel_ring *ring); | |
7ba717cf | 223 | |
73e4d07f OM |
224 | /** |
225 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 226 | * @dev_priv: i915 device private |
73e4d07f OM |
227 | * @enable_execlists: value of i915.enable_execlists module parameter. |
228 | * | |
229 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 230 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
231 | * |
232 | * Return: 1 if Execlists is supported and has to be enabled. | |
233 | */ | |
c033666a | 234 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 235 | { |
a0bd6c31 ZL |
236 | /* On platforms with execlist available, vGPU will only |
237 | * support execlist mode, no ring buffer mode. | |
238 | */ | |
c033666a | 239 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
240 | return 1; |
241 | ||
c033666a | 242 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
243 | return 1; |
244 | ||
127f1003 OM |
245 | if (enable_execlists == 0) |
246 | return 0; | |
247 | ||
5a21b665 DV |
248 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
249 | USES_PPGTT(dev_priv) && | |
250 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
251 | return 1; |
252 | ||
253 | return 0; | |
254 | } | |
ede7d42b | 255 | |
73e4d07f | 256 | /** |
ca82580c TU |
257 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
258 | * descriptor for a pinned context | |
ca82580c | 259 | * @ctx: Context to work on |
9021ad03 | 260 | * @engine: Engine the descriptor will be used with |
73e4d07f | 261 | * |
ca82580c TU |
262 | * The context descriptor encodes various attributes of a context, |
263 | * including its GTT address and some flags. Because it's fairly | |
264 | * expensive to calculate, we'll just do it once and cache the result, | |
265 | * which remains valid until the context is unpinned. | |
266 | * | |
6e5248b5 DV |
267 | * This is what a descriptor looks like, from LSB to MSB:: |
268 | * | |
2355cf08 | 269 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
270 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
271 | * bits 32-52: ctx ID, a globally unique tag | |
272 | * bits 53-54: mbz, reserved for use by hardware | |
273 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 274 | */ |
ca82580c | 275 | static void |
e2efd130 | 276 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 277 | struct intel_engine_cs *engine) |
84b790f8 | 278 | { |
9021ad03 | 279 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 280 | u64 desc; |
84b790f8 | 281 | |
7069b144 | 282 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 283 | |
2355cf08 | 284 | desc = ctx->desc_template; /* bits 0-11 */ |
bde13ebd | 285 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 286 | /* bits 12-31 */ |
7069b144 | 287 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 288 | |
9021ad03 | 289 | ce->lrc_desc = desc; |
5af05fef MT |
290 | } |
291 | ||
e2efd130 | 292 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 293 | struct intel_engine_cs *engine) |
84b790f8 | 294 | { |
0bc40be8 | 295 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 296 | } |
203a571b | 297 | |
bbd6c47e CW |
298 | static inline void |
299 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
300 | unsigned long status) | |
84b790f8 | 301 | { |
bbd6c47e CW |
302 | /* |
303 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
304 | * The compiler should eliminate this function as dead-code. | |
305 | */ | |
306 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
307 | return; | |
6daccb0b | 308 | |
3fc03069 CD |
309 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
310 | status, rq); | |
84b790f8 BW |
311 | } |
312 | ||
c6a2ac71 TU |
313 | static void |
314 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
315 | { | |
316 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
317 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
318 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
319 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
320 | } | |
321 | ||
70c2a24d | 322 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 323 | { |
70c2a24d | 324 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
325 | struct i915_hw_ppgtt *ppgtt = |
326 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 327 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 328 | |
ed1501d4 | 329 | assert_ring_tail_valid(rq->ring, rq->tail); |
caddfe71 | 330 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
ae1250b9 | 331 | |
c6a2ac71 TU |
332 | /* True 32b PPGTT with dynamic page allocation: update PDP |
333 | * registers and point the unallocated PDPs to scratch page. | |
334 | * PML4 is allocated during ppgtt init, so this is not needed | |
335 | * in 48-bit mode. | |
336 | */ | |
949e8ab3 | 337 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 338 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
339 | |
340 | return ce->lrc_desc; | |
ae1250b9 OM |
341 | } |
342 | ||
70c2a24d | 343 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 344 | { |
70c2a24d CW |
345 | struct drm_i915_private *dev_priv = engine->i915; |
346 | struct execlist_port *port = engine->execlist_port; | |
bbd6c47e CW |
347 | u32 __iomem *elsp = |
348 | dev_priv->regs + i915_mmio_reg_offset(RING_ELSP(engine)); | |
349 | u64 desc[2]; | |
350 | ||
c816e605 | 351 | GEM_BUG_ON(port[0].count > 1); |
70c2a24d CW |
352 | if (!port[0].count) |
353 | execlists_context_status_change(port[0].request, | |
354 | INTEL_CONTEXT_SCHEDULE_IN); | |
355 | desc[0] = execlists_update_context(port[0].request); | |
ae9a043b | 356 | GEM_DEBUG_EXEC(port[0].context_id = upper_32_bits(desc[0])); |
816ee798 | 357 | port[0].count++; |
70c2a24d CW |
358 | |
359 | if (port[1].request) { | |
360 | GEM_BUG_ON(port[1].count); | |
361 | execlists_context_status_change(port[1].request, | |
362 | INTEL_CONTEXT_SCHEDULE_IN); | |
363 | desc[1] = execlists_update_context(port[1].request); | |
ae9a043b | 364 | GEM_DEBUG_EXEC(port[1].context_id = upper_32_bits(desc[1])); |
70c2a24d | 365 | port[1].count = 1; |
bbd6c47e CW |
366 | } else { |
367 | desc[1] = 0; | |
368 | } | |
70c2a24d | 369 | GEM_BUG_ON(desc[0] == desc[1]); |
bbd6c47e CW |
370 | |
371 | /* You must always write both descriptors in the order below. */ | |
372 | writel(upper_32_bits(desc[1]), elsp); | |
373 | writel(lower_32_bits(desc[1]), elsp); | |
374 | ||
375 | writel(upper_32_bits(desc[0]), elsp); | |
376 | /* The context is automatically loaded after the following */ | |
377 | writel(lower_32_bits(desc[0]), elsp); | |
378 | } | |
379 | ||
70c2a24d | 380 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 381 | { |
70c2a24d | 382 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 383 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 384 | } |
84b790f8 | 385 | |
70c2a24d CW |
386 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
387 | const struct i915_gem_context *next) | |
388 | { | |
389 | if (prev != next) | |
390 | return false; | |
26720ab9 | 391 | |
70c2a24d CW |
392 | if (ctx_single_port_submission(prev)) |
393 | return false; | |
26720ab9 | 394 | |
70c2a24d | 395 | return true; |
84b790f8 BW |
396 | } |
397 | ||
70c2a24d | 398 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 399 | { |
20311bd3 | 400 | struct drm_i915_gem_request *last; |
70c2a24d | 401 | struct execlist_port *port = engine->execlist_port; |
20311bd3 | 402 | struct rb_node *rb; |
70c2a24d CW |
403 | bool submit = false; |
404 | ||
6c943de6 CW |
405 | /* After execlist_first is updated, the tasklet will be rescheduled. |
406 | * | |
407 | * If we are currently running (inside the tasklet) and a third | |
408 | * party queues a request and so updates engine->execlist_first under | |
409 | * the spinlock (which we have elided), it will atomically set the | |
410 | * TASKLET_SCHED flag causing the us to be re-executed and pick up | |
411 | * the change in state (the update to TASKLET_SCHED incurs a memory | |
412 | * barrier making this cross-cpu checking safe). | |
413 | */ | |
414 | if (!READ_ONCE(engine->execlist_first)) | |
415 | return; | |
416 | ||
70c2a24d CW |
417 | last = port->request; |
418 | if (last) | |
419 | /* WaIdleLiteRestore:bdw,skl | |
420 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 421 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
422 | * for where we prepare the padding after the end of the |
423 | * request. | |
424 | */ | |
425 | last->tail = last->wa_tail; | |
e981e7b1 | 426 | |
70c2a24d | 427 | GEM_BUG_ON(port[1].request); |
acdd884a | 428 | |
70c2a24d CW |
429 | /* Hardware submission is through 2 ports. Conceptually each port |
430 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
431 | * static for a context, and unique to each, so we only execute | |
432 | * requests belonging to a single context from each ring. RING_HEAD | |
433 | * is maintained by the CS in the context image, it marks the place | |
434 | * where it got up to last time, and through RING_TAIL we tell the CS | |
435 | * where we want to execute up to this time. | |
436 | * | |
437 | * In this list the requests are in order of execution. Consecutive | |
438 | * requests from the same context are adjacent in the ringbuffer. We | |
439 | * can combine these requests into a single RING_TAIL update: | |
440 | * | |
441 | * RING_HEAD...req1...req2 | |
442 | * ^- RING_TAIL | |
443 | * since to execute req2 the CS must first execute req1. | |
444 | * | |
445 | * Our goal then is to point each port to the end of a consecutive | |
446 | * sequence of requests as being the most optimal (fewest wake ups | |
447 | * and context switches) submission. | |
779949f4 | 448 | */ |
acdd884a | 449 | |
9f7886d0 | 450 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 CW |
451 | rb = engine->execlist_first; |
452 | while (rb) { | |
453 | struct drm_i915_gem_request *cursor = | |
454 | rb_entry(rb, typeof(*cursor), priotree.node); | |
455 | ||
70c2a24d CW |
456 | /* Can we combine this request with the current port? It has to |
457 | * be the same context/ringbuffer and not have any exceptions | |
458 | * (e.g. GVT saying never to combine contexts). | |
c6a2ac71 | 459 | * |
70c2a24d CW |
460 | * If we can combine the requests, we can execute both by |
461 | * updating the RING_TAIL to point to the end of the second | |
462 | * request, and so we never need to tell the hardware about | |
463 | * the first. | |
53292cdb | 464 | */ |
70c2a24d CW |
465 | if (last && !can_merge_ctx(cursor->ctx, last->ctx)) { |
466 | /* If we are on the second port and cannot combine | |
467 | * this request with the last, then we are done. | |
468 | */ | |
469 | if (port != engine->execlist_port) | |
470 | break; | |
471 | ||
472 | /* If GVT overrides us we only ever submit port[0], | |
473 | * leaving port[1] empty. Note that we also have | |
474 | * to be careful that we don't queue the same | |
475 | * context (even though a different request) to | |
476 | * the second port. | |
477 | */ | |
d7ab992c MH |
478 | if (ctx_single_port_submission(last->ctx) || |
479 | ctx_single_port_submission(cursor->ctx)) | |
70c2a24d CW |
480 | break; |
481 | ||
482 | GEM_BUG_ON(last->ctx == cursor->ctx); | |
483 | ||
484 | i915_gem_request_assign(&port->request, last); | |
485 | port++; | |
486 | } | |
d55ac5bf | 487 | |
20311bd3 CW |
488 | rb = rb_next(rb); |
489 | rb_erase(&cursor->priotree.node, &engine->execlist_queue); | |
490 | RB_CLEAR_NODE(&cursor->priotree.node); | |
491 | cursor->priotree.priority = INT_MAX; | |
492 | ||
d55ac5bf | 493 | __i915_gem_request_submit(cursor); |
d7d96833 | 494 | trace_i915_gem_request_in(cursor, port - engine->execlist_port); |
70c2a24d CW |
495 | last = cursor; |
496 | submit = true; | |
497 | } | |
498 | if (submit) { | |
70c2a24d | 499 | i915_gem_request_assign(&port->request, last); |
20311bd3 | 500 | engine->execlist_first = rb; |
53292cdb | 501 | } |
9f7886d0 | 502 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 503 | |
70c2a24d CW |
504 | if (submit) |
505 | execlists_submit_ports(engine); | |
acdd884a MT |
506 | } |
507 | ||
70c2a24d | 508 | static bool execlists_elsp_idle(struct intel_engine_cs *engine) |
e981e7b1 | 509 | { |
70c2a24d | 510 | return !engine->execlist_port[0].request; |
e981e7b1 TD |
511 | } |
512 | ||
816ee798 | 513 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 514 | { |
816ee798 | 515 | const struct execlist_port *port = engine->execlist_port; |
91a41032 | 516 | |
816ee798 | 517 | return port[0].count + port[1].count < 2; |
91a41032 BW |
518 | } |
519 | ||
6e5248b5 | 520 | /* |
73e4d07f OM |
521 | * Check the unread Context Status Buffers and manage the submission of new |
522 | * contexts to the ELSP accordingly. | |
523 | */ | |
27af5eea | 524 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 525 | { |
27af5eea | 526 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 527 | struct execlist_port *port = engine->execlist_port; |
c033666a | 528 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 529 | |
3756685a | 530 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 531 | |
899f6204 CW |
532 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
533 | * imposing the cost of a locked atomic transaction when submitting a | |
534 | * new request (outside of the context-switch interrupt). | |
535 | */ | |
536 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
70c2a24d CW |
537 | u32 __iomem *csb_mmio = |
538 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
539 | u32 __iomem *buf = | |
540 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
4af0d727 | 541 | unsigned int head, tail; |
70c2a24d | 542 | |
2e70b8c6 CW |
543 | /* The write will be ordered by the uncached read (itself |
544 | * a memory barrier), so we do not need another in the form | |
545 | * of a locked instruction. The race between the interrupt | |
546 | * handler and the split test/clear is harmless as we order | |
547 | * our clear before the CSB read. If the interrupt arrived | |
548 | * first between the test and the clear, we read the updated | |
549 | * CSB and clear the bit. If the interrupt arrives as we read | |
550 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
551 | * is set and we do a new loop. | |
552 | */ | |
553 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
4af0d727 CW |
554 | head = readl(csb_mmio); |
555 | tail = GEN8_CSB_WRITE_PTR(head); | |
556 | head = GEN8_CSB_READ_PTR(head); | |
557 | while (head != tail) { | |
558 | unsigned int status; | |
559 | ||
560 | if (++head == GEN8_CSB_ENTRIES) | |
561 | head = 0; | |
70c2a24d | 562 | |
2ffe80aa CW |
563 | /* We are flying near dragons again. |
564 | * | |
565 | * We hold a reference to the request in execlist_port[] | |
566 | * but no more than that. We are operating in softirq | |
567 | * context and so cannot hold any mutex or sleep. That | |
568 | * prevents us stopping the requests we are processing | |
569 | * in port[] from being retired simultaneously (the | |
570 | * breadcrumb will be complete before we see the | |
571 | * context-switch). As we only hold the reference to the | |
572 | * request, any pointer chasing underneath the request | |
573 | * is subject to a potential use-after-free. Thus we | |
574 | * store all of the bookkeeping within port[] as | |
575 | * required, and avoid using unguarded pointers beneath | |
576 | * request itself. The same applies to the atomic | |
577 | * status notifier. | |
578 | */ | |
579 | ||
4af0d727 | 580 | status = readl(buf + 2 * head); |
70c2a24d CW |
581 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
582 | continue; | |
583 | ||
86aa7e76 | 584 | /* Check the context/desc id for this event matches */ |
4af0d727 | 585 | GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != |
ae9a043b | 586 | port[0].context_id); |
86aa7e76 | 587 | |
70c2a24d CW |
588 | GEM_BUG_ON(port[0].count == 0); |
589 | if (--port[0].count == 0) { | |
590 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); | |
fe9ae7a3 | 591 | GEM_BUG_ON(!i915_gem_request_completed(port[0].request)); |
70c2a24d CW |
592 | execlists_context_status_change(port[0].request, |
593 | INTEL_CONTEXT_SCHEDULE_OUT); | |
594 | ||
d7d96833 | 595 | trace_i915_gem_request_out(port[0].request); |
70c2a24d CW |
596 | i915_gem_request_put(port[0].request); |
597 | port[0] = port[1]; | |
598 | memset(&port[1], 0, sizeof(port[1])); | |
70c2a24d | 599 | } |
26720ab9 | 600 | |
70c2a24d CW |
601 | GEM_BUG_ON(port[0].count == 0 && |
602 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); | |
4af0d727 | 603 | } |
e1fee72c | 604 | |
4af0d727 | 605 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
70c2a24d | 606 | csb_mmio); |
e981e7b1 TD |
607 | } |
608 | ||
70c2a24d CW |
609 | if (execlists_elsp_ready(engine)) |
610 | execlists_dequeue(engine); | |
c6a2ac71 | 611 | |
70c2a24d | 612 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
613 | } |
614 | ||
20311bd3 CW |
615 | static bool insert_request(struct i915_priotree *pt, struct rb_root *root) |
616 | { | |
617 | struct rb_node **p, *rb; | |
618 | bool first = true; | |
619 | ||
620 | /* most positive priority is scheduled first, equal priorities fifo */ | |
621 | rb = NULL; | |
622 | p = &root->rb_node; | |
623 | while (*p) { | |
624 | struct i915_priotree *pos; | |
625 | ||
626 | rb = *p; | |
627 | pos = rb_entry(rb, typeof(*pos), node); | |
628 | if (pt->priority > pos->priority) { | |
629 | p = &rb->rb_left; | |
630 | } else { | |
631 | p = &rb->rb_right; | |
632 | first = false; | |
633 | } | |
634 | } | |
635 | rb_link_node(&pt->node, rb, p); | |
636 | rb_insert_color(&pt->node, root); | |
637 | ||
638 | return first; | |
639 | } | |
640 | ||
f4ea6bdd | 641 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 642 | { |
4a570db5 | 643 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 644 | unsigned long flags; |
acdd884a | 645 | |
663f71e7 CW |
646 | /* Will be called from irq-context when using foreign fences. */ |
647 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 648 | |
3833281a | 649 | if (insert_request(&request->priotree, &engine->execlist_queue)) { |
20311bd3 | 650 | engine->execlist_first = &request->priotree.node; |
48ea2554 | 651 | if (execlists_elsp_ready(engine)) |
3833281a CW |
652 | tasklet_hi_schedule(&engine->irq_tasklet); |
653 | } | |
acdd884a | 654 | |
663f71e7 | 655 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
656 | } |
657 | ||
20311bd3 CW |
658 | static struct intel_engine_cs * |
659 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
660 | { | |
a79a524e CW |
661 | struct intel_engine_cs *engine = |
662 | container_of(pt, struct drm_i915_gem_request, priotree)->engine; | |
663 | ||
664 | GEM_BUG_ON(!locked); | |
20311bd3 | 665 | |
20311bd3 | 666 | if (engine != locked) { |
a79a524e CW |
667 | spin_unlock(&locked->timeline->lock); |
668 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
669 | } |
670 | ||
671 | return engine; | |
672 | } | |
673 | ||
674 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
675 | { | |
a79a524e | 676 | struct intel_engine_cs *engine; |
20311bd3 CW |
677 | struct i915_dependency *dep, *p; |
678 | struct i915_dependency stack; | |
679 | LIST_HEAD(dfs); | |
680 | ||
681 | if (prio <= READ_ONCE(request->priotree.priority)) | |
682 | return; | |
683 | ||
70cd1476 CW |
684 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
685 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
686 | |
687 | stack.signaler = &request->priotree; | |
688 | list_add(&stack.dfs_link, &dfs); | |
689 | ||
690 | /* Recursively bump all dependent priorities to match the new request. | |
691 | * | |
692 | * A naive approach would be to use recursion: | |
693 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
694 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
695 | * update_priorities(dep->signal, prio) | |
696 | * insert_request(pt); | |
697 | * } | |
698 | * but that may have unlimited recursion depth and so runs a very | |
699 | * real risk of overunning the kernel stack. Instead, we build | |
700 | * a flat list of all dependencies starting with the current request. | |
701 | * As we walk the list of dependencies, we add all of its dependencies | |
702 | * to the end of the list (this may include an already visited | |
703 | * request) and continue to walk onwards onto the new dependencies. The | |
704 | * end result is a topological list of requests in reverse order, the | |
705 | * last element in the list is the request we must execute first. | |
706 | */ | |
707 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
708 | struct i915_priotree *pt = dep->signaler; | |
709 | ||
a79a524e CW |
710 | /* Within an engine, there can be no cycle, but we may |
711 | * refer to the same dependency chain multiple times | |
712 | * (redundant dependencies are not eliminated) and across | |
713 | * engines. | |
714 | */ | |
715 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
716 | GEM_BUG_ON(p->signaler->priority < pt->priority); | |
20311bd3 CW |
717 | if (prio > READ_ONCE(p->signaler->priority)) |
718 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 719 | } |
20311bd3 | 720 | |
0798cff4 | 721 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
722 | } |
723 | ||
a79a524e CW |
724 | engine = request->engine; |
725 | spin_lock_irq(&engine->timeline->lock); | |
726 | ||
20311bd3 CW |
727 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
728 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
729 | struct i915_priotree *pt = dep->signaler; | |
730 | ||
731 | INIT_LIST_HEAD(&dep->dfs_link); | |
732 | ||
733 | engine = pt_lock_engine(pt, engine); | |
734 | ||
735 | if (prio <= pt->priority) | |
736 | continue; | |
737 | ||
20311bd3 | 738 | pt->priority = prio; |
a79a524e CW |
739 | if (!RB_EMPTY_NODE(&pt->node)) { |
740 | rb_erase(&pt->node, &engine->execlist_queue); | |
741 | if (insert_request(pt, &engine->execlist_queue)) | |
742 | engine->execlist_first = &pt->node; | |
743 | } | |
20311bd3 CW |
744 | } |
745 | ||
a79a524e | 746 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
747 | |
748 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
749 | } | |
750 | ||
e8a9c58f CW |
751 | static int execlists_context_pin(struct intel_engine_cs *engine, |
752 | struct i915_gem_context *ctx) | |
dcb4c12a | 753 | { |
9021ad03 | 754 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 755 | unsigned int flags; |
7d774cac | 756 | void *vaddr; |
ca82580c | 757 | int ret; |
dcb4c12a | 758 | |
91c8a326 | 759 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 760 | |
9021ad03 | 761 | if (ce->pin_count++) |
24f1d3cc | 762 | return 0; |
a533b4ba | 763 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 764 | |
e8a9c58f CW |
765 | if (!ce->state) { |
766 | ret = execlists_context_deferred_alloc(ctx, engine); | |
767 | if (ret) | |
768 | goto err; | |
769 | } | |
56f6e0a7 | 770 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 771 | |
72b72ae4 | 772 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
773 | if (ctx->ggtt_offset_bias) |
774 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
775 | |
776 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 777 | if (ret) |
24f1d3cc | 778 | goto err; |
7ba717cf | 779 | |
bf3783e5 | 780 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
781 | if (IS_ERR(vaddr)) { |
782 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 783 | goto unpin_vma; |
82352e90 TU |
784 | } |
785 | ||
d3ef1af6 | 786 | ret = intel_ring_pin(ce->ring, ctx->ggtt_offset_bias); |
e84fe803 | 787 | if (ret) |
7d774cac | 788 | goto unpin_map; |
d1675198 | 789 | |
0bc40be8 | 790 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 791 | |
a3aabe86 CW |
792 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
793 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 794 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 795 | |
a4f5ea64 | 796 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 797 | |
9a6feaf0 | 798 | i915_gem_context_get(ctx); |
24f1d3cc | 799 | return 0; |
7ba717cf | 800 | |
7d774cac | 801 | unpin_map: |
bf3783e5 CW |
802 | i915_gem_object_unpin_map(ce->state->obj); |
803 | unpin_vma: | |
804 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 805 | err: |
9021ad03 | 806 | ce->pin_count = 0; |
e84fe803 NH |
807 | return ret; |
808 | } | |
809 | ||
e8a9c58f CW |
810 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
811 | struct i915_gem_context *ctx) | |
e84fe803 | 812 | { |
9021ad03 | 813 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 814 | |
91c8a326 | 815 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 816 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 817 | |
9021ad03 | 818 | if (--ce->pin_count) |
24f1d3cc | 819 | return; |
e84fe803 | 820 | |
aad29fbb | 821 | intel_ring_unpin(ce->ring); |
dcb4c12a | 822 | |
bf3783e5 CW |
823 | i915_gem_object_unpin_map(ce->state->obj); |
824 | i915_vma_unpin(ce->state); | |
321fe304 | 825 | |
9a6feaf0 | 826 | i915_gem_context_put(ctx); |
dcb4c12a OM |
827 | } |
828 | ||
f73e7399 | 829 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
830 | { |
831 | struct intel_engine_cs *engine = request->engine; | |
832 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 833 | u32 *cs; |
ef11c01d CW |
834 | int ret; |
835 | ||
e8a9c58f CW |
836 | GEM_BUG_ON(!ce->pin_count); |
837 | ||
ef11c01d CW |
838 | /* Flush enough space to reduce the likelihood of waiting after |
839 | * we start building the request - in which case we will just | |
840 | * have to repeat work. | |
841 | */ | |
842 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
843 | ||
e8a9c58f | 844 | GEM_BUG_ON(!ce->ring); |
ef11c01d CW |
845 | request->ring = ce->ring; |
846 | ||
ef11c01d CW |
847 | if (i915.enable_guc_submission) { |
848 | /* | |
849 | * Check that the GuC has space for the request before | |
850 | * going any further, as the i915_add_request() call | |
851 | * later on mustn't fail ... | |
852 | */ | |
853 | ret = i915_guc_wq_reserve(request); | |
854 | if (ret) | |
e8a9c58f | 855 | goto err; |
ef11c01d CW |
856 | } |
857 | ||
73dec95e TU |
858 | cs = intel_ring_begin(request, 0); |
859 | if (IS_ERR(cs)) { | |
860 | ret = PTR_ERR(cs); | |
ef11c01d | 861 | goto err_unreserve; |
73dec95e | 862 | } |
ef11c01d CW |
863 | |
864 | if (!ce->initialised) { | |
865 | ret = engine->init_context(request); | |
866 | if (ret) | |
867 | goto err_unreserve; | |
868 | ||
869 | ce->initialised = true; | |
870 | } | |
871 | ||
872 | /* Note that after this point, we have committed to using | |
873 | * this request as it is being used to both track the | |
874 | * state of engine initialisation and liveness of the | |
875 | * golden renderstate above. Think twice before you try | |
876 | * to cancel/unwind this request now. | |
877 | */ | |
878 | ||
879 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
880 | return 0; | |
881 | ||
882 | err_unreserve: | |
883 | if (i915.enable_guc_submission) | |
884 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 885 | err: |
ef11c01d CW |
886 | return ret; |
887 | } | |
888 | ||
9e000847 AS |
889 | /* |
890 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
891 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
892 | * but there is a slight complication as this is applied in WA batch where the | |
893 | * values are only initialized once so we cannot take register value at the | |
894 | * beginning and reuse it further; hence we save its value to memory, upload a | |
895 | * constant value with bit21 set and then we restore it back with the saved value. | |
896 | * To simplify the WA, a constant value is formed by using the default value | |
897 | * of this register. This shouldn't be a problem because we are only modifying | |
898 | * it for a short period and this batch in non-premptible. We can ofcourse | |
899 | * use additional instructions that read the actual value of the register | |
900 | * at that time and set our bit of interest but it makes the WA complicated. | |
901 | * | |
902 | * This WA is also required for Gen9 so extracting as a function avoids | |
903 | * code duplication. | |
904 | */ | |
097d4f1c TU |
905 | static u32 * |
906 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 907 | { |
097d4f1c TU |
908 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
909 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
910 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
911 | *batch++ = 0; | |
912 | ||
913 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
914 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
915 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
916 | ||
9f235dfa TU |
917 | batch = gen8_emit_pipe_control(batch, |
918 | PIPE_CONTROL_CS_STALL | | |
919 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
920 | 0); | |
097d4f1c TU |
921 | |
922 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
923 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
924 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
925 | *batch++ = 0; | |
926 | ||
927 | return batch; | |
17ee950d AS |
928 | } |
929 | ||
6e5248b5 DV |
930 | /* |
931 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
932 | * initialized at the beginning and shared across all contexts but this field | |
933 | * helps us to have multiple batches at different offsets and select them based | |
934 | * on a criteria. At the moment this batch always start at the beginning of the page | |
935 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 936 | * |
6e5248b5 DV |
937 | * The number of WA applied are not known at the beginning; we use this field |
938 | * to return the no of DWORDS written. | |
17ee950d | 939 | * |
6e5248b5 DV |
940 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
941 | * so it adds NOOPs as padding to make it cacheline aligned. | |
942 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
943 | * makes a complete batch buffer. | |
17ee950d | 944 | */ |
097d4f1c | 945 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 946 | { |
7ad00d1a | 947 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 948 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 949 | |
c82435bb | 950 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
951 | if (IS_BROADWELL(engine->i915)) |
952 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 953 | |
0160f055 AS |
954 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
955 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
956 | batch = gen8_emit_pipe_control(batch, |
957 | PIPE_CONTROL_FLUSH_L3 | | |
958 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
959 | PIPE_CONTROL_CS_STALL | | |
960 | PIPE_CONTROL_QW_WRITE, | |
961 | i915_ggtt_offset(engine->scratch) + | |
962 | 2 * CACHELINE_BYTES); | |
0160f055 | 963 | |
17ee950d | 964 | /* Pad to end of cacheline */ |
097d4f1c TU |
965 | while ((unsigned long)batch % CACHELINE_BYTES) |
966 | *batch++ = MI_NOOP; | |
17ee950d AS |
967 | |
968 | /* | |
969 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
970 | * execution depends on the length specified in terms of cache lines | |
971 | * in the register CTX_RCS_INDIRECT_CTX | |
972 | */ | |
973 | ||
097d4f1c | 974 | return batch; |
17ee950d AS |
975 | } |
976 | ||
6e5248b5 DV |
977 | /* |
978 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
979 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 980 | * |
6e5248b5 | 981 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
982 | * |
983 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
984 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
985 | */ | |
097d4f1c | 986 | static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 987 | { |
7ad00d1a | 988 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c TU |
989 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
990 | *batch++ = MI_BATCH_BUFFER_END; | |
17ee950d | 991 | |
097d4f1c | 992 | return batch; |
17ee950d AS |
993 | } |
994 | ||
097d4f1c | 995 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 996 | { |
9fb5026f | 997 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 998 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 999 | |
9fb5026f | 1000 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1001 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1002 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1003 | *batch++ = _MASKED_BIT_DISABLE( | |
1004 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1005 | *batch++ = MI_NOOP; | |
873e8171 | 1006 | |
066d4628 MK |
1007 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1008 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1009 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1010 | batch = gen8_emit_pipe_control(batch, |
1011 | PIPE_CONTROL_FLUSH_L3 | | |
1012 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1013 | PIPE_CONTROL_CS_STALL | | |
1014 | PIPE_CONTROL_QW_WRITE, | |
1015 | i915_ggtt_offset(engine->scratch) | |
1016 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1017 | } |
3485d99e | 1018 | |
9fb5026f | 1019 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1020 | if (HAS_POOLED_EU(engine->i915)) { |
1021 | /* | |
1022 | * EU pool configuration is setup along with golden context | |
1023 | * during context initialization. This value depends on | |
1024 | * device type (2x6 or 3x6) and needs to be updated based | |
1025 | * on which subslice is disabled especially for 2x6 | |
1026 | * devices, however it is safe to load default | |
1027 | * configuration of 3x6 device instead of masking off | |
1028 | * corresponding bits because HW ignores bits of a disabled | |
1029 | * subslice and drops down to appropriate config. Please | |
1030 | * see render_state_setup() in i915_gem_render_state.c for | |
1031 | * possible configurations, to avoid duplication they are | |
1032 | * not shown here again. | |
1033 | */ | |
097d4f1c TU |
1034 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1035 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1036 | *batch++ = 0x00777000; | |
1037 | *batch++ = 0; | |
1038 | *batch++ = 0; | |
1039 | *batch++ = 0; | |
3485d99e TG |
1040 | } |
1041 | ||
0504cffc | 1042 | /* Pad to end of cacheline */ |
097d4f1c TU |
1043 | while ((unsigned long)batch % CACHELINE_BYTES) |
1044 | *batch++ = MI_NOOP; | |
0504cffc | 1045 | |
097d4f1c | 1046 | return batch; |
0504cffc AS |
1047 | } |
1048 | ||
097d4f1c | 1049 | static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1050 | { |
097d4f1c | 1051 | *batch++ = MI_BATCH_BUFFER_END; |
0504cffc | 1052 | |
097d4f1c | 1053 | return batch; |
0504cffc AS |
1054 | } |
1055 | ||
097d4f1c TU |
1056 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1057 | ||
1058 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1059 | { |
48bb74e4 CW |
1060 | struct drm_i915_gem_object *obj; |
1061 | struct i915_vma *vma; | |
1062 | int err; | |
17ee950d | 1063 | |
097d4f1c | 1064 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1065 | if (IS_ERR(obj)) |
1066 | return PTR_ERR(obj); | |
17ee950d | 1067 | |
a01cb37a | 1068 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1069 | if (IS_ERR(vma)) { |
1070 | err = PTR_ERR(vma); | |
1071 | goto err; | |
17ee950d AS |
1072 | } |
1073 | ||
48bb74e4 CW |
1074 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1075 | if (err) | |
1076 | goto err; | |
1077 | ||
1078 | engine->wa_ctx.vma = vma; | |
17ee950d | 1079 | return 0; |
48bb74e4 CW |
1080 | |
1081 | err: | |
1082 | i915_gem_object_put(obj); | |
1083 | return err; | |
17ee950d AS |
1084 | } |
1085 | ||
097d4f1c | 1086 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1087 | { |
19880c4a | 1088 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1089 | } |
1090 | ||
097d4f1c TU |
1091 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1092 | ||
0bc40be8 | 1093 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1094 | { |
48bb74e4 | 1095 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1096 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1097 | &wa_ctx->per_ctx }; | |
1098 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1099 | struct page *page; |
097d4f1c TU |
1100 | void *batch, *batch_ptr; |
1101 | unsigned int i; | |
48bb74e4 | 1102 | int ret; |
17ee950d | 1103 | |
097d4f1c TU |
1104 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1105 | return -EINVAL; | |
17ee950d | 1106 | |
097d4f1c TU |
1107 | switch (INTEL_GEN(engine->i915)) { |
1108 | case 9: | |
1109 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
1110 | wa_bb_fn[1] = gen9_init_perctx_bb; | |
1111 | break; | |
1112 | case 8: | |
1113 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
1114 | wa_bb_fn[1] = gen8_init_perctx_bb; | |
1115 | break; | |
1116 | default: | |
1117 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1118 | return 0; |
0504cffc | 1119 | } |
5e60d790 | 1120 | |
097d4f1c | 1121 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1122 | if (ret) { |
1123 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1124 | return ret; | |
1125 | } | |
1126 | ||
48bb74e4 | 1127 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1128 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1129 | |
097d4f1c TU |
1130 | /* |
1131 | * Emit the two workaround batch buffers, recording the offset from the | |
1132 | * start of the workaround batch buffer object for each and their | |
1133 | * respective sizes. | |
1134 | */ | |
1135 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1136 | wa_bb[i]->offset = batch_ptr - batch; | |
1137 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1138 | ret = -EINVAL; | |
1139 | break; | |
1140 | } | |
1141 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
1142 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); | |
17ee950d AS |
1143 | } |
1144 | ||
097d4f1c TU |
1145 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1146 | ||
17ee950d AS |
1147 | kunmap_atomic(batch); |
1148 | if (ret) | |
097d4f1c | 1149 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1150 | |
1151 | return ret; | |
1152 | } | |
1153 | ||
22cc440e CW |
1154 | static u32 port_seqno(struct execlist_port *port) |
1155 | { | |
1156 | return port->request ? port->request->global_seqno : 0; | |
1157 | } | |
1158 | ||
0bc40be8 | 1159 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1160 | { |
c033666a | 1161 | struct drm_i915_private *dev_priv = engine->i915; |
821ed7df CW |
1162 | int ret; |
1163 | ||
1164 | ret = intel_mocs_init_engine(engine); | |
1165 | if (ret) | |
1166 | return ret; | |
9b1136d5 | 1167 | |
ad07dfcd | 1168 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1169 | intel_engine_init_hangcheck(engine); |
821ed7df | 1170 | |
0bc40be8 | 1171 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1172 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1173 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1174 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1175 | engine->status_page.ggtt_offset); | |
1176 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1177 | |
0bc40be8 | 1178 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1179 | |
c87d50cc | 1180 | /* After a GPU reset, we may have requests to replay */ |
f747026c | 1181 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
31de7350 | 1182 | if (!i915.enable_guc_submission && !execlists_elsp_idle(engine)) { |
22cc440e CW |
1183 | DRM_DEBUG_DRIVER("Restarting %s from requests [0x%x, 0x%x]\n", |
1184 | engine->name, | |
1185 | port_seqno(&engine->execlist_port[0]), | |
1186 | port_seqno(&engine->execlist_port[1])); | |
c87d50cc CW |
1187 | engine->execlist_port[0].count = 0; |
1188 | engine->execlist_port[1].count = 0; | |
821ed7df | 1189 | execlists_submit_ports(engine); |
c87d50cc | 1190 | } |
821ed7df CW |
1191 | |
1192 | return 0; | |
9b1136d5 OM |
1193 | } |
1194 | ||
0bc40be8 | 1195 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1196 | { |
c033666a | 1197 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1198 | int ret; |
1199 | ||
0bc40be8 | 1200 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1201 | if (ret) |
1202 | return ret; | |
1203 | ||
1204 | /* We need to disable the AsyncFlip performance optimisations in order | |
1205 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1206 | * programmed to '1' on all products. | |
1207 | * | |
1208 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1209 | */ | |
1210 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1211 | ||
9b1136d5 OM |
1212 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1213 | ||
0bc40be8 | 1214 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1215 | } |
1216 | ||
0bc40be8 | 1217 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1218 | { |
1219 | int ret; | |
1220 | ||
0bc40be8 | 1221 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1222 | if (ret) |
1223 | return ret; | |
1224 | ||
0bc40be8 | 1225 | return init_workarounds_ring(engine); |
82ef822e DL |
1226 | } |
1227 | ||
821ed7df CW |
1228 | static void reset_common_ring(struct intel_engine_cs *engine, |
1229 | struct drm_i915_gem_request *request) | |
1230 | { | |
821ed7df | 1231 | struct execlist_port *port = engine->execlist_port; |
c0dcb203 CW |
1232 | struct intel_context *ce; |
1233 | ||
1234 | /* If the request was innocent, we leave the request in the ELSP | |
1235 | * and will try to replay it on restarting. The context image may | |
1236 | * have been corrupted by the reset, in which case we may have | |
1237 | * to service a new GPU hang, but more likely we can continue on | |
1238 | * without impact. | |
1239 | * | |
1240 | * If the request was guilty, we presume the context is corrupt | |
1241 | * and have to at least restore the RING register in the context | |
1242 | * image back to the expected values to skip over the guilty request. | |
1243 | */ | |
1244 | if (!request || request->fence.error != -EIO) | |
1245 | return; | |
821ed7df | 1246 | |
a3aabe86 CW |
1247 | /* We want a simple context + ring to execute the breadcrumb update. |
1248 | * We cannot rely on the context being intact across the GPU hang, | |
1249 | * so clear it and rebuild just what we need for the breadcrumb. | |
1250 | * All pending requests for this context will be zapped, and any | |
1251 | * future request will be after userspace has had the opportunity | |
1252 | * to recreate its own state. | |
1253 | */ | |
c0dcb203 | 1254 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1255 | execlists_init_reg_state(ce->lrc_reg_state, |
1256 | request->ctx, engine, ce->ring); | |
1257 | ||
821ed7df | 1258 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1259 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1260 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1261 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1262 | |
821ed7df | 1263 | request->ring->head = request->postfix; |
821ed7df CW |
1264 | intel_ring_update_space(request->ring); |
1265 | ||
821ed7df | 1266 | /* Catch up with any missed context-switch interrupts */ |
821ed7df CW |
1267 | if (request->ctx != port[0].request->ctx) { |
1268 | i915_gem_request_put(port[0].request); | |
1269 | port[0] = port[1]; | |
1270 | memset(&port[1], 0, sizeof(port[1])); | |
1271 | } | |
1272 | ||
821ed7df | 1273 | GEM_BUG_ON(request->ctx != port[0].request->ctx); |
a3aabe86 CW |
1274 | |
1275 | /* Reset WaIdleLiteRestore:bdw,skl as well */ | |
450362d3 CW |
1276 | request->tail = |
1277 | intel_ring_wrap(request->ring, | |
1278 | request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); | |
ed1501d4 | 1279 | assert_ring_tail_valid(request->ring, request->tail); |
821ed7df CW |
1280 | } |
1281 | ||
7a01a0a2 MT |
1282 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1283 | { | |
1284 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1285 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1286 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1287 | u32 *cs; |
1288 | int i; | |
7a01a0a2 | 1289 | |
73dec95e TU |
1290 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1291 | if (IS_ERR(cs)) | |
1292 | return PTR_ERR(cs); | |
7a01a0a2 | 1293 | |
73dec95e | 1294 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1295 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1296 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1297 | ||
73dec95e TU |
1298 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1299 | *cs++ = upper_32_bits(pd_daddr); | |
1300 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1301 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1302 | } |
1303 | ||
73dec95e TU |
1304 | *cs++ = MI_NOOP; |
1305 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1306 | |
1307 | return 0; | |
1308 | } | |
1309 | ||
be795fc1 | 1310 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1311 | u64 offset, u32 len, |
54af56db | 1312 | const unsigned int flags) |
15648585 | 1313 | { |
73dec95e | 1314 | u32 *cs; |
15648585 OM |
1315 | int ret; |
1316 | ||
7a01a0a2 MT |
1317 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1318 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1319 | * but we can't. Force Restore would be a second option, but | |
1320 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1321 | * not idle). PML4 is allocated during ppgtt init so this is |
1322 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1323 | if (req->ctx->ppgtt && |
54af56db MK |
1324 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1325 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1326 | !intel_vgpu_active(req->i915)) { | |
1327 | ret = intel_logical_ring_emit_pdps(req); | |
1328 | if (ret) | |
1329 | return ret; | |
7a01a0a2 | 1330 | |
666796da | 1331 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1332 | } |
1333 | ||
73dec95e TU |
1334 | cs = intel_ring_begin(req, 4); |
1335 | if (IS_ERR(cs)) | |
1336 | return PTR_ERR(cs); | |
15648585 OM |
1337 | |
1338 | /* FIXME(BDW): Address space and security selectors. */ | |
54af56db MK |
1339 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1340 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1341 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1342 | *cs++ = lower_32_bits(offset); |
1343 | *cs++ = upper_32_bits(offset); | |
1344 | *cs++ = MI_NOOP; | |
1345 | intel_ring_advance(req, cs); | |
15648585 OM |
1346 | |
1347 | return 0; | |
1348 | } | |
1349 | ||
31bb59cc | 1350 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1351 | { |
c033666a | 1352 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1353 | I915_WRITE_IMR(engine, |
1354 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1355 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1356 | } |
1357 | ||
31bb59cc | 1358 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1359 | { |
c033666a | 1360 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1361 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1362 | } |
1363 | ||
7c9cf4e3 | 1364 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1365 | { |
73dec95e | 1366 | u32 cmd, *cs; |
4712274c | 1367 | |
73dec95e TU |
1368 | cs = intel_ring_begin(request, 4); |
1369 | if (IS_ERR(cs)) | |
1370 | return PTR_ERR(cs); | |
4712274c OM |
1371 | |
1372 | cmd = MI_FLUSH_DW + 1; | |
1373 | ||
f0a1fb10 CW |
1374 | /* We always require a command barrier so that subsequent |
1375 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1376 | * wrt the contents of the write cache being flushed to memory | |
1377 | * (and thus being coherent from the CPU). | |
1378 | */ | |
1379 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1380 | ||
7c9cf4e3 | 1381 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1382 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1383 | if (request->engine->id == VCS) |
f0a1fb10 | 1384 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1385 | } |
1386 | ||
73dec95e TU |
1387 | *cs++ = cmd; |
1388 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1389 | *cs++ = 0; /* upper addr */ | |
1390 | *cs++ = 0; /* value */ | |
1391 | intel_ring_advance(request, cs); | |
4712274c OM |
1392 | |
1393 | return 0; | |
1394 | } | |
1395 | ||
7deb4d39 | 1396 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1397 | u32 mode) |
4712274c | 1398 | { |
b5321f30 | 1399 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1400 | u32 scratch_addr = |
1401 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1402 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1403 | u32 *cs, flags = 0; |
0b2d0934 | 1404 | int len; |
4712274c OM |
1405 | |
1406 | flags |= PIPE_CONTROL_CS_STALL; | |
1407 | ||
7c9cf4e3 | 1408 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1409 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1410 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1411 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1412 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1413 | } |
1414 | ||
7c9cf4e3 | 1415 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1416 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1417 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1418 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1419 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1420 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1421 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1422 | flags |= PIPE_CONTROL_QW_WRITE; | |
1423 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1424 | |
1a5a9ce7 BW |
1425 | /* |
1426 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1427 | * pipe control. | |
1428 | */ | |
c033666a | 1429 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1430 | vf_flush_wa = true; |
0b2d0934 MK |
1431 | |
1432 | /* WaForGAMHang:kbl */ | |
1433 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1434 | dc_flush_wa = true; | |
1a5a9ce7 | 1435 | } |
9647ff36 | 1436 | |
0b2d0934 MK |
1437 | len = 6; |
1438 | ||
1439 | if (vf_flush_wa) | |
1440 | len += 6; | |
1441 | ||
1442 | if (dc_flush_wa) | |
1443 | len += 12; | |
1444 | ||
73dec95e TU |
1445 | cs = intel_ring_begin(request, len); |
1446 | if (IS_ERR(cs)) | |
1447 | return PTR_ERR(cs); | |
4712274c | 1448 | |
9f235dfa TU |
1449 | if (vf_flush_wa) |
1450 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1451 | |
9f235dfa TU |
1452 | if (dc_flush_wa) |
1453 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1454 | 0); | |
0b2d0934 | 1455 | |
9f235dfa | 1456 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1457 | |
9f235dfa TU |
1458 | if (dc_flush_wa) |
1459 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1460 | |
73dec95e | 1461 | intel_ring_advance(request, cs); |
4712274c OM |
1462 | |
1463 | return 0; | |
1464 | } | |
1465 | ||
7c17d377 CW |
1466 | /* |
1467 | * Reserve space for 2 NOOPs at the end of each request to be | |
1468 | * used as a workaround for not being allowed to do lite | |
1469 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1470 | */ | |
73dec95e | 1471 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1472 | { |
73dec95e TU |
1473 | *cs++ = MI_NOOP; |
1474 | *cs++ = MI_NOOP; | |
1475 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1476 | } |
4da46e1e | 1477 | |
73dec95e | 1478 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1479 | { |
7c17d377 CW |
1480 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1481 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1482 | |
73dec95e TU |
1483 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1484 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1485 | *cs++ = 0; | |
1486 | *cs++ = request->global_seqno; | |
1487 | *cs++ = MI_USER_INTERRUPT; | |
1488 | *cs++ = MI_NOOP; | |
1489 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1490 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1491 | |
73dec95e | 1492 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1493 | } |
4da46e1e | 1494 | |
98f29e8d CW |
1495 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1496 | ||
caddfe71 | 1497 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1498 | u32 *cs) |
7c17d377 | 1499 | { |
ce81a65c MW |
1500 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1501 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1502 | ||
7c17d377 CW |
1503 | /* w/a for post sync ops following a GPGPU operation we |
1504 | * need a prior CS_STALL, which is emitted by the flush | |
1505 | * following the batch. | |
1506 | */ | |
73dec95e TU |
1507 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1508 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1509 | PIPE_CONTROL_QW_WRITE; | |
1510 | *cs++ = intel_hws_seqno_address(request->engine); | |
1511 | *cs++ = 0; | |
1512 | *cs++ = request->global_seqno; | |
ce81a65c | 1513 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1514 | *cs++ = 0; |
1515 | *cs++ = MI_USER_INTERRUPT; | |
1516 | *cs++ = MI_NOOP; | |
1517 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1518 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1519 | |
73dec95e | 1520 | gen8_emit_wa_tail(request, cs); |
4da46e1e OM |
1521 | } |
1522 | ||
98f29e8d CW |
1523 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1524 | ||
8753181e | 1525 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1526 | { |
1527 | int ret; | |
1528 | ||
4ac9659e | 1529 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1530 | if (ret) |
1531 | return ret; | |
1532 | ||
3bbaba0c PA |
1533 | ret = intel_rcs_context_init_mocs(req); |
1534 | /* | |
1535 | * Failing to program the MOCS is non-fatal.The system will not | |
1536 | * run at peak performance. So generate an error and carry on. | |
1537 | */ | |
1538 | if (ret) | |
1539 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1540 | ||
4e50f082 | 1541 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1542 | } |
1543 | ||
73e4d07f OM |
1544 | /** |
1545 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1546 | * @engine: Engine Command Streamer. |
73e4d07f | 1547 | */ |
0bc40be8 | 1548 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1549 | { |
6402c330 | 1550 | struct drm_i915_private *dev_priv; |
9832b9da | 1551 | |
27af5eea TU |
1552 | /* |
1553 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1554 | * so this is just for documentation. | |
1555 | */ | |
1556 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1557 | tasklet_kill(&engine->irq_tasklet); | |
1558 | ||
c033666a | 1559 | dev_priv = engine->i915; |
6402c330 | 1560 | |
0bc40be8 | 1561 | if (engine->buffer) { |
0bc40be8 | 1562 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1563 | } |
48d82387 | 1564 | |
0bc40be8 TU |
1565 | if (engine->cleanup) |
1566 | engine->cleanup(engine); | |
48d82387 | 1567 | |
57e88531 CW |
1568 | if (engine->status_page.vma) { |
1569 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1570 | engine->status_page.vma = NULL; | |
48d82387 | 1571 | } |
e8a9c58f CW |
1572 | |
1573 | intel_engine_cleanup_common(engine); | |
17ee950d | 1574 | |
097d4f1c | 1575 | lrc_destroy_wa_ctx(engine); |
c033666a | 1576 | engine->i915 = NULL; |
3b3f1650 AG |
1577 | dev_priv->engine[engine->id] = NULL; |
1578 | kfree(engine); | |
454afebd OM |
1579 | } |
1580 | ||
ff44ad51 | 1581 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1582 | { |
ff44ad51 CW |
1583 | engine->submit_request = execlists_submit_request; |
1584 | engine->schedule = execlists_schedule; | |
c9203e82 | 1585 | engine->irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1586 | } |
1587 | ||
c9cacf93 | 1588 | static void |
e1382efb | 1589 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1590 | { |
1591 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1592 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1593 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1594 | |
1595 | engine->context_pin = execlists_context_pin; | |
1596 | engine->context_unpin = execlists_context_unpin; | |
1597 | ||
f73e7399 CW |
1598 | engine->request_alloc = execlists_request_alloc; |
1599 | ||
0bc40be8 | 1600 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1601 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1602 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1603 | |
1604 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1605 | |
31bb59cc CW |
1606 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1607 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1608 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1609 | } |
1610 | ||
d9f3af96 | 1611 | static inline void |
c2c7f240 | 1612 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1613 | { |
c2c7f240 | 1614 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1615 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1616 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1617 | } |
1618 | ||
7d774cac | 1619 | static int |
bf3783e5 | 1620 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1621 | { |
57e88531 | 1622 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1623 | void *hws; |
04794adb TU |
1624 | |
1625 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1626 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1627 | if (IS_ERR(hws)) |
1628 | return PTR_ERR(hws); | |
57e88531 CW |
1629 | |
1630 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1631 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1632 | engine->status_page.vma = vma; |
7d774cac TU |
1633 | |
1634 | return 0; | |
04794adb TU |
1635 | } |
1636 | ||
bb45438f TU |
1637 | static void |
1638 | logical_ring_setup(struct intel_engine_cs *engine) | |
1639 | { | |
1640 | struct drm_i915_private *dev_priv = engine->i915; | |
1641 | enum forcewake_domains fw_domains; | |
1642 | ||
019bf277 TU |
1643 | intel_engine_setup_common(engine); |
1644 | ||
bb45438f TU |
1645 | /* Intentionally left blank. */ |
1646 | engine->buffer = NULL; | |
1647 | ||
1648 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1649 | RING_ELSP(engine), | |
1650 | FW_REG_WRITE); | |
1651 | ||
1652 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1653 | RING_CONTEXT_STATUS_PTR(engine), | |
1654 | FW_REG_READ | FW_REG_WRITE); | |
1655 | ||
1656 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1657 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1658 | FW_REG_READ); | |
1659 | ||
1660 | engine->fw_domains = fw_domains; | |
1661 | ||
bb45438f TU |
1662 | tasklet_init(&engine->irq_tasklet, |
1663 | intel_lrc_irq_handler, (unsigned long)engine); | |
1664 | ||
bb45438f TU |
1665 | logical_ring_default_vfuncs(engine); |
1666 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1667 | } |
1668 | ||
a19d6ff2 TU |
1669 | static int |
1670 | logical_ring_init(struct intel_engine_cs *engine) | |
1671 | { | |
1672 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1673 | int ret; | |
1674 | ||
019bf277 | 1675 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1676 | if (ret) |
1677 | goto error; | |
1678 | ||
a19d6ff2 TU |
1679 | /* And setup the hardware status page. */ |
1680 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1681 | if (ret) { | |
1682 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1683 | goto error; | |
1684 | } | |
1685 | ||
1686 | return 0; | |
1687 | ||
1688 | error: | |
1689 | intel_logical_ring_cleanup(engine); | |
1690 | return ret; | |
1691 | } | |
1692 | ||
88d2ba2e | 1693 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1694 | { |
1695 | struct drm_i915_private *dev_priv = engine->i915; | |
1696 | int ret; | |
1697 | ||
bb45438f TU |
1698 | logical_ring_setup(engine); |
1699 | ||
a19d6ff2 TU |
1700 | if (HAS_L3_DPF(dev_priv)) |
1701 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1702 | ||
1703 | /* Override some for render ring. */ | |
1704 | if (INTEL_GEN(dev_priv) >= 9) | |
1705 | engine->init_hw = gen9_init_render_ring; | |
1706 | else | |
1707 | engine->init_hw = gen8_init_render_ring; | |
1708 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1709 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1710 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1711 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1712 | |
f51455d4 | 1713 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1714 | if (ret) |
1715 | return ret; | |
1716 | ||
1717 | ret = intel_init_workaround_bb(engine); | |
1718 | if (ret) { | |
1719 | /* | |
1720 | * We continue even if we fail to initialize WA batch | |
1721 | * because we only expect rare glitches but nothing | |
1722 | * critical to prevent us from using GPU | |
1723 | */ | |
1724 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1725 | ret); | |
1726 | } | |
1727 | ||
d038fc7e | 1728 | return logical_ring_init(engine); |
a19d6ff2 TU |
1729 | } |
1730 | ||
88d2ba2e | 1731 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1732 | { |
1733 | logical_ring_setup(engine); | |
1734 | ||
1735 | return logical_ring_init(engine); | |
454afebd OM |
1736 | } |
1737 | ||
0cea6502 | 1738 | static u32 |
c033666a | 1739 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1740 | { |
1741 | u32 rpcs = 0; | |
1742 | ||
1743 | /* | |
1744 | * No explicit RPCS request is needed to ensure full | |
1745 | * slice/subslice/EU enablement prior to Gen9. | |
1746 | */ | |
c033666a | 1747 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1748 | return 0; |
1749 | ||
1750 | /* | |
1751 | * Starting in Gen9, render power gating can leave | |
1752 | * slice/subslice/EU in a partially enabled state. We | |
1753 | * must make an explicit request through RPCS for full | |
1754 | * enablement. | |
1755 | */ | |
43b67998 | 1756 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1757 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1758 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1759 | GEN8_RPCS_S_CNT_SHIFT; |
1760 | rpcs |= GEN8_RPCS_ENABLE; | |
1761 | } | |
1762 | ||
43b67998 | 1763 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1764 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1765 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1766 | GEN8_RPCS_SS_CNT_SHIFT; |
1767 | rpcs |= GEN8_RPCS_ENABLE; | |
1768 | } | |
1769 | ||
43b67998 ID |
1770 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1771 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1772 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1773 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1774 | GEN8_RPCS_EU_MAX_SHIFT; |
1775 | rpcs |= GEN8_RPCS_ENABLE; | |
1776 | } | |
1777 | ||
1778 | return rpcs; | |
1779 | } | |
1780 | ||
0bc40be8 | 1781 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1782 | { |
1783 | u32 indirect_ctx_offset; | |
1784 | ||
c033666a | 1785 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1786 | default: |
c033666a | 1787 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1788 | /* fall through */ |
1789 | case 9: | |
1790 | indirect_ctx_offset = | |
1791 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1792 | break; | |
1793 | case 8: | |
1794 | indirect_ctx_offset = | |
1795 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1796 | break; | |
1797 | } | |
1798 | ||
1799 | return indirect_ctx_offset; | |
1800 | } | |
1801 | ||
56e51bf0 | 1802 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
1803 | struct i915_gem_context *ctx, |
1804 | struct intel_engine_cs *engine, | |
1805 | struct intel_ring *ring) | |
8670d6f9 | 1806 | { |
a3aabe86 CW |
1807 | struct drm_i915_private *dev_priv = engine->i915; |
1808 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
1809 | u32 base = engine->mmio_base; |
1810 | bool rcs = engine->id == RCS; | |
1811 | ||
1812 | /* A context is actually a big batch buffer with several | |
1813 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
1814 | * values we are setting here are only for the first context restore: | |
1815 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
1816 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
1817 | * we are not initializing here). | |
1818 | */ | |
1819 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
1820 | MI_LRI_FORCE_POSTED; | |
1821 | ||
1822 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
1823 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
1824 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
1825 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
1826 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
1827 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
1828 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
1829 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
1830 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
1831 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
1832 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
1833 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
1834 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
1835 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
1836 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
1837 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
1838 | if (rcs) { | |
1839 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
1840 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); | |
1841 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1842 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
8670d6f9 | 1843 | |
48bb74e4 | 1844 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1845 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1846 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 1847 | |
56e51bf0 | 1848 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
1849 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
1850 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 1851 | |
56e51bf0 | 1852 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 1853 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d | 1854 | |
56e51bf0 | 1855 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 1856 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 1857 | } |
8670d6f9 | 1858 | } |
56e51bf0 TU |
1859 | |
1860 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
1861 | ||
1862 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 1863 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
1864 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
1865 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
1866 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
1867 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
1868 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
1869 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
1870 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
1871 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 1872 | |
949e8ab3 | 1873 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
1874 | /* 64b PPGTT (48bit canonical) |
1875 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
1876 | * other PDP Descriptors are ignored. | |
1877 | */ | |
56e51bf0 | 1878 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
1879 | } |
1880 | ||
56e51bf0 TU |
1881 | if (rcs) { |
1882 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1883 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
1884 | make_rpcs(dev_priv)); | |
8670d6f9 | 1885 | } |
a3aabe86 CW |
1886 | } |
1887 | ||
1888 | static int | |
1889 | populate_lr_context(struct i915_gem_context *ctx, | |
1890 | struct drm_i915_gem_object *ctx_obj, | |
1891 | struct intel_engine_cs *engine, | |
1892 | struct intel_ring *ring) | |
1893 | { | |
1894 | void *vaddr; | |
1895 | int ret; | |
1896 | ||
1897 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
1898 | if (ret) { | |
1899 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1900 | return ret; | |
1901 | } | |
1902 | ||
1903 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
1904 | if (IS_ERR(vaddr)) { | |
1905 | ret = PTR_ERR(vaddr); | |
1906 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
1907 | return ret; | |
1908 | } | |
a4f5ea64 | 1909 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
1910 | |
1911 | /* The second page of the context object contains some fields which must | |
1912 | * be set up prior to the first execution. */ | |
1913 | ||
1914 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
1915 | ctx, engine, ring); | |
8670d6f9 | 1916 | |
7d774cac | 1917 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
1918 | |
1919 | return 0; | |
1920 | } | |
1921 | ||
c5d46ee2 DG |
1922 | /** |
1923 | * intel_lr_context_size() - return the size of the context for an engine | |
14bb2c11 | 1924 | * @engine: which engine to find the context size for |
c5d46ee2 DG |
1925 | * |
1926 | * Each engine may require a different amount of space for a context image, | |
1927 | * so when allocating (or copying) an image, this function can be used to | |
1928 | * find the right size for the specific engine. | |
1929 | * | |
1930 | * Return: size (in bytes) of an engine-specific context image | |
1931 | * | |
1932 | * Note: this size includes the HWSP, which is part of the context image | |
1933 | * in LRC mode, but does not include the "shared data page" used with | |
1934 | * GuC submission. The caller should account for this if using the GuC. | |
1935 | */ | |
0bc40be8 | 1936 | uint32_t intel_lr_context_size(struct intel_engine_cs *engine) |
8c857917 OM |
1937 | { |
1938 | int ret = 0; | |
1939 | ||
c033666a | 1940 | WARN_ON(INTEL_GEN(engine->i915) < 8); |
8c857917 | 1941 | |
0bc40be8 | 1942 | switch (engine->id) { |
8c857917 | 1943 | case RCS: |
c033666a | 1944 | if (INTEL_GEN(engine->i915) >= 9) |
468c6816 MN |
1945 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; |
1946 | else | |
1947 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
1948 | break; |
1949 | case VCS: | |
1950 | case BCS: | |
1951 | case VECS: | |
1952 | case VCS2: | |
1953 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
1954 | break; | |
1955 | } | |
1956 | ||
1957 | return ret; | |
ede7d42b OM |
1958 | } |
1959 | ||
e2efd130 | 1960 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 1961 | struct intel_engine_cs *engine) |
ede7d42b | 1962 | { |
8c857917 | 1963 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 1964 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 1965 | struct i915_vma *vma; |
8c857917 | 1966 | uint32_t context_size; |
7e37f889 | 1967 | struct intel_ring *ring; |
8c857917 OM |
1968 | int ret; |
1969 | ||
9021ad03 | 1970 | WARN_ON(ce->state); |
ede7d42b | 1971 | |
f51455d4 CW |
1972 | context_size = round_up(intel_lr_context_size(engine), |
1973 | I915_GTT_PAGE_SIZE); | |
8c857917 | 1974 | |
d1675198 AD |
1975 | /* One extra page as the sharing data between driver and GuC */ |
1976 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
1977 | ||
12d79d78 | 1978 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 1979 | if (IS_ERR(ctx_obj)) { |
3126a660 | 1980 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 1981 | return PTR_ERR(ctx_obj); |
8c857917 OM |
1982 | } |
1983 | ||
a01cb37a | 1984 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
1985 | if (IS_ERR(vma)) { |
1986 | ret = PTR_ERR(vma); | |
1987 | goto error_deref_obj; | |
1988 | } | |
1989 | ||
7e37f889 | 1990 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
1991 | if (IS_ERR(ring)) { |
1992 | ret = PTR_ERR(ring); | |
e84fe803 | 1993 | goto error_deref_obj; |
8670d6f9 OM |
1994 | } |
1995 | ||
dca33ecc | 1996 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
1997 | if (ret) { |
1998 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 1999 | goto error_ring_free; |
84c2377f OM |
2000 | } |
2001 | ||
dca33ecc | 2002 | ce->ring = ring; |
bf3783e5 | 2003 | ce->state = vma; |
9021ad03 | 2004 | ce->initialised = engine->init_context == NULL; |
ede7d42b OM |
2005 | |
2006 | return 0; | |
8670d6f9 | 2007 | |
dca33ecc | 2008 | error_ring_free: |
7e37f889 | 2009 | intel_ring_free(ring); |
e84fe803 | 2010 | error_deref_obj: |
f8c417cd | 2011 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2012 | return ret; |
ede7d42b | 2013 | } |
3e5b6f05 | 2014 | |
821ed7df | 2015 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2016 | { |
e2f80391 | 2017 | struct intel_engine_cs *engine; |
bafb2f7d | 2018 | struct i915_gem_context *ctx; |
3b3f1650 | 2019 | enum intel_engine_id id; |
bafb2f7d CW |
2020 | |
2021 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2022 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2023 | * that stored in context. As we only write new commands from | |
2024 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2025 | * starts reading from its RING_HEAD from the context, it may try to | |
2026 | * execute that junk and die. | |
2027 | * | |
2028 | * So to avoid that we reset the context images upon resume. For | |
2029 | * simplicity, we just zero everything out. | |
2030 | */ | |
2031 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
3b3f1650 | 2032 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2033 | struct intel_context *ce = &ctx->engine[engine->id]; |
2034 | u32 *reg; | |
3e5b6f05 | 2035 | |
bafb2f7d CW |
2036 | if (!ce->state) |
2037 | continue; | |
7d774cac | 2038 | |
bafb2f7d CW |
2039 | reg = i915_gem_object_pin_map(ce->state->obj, |
2040 | I915_MAP_WB); | |
2041 | if (WARN_ON(IS_ERR(reg))) | |
2042 | continue; | |
3e5b6f05 | 2043 | |
bafb2f7d CW |
2044 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2045 | reg[CTX_RING_HEAD+1] = 0; | |
2046 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2047 | |
a4f5ea64 | 2048 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2049 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2050 | |
bafb2f7d | 2051 | ce->ring->head = ce->ring->tail = 0; |
bafb2f7d CW |
2052 | intel_ring_update_space(ce->ring); |
2053 | } | |
3e5b6f05 TD |
2054 | } |
2055 | } |