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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 | 133 | */ |
27af5eea | 134 | #include <linux/interrupt.h> |
b20385f1 OM |
135 | |
136 | #include <drm/drmP.h> | |
137 | #include <drm/i915_drm.h> | |
138 | #include "i915_drv.h" | |
3bbaba0c | 139 | #include "intel_mocs.h" |
127f1003 | 140 | |
e981e7b1 TD |
141 | #define RING_EXECLIST_QFULL (1 << 0x2) |
142 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
143 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
144 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
145 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
146 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
147 | ||
148 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
149 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
150 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
151 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
152 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
153 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 | 154 | |
70c2a24d CW |
155 | #define GEN8_CTX_STATUS_COMPLETED_MASK \ |
156 | (GEN8_CTX_STATUS_ACTIVE_IDLE | \ | |
157 | GEN8_CTX_STATUS_PREEMPTED | \ | |
158 | GEN8_CTX_STATUS_ELEMENT_SWITCH) | |
159 | ||
8670d6f9 OM |
160 | #define CTX_LRI_HEADER_0 0x01 |
161 | #define CTX_CONTEXT_CONTROL 0x02 | |
162 | #define CTX_RING_HEAD 0x04 | |
163 | #define CTX_RING_TAIL 0x06 | |
164 | #define CTX_RING_BUFFER_START 0x08 | |
165 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
166 | #define CTX_BB_HEAD_U 0x0c | |
167 | #define CTX_BB_HEAD_L 0x0e | |
168 | #define CTX_BB_STATE 0x10 | |
169 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
170 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
171 | #define CTX_SECOND_BB_STATE 0x16 | |
172 | #define CTX_BB_PER_CTX_PTR 0x18 | |
173 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
174 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
175 | #define CTX_LRI_HEADER_1 0x21 | |
176 | #define CTX_CTX_TIMESTAMP 0x22 | |
177 | #define CTX_PDP3_UDW 0x24 | |
178 | #define CTX_PDP3_LDW 0x26 | |
179 | #define CTX_PDP2_UDW 0x28 | |
180 | #define CTX_PDP2_LDW 0x2a | |
181 | #define CTX_PDP1_UDW 0x2c | |
182 | #define CTX_PDP1_LDW 0x2e | |
183 | #define CTX_PDP0_UDW 0x30 | |
184 | #define CTX_PDP0_LDW 0x32 | |
185 | #define CTX_LRI_HEADER_2 0x41 | |
186 | #define CTX_R_PWR_CLK_STATE 0x42 | |
187 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
188 | ||
56e51bf0 | 189 | #define CTX_REG(reg_state, pos, reg, val) do { \ |
f0f59a00 | 190 | (reg_state)[(pos)+0] = i915_mmio_reg_offset(reg); \ |
0d925ea0 VS |
191 | (reg_state)[(pos)+1] = (val); \ |
192 | } while (0) | |
193 | ||
194 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) do { \ | |
d852c7bf | 195 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
196 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
197 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
9244a817 | 198 | } while (0) |
e5815a2e | 199 | |
9244a817 | 200 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) do { \ |
2dba3239 MT |
201 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ |
202 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
9244a817 | 203 | } while (0) |
2dba3239 | 204 | |
71562919 MT |
205 | #define GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
206 | #define GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x26 | |
84b790f8 | 207 | |
0e93cdd4 CW |
208 | /* Typical size of the average request (2 pipecontrols and a MI_BB) */ |
209 | #define EXECLISTS_REQUEST_SIZE 64 /* bytes */ | |
210 | ||
a3aabe86 CW |
211 | #define WA_TAIL_DWORDS 2 |
212 | ||
e2efd130 | 213 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 214 | struct intel_engine_cs *engine); |
a3aabe86 CW |
215 | static void execlists_init_reg_state(u32 *reg_state, |
216 | struct i915_gem_context *ctx, | |
217 | struct intel_engine_cs *engine, | |
218 | struct intel_ring *ring); | |
7ba717cf | 219 | |
73e4d07f OM |
220 | /** |
221 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
14bb2c11 | 222 | * @dev_priv: i915 device private |
73e4d07f OM |
223 | * @enable_execlists: value of i915.enable_execlists module parameter. |
224 | * | |
225 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 226 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
227 | * |
228 | * Return: 1 if Execlists is supported and has to be enabled. | |
229 | */ | |
c033666a | 230 | int intel_sanitize_enable_execlists(struct drm_i915_private *dev_priv, int enable_execlists) |
127f1003 | 231 | { |
a0bd6c31 ZL |
232 | /* On platforms with execlist available, vGPU will only |
233 | * support execlist mode, no ring buffer mode. | |
234 | */ | |
c033666a | 235 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && intel_vgpu_active(dev_priv)) |
a0bd6c31 ZL |
236 | return 1; |
237 | ||
c033666a | 238 | if (INTEL_GEN(dev_priv) >= 9) |
70ee45e1 DL |
239 | return 1; |
240 | ||
127f1003 OM |
241 | if (enable_execlists == 0) |
242 | return 0; | |
243 | ||
5a21b665 DV |
244 | if (HAS_LOGICAL_RING_CONTEXTS(dev_priv) && |
245 | USES_PPGTT(dev_priv) && | |
246 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
247 | return 1; |
248 | ||
249 | return 0; | |
250 | } | |
ede7d42b | 251 | |
73e4d07f | 252 | /** |
ca82580c TU |
253 | * intel_lr_context_descriptor_update() - calculate & cache the descriptor |
254 | * descriptor for a pinned context | |
ca82580c | 255 | * @ctx: Context to work on |
9021ad03 | 256 | * @engine: Engine the descriptor will be used with |
73e4d07f | 257 | * |
ca82580c TU |
258 | * The context descriptor encodes various attributes of a context, |
259 | * including its GTT address and some flags. Because it's fairly | |
260 | * expensive to calculate, we'll just do it once and cache the result, | |
261 | * which remains valid until the context is unpinned. | |
262 | * | |
6e5248b5 DV |
263 | * This is what a descriptor looks like, from LSB to MSB:: |
264 | * | |
2355cf08 | 265 | * bits 0-11: flags, GEN8_CTX_* (cached in ctx->desc_template) |
6e5248b5 DV |
266 | * bits 12-31: LRCA, GTT address of (the HWSP of) this context |
267 | * bits 32-52: ctx ID, a globally unique tag | |
268 | * bits 53-54: mbz, reserved for use by hardware | |
269 | * bits 55-63: group ID, currently unused and set to 0 | |
73e4d07f | 270 | */ |
ca82580c | 271 | static void |
e2efd130 | 272 | intel_lr_context_descriptor_update(struct i915_gem_context *ctx, |
0bc40be8 | 273 | struct intel_engine_cs *engine) |
84b790f8 | 274 | { |
9021ad03 | 275 | struct intel_context *ce = &ctx->engine[engine->id]; |
7069b144 | 276 | u64 desc; |
84b790f8 | 277 | |
7069b144 | 278 | BUILD_BUG_ON(MAX_CONTEXT_HW_ID > (1<<GEN8_CTX_ID_WIDTH)); |
84b790f8 | 279 | |
2355cf08 | 280 | desc = ctx->desc_template; /* bits 0-11 */ |
bde13ebd | 281 | desc |= i915_ggtt_offset(ce->state) + LRC_PPHWSP_PN * PAGE_SIZE; |
9021ad03 | 282 | /* bits 12-31 */ |
7069b144 | 283 | desc |= (u64)ctx->hw_id << GEN8_CTX_ID_SHIFT; /* bits 32-52 */ |
5af05fef | 284 | |
9021ad03 | 285 | ce->lrc_desc = desc; |
5af05fef MT |
286 | } |
287 | ||
e2efd130 | 288 | uint64_t intel_lr_context_descriptor(struct i915_gem_context *ctx, |
0bc40be8 | 289 | struct intel_engine_cs *engine) |
84b790f8 | 290 | { |
0bc40be8 | 291 | return ctx->engine[engine->id].lrc_desc; |
ca82580c | 292 | } |
203a571b | 293 | |
bbd6c47e CW |
294 | static inline void |
295 | execlists_context_status_change(struct drm_i915_gem_request *rq, | |
296 | unsigned long status) | |
84b790f8 | 297 | { |
bbd6c47e CW |
298 | /* |
299 | * Only used when GVT-g is enabled now. When GVT-g is disabled, | |
300 | * The compiler should eliminate this function as dead-code. | |
301 | */ | |
302 | if (!IS_ENABLED(CONFIG_DRM_I915_GVT)) | |
303 | return; | |
6daccb0b | 304 | |
3fc03069 CD |
305 | atomic_notifier_call_chain(&rq->engine->context_status_notifier, |
306 | status, rq); | |
84b790f8 BW |
307 | } |
308 | ||
c6a2ac71 TU |
309 | static void |
310 | execlists_update_context_pdps(struct i915_hw_ppgtt *ppgtt, u32 *reg_state) | |
311 | { | |
312 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
313 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
314 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
315 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
316 | } | |
317 | ||
70c2a24d | 318 | static u64 execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 319 | { |
70c2a24d | 320 | struct intel_context *ce = &rq->ctx->engine[rq->engine->id]; |
04da811b ZW |
321 | struct i915_hw_ppgtt *ppgtt = |
322 | rq->ctx->ppgtt ?: rq->i915->mm.aliasing_ppgtt; | |
70c2a24d | 323 | u32 *reg_state = ce->lrc_reg_state; |
ae1250b9 | 324 | |
e6ba9992 | 325 | reg_state[CTX_RING_TAIL+1] = intel_ring_set_tail(rq->ring, rq->tail); |
ae1250b9 | 326 | |
c6a2ac71 TU |
327 | /* True 32b PPGTT with dynamic page allocation: update PDP |
328 | * registers and point the unallocated PDPs to scratch page. | |
329 | * PML4 is allocated during ppgtt init, so this is not needed | |
330 | * in 48-bit mode. | |
331 | */ | |
949e8ab3 | 332 | if (ppgtt && !i915_vm_is_48bit(&ppgtt->base)) |
c6a2ac71 | 333 | execlists_update_context_pdps(ppgtt, reg_state); |
70c2a24d CW |
334 | |
335 | return ce->lrc_desc; | |
ae1250b9 OM |
336 | } |
337 | ||
70c2a24d | 338 | static void execlists_submit_ports(struct intel_engine_cs *engine) |
bbd6c47e | 339 | { |
70c2a24d | 340 | struct execlist_port *port = engine->execlist_port; |
bbd6c47e | 341 | u32 __iomem *elsp = |
77f0d0e9 CW |
342 | engine->i915->regs + i915_mmio_reg_offset(RING_ELSP(engine)); |
343 | unsigned int n; | |
bbd6c47e | 344 | |
77f0d0e9 CW |
345 | for (n = ARRAY_SIZE(engine->execlist_port); n--; ) { |
346 | struct drm_i915_gem_request *rq; | |
347 | unsigned int count; | |
348 | u64 desc; | |
349 | ||
350 | rq = port_unpack(&port[n], &count); | |
351 | if (rq) { | |
352 | GEM_BUG_ON(count > !n); | |
353 | if (!count++) | |
354 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_IN); | |
355 | port_set(&port[n], port_pack(rq, count)); | |
356 | desc = execlists_update_context(rq); | |
357 | GEM_DEBUG_EXEC(port[n].context_id = upper_32_bits(desc)); | |
358 | } else { | |
359 | GEM_BUG_ON(!n); | |
360 | desc = 0; | |
361 | } | |
bbd6c47e | 362 | |
77f0d0e9 CW |
363 | writel(upper_32_bits(desc), elsp); |
364 | writel(lower_32_bits(desc), elsp); | |
365 | } | |
bbd6c47e CW |
366 | } |
367 | ||
70c2a24d | 368 | static bool ctx_single_port_submission(const struct i915_gem_context *ctx) |
84b790f8 | 369 | { |
70c2a24d | 370 | return (IS_ENABLED(CONFIG_DRM_I915_GVT) && |
6095868a | 371 | i915_gem_context_force_single_submission(ctx)); |
70c2a24d | 372 | } |
84b790f8 | 373 | |
70c2a24d CW |
374 | static bool can_merge_ctx(const struct i915_gem_context *prev, |
375 | const struct i915_gem_context *next) | |
376 | { | |
377 | if (prev != next) | |
378 | return false; | |
26720ab9 | 379 | |
70c2a24d CW |
380 | if (ctx_single_port_submission(prev)) |
381 | return false; | |
26720ab9 | 382 | |
70c2a24d | 383 | return true; |
84b790f8 BW |
384 | } |
385 | ||
77f0d0e9 CW |
386 | static void port_assign(struct execlist_port *port, |
387 | struct drm_i915_gem_request *rq) | |
388 | { | |
389 | GEM_BUG_ON(rq == port_request(port)); | |
390 | ||
391 | if (port_isset(port)) | |
392 | i915_gem_request_put(port_request(port)); | |
393 | ||
394 | port_set(port, port_pack(i915_gem_request_get(rq), port_count(port))); | |
395 | } | |
396 | ||
70c2a24d | 397 | static void execlists_dequeue(struct intel_engine_cs *engine) |
acdd884a | 398 | { |
20311bd3 | 399 | struct drm_i915_gem_request *last; |
70c2a24d | 400 | struct execlist_port *port = engine->execlist_port; |
20311bd3 | 401 | struct rb_node *rb; |
70c2a24d CW |
402 | bool submit = false; |
403 | ||
77f0d0e9 | 404 | last = port_request(port); |
70c2a24d CW |
405 | if (last) |
406 | /* WaIdleLiteRestore:bdw,skl | |
407 | * Apply the wa NOOPs to prevent ring:HEAD == req:TAIL | |
9b81d556 | 408 | * as we resubmit the request. See gen8_emit_breadcrumb() |
70c2a24d CW |
409 | * for where we prepare the padding after the end of the |
410 | * request. | |
411 | */ | |
412 | last->tail = last->wa_tail; | |
e981e7b1 | 413 | |
77f0d0e9 | 414 | GEM_BUG_ON(port_isset(&port[1])); |
acdd884a | 415 | |
70c2a24d CW |
416 | /* Hardware submission is through 2 ports. Conceptually each port |
417 | * has a (RING_START, RING_HEAD, RING_TAIL) tuple. RING_START is | |
418 | * static for a context, and unique to each, so we only execute | |
419 | * requests belonging to a single context from each ring. RING_HEAD | |
420 | * is maintained by the CS in the context image, it marks the place | |
421 | * where it got up to last time, and through RING_TAIL we tell the CS | |
422 | * where we want to execute up to this time. | |
423 | * | |
424 | * In this list the requests are in order of execution. Consecutive | |
425 | * requests from the same context are adjacent in the ringbuffer. We | |
426 | * can combine these requests into a single RING_TAIL update: | |
427 | * | |
428 | * RING_HEAD...req1...req2 | |
429 | * ^- RING_TAIL | |
430 | * since to execute req2 the CS must first execute req1. | |
431 | * | |
432 | * Our goal then is to point each port to the end of a consecutive | |
433 | * sequence of requests as being the most optimal (fewest wake ups | |
434 | * and context switches) submission. | |
779949f4 | 435 | */ |
acdd884a | 436 | |
9f7886d0 | 437 | spin_lock_irq(&engine->timeline->lock); |
20311bd3 | 438 | rb = engine->execlist_first; |
6c067579 | 439 | GEM_BUG_ON(rb_first(&engine->execlist_queue) != rb); |
20311bd3 | 440 | while (rb) { |
6c067579 CW |
441 | struct i915_priolist *p = rb_entry(rb, typeof(*p), node); |
442 | struct drm_i915_gem_request *rq, *rn; | |
443 | ||
444 | list_for_each_entry_safe(rq, rn, &p->requests, priotree.link) { | |
445 | /* | |
446 | * Can we combine this request with the current port? | |
447 | * It has to be the same context/ringbuffer and not | |
448 | * have any exceptions (e.g. GVT saying never to | |
449 | * combine contexts). | |
450 | * | |
451 | * If we can combine the requests, we can execute both | |
452 | * by updating the RING_TAIL to point to the end of the | |
453 | * second request, and so we never need to tell the | |
454 | * hardware about the first. | |
70c2a24d | 455 | */ |
6c067579 CW |
456 | if (last && !can_merge_ctx(rq->ctx, last->ctx)) { |
457 | /* | |
458 | * If we are on the second port and cannot | |
459 | * combine this request with the last, then we | |
460 | * are done. | |
461 | */ | |
462 | if (port != engine->execlist_port) { | |
463 | __list_del_many(&p->requests, | |
464 | &rq->priotree.link); | |
465 | goto done; | |
466 | } | |
467 | ||
468 | /* | |
469 | * If GVT overrides us we only ever submit | |
470 | * port[0], leaving port[1] empty. Note that we | |
471 | * also have to be careful that we don't queue | |
472 | * the same context (even though a different | |
473 | * request) to the second port. | |
474 | */ | |
475 | if (ctx_single_port_submission(last->ctx) || | |
476 | ctx_single_port_submission(rq->ctx)) { | |
477 | __list_del_many(&p->requests, | |
478 | &rq->priotree.link); | |
479 | goto done; | |
480 | } | |
481 | ||
482 | GEM_BUG_ON(last->ctx == rq->ctx); | |
483 | ||
484 | if (submit) | |
485 | port_assign(port, last); | |
486 | port++; | |
487 | } | |
70c2a24d | 488 | |
6c067579 CW |
489 | INIT_LIST_HEAD(&rq->priotree.link); |
490 | rq->priotree.priority = INT_MAX; | |
70c2a24d | 491 | |
6c067579 CW |
492 | __i915_gem_request_submit(rq); |
493 | trace_i915_gem_request_in(rq, port_index(port, engine)); | |
494 | last = rq; | |
495 | submit = true; | |
70c2a24d | 496 | } |
d55ac5bf | 497 | |
20311bd3 | 498 | rb = rb_next(rb); |
6c067579 CW |
499 | rb_erase(&p->node, &engine->execlist_queue); |
500 | INIT_LIST_HEAD(&p->requests); | |
501 | if (p->priority != I915_PRIORITY_NORMAL) | |
c5cf9a91 | 502 | kmem_cache_free(engine->i915->priorities, p); |
70c2a24d | 503 | } |
6c067579 CW |
504 | done: |
505 | engine->execlist_first = rb; | |
506 | if (submit) | |
77f0d0e9 | 507 | port_assign(port, last); |
9f7886d0 | 508 | spin_unlock_irq(&engine->timeline->lock); |
53292cdb | 509 | |
70c2a24d CW |
510 | if (submit) |
511 | execlists_submit_ports(engine); | |
acdd884a MT |
512 | } |
513 | ||
816ee798 | 514 | static bool execlists_elsp_ready(const struct intel_engine_cs *engine) |
91a41032 | 515 | { |
816ee798 | 516 | const struct execlist_port *port = engine->execlist_port; |
91a41032 | 517 | |
77f0d0e9 | 518 | return port_count(&port[0]) + port_count(&port[1]) < 2; |
91a41032 BW |
519 | } |
520 | ||
6e5248b5 | 521 | /* |
73e4d07f OM |
522 | * Check the unread Context Status Buffers and manage the submission of new |
523 | * contexts to the ELSP accordingly. | |
524 | */ | |
27af5eea | 525 | static void intel_lrc_irq_handler(unsigned long data) |
e981e7b1 | 526 | { |
27af5eea | 527 | struct intel_engine_cs *engine = (struct intel_engine_cs *)data; |
70c2a24d | 528 | struct execlist_port *port = engine->execlist_port; |
c033666a | 529 | struct drm_i915_private *dev_priv = engine->i915; |
c6a2ac71 | 530 | |
48921260 CW |
531 | /* We can skip acquiring intel_runtime_pm_get() here as it was taken |
532 | * on our behalf by the request (see i915_gem_mark_busy()) and it will | |
533 | * not be relinquished until the device is idle (see | |
534 | * i915_gem_idle_work_handler()). As a precaution, we make sure | |
535 | * that all ELSP are drained i.e. we have processed the CSB, | |
536 | * before allowing ourselves to idle and calling intel_runtime_pm_put(). | |
537 | */ | |
538 | GEM_BUG_ON(!dev_priv->gt.awake); | |
539 | ||
3756685a | 540 | intel_uncore_forcewake_get(dev_priv, engine->fw_domains); |
c6a2ac71 | 541 | |
899f6204 CW |
542 | /* Prefer doing test_and_clear_bit() as a two stage operation to avoid |
543 | * imposing the cost of a locked atomic transaction when submitting a | |
544 | * new request (outside of the context-switch interrupt). | |
545 | */ | |
546 | while (test_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted)) { | |
70c2a24d CW |
547 | u32 __iomem *csb_mmio = |
548 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_PTR(engine)); | |
549 | u32 __iomem *buf = | |
550 | dev_priv->regs + i915_mmio_reg_offset(RING_CONTEXT_STATUS_BUF_LO(engine, 0)); | |
4af0d727 | 551 | unsigned int head, tail; |
70c2a24d | 552 | |
2e70b8c6 CW |
553 | /* The write will be ordered by the uncached read (itself |
554 | * a memory barrier), so we do not need another in the form | |
555 | * of a locked instruction. The race between the interrupt | |
556 | * handler and the split test/clear is harmless as we order | |
557 | * our clear before the CSB read. If the interrupt arrived | |
558 | * first between the test and the clear, we read the updated | |
559 | * CSB and clear the bit. If the interrupt arrives as we read | |
560 | * the CSB or later (i.e. after we had cleared the bit) the bit | |
561 | * is set and we do a new loop. | |
562 | */ | |
563 | __clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); | |
4af0d727 CW |
564 | head = readl(csb_mmio); |
565 | tail = GEN8_CSB_WRITE_PTR(head); | |
566 | head = GEN8_CSB_READ_PTR(head); | |
567 | while (head != tail) { | |
77f0d0e9 | 568 | struct drm_i915_gem_request *rq; |
4af0d727 | 569 | unsigned int status; |
77f0d0e9 | 570 | unsigned int count; |
4af0d727 CW |
571 | |
572 | if (++head == GEN8_CSB_ENTRIES) | |
573 | head = 0; | |
70c2a24d | 574 | |
2ffe80aa CW |
575 | /* We are flying near dragons again. |
576 | * | |
577 | * We hold a reference to the request in execlist_port[] | |
578 | * but no more than that. We are operating in softirq | |
579 | * context and so cannot hold any mutex or sleep. That | |
580 | * prevents us stopping the requests we are processing | |
581 | * in port[] from being retired simultaneously (the | |
582 | * breadcrumb will be complete before we see the | |
583 | * context-switch). As we only hold the reference to the | |
584 | * request, any pointer chasing underneath the request | |
585 | * is subject to a potential use-after-free. Thus we | |
586 | * store all of the bookkeeping within port[] as | |
587 | * required, and avoid using unguarded pointers beneath | |
588 | * request itself. The same applies to the atomic | |
589 | * status notifier. | |
590 | */ | |
591 | ||
4af0d727 | 592 | status = readl(buf + 2 * head); |
70c2a24d CW |
593 | if (!(status & GEN8_CTX_STATUS_COMPLETED_MASK)) |
594 | continue; | |
595 | ||
86aa7e76 | 596 | /* Check the context/desc id for this event matches */ |
4af0d727 | 597 | GEM_DEBUG_BUG_ON(readl(buf + 2 * head + 1) != |
77f0d0e9 | 598 | port->context_id); |
86aa7e76 | 599 | |
77f0d0e9 CW |
600 | rq = port_unpack(port, &count); |
601 | GEM_BUG_ON(count == 0); | |
602 | if (--count == 0) { | |
70c2a24d | 603 | GEM_BUG_ON(status & GEN8_CTX_STATUS_PREEMPTED); |
77f0d0e9 CW |
604 | GEM_BUG_ON(!i915_gem_request_completed(rq)); |
605 | execlists_context_status_change(rq, INTEL_CONTEXT_SCHEDULE_OUT); | |
606 | ||
607 | trace_i915_gem_request_out(rq); | |
608 | i915_gem_request_put(rq); | |
70c2a24d | 609 | |
70c2a24d CW |
610 | port[0] = port[1]; |
611 | memset(&port[1], 0, sizeof(port[1])); | |
77f0d0e9 CW |
612 | } else { |
613 | port_set(port, port_pack(rq, count)); | |
70c2a24d | 614 | } |
26720ab9 | 615 | |
77f0d0e9 CW |
616 | /* After the final element, the hw should be idle */ |
617 | GEM_BUG_ON(port_count(port) == 0 && | |
70c2a24d | 618 | !(status & GEN8_CTX_STATUS_ACTIVE_IDLE)); |
4af0d727 | 619 | } |
e1fee72c | 620 | |
4af0d727 | 621 | writel(_MASKED_FIELD(GEN8_CSB_READ_PTR_MASK, head << 8), |
70c2a24d | 622 | csb_mmio); |
e981e7b1 TD |
623 | } |
624 | ||
70c2a24d CW |
625 | if (execlists_elsp_ready(engine)) |
626 | execlists_dequeue(engine); | |
c6a2ac71 | 627 | |
70c2a24d | 628 | intel_uncore_forcewake_put(dev_priv, engine->fw_domains); |
e981e7b1 TD |
629 | } |
630 | ||
6c067579 CW |
631 | static bool |
632 | insert_request(struct intel_engine_cs *engine, | |
633 | struct i915_priotree *pt, | |
634 | int prio) | |
20311bd3 | 635 | { |
6c067579 CW |
636 | struct i915_priolist *p; |
637 | struct rb_node **parent, *rb; | |
20311bd3 CW |
638 | bool first = true; |
639 | ||
6c067579 CW |
640 | if (unlikely(engine->no_priolist)) |
641 | prio = I915_PRIORITY_NORMAL; | |
642 | ||
643 | find_priolist: | |
20311bd3 CW |
644 | /* most positive priority is scheduled first, equal priorities fifo */ |
645 | rb = NULL; | |
6c067579 CW |
646 | parent = &engine->execlist_queue.rb_node; |
647 | while (*parent) { | |
648 | rb = *parent; | |
649 | p = rb_entry(rb, typeof(*p), node); | |
650 | if (prio > p->priority) { | |
651 | parent = &rb->rb_left; | |
652 | } else if (prio < p->priority) { | |
653 | parent = &rb->rb_right; | |
20311bd3 | 654 | first = false; |
6c067579 CW |
655 | } else { |
656 | list_add_tail(&pt->link, &p->requests); | |
657 | return false; | |
20311bd3 CW |
658 | } |
659 | } | |
6c067579 CW |
660 | |
661 | if (prio == I915_PRIORITY_NORMAL) { | |
662 | p = &engine->default_priolist; | |
663 | } else { | |
c5cf9a91 | 664 | p = kmem_cache_alloc(engine->i915->priorities, GFP_ATOMIC); |
6c067579 CW |
665 | /* Convert an allocation failure to a priority bump */ |
666 | if (unlikely(!p)) { | |
667 | prio = I915_PRIORITY_NORMAL; /* recurses just once */ | |
668 | ||
669 | /* To maintain ordering with all rendering, after an | |
670 | * allocation failure we have to disable all scheduling. | |
671 | * Requests will then be executed in fifo, and schedule | |
672 | * will ensure that dependencies are emitted in fifo. | |
673 | * There will be still some reordering with existing | |
674 | * requests, so if userspace lied about their | |
675 | * dependencies that reordering may be visible. | |
676 | */ | |
677 | engine->no_priolist = true; | |
678 | goto find_priolist; | |
679 | } | |
680 | } | |
681 | ||
682 | p->priority = prio; | |
683 | rb_link_node(&p->node, rb, parent); | |
684 | rb_insert_color(&p->node, &engine->execlist_queue); | |
685 | ||
686 | INIT_LIST_HEAD(&p->requests); | |
687 | list_add_tail(&pt->link, &p->requests); | |
688 | ||
689 | if (first) | |
690 | engine->execlist_first = &p->node; | |
20311bd3 CW |
691 | |
692 | return first; | |
693 | } | |
694 | ||
f4ea6bdd | 695 | static void execlists_submit_request(struct drm_i915_gem_request *request) |
acdd884a | 696 | { |
4a570db5 | 697 | struct intel_engine_cs *engine = request->engine; |
5590af3e | 698 | unsigned long flags; |
acdd884a | 699 | |
663f71e7 CW |
700 | /* Will be called from irq-context when using foreign fences. */ |
701 | spin_lock_irqsave(&engine->timeline->lock, flags); | |
acdd884a | 702 | |
6c067579 CW |
703 | if (insert_request(engine, |
704 | &request->priotree, | |
705 | request->priotree.priority)) { | |
48ea2554 | 706 | if (execlists_elsp_ready(engine)) |
3833281a CW |
707 | tasklet_hi_schedule(&engine->irq_tasklet); |
708 | } | |
acdd884a | 709 | |
6c067579 CW |
710 | GEM_BUG_ON(!engine->execlist_first); |
711 | GEM_BUG_ON(list_empty(&request->priotree.link)); | |
712 | ||
663f71e7 | 713 | spin_unlock_irqrestore(&engine->timeline->lock, flags); |
acdd884a MT |
714 | } |
715 | ||
20311bd3 CW |
716 | static struct intel_engine_cs * |
717 | pt_lock_engine(struct i915_priotree *pt, struct intel_engine_cs *locked) | |
718 | { | |
a79a524e CW |
719 | struct intel_engine_cs *engine = |
720 | container_of(pt, struct drm_i915_gem_request, priotree)->engine; | |
721 | ||
722 | GEM_BUG_ON(!locked); | |
20311bd3 | 723 | |
20311bd3 | 724 | if (engine != locked) { |
a79a524e CW |
725 | spin_unlock(&locked->timeline->lock); |
726 | spin_lock(&engine->timeline->lock); | |
20311bd3 CW |
727 | } |
728 | ||
729 | return engine; | |
730 | } | |
731 | ||
732 | static void execlists_schedule(struct drm_i915_gem_request *request, int prio) | |
733 | { | |
a79a524e | 734 | struct intel_engine_cs *engine; |
20311bd3 CW |
735 | struct i915_dependency *dep, *p; |
736 | struct i915_dependency stack; | |
737 | LIST_HEAD(dfs); | |
738 | ||
739 | if (prio <= READ_ONCE(request->priotree.priority)) | |
740 | return; | |
741 | ||
70cd1476 CW |
742 | /* Need BKL in order to use the temporary link inside i915_dependency */ |
743 | lockdep_assert_held(&request->i915->drm.struct_mutex); | |
20311bd3 CW |
744 | |
745 | stack.signaler = &request->priotree; | |
746 | list_add(&stack.dfs_link, &dfs); | |
747 | ||
748 | /* Recursively bump all dependent priorities to match the new request. | |
749 | * | |
750 | * A naive approach would be to use recursion: | |
751 | * static void update_priorities(struct i915_priotree *pt, prio) { | |
752 | * list_for_each_entry(dep, &pt->signalers_list, signal_link) | |
753 | * update_priorities(dep->signal, prio) | |
754 | * insert_request(pt); | |
755 | * } | |
756 | * but that may have unlimited recursion depth and so runs a very | |
757 | * real risk of overunning the kernel stack. Instead, we build | |
758 | * a flat list of all dependencies starting with the current request. | |
759 | * As we walk the list of dependencies, we add all of its dependencies | |
760 | * to the end of the list (this may include an already visited | |
761 | * request) and continue to walk onwards onto the new dependencies. The | |
762 | * end result is a topological list of requests in reverse order, the | |
763 | * last element in the list is the request we must execute first. | |
764 | */ | |
765 | list_for_each_entry_safe(dep, p, &dfs, dfs_link) { | |
766 | struct i915_priotree *pt = dep->signaler; | |
767 | ||
a79a524e CW |
768 | /* Within an engine, there can be no cycle, but we may |
769 | * refer to the same dependency chain multiple times | |
770 | * (redundant dependencies are not eliminated) and across | |
771 | * engines. | |
772 | */ | |
773 | list_for_each_entry(p, &pt->signalers_list, signal_link) { | |
774 | GEM_BUG_ON(p->signaler->priority < pt->priority); | |
20311bd3 CW |
775 | if (prio > READ_ONCE(p->signaler->priority)) |
776 | list_move_tail(&p->dfs_link, &dfs); | |
a79a524e | 777 | } |
20311bd3 | 778 | |
0798cff4 | 779 | list_safe_reset_next(dep, p, dfs_link); |
20311bd3 CW |
780 | } |
781 | ||
a79a524e CW |
782 | engine = request->engine; |
783 | spin_lock_irq(&engine->timeline->lock); | |
784 | ||
20311bd3 CW |
785 | /* Fifo and depth-first replacement ensure our deps execute before us */ |
786 | list_for_each_entry_safe_reverse(dep, p, &dfs, dfs_link) { | |
787 | struct i915_priotree *pt = dep->signaler; | |
788 | ||
789 | INIT_LIST_HEAD(&dep->dfs_link); | |
790 | ||
791 | engine = pt_lock_engine(pt, engine); | |
792 | ||
793 | if (prio <= pt->priority) | |
794 | continue; | |
795 | ||
20311bd3 | 796 | pt->priority = prio; |
6c067579 CW |
797 | if (!list_empty(&pt->link)) { |
798 | __list_del_entry(&pt->link); | |
799 | insert_request(engine, pt, prio); | |
a79a524e | 800 | } |
20311bd3 CW |
801 | } |
802 | ||
a79a524e | 803 | spin_unlock_irq(&engine->timeline->lock); |
20311bd3 CW |
804 | |
805 | /* XXX Do we need to preempt to make room for us and our deps? */ | |
806 | } | |
807 | ||
266a240b CW |
808 | static struct intel_ring * |
809 | execlists_context_pin(struct intel_engine_cs *engine, | |
810 | struct i915_gem_context *ctx) | |
dcb4c12a | 811 | { |
9021ad03 | 812 | struct intel_context *ce = &ctx->engine[engine->id]; |
2947e408 | 813 | unsigned int flags; |
7d774cac | 814 | void *vaddr; |
ca82580c | 815 | int ret; |
dcb4c12a | 816 | |
91c8a326 | 817 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
ca82580c | 818 | |
266a240b CW |
819 | if (likely(ce->pin_count++)) |
820 | goto out; | |
a533b4ba | 821 | GEM_BUG_ON(!ce->pin_count); /* no overflow please! */ |
24f1d3cc | 822 | |
e8a9c58f CW |
823 | if (!ce->state) { |
824 | ret = execlists_context_deferred_alloc(ctx, engine); | |
825 | if (ret) | |
826 | goto err; | |
827 | } | |
56f6e0a7 | 828 | GEM_BUG_ON(!ce->state); |
e8a9c58f | 829 | |
72b72ae4 | 830 | flags = PIN_GLOBAL | PIN_HIGH; |
feef2a7c DCS |
831 | if (ctx->ggtt_offset_bias) |
832 | flags |= PIN_OFFSET_BIAS | ctx->ggtt_offset_bias; | |
2947e408 CW |
833 | |
834 | ret = i915_vma_pin(ce->state, 0, GEN8_LR_CONTEXT_ALIGN, flags); | |
e84fe803 | 835 | if (ret) |
24f1d3cc | 836 | goto err; |
7ba717cf | 837 | |
bf3783e5 | 838 | vaddr = i915_gem_object_pin_map(ce->state->obj, I915_MAP_WB); |
7d774cac TU |
839 | if (IS_ERR(vaddr)) { |
840 | ret = PTR_ERR(vaddr); | |
bf3783e5 | 841 | goto unpin_vma; |
82352e90 TU |
842 | } |
843 | ||
d822bb18 | 844 | ret = intel_ring_pin(ce->ring, ctx->i915, ctx->ggtt_offset_bias); |
e84fe803 | 845 | if (ret) |
7d774cac | 846 | goto unpin_map; |
d1675198 | 847 | |
0bc40be8 | 848 | intel_lr_context_descriptor_update(ctx, engine); |
9021ad03 | 849 | |
a3aabe86 CW |
850 | ce->lrc_reg_state = vaddr + LRC_STATE_PN * PAGE_SIZE; |
851 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = | |
bde13ebd | 852 | i915_ggtt_offset(ce->ring->vma); |
a3aabe86 | 853 | |
a4f5ea64 | 854 | ce->state->obj->mm.dirty = true; |
e93c28f3 | 855 | |
9a6feaf0 | 856 | i915_gem_context_get(ctx); |
266a240b CW |
857 | out: |
858 | return ce->ring; | |
7ba717cf | 859 | |
7d774cac | 860 | unpin_map: |
bf3783e5 CW |
861 | i915_gem_object_unpin_map(ce->state->obj); |
862 | unpin_vma: | |
863 | __i915_vma_unpin(ce->state); | |
24f1d3cc | 864 | err: |
9021ad03 | 865 | ce->pin_count = 0; |
266a240b | 866 | return ERR_PTR(ret); |
e84fe803 NH |
867 | } |
868 | ||
e8a9c58f CW |
869 | static void execlists_context_unpin(struct intel_engine_cs *engine, |
870 | struct i915_gem_context *ctx) | |
e84fe803 | 871 | { |
9021ad03 | 872 | struct intel_context *ce = &ctx->engine[engine->id]; |
e84fe803 | 873 | |
91c8a326 | 874 | lockdep_assert_held(&ctx->i915->drm.struct_mutex); |
9021ad03 | 875 | GEM_BUG_ON(ce->pin_count == 0); |
321fe304 | 876 | |
9021ad03 | 877 | if (--ce->pin_count) |
24f1d3cc | 878 | return; |
e84fe803 | 879 | |
aad29fbb | 880 | intel_ring_unpin(ce->ring); |
dcb4c12a | 881 | |
bf3783e5 CW |
882 | i915_gem_object_unpin_map(ce->state->obj); |
883 | i915_vma_unpin(ce->state); | |
321fe304 | 884 | |
9a6feaf0 | 885 | i915_gem_context_put(ctx); |
dcb4c12a OM |
886 | } |
887 | ||
f73e7399 | 888 | static int execlists_request_alloc(struct drm_i915_gem_request *request) |
ef11c01d CW |
889 | { |
890 | struct intel_engine_cs *engine = request->engine; | |
891 | struct intel_context *ce = &request->ctx->engine[engine->id]; | |
73dec95e | 892 | u32 *cs; |
ef11c01d CW |
893 | int ret; |
894 | ||
e8a9c58f CW |
895 | GEM_BUG_ON(!ce->pin_count); |
896 | ||
ef11c01d CW |
897 | /* Flush enough space to reduce the likelihood of waiting after |
898 | * we start building the request - in which case we will just | |
899 | * have to repeat work. | |
900 | */ | |
901 | request->reserved_space += EXECLISTS_REQUEST_SIZE; | |
902 | ||
ef11c01d CW |
903 | if (i915.enable_guc_submission) { |
904 | /* | |
905 | * Check that the GuC has space for the request before | |
906 | * going any further, as the i915_add_request() call | |
907 | * later on mustn't fail ... | |
908 | */ | |
909 | ret = i915_guc_wq_reserve(request); | |
910 | if (ret) | |
e8a9c58f | 911 | goto err; |
ef11c01d CW |
912 | } |
913 | ||
73dec95e TU |
914 | cs = intel_ring_begin(request, 0); |
915 | if (IS_ERR(cs)) { | |
916 | ret = PTR_ERR(cs); | |
ef11c01d | 917 | goto err_unreserve; |
73dec95e | 918 | } |
ef11c01d CW |
919 | |
920 | if (!ce->initialised) { | |
921 | ret = engine->init_context(request); | |
922 | if (ret) | |
923 | goto err_unreserve; | |
924 | ||
925 | ce->initialised = true; | |
926 | } | |
927 | ||
928 | /* Note that after this point, we have committed to using | |
929 | * this request as it is being used to both track the | |
930 | * state of engine initialisation and liveness of the | |
931 | * golden renderstate above. Think twice before you try | |
932 | * to cancel/unwind this request now. | |
933 | */ | |
934 | ||
935 | request->reserved_space -= EXECLISTS_REQUEST_SIZE; | |
936 | return 0; | |
937 | ||
938 | err_unreserve: | |
939 | if (i915.enable_guc_submission) | |
940 | i915_guc_wq_unreserve(request); | |
e8a9c58f | 941 | err: |
ef11c01d CW |
942 | return ret; |
943 | } | |
944 | ||
9e000847 AS |
945 | /* |
946 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
947 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
948 | * but there is a slight complication as this is applied in WA batch where the | |
949 | * values are only initialized once so we cannot take register value at the | |
950 | * beginning and reuse it further; hence we save its value to memory, upload a | |
951 | * constant value with bit21 set and then we restore it back with the saved value. | |
952 | * To simplify the WA, a constant value is formed by using the default value | |
953 | * of this register. This shouldn't be a problem because we are only modifying | |
954 | * it for a short period and this batch in non-premptible. We can ofcourse | |
955 | * use additional instructions that read the actual value of the register | |
956 | * at that time and set our bit of interest but it makes the WA complicated. | |
957 | * | |
958 | * This WA is also required for Gen9 so extracting as a function avoids | |
959 | * code duplication. | |
960 | */ | |
097d4f1c TU |
961 | static u32 * |
962 | gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *engine, u32 *batch) | |
17ee950d | 963 | { |
097d4f1c TU |
964 | *batch++ = MI_STORE_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; |
965 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
966 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
967 | *batch++ = 0; | |
968 | ||
969 | *batch++ = MI_LOAD_REGISTER_IMM(1); | |
970 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
971 | *batch++ = 0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES; | |
972 | ||
9f235dfa TU |
973 | batch = gen8_emit_pipe_control(batch, |
974 | PIPE_CONTROL_CS_STALL | | |
975 | PIPE_CONTROL_DC_FLUSH_ENABLE, | |
976 | 0); | |
097d4f1c TU |
977 | |
978 | *batch++ = MI_LOAD_REGISTER_MEM_GEN8 | MI_SRM_LRM_GLOBAL_GTT; | |
979 | *batch++ = i915_mmio_reg_offset(GEN8_L3SQCREG4); | |
980 | *batch++ = i915_ggtt_offset(engine->scratch) + 256; | |
981 | *batch++ = 0; | |
982 | ||
983 | return batch; | |
17ee950d AS |
984 | } |
985 | ||
6e5248b5 DV |
986 | /* |
987 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
988 | * initialized at the beginning and shared across all contexts but this field | |
989 | * helps us to have multiple batches at different offsets and select them based | |
990 | * on a criteria. At the moment this batch always start at the beginning of the page | |
991 | * and at this point we don't have multiple wa_ctx batch buffers. | |
4d78c8dc | 992 | * |
6e5248b5 DV |
993 | * The number of WA applied are not known at the beginning; we use this field |
994 | * to return the no of DWORDS written. | |
17ee950d | 995 | * |
6e5248b5 DV |
996 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
997 | * so it adds NOOPs as padding to make it cacheline aligned. | |
998 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
999 | * makes a complete batch buffer. | |
17ee950d | 1000 | */ |
097d4f1c | 1001 | static u32 *gen8_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1002 | { |
7ad00d1a | 1003 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c | 1004 | *batch++ = MI_ARB_ON_OFF | MI_ARB_DISABLE; |
17ee950d | 1005 | |
c82435bb | 1006 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
097d4f1c TU |
1007 | if (IS_BROADWELL(engine->i915)) |
1008 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); | |
c82435bb | 1009 | |
0160f055 AS |
1010 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1011 | /* Actual scratch location is at 128 bytes offset */ | |
9f235dfa TU |
1012 | batch = gen8_emit_pipe_control(batch, |
1013 | PIPE_CONTROL_FLUSH_L3 | | |
1014 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1015 | PIPE_CONTROL_CS_STALL | | |
1016 | PIPE_CONTROL_QW_WRITE, | |
1017 | i915_ggtt_offset(engine->scratch) + | |
1018 | 2 * CACHELINE_BYTES); | |
0160f055 | 1019 | |
17ee950d | 1020 | /* Pad to end of cacheline */ |
097d4f1c TU |
1021 | while ((unsigned long)batch % CACHELINE_BYTES) |
1022 | *batch++ = MI_NOOP; | |
17ee950d AS |
1023 | |
1024 | /* | |
1025 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1026 | * execution depends on the length specified in terms of cache lines | |
1027 | * in the register CTX_RCS_INDIRECT_CTX | |
1028 | */ | |
1029 | ||
097d4f1c | 1030 | return batch; |
17ee950d AS |
1031 | } |
1032 | ||
6e5248b5 DV |
1033 | /* |
1034 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1035 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
17ee950d | 1036 | * |
6e5248b5 | 1037 | * The number of DWORDS written are returned using this field. |
17ee950d AS |
1038 | * |
1039 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1040 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1041 | */ | |
097d4f1c | 1042 | static u32 *gen8_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
17ee950d | 1043 | { |
7ad00d1a | 1044 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
097d4f1c TU |
1045 | *batch++ = MI_ARB_ON_OFF | MI_ARB_ENABLE; |
1046 | *batch++ = MI_BATCH_BUFFER_END; | |
17ee950d | 1047 | |
097d4f1c | 1048 | return batch; |
17ee950d AS |
1049 | } |
1050 | ||
097d4f1c | 1051 | static u32 *gen9_init_indirectctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1052 | { |
9fb5026f | 1053 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt,glk */ |
097d4f1c | 1054 | batch = gen8_emit_flush_coherentl3_wa(engine, batch); |
a4106a78 | 1055 | |
9fb5026f | 1056 | /* WaDisableGatherAtSetShaderCommonSlice:skl,bxt,kbl,glk */ |
097d4f1c TU |
1057 | *batch++ = MI_LOAD_REGISTER_IMM(1); |
1058 | *batch++ = i915_mmio_reg_offset(COMMON_SLICE_CHICKEN2); | |
1059 | *batch++ = _MASKED_BIT_DISABLE( | |
1060 | GEN9_DISABLE_GATHER_AT_SET_SHADER_COMMON_SLICE); | |
1061 | *batch++ = MI_NOOP; | |
873e8171 | 1062 | |
066d4628 MK |
1063 | /* WaClearSlmSpaceAtContextSwitch:kbl */ |
1064 | /* Actual scratch location is at 128 bytes offset */ | |
097d4f1c | 1065 | if (IS_KBL_REVID(engine->i915, 0, KBL_REVID_A0)) { |
9f235dfa TU |
1066 | batch = gen8_emit_pipe_control(batch, |
1067 | PIPE_CONTROL_FLUSH_L3 | | |
1068 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1069 | PIPE_CONTROL_CS_STALL | | |
1070 | PIPE_CONTROL_QW_WRITE, | |
1071 | i915_ggtt_offset(engine->scratch) | |
1072 | + 2 * CACHELINE_BYTES); | |
066d4628 | 1073 | } |
3485d99e | 1074 | |
9fb5026f | 1075 | /* WaMediaPoolStateCmdInWABB:bxt,glk */ |
3485d99e TG |
1076 | if (HAS_POOLED_EU(engine->i915)) { |
1077 | /* | |
1078 | * EU pool configuration is setup along with golden context | |
1079 | * during context initialization. This value depends on | |
1080 | * device type (2x6 or 3x6) and needs to be updated based | |
1081 | * on which subslice is disabled especially for 2x6 | |
1082 | * devices, however it is safe to load default | |
1083 | * configuration of 3x6 device instead of masking off | |
1084 | * corresponding bits because HW ignores bits of a disabled | |
1085 | * subslice and drops down to appropriate config. Please | |
1086 | * see render_state_setup() in i915_gem_render_state.c for | |
1087 | * possible configurations, to avoid duplication they are | |
1088 | * not shown here again. | |
1089 | */ | |
097d4f1c TU |
1090 | *batch++ = GEN9_MEDIA_POOL_STATE; |
1091 | *batch++ = GEN9_MEDIA_POOL_ENABLE; | |
1092 | *batch++ = 0x00777000; | |
1093 | *batch++ = 0; | |
1094 | *batch++ = 0; | |
1095 | *batch++ = 0; | |
3485d99e TG |
1096 | } |
1097 | ||
0504cffc | 1098 | /* Pad to end of cacheline */ |
097d4f1c TU |
1099 | while ((unsigned long)batch % CACHELINE_BYTES) |
1100 | *batch++ = MI_NOOP; | |
0504cffc | 1101 | |
097d4f1c | 1102 | return batch; |
0504cffc AS |
1103 | } |
1104 | ||
097d4f1c | 1105 | static u32 *gen9_init_perctx_bb(struct intel_engine_cs *engine, u32 *batch) |
0504cffc | 1106 | { |
097d4f1c | 1107 | *batch++ = MI_BATCH_BUFFER_END; |
0504cffc | 1108 | |
097d4f1c | 1109 | return batch; |
0504cffc AS |
1110 | } |
1111 | ||
097d4f1c TU |
1112 | #define CTX_WA_BB_OBJ_SIZE (PAGE_SIZE) |
1113 | ||
1114 | static int lrc_setup_wa_ctx(struct intel_engine_cs *engine) | |
17ee950d | 1115 | { |
48bb74e4 CW |
1116 | struct drm_i915_gem_object *obj; |
1117 | struct i915_vma *vma; | |
1118 | int err; | |
17ee950d | 1119 | |
097d4f1c | 1120 | obj = i915_gem_object_create(engine->i915, CTX_WA_BB_OBJ_SIZE); |
48bb74e4 CW |
1121 | if (IS_ERR(obj)) |
1122 | return PTR_ERR(obj); | |
17ee950d | 1123 | |
a01cb37a | 1124 | vma = i915_vma_instance(obj, &engine->i915->ggtt.base, NULL); |
48bb74e4 CW |
1125 | if (IS_ERR(vma)) { |
1126 | err = PTR_ERR(vma); | |
1127 | goto err; | |
17ee950d AS |
1128 | } |
1129 | ||
48bb74e4 CW |
1130 | err = i915_vma_pin(vma, 0, PAGE_SIZE, PIN_GLOBAL | PIN_HIGH); |
1131 | if (err) | |
1132 | goto err; | |
1133 | ||
1134 | engine->wa_ctx.vma = vma; | |
17ee950d | 1135 | return 0; |
48bb74e4 CW |
1136 | |
1137 | err: | |
1138 | i915_gem_object_put(obj); | |
1139 | return err; | |
17ee950d AS |
1140 | } |
1141 | ||
097d4f1c | 1142 | static void lrc_destroy_wa_ctx(struct intel_engine_cs *engine) |
17ee950d | 1143 | { |
19880c4a | 1144 | i915_vma_unpin_and_release(&engine->wa_ctx.vma); |
17ee950d AS |
1145 | } |
1146 | ||
097d4f1c TU |
1147 | typedef u32 *(*wa_bb_func_t)(struct intel_engine_cs *engine, u32 *batch); |
1148 | ||
0bc40be8 | 1149 | static int intel_init_workaround_bb(struct intel_engine_cs *engine) |
17ee950d | 1150 | { |
48bb74e4 | 1151 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
097d4f1c TU |
1152 | struct i915_wa_ctx_bb *wa_bb[2] = { &wa_ctx->indirect_ctx, |
1153 | &wa_ctx->per_ctx }; | |
1154 | wa_bb_func_t wa_bb_fn[2]; | |
17ee950d | 1155 | struct page *page; |
097d4f1c TU |
1156 | void *batch, *batch_ptr; |
1157 | unsigned int i; | |
48bb74e4 | 1158 | int ret; |
17ee950d | 1159 | |
097d4f1c TU |
1160 | if (WARN_ON(engine->id != RCS || !engine->scratch)) |
1161 | return -EINVAL; | |
17ee950d | 1162 | |
097d4f1c TU |
1163 | switch (INTEL_GEN(engine->i915)) { |
1164 | case 9: | |
1165 | wa_bb_fn[0] = gen9_init_indirectctx_bb; | |
1166 | wa_bb_fn[1] = gen9_init_perctx_bb; | |
1167 | break; | |
1168 | case 8: | |
1169 | wa_bb_fn[0] = gen8_init_indirectctx_bb; | |
1170 | wa_bb_fn[1] = gen8_init_perctx_bb; | |
1171 | break; | |
1172 | default: | |
1173 | MISSING_CASE(INTEL_GEN(engine->i915)); | |
5e60d790 | 1174 | return 0; |
0504cffc | 1175 | } |
5e60d790 | 1176 | |
097d4f1c | 1177 | ret = lrc_setup_wa_ctx(engine); |
17ee950d AS |
1178 | if (ret) { |
1179 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1180 | return ret; | |
1181 | } | |
1182 | ||
48bb74e4 | 1183 | page = i915_gem_object_get_dirty_page(wa_ctx->vma->obj, 0); |
097d4f1c | 1184 | batch = batch_ptr = kmap_atomic(page); |
17ee950d | 1185 | |
097d4f1c TU |
1186 | /* |
1187 | * Emit the two workaround batch buffers, recording the offset from the | |
1188 | * start of the workaround batch buffer object for each and their | |
1189 | * respective sizes. | |
1190 | */ | |
1191 | for (i = 0; i < ARRAY_SIZE(wa_bb_fn); i++) { | |
1192 | wa_bb[i]->offset = batch_ptr - batch; | |
1193 | if (WARN_ON(!IS_ALIGNED(wa_bb[i]->offset, CACHELINE_BYTES))) { | |
1194 | ret = -EINVAL; | |
1195 | break; | |
1196 | } | |
1197 | batch_ptr = wa_bb_fn[i](engine, batch_ptr); | |
1198 | wa_bb[i]->size = batch_ptr - (batch + wa_bb[i]->offset); | |
17ee950d AS |
1199 | } |
1200 | ||
097d4f1c TU |
1201 | BUG_ON(batch_ptr - batch > CTX_WA_BB_OBJ_SIZE); |
1202 | ||
17ee950d AS |
1203 | kunmap_atomic(batch); |
1204 | if (ret) | |
097d4f1c | 1205 | lrc_destroy_wa_ctx(engine); |
17ee950d AS |
1206 | |
1207 | return ret; | |
1208 | } | |
1209 | ||
0bc40be8 | 1210 | static int gen8_init_common_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1211 | { |
c033666a | 1212 | struct drm_i915_private *dev_priv = engine->i915; |
6b764a59 CW |
1213 | struct execlist_port *port = engine->execlist_port; |
1214 | unsigned int n; | |
77f0d0e9 | 1215 | bool submit; |
821ed7df CW |
1216 | int ret; |
1217 | ||
1218 | ret = intel_mocs_init_engine(engine); | |
1219 | if (ret) | |
1220 | return ret; | |
9b1136d5 | 1221 | |
ad07dfcd | 1222 | intel_engine_reset_breadcrumbs(engine); |
f3b8f912 | 1223 | intel_engine_init_hangcheck(engine); |
821ed7df | 1224 | |
0bc40be8 | 1225 | I915_WRITE(RING_HWSTAM(engine->mmio_base), 0xffffffff); |
0bc40be8 | 1226 | I915_WRITE(RING_MODE_GEN7(engine), |
9b1136d5 | 1227 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); |
f3b8f912 CW |
1228 | I915_WRITE(RING_HWS_PGA(engine->mmio_base), |
1229 | engine->status_page.ggtt_offset); | |
1230 | POSTING_READ(RING_HWS_PGA(engine->mmio_base)); | |
dfc53c5e | 1231 | |
0bc40be8 | 1232 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", engine->name); |
9b1136d5 | 1233 | |
c87d50cc | 1234 | /* After a GPU reset, we may have requests to replay */ |
f747026c | 1235 | clear_bit(ENGINE_IRQ_EXECLIST, &engine->irq_posted); |
6b764a59 | 1236 | |
77f0d0e9 | 1237 | submit = false; |
6b764a59 | 1238 | for (n = 0; n < ARRAY_SIZE(engine->execlist_port); n++) { |
77f0d0e9 | 1239 | if (!port_isset(&port[n])) |
6b764a59 CW |
1240 | break; |
1241 | ||
1242 | DRM_DEBUG_DRIVER("Restarting %s:%d from 0x%x\n", | |
1243 | engine->name, n, | |
77f0d0e9 | 1244 | port_request(&port[n])->global_seqno); |
6b764a59 CW |
1245 | |
1246 | /* Discard the current inflight count */ | |
77f0d0e9 CW |
1247 | port_set(&port[n], port_request(&port[n])); |
1248 | submit = true; | |
c87d50cc | 1249 | } |
821ed7df | 1250 | |
77f0d0e9 | 1251 | if (submit && !i915.enable_guc_submission) |
6b764a59 CW |
1252 | execlists_submit_ports(engine); |
1253 | ||
821ed7df | 1254 | return 0; |
9b1136d5 OM |
1255 | } |
1256 | ||
0bc40be8 | 1257 | static int gen8_init_render_ring(struct intel_engine_cs *engine) |
9b1136d5 | 1258 | { |
c033666a | 1259 | struct drm_i915_private *dev_priv = engine->i915; |
9b1136d5 OM |
1260 | int ret; |
1261 | ||
0bc40be8 | 1262 | ret = gen8_init_common_ring(engine); |
9b1136d5 OM |
1263 | if (ret) |
1264 | return ret; | |
1265 | ||
1266 | /* We need to disable the AsyncFlip performance optimisations in order | |
1267 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1268 | * programmed to '1' on all products. | |
1269 | * | |
1270 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1271 | */ | |
1272 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1273 | ||
9b1136d5 OM |
1274 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1275 | ||
0bc40be8 | 1276 | return init_workarounds_ring(engine); |
9b1136d5 OM |
1277 | } |
1278 | ||
0bc40be8 | 1279 | static int gen9_init_render_ring(struct intel_engine_cs *engine) |
82ef822e DL |
1280 | { |
1281 | int ret; | |
1282 | ||
0bc40be8 | 1283 | ret = gen8_init_common_ring(engine); |
82ef822e DL |
1284 | if (ret) |
1285 | return ret; | |
1286 | ||
0bc40be8 | 1287 | return init_workarounds_ring(engine); |
82ef822e DL |
1288 | } |
1289 | ||
821ed7df CW |
1290 | static void reset_common_ring(struct intel_engine_cs *engine, |
1291 | struct drm_i915_gem_request *request) | |
1292 | { | |
821ed7df | 1293 | struct execlist_port *port = engine->execlist_port; |
c0dcb203 CW |
1294 | struct intel_context *ce; |
1295 | ||
1296 | /* If the request was innocent, we leave the request in the ELSP | |
1297 | * and will try to replay it on restarting. The context image may | |
1298 | * have been corrupted by the reset, in which case we may have | |
1299 | * to service a new GPU hang, but more likely we can continue on | |
1300 | * without impact. | |
1301 | * | |
1302 | * If the request was guilty, we presume the context is corrupt | |
1303 | * and have to at least restore the RING register in the context | |
1304 | * image back to the expected values to skip over the guilty request. | |
1305 | */ | |
1306 | if (!request || request->fence.error != -EIO) | |
1307 | return; | |
821ed7df | 1308 | |
a3aabe86 CW |
1309 | /* We want a simple context + ring to execute the breadcrumb update. |
1310 | * We cannot rely on the context being intact across the GPU hang, | |
1311 | * so clear it and rebuild just what we need for the breadcrumb. | |
1312 | * All pending requests for this context will be zapped, and any | |
1313 | * future request will be after userspace has had the opportunity | |
1314 | * to recreate its own state. | |
1315 | */ | |
c0dcb203 | 1316 | ce = &request->ctx->engine[engine->id]; |
a3aabe86 CW |
1317 | execlists_init_reg_state(ce->lrc_reg_state, |
1318 | request->ctx, engine, ce->ring); | |
1319 | ||
821ed7df | 1320 | /* Move the RING_HEAD onto the breadcrumb, past the hanging batch */ |
a3aabe86 CW |
1321 | ce->lrc_reg_state[CTX_RING_BUFFER_START+1] = |
1322 | i915_ggtt_offset(ce->ring->vma); | |
821ed7df | 1323 | ce->lrc_reg_state[CTX_RING_HEAD+1] = request->postfix; |
a3aabe86 | 1324 | |
821ed7df | 1325 | request->ring->head = request->postfix; |
821ed7df CW |
1326 | intel_ring_update_space(request->ring); |
1327 | ||
821ed7df | 1328 | /* Catch up with any missed context-switch interrupts */ |
77f0d0e9 CW |
1329 | if (request->ctx != port_request(port)->ctx) { |
1330 | i915_gem_request_put(port_request(port)); | |
821ed7df CW |
1331 | port[0] = port[1]; |
1332 | memset(&port[1], 0, sizeof(port[1])); | |
1333 | } | |
1334 | ||
77f0d0e9 | 1335 | GEM_BUG_ON(request->ctx != port_request(port)->ctx); |
a3aabe86 CW |
1336 | |
1337 | /* Reset WaIdleLiteRestore:bdw,skl as well */ | |
450362d3 CW |
1338 | request->tail = |
1339 | intel_ring_wrap(request->ring, | |
1340 | request->wa_tail - WA_TAIL_DWORDS*sizeof(u32)); | |
ed1501d4 | 1341 | assert_ring_tail_valid(request->ring, request->tail); |
821ed7df CW |
1342 | } |
1343 | ||
7a01a0a2 MT |
1344 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1345 | { | |
1346 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
4a570db5 | 1347 | struct intel_engine_cs *engine = req->engine; |
e7167769 | 1348 | const int num_lri_cmds = GEN8_3LVL_PDPES * 2; |
73dec95e TU |
1349 | u32 *cs; |
1350 | int i; | |
7a01a0a2 | 1351 | |
73dec95e TU |
1352 | cs = intel_ring_begin(req, num_lri_cmds * 2 + 2); |
1353 | if (IS_ERR(cs)) | |
1354 | return PTR_ERR(cs); | |
7a01a0a2 | 1355 | |
73dec95e | 1356 | *cs++ = MI_LOAD_REGISTER_IMM(num_lri_cmds); |
e7167769 | 1357 | for (i = GEN8_3LVL_PDPES - 1; i >= 0; i--) { |
7a01a0a2 MT |
1358 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); |
1359 | ||
73dec95e TU |
1360 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_UDW(engine, i)); |
1361 | *cs++ = upper_32_bits(pd_daddr); | |
1362 | *cs++ = i915_mmio_reg_offset(GEN8_RING_PDP_LDW(engine, i)); | |
1363 | *cs++ = lower_32_bits(pd_daddr); | |
7a01a0a2 MT |
1364 | } |
1365 | ||
73dec95e TU |
1366 | *cs++ = MI_NOOP; |
1367 | intel_ring_advance(req, cs); | |
7a01a0a2 MT |
1368 | |
1369 | return 0; | |
1370 | } | |
1371 | ||
be795fc1 | 1372 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
803688ba | 1373 | u64 offset, u32 len, |
54af56db | 1374 | const unsigned int flags) |
15648585 | 1375 | { |
73dec95e | 1376 | u32 *cs; |
15648585 OM |
1377 | int ret; |
1378 | ||
7a01a0a2 MT |
1379 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1380 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1381 | * but we can't. Force Restore would be a second option, but | |
1382 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1383 | * not idle). PML4 is allocated during ppgtt init so this is |
1384 | * not needed in 48-bit.*/ | |
7a01a0a2 | 1385 | if (req->ctx->ppgtt && |
54af56db MK |
1386 | (intel_engine_flag(req->engine) & req->ctx->ppgtt->pd_dirty_rings) && |
1387 | !i915_vm_is_48bit(&req->ctx->ppgtt->base) && | |
1388 | !intel_vgpu_active(req->i915)) { | |
1389 | ret = intel_logical_ring_emit_pdps(req); | |
1390 | if (ret) | |
1391 | return ret; | |
7a01a0a2 | 1392 | |
666796da | 1393 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_engine_flag(req->engine); |
7a01a0a2 MT |
1394 | } |
1395 | ||
73dec95e TU |
1396 | cs = intel_ring_begin(req, 4); |
1397 | if (IS_ERR(cs)) | |
1398 | return PTR_ERR(cs); | |
15648585 OM |
1399 | |
1400 | /* FIXME(BDW): Address space and security selectors. */ | |
54af56db MK |
1401 | *cs++ = MI_BATCH_BUFFER_START_GEN8 | |
1402 | (flags & I915_DISPATCH_SECURE ? 0 : BIT(8)) | | |
1403 | (flags & I915_DISPATCH_RS ? MI_BATCH_RESOURCE_STREAMER : 0); | |
73dec95e TU |
1404 | *cs++ = lower_32_bits(offset); |
1405 | *cs++ = upper_32_bits(offset); | |
1406 | *cs++ = MI_NOOP; | |
1407 | intel_ring_advance(req, cs); | |
15648585 OM |
1408 | |
1409 | return 0; | |
1410 | } | |
1411 | ||
31bb59cc | 1412 | static void gen8_logical_ring_enable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1413 | { |
c033666a | 1414 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc CW |
1415 | I915_WRITE_IMR(engine, |
1416 | ~(engine->irq_enable_mask | engine->irq_keep_mask)); | |
1417 | POSTING_READ_FW(RING_IMR(engine->mmio_base)); | |
73d477f6 OM |
1418 | } |
1419 | ||
31bb59cc | 1420 | static void gen8_logical_ring_disable_irq(struct intel_engine_cs *engine) |
73d477f6 | 1421 | { |
c033666a | 1422 | struct drm_i915_private *dev_priv = engine->i915; |
31bb59cc | 1423 | I915_WRITE_IMR(engine, ~engine->irq_keep_mask); |
73d477f6 OM |
1424 | } |
1425 | ||
7c9cf4e3 | 1426 | static int gen8_emit_flush(struct drm_i915_gem_request *request, u32 mode) |
4712274c | 1427 | { |
73dec95e | 1428 | u32 cmd, *cs; |
4712274c | 1429 | |
73dec95e TU |
1430 | cs = intel_ring_begin(request, 4); |
1431 | if (IS_ERR(cs)) | |
1432 | return PTR_ERR(cs); | |
4712274c OM |
1433 | |
1434 | cmd = MI_FLUSH_DW + 1; | |
1435 | ||
f0a1fb10 CW |
1436 | /* We always require a command barrier so that subsequent |
1437 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1438 | * wrt the contents of the write cache being flushed to memory | |
1439 | * (and thus being coherent from the CPU). | |
1440 | */ | |
1441 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1442 | ||
7c9cf4e3 | 1443 | if (mode & EMIT_INVALIDATE) { |
f0a1fb10 | 1444 | cmd |= MI_INVALIDATE_TLB; |
1dae2dfb | 1445 | if (request->engine->id == VCS) |
f0a1fb10 | 1446 | cmd |= MI_INVALIDATE_BSD; |
4712274c OM |
1447 | } |
1448 | ||
73dec95e TU |
1449 | *cs++ = cmd; |
1450 | *cs++ = I915_GEM_HWS_SCRATCH_ADDR | MI_FLUSH_DW_USE_GTT; | |
1451 | *cs++ = 0; /* upper addr */ | |
1452 | *cs++ = 0; /* value */ | |
1453 | intel_ring_advance(request, cs); | |
4712274c OM |
1454 | |
1455 | return 0; | |
1456 | } | |
1457 | ||
7deb4d39 | 1458 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
7c9cf4e3 | 1459 | u32 mode) |
4712274c | 1460 | { |
b5321f30 | 1461 | struct intel_engine_cs *engine = request->engine; |
bde13ebd CW |
1462 | u32 scratch_addr = |
1463 | i915_ggtt_offset(engine->scratch) + 2 * CACHELINE_BYTES; | |
0b2d0934 | 1464 | bool vf_flush_wa = false, dc_flush_wa = false; |
73dec95e | 1465 | u32 *cs, flags = 0; |
0b2d0934 | 1466 | int len; |
4712274c OM |
1467 | |
1468 | flags |= PIPE_CONTROL_CS_STALL; | |
1469 | ||
7c9cf4e3 | 1470 | if (mode & EMIT_FLUSH) { |
4712274c OM |
1471 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; |
1472 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
965fd602 | 1473 | flags |= PIPE_CONTROL_DC_FLUSH_ENABLE; |
40a24488 | 1474 | flags |= PIPE_CONTROL_FLUSH_ENABLE; |
4712274c OM |
1475 | } |
1476 | ||
7c9cf4e3 | 1477 | if (mode & EMIT_INVALIDATE) { |
4712274c OM |
1478 | flags |= PIPE_CONTROL_TLB_INVALIDATE; |
1479 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1480 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1481 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1482 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1483 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1484 | flags |= PIPE_CONTROL_QW_WRITE; | |
1485 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
4712274c | 1486 | |
1a5a9ce7 BW |
1487 | /* |
1488 | * On GEN9: before VF_CACHE_INVALIDATE we need to emit a NULL | |
1489 | * pipe control. | |
1490 | */ | |
c033666a | 1491 | if (IS_GEN9(request->i915)) |
1a5a9ce7 | 1492 | vf_flush_wa = true; |
0b2d0934 MK |
1493 | |
1494 | /* WaForGAMHang:kbl */ | |
1495 | if (IS_KBL_REVID(request->i915, 0, KBL_REVID_B0)) | |
1496 | dc_flush_wa = true; | |
1a5a9ce7 | 1497 | } |
9647ff36 | 1498 | |
0b2d0934 MK |
1499 | len = 6; |
1500 | ||
1501 | if (vf_flush_wa) | |
1502 | len += 6; | |
1503 | ||
1504 | if (dc_flush_wa) | |
1505 | len += 12; | |
1506 | ||
73dec95e TU |
1507 | cs = intel_ring_begin(request, len); |
1508 | if (IS_ERR(cs)) | |
1509 | return PTR_ERR(cs); | |
4712274c | 1510 | |
9f235dfa TU |
1511 | if (vf_flush_wa) |
1512 | cs = gen8_emit_pipe_control(cs, 0, 0); | |
9647ff36 | 1513 | |
9f235dfa TU |
1514 | if (dc_flush_wa) |
1515 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_DC_FLUSH_ENABLE, | |
1516 | 0); | |
0b2d0934 | 1517 | |
9f235dfa | 1518 | cs = gen8_emit_pipe_control(cs, flags, scratch_addr); |
0b2d0934 | 1519 | |
9f235dfa TU |
1520 | if (dc_flush_wa) |
1521 | cs = gen8_emit_pipe_control(cs, PIPE_CONTROL_CS_STALL, 0); | |
0b2d0934 | 1522 | |
73dec95e | 1523 | intel_ring_advance(request, cs); |
4712274c OM |
1524 | |
1525 | return 0; | |
1526 | } | |
1527 | ||
7c17d377 CW |
1528 | /* |
1529 | * Reserve space for 2 NOOPs at the end of each request to be | |
1530 | * used as a workaround for not being allowed to do lite | |
1531 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1532 | */ | |
73dec95e | 1533 | static void gen8_emit_wa_tail(struct drm_i915_gem_request *request, u32 *cs) |
4da46e1e | 1534 | { |
73dec95e TU |
1535 | *cs++ = MI_NOOP; |
1536 | *cs++ = MI_NOOP; | |
1537 | request->wa_tail = intel_ring_offset(request, cs); | |
caddfe71 | 1538 | } |
4da46e1e | 1539 | |
73dec95e | 1540 | static void gen8_emit_breadcrumb(struct drm_i915_gem_request *request, u32 *cs) |
caddfe71 | 1541 | { |
7c17d377 CW |
1542 | /* w/a: bit 5 needs to be zero for MI_FLUSH_DW address. */ |
1543 | BUILD_BUG_ON(I915_GEM_HWS_INDEX_ADDR & (1 << 5)); | |
4da46e1e | 1544 | |
73dec95e TU |
1545 | *cs++ = (MI_FLUSH_DW + 1) | MI_FLUSH_DW_OP_STOREDW; |
1546 | *cs++ = intel_hws_seqno_address(request->engine) | MI_FLUSH_DW_USE_GTT; | |
1547 | *cs++ = 0; | |
1548 | *cs++ = request->global_seqno; | |
1549 | *cs++ = MI_USER_INTERRUPT; | |
1550 | *cs++ = MI_NOOP; | |
1551 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1552 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1553 | |
73dec95e | 1554 | gen8_emit_wa_tail(request, cs); |
7c17d377 | 1555 | } |
4da46e1e | 1556 | |
98f29e8d CW |
1557 | static const int gen8_emit_breadcrumb_sz = 6 + WA_TAIL_DWORDS; |
1558 | ||
caddfe71 | 1559 | static void gen8_emit_breadcrumb_render(struct drm_i915_gem_request *request, |
73dec95e | 1560 | u32 *cs) |
7c17d377 | 1561 | { |
ce81a65c MW |
1562 | /* We're using qword write, seqno should be aligned to 8 bytes. */ |
1563 | BUILD_BUG_ON(I915_GEM_HWS_INDEX & 1); | |
1564 | ||
7c17d377 CW |
1565 | /* w/a for post sync ops following a GPGPU operation we |
1566 | * need a prior CS_STALL, which is emitted by the flush | |
1567 | * following the batch. | |
1568 | */ | |
73dec95e TU |
1569 | *cs++ = GFX_OP_PIPE_CONTROL(6); |
1570 | *cs++ = PIPE_CONTROL_GLOBAL_GTT_IVB | PIPE_CONTROL_CS_STALL | | |
1571 | PIPE_CONTROL_QW_WRITE; | |
1572 | *cs++ = intel_hws_seqno_address(request->engine); | |
1573 | *cs++ = 0; | |
1574 | *cs++ = request->global_seqno; | |
ce81a65c | 1575 | /* We're thrashing one dword of HWS. */ |
73dec95e TU |
1576 | *cs++ = 0; |
1577 | *cs++ = MI_USER_INTERRUPT; | |
1578 | *cs++ = MI_NOOP; | |
1579 | request->tail = intel_ring_offset(request, cs); | |
ed1501d4 | 1580 | assert_ring_tail_valid(request->ring, request->tail); |
caddfe71 | 1581 | |
73dec95e | 1582 | gen8_emit_wa_tail(request, cs); |
4da46e1e OM |
1583 | } |
1584 | ||
98f29e8d CW |
1585 | static const int gen8_emit_breadcrumb_render_sz = 8 + WA_TAIL_DWORDS; |
1586 | ||
8753181e | 1587 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1588 | { |
1589 | int ret; | |
1590 | ||
4ac9659e | 1591 | ret = intel_ring_workarounds_emit(req); |
e7778be1 TD |
1592 | if (ret) |
1593 | return ret; | |
1594 | ||
3bbaba0c PA |
1595 | ret = intel_rcs_context_init_mocs(req); |
1596 | /* | |
1597 | * Failing to program the MOCS is non-fatal.The system will not | |
1598 | * run at peak performance. So generate an error and carry on. | |
1599 | */ | |
1600 | if (ret) | |
1601 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1602 | ||
4e50f082 | 1603 | return i915_gem_render_state_emit(req); |
e7778be1 TD |
1604 | } |
1605 | ||
73e4d07f OM |
1606 | /** |
1607 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
14bb2c11 | 1608 | * @engine: Engine Command Streamer. |
73e4d07f | 1609 | */ |
0bc40be8 | 1610 | void intel_logical_ring_cleanup(struct intel_engine_cs *engine) |
454afebd | 1611 | { |
6402c330 | 1612 | struct drm_i915_private *dev_priv; |
9832b9da | 1613 | |
27af5eea TU |
1614 | /* |
1615 | * Tasklet cannot be active at this point due intel_mark_active/idle | |
1616 | * so this is just for documentation. | |
1617 | */ | |
1618 | if (WARN_ON(test_bit(TASKLET_STATE_SCHED, &engine->irq_tasklet.state))) | |
1619 | tasklet_kill(&engine->irq_tasklet); | |
1620 | ||
c033666a | 1621 | dev_priv = engine->i915; |
6402c330 | 1622 | |
0bc40be8 | 1623 | if (engine->buffer) { |
0bc40be8 | 1624 | WARN_ON((I915_READ_MODE(engine) & MODE_IDLE) == 0); |
b0366a54 | 1625 | } |
48d82387 | 1626 | |
0bc40be8 TU |
1627 | if (engine->cleanup) |
1628 | engine->cleanup(engine); | |
48d82387 | 1629 | |
57e88531 CW |
1630 | if (engine->status_page.vma) { |
1631 | i915_gem_object_unpin_map(engine->status_page.vma->obj); | |
1632 | engine->status_page.vma = NULL; | |
48d82387 | 1633 | } |
e8a9c58f CW |
1634 | |
1635 | intel_engine_cleanup_common(engine); | |
17ee950d | 1636 | |
097d4f1c | 1637 | lrc_destroy_wa_ctx(engine); |
c033666a | 1638 | engine->i915 = NULL; |
3b3f1650 AG |
1639 | dev_priv->engine[engine->id] = NULL; |
1640 | kfree(engine); | |
454afebd OM |
1641 | } |
1642 | ||
ff44ad51 | 1643 | static void execlists_set_default_submission(struct intel_engine_cs *engine) |
ddd66c51 | 1644 | { |
ff44ad51 CW |
1645 | engine->submit_request = execlists_submit_request; |
1646 | engine->schedule = execlists_schedule; | |
c9203e82 | 1647 | engine->irq_tasklet.func = intel_lrc_irq_handler; |
ddd66c51 CW |
1648 | } |
1649 | ||
c9cacf93 | 1650 | static void |
e1382efb | 1651 | logical_ring_default_vfuncs(struct intel_engine_cs *engine) |
c9cacf93 TU |
1652 | { |
1653 | /* Default vfuncs which can be overriden by each engine. */ | |
0bc40be8 | 1654 | engine->init_hw = gen8_init_common_ring; |
821ed7df | 1655 | engine->reset_hw = reset_common_ring; |
e8a9c58f CW |
1656 | |
1657 | engine->context_pin = execlists_context_pin; | |
1658 | engine->context_unpin = execlists_context_unpin; | |
1659 | ||
f73e7399 CW |
1660 | engine->request_alloc = execlists_request_alloc; |
1661 | ||
0bc40be8 | 1662 | engine->emit_flush = gen8_emit_flush; |
9b81d556 | 1663 | engine->emit_breadcrumb = gen8_emit_breadcrumb; |
98f29e8d | 1664 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_sz; |
ff44ad51 CW |
1665 | |
1666 | engine->set_default_submission = execlists_set_default_submission; | |
ddd66c51 | 1667 | |
31bb59cc CW |
1668 | engine->irq_enable = gen8_logical_ring_enable_irq; |
1669 | engine->irq_disable = gen8_logical_ring_disable_irq; | |
0bc40be8 | 1670 | engine->emit_bb_start = gen8_emit_bb_start; |
c9cacf93 TU |
1671 | } |
1672 | ||
d9f3af96 | 1673 | static inline void |
c2c7f240 | 1674 | logical_ring_default_irqs(struct intel_engine_cs *engine) |
d9f3af96 | 1675 | { |
c2c7f240 | 1676 | unsigned shift = engine->irq_shift; |
0bc40be8 TU |
1677 | engine->irq_enable_mask = GT_RENDER_USER_INTERRUPT << shift; |
1678 | engine->irq_keep_mask = GT_CONTEXT_SWITCH_INTERRUPT << shift; | |
d9f3af96 TU |
1679 | } |
1680 | ||
7d774cac | 1681 | static int |
bf3783e5 | 1682 | lrc_setup_hws(struct intel_engine_cs *engine, struct i915_vma *vma) |
04794adb | 1683 | { |
57e88531 | 1684 | const int hws_offset = LRC_PPHWSP_PN * PAGE_SIZE; |
7d774cac | 1685 | void *hws; |
04794adb TU |
1686 | |
1687 | /* The HWSP is part of the default context object in LRC mode. */ | |
bf3783e5 | 1688 | hws = i915_gem_object_pin_map(vma->obj, I915_MAP_WB); |
7d774cac TU |
1689 | if (IS_ERR(hws)) |
1690 | return PTR_ERR(hws); | |
57e88531 CW |
1691 | |
1692 | engine->status_page.page_addr = hws + hws_offset; | |
bde13ebd | 1693 | engine->status_page.ggtt_offset = i915_ggtt_offset(vma) + hws_offset; |
57e88531 | 1694 | engine->status_page.vma = vma; |
7d774cac TU |
1695 | |
1696 | return 0; | |
04794adb TU |
1697 | } |
1698 | ||
bb45438f TU |
1699 | static void |
1700 | logical_ring_setup(struct intel_engine_cs *engine) | |
1701 | { | |
1702 | struct drm_i915_private *dev_priv = engine->i915; | |
1703 | enum forcewake_domains fw_domains; | |
1704 | ||
019bf277 TU |
1705 | intel_engine_setup_common(engine); |
1706 | ||
bb45438f TU |
1707 | /* Intentionally left blank. */ |
1708 | engine->buffer = NULL; | |
1709 | ||
1710 | fw_domains = intel_uncore_forcewake_for_reg(dev_priv, | |
1711 | RING_ELSP(engine), | |
1712 | FW_REG_WRITE); | |
1713 | ||
1714 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1715 | RING_CONTEXT_STATUS_PTR(engine), | |
1716 | FW_REG_READ | FW_REG_WRITE); | |
1717 | ||
1718 | fw_domains |= intel_uncore_forcewake_for_reg(dev_priv, | |
1719 | RING_CONTEXT_STATUS_BUF_BASE(engine), | |
1720 | FW_REG_READ); | |
1721 | ||
1722 | engine->fw_domains = fw_domains; | |
1723 | ||
bb45438f TU |
1724 | tasklet_init(&engine->irq_tasklet, |
1725 | intel_lrc_irq_handler, (unsigned long)engine); | |
1726 | ||
bb45438f TU |
1727 | logical_ring_default_vfuncs(engine); |
1728 | logical_ring_default_irqs(engine); | |
bb45438f TU |
1729 | } |
1730 | ||
a19d6ff2 TU |
1731 | static int |
1732 | logical_ring_init(struct intel_engine_cs *engine) | |
1733 | { | |
1734 | struct i915_gem_context *dctx = engine->i915->kernel_context; | |
1735 | int ret; | |
1736 | ||
019bf277 | 1737 | ret = intel_engine_init_common(engine); |
a19d6ff2 TU |
1738 | if (ret) |
1739 | goto error; | |
1740 | ||
a19d6ff2 TU |
1741 | /* And setup the hardware status page. */ |
1742 | ret = lrc_setup_hws(engine, dctx->engine[engine->id].state); | |
1743 | if (ret) { | |
1744 | DRM_ERROR("Failed to set up hws %s: %d\n", engine->name, ret); | |
1745 | goto error; | |
1746 | } | |
1747 | ||
1748 | return 0; | |
1749 | ||
1750 | error: | |
1751 | intel_logical_ring_cleanup(engine); | |
1752 | return ret; | |
1753 | } | |
1754 | ||
88d2ba2e | 1755 | int logical_render_ring_init(struct intel_engine_cs *engine) |
a19d6ff2 TU |
1756 | { |
1757 | struct drm_i915_private *dev_priv = engine->i915; | |
1758 | int ret; | |
1759 | ||
bb45438f TU |
1760 | logical_ring_setup(engine); |
1761 | ||
a19d6ff2 TU |
1762 | if (HAS_L3_DPF(dev_priv)) |
1763 | engine->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
1764 | ||
1765 | /* Override some for render ring. */ | |
1766 | if (INTEL_GEN(dev_priv) >= 9) | |
1767 | engine->init_hw = gen9_init_render_ring; | |
1768 | else | |
1769 | engine->init_hw = gen8_init_render_ring; | |
1770 | engine->init_context = gen8_init_rcs_context; | |
a19d6ff2 | 1771 | engine->emit_flush = gen8_emit_flush_render; |
9b81d556 | 1772 | engine->emit_breadcrumb = gen8_emit_breadcrumb_render; |
98f29e8d | 1773 | engine->emit_breadcrumb_sz = gen8_emit_breadcrumb_render_sz; |
a19d6ff2 | 1774 | |
f51455d4 | 1775 | ret = intel_engine_create_scratch(engine, PAGE_SIZE); |
a19d6ff2 TU |
1776 | if (ret) |
1777 | return ret; | |
1778 | ||
1779 | ret = intel_init_workaround_bb(engine); | |
1780 | if (ret) { | |
1781 | /* | |
1782 | * We continue even if we fail to initialize WA batch | |
1783 | * because we only expect rare glitches but nothing | |
1784 | * critical to prevent us from using GPU | |
1785 | */ | |
1786 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1787 | ret); | |
1788 | } | |
1789 | ||
d038fc7e | 1790 | return logical_ring_init(engine); |
a19d6ff2 TU |
1791 | } |
1792 | ||
88d2ba2e | 1793 | int logical_xcs_ring_init(struct intel_engine_cs *engine) |
bb45438f TU |
1794 | { |
1795 | logical_ring_setup(engine); | |
1796 | ||
1797 | return logical_ring_init(engine); | |
454afebd OM |
1798 | } |
1799 | ||
0cea6502 | 1800 | static u32 |
c033666a | 1801 | make_rpcs(struct drm_i915_private *dev_priv) |
0cea6502 JM |
1802 | { |
1803 | u32 rpcs = 0; | |
1804 | ||
1805 | /* | |
1806 | * No explicit RPCS request is needed to ensure full | |
1807 | * slice/subslice/EU enablement prior to Gen9. | |
1808 | */ | |
c033666a | 1809 | if (INTEL_GEN(dev_priv) < 9) |
0cea6502 JM |
1810 | return 0; |
1811 | ||
1812 | /* | |
1813 | * Starting in Gen9, render power gating can leave | |
1814 | * slice/subslice/EU in a partially enabled state. We | |
1815 | * must make an explicit request through RPCS for full | |
1816 | * enablement. | |
1817 | */ | |
43b67998 | 1818 | if (INTEL_INFO(dev_priv)->sseu.has_slice_pg) { |
0cea6502 | 1819 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; |
f08a0c92 | 1820 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.slice_mask) << |
0cea6502 JM |
1821 | GEN8_RPCS_S_CNT_SHIFT; |
1822 | rpcs |= GEN8_RPCS_ENABLE; | |
1823 | } | |
1824 | ||
43b67998 | 1825 | if (INTEL_INFO(dev_priv)->sseu.has_subslice_pg) { |
0cea6502 | 1826 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; |
57ec171e | 1827 | rpcs |= hweight8(INTEL_INFO(dev_priv)->sseu.subslice_mask) << |
0cea6502 JM |
1828 | GEN8_RPCS_SS_CNT_SHIFT; |
1829 | rpcs |= GEN8_RPCS_ENABLE; | |
1830 | } | |
1831 | ||
43b67998 ID |
1832 | if (INTEL_INFO(dev_priv)->sseu.has_eu_pg) { |
1833 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << | |
0cea6502 | 1834 | GEN8_RPCS_EU_MIN_SHIFT; |
43b67998 | 1835 | rpcs |= INTEL_INFO(dev_priv)->sseu.eu_per_subslice << |
0cea6502 JM |
1836 | GEN8_RPCS_EU_MAX_SHIFT; |
1837 | rpcs |= GEN8_RPCS_ENABLE; | |
1838 | } | |
1839 | ||
1840 | return rpcs; | |
1841 | } | |
1842 | ||
0bc40be8 | 1843 | static u32 intel_lr_indirect_ctx_offset(struct intel_engine_cs *engine) |
71562919 MT |
1844 | { |
1845 | u32 indirect_ctx_offset; | |
1846 | ||
c033666a | 1847 | switch (INTEL_GEN(engine->i915)) { |
71562919 | 1848 | default: |
c033666a | 1849 | MISSING_CASE(INTEL_GEN(engine->i915)); |
71562919 MT |
1850 | /* fall through */ |
1851 | case 9: | |
1852 | indirect_ctx_offset = | |
1853 | GEN9_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1854 | break; | |
1855 | case 8: | |
1856 | indirect_ctx_offset = | |
1857 | GEN8_CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT; | |
1858 | break; | |
1859 | } | |
1860 | ||
1861 | return indirect_ctx_offset; | |
1862 | } | |
1863 | ||
56e51bf0 | 1864 | static void execlists_init_reg_state(u32 *regs, |
a3aabe86 CW |
1865 | struct i915_gem_context *ctx, |
1866 | struct intel_engine_cs *engine, | |
1867 | struct intel_ring *ring) | |
8670d6f9 | 1868 | { |
a3aabe86 CW |
1869 | struct drm_i915_private *dev_priv = engine->i915; |
1870 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt ?: dev_priv->mm.aliasing_ppgtt; | |
56e51bf0 TU |
1871 | u32 base = engine->mmio_base; |
1872 | bool rcs = engine->id == RCS; | |
1873 | ||
1874 | /* A context is actually a big batch buffer with several | |
1875 | * MI_LOAD_REGISTER_IMM commands followed by (reg, value) pairs. The | |
1876 | * values we are setting here are only for the first context restore: | |
1877 | * on a subsequent save, the GPU will recreate this batchbuffer with new | |
1878 | * values (including all the missing MI_LOAD_REGISTER_IMM commands that | |
1879 | * we are not initializing here). | |
1880 | */ | |
1881 | regs[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(rcs ? 14 : 11) | | |
1882 | MI_LRI_FORCE_POSTED; | |
1883 | ||
1884 | CTX_REG(regs, CTX_CONTEXT_CONTROL, RING_CONTEXT_CONTROL(engine), | |
1885 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | | |
1886 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | | |
1887 | (HAS_RESOURCE_STREAMER(dev_priv) ? | |
1888 | CTX_CTRL_RS_CTX_ENABLE : 0))); | |
1889 | CTX_REG(regs, CTX_RING_HEAD, RING_HEAD(base), 0); | |
1890 | CTX_REG(regs, CTX_RING_TAIL, RING_TAIL(base), 0); | |
1891 | CTX_REG(regs, CTX_RING_BUFFER_START, RING_START(base), 0); | |
1892 | CTX_REG(regs, CTX_RING_BUFFER_CONTROL, RING_CTL(base), | |
1893 | RING_CTL_SIZE(ring->size) | RING_VALID); | |
1894 | CTX_REG(regs, CTX_BB_HEAD_U, RING_BBADDR_UDW(base), 0); | |
1895 | CTX_REG(regs, CTX_BB_HEAD_L, RING_BBADDR(base), 0); | |
1896 | CTX_REG(regs, CTX_BB_STATE, RING_BBSTATE(base), RING_BB_PPGTT); | |
1897 | CTX_REG(regs, CTX_SECOND_BB_HEAD_U, RING_SBBADDR_UDW(base), 0); | |
1898 | CTX_REG(regs, CTX_SECOND_BB_HEAD_L, RING_SBBADDR(base), 0); | |
1899 | CTX_REG(regs, CTX_SECOND_BB_STATE, RING_SBBSTATE(base), 0); | |
1900 | if (rcs) { | |
1901 | CTX_REG(regs, CTX_BB_PER_CTX_PTR, RING_BB_PER_CTX_PTR(base), 0); | |
1902 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX, RING_INDIRECT_CTX(base), 0); | |
1903 | CTX_REG(regs, CTX_RCS_INDIRECT_CTX_OFFSET, | |
1904 | RING_INDIRECT_CTX_OFFSET(base), 0); | |
8670d6f9 | 1905 | |
48bb74e4 | 1906 | if (engine->wa_ctx.vma) { |
0bc40be8 | 1907 | struct i915_ctx_workarounds *wa_ctx = &engine->wa_ctx; |
bde13ebd | 1908 | u32 ggtt_offset = i915_ggtt_offset(wa_ctx->vma); |
17ee950d | 1909 | |
56e51bf0 | 1910 | regs[CTX_RCS_INDIRECT_CTX + 1] = |
097d4f1c TU |
1911 | (ggtt_offset + wa_ctx->indirect_ctx.offset) | |
1912 | (wa_ctx->indirect_ctx.size / CACHELINE_BYTES); | |
17ee950d | 1913 | |
56e51bf0 | 1914 | regs[CTX_RCS_INDIRECT_CTX_OFFSET + 1] = |
0bc40be8 | 1915 | intel_lr_indirect_ctx_offset(engine) << 6; |
17ee950d | 1916 | |
56e51bf0 | 1917 | regs[CTX_BB_PER_CTX_PTR + 1] = |
097d4f1c | 1918 | (ggtt_offset + wa_ctx->per_ctx.offset) | 0x01; |
17ee950d | 1919 | } |
8670d6f9 | 1920 | } |
56e51bf0 TU |
1921 | |
1922 | regs[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9) | MI_LRI_FORCE_POSTED; | |
1923 | ||
1924 | CTX_REG(regs, CTX_CTX_TIMESTAMP, RING_CTX_TIMESTAMP(base), 0); | |
0d925ea0 | 1925 | /* PDP values well be assigned later if needed */ |
56e51bf0 TU |
1926 | CTX_REG(regs, CTX_PDP3_UDW, GEN8_RING_PDP_UDW(engine, 3), 0); |
1927 | CTX_REG(regs, CTX_PDP3_LDW, GEN8_RING_PDP_LDW(engine, 3), 0); | |
1928 | CTX_REG(regs, CTX_PDP2_UDW, GEN8_RING_PDP_UDW(engine, 2), 0); | |
1929 | CTX_REG(regs, CTX_PDP2_LDW, GEN8_RING_PDP_LDW(engine, 2), 0); | |
1930 | CTX_REG(regs, CTX_PDP1_UDW, GEN8_RING_PDP_UDW(engine, 1), 0); | |
1931 | CTX_REG(regs, CTX_PDP1_LDW, GEN8_RING_PDP_LDW(engine, 1), 0); | |
1932 | CTX_REG(regs, CTX_PDP0_UDW, GEN8_RING_PDP_UDW(engine, 0), 0); | |
1933 | CTX_REG(regs, CTX_PDP0_LDW, GEN8_RING_PDP_LDW(engine, 0), 0); | |
d7b2633d | 1934 | |
949e8ab3 | 1935 | if (ppgtt && i915_vm_is_48bit(&ppgtt->base)) { |
2dba3239 MT |
1936 | /* 64b PPGTT (48bit canonical) |
1937 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
1938 | * other PDP Descriptors are ignored. | |
1939 | */ | |
56e51bf0 | 1940 | ASSIGN_CTX_PML4(ppgtt, regs); |
2dba3239 MT |
1941 | } |
1942 | ||
56e51bf0 TU |
1943 | if (rcs) { |
1944 | regs[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
1945 | CTX_REG(regs, CTX_R_PWR_CLK_STATE, GEN8_R_PWR_CLK_STATE, | |
1946 | make_rpcs(dev_priv)); | |
8670d6f9 | 1947 | } |
a3aabe86 CW |
1948 | } |
1949 | ||
1950 | static int | |
1951 | populate_lr_context(struct i915_gem_context *ctx, | |
1952 | struct drm_i915_gem_object *ctx_obj, | |
1953 | struct intel_engine_cs *engine, | |
1954 | struct intel_ring *ring) | |
1955 | { | |
1956 | void *vaddr; | |
1957 | int ret; | |
1958 | ||
1959 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); | |
1960 | if (ret) { | |
1961 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
1962 | return ret; | |
1963 | } | |
1964 | ||
1965 | vaddr = i915_gem_object_pin_map(ctx_obj, I915_MAP_WB); | |
1966 | if (IS_ERR(vaddr)) { | |
1967 | ret = PTR_ERR(vaddr); | |
1968 | DRM_DEBUG_DRIVER("Could not map object pages! (%d)\n", ret); | |
1969 | return ret; | |
1970 | } | |
a4f5ea64 | 1971 | ctx_obj->mm.dirty = true; |
a3aabe86 CW |
1972 | |
1973 | /* The second page of the context object contains some fields which must | |
1974 | * be set up prior to the first execution. */ | |
1975 | ||
1976 | execlists_init_reg_state(vaddr + LRC_STATE_PN * PAGE_SIZE, | |
1977 | ctx, engine, ring); | |
8670d6f9 | 1978 | |
7d774cac | 1979 | i915_gem_object_unpin_map(ctx_obj); |
8670d6f9 OM |
1980 | |
1981 | return 0; | |
1982 | } | |
1983 | ||
e2efd130 | 1984 | static int execlists_context_deferred_alloc(struct i915_gem_context *ctx, |
978f1e09 | 1985 | struct intel_engine_cs *engine) |
ede7d42b | 1986 | { |
8c857917 | 1987 | struct drm_i915_gem_object *ctx_obj; |
9021ad03 | 1988 | struct intel_context *ce = &ctx->engine[engine->id]; |
bf3783e5 | 1989 | struct i915_vma *vma; |
8c857917 | 1990 | uint32_t context_size; |
7e37f889 | 1991 | struct intel_ring *ring; |
8c857917 OM |
1992 | int ret; |
1993 | ||
9021ad03 | 1994 | WARN_ON(ce->state); |
ede7d42b | 1995 | |
63ffbcda | 1996 | context_size = round_up(engine->context_size, I915_GTT_PAGE_SIZE); |
8c857917 | 1997 | |
d1675198 AD |
1998 | /* One extra page as the sharing data between driver and GuC */ |
1999 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2000 | ||
12d79d78 | 2001 | ctx_obj = i915_gem_object_create(ctx->i915, context_size); |
fe3db79b | 2002 | if (IS_ERR(ctx_obj)) { |
3126a660 | 2003 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); |
fe3db79b | 2004 | return PTR_ERR(ctx_obj); |
8c857917 OM |
2005 | } |
2006 | ||
a01cb37a | 2007 | vma = i915_vma_instance(ctx_obj, &ctx->i915->ggtt.base, NULL); |
bf3783e5 CW |
2008 | if (IS_ERR(vma)) { |
2009 | ret = PTR_ERR(vma); | |
2010 | goto error_deref_obj; | |
2011 | } | |
2012 | ||
7e37f889 | 2013 | ring = intel_engine_create_ring(engine, ctx->ring_size); |
dca33ecc CW |
2014 | if (IS_ERR(ring)) { |
2015 | ret = PTR_ERR(ring); | |
e84fe803 | 2016 | goto error_deref_obj; |
8670d6f9 OM |
2017 | } |
2018 | ||
dca33ecc | 2019 | ret = populate_lr_context(ctx, ctx_obj, engine, ring); |
8670d6f9 OM |
2020 | if (ret) { |
2021 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
dca33ecc | 2022 | goto error_ring_free; |
84c2377f OM |
2023 | } |
2024 | ||
dca33ecc | 2025 | ce->ring = ring; |
bf3783e5 | 2026 | ce->state = vma; |
0d402a24 | 2027 | ce->initialised |= engine->init_context == NULL; |
ede7d42b OM |
2028 | |
2029 | return 0; | |
8670d6f9 | 2030 | |
dca33ecc | 2031 | error_ring_free: |
7e37f889 | 2032 | intel_ring_free(ring); |
e84fe803 | 2033 | error_deref_obj: |
f8c417cd | 2034 | i915_gem_object_put(ctx_obj); |
8670d6f9 | 2035 | return ret; |
ede7d42b | 2036 | } |
3e5b6f05 | 2037 | |
821ed7df | 2038 | void intel_lr_context_resume(struct drm_i915_private *dev_priv) |
3e5b6f05 | 2039 | { |
e2f80391 | 2040 | struct intel_engine_cs *engine; |
bafb2f7d | 2041 | struct i915_gem_context *ctx; |
3b3f1650 | 2042 | enum intel_engine_id id; |
bafb2f7d CW |
2043 | |
2044 | /* Because we emit WA_TAIL_DWORDS there may be a disparity | |
2045 | * between our bookkeeping in ce->ring->head and ce->ring->tail and | |
2046 | * that stored in context. As we only write new commands from | |
2047 | * ce->ring->tail onwards, everything before that is junk. If the GPU | |
2048 | * starts reading from its RING_HEAD from the context, it may try to | |
2049 | * execute that junk and die. | |
2050 | * | |
2051 | * So to avoid that we reset the context images upon resume. For | |
2052 | * simplicity, we just zero everything out. | |
2053 | */ | |
2054 | list_for_each_entry(ctx, &dev_priv->context_list, link) { | |
3b3f1650 | 2055 | for_each_engine(engine, dev_priv, id) { |
bafb2f7d CW |
2056 | struct intel_context *ce = &ctx->engine[engine->id]; |
2057 | u32 *reg; | |
3e5b6f05 | 2058 | |
bafb2f7d CW |
2059 | if (!ce->state) |
2060 | continue; | |
7d774cac | 2061 | |
bafb2f7d CW |
2062 | reg = i915_gem_object_pin_map(ce->state->obj, |
2063 | I915_MAP_WB); | |
2064 | if (WARN_ON(IS_ERR(reg))) | |
2065 | continue; | |
3e5b6f05 | 2066 | |
bafb2f7d CW |
2067 | reg += LRC_STATE_PN * PAGE_SIZE / sizeof(*reg); |
2068 | reg[CTX_RING_HEAD+1] = 0; | |
2069 | reg[CTX_RING_TAIL+1] = 0; | |
3e5b6f05 | 2070 | |
a4f5ea64 | 2071 | ce->state->obj->mm.dirty = true; |
bafb2f7d | 2072 | i915_gem_object_unpin_map(ce->state->obj); |
3e5b6f05 | 2073 | |
e6ba9992 | 2074 | intel_ring_reset(ce->ring, 0); |
bafb2f7d | 2075 | } |
3e5b6f05 TD |
2076 | } |
2077 | } |