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b20385f1 OM |
1 | /* |
2 | * Copyright © 2014 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Ben Widawsky <ben@bwidawsk.net> | |
25 | * Michel Thierry <michel.thierry@intel.com> | |
26 | * Thomas Daniel <thomas.daniel@intel.com> | |
27 | * Oscar Mateo <oscar.mateo@intel.com> | |
28 | * | |
29 | */ | |
30 | ||
73e4d07f OM |
31 | /** |
32 | * DOC: Logical Rings, Logical Ring Contexts and Execlists | |
33 | * | |
34 | * Motivation: | |
b20385f1 OM |
35 | * GEN8 brings an expansion of the HW contexts: "Logical Ring Contexts". |
36 | * These expanded contexts enable a number of new abilities, especially | |
37 | * "Execlists" (also implemented in this file). | |
38 | * | |
73e4d07f OM |
39 | * One of the main differences with the legacy HW contexts is that logical |
40 | * ring contexts incorporate many more things to the context's state, like | |
41 | * PDPs or ringbuffer control registers: | |
42 | * | |
43 | * The reason why PDPs are included in the context is straightforward: as | |
44 | * PPGTTs (per-process GTTs) are actually per-context, having the PDPs | |
45 | * contained there mean you don't need to do a ppgtt->switch_mm yourself, | |
46 | * instead, the GPU will do it for you on the context switch. | |
47 | * | |
48 | * But, what about the ringbuffer control registers (head, tail, etc..)? | |
49 | * shouldn't we just need a set of those per engine command streamer? This is | |
50 | * where the name "Logical Rings" starts to make sense: by virtualizing the | |
51 | * rings, the engine cs shifts to a new "ring buffer" with every context | |
52 | * switch. When you want to submit a workload to the GPU you: A) choose your | |
53 | * context, B) find its appropriate virtualized ring, C) write commands to it | |
54 | * and then, finally, D) tell the GPU to switch to that context. | |
55 | * | |
56 | * Instead of the legacy MI_SET_CONTEXT, the way you tell the GPU to switch | |
57 | * to a contexts is via a context execution list, ergo "Execlists". | |
58 | * | |
59 | * LRC implementation: | |
60 | * Regarding the creation of contexts, we have: | |
61 | * | |
62 | * - One global default context. | |
63 | * - One local default context for each opened fd. | |
64 | * - One local extra context for each context create ioctl call. | |
65 | * | |
66 | * Now that ringbuffers belong per-context (and not per-engine, like before) | |
67 | * and that contexts are uniquely tied to a given engine (and not reusable, | |
68 | * like before) we need: | |
69 | * | |
70 | * - One ringbuffer per-engine inside each context. | |
71 | * - One backing object per-engine inside each context. | |
72 | * | |
73 | * The global default context starts its life with these new objects fully | |
74 | * allocated and populated. The local default context for each opened fd is | |
75 | * more complex, because we don't know at creation time which engine is going | |
76 | * to use them. To handle this, we have implemented a deferred creation of LR | |
77 | * contexts: | |
78 | * | |
79 | * The local context starts its life as a hollow or blank holder, that only | |
80 | * gets populated for a given engine once we receive an execbuffer. If later | |
81 | * on we receive another execbuffer ioctl for the same context but a different | |
82 | * engine, we allocate/populate a new ringbuffer and context backing object and | |
83 | * so on. | |
84 | * | |
85 | * Finally, regarding local contexts created using the ioctl call: as they are | |
86 | * only allowed with the render ring, we can allocate & populate them right | |
87 | * away (no need to defer anything, at least for now). | |
88 | * | |
89 | * Execlists implementation: | |
b20385f1 OM |
90 | * Execlists are the new method by which, on gen8+ hardware, workloads are |
91 | * submitted for execution (as opposed to the legacy, ringbuffer-based, method). | |
73e4d07f OM |
92 | * This method works as follows: |
93 | * | |
94 | * When a request is committed, its commands (the BB start and any leading or | |
95 | * trailing commands, like the seqno breadcrumbs) are placed in the ringbuffer | |
96 | * for the appropriate context. The tail pointer in the hardware context is not | |
97 | * updated at this time, but instead, kept by the driver in the ringbuffer | |
98 | * structure. A structure representing this request is added to a request queue | |
99 | * for the appropriate engine: this structure contains a copy of the context's | |
100 | * tail after the request was written to the ring buffer and a pointer to the | |
101 | * context itself. | |
102 | * | |
103 | * If the engine's request queue was empty before the request was added, the | |
104 | * queue is processed immediately. Otherwise the queue will be processed during | |
105 | * a context switch interrupt. In any case, elements on the queue will get sent | |
106 | * (in pairs) to the GPU's ExecLists Submit Port (ELSP, for short) with a | |
107 | * globally unique 20-bits submission ID. | |
108 | * | |
109 | * When execution of a request completes, the GPU updates the context status | |
110 | * buffer with a context complete event and generates a context switch interrupt. | |
111 | * During the interrupt handling, the driver examines the events in the buffer: | |
112 | * for each context complete event, if the announced ID matches that on the head | |
113 | * of the request queue, then that request is retired and removed from the queue. | |
114 | * | |
115 | * After processing, if any requests were retired and the queue is not empty | |
116 | * then a new execution list can be submitted. The two requests at the front of | |
117 | * the queue are next to be submitted but since a context may not occur twice in | |
118 | * an execution list, if subsequent requests have the same ID as the first then | |
119 | * the two requests must be combined. This is done simply by discarding requests | |
120 | * at the head of the queue until either only one requests is left (in which case | |
121 | * we use a NULL second context) or the first two requests have unique IDs. | |
122 | * | |
123 | * By always executing the first two requests in the queue the driver ensures | |
124 | * that the GPU is kept as busy as possible. In the case where a single context | |
125 | * completes but a second context is still executing, the request for this second | |
126 | * context will be at the head of the queue when we remove the first one. This | |
127 | * request will then be resubmitted along with a new request for a different context, | |
128 | * which will cause the hardware to continue executing the second request and queue | |
129 | * the new request (the GPU detects the condition of a context getting preempted | |
130 | * with the same context and optimizes the context switch flow by not doing | |
131 | * preemption, but just sampling the new tail pointer). | |
132 | * | |
b20385f1 OM |
133 | */ |
134 | ||
135 | #include <drm/drmP.h> | |
136 | #include <drm/i915_drm.h> | |
137 | #include "i915_drv.h" | |
3bbaba0c | 138 | #include "intel_mocs.h" |
127f1003 | 139 | |
468c6816 | 140 | #define GEN9_LR_CONTEXT_RENDER_SIZE (22 * PAGE_SIZE) |
8c857917 OM |
141 | #define GEN8_LR_CONTEXT_RENDER_SIZE (20 * PAGE_SIZE) |
142 | #define GEN8_LR_CONTEXT_OTHER_SIZE (2 * PAGE_SIZE) | |
143 | ||
e981e7b1 TD |
144 | #define RING_EXECLIST_QFULL (1 << 0x2) |
145 | #define RING_EXECLIST1_VALID (1 << 0x3) | |
146 | #define RING_EXECLIST0_VALID (1 << 0x4) | |
147 | #define RING_EXECLIST_ACTIVE_STATUS (3 << 0xE) | |
148 | #define RING_EXECLIST1_ACTIVE (1 << 0x11) | |
149 | #define RING_EXECLIST0_ACTIVE (1 << 0x12) | |
150 | ||
151 | #define GEN8_CTX_STATUS_IDLE_ACTIVE (1 << 0) | |
152 | #define GEN8_CTX_STATUS_PREEMPTED (1 << 1) | |
153 | #define GEN8_CTX_STATUS_ELEMENT_SWITCH (1 << 2) | |
154 | #define GEN8_CTX_STATUS_ACTIVE_IDLE (1 << 3) | |
155 | #define GEN8_CTX_STATUS_COMPLETE (1 << 4) | |
156 | #define GEN8_CTX_STATUS_LITE_RESTORE (1 << 15) | |
8670d6f9 OM |
157 | |
158 | #define CTX_LRI_HEADER_0 0x01 | |
159 | #define CTX_CONTEXT_CONTROL 0x02 | |
160 | #define CTX_RING_HEAD 0x04 | |
161 | #define CTX_RING_TAIL 0x06 | |
162 | #define CTX_RING_BUFFER_START 0x08 | |
163 | #define CTX_RING_BUFFER_CONTROL 0x0a | |
164 | #define CTX_BB_HEAD_U 0x0c | |
165 | #define CTX_BB_HEAD_L 0x0e | |
166 | #define CTX_BB_STATE 0x10 | |
167 | #define CTX_SECOND_BB_HEAD_U 0x12 | |
168 | #define CTX_SECOND_BB_HEAD_L 0x14 | |
169 | #define CTX_SECOND_BB_STATE 0x16 | |
170 | #define CTX_BB_PER_CTX_PTR 0x18 | |
171 | #define CTX_RCS_INDIRECT_CTX 0x1a | |
172 | #define CTX_RCS_INDIRECT_CTX_OFFSET 0x1c | |
173 | #define CTX_LRI_HEADER_1 0x21 | |
174 | #define CTX_CTX_TIMESTAMP 0x22 | |
175 | #define CTX_PDP3_UDW 0x24 | |
176 | #define CTX_PDP3_LDW 0x26 | |
177 | #define CTX_PDP2_UDW 0x28 | |
178 | #define CTX_PDP2_LDW 0x2a | |
179 | #define CTX_PDP1_UDW 0x2c | |
180 | #define CTX_PDP1_LDW 0x2e | |
181 | #define CTX_PDP0_UDW 0x30 | |
182 | #define CTX_PDP0_LDW 0x32 | |
183 | #define CTX_LRI_HEADER_2 0x41 | |
184 | #define CTX_R_PWR_CLK_STATE 0x42 | |
185 | #define CTX_GPGPU_CSR_BASE_ADDRESS 0x44 | |
186 | ||
84b790f8 BW |
187 | #define GEN8_CTX_VALID (1<<0) |
188 | #define GEN8_CTX_FORCE_PD_RESTORE (1<<1) | |
189 | #define GEN8_CTX_FORCE_RESTORE (1<<2) | |
190 | #define GEN8_CTX_L3LLC_COHERENT (1<<5) | |
191 | #define GEN8_CTX_PRIVILEGE (1<<8) | |
e5815a2e MT |
192 | |
193 | #define ASSIGN_CTX_PDP(ppgtt, reg_state, n) { \ | |
d852c7bf | 194 | const u64 _addr = i915_page_dir_dma_addr((ppgtt), (n)); \ |
e5815a2e MT |
195 | reg_state[CTX_PDP ## n ## _UDW+1] = upper_32_bits(_addr); \ |
196 | reg_state[CTX_PDP ## n ## _LDW+1] = lower_32_bits(_addr); \ | |
197 | } | |
198 | ||
2dba3239 MT |
199 | #define ASSIGN_CTX_PML4(ppgtt, reg_state) { \ |
200 | reg_state[CTX_PDP0_UDW + 1] = upper_32_bits(px_dma(&ppgtt->pml4)); \ | |
201 | reg_state[CTX_PDP0_LDW + 1] = lower_32_bits(px_dma(&ppgtt->pml4)); \ | |
202 | } | |
203 | ||
84b790f8 BW |
204 | enum { |
205 | ADVANCED_CONTEXT = 0, | |
2dba3239 | 206 | LEGACY_32B_CONTEXT, |
84b790f8 BW |
207 | ADVANCED_AD_CONTEXT, |
208 | LEGACY_64B_CONTEXT | |
209 | }; | |
2dba3239 MT |
210 | #define GEN8_CTX_ADDRESSING_MODE_SHIFT 3 |
211 | #define GEN8_CTX_ADDRESSING_MODE(dev) (USES_FULL_48BIT_PPGTT(dev) ?\ | |
212 | LEGACY_64B_CONTEXT :\ | |
213 | LEGACY_32B_CONTEXT) | |
84b790f8 BW |
214 | enum { |
215 | FAULT_AND_HANG = 0, | |
216 | FAULT_AND_HALT, /* Debug only */ | |
217 | FAULT_AND_STREAM, | |
218 | FAULT_AND_CONTINUE /* Unsupported */ | |
219 | }; | |
220 | #define GEN8_CTX_ID_SHIFT 32 | |
17ee950d | 221 | #define CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT 0x17 |
84b790f8 | 222 | |
8ba319da | 223 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq); |
e84fe803 NH |
224 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
225 | struct drm_i915_gem_object *default_ctx_obj); | |
226 | ||
7ba717cf | 227 | |
73e4d07f OM |
228 | /** |
229 | * intel_sanitize_enable_execlists() - sanitize i915.enable_execlists | |
230 | * @dev: DRM device. | |
231 | * @enable_execlists: value of i915.enable_execlists module parameter. | |
232 | * | |
233 | * Only certain platforms support Execlists (the prerequisites being | |
27401d12 | 234 | * support for Logical Ring Contexts and Aliasing PPGTT or better). |
73e4d07f OM |
235 | * |
236 | * Return: 1 if Execlists is supported and has to be enabled. | |
237 | */ | |
127f1003 OM |
238 | int intel_sanitize_enable_execlists(struct drm_device *dev, int enable_execlists) |
239 | { | |
bd84b1e9 DV |
240 | WARN_ON(i915.enable_ppgtt == -1); |
241 | ||
a0bd6c31 ZL |
242 | /* On platforms with execlist available, vGPU will only |
243 | * support execlist mode, no ring buffer mode. | |
244 | */ | |
245 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && intel_vgpu_active(dev)) | |
246 | return 1; | |
247 | ||
70ee45e1 DL |
248 | if (INTEL_INFO(dev)->gen >= 9) |
249 | return 1; | |
250 | ||
127f1003 OM |
251 | if (enable_execlists == 0) |
252 | return 0; | |
253 | ||
14bf993e OM |
254 | if (HAS_LOGICAL_RING_CONTEXTS(dev) && USES_PPGTT(dev) && |
255 | i915.use_mmio_flip >= 0) | |
127f1003 OM |
256 | return 1; |
257 | ||
258 | return 0; | |
259 | } | |
ede7d42b | 260 | |
73e4d07f OM |
261 | /** |
262 | * intel_execlists_ctx_id() - get the Execlists Context ID | |
263 | * @ctx_obj: Logical Ring Context backing object. | |
264 | * | |
265 | * Do not confuse with ctx->id! Unfortunately we have a name overload | |
266 | * here: the old context ID we pass to userspace as a handler so that | |
267 | * they can refer to a context, and the new context ID we pass to the | |
268 | * ELSP so that the GPU can inform us of the context status via | |
269 | * interrupts. | |
270 | * | |
271 | * Return: 20-bits globally unique context ID. | |
272 | */ | |
84b790f8 BW |
273 | u32 intel_execlists_ctx_id(struct drm_i915_gem_object *ctx_obj) |
274 | { | |
d1675198 AD |
275 | u32 lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
276 | LRC_PPHWSP_PN * PAGE_SIZE; | |
84b790f8 BW |
277 | |
278 | /* LRCA is required to be 4K aligned so the more significant 20 bits | |
279 | * are globally unique */ | |
280 | return lrca >> 12; | |
281 | } | |
282 | ||
5af05fef MT |
283 | static bool disable_lite_restore_wa(struct intel_engine_cs *ring) |
284 | { | |
285 | struct drm_device *dev = ring->dev; | |
286 | ||
287 | return ((IS_SKYLAKE(dev) && INTEL_REVID(dev) <= SKL_REVID_B0) || | |
288 | (IS_BROXTON(dev) && INTEL_REVID(dev) == BXT_REVID_A0)) && | |
289 | (ring->id == VCS || ring->id == VCS2); | |
290 | } | |
291 | ||
919f1f55 DG |
292 | uint64_t intel_lr_context_descriptor(struct intel_context *ctx, |
293 | struct intel_engine_cs *ring) | |
84b790f8 | 294 | { |
919f1f55 | 295 | struct drm_i915_gem_object *ctx_obj = ctx->engine[ring->id].state; |
84b790f8 | 296 | uint64_t desc; |
d1675198 AD |
297 | uint64_t lrca = i915_gem_obj_ggtt_offset(ctx_obj) + |
298 | LRC_PPHWSP_PN * PAGE_SIZE; | |
acdd884a MT |
299 | |
300 | WARN_ON(lrca & 0xFFFFFFFF00000FFFULL); | |
84b790f8 BW |
301 | |
302 | desc = GEN8_CTX_VALID; | |
2dba3239 | 303 | desc |= GEN8_CTX_ADDRESSING_MODE(dev) << GEN8_CTX_ADDRESSING_MODE_SHIFT; |
51847fb9 AS |
304 | if (IS_GEN8(ctx_obj->base.dev)) |
305 | desc |= GEN8_CTX_L3LLC_COHERENT; | |
84b790f8 BW |
306 | desc |= GEN8_CTX_PRIVILEGE; |
307 | desc |= lrca; | |
308 | desc |= (u64)intel_execlists_ctx_id(ctx_obj) << GEN8_CTX_ID_SHIFT; | |
309 | ||
310 | /* TODO: WaDisableLiteRestore when we start using semaphore | |
311 | * signalling between Command Streamers */ | |
312 | /* desc |= GEN8_CTX_FORCE_RESTORE; */ | |
313 | ||
203a571b | 314 | /* WaEnableForceRestoreInCtxtDescForVCS:skl */ |
ec72d588 | 315 | /* WaEnableForceRestoreInCtxtDescForVCS:bxt */ |
5af05fef | 316 | if (disable_lite_restore_wa(ring)) |
203a571b NH |
317 | desc |= GEN8_CTX_FORCE_RESTORE; |
318 | ||
84b790f8 BW |
319 | return desc; |
320 | } | |
321 | ||
cc3c4253 MK |
322 | static void execlists_elsp_write(struct drm_i915_gem_request *rq0, |
323 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 324 | { |
cc3c4253 MK |
325 | |
326 | struct intel_engine_cs *ring = rq0->ring; | |
6e7cc470 TU |
327 | struct drm_device *dev = ring->dev; |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1cff8cc3 | 329 | uint64_t desc[2]; |
84b790f8 | 330 | |
1cff8cc3 | 331 | if (rq1) { |
919f1f55 | 332 | desc[1] = intel_lr_context_descriptor(rq1->ctx, rq1->ring); |
1cff8cc3 MK |
333 | rq1->elsp_submitted++; |
334 | } else { | |
335 | desc[1] = 0; | |
336 | } | |
84b790f8 | 337 | |
919f1f55 | 338 | desc[0] = intel_lr_context_descriptor(rq0->ctx, rq0->ring); |
1cff8cc3 | 339 | rq0->elsp_submitted++; |
84b790f8 | 340 | |
1cff8cc3 | 341 | /* You must always write both descriptors in the order below. */ |
a6111f7b CW |
342 | spin_lock(&dev_priv->uncore.lock); |
343 | intel_uncore_forcewake_get__locked(dev_priv, FORCEWAKE_ALL); | |
1cff8cc3 MK |
344 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[1])); |
345 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[1])); | |
6daccb0b | 346 | |
1cff8cc3 | 347 | I915_WRITE_FW(RING_ELSP(ring), upper_32_bits(desc[0])); |
84b790f8 | 348 | /* The context is automatically loaded after the following */ |
1cff8cc3 | 349 | I915_WRITE_FW(RING_ELSP(ring), lower_32_bits(desc[0])); |
84b790f8 | 350 | |
1cff8cc3 | 351 | /* ELSP is a wo register, use another nearby reg for posting */ |
a6111f7b CW |
352 | POSTING_READ_FW(RING_EXECLIST_STATUS(ring)); |
353 | intel_uncore_forcewake_put__locked(dev_priv, FORCEWAKE_ALL); | |
354 | spin_unlock(&dev_priv->uncore.lock); | |
84b790f8 BW |
355 | } |
356 | ||
05d9824b | 357 | static int execlists_update_context(struct drm_i915_gem_request *rq) |
ae1250b9 | 358 | { |
05d9824b MK |
359 | struct intel_engine_cs *ring = rq->ring; |
360 | struct i915_hw_ppgtt *ppgtt = rq->ctx->ppgtt; | |
361 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
362 | struct drm_i915_gem_object *rb_obj = rq->ringbuf->obj; | |
ae1250b9 OM |
363 | struct page *page; |
364 | uint32_t *reg_state; | |
365 | ||
05d9824b MK |
366 | BUG_ON(!ctx_obj); |
367 | WARN_ON(!i915_gem_obj_is_pinned(ctx_obj)); | |
368 | WARN_ON(!i915_gem_obj_is_pinned(rb_obj)); | |
369 | ||
d1675198 | 370 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
ae1250b9 OM |
371 | reg_state = kmap_atomic(page); |
372 | ||
05d9824b MK |
373 | reg_state[CTX_RING_TAIL+1] = rq->tail; |
374 | reg_state[CTX_RING_BUFFER_START+1] = i915_gem_obj_ggtt_offset(rb_obj); | |
ae1250b9 | 375 | |
2dba3239 MT |
376 | if (ppgtt && !USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
377 | /* True 32b PPGTT with dynamic page allocation: update PDP | |
378 | * registers and point the unallocated PDPs to scratch page. | |
379 | * PML4 is allocated during ppgtt init, so this is not needed | |
380 | * in 48-bit mode. | |
381 | */ | |
d7b2633d MT |
382 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); |
383 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
384 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
385 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
386 | } | |
387 | ||
ae1250b9 OM |
388 | kunmap_atomic(reg_state); |
389 | ||
390 | return 0; | |
391 | } | |
392 | ||
d8cb8875 MK |
393 | static void execlists_submit_requests(struct drm_i915_gem_request *rq0, |
394 | struct drm_i915_gem_request *rq1) | |
84b790f8 | 395 | { |
05d9824b | 396 | execlists_update_context(rq0); |
d8cb8875 | 397 | |
cc3c4253 | 398 | if (rq1) |
05d9824b | 399 | execlists_update_context(rq1); |
84b790f8 | 400 | |
cc3c4253 | 401 | execlists_elsp_write(rq0, rq1); |
84b790f8 BW |
402 | } |
403 | ||
acdd884a MT |
404 | static void execlists_context_unqueue(struct intel_engine_cs *ring) |
405 | { | |
6d3d8274 NH |
406 | struct drm_i915_gem_request *req0 = NULL, *req1 = NULL; |
407 | struct drm_i915_gem_request *cursor = NULL, *tmp = NULL; | |
e981e7b1 TD |
408 | |
409 | assert_spin_locked(&ring->execlist_lock); | |
acdd884a | 410 | |
779949f4 PA |
411 | /* |
412 | * If irqs are not active generate a warning as batches that finish | |
413 | * without the irqs may get lost and a GPU Hang may occur. | |
414 | */ | |
415 | WARN_ON(!intel_irqs_enabled(ring->dev->dev_private)); | |
416 | ||
acdd884a MT |
417 | if (list_empty(&ring->execlist_queue)) |
418 | return; | |
419 | ||
420 | /* Try to read in pairs */ | |
421 | list_for_each_entry_safe(cursor, tmp, &ring->execlist_queue, | |
422 | execlist_link) { | |
423 | if (!req0) { | |
424 | req0 = cursor; | |
6d3d8274 | 425 | } else if (req0->ctx == cursor->ctx) { |
acdd884a MT |
426 | /* Same ctx: ignore first request, as second request |
427 | * will update tail past first request's workload */ | |
e1fee72c | 428 | cursor->elsp_submitted = req0->elsp_submitted; |
acdd884a | 429 | list_del(&req0->execlist_link); |
c86ee3a9 TD |
430 | list_add_tail(&req0->execlist_link, |
431 | &ring->execlist_retired_req_list); | |
acdd884a MT |
432 | req0 = cursor; |
433 | } else { | |
434 | req1 = cursor; | |
435 | break; | |
436 | } | |
437 | } | |
438 | ||
53292cdb MT |
439 | if (IS_GEN8(ring->dev) || IS_GEN9(ring->dev)) { |
440 | /* | |
441 | * WaIdleLiteRestore: make sure we never cause a lite | |
442 | * restore with HEAD==TAIL | |
443 | */ | |
d63f820f | 444 | if (req0->elsp_submitted) { |
53292cdb MT |
445 | /* |
446 | * Apply the wa NOOPS to prevent ring:HEAD == req:TAIL | |
447 | * as we resubmit the request. See gen8_emit_request() | |
448 | * for where we prepare the padding after the end of the | |
449 | * request. | |
450 | */ | |
451 | struct intel_ringbuffer *ringbuf; | |
452 | ||
453 | ringbuf = req0->ctx->engine[ring->id].ringbuf; | |
454 | req0->tail += 8; | |
455 | req0->tail &= ringbuf->size - 1; | |
456 | } | |
457 | } | |
458 | ||
e1fee72c OM |
459 | WARN_ON(req1 && req1->elsp_submitted); |
460 | ||
d8cb8875 | 461 | execlists_submit_requests(req0, req1); |
acdd884a MT |
462 | } |
463 | ||
e981e7b1 TD |
464 | static bool execlists_check_remove_request(struct intel_engine_cs *ring, |
465 | u32 request_id) | |
466 | { | |
6d3d8274 | 467 | struct drm_i915_gem_request *head_req; |
e981e7b1 TD |
468 | |
469 | assert_spin_locked(&ring->execlist_lock); | |
470 | ||
471 | head_req = list_first_entry_or_null(&ring->execlist_queue, | |
6d3d8274 | 472 | struct drm_i915_gem_request, |
e981e7b1 TD |
473 | execlist_link); |
474 | ||
475 | if (head_req != NULL) { | |
476 | struct drm_i915_gem_object *ctx_obj = | |
6d3d8274 | 477 | head_req->ctx->engine[ring->id].state; |
e981e7b1 | 478 | if (intel_execlists_ctx_id(ctx_obj) == request_id) { |
e1fee72c OM |
479 | WARN(head_req->elsp_submitted == 0, |
480 | "Never submitted head request\n"); | |
481 | ||
482 | if (--head_req->elsp_submitted <= 0) { | |
483 | list_del(&head_req->execlist_link); | |
c86ee3a9 TD |
484 | list_add_tail(&head_req->execlist_link, |
485 | &ring->execlist_retired_req_list); | |
e1fee72c OM |
486 | return true; |
487 | } | |
e981e7b1 TD |
488 | } |
489 | } | |
490 | ||
491 | return false; | |
492 | } | |
493 | ||
73e4d07f | 494 | /** |
3f7531c3 | 495 | * intel_lrc_irq_handler() - handle Context Switch interrupts |
73e4d07f OM |
496 | * @ring: Engine Command Streamer to handle. |
497 | * | |
498 | * Check the unread Context Status Buffers and manage the submission of new | |
499 | * contexts to the ELSP accordingly. | |
500 | */ | |
3f7531c3 | 501 | void intel_lrc_irq_handler(struct intel_engine_cs *ring) |
e981e7b1 TD |
502 | { |
503 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
504 | u32 status_pointer; | |
505 | u8 read_pointer; | |
506 | u8 write_pointer; | |
5af05fef | 507 | u32 status = 0; |
e981e7b1 TD |
508 | u32 status_id; |
509 | u32 submit_contexts = 0; | |
510 | ||
511 | status_pointer = I915_READ(RING_CONTEXT_STATUS_PTR(ring)); | |
512 | ||
513 | read_pointer = ring->next_context_status_buffer; | |
514 | write_pointer = status_pointer & 0x07; | |
515 | if (read_pointer > write_pointer) | |
516 | write_pointer += 6; | |
517 | ||
518 | spin_lock(&ring->execlist_lock); | |
519 | ||
520 | while (read_pointer < write_pointer) { | |
521 | read_pointer++; | |
522 | status = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
523 | (read_pointer % 6) * 8); | |
524 | status_id = I915_READ(RING_CONTEXT_STATUS_BUF(ring) + | |
525 | (read_pointer % 6) * 8 + 4); | |
526 | ||
031a8936 MK |
527 | if (status & GEN8_CTX_STATUS_IDLE_ACTIVE) |
528 | continue; | |
529 | ||
e1fee72c OM |
530 | if (status & GEN8_CTX_STATUS_PREEMPTED) { |
531 | if (status & GEN8_CTX_STATUS_LITE_RESTORE) { | |
532 | if (execlists_check_remove_request(ring, status_id)) | |
533 | WARN(1, "Lite Restored request removed from queue\n"); | |
534 | } else | |
535 | WARN(1, "Preemption without Lite Restore\n"); | |
536 | } | |
537 | ||
538 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) || | |
539 | (status & GEN8_CTX_STATUS_ELEMENT_SWITCH)) { | |
e981e7b1 TD |
540 | if (execlists_check_remove_request(ring, status_id)) |
541 | submit_contexts++; | |
542 | } | |
543 | } | |
544 | ||
5af05fef MT |
545 | if (disable_lite_restore_wa(ring)) { |
546 | /* Prevent a ctx to preempt itself */ | |
547 | if ((status & GEN8_CTX_STATUS_ACTIVE_IDLE) && | |
548 | (submit_contexts != 0)) | |
549 | execlists_context_unqueue(ring); | |
550 | } else if (submit_contexts != 0) { | |
e981e7b1 | 551 | execlists_context_unqueue(ring); |
5af05fef | 552 | } |
e981e7b1 TD |
553 | |
554 | spin_unlock(&ring->execlist_lock); | |
555 | ||
556 | WARN(submit_contexts > 2, "More than two context complete events?\n"); | |
557 | ring->next_context_status_buffer = write_pointer % 6; | |
558 | ||
559 | I915_WRITE(RING_CONTEXT_STATUS_PTR(ring), | |
cc53699b | 560 | _MASKED_FIELD(0x07 << 8, ((u32)ring->next_context_status_buffer & 0x07) << 8)); |
e981e7b1 TD |
561 | } |
562 | ||
ae70797d | 563 | static int execlists_context_queue(struct drm_i915_gem_request *request) |
acdd884a | 564 | { |
ae70797d | 565 | struct intel_engine_cs *ring = request->ring; |
6d3d8274 | 566 | struct drm_i915_gem_request *cursor; |
f1ad5a1f | 567 | int num_elements = 0; |
acdd884a | 568 | |
ae70797d | 569 | if (request->ctx != ring->default_context) |
8ba319da | 570 | intel_lr_context_pin(request); |
9bb1af44 JH |
571 | |
572 | i915_gem_request_reference(request); | |
573 | ||
b5eba372 | 574 | spin_lock_irq(&ring->execlist_lock); |
acdd884a | 575 | |
f1ad5a1f OM |
576 | list_for_each_entry(cursor, &ring->execlist_queue, execlist_link) |
577 | if (++num_elements > 2) | |
578 | break; | |
579 | ||
580 | if (num_elements > 2) { | |
6d3d8274 | 581 | struct drm_i915_gem_request *tail_req; |
f1ad5a1f OM |
582 | |
583 | tail_req = list_last_entry(&ring->execlist_queue, | |
6d3d8274 | 584 | struct drm_i915_gem_request, |
f1ad5a1f OM |
585 | execlist_link); |
586 | ||
ae70797d | 587 | if (request->ctx == tail_req->ctx) { |
f1ad5a1f | 588 | WARN(tail_req->elsp_submitted != 0, |
7ba717cf | 589 | "More than 2 already-submitted reqs queued\n"); |
f1ad5a1f | 590 | list_del(&tail_req->execlist_link); |
c86ee3a9 TD |
591 | list_add_tail(&tail_req->execlist_link, |
592 | &ring->execlist_retired_req_list); | |
f1ad5a1f OM |
593 | } |
594 | } | |
595 | ||
6d3d8274 | 596 | list_add_tail(&request->execlist_link, &ring->execlist_queue); |
f1ad5a1f | 597 | if (num_elements == 0) |
acdd884a MT |
598 | execlists_context_unqueue(ring); |
599 | ||
b5eba372 | 600 | spin_unlock_irq(&ring->execlist_lock); |
acdd884a MT |
601 | |
602 | return 0; | |
603 | } | |
604 | ||
2f20055d | 605 | static int logical_ring_invalidate_all_caches(struct drm_i915_gem_request *req) |
ba8b7ccb | 606 | { |
2f20055d | 607 | struct intel_engine_cs *ring = req->ring; |
ba8b7ccb OM |
608 | uint32_t flush_domains; |
609 | int ret; | |
610 | ||
611 | flush_domains = 0; | |
612 | if (ring->gpu_caches_dirty) | |
613 | flush_domains = I915_GEM_GPU_DOMAINS; | |
614 | ||
7deb4d39 | 615 | ret = ring->emit_flush(req, I915_GEM_GPU_DOMAINS, flush_domains); |
ba8b7ccb OM |
616 | if (ret) |
617 | return ret; | |
618 | ||
619 | ring->gpu_caches_dirty = false; | |
620 | return 0; | |
621 | } | |
622 | ||
535fbe82 | 623 | static int execlists_move_to_gpu(struct drm_i915_gem_request *req, |
ba8b7ccb OM |
624 | struct list_head *vmas) |
625 | { | |
535fbe82 | 626 | const unsigned other_rings = ~intel_ring_flag(req->ring); |
ba8b7ccb OM |
627 | struct i915_vma *vma; |
628 | uint32_t flush_domains = 0; | |
629 | bool flush_chipset = false; | |
630 | int ret; | |
631 | ||
632 | list_for_each_entry(vma, vmas, exec_list) { | |
633 | struct drm_i915_gem_object *obj = vma->obj; | |
634 | ||
03ade511 | 635 | if (obj->active & other_rings) { |
91af127f | 636 | ret = i915_gem_object_sync(obj, req->ring, &req); |
03ade511 CW |
637 | if (ret) |
638 | return ret; | |
639 | } | |
ba8b7ccb OM |
640 | |
641 | if (obj->base.write_domain & I915_GEM_DOMAIN_CPU) | |
642 | flush_chipset |= i915_gem_clflush_object(obj, false); | |
643 | ||
644 | flush_domains |= obj->base.write_domain; | |
645 | } | |
646 | ||
647 | if (flush_domains & I915_GEM_DOMAIN_GTT) | |
648 | wmb(); | |
649 | ||
650 | /* Unconditionally invalidate gpu caches and ensure that we do flush | |
651 | * any residual writes from the previous batch. | |
652 | */ | |
2f20055d | 653 | return logical_ring_invalidate_all_caches(req); |
ba8b7ccb OM |
654 | } |
655 | ||
40e895ce | 656 | int intel_logical_ring_alloc_request_extras(struct drm_i915_gem_request *request) |
bc0dce3f | 657 | { |
bc0dce3f JH |
658 | int ret; |
659 | ||
f3cc01f0 MK |
660 | request->ringbuf = request->ctx->engine[request->ring->id].ringbuf; |
661 | ||
40e895ce | 662 | if (request->ctx != request->ring->default_context) { |
8ba319da | 663 | ret = intel_lr_context_pin(request); |
6689cb2b | 664 | if (ret) |
bc0dce3f | 665 | return ret; |
bc0dce3f JH |
666 | } |
667 | ||
bc0dce3f JH |
668 | return 0; |
669 | } | |
670 | ||
ae70797d | 671 | static int logical_ring_wait_for_space(struct drm_i915_gem_request *req, |
595e1eeb | 672 | int bytes) |
bc0dce3f | 673 | { |
ae70797d JH |
674 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
675 | struct intel_engine_cs *ring = req->ring; | |
676 | struct drm_i915_gem_request *target; | |
b4716185 CW |
677 | unsigned space; |
678 | int ret; | |
bc0dce3f JH |
679 | |
680 | if (intel_ring_space(ringbuf) >= bytes) | |
681 | return 0; | |
682 | ||
79bbcc29 JH |
683 | /* The whole point of reserving space is to not wait! */ |
684 | WARN_ON(ringbuf->reserved_in_use); | |
685 | ||
ae70797d | 686 | list_for_each_entry(target, &ring->request_list, list) { |
bc0dce3f JH |
687 | /* |
688 | * The request queue is per-engine, so can contain requests | |
689 | * from multiple ringbuffers. Here, we must ignore any that | |
690 | * aren't from the ringbuffer we're considering. | |
691 | */ | |
ae70797d | 692 | if (target->ringbuf != ringbuf) |
bc0dce3f JH |
693 | continue; |
694 | ||
695 | /* Would completion of this request free enough space? */ | |
ae70797d | 696 | space = __intel_ring_space(target->postfix, ringbuf->tail, |
b4716185 CW |
697 | ringbuf->size); |
698 | if (space >= bytes) | |
bc0dce3f | 699 | break; |
bc0dce3f JH |
700 | } |
701 | ||
ae70797d | 702 | if (WARN_ON(&target->list == &ring->request_list)) |
bc0dce3f JH |
703 | return -ENOSPC; |
704 | ||
ae70797d | 705 | ret = i915_wait_request(target); |
bc0dce3f JH |
706 | if (ret) |
707 | return ret; | |
708 | ||
b4716185 CW |
709 | ringbuf->space = space; |
710 | return 0; | |
bc0dce3f JH |
711 | } |
712 | ||
713 | /* | |
714 | * intel_logical_ring_advance_and_submit() - advance the tail and submit the workload | |
ae70797d | 715 | * @request: Request to advance the logical ringbuffer of. |
bc0dce3f JH |
716 | * |
717 | * The tail is updated in our logical ringbuffer struct, not in the actual context. What | |
718 | * really happens during submission is that the context and current tail will be placed | |
719 | * on a queue waiting for the ELSP to be ready to accept a new context submission. At that | |
720 | * point, the tail *inside* the context is updated and the ELSP written to. | |
721 | */ | |
722 | static void | |
ae70797d | 723 | intel_logical_ring_advance_and_submit(struct drm_i915_gem_request *request) |
bc0dce3f | 724 | { |
ae70797d | 725 | struct intel_engine_cs *ring = request->ring; |
d1675198 | 726 | struct drm_i915_private *dev_priv = request->i915; |
bc0dce3f | 727 | |
ae70797d | 728 | intel_logical_ring_advance(request->ringbuf); |
bc0dce3f | 729 | |
d1675198 AD |
730 | request->tail = request->ringbuf->tail; |
731 | ||
bc0dce3f JH |
732 | if (intel_ring_stopped(ring)) |
733 | return; | |
734 | ||
d1675198 AD |
735 | if (dev_priv->guc.execbuf_client) |
736 | i915_guc_submit(dev_priv->guc.execbuf_client, request); | |
737 | else | |
738 | execlists_context_queue(request); | |
bc0dce3f JH |
739 | } |
740 | ||
79bbcc29 | 741 | static void __wrap_ring_buffer(struct intel_ringbuffer *ringbuf) |
bc0dce3f JH |
742 | { |
743 | uint32_t __iomem *virt; | |
744 | int rem = ringbuf->size - ringbuf->tail; | |
745 | ||
bc0dce3f JH |
746 | virt = ringbuf->virtual_start + ringbuf->tail; |
747 | rem /= 4; | |
748 | while (rem--) | |
749 | iowrite32(MI_NOOP, virt++); | |
750 | ||
751 | ringbuf->tail = 0; | |
752 | intel_ring_update_space(ringbuf); | |
bc0dce3f JH |
753 | } |
754 | ||
ae70797d | 755 | static int logical_ring_prepare(struct drm_i915_gem_request *req, int bytes) |
bc0dce3f | 756 | { |
ae70797d | 757 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
79bbcc29 JH |
758 | int remain_usable = ringbuf->effective_size - ringbuf->tail; |
759 | int remain_actual = ringbuf->size - ringbuf->tail; | |
760 | int ret, total_bytes, wait_bytes = 0; | |
761 | bool need_wrap = false; | |
29b1b415 | 762 | |
79bbcc29 JH |
763 | if (ringbuf->reserved_in_use) |
764 | total_bytes = bytes; | |
765 | else | |
766 | total_bytes = bytes + ringbuf->reserved_size; | |
29b1b415 | 767 | |
79bbcc29 JH |
768 | if (unlikely(bytes > remain_usable)) { |
769 | /* | |
770 | * Not enough space for the basic request. So need to flush | |
771 | * out the remainder and then wait for base + reserved. | |
772 | */ | |
773 | wait_bytes = remain_actual + total_bytes; | |
774 | need_wrap = true; | |
775 | } else { | |
776 | if (unlikely(total_bytes > remain_usable)) { | |
777 | /* | |
778 | * The base request will fit but the reserved space | |
779 | * falls off the end. So only need to to wait for the | |
780 | * reserved size after flushing out the remainder. | |
781 | */ | |
782 | wait_bytes = remain_actual + ringbuf->reserved_size; | |
783 | need_wrap = true; | |
784 | } else if (total_bytes > ringbuf->space) { | |
785 | /* No wrapping required, just waiting. */ | |
786 | wait_bytes = total_bytes; | |
29b1b415 | 787 | } |
bc0dce3f JH |
788 | } |
789 | ||
79bbcc29 JH |
790 | if (wait_bytes) { |
791 | ret = logical_ring_wait_for_space(req, wait_bytes); | |
bc0dce3f JH |
792 | if (unlikely(ret)) |
793 | return ret; | |
79bbcc29 JH |
794 | |
795 | if (need_wrap) | |
796 | __wrap_ring_buffer(ringbuf); | |
bc0dce3f JH |
797 | } |
798 | ||
799 | return 0; | |
800 | } | |
801 | ||
802 | /** | |
803 | * intel_logical_ring_begin() - prepare the logical ringbuffer to accept some commands | |
804 | * | |
4d616a29 | 805 | * @request: The request to start some new work for |
4d78c8dc | 806 | * @ctx: Logical ring context whose ringbuffer is being prepared. |
bc0dce3f JH |
807 | * @num_dwords: number of DWORDs that we plan to write to the ringbuffer. |
808 | * | |
809 | * The ringbuffer might not be ready to accept the commands right away (maybe it needs to | |
810 | * be wrapped, or wait a bit for the tail to be updated). This function takes care of that | |
811 | * and also preallocates a request (every workload submission is still mediated through | |
812 | * requests, same as it did with legacy ringbuffer submission). | |
813 | * | |
814 | * Return: non-zero if the ringbuffer is not ready to be written to. | |
815 | */ | |
3bbaba0c | 816 | int intel_logical_ring_begin(struct drm_i915_gem_request *req, int num_dwords) |
bc0dce3f | 817 | { |
4d616a29 | 818 | struct drm_i915_private *dev_priv; |
bc0dce3f JH |
819 | int ret; |
820 | ||
4d616a29 JH |
821 | WARN_ON(req == NULL); |
822 | dev_priv = req->ring->dev->dev_private; | |
823 | ||
bc0dce3f JH |
824 | ret = i915_gem_check_wedge(&dev_priv->gpu_error, |
825 | dev_priv->mm.interruptible); | |
826 | if (ret) | |
827 | return ret; | |
828 | ||
ae70797d | 829 | ret = logical_ring_prepare(req, num_dwords * sizeof(uint32_t)); |
bc0dce3f JH |
830 | if (ret) |
831 | return ret; | |
832 | ||
4d616a29 | 833 | req->ringbuf->space -= num_dwords * sizeof(uint32_t); |
bc0dce3f JH |
834 | return 0; |
835 | } | |
836 | ||
ccd98fe4 JH |
837 | int intel_logical_ring_reserve_space(struct drm_i915_gem_request *request) |
838 | { | |
839 | /* | |
840 | * The first call merely notes the reserve request and is common for | |
841 | * all back ends. The subsequent localised _begin() call actually | |
842 | * ensures that the reservation is available. Without the begin, if | |
843 | * the request creator immediately submitted the request without | |
844 | * adding any commands to it then there might not actually be | |
845 | * sufficient room for the submission commands. | |
846 | */ | |
847 | intel_ring_reserved_space_reserve(request->ringbuf, MIN_SPACE_FOR_ADD_REQUEST); | |
848 | ||
849 | return intel_logical_ring_begin(request, 0); | |
850 | } | |
851 | ||
73e4d07f OM |
852 | /** |
853 | * execlists_submission() - submit a batchbuffer for execution, Execlists style | |
854 | * @dev: DRM device. | |
855 | * @file: DRM file. | |
856 | * @ring: Engine Command Streamer to submit to. | |
857 | * @ctx: Context to employ for this submission. | |
858 | * @args: execbuffer call arguments. | |
859 | * @vmas: list of vmas. | |
860 | * @batch_obj: the batchbuffer to submit. | |
861 | * @exec_start: batchbuffer start virtual address pointer. | |
8e004efc | 862 | * @dispatch_flags: translated execbuffer call flags. |
73e4d07f OM |
863 | * |
864 | * This is the evil twin version of i915_gem_ringbuffer_submission. It abstracts | |
865 | * away the submission details of the execbuffer ioctl call. | |
866 | * | |
867 | * Return: non-zero if the submission fails. | |
868 | */ | |
5f19e2bf | 869 | int intel_execlists_submission(struct i915_execbuffer_params *params, |
454afebd | 870 | struct drm_i915_gem_execbuffer2 *args, |
5f19e2bf | 871 | struct list_head *vmas) |
454afebd | 872 | { |
5f19e2bf JH |
873 | struct drm_device *dev = params->dev; |
874 | struct intel_engine_cs *ring = params->ring; | |
ba8b7ccb | 875 | struct drm_i915_private *dev_priv = dev->dev_private; |
5f19e2bf JH |
876 | struct intel_ringbuffer *ringbuf = params->ctx->engine[ring->id].ringbuf; |
877 | u64 exec_start; | |
ba8b7ccb OM |
878 | int instp_mode; |
879 | u32 instp_mask; | |
880 | int ret; | |
881 | ||
882 | instp_mode = args->flags & I915_EXEC_CONSTANTS_MASK; | |
883 | instp_mask = I915_EXEC_CONSTANTS_MASK; | |
884 | switch (instp_mode) { | |
885 | case I915_EXEC_CONSTANTS_REL_GENERAL: | |
886 | case I915_EXEC_CONSTANTS_ABSOLUTE: | |
887 | case I915_EXEC_CONSTANTS_REL_SURFACE: | |
888 | if (instp_mode != 0 && ring != &dev_priv->ring[RCS]) { | |
889 | DRM_DEBUG("non-0 rel constants mode on non-RCS\n"); | |
890 | return -EINVAL; | |
891 | } | |
892 | ||
893 | if (instp_mode != dev_priv->relative_constants_mode) { | |
894 | if (instp_mode == I915_EXEC_CONSTANTS_REL_SURFACE) { | |
895 | DRM_DEBUG("rel surface constants mode invalid on gen5+\n"); | |
896 | return -EINVAL; | |
897 | } | |
898 | ||
899 | /* The HW changed the meaning on this bit on gen6 */ | |
900 | instp_mask &= ~I915_EXEC_CONSTANTS_REL_SURFACE; | |
901 | } | |
902 | break; | |
903 | default: | |
904 | DRM_DEBUG("execbuf with unknown constants: %d\n", instp_mode); | |
905 | return -EINVAL; | |
906 | } | |
907 | ||
908 | if (args->num_cliprects != 0) { | |
909 | DRM_DEBUG("clip rectangles are only valid on pre-gen5\n"); | |
910 | return -EINVAL; | |
911 | } else { | |
912 | if (args->DR4 == 0xffffffff) { | |
913 | DRM_DEBUG("UXA submitting garbage DR4, fixing up\n"); | |
914 | args->DR4 = 0; | |
915 | } | |
916 | ||
917 | if (args->DR1 || args->DR4 || args->cliprects_ptr) { | |
918 | DRM_DEBUG("0 cliprects but dirt in cliprects fields\n"); | |
919 | return -EINVAL; | |
920 | } | |
921 | } | |
922 | ||
923 | if (args->flags & I915_EXEC_GEN7_SOL_RESET) { | |
924 | DRM_DEBUG("sol reset is gen7 only\n"); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
535fbe82 | 928 | ret = execlists_move_to_gpu(params->request, vmas); |
ba8b7ccb OM |
929 | if (ret) |
930 | return ret; | |
931 | ||
932 | if (ring == &dev_priv->ring[RCS] && | |
933 | instp_mode != dev_priv->relative_constants_mode) { | |
4d616a29 | 934 | ret = intel_logical_ring_begin(params->request, 4); |
ba8b7ccb OM |
935 | if (ret) |
936 | return ret; | |
937 | ||
938 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
939 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(1)); | |
940 | intel_logical_ring_emit(ringbuf, INSTPM); | |
941 | intel_logical_ring_emit(ringbuf, instp_mask << 16 | instp_mode); | |
942 | intel_logical_ring_advance(ringbuf); | |
943 | ||
944 | dev_priv->relative_constants_mode = instp_mode; | |
945 | } | |
946 | ||
5f19e2bf JH |
947 | exec_start = params->batch_obj_vm_offset + |
948 | args->batch_start_offset; | |
949 | ||
be795fc1 | 950 | ret = ring->emit_bb_start(params->request, exec_start, params->dispatch_flags); |
ba8b7ccb OM |
951 | if (ret) |
952 | return ret; | |
953 | ||
95c24161 | 954 | trace_i915_gem_ring_dispatch(params->request, params->dispatch_flags); |
5e4be7bd | 955 | |
8a8edb59 | 956 | i915_gem_execbuffer_move_to_active(vmas, params->request); |
adeca76d | 957 | i915_gem_execbuffer_retire_commands(params); |
ba8b7ccb | 958 | |
454afebd OM |
959 | return 0; |
960 | } | |
961 | ||
c86ee3a9 TD |
962 | void intel_execlists_retire_requests(struct intel_engine_cs *ring) |
963 | { | |
6d3d8274 | 964 | struct drm_i915_gem_request *req, *tmp; |
c86ee3a9 TD |
965 | struct list_head retired_list; |
966 | ||
967 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
968 | if (list_empty(&ring->execlist_retired_req_list)) | |
969 | return; | |
970 | ||
971 | INIT_LIST_HEAD(&retired_list); | |
b5eba372 | 972 | spin_lock_irq(&ring->execlist_lock); |
c86ee3a9 | 973 | list_replace_init(&ring->execlist_retired_req_list, &retired_list); |
b5eba372 | 974 | spin_unlock_irq(&ring->execlist_lock); |
c86ee3a9 TD |
975 | |
976 | list_for_each_entry_safe(req, tmp, &retired_list, execlist_link) { | |
6d3d8274 | 977 | struct intel_context *ctx = req->ctx; |
7ba717cf TD |
978 | struct drm_i915_gem_object *ctx_obj = |
979 | ctx->engine[ring->id].state; | |
980 | ||
981 | if (ctx_obj && (ctx != ring->default_context)) | |
8ba319da | 982 | intel_lr_context_unpin(req); |
c86ee3a9 | 983 | list_del(&req->execlist_link); |
f8210795 | 984 | i915_gem_request_unreference(req); |
c86ee3a9 TD |
985 | } |
986 | } | |
987 | ||
454afebd OM |
988 | void intel_logical_ring_stop(struct intel_engine_cs *ring) |
989 | { | |
9832b9da OM |
990 | struct drm_i915_private *dev_priv = ring->dev->dev_private; |
991 | int ret; | |
992 | ||
993 | if (!intel_ring_initialized(ring)) | |
994 | return; | |
995 | ||
996 | ret = intel_ring_idle(ring); | |
997 | if (ret && !i915_reset_in_progress(&to_i915(ring->dev)->gpu_error)) | |
998 | DRM_ERROR("failed to quiesce %s whilst cleaning up: %d\n", | |
999 | ring->name, ret); | |
1000 | ||
1001 | /* TODO: Is this correct with Execlists enabled? */ | |
1002 | I915_WRITE_MODE(ring, _MASKED_BIT_ENABLE(STOP_RING)); | |
1003 | if (wait_for_atomic((I915_READ_MODE(ring) & MODE_IDLE) != 0, 1000)) { | |
1004 | DRM_ERROR("%s :timed out trying to stop ring\n", ring->name); | |
1005 | return; | |
1006 | } | |
1007 | I915_WRITE_MODE(ring, _MASKED_BIT_DISABLE(STOP_RING)); | |
454afebd OM |
1008 | } |
1009 | ||
4866d729 | 1010 | int logical_ring_flush_all_caches(struct drm_i915_gem_request *req) |
48e29f55 | 1011 | { |
4866d729 | 1012 | struct intel_engine_cs *ring = req->ring; |
48e29f55 OM |
1013 | int ret; |
1014 | ||
1015 | if (!ring->gpu_caches_dirty) | |
1016 | return 0; | |
1017 | ||
7deb4d39 | 1018 | ret = ring->emit_flush(req, 0, I915_GEM_GPU_DOMAINS); |
48e29f55 OM |
1019 | if (ret) |
1020 | return ret; | |
1021 | ||
1022 | ring->gpu_caches_dirty = false; | |
1023 | return 0; | |
1024 | } | |
1025 | ||
e84fe803 NH |
1026 | static int intel_lr_context_do_pin(struct intel_engine_cs *ring, |
1027 | struct drm_i915_gem_object *ctx_obj, | |
1028 | struct intel_ringbuffer *ringbuf) | |
dcb4c12a | 1029 | { |
e84fe803 NH |
1030 | struct drm_device *dev = ring->dev; |
1031 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dcb4c12a OM |
1032 | int ret = 0; |
1033 | ||
1034 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
e84fe803 NH |
1035 | ret = i915_gem_obj_ggtt_pin(ctx_obj, GEN8_LR_CONTEXT_ALIGN, |
1036 | PIN_OFFSET_BIAS | GUC_WOPCM_TOP); | |
1037 | if (ret) | |
1038 | return ret; | |
7ba717cf | 1039 | |
e84fe803 NH |
1040 | ret = intel_pin_and_map_ringbuffer_obj(ring->dev, ringbuf); |
1041 | if (ret) | |
1042 | goto unpin_ctx_obj; | |
d1675198 | 1043 | |
e84fe803 | 1044 | ctx_obj->dirty = true; |
e93c28f3 | 1045 | |
e84fe803 NH |
1046 | /* Invalidate GuC TLB. */ |
1047 | if (i915.enable_guc_submission) | |
1048 | I915_WRITE(GEN8_GTCR, GEN8_GTCR_INVALIDATE); | |
dcb4c12a | 1049 | |
7ba717cf TD |
1050 | return ret; |
1051 | ||
1052 | unpin_ctx_obj: | |
1053 | i915_gem_object_ggtt_unpin(ctx_obj); | |
e84fe803 NH |
1054 | |
1055 | return ret; | |
1056 | } | |
1057 | ||
1058 | static int intel_lr_context_pin(struct drm_i915_gem_request *rq) | |
1059 | { | |
1060 | int ret = 0; | |
1061 | struct intel_engine_cs *ring = rq->ring; | |
1062 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
1063 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
1064 | ||
1065 | if (rq->ctx->engine[ring->id].pin_count++ == 0) { | |
1066 | ret = intel_lr_context_do_pin(ring, ctx_obj, ringbuf); | |
1067 | if (ret) | |
1068 | goto reset_pin_count; | |
1069 | } | |
1070 | return ret; | |
1071 | ||
a7cbedec | 1072 | reset_pin_count: |
8ba319da | 1073 | rq->ctx->engine[ring->id].pin_count = 0; |
dcb4c12a OM |
1074 | return ret; |
1075 | } | |
1076 | ||
8ba319da | 1077 | void intel_lr_context_unpin(struct drm_i915_gem_request *rq) |
dcb4c12a | 1078 | { |
8ba319da MK |
1079 | struct intel_engine_cs *ring = rq->ring; |
1080 | struct drm_i915_gem_object *ctx_obj = rq->ctx->engine[ring->id].state; | |
1081 | struct intel_ringbuffer *ringbuf = rq->ringbuf; | |
dcb4c12a OM |
1082 | |
1083 | if (ctx_obj) { | |
1084 | WARN_ON(!mutex_is_locked(&ring->dev->struct_mutex)); | |
8ba319da | 1085 | if (--rq->ctx->engine[ring->id].pin_count == 0) { |
7ba717cf | 1086 | intel_unpin_ringbuffer_obj(ringbuf); |
dcb4c12a | 1087 | i915_gem_object_ggtt_unpin(ctx_obj); |
7ba717cf | 1088 | } |
dcb4c12a OM |
1089 | } |
1090 | } | |
1091 | ||
e2be4faf | 1092 | static int intel_logical_ring_workarounds_emit(struct drm_i915_gem_request *req) |
771b9a53 MT |
1093 | { |
1094 | int ret, i; | |
e2be4faf JH |
1095 | struct intel_engine_cs *ring = req->ring; |
1096 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
771b9a53 MT |
1097 | struct drm_device *dev = ring->dev; |
1098 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1099 | struct i915_workarounds *w = &dev_priv->workarounds; | |
1100 | ||
e6c1abb7 | 1101 | if (WARN_ON_ONCE(w->count == 0)) |
771b9a53 MT |
1102 | return 0; |
1103 | ||
1104 | ring->gpu_caches_dirty = true; | |
4866d729 | 1105 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1106 | if (ret) |
1107 | return ret; | |
1108 | ||
4d616a29 | 1109 | ret = intel_logical_ring_begin(req, w->count * 2 + 2); |
771b9a53 MT |
1110 | if (ret) |
1111 | return ret; | |
1112 | ||
1113 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(w->count)); | |
1114 | for (i = 0; i < w->count; i++) { | |
1115 | intel_logical_ring_emit(ringbuf, w->reg[i].addr); | |
1116 | intel_logical_ring_emit(ringbuf, w->reg[i].value); | |
1117 | } | |
1118 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1119 | ||
1120 | intel_logical_ring_advance(ringbuf); | |
1121 | ||
1122 | ring->gpu_caches_dirty = true; | |
4866d729 | 1123 | ret = logical_ring_flush_all_caches(req); |
771b9a53 MT |
1124 | if (ret) |
1125 | return ret; | |
1126 | ||
1127 | return 0; | |
1128 | } | |
1129 | ||
83b8a982 | 1130 | #define wa_ctx_emit(batch, index, cmd) \ |
17ee950d | 1131 | do { \ |
83b8a982 AS |
1132 | int __index = (index)++; \ |
1133 | if (WARN_ON(__index >= (PAGE_SIZE / sizeof(uint32_t)))) { \ | |
17ee950d AS |
1134 | return -ENOSPC; \ |
1135 | } \ | |
83b8a982 | 1136 | batch[__index] = (cmd); \ |
17ee950d AS |
1137 | } while (0) |
1138 | ||
9e000847 AS |
1139 | |
1140 | /* | |
1141 | * In this WA we need to set GEN8_L3SQCREG4[21:21] and reset it after | |
1142 | * PIPE_CONTROL instruction. This is required for the flush to happen correctly | |
1143 | * but there is a slight complication as this is applied in WA batch where the | |
1144 | * values are only initialized once so we cannot take register value at the | |
1145 | * beginning and reuse it further; hence we save its value to memory, upload a | |
1146 | * constant value with bit21 set and then we restore it back with the saved value. | |
1147 | * To simplify the WA, a constant value is formed by using the default value | |
1148 | * of this register. This shouldn't be a problem because we are only modifying | |
1149 | * it for a short period and this batch in non-premptible. We can ofcourse | |
1150 | * use additional instructions that read the actual value of the register | |
1151 | * at that time and set our bit of interest but it makes the WA complicated. | |
1152 | * | |
1153 | * This WA is also required for Gen9 so extracting as a function avoids | |
1154 | * code duplication. | |
1155 | */ | |
1156 | static inline int gen8_emit_flush_coherentl3_wa(struct intel_engine_cs *ring, | |
1157 | uint32_t *const batch, | |
1158 | uint32_t index) | |
1159 | { | |
1160 | uint32_t l3sqc4_flush = (0x40400000 | GEN8_LQSC_FLUSH_COHERENT_LINES); | |
1161 | ||
a4106a78 AS |
1162 | /* |
1163 | * WaDisableLSQCROPERFforOCL:skl | |
1164 | * This WA is implemented in skl_init_clock_gating() but since | |
1165 | * this batch updates GEN8_L3SQCREG4 with default value we need to | |
1166 | * set this bit here to retain the WA during flush. | |
1167 | */ | |
1168 | if (IS_SKYLAKE(ring->dev) && INTEL_REVID(ring->dev) <= SKL_REVID_E0) | |
1169 | l3sqc4_flush |= GEN8_LQSC_RO_PERF_DIS; | |
1170 | ||
f1afe24f | 1171 | wa_ctx_emit(batch, index, (MI_STORE_REGISTER_MEM_GEN8 | |
83b8a982 AS |
1172 | MI_SRM_LRM_GLOBAL_GTT)); |
1173 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1174 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1175 | wa_ctx_emit(batch, index, 0); | |
1176 | ||
1177 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1178 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1179 | wa_ctx_emit(batch, index, l3sqc4_flush); | |
1180 | ||
1181 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); | |
1182 | wa_ctx_emit(batch, index, (PIPE_CONTROL_CS_STALL | | |
1183 | PIPE_CONTROL_DC_FLUSH_ENABLE)); | |
1184 | wa_ctx_emit(batch, index, 0); | |
1185 | wa_ctx_emit(batch, index, 0); | |
1186 | wa_ctx_emit(batch, index, 0); | |
1187 | wa_ctx_emit(batch, index, 0); | |
1188 | ||
f1afe24f | 1189 | wa_ctx_emit(batch, index, (MI_LOAD_REGISTER_MEM_GEN8 | |
83b8a982 AS |
1190 | MI_SRM_LRM_GLOBAL_GTT)); |
1191 | wa_ctx_emit(batch, index, GEN8_L3SQCREG4); | |
1192 | wa_ctx_emit(batch, index, ring->scratch.gtt_offset + 256); | |
1193 | wa_ctx_emit(batch, index, 0); | |
9e000847 AS |
1194 | |
1195 | return index; | |
1196 | } | |
1197 | ||
17ee950d AS |
1198 | static inline uint32_t wa_ctx_start(struct i915_wa_ctx_bb *wa_ctx, |
1199 | uint32_t offset, | |
1200 | uint32_t start_alignment) | |
1201 | { | |
1202 | return wa_ctx->offset = ALIGN(offset, start_alignment); | |
1203 | } | |
1204 | ||
1205 | static inline int wa_ctx_end(struct i915_wa_ctx_bb *wa_ctx, | |
1206 | uint32_t offset, | |
1207 | uint32_t size_alignment) | |
1208 | { | |
1209 | wa_ctx->size = offset - wa_ctx->offset; | |
1210 | ||
1211 | WARN(wa_ctx->size % size_alignment, | |
1212 | "wa_ctx_bb failed sanity checks: size %d is not aligned to %d\n", | |
1213 | wa_ctx->size, size_alignment); | |
1214 | return 0; | |
1215 | } | |
1216 | ||
1217 | /** | |
1218 | * gen8_init_indirectctx_bb() - initialize indirect ctx batch with WA | |
1219 | * | |
1220 | * @ring: only applicable for RCS | |
1221 | * @wa_ctx: structure representing wa_ctx | |
1222 | * offset: specifies start of the batch, should be cache-aligned. This is updated | |
1223 | * with the offset value received as input. | |
1224 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
1225 | * @batch: page in which WA are loaded | |
1226 | * @offset: This field specifies the start of the batch, it should be | |
1227 | * cache-aligned otherwise it is adjusted accordingly. | |
1228 | * Typically we only have one indirect_ctx and per_ctx batch buffer which are | |
1229 | * initialized at the beginning and shared across all contexts but this field | |
1230 | * helps us to have multiple batches at different offsets and select them based | |
1231 | * on a criteria. At the moment this batch always start at the beginning of the page | |
1232 | * and at this point we don't have multiple wa_ctx batch buffers. | |
1233 | * | |
1234 | * The number of WA applied are not known at the beginning; we use this field | |
1235 | * to return the no of DWORDS written. | |
4d78c8dc | 1236 | * |
17ee950d AS |
1237 | * It is to be noted that this batch does not contain MI_BATCH_BUFFER_END |
1238 | * so it adds NOOPs as padding to make it cacheline aligned. | |
1239 | * MI_BATCH_BUFFER_END will be added to perctx batch and both of them together | |
1240 | * makes a complete batch buffer. | |
1241 | * | |
1242 | * Return: non-zero if we exceed the PAGE_SIZE limit. | |
1243 | */ | |
1244 | ||
1245 | static int gen8_init_indirectctx_bb(struct intel_engine_cs *ring, | |
1246 | struct i915_wa_ctx_bb *wa_ctx, | |
1247 | uint32_t *const batch, | |
1248 | uint32_t *offset) | |
1249 | { | |
0160f055 | 1250 | uint32_t scratch_addr; |
17ee950d AS |
1251 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1252 | ||
7ad00d1a | 1253 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1254 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); |
17ee950d | 1255 | |
c82435bb AS |
1256 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:bdw */ |
1257 | if (IS_BROADWELL(ring->dev)) { | |
9e000847 AS |
1258 | index = gen8_emit_flush_coherentl3_wa(ring, batch, index); |
1259 | if (index < 0) | |
1260 | return index; | |
c82435bb AS |
1261 | } |
1262 | ||
0160f055 AS |
1263 | /* WaClearSlmSpaceAtContextSwitch:bdw,chv */ |
1264 | /* Actual scratch location is at 128 bytes offset */ | |
1265 | scratch_addr = ring->scratch.gtt_offset + 2*CACHELINE_BYTES; | |
1266 | ||
83b8a982 AS |
1267 | wa_ctx_emit(batch, index, GFX_OP_PIPE_CONTROL(6)); |
1268 | wa_ctx_emit(batch, index, (PIPE_CONTROL_FLUSH_L3 | | |
1269 | PIPE_CONTROL_GLOBAL_GTT_IVB | | |
1270 | PIPE_CONTROL_CS_STALL | | |
1271 | PIPE_CONTROL_QW_WRITE)); | |
1272 | wa_ctx_emit(batch, index, scratch_addr); | |
1273 | wa_ctx_emit(batch, index, 0); | |
1274 | wa_ctx_emit(batch, index, 0); | |
1275 | wa_ctx_emit(batch, index, 0); | |
0160f055 | 1276 | |
17ee950d AS |
1277 | /* Pad to end of cacheline */ |
1278 | while (index % CACHELINE_DWORDS) | |
83b8a982 | 1279 | wa_ctx_emit(batch, index, MI_NOOP); |
17ee950d AS |
1280 | |
1281 | /* | |
1282 | * MI_BATCH_BUFFER_END is not required in Indirect ctx BB because | |
1283 | * execution depends on the length specified in terms of cache lines | |
1284 | * in the register CTX_RCS_INDIRECT_CTX | |
1285 | */ | |
1286 | ||
1287 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1288 | } | |
1289 | ||
1290 | /** | |
1291 | * gen8_init_perctx_bb() - initialize per ctx batch with WA | |
1292 | * | |
1293 | * @ring: only applicable for RCS | |
1294 | * @wa_ctx: structure representing wa_ctx | |
1295 | * offset: specifies start of the batch, should be cache-aligned. | |
1296 | * size: size of the batch in DWORDS but HW expects in terms of cachelines | |
4d78c8dc | 1297 | * @batch: page in which WA are loaded |
17ee950d AS |
1298 | * @offset: This field specifies the start of this batch. |
1299 | * This batch is started immediately after indirect_ctx batch. Since we ensure | |
1300 | * that indirect_ctx ends on a cacheline this batch is aligned automatically. | |
1301 | * | |
1302 | * The number of DWORDS written are returned using this field. | |
1303 | * | |
1304 | * This batch is terminated with MI_BATCH_BUFFER_END and so we need not add padding | |
1305 | * to align it with cacheline as padding after MI_BATCH_BUFFER_END is redundant. | |
1306 | */ | |
1307 | static int gen8_init_perctx_bb(struct intel_engine_cs *ring, | |
1308 | struct i915_wa_ctx_bb *wa_ctx, | |
1309 | uint32_t *const batch, | |
1310 | uint32_t *offset) | |
1311 | { | |
1312 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); | |
1313 | ||
7ad00d1a | 1314 | /* WaDisableCtxRestoreArbitration:bdw,chv */ |
83b8a982 | 1315 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); |
7ad00d1a | 1316 | |
83b8a982 | 1317 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
17ee950d AS |
1318 | |
1319 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1320 | } | |
1321 | ||
0504cffc AS |
1322 | static int gen9_init_indirectctx_bb(struct intel_engine_cs *ring, |
1323 | struct i915_wa_ctx_bb *wa_ctx, | |
1324 | uint32_t *const batch, | |
1325 | uint32_t *offset) | |
1326 | { | |
a4106a78 | 1327 | int ret; |
0907c8f7 | 1328 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1329 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1330 | ||
0907c8f7 AS |
1331 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1332 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1333 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1334 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_DISABLE); | |
0504cffc | 1335 | |
a4106a78 AS |
1336 | /* WaFlushCoherentL3CacheLinesAtContextSwitch:skl,bxt */ |
1337 | ret = gen8_emit_flush_coherentl3_wa(ring, batch, index); | |
1338 | if (ret < 0) | |
1339 | return ret; | |
1340 | index = ret; | |
1341 | ||
0504cffc AS |
1342 | /* Pad to end of cacheline */ |
1343 | while (index % CACHELINE_DWORDS) | |
1344 | wa_ctx_emit(batch, index, MI_NOOP); | |
1345 | ||
1346 | return wa_ctx_end(wa_ctx, *offset = index, CACHELINE_DWORDS); | |
1347 | } | |
1348 | ||
1349 | static int gen9_init_perctx_bb(struct intel_engine_cs *ring, | |
1350 | struct i915_wa_ctx_bb *wa_ctx, | |
1351 | uint32_t *const batch, | |
1352 | uint32_t *offset) | |
1353 | { | |
0907c8f7 | 1354 | struct drm_device *dev = ring->dev; |
0504cffc AS |
1355 | uint32_t index = wa_ctx_start(wa_ctx, *offset, CACHELINE_DWORDS); |
1356 | ||
9b01435d AS |
1357 | /* WaSetDisablePixMaskCammingAndRhwoInCommonSliceChicken:skl,bxt */ |
1358 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_B0)) || | |
1359 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) { | |
1360 | wa_ctx_emit(batch, index, MI_LOAD_REGISTER_IMM(1)); | |
1361 | wa_ctx_emit(batch, index, GEN9_SLICE_COMMON_ECO_CHICKEN0); | |
1362 | wa_ctx_emit(batch, index, | |
1363 | _MASKED_BIT_ENABLE(DISABLE_PIXEL_MASK_CAMMING)); | |
1364 | wa_ctx_emit(batch, index, MI_NOOP); | |
1365 | } | |
1366 | ||
0907c8f7 AS |
1367 | /* WaDisableCtxRestoreArbitration:skl,bxt */ |
1368 | if ((IS_SKYLAKE(dev) && (INTEL_REVID(dev) <= SKL_REVID_D0)) || | |
1369 | (IS_BROXTON(dev) && (INTEL_REVID(dev) == BXT_REVID_A0))) | |
1370 | wa_ctx_emit(batch, index, MI_ARB_ON_OFF | MI_ARB_ENABLE); | |
1371 | ||
0504cffc AS |
1372 | wa_ctx_emit(batch, index, MI_BATCH_BUFFER_END); |
1373 | ||
1374 | return wa_ctx_end(wa_ctx, *offset = index, 1); | |
1375 | } | |
1376 | ||
17ee950d AS |
1377 | static int lrc_setup_wa_ctx_obj(struct intel_engine_cs *ring, u32 size) |
1378 | { | |
1379 | int ret; | |
1380 | ||
1381 | ring->wa_ctx.obj = i915_gem_alloc_object(ring->dev, PAGE_ALIGN(size)); | |
1382 | if (!ring->wa_ctx.obj) { | |
1383 | DRM_DEBUG_DRIVER("alloc LRC WA ctx backing obj failed.\n"); | |
1384 | return -ENOMEM; | |
1385 | } | |
1386 | ||
1387 | ret = i915_gem_obj_ggtt_pin(ring->wa_ctx.obj, PAGE_SIZE, 0); | |
1388 | if (ret) { | |
1389 | DRM_DEBUG_DRIVER("pin LRC WA ctx backing obj failed: %d\n", | |
1390 | ret); | |
1391 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1392 | return ret; | |
1393 | } | |
1394 | ||
1395 | return 0; | |
1396 | } | |
1397 | ||
1398 | static void lrc_destroy_wa_ctx_obj(struct intel_engine_cs *ring) | |
1399 | { | |
1400 | if (ring->wa_ctx.obj) { | |
1401 | i915_gem_object_ggtt_unpin(ring->wa_ctx.obj); | |
1402 | drm_gem_object_unreference(&ring->wa_ctx.obj->base); | |
1403 | ring->wa_ctx.obj = NULL; | |
1404 | } | |
1405 | } | |
1406 | ||
1407 | static int intel_init_workaround_bb(struct intel_engine_cs *ring) | |
1408 | { | |
1409 | int ret; | |
1410 | uint32_t *batch; | |
1411 | uint32_t offset; | |
1412 | struct page *page; | |
1413 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
1414 | ||
1415 | WARN_ON(ring->id != RCS); | |
1416 | ||
5e60d790 | 1417 | /* update this when WA for higher Gen are added */ |
0504cffc AS |
1418 | if (INTEL_INFO(ring->dev)->gen > 9) { |
1419 | DRM_ERROR("WA batch buffer is not initialized for Gen%d\n", | |
1420 | INTEL_INFO(ring->dev)->gen); | |
5e60d790 | 1421 | return 0; |
0504cffc | 1422 | } |
5e60d790 | 1423 | |
c4db7599 AS |
1424 | /* some WA perform writes to scratch page, ensure it is valid */ |
1425 | if (ring->scratch.obj == NULL) { | |
1426 | DRM_ERROR("scratch page not allocated for %s\n", ring->name); | |
1427 | return -EINVAL; | |
1428 | } | |
1429 | ||
17ee950d AS |
1430 | ret = lrc_setup_wa_ctx_obj(ring, PAGE_SIZE); |
1431 | if (ret) { | |
1432 | DRM_DEBUG_DRIVER("Failed to setup context WA page: %d\n", ret); | |
1433 | return ret; | |
1434 | } | |
1435 | ||
1436 | page = i915_gem_object_get_page(wa_ctx->obj, 0); | |
1437 | batch = kmap_atomic(page); | |
1438 | offset = 0; | |
1439 | ||
1440 | if (INTEL_INFO(ring->dev)->gen == 8) { | |
1441 | ret = gen8_init_indirectctx_bb(ring, | |
1442 | &wa_ctx->indirect_ctx, | |
1443 | batch, | |
1444 | &offset); | |
1445 | if (ret) | |
1446 | goto out; | |
1447 | ||
1448 | ret = gen8_init_perctx_bb(ring, | |
1449 | &wa_ctx->per_ctx, | |
1450 | batch, | |
1451 | &offset); | |
1452 | if (ret) | |
1453 | goto out; | |
0504cffc AS |
1454 | } else if (INTEL_INFO(ring->dev)->gen == 9) { |
1455 | ret = gen9_init_indirectctx_bb(ring, | |
1456 | &wa_ctx->indirect_ctx, | |
1457 | batch, | |
1458 | &offset); | |
1459 | if (ret) | |
1460 | goto out; | |
1461 | ||
1462 | ret = gen9_init_perctx_bb(ring, | |
1463 | &wa_ctx->per_ctx, | |
1464 | batch, | |
1465 | &offset); | |
1466 | if (ret) | |
1467 | goto out; | |
17ee950d AS |
1468 | } |
1469 | ||
1470 | out: | |
1471 | kunmap_atomic(batch); | |
1472 | if (ret) | |
1473 | lrc_destroy_wa_ctx_obj(ring); | |
1474 | ||
1475 | return ret; | |
1476 | } | |
1477 | ||
9b1136d5 OM |
1478 | static int gen8_init_common_ring(struct intel_engine_cs *ring) |
1479 | { | |
1480 | struct drm_device *dev = ring->dev; | |
1481 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1482 | ||
e84fe803 NH |
1483 | lrc_setup_hardware_status_page(ring, |
1484 | ring->default_context->engine[ring->id].state); | |
1485 | ||
73d477f6 OM |
1486 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); |
1487 | I915_WRITE(RING_HWSTAM(ring->mmio_base), 0xffffffff); | |
1488 | ||
2e5356da AS |
1489 | if (ring->status_page.obj) { |
1490 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
1491 | (u32)ring->status_page.gfx_addr); | |
1492 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1493 | } | |
1494 | ||
9b1136d5 OM |
1495 | I915_WRITE(RING_MODE_GEN7(ring), |
1496 | _MASKED_BIT_DISABLE(GFX_REPLAY_MODE) | | |
1497 | _MASKED_BIT_ENABLE(GFX_RUN_LIST_ENABLE)); | |
1498 | POSTING_READ(RING_MODE_GEN7(ring)); | |
c0a03a2e | 1499 | ring->next_context_status_buffer = 0; |
9b1136d5 OM |
1500 | DRM_DEBUG_DRIVER("Execlists enabled for %s\n", ring->name); |
1501 | ||
1502 | memset(&ring->hangcheck, 0, sizeof(ring->hangcheck)); | |
1503 | ||
1504 | return 0; | |
1505 | } | |
1506 | ||
1507 | static int gen8_init_render_ring(struct intel_engine_cs *ring) | |
1508 | { | |
1509 | struct drm_device *dev = ring->dev; | |
1510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1511 | int ret; | |
1512 | ||
1513 | ret = gen8_init_common_ring(ring); | |
1514 | if (ret) | |
1515 | return ret; | |
1516 | ||
1517 | /* We need to disable the AsyncFlip performance optimisations in order | |
1518 | * to use MI_WAIT_FOR_EVENT within the CS. It should already be | |
1519 | * programmed to '1' on all products. | |
1520 | * | |
1521 | * WaDisableAsyncFlipPerfMode:snb,ivb,hsw,vlv,bdw,chv | |
1522 | */ | |
1523 | I915_WRITE(MI_MODE, _MASKED_BIT_ENABLE(ASYNC_FLIP_PERF_DISABLE)); | |
1524 | ||
9b1136d5 OM |
1525 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_FORCE_ORDERING)); |
1526 | ||
771b9a53 | 1527 | return init_workarounds_ring(ring); |
9b1136d5 OM |
1528 | } |
1529 | ||
82ef822e DL |
1530 | static int gen9_init_render_ring(struct intel_engine_cs *ring) |
1531 | { | |
1532 | int ret; | |
1533 | ||
1534 | ret = gen8_init_common_ring(ring); | |
1535 | if (ret) | |
1536 | return ret; | |
1537 | ||
1538 | return init_workarounds_ring(ring); | |
1539 | } | |
1540 | ||
7a01a0a2 MT |
1541 | static int intel_logical_ring_emit_pdps(struct drm_i915_gem_request *req) |
1542 | { | |
1543 | struct i915_hw_ppgtt *ppgtt = req->ctx->ppgtt; | |
1544 | struct intel_engine_cs *ring = req->ring; | |
1545 | struct intel_ringbuffer *ringbuf = req->ringbuf; | |
1546 | const int num_lri_cmds = GEN8_LEGACY_PDPES * 2; | |
1547 | int i, ret; | |
1548 | ||
1549 | ret = intel_logical_ring_begin(req, num_lri_cmds * 2 + 2); | |
1550 | if (ret) | |
1551 | return ret; | |
1552 | ||
1553 | intel_logical_ring_emit(ringbuf, MI_LOAD_REGISTER_IMM(num_lri_cmds)); | |
1554 | for (i = GEN8_LEGACY_PDPES - 1; i >= 0; i--) { | |
1555 | const dma_addr_t pd_daddr = i915_page_dir_dma_addr(ppgtt, i); | |
1556 | ||
1557 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_UDW(ring, i)); | |
1558 | intel_logical_ring_emit(ringbuf, upper_32_bits(pd_daddr)); | |
1559 | intel_logical_ring_emit(ringbuf, GEN8_RING_PDP_LDW(ring, i)); | |
1560 | intel_logical_ring_emit(ringbuf, lower_32_bits(pd_daddr)); | |
1561 | } | |
1562 | ||
1563 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1564 | intel_logical_ring_advance(ringbuf); | |
1565 | ||
1566 | return 0; | |
1567 | } | |
1568 | ||
be795fc1 | 1569 | static int gen8_emit_bb_start(struct drm_i915_gem_request *req, |
8e004efc | 1570 | u64 offset, unsigned dispatch_flags) |
15648585 | 1571 | { |
be795fc1 | 1572 | struct intel_ringbuffer *ringbuf = req->ringbuf; |
8e004efc | 1573 | bool ppgtt = !(dispatch_flags & I915_DISPATCH_SECURE); |
15648585 OM |
1574 | int ret; |
1575 | ||
7a01a0a2 MT |
1576 | /* Don't rely in hw updating PDPs, specially in lite-restore. |
1577 | * Ideally, we should set Force PD Restore in ctx descriptor, | |
1578 | * but we can't. Force Restore would be a second option, but | |
1579 | * it is unsafe in case of lite-restore (because the ctx is | |
2dba3239 MT |
1580 | * not idle). PML4 is allocated during ppgtt init so this is |
1581 | * not needed in 48-bit.*/ | |
7a01a0a2 MT |
1582 | if (req->ctx->ppgtt && |
1583 | (intel_ring_flag(req->ring) & req->ctx->ppgtt->pd_dirty_rings)) { | |
331f38e7 ZL |
1584 | if (!USES_FULL_48BIT_PPGTT(req->i915) && |
1585 | !intel_vgpu_active(req->i915->dev)) { | |
2dba3239 MT |
1586 | ret = intel_logical_ring_emit_pdps(req); |
1587 | if (ret) | |
1588 | return ret; | |
1589 | } | |
7a01a0a2 MT |
1590 | |
1591 | req->ctx->ppgtt->pd_dirty_rings &= ~intel_ring_flag(req->ring); | |
1592 | } | |
1593 | ||
4d616a29 | 1594 | ret = intel_logical_ring_begin(req, 4); |
15648585 OM |
1595 | if (ret) |
1596 | return ret; | |
1597 | ||
1598 | /* FIXME(BDW): Address space and security selectors. */ | |
6922528a AJ |
1599 | intel_logical_ring_emit(ringbuf, MI_BATCH_BUFFER_START_GEN8 | |
1600 | (ppgtt<<8) | | |
1601 | (dispatch_flags & I915_DISPATCH_RS ? | |
1602 | MI_BATCH_RESOURCE_STREAMER : 0)); | |
15648585 OM |
1603 | intel_logical_ring_emit(ringbuf, lower_32_bits(offset)); |
1604 | intel_logical_ring_emit(ringbuf, upper_32_bits(offset)); | |
1605 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1606 | intel_logical_ring_advance(ringbuf); | |
1607 | ||
1608 | return 0; | |
1609 | } | |
1610 | ||
73d477f6 OM |
1611 | static bool gen8_logical_ring_get_irq(struct intel_engine_cs *ring) |
1612 | { | |
1613 | struct drm_device *dev = ring->dev; | |
1614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1615 | unsigned long flags; | |
1616 | ||
7cd512f1 | 1617 | if (WARN_ON(!intel_irqs_enabled(dev_priv))) |
73d477f6 OM |
1618 | return false; |
1619 | ||
1620 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1621 | if (ring->irq_refcount++ == 0) { | |
1622 | I915_WRITE_IMR(ring, ~(ring->irq_enable_mask | ring->irq_keep_mask)); | |
1623 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1624 | } | |
1625 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1626 | ||
1627 | return true; | |
1628 | } | |
1629 | ||
1630 | static void gen8_logical_ring_put_irq(struct intel_engine_cs *ring) | |
1631 | { | |
1632 | struct drm_device *dev = ring->dev; | |
1633 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1634 | unsigned long flags; | |
1635 | ||
1636 | spin_lock_irqsave(&dev_priv->irq_lock, flags); | |
1637 | if (--ring->irq_refcount == 0) { | |
1638 | I915_WRITE_IMR(ring, ~ring->irq_keep_mask); | |
1639 | POSTING_READ(RING_IMR(ring->mmio_base)); | |
1640 | } | |
1641 | spin_unlock_irqrestore(&dev_priv->irq_lock, flags); | |
1642 | } | |
1643 | ||
7deb4d39 | 1644 | static int gen8_emit_flush(struct drm_i915_gem_request *request, |
4712274c OM |
1645 | u32 invalidate_domains, |
1646 | u32 unused) | |
1647 | { | |
7deb4d39 | 1648 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1649 | struct intel_engine_cs *ring = ringbuf->ring; |
1650 | struct drm_device *dev = ring->dev; | |
1651 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1652 | uint32_t cmd; | |
1653 | int ret; | |
1654 | ||
4d616a29 | 1655 | ret = intel_logical_ring_begin(request, 4); |
4712274c OM |
1656 | if (ret) |
1657 | return ret; | |
1658 | ||
1659 | cmd = MI_FLUSH_DW + 1; | |
1660 | ||
f0a1fb10 CW |
1661 | /* We always require a command barrier so that subsequent |
1662 | * commands, such as breadcrumb interrupts, are strictly ordered | |
1663 | * wrt the contents of the write cache being flushed to memory | |
1664 | * (and thus being coherent from the CPU). | |
1665 | */ | |
1666 | cmd |= MI_FLUSH_DW_STORE_INDEX | MI_FLUSH_DW_OP_STOREDW; | |
1667 | ||
1668 | if (invalidate_domains & I915_GEM_GPU_DOMAINS) { | |
1669 | cmd |= MI_INVALIDATE_TLB; | |
1670 | if (ring == &dev_priv->ring[VCS]) | |
1671 | cmd |= MI_INVALIDATE_BSD; | |
4712274c OM |
1672 | } |
1673 | ||
1674 | intel_logical_ring_emit(ringbuf, cmd); | |
1675 | intel_logical_ring_emit(ringbuf, | |
1676 | I915_GEM_HWS_SCRATCH_ADDR | | |
1677 | MI_FLUSH_DW_USE_GTT); | |
1678 | intel_logical_ring_emit(ringbuf, 0); /* upper addr */ | |
1679 | intel_logical_ring_emit(ringbuf, 0); /* value */ | |
1680 | intel_logical_ring_advance(ringbuf); | |
1681 | ||
1682 | return 0; | |
1683 | } | |
1684 | ||
7deb4d39 | 1685 | static int gen8_emit_flush_render(struct drm_i915_gem_request *request, |
4712274c OM |
1686 | u32 invalidate_domains, |
1687 | u32 flush_domains) | |
1688 | { | |
7deb4d39 | 1689 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4712274c OM |
1690 | struct intel_engine_cs *ring = ringbuf->ring; |
1691 | u32 scratch_addr = ring->scratch.gtt_offset + 2 * CACHELINE_BYTES; | |
9647ff36 | 1692 | bool vf_flush_wa; |
4712274c OM |
1693 | u32 flags = 0; |
1694 | int ret; | |
1695 | ||
1696 | flags |= PIPE_CONTROL_CS_STALL; | |
1697 | ||
1698 | if (flush_domains) { | |
1699 | flags |= PIPE_CONTROL_RENDER_TARGET_CACHE_FLUSH; | |
1700 | flags |= PIPE_CONTROL_DEPTH_CACHE_FLUSH; | |
1701 | } | |
1702 | ||
1703 | if (invalidate_domains) { | |
1704 | flags |= PIPE_CONTROL_TLB_INVALIDATE; | |
1705 | flags |= PIPE_CONTROL_INSTRUCTION_CACHE_INVALIDATE; | |
1706 | flags |= PIPE_CONTROL_TEXTURE_CACHE_INVALIDATE; | |
1707 | flags |= PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1708 | flags |= PIPE_CONTROL_CONST_CACHE_INVALIDATE; | |
1709 | flags |= PIPE_CONTROL_STATE_CACHE_INVALIDATE; | |
1710 | flags |= PIPE_CONTROL_QW_WRITE; | |
1711 | flags |= PIPE_CONTROL_GLOBAL_GTT_IVB; | |
1712 | } | |
1713 | ||
9647ff36 ID |
1714 | /* |
1715 | * On GEN9+ Before VF_CACHE_INVALIDATE we need to emit a NULL pipe | |
1716 | * control. | |
1717 | */ | |
1718 | vf_flush_wa = INTEL_INFO(ring->dev)->gen >= 9 && | |
1719 | flags & PIPE_CONTROL_VF_CACHE_INVALIDATE; | |
1720 | ||
4d616a29 | 1721 | ret = intel_logical_ring_begin(request, vf_flush_wa ? 12 : 6); |
4712274c OM |
1722 | if (ret) |
1723 | return ret; | |
1724 | ||
9647ff36 ID |
1725 | if (vf_flush_wa) { |
1726 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); | |
1727 | intel_logical_ring_emit(ringbuf, 0); | |
1728 | intel_logical_ring_emit(ringbuf, 0); | |
1729 | intel_logical_ring_emit(ringbuf, 0); | |
1730 | intel_logical_ring_emit(ringbuf, 0); | |
1731 | intel_logical_ring_emit(ringbuf, 0); | |
1732 | } | |
1733 | ||
4712274c OM |
1734 | intel_logical_ring_emit(ringbuf, GFX_OP_PIPE_CONTROL(6)); |
1735 | intel_logical_ring_emit(ringbuf, flags); | |
1736 | intel_logical_ring_emit(ringbuf, scratch_addr); | |
1737 | intel_logical_ring_emit(ringbuf, 0); | |
1738 | intel_logical_ring_emit(ringbuf, 0); | |
1739 | intel_logical_ring_emit(ringbuf, 0); | |
1740 | intel_logical_ring_advance(ringbuf); | |
1741 | ||
1742 | return 0; | |
1743 | } | |
1744 | ||
e94e37ad OM |
1745 | static u32 gen8_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1746 | { | |
1747 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1748 | } | |
1749 | ||
1750 | static void gen8_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1751 | { | |
1752 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1753 | } | |
1754 | ||
319404df ID |
1755 | static u32 bxt_a_get_seqno(struct intel_engine_cs *ring, bool lazy_coherency) |
1756 | { | |
1757 | ||
1758 | /* | |
1759 | * On BXT A steppings there is a HW coherency issue whereby the | |
1760 | * MI_STORE_DATA_IMM storing the completed request's seqno | |
1761 | * occasionally doesn't invalidate the CPU cache. Work around this by | |
1762 | * clflushing the corresponding cacheline whenever the caller wants | |
1763 | * the coherency to be guaranteed. Note that this cacheline is known | |
1764 | * to be clean at this point, since we only write it in | |
1765 | * bxt_a_set_seqno(), where we also do a clflush after the write. So | |
1766 | * this clflush in practice becomes an invalidate operation. | |
1767 | */ | |
1768 | ||
1769 | if (!lazy_coherency) | |
1770 | intel_flush_status_page(ring, I915_GEM_HWS_INDEX); | |
1771 | ||
1772 | return intel_read_status_page(ring, I915_GEM_HWS_INDEX); | |
1773 | } | |
1774 | ||
1775 | static void bxt_a_set_seqno(struct intel_engine_cs *ring, u32 seqno) | |
1776 | { | |
1777 | intel_write_status_page(ring, I915_GEM_HWS_INDEX, seqno); | |
1778 | ||
1779 | /* See bxt_a_get_seqno() explaining the reason for the clflush. */ | |
1780 | intel_flush_status_page(ring, I915_GEM_HWS_INDEX); | |
1781 | } | |
1782 | ||
c4e76638 | 1783 | static int gen8_emit_request(struct drm_i915_gem_request *request) |
4da46e1e | 1784 | { |
c4e76638 | 1785 | struct intel_ringbuffer *ringbuf = request->ringbuf; |
4da46e1e OM |
1786 | struct intel_engine_cs *ring = ringbuf->ring; |
1787 | u32 cmd; | |
1788 | int ret; | |
1789 | ||
53292cdb MT |
1790 | /* |
1791 | * Reserve space for 2 NOOPs at the end of each request to be | |
1792 | * used as a workaround for not being allowed to do lite | |
1793 | * restore with HEAD==TAIL (WaIdleLiteRestore). | |
1794 | */ | |
4d616a29 | 1795 | ret = intel_logical_ring_begin(request, 8); |
4da46e1e OM |
1796 | if (ret) |
1797 | return ret; | |
1798 | ||
8edfbb8b | 1799 | cmd = MI_STORE_DWORD_IMM_GEN4; |
4da46e1e OM |
1800 | cmd |= MI_GLOBAL_GTT; |
1801 | ||
1802 | intel_logical_ring_emit(ringbuf, cmd); | |
1803 | intel_logical_ring_emit(ringbuf, | |
1804 | (ring->status_page.gfx_addr + | |
1805 | (I915_GEM_HWS_INDEX << MI_STORE_DWORD_INDEX_SHIFT))); | |
1806 | intel_logical_ring_emit(ringbuf, 0); | |
c4e76638 | 1807 | intel_logical_ring_emit(ringbuf, i915_gem_request_get_seqno(request)); |
4da46e1e OM |
1808 | intel_logical_ring_emit(ringbuf, MI_USER_INTERRUPT); |
1809 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
ae70797d | 1810 | intel_logical_ring_advance_and_submit(request); |
4da46e1e | 1811 | |
53292cdb MT |
1812 | /* |
1813 | * Here we add two extra NOOPs as padding to avoid | |
1814 | * lite restore of a context with HEAD==TAIL. | |
1815 | */ | |
1816 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1817 | intel_logical_ring_emit(ringbuf, MI_NOOP); | |
1818 | intel_logical_ring_advance(ringbuf); | |
1819 | ||
4da46e1e OM |
1820 | return 0; |
1821 | } | |
1822 | ||
be01363f | 1823 | static int intel_lr_context_render_state_init(struct drm_i915_gem_request *req) |
cef437ad | 1824 | { |
cef437ad | 1825 | struct render_state so; |
cef437ad DL |
1826 | int ret; |
1827 | ||
be01363f | 1828 | ret = i915_gem_render_state_prepare(req->ring, &so); |
cef437ad DL |
1829 | if (ret) |
1830 | return ret; | |
1831 | ||
1832 | if (so.rodata == NULL) | |
1833 | return 0; | |
1834 | ||
be795fc1 | 1835 | ret = req->ring->emit_bb_start(req, so.ggtt_offset, |
be01363f | 1836 | I915_DISPATCH_SECURE); |
cef437ad DL |
1837 | if (ret) |
1838 | goto out; | |
1839 | ||
84e81020 AS |
1840 | ret = req->ring->emit_bb_start(req, |
1841 | (so.ggtt_offset + so.aux_batch_offset), | |
1842 | I915_DISPATCH_SECURE); | |
1843 | if (ret) | |
1844 | goto out; | |
1845 | ||
b2af0376 | 1846 | i915_vma_move_to_active(i915_gem_obj_to_ggtt(so.obj), req); |
cef437ad | 1847 | |
cef437ad DL |
1848 | out: |
1849 | i915_gem_render_state_fini(&so); | |
1850 | return ret; | |
1851 | } | |
1852 | ||
8753181e | 1853 | static int gen8_init_rcs_context(struct drm_i915_gem_request *req) |
e7778be1 TD |
1854 | { |
1855 | int ret; | |
1856 | ||
e2be4faf | 1857 | ret = intel_logical_ring_workarounds_emit(req); |
e7778be1 TD |
1858 | if (ret) |
1859 | return ret; | |
1860 | ||
3bbaba0c PA |
1861 | ret = intel_rcs_context_init_mocs(req); |
1862 | /* | |
1863 | * Failing to program the MOCS is non-fatal.The system will not | |
1864 | * run at peak performance. So generate an error and carry on. | |
1865 | */ | |
1866 | if (ret) | |
1867 | DRM_ERROR("MOCS failed to program: expect performance issues.\n"); | |
1868 | ||
be01363f | 1869 | return intel_lr_context_render_state_init(req); |
e7778be1 TD |
1870 | } |
1871 | ||
73e4d07f OM |
1872 | /** |
1873 | * intel_logical_ring_cleanup() - deallocate the Engine Command Streamer | |
1874 | * | |
1875 | * @ring: Engine Command Streamer. | |
1876 | * | |
1877 | */ | |
454afebd OM |
1878 | void intel_logical_ring_cleanup(struct intel_engine_cs *ring) |
1879 | { | |
6402c330 | 1880 | struct drm_i915_private *dev_priv; |
9832b9da | 1881 | |
48d82387 OM |
1882 | if (!intel_ring_initialized(ring)) |
1883 | return; | |
1884 | ||
6402c330 JH |
1885 | dev_priv = ring->dev->dev_private; |
1886 | ||
9832b9da OM |
1887 | intel_logical_ring_stop(ring); |
1888 | WARN_ON((I915_READ_MODE(ring) & MODE_IDLE) == 0); | |
48d82387 OM |
1889 | |
1890 | if (ring->cleanup) | |
1891 | ring->cleanup(ring); | |
1892 | ||
1893 | i915_cmd_parser_fini_ring(ring); | |
06fbca71 | 1894 | i915_gem_batch_pool_fini(&ring->batch_pool); |
48d82387 OM |
1895 | |
1896 | if (ring->status_page.obj) { | |
1897 | kunmap(sg_page(ring->status_page.obj->pages->sgl)); | |
1898 | ring->status_page.obj = NULL; | |
1899 | } | |
17ee950d AS |
1900 | |
1901 | lrc_destroy_wa_ctx_obj(ring); | |
454afebd OM |
1902 | } |
1903 | ||
1904 | static int logical_ring_init(struct drm_device *dev, struct intel_engine_cs *ring) | |
1905 | { | |
48d82387 | 1906 | int ret; |
48d82387 OM |
1907 | |
1908 | /* Intentionally left blank. */ | |
1909 | ring->buffer = NULL; | |
1910 | ||
1911 | ring->dev = dev; | |
1912 | INIT_LIST_HEAD(&ring->active_list); | |
1913 | INIT_LIST_HEAD(&ring->request_list); | |
06fbca71 | 1914 | i915_gem_batch_pool_init(dev, &ring->batch_pool); |
48d82387 OM |
1915 | init_waitqueue_head(&ring->irq_queue); |
1916 | ||
acdd884a | 1917 | INIT_LIST_HEAD(&ring->execlist_queue); |
c86ee3a9 | 1918 | INIT_LIST_HEAD(&ring->execlist_retired_req_list); |
acdd884a MT |
1919 | spin_lock_init(&ring->execlist_lock); |
1920 | ||
48d82387 OM |
1921 | ret = i915_cmd_parser_init_ring(ring); |
1922 | if (ret) | |
1923 | return ret; | |
1924 | ||
e84fe803 NH |
1925 | ret = intel_lr_context_deferred_alloc(ring->default_context, ring); |
1926 | if (ret) | |
1927 | return ret; | |
1928 | ||
1929 | /* As this is the default context, always pin it */ | |
1930 | ret = intel_lr_context_do_pin( | |
1931 | ring, | |
1932 | ring->default_context->engine[ring->id].state, | |
1933 | ring->default_context->engine[ring->id].ringbuf); | |
1934 | if (ret) { | |
1935 | DRM_ERROR( | |
1936 | "Failed to pin and map ringbuffer %s: %d\n", | |
1937 | ring->name, ret); | |
1938 | return ret; | |
1939 | } | |
564ddb2f OM |
1940 | |
1941 | return ret; | |
454afebd OM |
1942 | } |
1943 | ||
1944 | static int logical_render_ring_init(struct drm_device *dev) | |
1945 | { | |
1946 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1947 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; | |
99be1dfe | 1948 | int ret; |
454afebd OM |
1949 | |
1950 | ring->name = "render ring"; | |
1951 | ring->id = RCS; | |
1952 | ring->mmio_base = RENDER_RING_BASE; | |
1953 | ring->irq_enable_mask = | |
1954 | GT_RENDER_USER_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
73d477f6 OM |
1955 | ring->irq_keep_mask = |
1956 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_RCS_IRQ_SHIFT; | |
1957 | if (HAS_L3_DPF(dev)) | |
1958 | ring->irq_keep_mask |= GT_RENDER_L3_PARITY_ERROR_INTERRUPT; | |
454afebd | 1959 | |
82ef822e DL |
1960 | if (INTEL_INFO(dev)->gen >= 9) |
1961 | ring->init_hw = gen9_init_render_ring; | |
1962 | else | |
1963 | ring->init_hw = gen8_init_render_ring; | |
e7778be1 | 1964 | ring->init_context = gen8_init_rcs_context; |
9b1136d5 | 1965 | ring->cleanup = intel_fini_pipe_control; |
319404df ID |
1966 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
1967 | ring->get_seqno = bxt_a_get_seqno; | |
1968 | ring->set_seqno = bxt_a_set_seqno; | |
1969 | } else { | |
1970 | ring->get_seqno = gen8_get_seqno; | |
1971 | ring->set_seqno = gen8_set_seqno; | |
1972 | } | |
4da46e1e | 1973 | ring->emit_request = gen8_emit_request; |
4712274c | 1974 | ring->emit_flush = gen8_emit_flush_render; |
73d477f6 OM |
1975 | ring->irq_get = gen8_logical_ring_get_irq; |
1976 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 1977 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 1978 | |
99be1dfe | 1979 | ring->dev = dev; |
c4db7599 AS |
1980 | |
1981 | ret = intel_init_pipe_control(ring); | |
99be1dfe DV |
1982 | if (ret) |
1983 | return ret; | |
1984 | ||
17ee950d AS |
1985 | ret = intel_init_workaround_bb(ring); |
1986 | if (ret) { | |
1987 | /* | |
1988 | * We continue even if we fail to initialize WA batch | |
1989 | * because we only expect rare glitches but nothing | |
1990 | * critical to prevent us from using GPU | |
1991 | */ | |
1992 | DRM_ERROR("WA batch buffer initialization failed: %d\n", | |
1993 | ret); | |
1994 | } | |
1995 | ||
c4db7599 AS |
1996 | ret = logical_ring_init(dev, ring); |
1997 | if (ret) { | |
17ee950d | 1998 | lrc_destroy_wa_ctx_obj(ring); |
c4db7599 | 1999 | } |
17ee950d AS |
2000 | |
2001 | return ret; | |
454afebd OM |
2002 | } |
2003 | ||
2004 | static int logical_bsd_ring_init(struct drm_device *dev) | |
2005 | { | |
2006 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2007 | struct intel_engine_cs *ring = &dev_priv->ring[VCS]; | |
2008 | ||
2009 | ring->name = "bsd ring"; | |
2010 | ring->id = VCS; | |
2011 | ring->mmio_base = GEN6_BSD_RING_BASE; | |
2012 | ring->irq_enable_mask = | |
2013 | GT_RENDER_USER_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
73d477f6 OM |
2014 | ring->irq_keep_mask = |
2015 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS1_IRQ_SHIFT; | |
454afebd | 2016 | |
ecfe00d8 | 2017 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
2018 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
2019 | ring->get_seqno = bxt_a_get_seqno; | |
2020 | ring->set_seqno = bxt_a_set_seqno; | |
2021 | } else { | |
2022 | ring->get_seqno = gen8_get_seqno; | |
2023 | ring->set_seqno = gen8_set_seqno; | |
2024 | } | |
4da46e1e | 2025 | ring->emit_request = gen8_emit_request; |
4712274c | 2026 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2027 | ring->irq_get = gen8_logical_ring_get_irq; |
2028 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2029 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2030 | |
454afebd OM |
2031 | return logical_ring_init(dev, ring); |
2032 | } | |
2033 | ||
2034 | static int logical_bsd2_ring_init(struct drm_device *dev) | |
2035 | { | |
2036 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2037 | struct intel_engine_cs *ring = &dev_priv->ring[VCS2]; | |
2038 | ||
2039 | ring->name = "bds2 ring"; | |
2040 | ring->id = VCS2; | |
2041 | ring->mmio_base = GEN8_BSD2_RING_BASE; | |
2042 | ring->irq_enable_mask = | |
2043 | GT_RENDER_USER_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
73d477f6 OM |
2044 | ring->irq_keep_mask = |
2045 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VCS2_IRQ_SHIFT; | |
454afebd | 2046 | |
ecfe00d8 | 2047 | ring->init_hw = gen8_init_common_ring; |
e94e37ad OM |
2048 | ring->get_seqno = gen8_get_seqno; |
2049 | ring->set_seqno = gen8_set_seqno; | |
4da46e1e | 2050 | ring->emit_request = gen8_emit_request; |
4712274c | 2051 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2052 | ring->irq_get = gen8_logical_ring_get_irq; |
2053 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2054 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2055 | |
454afebd OM |
2056 | return logical_ring_init(dev, ring); |
2057 | } | |
2058 | ||
2059 | static int logical_blt_ring_init(struct drm_device *dev) | |
2060 | { | |
2061 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2062 | struct intel_engine_cs *ring = &dev_priv->ring[BCS]; | |
2063 | ||
2064 | ring->name = "blitter ring"; | |
2065 | ring->id = BCS; | |
2066 | ring->mmio_base = BLT_RING_BASE; | |
2067 | ring->irq_enable_mask = | |
2068 | GT_RENDER_USER_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
73d477f6 OM |
2069 | ring->irq_keep_mask = |
2070 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_BCS_IRQ_SHIFT; | |
454afebd | 2071 | |
ecfe00d8 | 2072 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
2073 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
2074 | ring->get_seqno = bxt_a_get_seqno; | |
2075 | ring->set_seqno = bxt_a_set_seqno; | |
2076 | } else { | |
2077 | ring->get_seqno = gen8_get_seqno; | |
2078 | ring->set_seqno = gen8_set_seqno; | |
2079 | } | |
4da46e1e | 2080 | ring->emit_request = gen8_emit_request; |
4712274c | 2081 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2082 | ring->irq_get = gen8_logical_ring_get_irq; |
2083 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2084 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2085 | |
454afebd OM |
2086 | return logical_ring_init(dev, ring); |
2087 | } | |
2088 | ||
2089 | static int logical_vebox_ring_init(struct drm_device *dev) | |
2090 | { | |
2091 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2092 | struct intel_engine_cs *ring = &dev_priv->ring[VECS]; | |
2093 | ||
2094 | ring->name = "video enhancement ring"; | |
2095 | ring->id = VECS; | |
2096 | ring->mmio_base = VEBOX_RING_BASE; | |
2097 | ring->irq_enable_mask = | |
2098 | GT_RENDER_USER_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
73d477f6 OM |
2099 | ring->irq_keep_mask = |
2100 | GT_CONTEXT_SWITCH_INTERRUPT << GEN8_VECS_IRQ_SHIFT; | |
454afebd | 2101 | |
ecfe00d8 | 2102 | ring->init_hw = gen8_init_common_ring; |
319404df ID |
2103 | if (IS_BROXTON(dev) && INTEL_REVID(dev) < BXT_REVID_B0) { |
2104 | ring->get_seqno = bxt_a_get_seqno; | |
2105 | ring->set_seqno = bxt_a_set_seqno; | |
2106 | } else { | |
2107 | ring->get_seqno = gen8_get_seqno; | |
2108 | ring->set_seqno = gen8_set_seqno; | |
2109 | } | |
4da46e1e | 2110 | ring->emit_request = gen8_emit_request; |
4712274c | 2111 | ring->emit_flush = gen8_emit_flush; |
73d477f6 OM |
2112 | ring->irq_get = gen8_logical_ring_get_irq; |
2113 | ring->irq_put = gen8_logical_ring_put_irq; | |
15648585 | 2114 | ring->emit_bb_start = gen8_emit_bb_start; |
9b1136d5 | 2115 | |
454afebd OM |
2116 | return logical_ring_init(dev, ring); |
2117 | } | |
2118 | ||
73e4d07f OM |
2119 | /** |
2120 | * intel_logical_rings_init() - allocate, populate and init the Engine Command Streamers | |
2121 | * @dev: DRM device. | |
2122 | * | |
2123 | * This function inits the engines for an Execlists submission style (the equivalent in the | |
2124 | * legacy ringbuffer submission world would be i915_gem_init_rings). It does it only for | |
2125 | * those engines that are present in the hardware. | |
2126 | * | |
2127 | * Return: non-zero if the initialization failed. | |
2128 | */ | |
454afebd OM |
2129 | int intel_logical_rings_init(struct drm_device *dev) |
2130 | { | |
2131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2132 | int ret; | |
2133 | ||
2134 | ret = logical_render_ring_init(dev); | |
2135 | if (ret) | |
2136 | return ret; | |
2137 | ||
2138 | if (HAS_BSD(dev)) { | |
2139 | ret = logical_bsd_ring_init(dev); | |
2140 | if (ret) | |
2141 | goto cleanup_render_ring; | |
2142 | } | |
2143 | ||
2144 | if (HAS_BLT(dev)) { | |
2145 | ret = logical_blt_ring_init(dev); | |
2146 | if (ret) | |
2147 | goto cleanup_bsd_ring; | |
2148 | } | |
2149 | ||
2150 | if (HAS_VEBOX(dev)) { | |
2151 | ret = logical_vebox_ring_init(dev); | |
2152 | if (ret) | |
2153 | goto cleanup_blt_ring; | |
2154 | } | |
2155 | ||
2156 | if (HAS_BSD2(dev)) { | |
2157 | ret = logical_bsd2_ring_init(dev); | |
2158 | if (ret) | |
2159 | goto cleanup_vebox_ring; | |
2160 | } | |
2161 | ||
454afebd OM |
2162 | return 0; |
2163 | ||
454afebd OM |
2164 | cleanup_vebox_ring: |
2165 | intel_logical_ring_cleanup(&dev_priv->ring[VECS]); | |
2166 | cleanup_blt_ring: | |
2167 | intel_logical_ring_cleanup(&dev_priv->ring[BCS]); | |
2168 | cleanup_bsd_ring: | |
2169 | intel_logical_ring_cleanup(&dev_priv->ring[VCS]); | |
2170 | cleanup_render_ring: | |
2171 | intel_logical_ring_cleanup(&dev_priv->ring[RCS]); | |
2172 | ||
2173 | return ret; | |
2174 | } | |
2175 | ||
0cea6502 JM |
2176 | static u32 |
2177 | make_rpcs(struct drm_device *dev) | |
2178 | { | |
2179 | u32 rpcs = 0; | |
2180 | ||
2181 | /* | |
2182 | * No explicit RPCS request is needed to ensure full | |
2183 | * slice/subslice/EU enablement prior to Gen9. | |
2184 | */ | |
2185 | if (INTEL_INFO(dev)->gen < 9) | |
2186 | return 0; | |
2187 | ||
2188 | /* | |
2189 | * Starting in Gen9, render power gating can leave | |
2190 | * slice/subslice/EU in a partially enabled state. We | |
2191 | * must make an explicit request through RPCS for full | |
2192 | * enablement. | |
2193 | */ | |
2194 | if (INTEL_INFO(dev)->has_slice_pg) { | |
2195 | rpcs |= GEN8_RPCS_S_CNT_ENABLE; | |
2196 | rpcs |= INTEL_INFO(dev)->slice_total << | |
2197 | GEN8_RPCS_S_CNT_SHIFT; | |
2198 | rpcs |= GEN8_RPCS_ENABLE; | |
2199 | } | |
2200 | ||
2201 | if (INTEL_INFO(dev)->has_subslice_pg) { | |
2202 | rpcs |= GEN8_RPCS_SS_CNT_ENABLE; | |
2203 | rpcs |= INTEL_INFO(dev)->subslice_per_slice << | |
2204 | GEN8_RPCS_SS_CNT_SHIFT; | |
2205 | rpcs |= GEN8_RPCS_ENABLE; | |
2206 | } | |
2207 | ||
2208 | if (INTEL_INFO(dev)->has_eu_pg) { | |
2209 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2210 | GEN8_RPCS_EU_MIN_SHIFT; | |
2211 | rpcs |= INTEL_INFO(dev)->eu_per_subslice << | |
2212 | GEN8_RPCS_EU_MAX_SHIFT; | |
2213 | rpcs |= GEN8_RPCS_ENABLE; | |
2214 | } | |
2215 | ||
2216 | return rpcs; | |
2217 | } | |
2218 | ||
8670d6f9 OM |
2219 | static int |
2220 | populate_lr_context(struct intel_context *ctx, struct drm_i915_gem_object *ctx_obj, | |
2221 | struct intel_engine_cs *ring, struct intel_ringbuffer *ringbuf) | |
2222 | { | |
2d965536 TD |
2223 | struct drm_device *dev = ring->dev; |
2224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ae6c4806 | 2225 | struct i915_hw_ppgtt *ppgtt = ctx->ppgtt; |
8670d6f9 OM |
2226 | struct page *page; |
2227 | uint32_t *reg_state; | |
2228 | int ret; | |
2229 | ||
2d965536 TD |
2230 | if (!ppgtt) |
2231 | ppgtt = dev_priv->mm.aliasing_ppgtt; | |
2232 | ||
8670d6f9 OM |
2233 | ret = i915_gem_object_set_to_cpu_domain(ctx_obj, true); |
2234 | if (ret) { | |
2235 | DRM_DEBUG_DRIVER("Could not set to CPU domain\n"); | |
2236 | return ret; | |
2237 | } | |
2238 | ||
2239 | ret = i915_gem_object_get_pages(ctx_obj); | |
2240 | if (ret) { | |
2241 | DRM_DEBUG_DRIVER("Could not get object pages\n"); | |
2242 | return ret; | |
2243 | } | |
2244 | ||
2245 | i915_gem_object_pin_pages(ctx_obj); | |
2246 | ||
2247 | /* The second page of the context object contains some fields which must | |
2248 | * be set up prior to the first execution. */ | |
d1675198 | 2249 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
8670d6f9 OM |
2250 | reg_state = kmap_atomic(page); |
2251 | ||
2252 | /* A context is actually a big batch buffer with several MI_LOAD_REGISTER_IMM | |
2253 | * commands followed by (reg, value) pairs. The values we are setting here are | |
2254 | * only for the first context restore: on a subsequent save, the GPU will | |
2255 | * recreate this batchbuffer with new values (including all the missing | |
2256 | * MI_LOAD_REGISTER_IMM commands that we are not initializing here). */ | |
2257 | if (ring->id == RCS) | |
2258 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(14); | |
2259 | else | |
2260 | reg_state[CTX_LRI_HEADER_0] = MI_LOAD_REGISTER_IMM(11); | |
2261 | reg_state[CTX_LRI_HEADER_0] |= MI_LRI_FORCE_POSTED; | |
2262 | reg_state[CTX_CONTEXT_CONTROL] = RING_CONTEXT_CONTROL(ring); | |
2263 | reg_state[CTX_CONTEXT_CONTROL+1] = | |
5baa22c5 | 2264 | _MASKED_BIT_ENABLE(CTX_CTRL_INHIBIT_SYN_CTX_SWITCH | |
6922528a AJ |
2265 | CTX_CTRL_ENGINE_CTX_RESTORE_INHIBIT | |
2266 | CTX_CTRL_RS_CTX_ENABLE); | |
8670d6f9 OM |
2267 | reg_state[CTX_RING_HEAD] = RING_HEAD(ring->mmio_base); |
2268 | reg_state[CTX_RING_HEAD+1] = 0; | |
2269 | reg_state[CTX_RING_TAIL] = RING_TAIL(ring->mmio_base); | |
2270 | reg_state[CTX_RING_TAIL+1] = 0; | |
2271 | reg_state[CTX_RING_BUFFER_START] = RING_START(ring->mmio_base); | |
7ba717cf TD |
2272 | /* Ring buffer start address is not known until the buffer is pinned. |
2273 | * It is written to the context image in execlists_update_context() | |
2274 | */ | |
8670d6f9 OM |
2275 | reg_state[CTX_RING_BUFFER_CONTROL] = RING_CTL(ring->mmio_base); |
2276 | reg_state[CTX_RING_BUFFER_CONTROL+1] = | |
2277 | ((ringbuf->size - PAGE_SIZE) & RING_NR_PAGES) | RING_VALID; | |
2278 | reg_state[CTX_BB_HEAD_U] = ring->mmio_base + 0x168; | |
2279 | reg_state[CTX_BB_HEAD_U+1] = 0; | |
2280 | reg_state[CTX_BB_HEAD_L] = ring->mmio_base + 0x140; | |
2281 | reg_state[CTX_BB_HEAD_L+1] = 0; | |
2282 | reg_state[CTX_BB_STATE] = ring->mmio_base + 0x110; | |
2283 | reg_state[CTX_BB_STATE+1] = (1<<5); | |
2284 | reg_state[CTX_SECOND_BB_HEAD_U] = ring->mmio_base + 0x11c; | |
2285 | reg_state[CTX_SECOND_BB_HEAD_U+1] = 0; | |
2286 | reg_state[CTX_SECOND_BB_HEAD_L] = ring->mmio_base + 0x114; | |
2287 | reg_state[CTX_SECOND_BB_HEAD_L+1] = 0; | |
2288 | reg_state[CTX_SECOND_BB_STATE] = ring->mmio_base + 0x118; | |
2289 | reg_state[CTX_SECOND_BB_STATE+1] = 0; | |
2290 | if (ring->id == RCS) { | |
8670d6f9 OM |
2291 | reg_state[CTX_BB_PER_CTX_PTR] = ring->mmio_base + 0x1c0; |
2292 | reg_state[CTX_BB_PER_CTX_PTR+1] = 0; | |
2293 | reg_state[CTX_RCS_INDIRECT_CTX] = ring->mmio_base + 0x1c4; | |
2294 | reg_state[CTX_RCS_INDIRECT_CTX+1] = 0; | |
2295 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET] = ring->mmio_base + 0x1c8; | |
2296 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = 0; | |
17ee950d AS |
2297 | if (ring->wa_ctx.obj) { |
2298 | struct i915_ctx_workarounds *wa_ctx = &ring->wa_ctx; | |
2299 | uint32_t ggtt_offset = i915_gem_obj_ggtt_offset(wa_ctx->obj); | |
2300 | ||
2301 | reg_state[CTX_RCS_INDIRECT_CTX+1] = | |
2302 | (ggtt_offset + wa_ctx->indirect_ctx.offset * sizeof(uint32_t)) | | |
2303 | (wa_ctx->indirect_ctx.size / CACHELINE_DWORDS); | |
2304 | ||
2305 | reg_state[CTX_RCS_INDIRECT_CTX_OFFSET+1] = | |
2306 | CTX_RCS_INDIRECT_CTX_OFFSET_DEFAULT << 6; | |
2307 | ||
2308 | reg_state[CTX_BB_PER_CTX_PTR+1] = | |
2309 | (ggtt_offset + wa_ctx->per_ctx.offset * sizeof(uint32_t)) | | |
2310 | 0x01; | |
2311 | } | |
8670d6f9 OM |
2312 | } |
2313 | reg_state[CTX_LRI_HEADER_1] = MI_LOAD_REGISTER_IMM(9); | |
2314 | reg_state[CTX_LRI_HEADER_1] |= MI_LRI_FORCE_POSTED; | |
2315 | reg_state[CTX_CTX_TIMESTAMP] = ring->mmio_base + 0x3a8; | |
2316 | reg_state[CTX_CTX_TIMESTAMP+1] = 0; | |
2317 | reg_state[CTX_PDP3_UDW] = GEN8_RING_PDP_UDW(ring, 3); | |
2318 | reg_state[CTX_PDP3_LDW] = GEN8_RING_PDP_LDW(ring, 3); | |
2319 | reg_state[CTX_PDP2_UDW] = GEN8_RING_PDP_UDW(ring, 2); | |
2320 | reg_state[CTX_PDP2_LDW] = GEN8_RING_PDP_LDW(ring, 2); | |
2321 | reg_state[CTX_PDP1_UDW] = GEN8_RING_PDP_UDW(ring, 1); | |
2322 | reg_state[CTX_PDP1_LDW] = GEN8_RING_PDP_LDW(ring, 1); | |
2323 | reg_state[CTX_PDP0_UDW] = GEN8_RING_PDP_UDW(ring, 0); | |
2324 | reg_state[CTX_PDP0_LDW] = GEN8_RING_PDP_LDW(ring, 0); | |
d7b2633d | 2325 | |
2dba3239 MT |
2326 | if (USES_FULL_48BIT_PPGTT(ppgtt->base.dev)) { |
2327 | /* 64b PPGTT (48bit canonical) | |
2328 | * PDP0_DESCRIPTOR contains the base address to PML4 and | |
2329 | * other PDP Descriptors are ignored. | |
2330 | */ | |
2331 | ASSIGN_CTX_PML4(ppgtt, reg_state); | |
2332 | } else { | |
2333 | /* 32b PPGTT | |
2334 | * PDP*_DESCRIPTOR contains the base address of space supported. | |
2335 | * With dynamic page allocation, PDPs may not be allocated at | |
2336 | * this point. Point the unallocated PDPs to the scratch page | |
2337 | */ | |
2338 | ASSIGN_CTX_PDP(ppgtt, reg_state, 3); | |
2339 | ASSIGN_CTX_PDP(ppgtt, reg_state, 2); | |
2340 | ASSIGN_CTX_PDP(ppgtt, reg_state, 1); | |
2341 | ASSIGN_CTX_PDP(ppgtt, reg_state, 0); | |
2342 | } | |
2343 | ||
8670d6f9 OM |
2344 | if (ring->id == RCS) { |
2345 | reg_state[CTX_LRI_HEADER_2] = MI_LOAD_REGISTER_IMM(1); | |
0cea6502 JM |
2346 | reg_state[CTX_R_PWR_CLK_STATE] = GEN8_R_PWR_CLK_STATE; |
2347 | reg_state[CTX_R_PWR_CLK_STATE+1] = make_rpcs(dev); | |
8670d6f9 OM |
2348 | } |
2349 | ||
2350 | kunmap_atomic(reg_state); | |
2351 | ||
2352 | ctx_obj->dirty = 1; | |
2353 | set_page_dirty(page); | |
2354 | i915_gem_object_unpin_pages(ctx_obj); | |
2355 | ||
2356 | return 0; | |
2357 | } | |
2358 | ||
73e4d07f OM |
2359 | /** |
2360 | * intel_lr_context_free() - free the LRC specific bits of a context | |
2361 | * @ctx: the LR context to free. | |
2362 | * | |
2363 | * The real context freeing is done in i915_gem_context_free: this only | |
2364 | * takes care of the bits that are LRC related: the per-engine backing | |
2365 | * objects and the logical ringbuffer. | |
2366 | */ | |
ede7d42b OM |
2367 | void intel_lr_context_free(struct intel_context *ctx) |
2368 | { | |
8c857917 OM |
2369 | int i; |
2370 | ||
2371 | for (i = 0; i < I915_NUM_RINGS; i++) { | |
2372 | struct drm_i915_gem_object *ctx_obj = ctx->engine[i].state; | |
84c2377f | 2373 | |
8c857917 | 2374 | if (ctx_obj) { |
dcb4c12a OM |
2375 | struct intel_ringbuffer *ringbuf = |
2376 | ctx->engine[i].ringbuf; | |
2377 | struct intel_engine_cs *ring = ringbuf->ring; | |
2378 | ||
7ba717cf TD |
2379 | if (ctx == ring->default_context) { |
2380 | intel_unpin_ringbuffer_obj(ringbuf); | |
2381 | i915_gem_object_ggtt_unpin(ctx_obj); | |
2382 | } | |
a7cbedec | 2383 | WARN_ON(ctx->engine[ring->id].pin_count); |
01101fa7 | 2384 | intel_ringbuffer_free(ringbuf); |
8c857917 OM |
2385 | drm_gem_object_unreference(&ctx_obj->base); |
2386 | } | |
2387 | } | |
2388 | } | |
2389 | ||
2390 | static uint32_t get_lr_context_size(struct intel_engine_cs *ring) | |
2391 | { | |
2392 | int ret = 0; | |
2393 | ||
468c6816 | 2394 | WARN_ON(INTEL_INFO(ring->dev)->gen < 8); |
8c857917 OM |
2395 | |
2396 | switch (ring->id) { | |
2397 | case RCS: | |
468c6816 MN |
2398 | if (INTEL_INFO(ring->dev)->gen >= 9) |
2399 | ret = GEN9_LR_CONTEXT_RENDER_SIZE; | |
2400 | else | |
2401 | ret = GEN8_LR_CONTEXT_RENDER_SIZE; | |
8c857917 OM |
2402 | break; |
2403 | case VCS: | |
2404 | case BCS: | |
2405 | case VECS: | |
2406 | case VCS2: | |
2407 | ret = GEN8_LR_CONTEXT_OTHER_SIZE; | |
2408 | break; | |
2409 | } | |
2410 | ||
2411 | return ret; | |
ede7d42b OM |
2412 | } |
2413 | ||
70b0ea86 | 2414 | static void lrc_setup_hardware_status_page(struct intel_engine_cs *ring, |
1df06b75 TD |
2415 | struct drm_i915_gem_object *default_ctx_obj) |
2416 | { | |
2417 | struct drm_i915_private *dev_priv = ring->dev->dev_private; | |
d1675198 | 2418 | struct page *page; |
1df06b75 | 2419 | |
d1675198 AD |
2420 | /* The HWSP is part of the default context object in LRC mode. */ |
2421 | ring->status_page.gfx_addr = i915_gem_obj_ggtt_offset(default_ctx_obj) | |
2422 | + LRC_PPHWSP_PN * PAGE_SIZE; | |
2423 | page = i915_gem_object_get_page(default_ctx_obj, LRC_PPHWSP_PN); | |
2424 | ring->status_page.page_addr = kmap(page); | |
1df06b75 TD |
2425 | ring->status_page.obj = default_ctx_obj; |
2426 | ||
2427 | I915_WRITE(RING_HWS_PGA(ring->mmio_base), | |
2428 | (u32)ring->status_page.gfx_addr); | |
2429 | POSTING_READ(RING_HWS_PGA(ring->mmio_base)); | |
1df06b75 TD |
2430 | } |
2431 | ||
73e4d07f | 2432 | /** |
e84fe803 | 2433 | * intel_lr_context_deferred_alloc() - create the LRC specific bits of a context |
73e4d07f OM |
2434 | * @ctx: LR context to create. |
2435 | * @ring: engine to be used with the context. | |
2436 | * | |
2437 | * This function can be called more than once, with different engines, if we plan | |
2438 | * to use the context with them. The context backing objects and the ringbuffers | |
2439 | * (specially the ringbuffer backing objects) suck a lot of memory up, and that's why | |
2440 | * the creation is a deferred call: it's better to make sure first that we need to use | |
2441 | * a given ring with the context. | |
2442 | * | |
32197aab | 2443 | * Return: non-zero on error. |
73e4d07f | 2444 | */ |
e84fe803 NH |
2445 | |
2446 | int intel_lr_context_deferred_alloc(struct intel_context *ctx, | |
ede7d42b OM |
2447 | struct intel_engine_cs *ring) |
2448 | { | |
8c857917 OM |
2449 | struct drm_device *dev = ring->dev; |
2450 | struct drm_i915_gem_object *ctx_obj; | |
2451 | uint32_t context_size; | |
84c2377f | 2452 | struct intel_ringbuffer *ringbuf; |
8c857917 OM |
2453 | int ret; |
2454 | ||
ede7d42b | 2455 | WARN_ON(ctx->legacy_hw_ctx.rcs_state != NULL); |
bfc882b4 | 2456 | WARN_ON(ctx->engine[ring->id].state); |
ede7d42b | 2457 | |
8c857917 OM |
2458 | context_size = round_up(get_lr_context_size(ring), 4096); |
2459 | ||
d1675198 AD |
2460 | /* One extra page as the sharing data between driver and GuC */ |
2461 | context_size += PAGE_SIZE * LRC_PPHWSP_PN; | |
2462 | ||
149c86e7 | 2463 | ctx_obj = i915_gem_alloc_object(dev, context_size); |
3126a660 DC |
2464 | if (!ctx_obj) { |
2465 | DRM_DEBUG_DRIVER("Alloc LRC backing obj failed.\n"); | |
2466 | return -ENOMEM; | |
8c857917 OM |
2467 | } |
2468 | ||
01101fa7 CW |
2469 | ringbuf = intel_engine_create_ringbuffer(ring, 4 * PAGE_SIZE); |
2470 | if (IS_ERR(ringbuf)) { | |
2471 | ret = PTR_ERR(ringbuf); | |
e84fe803 | 2472 | goto error_deref_obj; |
8670d6f9 OM |
2473 | } |
2474 | ||
2475 | ret = populate_lr_context(ctx, ctx_obj, ring, ringbuf); | |
2476 | if (ret) { | |
2477 | DRM_DEBUG_DRIVER("Failed to populate LRC: %d\n", ret); | |
e84fe803 | 2478 | goto error_ringbuf; |
84c2377f OM |
2479 | } |
2480 | ||
2481 | ctx->engine[ring->id].ringbuf = ringbuf; | |
8c857917 | 2482 | ctx->engine[ring->id].state = ctx_obj; |
ede7d42b | 2483 | |
e84fe803 NH |
2484 | if (ctx != ring->default_context && ring->init_context) { |
2485 | struct drm_i915_gem_request *req; | |
76c39168 | 2486 | |
e84fe803 NH |
2487 | ret = i915_gem_request_alloc(ring, |
2488 | ctx, &req); | |
2489 | if (ret) { | |
2490 | DRM_ERROR("ring create req: %d\n", | |
2491 | ret); | |
2492 | i915_gem_request_cancel(req); | |
2493 | goto error_ringbuf; | |
771b9a53 MT |
2494 | } |
2495 | ||
e84fe803 NH |
2496 | ret = ring->init_context(req); |
2497 | if (ret) { | |
2498 | DRM_ERROR("ring init context: %d\n", | |
2499 | ret); | |
2500 | i915_gem_request_cancel(req); | |
2501 | goto error_ringbuf; | |
2502 | } | |
2503 | i915_add_request_no_flush(req); | |
564ddb2f | 2504 | } |
ede7d42b | 2505 | return 0; |
8670d6f9 | 2506 | |
01101fa7 CW |
2507 | error_ringbuf: |
2508 | intel_ringbuffer_free(ringbuf); | |
e84fe803 | 2509 | error_deref_obj: |
8670d6f9 | 2510 | drm_gem_object_unreference(&ctx_obj->base); |
e84fe803 NH |
2511 | ctx->engine[ring->id].ringbuf = NULL; |
2512 | ctx->engine[ring->id].state = NULL; | |
8670d6f9 | 2513 | return ret; |
ede7d42b | 2514 | } |
3e5b6f05 TD |
2515 | |
2516 | void intel_lr_context_reset(struct drm_device *dev, | |
2517 | struct intel_context *ctx) | |
2518 | { | |
2519 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2520 | struct intel_engine_cs *ring; | |
2521 | int i; | |
2522 | ||
2523 | for_each_ring(ring, dev_priv, i) { | |
2524 | struct drm_i915_gem_object *ctx_obj = | |
2525 | ctx->engine[ring->id].state; | |
2526 | struct intel_ringbuffer *ringbuf = | |
2527 | ctx->engine[ring->id].ringbuf; | |
2528 | uint32_t *reg_state; | |
2529 | struct page *page; | |
2530 | ||
2531 | if (!ctx_obj) | |
2532 | continue; | |
2533 | ||
2534 | if (i915_gem_object_get_pages(ctx_obj)) { | |
2535 | WARN(1, "Failed get_pages for context obj\n"); | |
2536 | continue; | |
2537 | } | |
d1675198 | 2538 | page = i915_gem_object_get_page(ctx_obj, LRC_STATE_PN); |
3e5b6f05 TD |
2539 | reg_state = kmap_atomic(page); |
2540 | ||
2541 | reg_state[CTX_RING_HEAD+1] = 0; | |
2542 | reg_state[CTX_RING_TAIL+1] = 0; | |
2543 | ||
2544 | kunmap_atomic(reg_state); | |
2545 | ||
2546 | ringbuf->head = 0; | |
2547 | ringbuf->tail = 0; | |
2548 | } | |
2549 | } |