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CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7 34#include <drm/drmP.h>
c6f95f27 35#include <drm/drm_atomic_helper.h>
760285e7
DH
36#include <drm/drm_crtc.h>
37#include <drm/drm_edid.h>
79e53945 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
79e53945 40#include "i915_drv.h"
e99da35f 41#include <linux/acpi.h>
79e53945 42
3fbe18d6 43/* Private structure for the integrated LVDS support */
c7362c4d
JN
44struct intel_lvds_connector {
45 struct intel_connector base;
788319d4 46
db1740a0 47 struct notifier_block lid_notifier;
c7362c4d
JN
48};
49
29b99b48 50struct intel_lvds_encoder {
ea5b213a 51 struct intel_encoder base;
788319d4 52
13c7d870 53 bool is_dual_link;
7dec0606 54 u32 reg;
1f835a77 55 u32 a3_power;
788319d4 56
62165e0d 57 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
58};
59
29b99b48 60static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 61{
29b99b48 62 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
63}
64
c7362c4d 65static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 66{
c7362c4d 67 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
68}
69
b1dc332c
DV
70static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
71 enum pipe *pipe)
72{
73 struct drm_device *dev = encoder->base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 75 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
34a6c70f 76 enum intel_display_power_domain power_domain;
7dec0606 77 u32 tmp;
b1dc332c 78
34a6c70f 79 power_domain = intel_display_port_power_domain(encoder);
f458ebbc 80 if (!intel_display_power_is_enabled(dev_priv, power_domain))
34a6c70f
PZ
81 return false;
82
7dec0606 83 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
84
85 if (!(tmp & LVDS_PORT_EN))
86 return false;
87
88 if (HAS_PCH_CPT(dev))
89 *pipe = PORT_TO_PIPE_CPT(tmp);
90 else
91 *pipe = PORT_TO_PIPE(tmp);
92
93 return true;
94}
95
045ac3b5 96static void intel_lvds_get_config(struct intel_encoder *encoder,
5cec258b 97 struct intel_crtc_state *pipe_config)
045ac3b5
JB
98{
99 struct drm_device *dev = encoder->base.dev;
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 u32 lvds_reg, tmp, flags = 0;
18442d08 102 int dotclock;
045ac3b5
JB
103
104 if (HAS_PCH_SPLIT(dev))
105 lvds_reg = PCH_LVDS;
106 else
107 lvds_reg = LVDS;
108
109 tmp = I915_READ(lvds_reg);
110 if (tmp & LVDS_HSYNC_POLARITY)
111 flags |= DRM_MODE_FLAG_NHSYNC;
112 else
113 flags |= DRM_MODE_FLAG_PHSYNC;
114 if (tmp & LVDS_VSYNC_POLARITY)
115 flags |= DRM_MODE_FLAG_NVSYNC;
116 else
117 flags |= DRM_MODE_FLAG_PVSYNC;
118
2d112de7 119 pipe_config->base.adjusted_mode.flags |= flags;
06922821 120
6b89cdde
DV
121 /* gen2/3 store dither state in pfit control, needs to match */
122 if (INTEL_INFO(dev)->gen < 4) {
123 tmp = I915_READ(PFIT_CONTROL);
124
125 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
126 }
127
18442d08
VS
128 dotclock = pipe_config->port_clock;
129
130 if (HAS_PCH_SPLIT(dev_priv->dev))
131 ironlake_check_encoder_dotclock(pipe_config, dotclock);
132
2d112de7 133 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB
134}
135
f6736a1a 136static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
137{
138 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
139 struct drm_device *dev = encoder->base.dev;
140 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 141 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4c6df4b4 142 const struct drm_display_mode *adjusted_mode =
6e3c9717 143 &crtc->config->base.adjusted_mode;
55607e8a 144 int pipe = crtc->pipe;
fc683091
DV
145 u32 temp;
146
55607e8a
DV
147 if (HAS_PCH_SPLIT(dev)) {
148 assert_fdi_rx_pll_disabled(dev_priv, pipe);
149 assert_shared_dpll_disabled(dev_priv,
150 intel_crtc_to_shared_dpll(crtc));
151 } else {
152 assert_pll_disabled(dev_priv, pipe);
153 }
154
fc683091
DV
155 temp = I915_READ(lvds_encoder->reg);
156 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
157
158 if (HAS_PCH_CPT(dev)) {
159 temp &= ~PORT_TRANS_SEL_MASK;
160 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 161 } else {
62810e5a
DV
162 if (pipe == 1) {
163 temp |= LVDS_PIPEB_SELECT;
164 } else {
165 temp &= ~LVDS_PIPEB_SELECT;
166 }
fc683091 167 }
62810e5a 168
fc683091 169 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 170 temp &= ~LVDS_BORDER_ENABLE;
6e3c9717 171 temp |= crtc->config->gmch_pfit.lvds_border_bits;
fc683091
DV
172 /* Set the B0-B3 data pairs corresponding to whether we're going to
173 * set the DPLLs for dual-channel mode or not.
174 */
175 if (lvds_encoder->is_dual_link)
176 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
177 else
178 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
179
180 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
181 * appropriately here, but we need to look more thoroughly into how
1f835a77
PZ
182 * panels behave in the two modes. For now, let's just maintain the
183 * value we got from the BIOS.
fc683091 184 */
1f835a77
PZ
185 temp &= ~LVDS_A3_POWER_MASK;
186 temp |= lvds_encoder->a3_power;
62810e5a
DV
187
188 /* Set the dithering flag on LVDS as needed, note that there is no
189 * special lvds dither control bit on pch-split platforms, dithering is
190 * only controlled through the PIPECONF reg. */
191 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
192 /* Bspec wording suggests that LVDS port dithering only exists
193 * for 18bpp panels. */
6e3c9717 194 if (crtc->config->dither && crtc->config->pipe_bpp == 18)
fc683091
DV
195 temp |= LVDS_ENABLE_DITHER;
196 else
197 temp &= ~LVDS_ENABLE_DITHER;
198 }
199 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 200 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 201 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 202 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
203 temp |= LVDS_VSYNC_POLARITY;
204
205 I915_WRITE(lvds_encoder->reg, temp);
206}
207
79e53945
JB
208/**
209 * Sets the power state for the panel.
210 */
c22834ec 211static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 212{
c22834ec 213 struct drm_device *dev = encoder->base.dev;
29b99b48 214 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
215 struct intel_connector *intel_connector =
216 &lvds_encoder->attached_connector->base;
79e53945 217 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 218 u32 ctl_reg, stat_reg;
541998a1 219
c619eed4 220 if (HAS_PCH_SPLIT(dev)) {
541998a1 221 ctl_reg = PCH_PP_CONTROL;
de842eff 222 stat_reg = PCH_PP_STATUS;
541998a1
ZW
223 } else {
224 ctl_reg = PP_CONTROL;
de842eff 225 stat_reg = PP_STATUS;
541998a1 226 }
79e53945 227
7dec0606 228 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 229
2a1292fd 230 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 231 POSTING_READ(lvds_encoder->reg);
de842eff
KP
232 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
233 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 234
752aa88a 235 intel_panel_enable_backlight(intel_connector);
2a1292fd
CW
236}
237
c22834ec 238static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 239{
c22834ec 240 struct drm_device *dev = encoder->base.dev;
29b99b48 241 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 242 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 243 u32 ctl_reg, stat_reg;
2a1292fd
CW
244
245 if (HAS_PCH_SPLIT(dev)) {
246 ctl_reg = PCH_PP_CONTROL;
de842eff 247 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
248 } else {
249 ctl_reg = PP_CONTROL;
de842eff 250 stat_reg = PP_STATUS;
2a1292fd
CW
251 }
252
2a1292fd 253 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
254 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
255 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 256
7dec0606
DV
257 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
258 POSTING_READ(lvds_encoder->reg);
79e53945
JB
259}
260
d26a5b6e
VS
261static void gmch_disable_lvds(struct intel_encoder *encoder)
262{
263 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
264 struct intel_connector *intel_connector =
265 &lvds_encoder->attached_connector->base;
266
267 intel_panel_disable_backlight(intel_connector);
268
269 intel_disable_lvds(encoder);
270}
271
272static void pch_disable_lvds(struct intel_encoder *encoder)
273{
274 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
275 struct intel_connector *intel_connector =
276 &lvds_encoder->attached_connector->base;
277
278 intel_panel_disable_backlight(intel_connector);
279}
280
281static void pch_post_disable_lvds(struct intel_encoder *encoder)
282{
283 intel_disable_lvds(encoder);
284}
285
c19de8eb
DL
286static enum drm_mode_status
287intel_lvds_mode_valid(struct drm_connector *connector,
288 struct drm_display_mode *mode)
79e53945 289{
dd06f90e
JN
290 struct intel_connector *intel_connector = to_intel_connector(connector);
291 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 292
788319d4
CW
293 if (mode->hdisplay > fixed_mode->hdisplay)
294 return MODE_PANEL;
295 if (mode->vdisplay > fixed_mode->vdisplay)
296 return MODE_PANEL;
79e53945
JB
297
298 return MODE_OK;
299}
300
7ae89233 301static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
5cec258b 302 struct intel_crtc_state *pipe_config)
79e53945 303{
7ae89233 304 struct drm_device *dev = intel_encoder->base.dev;
7ae89233
DV
305 struct intel_lvds_encoder *lvds_encoder =
306 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
307 struct intel_connector *intel_connector =
308 &lvds_encoder->attached_connector->base;
2d112de7 309 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d21bd67b 310 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
4e53c2e0 311 unsigned int lvds_bpp;
79e53945
JB
312
313 /* Should never happen!! */
a6c45cf0 314 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 315 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
316 return false;
317 }
318
1f835a77 319 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
4e53c2e0
DV
320 lvds_bpp = 8*3;
321 else
322 lvds_bpp = 6*3;
323
e29c22c0 324 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
325 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
326 pipe_config->pipe_bpp, lvds_bpp);
327 pipe_config->pipe_bpp = lvds_bpp;
328 }
d8b32247 329
79e53945 330 /*
71677043 331 * We have timings from the BIOS for the panel, put them in
79e53945
JB
332 * to the adjusted mode. The CRTC will be set up for this mode,
333 * with the panel scaling set up to source from the H/VDisplay
334 * of the original mode.
335 */
4d891523 336 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 337 adjusted_mode);
1d8e1c75
CW
338
339 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
340 pipe_config->has_pch_encoder = true;
341
b074cec8
JB
342 intel_pch_panel_fitting(intel_crtc, pipe_config,
343 intel_connector->panel.fitting_mode);
2dd24552
JB
344 } else {
345 intel_gmch_panel_fitting(intel_crtc, pipe_config,
346 intel_connector->panel.fitting_mode);
79e53945 347
21d8a475 348 }
f9bef081 349
79e53945
JB
350 /*
351 * XXX: It would be nice to support lower refresh rates on the
352 * panels to reduce power consumption, and perhaps match the
353 * user's requested refresh rate.
354 */
355
356 return true;
357}
358
79e53945
JB
359/**
360 * Detect the LVDS connection.
361 *
b42d4c5c
JB
362 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
363 * connected and closed means disconnected. We also send hotplug events as
364 * needed, using lid status notification from the input layer.
79e53945 365 */
7b334fcb 366static enum drm_connector_status
930a9e28 367intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 368{
7b9c5abe 369 struct drm_device *dev = connector->dev;
6ee3b5a1 370 enum drm_connector_status status;
b42d4c5c 371
164c8598 372 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 373 connector->base.id, connector->name);
164c8598 374
fe16d949
CW
375 status = intel_panel_detect(dev);
376 if (status != connector_status_unknown)
377 return status;
01fe9dbd 378
6ee3b5a1 379 return connector_status_connected;
79e53945
JB
380}
381
382/**
383 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
384 */
385static int intel_lvds_get_modes(struct drm_connector *connector)
386{
62165e0d 387 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 388 struct drm_device *dev = connector->dev;
788319d4 389 struct drm_display_mode *mode;
79e53945 390
9cd300e0 391 /* use cached edid if we have one */
2aa4f099 392 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 393 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 394
dd06f90e 395 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 396 if (mode == NULL)
788319d4 397 return 0;
79e53945 398
788319d4
CW
399 drm_mode_probed_add(connector, mode);
400 return 1;
79e53945
JB
401}
402
0544edfd
TB
403static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
404{
bc0daf48 405 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
406 return 1;
407}
408
409/* The GPU hangs up on these systems if modeset is performed on LID open */
410static const struct dmi_system_id intel_no_modeset_on_lid[] = {
411 {
412 .callback = intel_no_modeset_on_lid_dmi_callback,
413 .ident = "Toshiba Tecra A11",
414 .matches = {
415 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
416 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
417 },
418 },
419
420 { } /* terminating entry */
421};
422
c9354c85 423/*
b8efb17b
ZR
424 * Lid events. Note the use of 'modeset':
425 * - we set it to MODESET_ON_LID_OPEN on lid close,
426 * and set it to MODESET_DONE on open
c9354c85 427 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
428 * duplicate events where it was already properly set)
429 * - the suspend/resume paths will set it to
430 * MODESET_SUSPENDED and ignore the lid open event,
431 * because they restore the mode ("lid open").
c9354c85 432 */
c1c7af60
JB
433static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
434 void *unused)
435{
db1740a0
JN
436 struct intel_lvds_connector *lvds_connector =
437 container_of(nb, struct intel_lvds_connector, lid_notifier);
438 struct drm_connector *connector = &lvds_connector->base.base;
439 struct drm_device *dev = connector->dev;
440 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 441
2fb4e61d
AW
442 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
443 return NOTIFY_OK;
444
b8efb17b
ZR
445 mutex_lock(&dev_priv->modeset_restore_lock);
446 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
447 goto exit;
a2565377
ZY
448 /*
449 * check and update the status of LVDS connector after receiving
450 * the LID nofication event.
451 */
db1740a0 452 connector->status = connector->funcs->detect(connector, false);
7b334fcb 453
0544edfd
TB
454 /* Don't force modeset on machines where it causes a GPU lockup */
455 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 456 goto exit;
c9354c85 457 if (!acpi_lid_open()) {
b8efb17b
ZR
458 /* do modeset on next lid open event */
459 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
460 goto exit;
06891e27 461 }
c1c7af60 462
b8efb17b
ZR
463 if (dev_priv->modeset_restore == MODESET_DONE)
464 goto exit;
c9354c85 465
5be19d91
DV
466 /*
467 * Some old platform's BIOS love to wreak havoc while the lid is closed.
468 * We try to detect this here and undo any damage. The split for PCH
469 * platforms is rather conservative and a bit arbitrary expect that on
470 * those platforms VGA disabling requires actual legacy VGA I/O access,
471 * and as part of the cleanup in the hw state restore we also redisable
472 * the vga plane.
473 */
474 if (!HAS_PCH_SPLIT(dev)) {
475 drm_modeset_lock_all(dev);
043e9bda 476 intel_display_resume(dev);
5be19d91
DV
477 drm_modeset_unlock_all(dev);
478 }
06324194 479
b8efb17b
ZR
480 dev_priv->modeset_restore = MODESET_DONE;
481
482exit:
483 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
484 return NOTIFY_OK;
485}
486
79e53945
JB
487/**
488 * intel_lvds_destroy - unregister and free LVDS structures
489 * @connector: connector to free
490 *
491 * Unregister the DDC bus for this connector then free the driver private
492 * structure.
493 */
494static void intel_lvds_destroy(struct drm_connector *connector)
495{
db1740a0
JN
496 struct intel_lvds_connector *lvds_connector =
497 to_lvds_connector(connector);
79e53945 498
db1740a0
JN
499 if (lvds_connector->lid_notifier.notifier_call)
500 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 501
9cd300e0
JN
502 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
503 kfree(lvds_connector->base.edid);
504
1d508706 505 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 506
79e53945
JB
507 drm_connector_cleanup(connector);
508 kfree(connector);
509}
510
335041ed
JB
511static int intel_lvds_set_property(struct drm_connector *connector,
512 struct drm_property *property,
513 uint64_t value)
514{
4d891523 515 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 516 struct drm_device *dev = connector->dev;
3fbe18d6 517
788319d4 518 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 519 struct drm_crtc *crtc;
bb8a3560 520
53bd8389
JB
521 if (value == DRM_MODE_SCALE_NONE) {
522 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 523 return -EINVAL;
3fbe18d6 524 }
788319d4 525
4d891523 526 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
527 /* the LVDS scaling property is not changed */
528 return 0;
529 }
4d891523 530 intel_connector->panel.fitting_mode = value;
62165e0d
JN
531
532 crtc = intel_attached_encoder(connector)->base.crtc;
83d65738 533 if (crtc && crtc->state->enable) {
3fbe18d6
ZY
534 /*
535 * If the CRTC is enabled, the display will be changed
536 * according to the new panel fitting mode.
537 */
c0c36b94 538 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
539 }
540 }
541
335041ed
JB
542 return 0;
543}
544
79e53945
JB
545static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
546 .get_modes = intel_lvds_get_modes,
547 .mode_valid = intel_lvds_mode_valid,
df0e9248 548 .best_encoder = intel_best_encoder,
79e53945
JB
549};
550
551static const struct drm_connector_funcs intel_lvds_connector_funcs = {
4d688a2a 552 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB
553 .detect = intel_lvds_detect,
554 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 555 .set_property = intel_lvds_set_property,
2545e4a6 556 .atomic_get_property = intel_connector_atomic_get_property,
79e53945 557 .destroy = intel_lvds_destroy,
c6f95f27 558 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 559 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945
JB
560};
561
79e53945 562static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 563 .destroy = intel_encoder_destroy,
79e53945
JB
564};
565
bbe1c274 566static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
425d244c 567{
bc0daf48 568 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
569 return 1;
570}
79e53945 571
425d244c 572/* These systems claim to have LVDS, but really don't */
93c05f22 573static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
574 {
575 .callback = intel_no_lvds_dmi_callback,
576 .ident = "Apple Mac Mini (Core series)",
577 .matches = {
98acd46f 578 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
579 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
580 },
581 },
582 {
583 .callback = intel_no_lvds_dmi_callback,
584 .ident = "Apple Mac Mini (Core 2 series)",
585 .matches = {
98acd46f 586 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
587 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
588 },
589 },
590 {
591 .callback = intel_no_lvds_dmi_callback,
592 .ident = "MSI IM-945GSE-A",
593 .matches = {
594 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
595 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
596 },
597 },
598 {
599 .callback = intel_no_lvds_dmi_callback,
600 .ident = "Dell Studio Hybrid",
601 .matches = {
602 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
603 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
604 },
605 },
70aa96ca
JW
606 {
607 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
608 .ident = "Dell OptiPlex FX170",
609 .matches = {
610 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
611 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
612 },
613 },
614 {
615 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
616 .ident = "AOpen Mini PC",
617 .matches = {
618 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
619 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
620 },
621 },
ed8c754b
TV
622 {
623 .callback = intel_no_lvds_dmi_callback,
624 .ident = "AOpen Mini PC MP915",
625 .matches = {
626 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
627 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
628 },
629 },
22ab70d3
KP
630 {
631 .callback = intel_no_lvds_dmi_callback,
632 .ident = "AOpen i915GMm-HFS",
633 .matches = {
634 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
635 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
636 },
637 },
e57b6886
DV
638 {
639 .callback = intel_no_lvds_dmi_callback,
640 .ident = "AOpen i45GMx-I",
641 .matches = {
642 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
643 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
644 },
645 },
fa0864b2
MC
646 {
647 .callback = intel_no_lvds_dmi_callback,
648 .ident = "Aopen i945GTt-VFA",
649 .matches = {
650 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
651 },
652 },
9875557e
SB
653 {
654 .callback = intel_no_lvds_dmi_callback,
655 .ident = "Clientron U800",
656 .matches = {
657 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
658 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
659 },
660 },
6a574b5b 661 {
44306ab3
JS
662 .callback = intel_no_lvds_dmi_callback,
663 .ident = "Clientron E830",
664 .matches = {
665 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
666 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
667 },
668 },
669 {
6a574b5b
HG
670 .callback = intel_no_lvds_dmi_callback,
671 .ident = "Asus EeeBox PC EB1007",
672 .matches = {
673 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
674 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
675 },
676 },
0999bbe0
AJ
677 {
678 .callback = intel_no_lvds_dmi_callback,
679 .ident = "Asus AT5NM10T-I",
680 .matches = {
681 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
682 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
683 },
684 },
33471119
JBG
685 {
686 .callback = intel_no_lvds_dmi_callback,
45a211d7 687 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
688 .matches = {
689 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 690 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
691 },
692 },
f5b8a7ed
MG
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "Hewlett-Packard t5745",
696 .matches = {
697 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 698 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
699 },
700 },
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Hewlett-Packard st5747",
704 .matches = {
705 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 706 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
707 },
708 },
97effadb
AA
709 {
710 .callback = intel_no_lvds_dmi_callback,
711 .ident = "MSI Wind Box DC500",
712 .matches = {
713 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
714 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
715 },
716 },
a51d4ed0
CW
717 {
718 .callback = intel_no_lvds_dmi_callback,
719 .ident = "Gigabyte GA-D525TUD",
720 .matches = {
721 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
722 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
723 },
724 },
c31407a3
CW
725 {
726 .callback = intel_no_lvds_dmi_callback,
727 .ident = "Supermicro X7SPA-H",
728 .matches = {
729 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
730 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
731 },
732 },
9e9dd0e8
CL
733 {
734 .callback = intel_no_lvds_dmi_callback,
735 .ident = "Fujitsu Esprimo Q900",
736 .matches = {
737 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
738 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
739 },
740 },
645378d8
RP
741 {
742 .callback = intel_no_lvds_dmi_callback,
743 .ident = "Intel D410PT",
744 .matches = {
745 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
746 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
747 },
748 },
749 {
750 .callback = intel_no_lvds_dmi_callback,
751 .ident = "Intel D425KT",
752 .matches = {
753 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
754 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
755 },
756 },
e5614f0c
CW
757 {
758 .callback = intel_no_lvds_dmi_callback,
759 .ident = "Intel D510MO",
760 .matches = {
761 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
762 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
763 },
764 },
dcf6d294
JN
765 {
766 .callback = intel_no_lvds_dmi_callback,
767 .ident = "Intel D525MW",
768 .matches = {
769 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
770 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
771 },
772 },
425d244c
JW
773
774 { } /* terminating entry */
775};
79e53945 776
7cf4f69d
ZY
777/*
778 * Enumerate the child dev array parsed from VBT to check whether
779 * the LVDS is present.
780 * If it is present, return 1.
781 * If it is not present, return false.
782 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 783 */
270eea0f
CW
784static bool lvds_is_present_in_vbt(struct drm_device *dev,
785 u8 *i2c_pin)
7cf4f69d
ZY
786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 788 int i;
7cf4f69d 789
41aa3448 790 if (!dev_priv->vbt.child_dev_num)
425904dd 791 return true;
7cf4f69d 792
41aa3448 793 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
768f69c9
PZ
794 union child_device_config *uchild = dev_priv->vbt.child_dev + i;
795 struct old_child_dev_config *child = &uchild->old;
425904dd
CW
796
797 /* If the device type is not LFP, continue.
798 * We have to check both the new identifiers as well as the
799 * old for compatibility with some BIOSes.
7cf4f69d 800 */
425904dd
CW
801 if (child->device_type != DEVICE_TYPE_INT_LFP &&
802 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
803 continue;
804
88ac7939 805 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
3bd7d909 806 *i2c_pin = child->i2c_pin;
270eea0f 807
425904dd
CW
808 /* However, we cannot trust the BIOS writers to populate
809 * the VBT correctly. Since LVDS requires additional
810 * information from AIM blocks, a non-zero addin offset is
811 * a good indicator that the LVDS is actually present.
7cf4f69d 812 */
425904dd
CW
813 if (child->addin_offset)
814 return true;
815
816 /* But even then some BIOS writers perform some black magic
817 * and instantiate the device without reference to any
818 * additional data. Trust that if the VBT was written into
819 * the OpRegion then they have validated the LVDS's existence.
820 */
821 if (dev_priv->opregion.vbt)
822 return true;
7cf4f69d 823 }
425904dd
CW
824
825 return false;
7cf4f69d
ZY
826}
827
1974cad0
DV
828static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
829{
830 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
831 return 1;
832}
833
834static const struct dmi_system_id intel_dual_link_lvds[] = {
835 {
836 .callback = intel_dual_link_lvds_callback,
3916e3fd
LW
837 .ident = "Apple MacBook Pro 15\" (2010)",
838 .matches = {
839 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
840 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
841 },
842 },
843 {
844 .callback = intel_dual_link_lvds_callback,
845 .ident = "Apple MacBook Pro 15\" (2011)",
1974cad0
DV
846 .matches = {
847 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
848 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
849 },
850 },
3916e3fd
LW
851 {
852 .callback = intel_dual_link_lvds_callback,
853 .ident = "Apple MacBook Pro 15\" (2012)",
854 .matches = {
855 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
856 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
857 },
858 },
1974cad0
DV
859 { } /* terminating entry */
860};
861
862bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
863{
864 struct intel_encoder *encoder;
865 struct intel_lvds_encoder *lvds_encoder;
866
b2784e15 867 for_each_intel_encoder(dev, encoder) {
13c7d870
DV
868 if (encoder->type == INTEL_OUTPUT_LVDS) {
869 lvds_encoder = to_lvds_encoder(&encoder->base);
870
871 return lvds_encoder->is_dual_link;
872 }
873 }
874
875 return false;
876}
877
7dec0606 878static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 879{
7dec0606 880 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
881 unsigned int val;
882 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
883
884 /* use the module option value if specified */
d330a953
JN
885 if (i915.lvds_channel_mode > 0)
886 return i915.lvds_channel_mode == 2;
1974cad0 887
6f317cfe
LW
888 /* single channel LVDS is limited to 112 MHz */
889 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
890 > 112999)
891 return true;
892
1974cad0
DV
893 if (dmi_check_system(intel_dual_link_lvds))
894 return true;
895
13c7d870
DV
896 /* BIOS should set the proper LVDS register value at boot, but
897 * in reality, it doesn't set the value when the lid is closed;
898 * we need to check "the value to be set" in VBT when LVDS
899 * register is uninitialized.
900 */
7dec0606 901 val = I915_READ(lvds_encoder->reg);
13c7d870 902 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 903 val = dev_priv->vbt.bios_lvds_val;
13c7d870 904
1974cad0
DV
905 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
906}
907
f3cfcba6
CW
908static bool intel_lvds_supported(struct drm_device *dev)
909{
910 /* With the introduction of the PCH we gained a dedicated
911 * LVDS presence pin, use it. */
311e359c 912 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
913 return true;
914
915 /* Otherwise LVDS was only attached to mobile products,
916 * except for the inglorious 830gm */
311e359c
PZ
917 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
918 return true;
919
920 return false;
f3cfcba6
CW
921}
922
79e53945
JB
923/**
924 * intel_lvds_init - setup LVDS connectors on this device
925 * @dev: drm device
926 *
927 * Create the connector, register the LVDS DDC bus, and try to figure out what
928 * modes we can display on the LVDS panel (if present).
929 */
c9093354 930void intel_lvds_init(struct drm_device *dev)
79e53945
JB
931{
932 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 933 struct intel_lvds_encoder *lvds_encoder;
21d40d37 934 struct intel_encoder *intel_encoder;
c7362c4d 935 struct intel_lvds_connector *lvds_connector;
bb8a3560 936 struct intel_connector *intel_connector;
79e53945
JB
937 struct drm_connector *connector;
938 struct drm_encoder *encoder;
939 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 940 struct drm_display_mode *fixed_mode = NULL;
4b6ed685 941 struct drm_display_mode *downclock_mode = NULL;
9cd300e0 942 struct edid *edid;
79e53945
JB
943 struct drm_crtc *crtc;
944 u32 lvds;
270eea0f
CW
945 int pipe;
946 u8 pin;
79e53945 947
b0616c53
DV
948 /*
949 * Unlock registers and just leave them unlocked. Do this before
950 * checking quirk lists to avoid bogus WARNINGs.
951 */
952 if (HAS_PCH_SPLIT(dev)) {
953 I915_WRITE(PCH_PP_CONTROL,
954 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
955 } else {
956 I915_WRITE(PP_CONTROL,
957 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
958 }
f3cfcba6 959 if (!intel_lvds_supported(dev))
c9093354 960 return;
f3cfcba6 961
425d244c
JW
962 /* Skip init on machines we know falsely report LVDS */
963 if (dmi_check_system(intel_no_lvds))
c9093354 964 return;
565dcd46 965
c619eed4 966 if (HAS_PCH_SPLIT(dev)) {
541998a1 967 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 968 return;
41aa3448 969 if (dev_priv->vbt.edp_support) {
28c97730 970 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 971 return;
32f9d658 972 }
541998a1
ZW
973 }
974
eebaed64
CW
975 pin = GMBUS_PIN_PANEL;
976 if (!lvds_is_present_in_vbt(dev, &pin)) {
977 u32 reg = HAS_PCH_SPLIT(dev) ? PCH_LVDS : LVDS;
978 if ((I915_READ(reg) & LVDS_PORT_EN) == 0) {
979 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
980 return;
981 }
982 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
983 }
984
b14c5679 985 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
29b99b48 986 if (!lvds_encoder)
c9093354 987 return;
79e53945 988
b14c5679 989 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
c7362c4d 990 if (!lvds_connector) {
29b99b48 991 kfree(lvds_encoder);
c9093354 992 return;
bb8a3560
ZW
993 }
994
9bdbd0b9
ACO
995 if (intel_connector_init(&lvds_connector->base) < 0) {
996 kfree(lvds_connector);
997 kfree(lvds_encoder);
998 return;
999 }
1000
62165e0d
JN
1001 lvds_encoder->attached_connector = lvds_connector;
1002
29b99b48 1003 intel_encoder = &lvds_encoder->base;
4ef69c7a 1004 encoder = &intel_encoder->base;
c7362c4d 1005 intel_connector = &lvds_connector->base;
ea5b213a 1006 connector = &intel_connector->base;
bb8a3560 1007 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
1008 DRM_MODE_CONNECTOR_LVDS);
1009
4ef69c7a 1010 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
1011 DRM_MODE_ENCODER_LVDS);
1012
c22834ec 1013 intel_encoder->enable = intel_enable_lvds;
f6736a1a 1014 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 1015 intel_encoder->compute_config = intel_lvds_compute_config;
d26a5b6e
VS
1016 if (HAS_PCH_SPLIT(dev_priv)) {
1017 intel_encoder->disable = pch_disable_lvds;
1018 intel_encoder->post_disable = pch_post_disable_lvds;
1019 } else {
1020 intel_encoder->disable = gmch_disable_lvds;
1021 }
b1dc332c 1022 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 1023 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 1024 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 1025 intel_connector->unregister = intel_connector_unregister;
c22834ec 1026
df0e9248 1027 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1028 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1029
bc079e8b 1030 intel_encoder->cloneable = 0;
27f8227b
JB
1031 if (HAS_PCH_SPLIT(dev))
1032 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1033 else if (IS_GEN4(dev))
1034 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1035 else
1036 intel_encoder->crtc_mask = (1 << 1);
1037
79e53945
JB
1038 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1039 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1040 connector->interlace_allowed = false;
1041 connector->doublescan_allowed = false;
1042
7dec0606
DV
1043 if (HAS_PCH_SPLIT(dev)) {
1044 lvds_encoder->reg = PCH_LVDS;
1045 } else {
1046 lvds_encoder->reg = LVDS;
1047 }
1048
3fbe18d6
ZY
1049 /* create the scaling mode property */
1050 drm_mode_create_scaling_mode_property(dev);
662595df 1051 drm_object_attach_property(&connector->base,
3fbe18d6 1052 dev->mode_config.scaling_mode_property,
dd1ea37d 1053 DRM_MODE_SCALE_ASPECT);
4d891523 1054 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1055 /*
1056 * LVDS discovery:
1057 * 1) check for EDID on DDC
1058 * 2) check for VBT data
1059 * 3) check to see if LVDS is already on
1060 * if none of the above, no panel
1061 * 4) make sure lid is open
1062 * if closed, act like it's not there for now
1063 */
1064
79e53945
JB
1065 /*
1066 * Attempt to get the fixed panel mode from DDC. Assume that the
1067 * preferred mode is the right one.
1068 */
4da98541 1069 mutex_lock(&dev->mode_config.mutex);
9cd300e0
JN
1070 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1071 if (edid) {
1072 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1073 drm_mode_connector_update_edid_property(connector,
9cd300e0 1074 edid);
3f8ff0e7 1075 } else {
9cd300e0
JN
1076 kfree(edid);
1077 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1078 }
9cd300e0
JN
1079 } else {
1080 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1081 }
9cd300e0
JN
1082 lvds_connector->base.edid = edid;
1083
1084 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1085 /* Didn't get an EDID, so
1086 * Set wide sync ranges so we get all modes
1087 * handed to valid_mode for checking
1088 */
1089 connector->display_info.min_vfreq = 0;
1090 connector->display_info.max_vfreq = 200;
1091 connector->display_info.min_hfreq = 0;
1092 connector->display_info.max_hfreq = 200;
1093 }
79e53945
JB
1094
1095 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1096 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1097 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1098 drm_mode_debug_printmodeline(scan);
1099
dd06f90e 1100 fixed_mode = drm_mode_duplicate(dev, scan);
c329a4ec 1101 if (fixed_mode)
6a9d51b7 1102 goto out;
79e53945 1103 }
79e53945
JB
1104 }
1105
1106 /* Failed to get EDID, what about VBT? */
41aa3448 1107 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1108 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1109 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1110
41aa3448 1111 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1112 if (fixed_mode) {
1113 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1114 goto out;
1115 }
79e53945
JB
1116 }
1117
1118 /*
1119 * If we didn't get EDID, try checking if the panel is already turned
1120 * on. If so, assume that whatever is currently programmed is the
1121 * correct mode.
1122 */
541998a1 1123
f2b115e6 1124 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1125 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1126 goto failed;
1127
79e53945
JB
1128 lvds = I915_READ(LVDS);
1129 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1130 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1131
1132 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1133 fixed_mode = intel_crtc_mode_get(dev, crtc);
1134 if (fixed_mode) {
6a9d51b7
CW
1135 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1136 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1137 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1138 goto out;
79e53945
JB
1139 }
1140 }
1141
1142 /* If we still don't have a mode after all that, give up. */
dd06f90e 1143 if (!fixed_mode)
79e53945
JB
1144 goto failed;
1145
79e53945 1146out:
4da98541
DV
1147 mutex_unlock(&dev->mode_config.mutex);
1148
6f317cfe
LW
1149 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1150
7dec0606 1151 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1152 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1153 lvds_encoder->is_dual_link ? "dual" : "single");
1154
1f835a77
PZ
1155 lvds_encoder->a3_power = I915_READ(lvds_encoder->reg) &
1156 LVDS_A3_POWER_MASK;
1157
db1740a0
JN
1158 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1159 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1160 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1161 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1162 }
34ea3d38 1163 drm_connector_register(connector);
aaa6fd2a 1164
6517d273 1165 intel_panel_setup_backlight(connector, INVALID_PIPE);
aaa6fd2a 1166
c9093354 1167 return;
79e53945
JB
1168
1169failed:
4da98541
DV
1170 mutex_unlock(&dev->mode_config.mutex);
1171
8a4c47f3 1172 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1173 drm_connector_cleanup(connector);
1991bdfa 1174 drm_encoder_cleanup(encoder);
29b99b48 1175 kfree(lvds_encoder);
c7362c4d 1176 kfree(lvds_connector);
c9093354 1177 return;
79e53945 1178}