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drm/i915: fix up readout of the lvds dither bit on gen2/3
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
045ac3b5
JB
89static void intel_lvds_get_config(struct intel_encoder *encoder,
90 struct intel_crtc_config *pipe_config)
91{
92 struct drm_device *dev = encoder->base.dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 u32 lvds_reg, tmp, flags = 0;
95
96 if (HAS_PCH_SPLIT(dev))
97 lvds_reg = PCH_LVDS;
98 else
99 lvds_reg = LVDS;
100
101 tmp = I915_READ(lvds_reg);
102 if (tmp & LVDS_HSYNC_POLARITY)
103 flags |= DRM_MODE_FLAG_NHSYNC;
104 else
105 flags |= DRM_MODE_FLAG_PHSYNC;
106 if (tmp & LVDS_VSYNC_POLARITY)
107 flags |= DRM_MODE_FLAG_NVSYNC;
108 else
109 flags |= DRM_MODE_FLAG_PVSYNC;
110
111 pipe_config->adjusted_mode.flags |= flags;
06922821
DV
112
113 /* gen2/3 store dither state in pfit control, needs to match */
114 if (INTEL_INFO(dev)->gen < 4) {
115 tmp = I915_READ(PFIT_CONTROL);
116
117 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
118 }
045ac3b5
JB
119}
120
fc683091
DV
121/* The LVDS pin pair needs to be on before the DPLLs are enabled.
122 * This is an exception to the general rule that mode_set doesn't turn
123 * things on.
124 */
125static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
126{
127 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
128 struct drm_device *dev = encoder->base.dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
131 struct drm_display_mode *fixed_mode =
132 lvds_encoder->attached_connector->base.panel.fixed_mode;
133 int pipe = intel_crtc->pipe;
134 u32 temp;
135
fc683091
DV
136 temp = I915_READ(lvds_encoder->reg);
137 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
138
139 if (HAS_PCH_CPT(dev)) {
140 temp &= ~PORT_TRANS_SEL_MASK;
141 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 142 } else {
62810e5a
DV
143 if (pipe == 1) {
144 temp |= LVDS_PIPEB_SELECT;
145 } else {
146 temp &= ~LVDS_PIPEB_SELECT;
147 }
fc683091 148 }
62810e5a 149
fc683091 150 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 151 temp &= ~LVDS_BORDER_ENABLE;
68fc8742 152 temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
153 /* Set the B0-B3 data pairs corresponding to whether we're going to
154 * set the DPLLs for dual-channel mode or not.
155 */
156 if (lvds_encoder->is_dual_link)
157 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
158 else
159 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
160
161 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
162 * appropriately here, but we need to look more thoroughly into how
163 * panels behave in the two modes.
164 */
62810e5a
DV
165
166 /* Set the dithering flag on LVDS as needed, note that there is no
167 * special lvds dither control bit on pch-split platforms, dithering is
168 * only controlled through the PIPECONF reg. */
169 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
170 /* Bspec wording suggests that LVDS port dithering only exists
171 * for 18bpp panels. */
172 if (intel_crtc->config.dither &&
173 intel_crtc->config.pipe_bpp == 18)
fc683091
DV
174 temp |= LVDS_ENABLE_DITHER;
175 else
176 temp &= ~LVDS_ENABLE_DITHER;
177 }
178 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
179 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
180 temp |= LVDS_HSYNC_POLARITY;
181 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
182 temp |= LVDS_VSYNC_POLARITY;
183
184 I915_WRITE(lvds_encoder->reg, temp);
185}
186
79e53945
JB
187/**
188 * Sets the power state for the panel.
189 */
c22834ec 190static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 191{
c22834ec 192 struct drm_device *dev = encoder->base.dev;
29b99b48 193 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 194 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 195 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 196 u32 ctl_reg, stat_reg;
541998a1 197
c619eed4 198 if (HAS_PCH_SPLIT(dev)) {
541998a1 199 ctl_reg = PCH_PP_CONTROL;
de842eff 200 stat_reg = PCH_PP_STATUS;
541998a1
ZW
201 } else {
202 ctl_reg = PP_CONTROL;
de842eff 203 stat_reg = PP_STATUS;
541998a1 204 }
79e53945 205
7dec0606 206 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 207
2a1292fd 208 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 209 POSTING_READ(lvds_encoder->reg);
de842eff
KP
210 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
211 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 212
24ded204 213 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
214}
215
c22834ec 216static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 217{
c22834ec 218 struct drm_device *dev = encoder->base.dev;
29b99b48 219 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 220 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 221 u32 ctl_reg, stat_reg;
2a1292fd
CW
222
223 if (HAS_PCH_SPLIT(dev)) {
224 ctl_reg = PCH_PP_CONTROL;
de842eff 225 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
226 } else {
227 ctl_reg = PP_CONTROL;
de842eff 228 stat_reg = PP_STATUS;
2a1292fd
CW
229 }
230
47356eb6 231 intel_panel_disable_backlight(dev);
2a1292fd
CW
232
233 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
234 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
235 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 236
7dec0606
DV
237 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
238 POSTING_READ(lvds_encoder->reg);
79e53945
JB
239}
240
79e53945
JB
241static int intel_lvds_mode_valid(struct drm_connector *connector,
242 struct drm_display_mode *mode)
243{
dd06f90e
JN
244 struct intel_connector *intel_connector = to_intel_connector(connector);
245 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 246
788319d4
CW
247 if (mode->hdisplay > fixed_mode->hdisplay)
248 return MODE_PANEL;
249 if (mode->vdisplay > fixed_mode->vdisplay)
250 return MODE_PANEL;
79e53945
JB
251
252 return MODE_OK;
253}
254
7ae89233
DV
255static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
256 struct intel_crtc_config *pipe_config)
79e53945 257{
7ae89233 258 struct drm_device *dev = intel_encoder->base.dev;
79e53945 259 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
260 struct intel_lvds_encoder *lvds_encoder =
261 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
262 struct intel_connector *intel_connector =
263 &lvds_encoder->attached_connector->base;
7ae89233 264 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 265 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 266 unsigned int lvds_bpp;
79e53945
JB
267
268 /* Should never happen!! */
a6c45cf0 269 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 270 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
271 return false;
272 }
273
4e53c2e0
DV
274 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
275 LVDS_A3_POWER_UP)
276 lvds_bpp = 8*3;
277 else
278 lvds_bpp = 6*3;
279
e29c22c0 280 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
281 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
282 pipe_config->pipe_bpp, lvds_bpp);
283 pipe_config->pipe_bpp = lvds_bpp;
284 }
d8b32247 285
79e53945 286 /*
71677043 287 * We have timings from the BIOS for the panel, put them in
79e53945
JB
288 * to the adjusted mode. The CRTC will be set up for this mode,
289 * with the panel scaling set up to source from the H/VDisplay
290 * of the original mode.
291 */
4d891523 292 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 293 adjusted_mode);
1d8e1c75
CW
294
295 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
296 pipe_config->has_pch_encoder = true;
297
b074cec8
JB
298 intel_pch_panel_fitting(intel_crtc, pipe_config,
299 intel_connector->panel.fitting_mode);
1d8e1c75 300 return true;
2dd24552
JB
301 } else {
302 intel_gmch_panel_fitting(intel_crtc, pipe_config,
303 intel_connector->panel.fitting_mode);
1d8e1c75 304 }
79e53945 305
f9bef081 306 drm_mode_set_crtcinfo(adjusted_mode, 0);
7ae89233 307 pipe_config->timings_set = true;
f9bef081 308
79e53945
JB
309 /*
310 * XXX: It would be nice to support lower refresh rates on the
311 * panels to reduce power consumption, and perhaps match the
312 * user's requested refresh rate.
313 */
314
315 return true;
316}
317
79e53945
JB
318static void intel_lvds_mode_set(struct drm_encoder *encoder,
319 struct drm_display_mode *mode,
320 struct drm_display_mode *adjusted_mode)
321{
79e53945
JB
322 /*
323 * The LVDS pin pair will already have been turned on in the
324 * intel_crtc_mode_set since it has a large impact on the DPLL
325 * settings.
326 */
79e53945
JB
327}
328
329/**
330 * Detect the LVDS connection.
331 *
b42d4c5c
JB
332 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
333 * connected and closed means disconnected. We also send hotplug events as
334 * needed, using lid status notification from the input layer.
79e53945 335 */
7b334fcb 336static enum drm_connector_status
930a9e28 337intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 338{
7b9c5abe 339 struct drm_device *dev = connector->dev;
6ee3b5a1 340 enum drm_connector_status status;
b42d4c5c 341
fe16d949
CW
342 status = intel_panel_detect(dev);
343 if (status != connector_status_unknown)
344 return status;
01fe9dbd 345
6ee3b5a1 346 return connector_status_connected;
79e53945
JB
347}
348
349/**
350 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
351 */
352static int intel_lvds_get_modes(struct drm_connector *connector)
353{
62165e0d 354 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 355 struct drm_device *dev = connector->dev;
788319d4 356 struct drm_display_mode *mode;
79e53945 357
9cd300e0 358 /* use cached edid if we have one */
2aa4f099 359 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 360 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 361
dd06f90e 362 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 363 if (mode == NULL)
788319d4 364 return 0;
79e53945 365
788319d4
CW
366 drm_mode_probed_add(connector, mode);
367 return 1;
79e53945
JB
368}
369
0544edfd
TB
370static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
371{
bc0daf48 372 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
373 return 1;
374}
375
376/* The GPU hangs up on these systems if modeset is performed on LID open */
377static const struct dmi_system_id intel_no_modeset_on_lid[] = {
378 {
379 .callback = intel_no_modeset_on_lid_dmi_callback,
380 .ident = "Toshiba Tecra A11",
381 .matches = {
382 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
383 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
384 },
385 },
386
387 { } /* terminating entry */
388};
389
c9354c85 390/*
b8efb17b
ZR
391 * Lid events. Note the use of 'modeset':
392 * - we set it to MODESET_ON_LID_OPEN on lid close,
393 * and set it to MODESET_DONE on open
c9354c85 394 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
395 * duplicate events where it was already properly set)
396 * - the suspend/resume paths will set it to
397 * MODESET_SUSPENDED and ignore the lid open event,
398 * because they restore the mode ("lid open").
c9354c85 399 */
c1c7af60
JB
400static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
401 void *unused)
402{
db1740a0
JN
403 struct intel_lvds_connector *lvds_connector =
404 container_of(nb, struct intel_lvds_connector, lid_notifier);
405 struct drm_connector *connector = &lvds_connector->base.base;
406 struct drm_device *dev = connector->dev;
407 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 408
2fb4e61d
AW
409 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
410 return NOTIFY_OK;
411
b8efb17b
ZR
412 mutex_lock(&dev_priv->modeset_restore_lock);
413 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
414 goto exit;
a2565377
ZY
415 /*
416 * check and update the status of LVDS connector after receiving
417 * the LID nofication event.
418 */
db1740a0 419 connector->status = connector->funcs->detect(connector, false);
7b334fcb 420
0544edfd
TB
421 /* Don't force modeset on machines where it causes a GPU lockup */
422 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 423 goto exit;
c9354c85 424 if (!acpi_lid_open()) {
b8efb17b
ZR
425 /* do modeset on next lid open event */
426 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
427 goto exit;
06891e27 428 }
c1c7af60 429
b8efb17b
ZR
430 if (dev_priv->modeset_restore == MODESET_DONE)
431 goto exit;
c9354c85 432
a0e99e68 433 drm_modeset_lock_all(dev);
45e2b5f6 434 intel_modeset_setup_hw_state(dev, true);
a0e99e68 435 drm_modeset_unlock_all(dev);
06324194 436
b8efb17b
ZR
437 dev_priv->modeset_restore = MODESET_DONE;
438
439exit:
440 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
441 return NOTIFY_OK;
442}
443
79e53945
JB
444/**
445 * intel_lvds_destroy - unregister and free LVDS structures
446 * @connector: connector to free
447 *
448 * Unregister the DDC bus for this connector then free the driver private
449 * structure.
450 */
451static void intel_lvds_destroy(struct drm_connector *connector)
452{
db1740a0
JN
453 struct intel_lvds_connector *lvds_connector =
454 to_lvds_connector(connector);
79e53945 455
db1740a0
JN
456 if (lvds_connector->lid_notifier.notifier_call)
457 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 458
9cd300e0
JN
459 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
460 kfree(lvds_connector->base.edid);
461
1d508706 462 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 463
79e53945
JB
464 drm_sysfs_connector_remove(connector);
465 drm_connector_cleanup(connector);
466 kfree(connector);
467}
468
335041ed
JB
469static int intel_lvds_set_property(struct drm_connector *connector,
470 struct drm_property *property,
471 uint64_t value)
472{
4d891523 473 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 474 struct drm_device *dev = connector->dev;
3fbe18d6 475
788319d4 476 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 477 struct drm_crtc *crtc;
bb8a3560 478
53bd8389
JB
479 if (value == DRM_MODE_SCALE_NONE) {
480 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 481 return -EINVAL;
3fbe18d6 482 }
788319d4 483
4d891523 484 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
485 /* the LVDS scaling property is not changed */
486 return 0;
487 }
4d891523 488 intel_connector->panel.fitting_mode = value;
62165e0d
JN
489
490 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
491 if (crtc && crtc->enabled) {
492 /*
493 * If the CRTC is enabled, the display will be changed
494 * according to the new panel fitting mode.
495 */
c0c36b94 496 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
497 }
498 }
499
335041ed
JB
500 return 0;
501}
502
79e53945 503static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 504 .mode_set = intel_lvds_mode_set,
79e53945
JB
505};
506
507static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
508 .get_modes = intel_lvds_get_modes,
509 .mode_valid = intel_lvds_mode_valid,
df0e9248 510 .best_encoder = intel_best_encoder,
79e53945
JB
511};
512
513static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 514 .dpms = intel_connector_dpms,
79e53945
JB
515 .detect = intel_lvds_detect,
516 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 517 .set_property = intel_lvds_set_property,
79e53945
JB
518 .destroy = intel_lvds_destroy,
519};
520
79e53945 521static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 522 .destroy = intel_encoder_destroy,
79e53945
JB
523};
524
425d244c
JW
525static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
526{
bc0daf48 527 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
528 return 1;
529}
79e53945 530
425d244c 531/* These systems claim to have LVDS, but really don't */
93c05f22 532static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
533 {
534 .callback = intel_no_lvds_dmi_callback,
535 .ident = "Apple Mac Mini (Core series)",
536 .matches = {
98acd46f 537 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
538 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
539 },
540 },
541 {
542 .callback = intel_no_lvds_dmi_callback,
543 .ident = "Apple Mac Mini (Core 2 series)",
544 .matches = {
98acd46f 545 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
546 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
547 },
548 },
549 {
550 .callback = intel_no_lvds_dmi_callback,
551 .ident = "MSI IM-945GSE-A",
552 .matches = {
553 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
554 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
555 },
556 },
557 {
558 .callback = intel_no_lvds_dmi_callback,
559 .ident = "Dell Studio Hybrid",
560 .matches = {
561 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
562 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
563 },
564 },
70aa96ca
JW
565 {
566 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
567 .ident = "Dell OptiPlex FX170",
568 .matches = {
569 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
570 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
571 },
572 },
573 {
574 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
575 .ident = "AOpen Mini PC",
576 .matches = {
577 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
578 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
579 },
580 },
ed8c754b
TV
581 {
582 .callback = intel_no_lvds_dmi_callback,
583 .ident = "AOpen Mini PC MP915",
584 .matches = {
585 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
586 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
587 },
588 },
22ab70d3
KP
589 {
590 .callback = intel_no_lvds_dmi_callback,
591 .ident = "AOpen i915GMm-HFS",
592 .matches = {
593 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
594 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
595 },
596 },
e57b6886
DV
597 {
598 .callback = intel_no_lvds_dmi_callback,
599 .ident = "AOpen i45GMx-I",
600 .matches = {
601 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
602 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
603 },
604 },
fa0864b2
MC
605 {
606 .callback = intel_no_lvds_dmi_callback,
607 .ident = "Aopen i945GTt-VFA",
608 .matches = {
609 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
610 },
611 },
9875557e
SB
612 {
613 .callback = intel_no_lvds_dmi_callback,
614 .ident = "Clientron U800",
615 .matches = {
616 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
617 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
618 },
619 },
6a574b5b 620 {
44306ab3
JS
621 .callback = intel_no_lvds_dmi_callback,
622 .ident = "Clientron E830",
623 .matches = {
624 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
625 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
626 },
627 },
628 {
6a574b5b
HG
629 .callback = intel_no_lvds_dmi_callback,
630 .ident = "Asus EeeBox PC EB1007",
631 .matches = {
632 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
633 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
634 },
635 },
0999bbe0
AJ
636 {
637 .callback = intel_no_lvds_dmi_callback,
638 .ident = "Asus AT5NM10T-I",
639 .matches = {
640 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
641 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
642 },
643 },
33471119
JBG
644 {
645 .callback = intel_no_lvds_dmi_callback,
45a211d7 646 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
647 .matches = {
648 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 649 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
650 },
651 },
f5b8a7ed
MG
652 {
653 .callback = intel_no_lvds_dmi_callback,
654 .ident = "Hewlett-Packard t5745",
655 .matches = {
656 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 657 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
658 },
659 },
660 {
661 .callback = intel_no_lvds_dmi_callback,
662 .ident = "Hewlett-Packard st5747",
663 .matches = {
664 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 665 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
666 },
667 },
97effadb
AA
668 {
669 .callback = intel_no_lvds_dmi_callback,
670 .ident = "MSI Wind Box DC500",
671 .matches = {
672 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
673 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
674 },
675 },
a51d4ed0
CW
676 {
677 .callback = intel_no_lvds_dmi_callback,
678 .ident = "Gigabyte GA-D525TUD",
679 .matches = {
680 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
681 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
682 },
683 },
c31407a3
CW
684 {
685 .callback = intel_no_lvds_dmi_callback,
686 .ident = "Supermicro X7SPA-H",
687 .matches = {
688 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
689 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
690 },
691 },
9e9dd0e8
CL
692 {
693 .callback = intel_no_lvds_dmi_callback,
694 .ident = "Fujitsu Esprimo Q900",
695 .matches = {
696 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
697 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
698 },
699 },
425d244c
JW
700
701 { } /* terminating entry */
702};
79e53945 703
18f9ed12
ZY
704/**
705 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
706 * @dev: drm device
707 * @connector: LVDS connector
708 *
709 * Find the reduced downclock for LVDS in EDID.
710 */
711static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
712 struct drm_display_mode *fixed_mode,
713 struct drm_connector *connector)
18f9ed12
ZY
714{
715 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 716 struct drm_display_mode *scan;
18f9ed12
ZY
717 int temp_downclock;
718
788319d4 719 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
720 list_for_each_entry(scan, &connector->probed_modes, head) {
721 /*
722 * If one mode has the same resolution with the fixed_panel
723 * mode while they have the different refresh rate, it means
724 * that the reduced downclock is found for the LVDS. In such
725 * case we can set the different FPx0/1 to dynamically select
726 * between low and high frequency.
727 */
788319d4
CW
728 if (scan->hdisplay == fixed_mode->hdisplay &&
729 scan->hsync_start == fixed_mode->hsync_start &&
730 scan->hsync_end == fixed_mode->hsync_end &&
731 scan->htotal == fixed_mode->htotal &&
732 scan->vdisplay == fixed_mode->vdisplay &&
733 scan->vsync_start == fixed_mode->vsync_start &&
734 scan->vsync_end == fixed_mode->vsync_end &&
735 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
736 if (scan->clock < temp_downclock) {
737 /*
738 * The downclock is already found. But we
739 * expect to find the lower downclock.
740 */
741 temp_downclock = scan->clock;
742 }
743 }
744 }
788319d4 745 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
746 /* We found the downclock for LVDS. */
747 dev_priv->lvds_downclock_avail = 1;
748 dev_priv->lvds_downclock = temp_downclock;
749 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
750 "Normal clock %dKhz, downclock %dKhz\n",
751 fixed_mode->clock, temp_downclock);
18f9ed12 752 }
18f9ed12
ZY
753}
754
7cf4f69d
ZY
755/*
756 * Enumerate the child dev array parsed from VBT to check whether
757 * the LVDS is present.
758 * If it is present, return 1.
759 * If it is not present, return false.
760 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 761 */
270eea0f
CW
762static bool lvds_is_present_in_vbt(struct drm_device *dev,
763 u8 *i2c_pin)
7cf4f69d
ZY
764{
765 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 766 int i;
7cf4f69d 767
41aa3448 768 if (!dev_priv->vbt.child_dev_num)
425904dd 769 return true;
7cf4f69d 770
41aa3448
RV
771 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
772 struct child_device_config *child = dev_priv->vbt.child_dev + i;
425904dd
CW
773
774 /* If the device type is not LFP, continue.
775 * We have to check both the new identifiers as well as the
776 * old for compatibility with some BIOSes.
7cf4f69d 777 */
425904dd
CW
778 if (child->device_type != DEVICE_TYPE_INT_LFP &&
779 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
780 continue;
781
3bd7d909
DK
782 if (intel_gmbus_is_port_valid(child->i2c_pin))
783 *i2c_pin = child->i2c_pin;
270eea0f 784
425904dd
CW
785 /* However, we cannot trust the BIOS writers to populate
786 * the VBT correctly. Since LVDS requires additional
787 * information from AIM blocks, a non-zero addin offset is
788 * a good indicator that the LVDS is actually present.
7cf4f69d 789 */
425904dd
CW
790 if (child->addin_offset)
791 return true;
792
793 /* But even then some BIOS writers perform some black magic
794 * and instantiate the device without reference to any
795 * additional data. Trust that if the VBT was written into
796 * the OpRegion then they have validated the LVDS's existence.
797 */
798 if (dev_priv->opregion.vbt)
799 return true;
7cf4f69d 800 }
425904dd
CW
801
802 return false;
7cf4f69d
ZY
803}
804
1974cad0
DV
805static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
806{
807 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
808 return 1;
809}
810
811static const struct dmi_system_id intel_dual_link_lvds[] = {
812 {
813 .callback = intel_dual_link_lvds_callback,
814 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
815 .matches = {
816 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
817 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
818 },
819 },
820 { } /* terminating entry */
821};
822
823bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
824{
825 struct intel_encoder *encoder;
826 struct intel_lvds_encoder *lvds_encoder;
827
828 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
829 base.head) {
830 if (encoder->type == INTEL_OUTPUT_LVDS) {
831 lvds_encoder = to_lvds_encoder(&encoder->base);
832
833 return lvds_encoder->is_dual_link;
834 }
835 }
836
837 return false;
838}
839
7dec0606 840static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 841{
7dec0606 842 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
843 unsigned int val;
844 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
845
846 /* use the module option value if specified */
847 if (i915_lvds_channel_mode > 0)
848 return i915_lvds_channel_mode == 2;
849
850 if (dmi_check_system(intel_dual_link_lvds))
851 return true;
852
13c7d870
DV
853 /* BIOS should set the proper LVDS register value at boot, but
854 * in reality, it doesn't set the value when the lid is closed;
855 * we need to check "the value to be set" in VBT when LVDS
856 * register is uninitialized.
857 */
7dec0606 858 val = I915_READ(lvds_encoder->reg);
13c7d870 859 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 860 val = dev_priv->vbt.bios_lvds_val;
13c7d870 861
1974cad0
DV
862 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
863}
864
f3cfcba6
CW
865static bool intel_lvds_supported(struct drm_device *dev)
866{
867 /* With the introduction of the PCH we gained a dedicated
868 * LVDS presence pin, use it. */
311e359c 869 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
870 return true;
871
872 /* Otherwise LVDS was only attached to mobile products,
873 * except for the inglorious 830gm */
311e359c
PZ
874 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
875 return true;
876
877 return false;
f3cfcba6
CW
878}
879
79e53945
JB
880/**
881 * intel_lvds_init - setup LVDS connectors on this device
882 * @dev: drm device
883 *
884 * Create the connector, register the LVDS DDC bus, and try to figure out what
885 * modes we can display on the LVDS panel (if present).
886 */
c9093354 887void intel_lvds_init(struct drm_device *dev)
79e53945
JB
888{
889 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 890 struct intel_lvds_encoder *lvds_encoder;
21d40d37 891 struct intel_encoder *intel_encoder;
c7362c4d 892 struct intel_lvds_connector *lvds_connector;
bb8a3560 893 struct intel_connector *intel_connector;
79e53945
JB
894 struct drm_connector *connector;
895 struct drm_encoder *encoder;
896 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 897 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 898 struct edid *edid;
79e53945
JB
899 struct drm_crtc *crtc;
900 u32 lvds;
270eea0f
CW
901 int pipe;
902 u8 pin;
79e53945 903
f3cfcba6 904 if (!intel_lvds_supported(dev))
c9093354 905 return;
f3cfcba6 906
425d244c
JW
907 /* Skip init on machines we know falsely report LVDS */
908 if (dmi_check_system(intel_no_lvds))
c9093354 909 return;
565dcd46 910
270eea0f
CW
911 pin = GMBUS_PORT_PANEL;
912 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 913 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c9093354 914 return;
38b3037e 915 }
e99da35f 916
c619eed4 917 if (HAS_PCH_SPLIT(dev)) {
541998a1 918 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 919 return;
41aa3448 920 if (dev_priv->vbt.edp_support) {
28c97730 921 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 922 return;
32f9d658 923 }
541998a1
ZW
924 }
925
29b99b48
JN
926 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
927 if (!lvds_encoder)
c9093354 928 return;
79e53945 929
c7362c4d
JN
930 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
931 if (!lvds_connector) {
29b99b48 932 kfree(lvds_encoder);
c9093354 933 return;
bb8a3560
ZW
934 }
935
62165e0d
JN
936 lvds_encoder->attached_connector = lvds_connector;
937
29b99b48 938 intel_encoder = &lvds_encoder->base;
4ef69c7a 939 encoder = &intel_encoder->base;
c7362c4d 940 intel_connector = &lvds_connector->base;
ea5b213a 941 connector = &intel_connector->base;
bb8a3560 942 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
943 DRM_MODE_CONNECTOR_LVDS);
944
4ef69c7a 945 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
946 DRM_MODE_ENCODER_LVDS);
947
c22834ec 948 intel_encoder->enable = intel_enable_lvds;
fc683091 949 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
7ae89233 950 intel_encoder->compute_config = intel_lvds_compute_config;
c22834ec 951 intel_encoder->disable = intel_disable_lvds;
b1dc332c 952 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 953 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 954 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 955
df0e9248 956 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 957 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 958
66a9278e 959 intel_encoder->cloneable = false;
27f8227b
JB
960 if (HAS_PCH_SPLIT(dev))
961 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
962 else if (IS_GEN4(dev))
963 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
964 else
965 intel_encoder->crtc_mask = (1 << 1);
966
79e53945
JB
967 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
968 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
969 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
970 connector->interlace_allowed = false;
971 connector->doublescan_allowed = false;
972
7dec0606
DV
973 if (HAS_PCH_SPLIT(dev)) {
974 lvds_encoder->reg = PCH_LVDS;
975 } else {
976 lvds_encoder->reg = LVDS;
977 }
978
3fbe18d6
ZY
979 /* create the scaling mode property */
980 drm_mode_create_scaling_mode_property(dev);
662595df 981 drm_object_attach_property(&connector->base,
3fbe18d6 982 dev->mode_config.scaling_mode_property,
dd1ea37d 983 DRM_MODE_SCALE_ASPECT);
4d891523 984 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
985 /*
986 * LVDS discovery:
987 * 1) check for EDID on DDC
988 * 2) check for VBT data
989 * 3) check to see if LVDS is already on
990 * if none of the above, no panel
991 * 4) make sure lid is open
992 * if closed, act like it's not there for now
993 */
994
79e53945
JB
995 /*
996 * Attempt to get the fixed panel mode from DDC. Assume that the
997 * preferred mode is the right one.
998 */
9cd300e0
JN
999 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1000 if (edid) {
1001 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1002 drm_mode_connector_update_edid_property(connector,
9cd300e0 1003 edid);
3f8ff0e7 1004 } else {
9cd300e0
JN
1005 kfree(edid);
1006 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1007 }
9cd300e0
JN
1008 } else {
1009 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1010 }
9cd300e0
JN
1011 lvds_connector->base.edid = edid;
1012
1013 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1014 /* Didn't get an EDID, so
1015 * Set wide sync ranges so we get all modes
1016 * handed to valid_mode for checking
1017 */
1018 connector->display_info.min_vfreq = 0;
1019 connector->display_info.max_vfreq = 200;
1020 connector->display_info.min_hfreq = 0;
1021 connector->display_info.max_hfreq = 200;
1022 }
79e53945
JB
1023
1024 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1025 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1026 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1027 drm_mode_debug_printmodeline(scan);
1028
dd06f90e 1029 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1030 if (fixed_mode) {
1031 intel_find_lvds_downclock(dev, fixed_mode,
1032 connector);
1033 goto out;
1034 }
79e53945 1035 }
79e53945
JB
1036 }
1037
1038 /* Failed to get EDID, what about VBT? */
41aa3448 1039 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1040 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1041 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1042
41aa3448 1043 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1044 if (fixed_mode) {
1045 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1046 goto out;
1047 }
79e53945
JB
1048 }
1049
1050 /*
1051 * If we didn't get EDID, try checking if the panel is already turned
1052 * on. If so, assume that whatever is currently programmed is the
1053 * correct mode.
1054 */
541998a1 1055
f2b115e6 1056 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1057 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1058 goto failed;
1059
79e53945
JB
1060 lvds = I915_READ(LVDS);
1061 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1062 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1063
1064 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1065 fixed_mode = intel_crtc_mode_get(dev, crtc);
1066 if (fixed_mode) {
6a9d51b7
CW
1067 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1068 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1069 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1070 goto out;
79e53945
JB
1071 }
1072 }
1073
1074 /* If we still don't have a mode after all that, give up. */
dd06f90e 1075 if (!fixed_mode)
79e53945
JB
1076 goto failed;
1077
79e53945 1078out:
7dec0606 1079 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1080 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1081 lvds_encoder->is_dual_link ? "dual" : "single");
1082
24ded204
DV
1083 /*
1084 * Unlock registers and just
1085 * leave them unlocked
1086 */
c619eed4 1087 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1088 I915_WRITE(PCH_PP_CONTROL,
1089 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1090 } else {
ed10fca9
KP
1091 I915_WRITE(PP_CONTROL,
1092 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1093 }
db1740a0
JN
1094 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1095 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1096 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1097 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1098 }
79e53945 1099 drm_sysfs_connector_add(connector);
aaa6fd2a 1100
dd06f90e 1101 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1102 intel_panel_setup_backlight(connector);
aaa6fd2a 1103
c9093354 1104 return;
79e53945
JB
1105
1106failed:
8a4c47f3 1107 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1108 drm_connector_cleanup(connector);
1991bdfa 1109 drm_encoder_cleanup(encoder);
dd06f90e
JN
1110 if (fixed_mode)
1111 drm_mode_destroy(dev, fixed_mode);
29b99b48 1112 kfree(lvds_encoder);
c7362c4d 1113 kfree(lvds_connector);
c9093354 1114 return;
79e53945 1115}