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CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
fc683091
DV
89/* The LVDS pin pair needs to be on before the DPLLs are enabled.
90 * This is an exception to the general rule that mode_set doesn't turn
91 * things on.
92 */
93static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
94{
95 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
96 struct drm_device *dev = encoder->base.dev;
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
99 struct drm_display_mode *fixed_mode =
100 lvds_encoder->attached_connector->base.panel.fixed_mode;
101 int pipe = intel_crtc->pipe;
102 u32 temp;
103
fc683091
DV
104 temp = I915_READ(lvds_encoder->reg);
105 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
106
107 if (HAS_PCH_CPT(dev)) {
108 temp &= ~PORT_TRANS_SEL_MASK;
109 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 110 } else {
62810e5a
DV
111 if (pipe == 1) {
112 temp |= LVDS_PIPEB_SELECT;
113 } else {
114 temp &= ~LVDS_PIPEB_SELECT;
115 }
fc683091 116 }
62810e5a 117
fc683091 118 /* set the corresponsding LVDS_BORDER bit */
68fc8742 119 temp |= intel_crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
120 /* Set the B0-B3 data pairs corresponding to whether we're going to
121 * set the DPLLs for dual-channel mode or not.
122 */
123 if (lvds_encoder->is_dual_link)
124 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
125 else
126 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
127
128 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
129 * appropriately here, but we need to look more thoroughly into how
130 * panels behave in the two modes.
131 */
62810e5a
DV
132
133 /* Set the dithering flag on LVDS as needed, note that there is no
134 * special lvds dither control bit on pch-split platforms, dithering is
135 * only controlled through the PIPECONF reg. */
136 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
137 /* Bspec wording suggests that LVDS port dithering only exists
138 * for 18bpp panels. */
139 if (intel_crtc->config.dither &&
140 intel_crtc->config.pipe_bpp == 18)
fc683091
DV
141 temp |= LVDS_ENABLE_DITHER;
142 else
143 temp &= ~LVDS_ENABLE_DITHER;
144 }
145 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
146 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
147 temp |= LVDS_HSYNC_POLARITY;
148 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
149 temp |= LVDS_VSYNC_POLARITY;
150
151 I915_WRITE(lvds_encoder->reg, temp);
152}
153
79e53945
JB
154/**
155 * Sets the power state for the panel.
156 */
c22834ec 157static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 158{
c22834ec 159 struct drm_device *dev = encoder->base.dev;
29b99b48 160 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 161 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 162 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 163 u32 ctl_reg, stat_reg;
541998a1 164
c619eed4 165 if (HAS_PCH_SPLIT(dev)) {
541998a1 166 ctl_reg = PCH_PP_CONTROL;
de842eff 167 stat_reg = PCH_PP_STATUS;
541998a1
ZW
168 } else {
169 ctl_reg = PP_CONTROL;
de842eff 170 stat_reg = PP_STATUS;
541998a1 171 }
79e53945 172
7dec0606 173 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 174
2a1292fd 175 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 176 POSTING_READ(lvds_encoder->reg);
de842eff
KP
177 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
178 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 179
24ded204 180 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
181}
182
c22834ec 183static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 184{
c22834ec 185 struct drm_device *dev = encoder->base.dev;
29b99b48 186 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 187 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 188 u32 ctl_reg, stat_reg;
2a1292fd
CW
189
190 if (HAS_PCH_SPLIT(dev)) {
191 ctl_reg = PCH_PP_CONTROL;
de842eff 192 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
193 } else {
194 ctl_reg = PP_CONTROL;
de842eff 195 stat_reg = PP_STATUS;
2a1292fd
CW
196 }
197
47356eb6 198 intel_panel_disable_backlight(dev);
2a1292fd
CW
199
200 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
201 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
202 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 203
7dec0606
DV
204 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
205 POSTING_READ(lvds_encoder->reg);
79e53945
JB
206}
207
79e53945
JB
208static int intel_lvds_mode_valid(struct drm_connector *connector,
209 struct drm_display_mode *mode)
210{
dd06f90e
JN
211 struct intel_connector *intel_connector = to_intel_connector(connector);
212 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 213
788319d4
CW
214 if (mode->hdisplay > fixed_mode->hdisplay)
215 return MODE_PANEL;
216 if (mode->vdisplay > fixed_mode->vdisplay)
217 return MODE_PANEL;
79e53945
JB
218
219 return MODE_OK;
220}
221
7ae89233
DV
222static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
223 struct intel_crtc_config *pipe_config)
79e53945 224{
7ae89233 225 struct drm_device *dev = intel_encoder->base.dev;
79e53945 226 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
227 struct intel_lvds_encoder *lvds_encoder =
228 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
229 struct intel_connector *intel_connector =
230 &lvds_encoder->attached_connector->base;
7ae89233 231 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 232 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 233 unsigned int lvds_bpp;
79e53945
JB
234
235 /* Should never happen!! */
a6c45cf0 236 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 237 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
238 return false;
239 }
240
29b99b48 241 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 242 return false;
1d8e1c75 243
4e53c2e0
DV
244 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
245 LVDS_A3_POWER_UP)
246 lvds_bpp = 8*3;
247 else
248 lvds_bpp = 6*3;
249
e29c22c0 250 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
251 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
252 pipe_config->pipe_bpp, lvds_bpp);
253 pipe_config->pipe_bpp = lvds_bpp;
254 }
d8b32247 255
79e53945 256 /*
71677043 257 * We have timings from the BIOS for the panel, put them in
79e53945
JB
258 * to the adjusted mode. The CRTC will be set up for this mode,
259 * with the panel scaling set up to source from the H/VDisplay
260 * of the original mode.
261 */
4d891523 262 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 263 adjusted_mode);
1d8e1c75
CW
264
265 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
266 pipe_config->has_pch_encoder = true;
267
b074cec8
JB
268 intel_pch_panel_fitting(intel_crtc, pipe_config,
269 intel_connector->panel.fitting_mode);
1d8e1c75 270 return true;
2dd24552
JB
271 } else {
272 intel_gmch_panel_fitting(intel_crtc, pipe_config,
273 intel_connector->panel.fitting_mode);
1d8e1c75 274 }
79e53945 275
f9bef081 276 drm_mode_set_crtcinfo(adjusted_mode, 0);
7ae89233 277 pipe_config->timings_set = true;
f9bef081 278
79e53945
JB
279 /*
280 * XXX: It would be nice to support lower refresh rates on the
281 * panels to reduce power consumption, and perhaps match the
282 * user's requested refresh rate.
283 */
284
285 return true;
286}
287
79e53945
JB
288static void intel_lvds_mode_set(struct drm_encoder *encoder,
289 struct drm_display_mode *mode,
290 struct drm_display_mode *adjusted_mode)
291{
79e53945
JB
292 /*
293 * The LVDS pin pair will already have been turned on in the
294 * intel_crtc_mode_set since it has a large impact on the DPLL
295 * settings.
296 */
79e53945
JB
297}
298
299/**
300 * Detect the LVDS connection.
301 *
b42d4c5c
JB
302 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
303 * connected and closed means disconnected. We also send hotplug events as
304 * needed, using lid status notification from the input layer.
79e53945 305 */
7b334fcb 306static enum drm_connector_status
930a9e28 307intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 308{
7b9c5abe 309 struct drm_device *dev = connector->dev;
6ee3b5a1 310 enum drm_connector_status status;
b42d4c5c 311
fe16d949
CW
312 status = intel_panel_detect(dev);
313 if (status != connector_status_unknown)
314 return status;
01fe9dbd 315
6ee3b5a1 316 return connector_status_connected;
79e53945
JB
317}
318
319/**
320 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
321 */
322static int intel_lvds_get_modes(struct drm_connector *connector)
323{
62165e0d 324 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 325 struct drm_device *dev = connector->dev;
788319d4 326 struct drm_display_mode *mode;
79e53945 327
9cd300e0 328 /* use cached edid if we have one */
2aa4f099 329 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 330 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 331
dd06f90e 332 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 333 if (mode == NULL)
788319d4 334 return 0;
79e53945 335
788319d4
CW
336 drm_mode_probed_add(connector, mode);
337 return 1;
79e53945
JB
338}
339
0544edfd
TB
340static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
341{
bc0daf48 342 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
343 return 1;
344}
345
346/* The GPU hangs up on these systems if modeset is performed on LID open */
347static const struct dmi_system_id intel_no_modeset_on_lid[] = {
348 {
349 .callback = intel_no_modeset_on_lid_dmi_callback,
350 .ident = "Toshiba Tecra A11",
351 .matches = {
352 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
353 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
354 },
355 },
356
357 { } /* terminating entry */
358};
359
c9354c85 360/*
b8efb17b
ZR
361 * Lid events. Note the use of 'modeset':
362 * - we set it to MODESET_ON_LID_OPEN on lid close,
363 * and set it to MODESET_DONE on open
c9354c85 364 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
365 * duplicate events where it was already properly set)
366 * - the suspend/resume paths will set it to
367 * MODESET_SUSPENDED and ignore the lid open event,
368 * because they restore the mode ("lid open").
c9354c85 369 */
c1c7af60
JB
370static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
371 void *unused)
372{
db1740a0
JN
373 struct intel_lvds_connector *lvds_connector =
374 container_of(nb, struct intel_lvds_connector, lid_notifier);
375 struct drm_connector *connector = &lvds_connector->base.base;
376 struct drm_device *dev = connector->dev;
377 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 378
2fb4e61d
AW
379 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
380 return NOTIFY_OK;
381
b8efb17b
ZR
382 mutex_lock(&dev_priv->modeset_restore_lock);
383 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
384 goto exit;
a2565377
ZY
385 /*
386 * check and update the status of LVDS connector after receiving
387 * the LID nofication event.
388 */
db1740a0 389 connector->status = connector->funcs->detect(connector, false);
7b334fcb 390
0544edfd
TB
391 /* Don't force modeset on machines where it causes a GPU lockup */
392 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 393 goto exit;
c9354c85 394 if (!acpi_lid_open()) {
b8efb17b
ZR
395 /* do modeset on next lid open event */
396 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
397 goto exit;
06891e27 398 }
c1c7af60 399
b8efb17b
ZR
400 if (dev_priv->modeset_restore == MODESET_DONE)
401 goto exit;
c9354c85 402
a0e99e68 403 drm_modeset_lock_all(dev);
45e2b5f6 404 intel_modeset_setup_hw_state(dev, true);
a0e99e68 405 drm_modeset_unlock_all(dev);
06324194 406
b8efb17b
ZR
407 dev_priv->modeset_restore = MODESET_DONE;
408
409exit:
410 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
411 return NOTIFY_OK;
412}
413
79e53945
JB
414/**
415 * intel_lvds_destroy - unregister and free LVDS structures
416 * @connector: connector to free
417 *
418 * Unregister the DDC bus for this connector then free the driver private
419 * structure.
420 */
421static void intel_lvds_destroy(struct drm_connector *connector)
422{
db1740a0
JN
423 struct intel_lvds_connector *lvds_connector =
424 to_lvds_connector(connector);
79e53945 425
db1740a0
JN
426 if (lvds_connector->lid_notifier.notifier_call)
427 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 428
9cd300e0
JN
429 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
430 kfree(lvds_connector->base.edid);
431
1d508706 432 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 433
79e53945
JB
434 drm_sysfs_connector_remove(connector);
435 drm_connector_cleanup(connector);
436 kfree(connector);
437}
438
335041ed
JB
439static int intel_lvds_set_property(struct drm_connector *connector,
440 struct drm_property *property,
441 uint64_t value)
442{
4d891523 443 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 444 struct drm_device *dev = connector->dev;
3fbe18d6 445
788319d4 446 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 447 struct drm_crtc *crtc;
bb8a3560 448
53bd8389
JB
449 if (value == DRM_MODE_SCALE_NONE) {
450 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 451 return -EINVAL;
3fbe18d6 452 }
788319d4 453
4d891523 454 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
455 /* the LVDS scaling property is not changed */
456 return 0;
457 }
4d891523 458 intel_connector->panel.fitting_mode = value;
62165e0d
JN
459
460 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
461 if (crtc && crtc->enabled) {
462 /*
463 * If the CRTC is enabled, the display will be changed
464 * according to the new panel fitting mode.
465 */
c0c36b94 466 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
467 }
468 }
469
335041ed
JB
470 return 0;
471}
472
79e53945 473static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 474 .mode_set = intel_lvds_mode_set,
79e53945
JB
475};
476
477static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
478 .get_modes = intel_lvds_get_modes,
479 .mode_valid = intel_lvds_mode_valid,
df0e9248 480 .best_encoder = intel_best_encoder,
79e53945
JB
481};
482
483static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 484 .dpms = intel_connector_dpms,
79e53945
JB
485 .detect = intel_lvds_detect,
486 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 487 .set_property = intel_lvds_set_property,
79e53945
JB
488 .destroy = intel_lvds_destroy,
489};
490
79e53945 491static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 492 .destroy = intel_encoder_destroy,
79e53945
JB
493};
494
425d244c
JW
495static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
496{
bc0daf48 497 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
498 return 1;
499}
79e53945 500
425d244c 501/* These systems claim to have LVDS, but really don't */
93c05f22 502static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
503 {
504 .callback = intel_no_lvds_dmi_callback,
505 .ident = "Apple Mac Mini (Core series)",
506 .matches = {
98acd46f 507 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
508 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
509 },
510 },
511 {
512 .callback = intel_no_lvds_dmi_callback,
513 .ident = "Apple Mac Mini (Core 2 series)",
514 .matches = {
98acd46f 515 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
516 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
517 },
518 },
519 {
520 .callback = intel_no_lvds_dmi_callback,
521 .ident = "MSI IM-945GSE-A",
522 .matches = {
523 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
524 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
525 },
526 },
527 {
528 .callback = intel_no_lvds_dmi_callback,
529 .ident = "Dell Studio Hybrid",
530 .matches = {
531 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
532 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
533 },
534 },
70aa96ca
JW
535 {
536 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
537 .ident = "Dell OptiPlex FX170",
538 .matches = {
539 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
540 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
541 },
542 },
543 {
544 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
545 .ident = "AOpen Mini PC",
546 .matches = {
547 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
548 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
549 },
550 },
ed8c754b
TV
551 {
552 .callback = intel_no_lvds_dmi_callback,
553 .ident = "AOpen Mini PC MP915",
554 .matches = {
555 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
556 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
557 },
558 },
22ab70d3
KP
559 {
560 .callback = intel_no_lvds_dmi_callback,
561 .ident = "AOpen i915GMm-HFS",
562 .matches = {
563 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
564 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
565 },
566 },
e57b6886
DV
567 {
568 .callback = intel_no_lvds_dmi_callback,
569 .ident = "AOpen i45GMx-I",
570 .matches = {
571 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
572 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
573 },
574 },
fa0864b2
MC
575 {
576 .callback = intel_no_lvds_dmi_callback,
577 .ident = "Aopen i945GTt-VFA",
578 .matches = {
579 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
580 },
581 },
9875557e
SB
582 {
583 .callback = intel_no_lvds_dmi_callback,
584 .ident = "Clientron U800",
585 .matches = {
586 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
587 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
588 },
589 },
6a574b5b 590 {
44306ab3
JS
591 .callback = intel_no_lvds_dmi_callback,
592 .ident = "Clientron E830",
593 .matches = {
594 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
595 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
596 },
597 },
598 {
6a574b5b
HG
599 .callback = intel_no_lvds_dmi_callback,
600 .ident = "Asus EeeBox PC EB1007",
601 .matches = {
602 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
603 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
604 },
605 },
0999bbe0
AJ
606 {
607 .callback = intel_no_lvds_dmi_callback,
608 .ident = "Asus AT5NM10T-I",
609 .matches = {
610 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
611 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
612 },
613 },
33471119
JBG
614 {
615 .callback = intel_no_lvds_dmi_callback,
616 .ident = "Hewlett-Packard HP t5740e Thin Client",
617 .matches = {
618 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
619 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
620 },
621 },
f5b8a7ed
MG
622 {
623 .callback = intel_no_lvds_dmi_callback,
624 .ident = "Hewlett-Packard t5745",
625 .matches = {
626 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 627 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
628 },
629 },
630 {
631 .callback = intel_no_lvds_dmi_callback,
632 .ident = "Hewlett-Packard st5747",
633 .matches = {
634 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 635 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
636 },
637 },
97effadb
AA
638 {
639 .callback = intel_no_lvds_dmi_callback,
640 .ident = "MSI Wind Box DC500",
641 .matches = {
642 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
643 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
644 },
645 },
a51d4ed0
CW
646 {
647 .callback = intel_no_lvds_dmi_callback,
648 .ident = "Gigabyte GA-D525TUD",
649 .matches = {
650 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
651 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
652 },
653 },
c31407a3
CW
654 {
655 .callback = intel_no_lvds_dmi_callback,
656 .ident = "Supermicro X7SPA-H",
657 .matches = {
658 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
659 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
660 },
661 },
9e9dd0e8
CL
662 {
663 .callback = intel_no_lvds_dmi_callback,
664 .ident = "Fujitsu Esprimo Q900",
665 .matches = {
666 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
667 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
668 },
669 },
425d244c
JW
670
671 { } /* terminating entry */
672};
79e53945 673
18f9ed12
ZY
674/**
675 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
676 * @dev: drm device
677 * @connector: LVDS connector
678 *
679 * Find the reduced downclock for LVDS in EDID.
680 */
681static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
682 struct drm_display_mode *fixed_mode,
683 struct drm_connector *connector)
18f9ed12
ZY
684{
685 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 686 struct drm_display_mode *scan;
18f9ed12
ZY
687 int temp_downclock;
688
788319d4 689 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
690 list_for_each_entry(scan, &connector->probed_modes, head) {
691 /*
692 * If one mode has the same resolution with the fixed_panel
693 * mode while they have the different refresh rate, it means
694 * that the reduced downclock is found for the LVDS. In such
695 * case we can set the different FPx0/1 to dynamically select
696 * between low and high frequency.
697 */
788319d4
CW
698 if (scan->hdisplay == fixed_mode->hdisplay &&
699 scan->hsync_start == fixed_mode->hsync_start &&
700 scan->hsync_end == fixed_mode->hsync_end &&
701 scan->htotal == fixed_mode->htotal &&
702 scan->vdisplay == fixed_mode->vdisplay &&
703 scan->vsync_start == fixed_mode->vsync_start &&
704 scan->vsync_end == fixed_mode->vsync_end &&
705 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
706 if (scan->clock < temp_downclock) {
707 /*
708 * The downclock is already found. But we
709 * expect to find the lower downclock.
710 */
711 temp_downclock = scan->clock;
712 }
713 }
714 }
788319d4 715 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
716 /* We found the downclock for LVDS. */
717 dev_priv->lvds_downclock_avail = 1;
718 dev_priv->lvds_downclock = temp_downclock;
719 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
720 "Normal clock %dKhz, downclock %dKhz\n",
721 fixed_mode->clock, temp_downclock);
18f9ed12 722 }
18f9ed12
ZY
723}
724
7cf4f69d
ZY
725/*
726 * Enumerate the child dev array parsed from VBT to check whether
727 * the LVDS is present.
728 * If it is present, return 1.
729 * If it is not present, return false.
730 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 731 */
270eea0f
CW
732static bool lvds_is_present_in_vbt(struct drm_device *dev,
733 u8 *i2c_pin)
7cf4f69d
ZY
734{
735 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 736 int i;
7cf4f69d
ZY
737
738 if (!dev_priv->child_dev_num)
425904dd 739 return true;
7cf4f69d 740
7cf4f69d 741 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
742 struct child_device_config *child = dev_priv->child_dev + i;
743
744 /* If the device type is not LFP, continue.
745 * We have to check both the new identifiers as well as the
746 * old for compatibility with some BIOSes.
7cf4f69d 747 */
425904dd
CW
748 if (child->device_type != DEVICE_TYPE_INT_LFP &&
749 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
750 continue;
751
3bd7d909
DK
752 if (intel_gmbus_is_port_valid(child->i2c_pin))
753 *i2c_pin = child->i2c_pin;
270eea0f 754
425904dd
CW
755 /* However, we cannot trust the BIOS writers to populate
756 * the VBT correctly. Since LVDS requires additional
757 * information from AIM blocks, a non-zero addin offset is
758 * a good indicator that the LVDS is actually present.
7cf4f69d 759 */
425904dd
CW
760 if (child->addin_offset)
761 return true;
762
763 /* But even then some BIOS writers perform some black magic
764 * and instantiate the device without reference to any
765 * additional data. Trust that if the VBT was written into
766 * the OpRegion then they have validated the LVDS's existence.
767 */
768 if (dev_priv->opregion.vbt)
769 return true;
7cf4f69d 770 }
425904dd
CW
771
772 return false;
7cf4f69d
ZY
773}
774
1974cad0
DV
775static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
776{
777 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
778 return 1;
779}
780
781static const struct dmi_system_id intel_dual_link_lvds[] = {
782 {
783 .callback = intel_dual_link_lvds_callback,
784 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
785 .matches = {
786 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
787 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
788 },
789 },
790 { } /* terminating entry */
791};
792
793bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
794{
795 struct intel_encoder *encoder;
796 struct intel_lvds_encoder *lvds_encoder;
797
798 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
799 base.head) {
800 if (encoder->type == INTEL_OUTPUT_LVDS) {
801 lvds_encoder = to_lvds_encoder(&encoder->base);
802
803 return lvds_encoder->is_dual_link;
804 }
805 }
806
807 return false;
808}
809
7dec0606 810static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 811{
7dec0606 812 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
813 unsigned int val;
814 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
815
816 /* use the module option value if specified */
817 if (i915_lvds_channel_mode > 0)
818 return i915_lvds_channel_mode == 2;
819
820 if (dmi_check_system(intel_dual_link_lvds))
821 return true;
822
13c7d870
DV
823 /* BIOS should set the proper LVDS register value at boot, but
824 * in reality, it doesn't set the value when the lid is closed;
825 * we need to check "the value to be set" in VBT when LVDS
826 * register is uninitialized.
827 */
7dec0606 828 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
829 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
830 val = dev_priv->bios_lvds_val;
831
1974cad0
DV
832 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
833}
834
f3cfcba6
CW
835static bool intel_lvds_supported(struct drm_device *dev)
836{
837 /* With the introduction of the PCH we gained a dedicated
838 * LVDS presence pin, use it. */
311e359c 839 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
840 return true;
841
842 /* Otherwise LVDS was only attached to mobile products,
843 * except for the inglorious 830gm */
311e359c
PZ
844 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
845 return true;
846
847 return false;
f3cfcba6
CW
848}
849
79e53945
JB
850/**
851 * intel_lvds_init - setup LVDS connectors on this device
852 * @dev: drm device
853 *
854 * Create the connector, register the LVDS DDC bus, and try to figure out what
855 * modes we can display on the LVDS panel (if present).
856 */
c5d1b51d 857bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
858{
859 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 860 struct intel_lvds_encoder *lvds_encoder;
21d40d37 861 struct intel_encoder *intel_encoder;
c7362c4d 862 struct intel_lvds_connector *lvds_connector;
bb8a3560 863 struct intel_connector *intel_connector;
79e53945
JB
864 struct drm_connector *connector;
865 struct drm_encoder *encoder;
866 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 867 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 868 struct edid *edid;
79e53945
JB
869 struct drm_crtc *crtc;
870 u32 lvds;
270eea0f
CW
871 int pipe;
872 u8 pin;
79e53945 873
f3cfcba6
CW
874 if (!intel_lvds_supported(dev))
875 return false;
876
425d244c
JW
877 /* Skip init on machines we know falsely report LVDS */
878 if (dmi_check_system(intel_no_lvds))
c5d1b51d 879 return false;
565dcd46 880
270eea0f
CW
881 pin = GMBUS_PORT_PANEL;
882 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 883 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 884 return false;
38b3037e 885 }
e99da35f 886
c619eed4 887 if (HAS_PCH_SPLIT(dev)) {
541998a1 888 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 889 return false;
5ceb0f9b 890 if (dev_priv->edp.support) {
28c97730 891 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 892 return false;
32f9d658 893 }
541998a1
ZW
894 }
895
29b99b48
JN
896 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
897 if (!lvds_encoder)
c5d1b51d 898 return false;
79e53945 899
c7362c4d
JN
900 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
901 if (!lvds_connector) {
29b99b48 902 kfree(lvds_encoder);
c5d1b51d 903 return false;
bb8a3560
ZW
904 }
905
62165e0d
JN
906 lvds_encoder->attached_connector = lvds_connector;
907
29b99b48 908 intel_encoder = &lvds_encoder->base;
4ef69c7a 909 encoder = &intel_encoder->base;
c7362c4d 910 intel_connector = &lvds_connector->base;
ea5b213a 911 connector = &intel_connector->base;
bb8a3560 912 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
913 DRM_MODE_CONNECTOR_LVDS);
914
4ef69c7a 915 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
916 DRM_MODE_ENCODER_LVDS);
917
c22834ec 918 intel_encoder->enable = intel_enable_lvds;
fc683091 919 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
7ae89233 920 intel_encoder->compute_config = intel_lvds_compute_config;
c22834ec 921 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
922 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
923 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 924
df0e9248 925 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 926 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 927
66a9278e 928 intel_encoder->cloneable = false;
27f8227b
JB
929 if (HAS_PCH_SPLIT(dev))
930 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
931 else if (IS_GEN4(dev))
932 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
933 else
934 intel_encoder->crtc_mask = (1 << 1);
935
79e53945
JB
936 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
937 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
938 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
939 connector->interlace_allowed = false;
940 connector->doublescan_allowed = false;
941
7dec0606
DV
942 if (HAS_PCH_SPLIT(dev)) {
943 lvds_encoder->reg = PCH_LVDS;
944 } else {
945 lvds_encoder->reg = LVDS;
946 }
947
3fbe18d6
ZY
948 /* create the scaling mode property */
949 drm_mode_create_scaling_mode_property(dev);
662595df 950 drm_object_attach_property(&connector->base,
3fbe18d6 951 dev->mode_config.scaling_mode_property,
dd1ea37d 952 DRM_MODE_SCALE_ASPECT);
4d891523 953 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
954 /*
955 * LVDS discovery:
956 * 1) check for EDID on DDC
957 * 2) check for VBT data
958 * 3) check to see if LVDS is already on
959 * if none of the above, no panel
960 * 4) make sure lid is open
961 * if closed, act like it's not there for now
962 */
963
79e53945
JB
964 /*
965 * Attempt to get the fixed panel mode from DDC. Assume that the
966 * preferred mode is the right one.
967 */
9cd300e0
JN
968 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
969 if (edid) {
970 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 971 drm_mode_connector_update_edid_property(connector,
9cd300e0 972 edid);
3f8ff0e7 973 } else {
9cd300e0
JN
974 kfree(edid);
975 edid = ERR_PTR(-EINVAL);
3f8ff0e7 976 }
9cd300e0
JN
977 } else {
978 edid = ERR_PTR(-ENOENT);
3f8ff0e7 979 }
9cd300e0
JN
980 lvds_connector->base.edid = edid;
981
982 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
983 /* Didn't get an EDID, so
984 * Set wide sync ranges so we get all modes
985 * handed to valid_mode for checking
986 */
987 connector->display_info.min_vfreq = 0;
988 connector->display_info.max_vfreq = 200;
989 connector->display_info.min_hfreq = 0;
990 connector->display_info.max_hfreq = 200;
991 }
79e53945
JB
992
993 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 994 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
995 DRM_DEBUG_KMS("using preferred mode from EDID: ");
996 drm_mode_debug_printmodeline(scan);
997
dd06f90e 998 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
999 if (fixed_mode) {
1000 intel_find_lvds_downclock(dev, fixed_mode,
1001 connector);
1002 goto out;
1003 }
79e53945 1004 }
79e53945
JB
1005 }
1006
1007 /* Failed to get EDID, what about VBT? */
88631706 1008 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1009 DRM_DEBUG_KMS("using mode from VBT: ");
1010 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1011
dd06f90e
JN
1012 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1013 if (fixed_mode) {
1014 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1015 goto out;
1016 }
79e53945
JB
1017 }
1018
1019 /*
1020 * If we didn't get EDID, try checking if the panel is already turned
1021 * on. If so, assume that whatever is currently programmed is the
1022 * correct mode.
1023 */
541998a1 1024
f2b115e6 1025 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1026 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1027 goto failed;
1028
79e53945
JB
1029 lvds = I915_READ(LVDS);
1030 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1031 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1032
1033 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1034 fixed_mode = intel_crtc_mode_get(dev, crtc);
1035 if (fixed_mode) {
6a9d51b7
CW
1036 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1037 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1038 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1039 goto out;
79e53945
JB
1040 }
1041 }
1042
1043 /* If we still don't have a mode after all that, give up. */
dd06f90e 1044 if (!fixed_mode)
79e53945
JB
1045 goto failed;
1046
79e53945 1047out:
7dec0606 1048 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1049 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1050 lvds_encoder->is_dual_link ? "dual" : "single");
1051
24ded204
DV
1052 /*
1053 * Unlock registers and just
1054 * leave them unlocked
1055 */
c619eed4 1056 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1057 I915_WRITE(PCH_PP_CONTROL,
1058 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1059 } else {
ed10fca9
KP
1060 I915_WRITE(PP_CONTROL,
1061 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1062 }
db1740a0
JN
1063 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1064 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1065 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1066 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1067 }
79e53945 1068 drm_sysfs_connector_add(connector);
aaa6fd2a 1069
dd06f90e 1070 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1071 intel_panel_setup_backlight(connector);
aaa6fd2a 1072
c5d1b51d 1073 return true;
79e53945
JB
1074
1075failed:
8a4c47f3 1076 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1077 drm_connector_cleanup(connector);
1991bdfa 1078 drm_encoder_cleanup(encoder);
dd06f90e
JN
1079 if (fixed_mode)
1080 drm_mode_destroy(dev, fixed_mode);
29b99b48 1081 kfree(lvds_encoder);
c7362c4d 1082 kfree(lvds_connector);
c5d1b51d 1083 return false;
79e53945 1084}