]>
Commit | Line | Data |
---|---|---|
79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
4eddaeec | 34 | #include <linux/vga_switcheroo.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_edid.h> | |
79e53945 | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
79e53945 | 41 | #include "i915_drv.h" |
e99da35f | 42 | #include <linux/acpi.h> |
79e53945 | 43 | |
3fbe18d6 | 44 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
45 | struct intel_lvds_connector { |
46 | struct intel_connector base; | |
788319d4 | 47 | |
db1740a0 | 48 | struct notifier_block lid_notifier; |
c7362c4d JN |
49 | }; |
50 | ||
ed6143b8 ID |
51 | struct intel_lvds_pps { |
52 | /* 100us units */ | |
53 | int t1_t2; | |
54 | int t3; | |
55 | int t4; | |
56 | int t5; | |
57 | int tx; | |
58 | ||
59 | int divider; | |
60 | ||
61 | int port; | |
62 | bool powerdown_on_reset; | |
63 | }; | |
64 | ||
29b99b48 | 65 | struct intel_lvds_encoder { |
ea5b213a | 66 | struct intel_encoder base; |
788319d4 | 67 | |
13c7d870 | 68 | bool is_dual_link; |
f0f59a00 | 69 | i915_reg_t reg; |
1f835a77 | 70 | u32 a3_power; |
788319d4 | 71 | |
ed6143b8 ID |
72 | struct intel_lvds_pps init_pps; |
73 | u32 init_lvds_val; | |
74 | ||
62165e0d | 75 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
76 | }; |
77 | ||
29b99b48 | 78 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 79 | { |
29b99b48 | 80 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
81 | } |
82 | ||
c7362c4d | 83 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 84 | { |
c7362c4d | 85 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
86 | } |
87 | ||
b1dc332c DV |
88 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
89 | enum pipe *pipe) | |
90 | { | |
91 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 92 | struct drm_i915_private *dev_priv = to_i915(dev); |
7dec0606 DV |
93 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
94 | u32 tmp; | |
ecb24482 | 95 | bool ret; |
b1dc332c | 96 | |
79f255a0 ACO |
97 | if (!intel_display_power_get_if_enabled(dev_priv, |
98 | encoder->power_domain)) | |
34a6c70f PZ |
99 | return false; |
100 | ||
ecb24482 ID |
101 | ret = false; |
102 | ||
7dec0606 | 103 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
104 | |
105 | if (!(tmp & LVDS_PORT_EN)) | |
ecb24482 | 106 | goto out; |
b1dc332c | 107 | |
6e266956 | 108 | if (HAS_PCH_CPT(dev_priv)) |
b1dc332c DV |
109 | *pipe = PORT_TO_PIPE_CPT(tmp); |
110 | else | |
111 | *pipe = PORT_TO_PIPE(tmp); | |
112 | ||
ecb24482 ID |
113 | ret = true; |
114 | ||
115 | out: | |
79f255a0 | 116 | intel_display_power_put(dev_priv, encoder->power_domain); |
ecb24482 ID |
117 | |
118 | return ret; | |
b1dc332c DV |
119 | } |
120 | ||
045ac3b5 | 121 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
5cec258b | 122 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 123 | { |
66478475 | 124 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d0669d00 VS |
125 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
126 | u32 tmp, flags = 0; | |
045ac3b5 | 127 | |
d0669d00 | 128 | tmp = I915_READ(lvds_encoder->reg); |
045ac3b5 JB |
129 | if (tmp & LVDS_HSYNC_POLARITY) |
130 | flags |= DRM_MODE_FLAG_NHSYNC; | |
131 | else | |
132 | flags |= DRM_MODE_FLAG_PHSYNC; | |
133 | if (tmp & LVDS_VSYNC_POLARITY) | |
134 | flags |= DRM_MODE_FLAG_NVSYNC; | |
135 | else | |
136 | flags |= DRM_MODE_FLAG_PVSYNC; | |
137 | ||
2d112de7 | 138 | pipe_config->base.adjusted_mode.flags |= flags; |
06922821 | 139 | |
66478475 | 140 | if (INTEL_GEN(dev_priv) < 5) |
a0cbe6a3 JN |
141 | pipe_config->gmch_pfit.lvds_border_bits = |
142 | tmp & LVDS_BORDER_ENABLE; | |
143 | ||
6b89cdde | 144 | /* gen2/3 store dither state in pfit control, needs to match */ |
66478475 | 145 | if (INTEL_GEN(dev_priv) < 4) { |
6b89cdde DV |
146 | tmp = I915_READ(PFIT_CONTROL); |
147 | ||
148 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
149 | } | |
150 | ||
e3b247da | 151 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
152 | } |
153 | ||
ed6143b8 ID |
154 | static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, |
155 | struct intel_lvds_pps *pps) | |
156 | { | |
157 | u32 val; | |
158 | ||
159 | pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; | |
160 | ||
161 | val = I915_READ(PP_ON_DELAYS(0)); | |
162 | pps->port = (val & PANEL_PORT_SELECT_MASK) >> | |
163 | PANEL_PORT_SELECT_SHIFT; | |
164 | pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> | |
165 | PANEL_POWER_UP_DELAY_SHIFT; | |
166 | pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> | |
167 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
168 | ||
169 | val = I915_READ(PP_OFF_DELAYS(0)); | |
170 | pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> | |
171 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
172 | pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
173 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
174 | ||
175 | val = I915_READ(PP_DIVISOR(0)); | |
176 | pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> | |
177 | PP_REFERENCE_DIVIDER_SHIFT; | |
178 | val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
179 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
180 | /* | |
181 | * Remove the BSpec specified +1 (100ms) offset that accounts for a | |
182 | * too short power-cycle delay due to the asynchronous programming of | |
183 | * the register. | |
184 | */ | |
185 | if (val) | |
186 | val--; | |
187 | /* Convert from 100ms to 100us units */ | |
188 | pps->t4 = val * 1000; | |
189 | ||
190 | if (INTEL_INFO(dev_priv)->gen <= 4 && | |
191 | pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { | |
192 | DRM_DEBUG_KMS("Panel power timings uninitialized, " | |
193 | "setting defaults\n"); | |
194 | /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ | |
195 | pps->t1_t2 = 40 * 10; | |
196 | pps->t5 = 200 * 10; | |
197 | /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ | |
198 | pps->t3 = 35 * 10; | |
199 | pps->tx = 200 * 10; | |
200 | } | |
201 | ||
202 | DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " | |
203 | "divider %d port %d powerdown_on_reset %d\n", | |
204 | pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, | |
205 | pps->divider, pps->port, pps->powerdown_on_reset); | |
206 | } | |
207 | ||
208 | static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, | |
209 | struct intel_lvds_pps *pps) | |
210 | { | |
211 | u32 val; | |
212 | ||
213 | val = I915_READ(PP_CONTROL(0)); | |
214 | WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); | |
215 | if (pps->powerdown_on_reset) | |
216 | val |= PANEL_POWER_RESET; | |
217 | I915_WRITE(PP_CONTROL(0), val); | |
218 | ||
219 | I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | | |
220 | (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | | |
221 | (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); | |
222 | I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | | |
223 | (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); | |
224 | ||
225 | val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; | |
226 | val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << | |
227 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
228 | I915_WRITE(PP_DIVISOR(0), val); | |
229 | } | |
230 | ||
fd6bbda9 ML |
231 | static void intel_pre_enable_lvds(struct intel_encoder *encoder, |
232 | struct intel_crtc_state *pipe_config, | |
233 | struct drm_connector_state *conn_state) | |
fc683091 DV |
234 | { |
235 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
d468e21e ML |
236 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
237 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); | |
238 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
55607e8a | 239 | int pipe = crtc->pipe; |
fc683091 DV |
240 | u32 temp; |
241 | ||
d468e21e | 242 | if (HAS_PCH_SPLIT(dev_priv)) { |
55607e8a DV |
243 | assert_fdi_rx_pll_disabled(dev_priv, pipe); |
244 | assert_shared_dpll_disabled(dev_priv, | |
d468e21e | 245 | pipe_config->shared_dpll); |
55607e8a DV |
246 | } else { |
247 | assert_pll_disabled(dev_priv, pipe); | |
248 | } | |
249 | ||
ed6143b8 ID |
250 | intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); |
251 | ||
252 | temp = lvds_encoder->init_lvds_val; | |
fc683091 | 253 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
62810e5a | 254 | |
d468e21e | 255 | if (HAS_PCH_CPT(dev_priv)) { |
62810e5a DV |
256 | temp &= ~PORT_TRANS_SEL_MASK; |
257 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 258 | } else { |
62810e5a DV |
259 | if (pipe == 1) { |
260 | temp |= LVDS_PIPEB_SELECT; | |
261 | } else { | |
262 | temp &= ~LVDS_PIPEB_SELECT; | |
263 | } | |
fc683091 | 264 | } |
62810e5a | 265 | |
fc683091 | 266 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 267 | temp &= ~LVDS_BORDER_ENABLE; |
d468e21e | 268 | temp |= pipe_config->gmch_pfit.lvds_border_bits; |
fc683091 DV |
269 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
270 | * set the DPLLs for dual-channel mode or not. | |
271 | */ | |
272 | if (lvds_encoder->is_dual_link) | |
273 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
274 | else | |
275 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
276 | ||
277 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
278 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
279 | * panels behave in the two modes. For now, let's just maintain the |
280 | * value we got from the BIOS. | |
fc683091 | 281 | */ |
f1fda745 CW |
282 | temp &= ~LVDS_A3_POWER_MASK; |
283 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
284 | |
285 | /* Set the dithering flag on LVDS as needed, note that there is no | |
286 | * special lvds dither control bit on pch-split platforms, dithering is | |
287 | * only controlled through the PIPECONF reg. */ | |
7e22dbbb | 288 | if (IS_GEN4(dev_priv)) { |
d8b32247 DV |
289 | /* Bspec wording suggests that LVDS port dithering only exists |
290 | * for 18bpp panels. */ | |
d468e21e | 291 | if (pipe_config->dither && pipe_config->pipe_bpp == 18) |
fc683091 DV |
292 | temp |= LVDS_ENABLE_DITHER; |
293 | else | |
294 | temp &= ~LVDS_ENABLE_DITHER; | |
295 | } | |
296 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 297 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 298 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 299 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
300 | temp |= LVDS_VSYNC_POLARITY; |
301 | ||
302 | I915_WRITE(lvds_encoder->reg, temp); | |
303 | } | |
304 | ||
79e53945 JB |
305 | /** |
306 | * Sets the power state for the panel. | |
307 | */ | |
fd6bbda9 ML |
308 | static void intel_enable_lvds(struct intel_encoder *encoder, |
309 | struct intel_crtc_state *pipe_config, | |
310 | struct drm_connector_state *conn_state) | |
79e53945 | 311 | { |
c22834ec | 312 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 313 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
314 | struct intel_connector *intel_connector = |
315 | &lvds_encoder->attached_connector->base; | |
fac5e23e | 316 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 317 | |
7dec0606 | 318 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 319 | |
5a162e22 | 320 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); |
7dec0606 | 321 | POSTING_READ(lvds_encoder->reg); |
44cb734c | 322 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) |
de842eff | 323 | DRM_ERROR("timed out waiting for panel to power on\n"); |
2a1292fd | 324 | |
752aa88a | 325 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
326 | } |
327 | ||
fd6bbda9 ML |
328 | static void intel_disable_lvds(struct intel_encoder *encoder, |
329 | struct intel_crtc_state *old_crtc_state, | |
330 | struct drm_connector_state *old_conn_state) | |
2a1292fd | 331 | { |
29b99b48 | 332 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
d468e21e | 333 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2a1292fd | 334 | |
5a162e22 | 335 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); |
44cb734c | 336 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) |
de842eff | 337 | DRM_ERROR("timed out waiting for panel to power off\n"); |
2a1292fd | 338 | |
7dec0606 DV |
339 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
340 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
341 | } |
342 | ||
fd6bbda9 ML |
343 | static void gmch_disable_lvds(struct intel_encoder *encoder, |
344 | struct intel_crtc_state *old_crtc_state, | |
345 | struct drm_connector_state *old_conn_state) | |
346 | ||
d26a5b6e VS |
347 | { |
348 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
349 | struct intel_connector *intel_connector = | |
350 | &lvds_encoder->attached_connector->base; | |
351 | ||
352 | intel_panel_disable_backlight(intel_connector); | |
353 | ||
fd6bbda9 | 354 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); |
d26a5b6e VS |
355 | } |
356 | ||
fd6bbda9 ML |
357 | static void pch_disable_lvds(struct intel_encoder *encoder, |
358 | struct intel_crtc_state *old_crtc_state, | |
359 | struct drm_connector_state *old_conn_state) | |
d26a5b6e VS |
360 | { |
361 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
362 | struct intel_connector *intel_connector = | |
363 | &lvds_encoder->attached_connector->base; | |
364 | ||
365 | intel_panel_disable_backlight(intel_connector); | |
366 | } | |
367 | ||
fd6bbda9 ML |
368 | static void pch_post_disable_lvds(struct intel_encoder *encoder, |
369 | struct intel_crtc_state *old_crtc_state, | |
370 | struct drm_connector_state *old_conn_state) | |
d26a5b6e | 371 | { |
fd6bbda9 | 372 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); |
d26a5b6e VS |
373 | } |
374 | ||
c19de8eb DL |
375 | static enum drm_mode_status |
376 | intel_lvds_mode_valid(struct drm_connector *connector, | |
377 | struct drm_display_mode *mode) | |
79e53945 | 378 | { |
dd06f90e JN |
379 | struct intel_connector *intel_connector = to_intel_connector(connector); |
380 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
7f7b58cc | 381 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; |
79e53945 | 382 | |
788319d4 CW |
383 | if (mode->hdisplay > fixed_mode->hdisplay) |
384 | return MODE_PANEL; | |
385 | if (mode->vdisplay > fixed_mode->vdisplay) | |
386 | return MODE_PANEL; | |
7f7b58cc MK |
387 | if (fixed_mode->clock > max_pixclk) |
388 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
389 | |
390 | return MODE_OK; | |
391 | } | |
392 | ||
7ae89233 | 393 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
0a478c27 ML |
394 | struct intel_crtc_state *pipe_config, |
395 | struct drm_connector_state *conn_state) | |
79e53945 | 396 | { |
6e266956 | 397 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
7ae89233 DV |
398 | struct intel_lvds_encoder *lvds_encoder = |
399 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
400 | struct intel_connector *intel_connector = |
401 | &lvds_encoder->attached_connector->base; | |
2d112de7 | 402 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d21bd67b | 403 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e53c2e0 | 404 | unsigned int lvds_bpp; |
79e53945 JB |
405 | |
406 | /* Should never happen!! */ | |
6e266956 | 407 | if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 408 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
409 | return false; |
410 | } | |
411 | ||
1f835a77 | 412 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
413 | lvds_bpp = 8*3; |
414 | else | |
415 | lvds_bpp = 6*3; | |
416 | ||
e29c22c0 | 417 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
418 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
419 | pipe_config->pipe_bpp, lvds_bpp); | |
420 | pipe_config->pipe_bpp = lvds_bpp; | |
421 | } | |
d8b32247 | 422 | |
79e53945 | 423 | /* |
71677043 | 424 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
425 | * to the adjusted mode. The CRTC will be set up for this mode, |
426 | * with the panel scaling set up to source from the H/VDisplay | |
427 | * of the original mode. | |
428 | */ | |
4d891523 | 429 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 430 | adjusted_mode); |
1d8e1c75 | 431 | |
6e266956 | 432 | if (HAS_PCH_SPLIT(dev_priv)) { |
5bfe2ac0 DV |
433 | pipe_config->has_pch_encoder = true; |
434 | ||
b074cec8 | 435 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
eead06df | 436 | conn_state->scaling_mode); |
2dd24552 JB |
437 | } else { |
438 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
eead06df | 439 | conn_state->scaling_mode); |
79e53945 | 440 | |
21d8a475 | 441 | } |
f9bef081 | 442 | |
79e53945 JB |
443 | /* |
444 | * XXX: It would be nice to support lower refresh rates on the | |
445 | * panels to reduce power consumption, and perhaps match the | |
446 | * user's requested refresh rate. | |
447 | */ | |
448 | ||
449 | return true; | |
450 | } | |
451 | ||
79e53945 JB |
452 | /** |
453 | * Detect the LVDS connection. | |
454 | * | |
b42d4c5c JB |
455 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
456 | * connected and closed means disconnected. We also send hotplug events as | |
457 | * needed, using lid status notification from the input layer. | |
79e53945 | 458 | */ |
7b334fcb | 459 | static enum drm_connector_status |
930a9e28 | 460 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 461 | { |
1650be74 | 462 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
6ee3b5a1 | 463 | enum drm_connector_status status; |
b42d4c5c | 464 | |
164c8598 | 465 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 466 | connector->base.id, connector->name); |
164c8598 | 467 | |
1650be74 | 468 | status = intel_panel_detect(dev_priv); |
fe16d949 CW |
469 | if (status != connector_status_unknown) |
470 | return status; | |
01fe9dbd | 471 | |
6ee3b5a1 | 472 | return connector_status_connected; |
79e53945 JB |
473 | } |
474 | ||
475 | /** | |
476 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
477 | */ | |
478 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
479 | { | |
62165e0d | 480 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 481 | struct drm_device *dev = connector->dev; |
788319d4 | 482 | struct drm_display_mode *mode; |
79e53945 | 483 | |
9cd300e0 | 484 | /* use cached edid if we have one */ |
2aa4f099 | 485 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 486 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 487 | |
dd06f90e | 488 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 489 | if (mode == NULL) |
788319d4 | 490 | return 0; |
79e53945 | 491 | |
788319d4 CW |
492 | drm_mode_probed_add(connector, mode); |
493 | return 1; | |
79e53945 JB |
494 | } |
495 | ||
0544edfd TB |
496 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
497 | { | |
bc0daf48 | 498 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
499 | return 1; |
500 | } | |
501 | ||
502 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
503 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
504 | { | |
505 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
506 | .ident = "Toshiba Tecra A11", | |
507 | .matches = { | |
508 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
509 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
510 | }, | |
511 | }, | |
512 | ||
513 | { } /* terminating entry */ | |
514 | }; | |
515 | ||
c9354c85 | 516 | /* |
b8efb17b ZR |
517 | * Lid events. Note the use of 'modeset': |
518 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
519 | * and set it to MODESET_DONE on open | |
c9354c85 | 520 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
521 | * duplicate events where it was already properly set) |
522 | * - the suspend/resume paths will set it to | |
523 | * MODESET_SUSPENDED and ignore the lid open event, | |
524 | * because they restore the mode ("lid open"). | |
c9354c85 | 525 | */ |
c1c7af60 JB |
526 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
527 | void *unused) | |
528 | { | |
db1740a0 JN |
529 | struct intel_lvds_connector *lvds_connector = |
530 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
531 | struct drm_connector *connector = &lvds_connector->base.base; | |
532 | struct drm_device *dev = connector->dev; | |
fac5e23e | 533 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1c7af60 | 534 | |
2fb4e61d AW |
535 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
536 | return NOTIFY_OK; | |
537 | ||
b8efb17b ZR |
538 | mutex_lock(&dev_priv->modeset_restore_lock); |
539 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
540 | goto exit; | |
a2565377 ZY |
541 | /* |
542 | * check and update the status of LVDS connector after receiving | |
543 | * the LID nofication event. | |
544 | */ | |
db1740a0 | 545 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 546 | |
0544edfd TB |
547 | /* Don't force modeset on machines where it causes a GPU lockup */ |
548 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 549 | goto exit; |
c9354c85 | 550 | if (!acpi_lid_open()) { |
b8efb17b ZR |
551 | /* do modeset on next lid open event */ |
552 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
553 | goto exit; | |
06891e27 | 554 | } |
c1c7af60 | 555 | |
b8efb17b ZR |
556 | if (dev_priv->modeset_restore == MODESET_DONE) |
557 | goto exit; | |
c9354c85 | 558 | |
5be19d91 DV |
559 | /* |
560 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
561 | * We try to detect this here and undo any damage. The split for PCH | |
562 | * platforms is rather conservative and a bit arbitrary expect that on | |
563 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
564 | * and as part of the cleanup in the hw state restore we also redisable | |
565 | * the vga plane. | |
566 | */ | |
6e266956 | 567 | if (!HAS_PCH_SPLIT(dev_priv)) |
043e9bda | 568 | intel_display_resume(dev); |
06324194 | 569 | |
b8efb17b ZR |
570 | dev_priv->modeset_restore = MODESET_DONE; |
571 | ||
572 | exit: | |
573 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
574 | return NOTIFY_OK; |
575 | } | |
576 | ||
79e53945 JB |
577 | /** |
578 | * intel_lvds_destroy - unregister and free LVDS structures | |
579 | * @connector: connector to free | |
580 | * | |
581 | * Unregister the DDC bus for this connector then free the driver private | |
582 | * structure. | |
583 | */ | |
584 | static void intel_lvds_destroy(struct drm_connector *connector) | |
585 | { | |
db1740a0 JN |
586 | struct intel_lvds_connector *lvds_connector = |
587 | to_lvds_connector(connector); | |
79e53945 | 588 | |
db1740a0 JN |
589 | if (lvds_connector->lid_notifier.notifier_call) |
590 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 591 | |
9cd300e0 JN |
592 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
593 | kfree(lvds_connector->base.edid); | |
594 | ||
1d508706 | 595 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 596 | |
79e53945 JB |
597 | drm_connector_cleanup(connector); |
598 | kfree(connector); | |
599 | } | |
600 | ||
79e53945 JB |
601 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
602 | .get_modes = intel_lvds_get_modes, | |
603 | .mode_valid = intel_lvds_mode_valid, | |
ca937582 | 604 | .atomic_check = intel_digital_connector_atomic_check, |
79e53945 JB |
605 | }; |
606 | ||
607 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
4d688a2a | 608 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
609 | .detect = intel_lvds_detect, |
610 | .fill_modes = drm_helper_probe_single_connector_modes, | |
ca937582 ML |
611 | .set_property = drm_atomic_helper_connector_set_property, |
612 | .atomic_get_property = intel_digital_connector_atomic_get_property, | |
613 | .atomic_set_property = intel_digital_connector_atomic_set_property, | |
1ebaa0b9 | 614 | .late_register = intel_connector_register, |
c191eca1 | 615 | .early_unregister = intel_connector_unregister, |
79e53945 | 616 | .destroy = intel_lvds_destroy, |
c6f95f27 | 617 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
ca937582 | 618 | .atomic_duplicate_state = intel_digital_connector_duplicate_state, |
79e53945 JB |
619 | }; |
620 | ||
79e53945 | 621 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 622 | .destroy = intel_encoder_destroy, |
79e53945 JB |
623 | }; |
624 | ||
bbe1c274 | 625 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 626 | { |
bc0daf48 | 627 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
628 | return 1; |
629 | } | |
79e53945 | 630 | |
425d244c | 631 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 632 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
633 | { |
634 | .callback = intel_no_lvds_dmi_callback, | |
635 | .ident = "Apple Mac Mini (Core series)", | |
636 | .matches = { | |
98acd46f | 637 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
638 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
639 | }, | |
640 | }, | |
641 | { | |
642 | .callback = intel_no_lvds_dmi_callback, | |
643 | .ident = "Apple Mac Mini (Core 2 series)", | |
644 | .matches = { | |
98acd46f | 645 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
646 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
647 | }, | |
648 | }, | |
649 | { | |
650 | .callback = intel_no_lvds_dmi_callback, | |
651 | .ident = "MSI IM-945GSE-A", | |
652 | .matches = { | |
653 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
654 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
655 | }, | |
656 | }, | |
657 | { | |
658 | .callback = intel_no_lvds_dmi_callback, | |
659 | .ident = "Dell Studio Hybrid", | |
660 | .matches = { | |
661 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
662 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
663 | }, | |
664 | }, | |
70aa96ca JW |
665 | { |
666 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
667 | .ident = "Dell OptiPlex FX170", |
668 | .matches = { | |
669 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
670 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
671 | }, | |
672 | }, | |
673 | { | |
674 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
675 | .ident = "AOpen Mini PC", |
676 | .matches = { | |
677 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
678 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
679 | }, | |
680 | }, | |
ed8c754b TV |
681 | { |
682 | .callback = intel_no_lvds_dmi_callback, | |
683 | .ident = "AOpen Mini PC MP915", | |
684 | .matches = { | |
685 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
686 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
687 | }, | |
688 | }, | |
22ab70d3 KP |
689 | { |
690 | .callback = intel_no_lvds_dmi_callback, | |
691 | .ident = "AOpen i915GMm-HFS", | |
692 | .matches = { | |
693 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
694 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
695 | }, | |
696 | }, | |
e57b6886 DV |
697 | { |
698 | .callback = intel_no_lvds_dmi_callback, | |
699 | .ident = "AOpen i45GMx-I", | |
700 | .matches = { | |
701 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
702 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
703 | }, | |
704 | }, | |
fa0864b2 MC |
705 | { |
706 | .callback = intel_no_lvds_dmi_callback, | |
707 | .ident = "Aopen i945GTt-VFA", | |
708 | .matches = { | |
709 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
710 | }, | |
711 | }, | |
9875557e SB |
712 | { |
713 | .callback = intel_no_lvds_dmi_callback, | |
714 | .ident = "Clientron U800", | |
715 | .matches = { | |
716 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
717 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
718 | }, | |
719 | }, | |
6a574b5b | 720 | { |
44306ab3 JS |
721 | .callback = intel_no_lvds_dmi_callback, |
722 | .ident = "Clientron E830", | |
723 | .matches = { | |
724 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
725 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
726 | }, | |
727 | }, | |
728 | { | |
6a574b5b HG |
729 | .callback = intel_no_lvds_dmi_callback, |
730 | .ident = "Asus EeeBox PC EB1007", | |
731 | .matches = { | |
732 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
733 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
734 | }, | |
735 | }, | |
0999bbe0 AJ |
736 | { |
737 | .callback = intel_no_lvds_dmi_callback, | |
738 | .ident = "Asus AT5NM10T-I", | |
739 | .matches = { | |
740 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
741 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
742 | }, | |
743 | }, | |
33471119 JBG |
744 | { |
745 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 746 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
747 | .matches = { |
748 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 749 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
750 | }, |
751 | }, | |
f5b8a7ed MG |
752 | { |
753 | .callback = intel_no_lvds_dmi_callback, | |
754 | .ident = "Hewlett-Packard t5745", | |
755 | .matches = { | |
756 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 757 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
758 | }, |
759 | }, | |
760 | { | |
761 | .callback = intel_no_lvds_dmi_callback, | |
762 | .ident = "Hewlett-Packard st5747", | |
763 | .matches = { | |
764 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 765 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
766 | }, |
767 | }, | |
97effadb AA |
768 | { |
769 | .callback = intel_no_lvds_dmi_callback, | |
770 | .ident = "MSI Wind Box DC500", | |
771 | .matches = { | |
772 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
773 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
774 | }, | |
775 | }, | |
a51d4ed0 CW |
776 | { |
777 | .callback = intel_no_lvds_dmi_callback, | |
778 | .ident = "Gigabyte GA-D525TUD", | |
779 | .matches = { | |
780 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
781 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
782 | }, | |
783 | }, | |
c31407a3 CW |
784 | { |
785 | .callback = intel_no_lvds_dmi_callback, | |
786 | .ident = "Supermicro X7SPA-H", | |
787 | .matches = { | |
788 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
789 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
790 | }, | |
791 | }, | |
9e9dd0e8 CL |
792 | { |
793 | .callback = intel_no_lvds_dmi_callback, | |
794 | .ident = "Fujitsu Esprimo Q900", | |
795 | .matches = { | |
796 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
797 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
798 | }, | |
799 | }, | |
645378d8 RP |
800 | { |
801 | .callback = intel_no_lvds_dmi_callback, | |
802 | .ident = "Intel D410PT", | |
803 | .matches = { | |
804 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
805 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
806 | }, | |
807 | }, | |
808 | { | |
809 | .callback = intel_no_lvds_dmi_callback, | |
810 | .ident = "Intel D425KT", | |
811 | .matches = { | |
812 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
813 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
814 | }, | |
815 | }, | |
e5614f0c CW |
816 | { |
817 | .callback = intel_no_lvds_dmi_callback, | |
818 | .ident = "Intel D510MO", | |
819 | .matches = { | |
820 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
821 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
822 | }, | |
823 | }, | |
dcf6d294 JN |
824 | { |
825 | .callback = intel_no_lvds_dmi_callback, | |
826 | .ident = "Intel D525MW", | |
827 | .matches = { | |
828 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
829 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
830 | }, | |
831 | }, | |
425d244c JW |
832 | |
833 | { } /* terminating entry */ | |
834 | }; | |
79e53945 | 835 | |
1974cad0 DV |
836 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
837 | { | |
838 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
839 | return 1; | |
840 | } | |
841 | ||
842 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
843 | { | |
844 | .callback = intel_dual_link_lvds_callback, | |
3916e3fd LW |
845 | .ident = "Apple MacBook Pro 15\" (2010)", |
846 | .matches = { | |
847 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
848 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
849 | }, | |
850 | }, | |
851 | { | |
852 | .callback = intel_dual_link_lvds_callback, | |
853 | .ident = "Apple MacBook Pro 15\" (2011)", | |
1974cad0 DV |
854 | .matches = { |
855 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
856 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
857 | }, | |
858 | }, | |
3916e3fd LW |
859 | { |
860 | .callback = intel_dual_link_lvds_callback, | |
861 | .ident = "Apple MacBook Pro 15\" (2012)", | |
862 | .matches = { | |
863 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
864 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
865 | }, | |
866 | }, | |
1974cad0 DV |
867 | { } /* terminating entry */ |
868 | }; | |
869 | ||
97a824e1 | 870 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) |
13c7d870 | 871 | { |
97a824e1 | 872 | struct intel_encoder *intel_encoder; |
13c7d870 | 873 | |
97a824e1 ID |
874 | for_each_intel_encoder(dev, intel_encoder) |
875 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
876 | return intel_encoder; | |
13c7d870 | 877 | |
97a824e1 ID |
878 | return NULL; |
879 | } | |
880 | ||
881 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
882 | { | |
883 | struct intel_encoder *encoder = intel_get_lvds_encoder(dev); | |
13c7d870 | 884 | |
97a824e1 | 885 | return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; |
13c7d870 DV |
886 | } |
887 | ||
7dec0606 | 888 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 889 | { |
7dec0606 | 890 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 | 891 | unsigned int val; |
fac5e23e | 892 | struct drm_i915_private *dev_priv = to_i915(dev); |
1974cad0 DV |
893 | |
894 | /* use the module option value if specified */ | |
d330a953 JN |
895 | if (i915.lvds_channel_mode > 0) |
896 | return i915.lvds_channel_mode == 2; | |
1974cad0 | 897 | |
6f317cfe LW |
898 | /* single channel LVDS is limited to 112 MHz */ |
899 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
900 | > 112999) | |
901 | return true; | |
902 | ||
1974cad0 DV |
903 | if (dmi_check_system(intel_dual_link_lvds)) |
904 | return true; | |
905 | ||
13c7d870 DV |
906 | /* BIOS should set the proper LVDS register value at boot, but |
907 | * in reality, it doesn't set the value when the lid is closed; | |
908 | * we need to check "the value to be set" in VBT when LVDS | |
909 | * register is uninitialized. | |
910 | */ | |
7dec0606 | 911 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 912 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 913 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 914 | |
1974cad0 DV |
915 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
916 | } | |
917 | ||
50a0bc90 | 918 | static bool intel_lvds_supported(struct drm_i915_private *dev_priv) |
f3cfcba6 CW |
919 | { |
920 | /* With the introduction of the PCH we gained a dedicated | |
921 | * LVDS presence pin, use it. */ | |
6e266956 | 922 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
f3cfcba6 CW |
923 | return true; |
924 | ||
925 | /* Otherwise LVDS was only attached to mobile products, | |
926 | * except for the inglorious 830gm */ | |
50a0bc90 TU |
927 | if (INTEL_GEN(dev_priv) <= 4 && |
928 | IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) | |
311e359c PZ |
929 | return true; |
930 | ||
931 | return false; | |
f3cfcba6 CW |
932 | } |
933 | ||
79e53945 JB |
934 | /** |
935 | * intel_lvds_init - setup LVDS connectors on this device | |
936 | * @dev: drm device | |
937 | * | |
938 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
939 | * modes we can display on the LVDS panel (if present). | |
940 | */ | |
c39055b0 | 941 | void intel_lvds_init(struct drm_i915_private *dev_priv) |
79e53945 | 942 | { |
c39055b0 | 943 | struct drm_device *dev = &dev_priv->drm; |
29b99b48 | 944 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 945 | struct intel_encoder *intel_encoder; |
c7362c4d | 946 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 947 | struct intel_connector *intel_connector; |
79e53945 JB |
948 | struct drm_connector *connector; |
949 | struct drm_encoder *encoder; | |
950 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 951 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 952 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 953 | struct edid *edid; |
e2af48c6 | 954 | struct intel_crtc *crtc; |
f0f59a00 | 955 | i915_reg_t lvds_reg; |
79e53945 | 956 | u32 lvds; |
270eea0f CW |
957 | int pipe; |
958 | u8 pin; | |
8b45330a | 959 | u32 allowed_scalers; |
79e53945 | 960 | |
50a0bc90 | 961 | if (!intel_lvds_supported(dev_priv)) |
c9093354 | 962 | return; |
f3cfcba6 | 963 | |
425d244c JW |
964 | /* Skip init on machines we know falsely report LVDS */ |
965 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 966 | return; |
565dcd46 | 967 | |
6e266956 | 968 | if (HAS_PCH_SPLIT(dev_priv)) |
d0669d00 VS |
969 | lvds_reg = PCH_LVDS; |
970 | else | |
971 | lvds_reg = LVDS; | |
972 | ||
973 | lvds = I915_READ(lvds_reg); | |
974 | ||
6e266956 | 975 | if (HAS_PCH_SPLIT(dev_priv)) { |
d0669d00 | 976 | if ((lvds & LVDS_DETECTED) == 0) |
c9093354 | 977 | return; |
6aa23e65 | 978 | if (dev_priv->vbt.edp.support) { |
28c97730 | 979 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 980 | return; |
32f9d658 | 981 | } |
541998a1 ZW |
982 | } |
983 | ||
eebaed64 | 984 | pin = GMBUS_PIN_PANEL; |
5a69d13d | 985 | if (!intel_bios_is_lvds_present(dev_priv, &pin)) { |
d0669d00 | 986 | if ((lvds & LVDS_PORT_EN) == 0) { |
eebaed64 CW |
987 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
988 | return; | |
989 | } | |
990 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); | |
991 | } | |
992 | ||
b14c5679 | 993 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 994 | if (!lvds_encoder) |
c9093354 | 995 | return; |
79e53945 | 996 | |
b14c5679 | 997 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 998 | if (!lvds_connector) { |
29b99b48 | 999 | kfree(lvds_encoder); |
c9093354 | 1000 | return; |
bb8a3560 ZW |
1001 | } |
1002 | ||
9bdbd0b9 ACO |
1003 | if (intel_connector_init(&lvds_connector->base) < 0) { |
1004 | kfree(lvds_connector); | |
1005 | kfree(lvds_encoder); | |
1006 | return; | |
1007 | } | |
1008 | ||
62165e0d JN |
1009 | lvds_encoder->attached_connector = lvds_connector; |
1010 | ||
29b99b48 | 1011 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1012 | encoder = &intel_encoder->base; |
c7362c4d | 1013 | intel_connector = &lvds_connector->base; |
ea5b213a | 1014 | connector = &intel_connector->base; |
bb8a3560 | 1015 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1016 | DRM_MODE_CONNECTOR_LVDS); |
1017 | ||
4ef69c7a | 1018 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
580d8ed5 | 1019 | DRM_MODE_ENCODER_LVDS, "LVDS"); |
79e53945 | 1020 | |
c22834ec | 1021 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 1022 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 1023 | intel_encoder->compute_config = intel_lvds_compute_config; |
d26a5b6e VS |
1024 | if (HAS_PCH_SPLIT(dev_priv)) { |
1025 | intel_encoder->disable = pch_disable_lvds; | |
1026 | intel_encoder->post_disable = pch_post_disable_lvds; | |
1027 | } else { | |
1028 | intel_encoder->disable = gmch_disable_lvds; | |
1029 | } | |
b1dc332c | 1030 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 1031 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 1032 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
c22834ec | 1033 | |
df0e9248 | 1034 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 | 1035 | |
03cdc1d4 | 1036 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79f255a0 | 1037 | intel_encoder->power_domain = POWER_DOMAIN_PORT_OTHER; |
03cdc1d4 | 1038 | intel_encoder->port = PORT_NONE; |
bc079e8b | 1039 | intel_encoder->cloneable = 0; |
6e266956 | 1040 | if (HAS_PCH_SPLIT(dev_priv)) |
27f8227b | 1041 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
5db94019 | 1042 | else if (IS_GEN4(dev_priv)) |
0b9f43a0 | 1043 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
27f8227b JB |
1044 | else |
1045 | intel_encoder->crtc_mask = (1 << 1); | |
1046 | ||
79e53945 JB |
1047 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1048 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1049 | connector->interlace_allowed = false; | |
1050 | connector->doublescan_allowed = false; | |
1051 | ||
d0669d00 | 1052 | lvds_encoder->reg = lvds_reg; |
7dec0606 | 1053 | |
3fbe18d6 | 1054 | /* create the scaling mode property */ |
8b45330a ML |
1055 | allowed_scalers = BIT(DRM_MODE_SCALE_ASPECT); |
1056 | allowed_scalers |= BIT(DRM_MODE_SCALE_FULLSCREEN); | |
1057 | allowed_scalers |= BIT(DRM_MODE_SCALE_CENTER); | |
1058 | drm_connector_attach_scaling_mode_property(connector, allowed_scalers); | |
eead06df | 1059 | connector->state->scaling_mode = DRM_MODE_SCALE_ASPECT; |
ed6143b8 ID |
1060 | |
1061 | intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); | |
1062 | lvds_encoder->init_lvds_val = lvds; | |
1063 | ||
79e53945 JB |
1064 | /* |
1065 | * LVDS discovery: | |
1066 | * 1) check for EDID on DDC | |
1067 | * 2) check for VBT data | |
1068 | * 3) check to see if LVDS is already on | |
1069 | * if none of the above, no panel | |
1070 | * 4) make sure lid is open | |
1071 | * if closed, act like it's not there for now | |
1072 | */ | |
1073 | ||
79e53945 JB |
1074 | /* |
1075 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1076 | * preferred mode is the right one. | |
1077 | */ | |
4da98541 | 1078 | mutex_lock(&dev->mode_config.mutex); |
4eddaeec LW |
1079 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) |
1080 | edid = drm_get_edid_switcheroo(connector, | |
1081 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1082 | else | |
1083 | edid = drm_get_edid(connector, | |
1084 | intel_gmbus_get_adapter(dev_priv, pin)); | |
9cd300e0 JN |
1085 | if (edid) { |
1086 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1087 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1088 | edid); |
3f8ff0e7 | 1089 | } else { |
9cd300e0 JN |
1090 | kfree(edid); |
1091 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1092 | } |
9cd300e0 JN |
1093 | } else { |
1094 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1095 | } |
9cd300e0 JN |
1096 | lvds_connector->base.edid = edid; |
1097 | ||
79e53945 | 1098 | list_for_each_entry(scan, &connector->probed_modes, head) { |
79e53945 | 1099 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1100 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1101 | drm_mode_debug_printmodeline(scan); | |
1102 | ||
dd06f90e | 1103 | fixed_mode = drm_mode_duplicate(dev, scan); |
c329a4ec | 1104 | if (fixed_mode) |
6a9d51b7 | 1105 | goto out; |
79e53945 | 1106 | } |
79e53945 JB |
1107 | } |
1108 | ||
1109 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1110 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1111 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1112 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1113 | |
41aa3448 | 1114 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1115 | if (fixed_mode) { |
1116 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
df457245 VS |
1117 | connector->display_info.width_mm = fixed_mode->width_mm; |
1118 | connector->display_info.height_mm = fixed_mode->height_mm; | |
e285f3cd JB |
1119 | goto out; |
1120 | } | |
79e53945 JB |
1121 | } |
1122 | ||
1123 | /* | |
1124 | * If we didn't get EDID, try checking if the panel is already turned | |
1125 | * on. If so, assume that whatever is currently programmed is the | |
1126 | * correct mode. | |
1127 | */ | |
541998a1 | 1128 | |
f2b115e6 | 1129 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
6e266956 | 1130 | if (HAS_PCH_SPLIT(dev_priv)) |
541998a1 ZW |
1131 | goto failed; |
1132 | ||
79e53945 | 1133 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
b91eb5cc | 1134 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
79e53945 JB |
1135 | |
1136 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
e2af48c6 | 1137 | fixed_mode = intel_crtc_mode_get(dev, &crtc->base); |
dd06f90e | 1138 | if (fixed_mode) { |
6a9d51b7 CW |
1139 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1140 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1141 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1142 | goto out; |
79e53945 JB |
1143 | } |
1144 | } | |
1145 | ||
1146 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1147 | if (!fixed_mode) |
79e53945 JB |
1148 | goto failed; |
1149 | ||
79e53945 | 1150 | out: |
4da98541 DV |
1151 | mutex_unlock(&dev->mode_config.mutex); |
1152 | ||
6f317cfe | 1153 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
fda9ee98 | 1154 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
6f317cfe | 1155 | |
7dec0606 | 1156 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1157 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1158 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1159 | ||
af9b9c19 | 1160 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
1f835a77 | 1161 | |
db1740a0 JN |
1162 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1163 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1164 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1165 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1166 | } |
aaa6fd2a | 1167 | |
c9093354 | 1168 | return; |
79e53945 JB |
1169 | |
1170 | failed: | |
4da98541 DV |
1171 | mutex_unlock(&dev->mode_config.mutex); |
1172 | ||
8a4c47f3 | 1173 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1174 | drm_connector_cleanup(connector); |
1991bdfa | 1175 | drm_encoder_cleanup(encoder); |
29b99b48 | 1176 | kfree(lvds_encoder); |
c7362c4d | 1177 | kfree(lvds_connector); |
c9093354 | 1178 | return; |
79e53945 | 1179 | } |