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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
3fbe18d6 ZY |
52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | |
e9e331a8 | 54 | bool pfit_dirty; |
13c7d870 | 55 | bool is_dual_link; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
75 | u32 lvds_reg, tmp; | |
76 | ||
77 | if (HAS_PCH_SPLIT(dev)) { | |
78 | lvds_reg = PCH_LVDS; | |
79 | } else { | |
80 | lvds_reg = LVDS; | |
81 | } | |
82 | ||
83 | tmp = I915_READ(lvds_reg); | |
84 | ||
85 | if (!(tmp & LVDS_PORT_EN)) | |
86 | return false; | |
87 | ||
88 | if (HAS_PCH_CPT(dev)) | |
89 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
90 | else | |
91 | *pipe = PORT_TO_PIPE(tmp); | |
92 | ||
93 | return true; | |
94 | } | |
95 | ||
79e53945 JB |
96 | /** |
97 | * Sets the power state for the panel. | |
98 | */ | |
c22834ec | 99 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 100 | { |
c22834ec | 101 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 102 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 103 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 104 | struct drm_i915_private *dev_priv = dev->dev_private; |
de842eff | 105 | u32 ctl_reg, lvds_reg, stat_reg; |
541998a1 | 106 | |
c619eed4 | 107 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 108 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 109 | lvds_reg = PCH_LVDS; |
de842eff | 110 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
111 | } else { |
112 | ctl_reg = PP_CONTROL; | |
469d1296 | 113 | lvds_reg = LVDS; |
de842eff | 114 | stat_reg = PP_STATUS; |
541998a1 | 115 | } |
79e53945 | 116 | |
2a1292fd | 117 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
e9e331a8 | 118 | |
29b99b48 | 119 | if (lvds_encoder->pfit_dirty) { |
2a1292fd CW |
120 | /* |
121 | * Enable automatic panel scaling so that non-native modes | |
122 | * fill the screen. The panel fitter should only be | |
123 | * adjusted whilst the pipe is disabled, according to | |
124 | * register description and PRM. | |
125 | */ | |
126 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
29b99b48 JN |
127 | lvds_encoder->pfit_control, |
128 | lvds_encoder->pfit_pgm_ratios); | |
de842eff | 129 | |
29b99b48 JN |
130 | I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios); |
131 | I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control); | |
132 | lvds_encoder->pfit_dirty = false; | |
2a1292fd CW |
133 | } |
134 | ||
135 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); | |
136 | POSTING_READ(lvds_reg); | |
de842eff KP |
137 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
138 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 139 | |
24ded204 | 140 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
141 | } |
142 | ||
c22834ec | 143 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 144 | { |
c22834ec | 145 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 146 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 147 | struct drm_i915_private *dev_priv = dev->dev_private; |
de842eff | 148 | u32 ctl_reg, lvds_reg, stat_reg; |
2a1292fd CW |
149 | |
150 | if (HAS_PCH_SPLIT(dev)) { | |
151 | ctl_reg = PCH_PP_CONTROL; | |
152 | lvds_reg = PCH_LVDS; | |
de842eff | 153 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
154 | } else { |
155 | ctl_reg = PP_CONTROL; | |
156 | lvds_reg = LVDS; | |
de842eff | 157 | stat_reg = PP_STATUS; |
2a1292fd CW |
158 | } |
159 | ||
47356eb6 | 160 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
161 | |
162 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
163 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
164 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 165 | |
29b99b48 | 166 | if (lvds_encoder->pfit_control) { |
2a1292fd | 167 | I915_WRITE(PFIT_CONTROL, 0); |
29b99b48 | 168 | lvds_encoder->pfit_dirty = true; |
79e53945 | 169 | } |
2a1292fd CW |
170 | |
171 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
c9f9ccc1 | 172 | POSTING_READ(lvds_reg); |
79e53945 JB |
173 | } |
174 | ||
79e53945 JB |
175 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
176 | struct drm_display_mode *mode) | |
177 | { | |
dd06f90e JN |
178 | struct intel_connector *intel_connector = to_intel_connector(connector); |
179 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 180 | |
788319d4 CW |
181 | if (mode->hdisplay > fixed_mode->hdisplay) |
182 | return MODE_PANEL; | |
183 | if (mode->vdisplay > fixed_mode->vdisplay) | |
184 | return MODE_PANEL; | |
79e53945 JB |
185 | |
186 | return MODE_OK; | |
187 | } | |
188 | ||
49be663f CW |
189 | static void |
190 | centre_horizontally(struct drm_display_mode *mode, | |
191 | int width) | |
192 | { | |
193 | u32 border, sync_pos, blank_width, sync_width; | |
194 | ||
195 | /* keep the hsync and hblank widths constant */ | |
196 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
197 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
198 | sync_pos = (blank_width - sync_width + 1) / 2; | |
199 | ||
200 | border = (mode->hdisplay - width + 1) / 2; | |
201 | border += border & 1; /* make the border even */ | |
202 | ||
203 | mode->crtc_hdisplay = width; | |
204 | mode->crtc_hblank_start = width + border; | |
205 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
206 | ||
207 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
208 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
f9bef081 DV |
209 | |
210 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
211 | } |
212 | ||
213 | static void | |
214 | centre_vertically(struct drm_display_mode *mode, | |
215 | int height) | |
216 | { | |
217 | u32 border, sync_pos, blank_width, sync_width; | |
218 | ||
219 | /* keep the vsync and vblank widths constant */ | |
220 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
221 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
222 | sync_pos = (blank_width - sync_width + 1) / 2; | |
223 | ||
224 | border = (mode->vdisplay - height + 1) / 2; | |
225 | ||
226 | mode->crtc_vdisplay = height; | |
227 | mode->crtc_vblank_start = height + border; | |
228 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
229 | ||
230 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
231 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
f9bef081 DV |
232 | |
233 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
234 | } |
235 | ||
236 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
237 | { | |
238 | /* | |
239 | * Floating point operation is not supported. So the FACTOR | |
240 | * is defined, which can avoid the floating point computation | |
241 | * when calculating the panel ratio. | |
242 | */ | |
243 | #define ACCURACY 12 | |
244 | #define FACTOR (1 << ACCURACY) | |
245 | u32 ratio = source * FACTOR / target; | |
246 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
247 | } | |
248 | ||
79e53945 | 249 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 250 | const struct drm_display_mode *mode, |
79e53945 JB |
251 | struct drm_display_mode *adjusted_mode) |
252 | { | |
253 | struct drm_device *dev = encoder->dev; | |
254 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 255 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
4d891523 JN |
256 | struct intel_connector *intel_connector = |
257 | &lvds_encoder->attached_connector->base; | |
29b99b48 | 258 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
49be663f | 259 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
9db4a9c7 | 260 | int pipe; |
79e53945 JB |
261 | |
262 | /* Should never happen!! */ | |
a6c45cf0 | 263 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 264 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
265 | return false; |
266 | } | |
267 | ||
29b99b48 | 268 | if (intel_encoder_check_is_cloned(&lvds_encoder->base)) |
e24c5c29 | 269 | return false; |
1d8e1c75 | 270 | |
79e53945 | 271 | /* |
71677043 | 272 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
273 | * to the adjusted mode. The CRTC will be set up for this mode, |
274 | * with the panel scaling set up to source from the H/VDisplay | |
275 | * of the original mode. | |
276 | */ | |
4d891523 | 277 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 278 | adjusted_mode); |
1d8e1c75 CW |
279 | |
280 | if (HAS_PCH_SPLIT(dev)) { | |
4d891523 JN |
281 | intel_pch_panel_fitting(dev, |
282 | intel_connector->panel.fitting_mode, | |
1d8e1c75 CW |
283 | mode, adjusted_mode); |
284 | return true; | |
285 | } | |
79e53945 | 286 | |
3fbe18d6 ZY |
287 | /* Native modes don't need fitting */ |
288 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 289 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 290 | goto out; |
3fbe18d6 ZY |
291 | |
292 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 293 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
294 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
295 | PFIT_FILTER_FUZZY); | |
296 | ||
3fbe18d6 ZY |
297 | /* |
298 | * Enable automatic panel scaling for non-native modes so that they fill | |
299 | * the screen. Should be enabled before the pipe is enabled, according | |
300 | * to register description and PRM. | |
301 | * Change the value here to see the borders for debugging | |
302 | */ | |
9db4a9c7 JB |
303 | for_each_pipe(pipe) |
304 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 305 | |
f9bef081 DV |
306 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
307 | ||
4d891523 | 308 | switch (intel_connector->panel.fitting_mode) { |
53bd8389 | 309 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
310 | /* |
311 | * For centered modes, we have to calculate border widths & | |
312 | * heights and modify the values programmed into the CRTC. | |
313 | */ | |
49be663f CW |
314 | centre_horizontally(adjusted_mode, mode->hdisplay); |
315 | centre_vertically(adjusted_mode, mode->vdisplay); | |
316 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 317 | break; |
49be663f | 318 | |
3fbe18d6 | 319 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 320 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 321 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
322 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
323 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
324 | ||
3fbe18d6 | 325 | /* 965+ is easy, it does everything in hw */ |
49be663f | 326 | if (scaled_width > scaled_height) |
257e48f1 | 327 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 328 | else if (scaled_width < scaled_height) |
257e48f1 CW |
329 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
330 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
331 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 332 | } else { |
49be663f CW |
333 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
334 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
335 | /* |
336 | * For earlier chips we have to calculate the scaling | |
337 | * ratio by hand and program it into the | |
338 | * PFIT_PGM_RATIO register | |
339 | */ | |
49be663f CW |
340 | if (scaled_width > scaled_height) { /* pillar */ |
341 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
342 | ||
343 | border = LVDS_BORDER_ENABLE; | |
344 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
345 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
346 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
347 | bits << PFIT_VERT_SCALE_SHIFT); | |
348 | pfit_control |= (PFIT_ENABLE | | |
349 | VERT_INTERP_BILINEAR | | |
350 | HORIZ_INTERP_BILINEAR); | |
351 | } | |
352 | } else if (scaled_width < scaled_height) { /* letter */ | |
353 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
354 | ||
355 | border = LVDS_BORDER_ENABLE; | |
356 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
357 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
358 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
359 | bits << PFIT_VERT_SCALE_SHIFT); | |
360 | pfit_control |= (PFIT_ENABLE | | |
361 | VERT_INTERP_BILINEAR | | |
362 | HORIZ_INTERP_BILINEAR); | |
363 | } | |
364 | } else | |
365 | /* Aspects match, Let hw scale both directions */ | |
366 | pfit_control |= (PFIT_ENABLE | | |
367 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
368 | VERT_INTERP_BILINEAR | |
369 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
370 | } |
371 | break; | |
372 | ||
373 | case DRM_MODE_SCALE_FULLSCREEN: | |
374 | /* | |
375 | * Full scaling, even if it changes the aspect ratio. | |
376 | * Fortunately this is all done for us in hw. | |
377 | */ | |
257e48f1 CW |
378 | if (mode->vdisplay != adjusted_mode->vdisplay || |
379 | mode->hdisplay != adjusted_mode->hdisplay) { | |
380 | pfit_control |= PFIT_ENABLE; | |
381 | if (INTEL_INFO(dev)->gen >= 4) | |
382 | pfit_control |= PFIT_SCALING_AUTO; | |
383 | else | |
384 | pfit_control |= (VERT_AUTO_SCALE | | |
385 | VERT_INTERP_BILINEAR | | |
386 | HORIZ_AUTO_SCALE | | |
387 | HORIZ_INTERP_BILINEAR); | |
388 | } | |
3fbe18d6 | 389 | break; |
49be663f | 390 | |
3fbe18d6 ZY |
391 | default: |
392 | break; | |
393 | } | |
394 | ||
395 | out: | |
72389a33 | 396 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
397 | if ((pfit_control & PFIT_ENABLE) == 0) { |
398 | pfit_control = 0; | |
399 | pfit_pgm_ratios = 0; | |
400 | } | |
72389a33 CW |
401 | |
402 | /* Make sure pre-965 set dither correctly */ | |
403 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
404 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
405 | ||
29b99b48 JN |
406 | if (pfit_control != lvds_encoder->pfit_control || |
407 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | |
408 | lvds_encoder->pfit_control = pfit_control; | |
409 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | |
410 | lvds_encoder->pfit_dirty = true; | |
e9e331a8 | 411 | } |
49be663f CW |
412 | dev_priv->lvds_border_bits = border; |
413 | ||
79e53945 JB |
414 | /* |
415 | * XXX: It would be nice to support lower refresh rates on the | |
416 | * panels to reduce power consumption, and perhaps match the | |
417 | * user's requested refresh rate. | |
418 | */ | |
419 | ||
420 | return true; | |
421 | } | |
422 | ||
79e53945 JB |
423 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
424 | struct drm_display_mode *mode, | |
425 | struct drm_display_mode *adjusted_mode) | |
426 | { | |
79e53945 JB |
427 | /* |
428 | * The LVDS pin pair will already have been turned on in the | |
429 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
430 | * settings. | |
431 | */ | |
79e53945 JB |
432 | } |
433 | ||
434 | /** | |
435 | * Detect the LVDS connection. | |
436 | * | |
b42d4c5c JB |
437 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
438 | * connected and closed means disconnected. We also send hotplug events as | |
439 | * needed, using lid status notification from the input layer. | |
79e53945 | 440 | */ |
7b334fcb | 441 | static enum drm_connector_status |
930a9e28 | 442 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 443 | { |
7b9c5abe | 444 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 445 | enum drm_connector_status status; |
b42d4c5c | 446 | |
fe16d949 CW |
447 | status = intel_panel_detect(dev); |
448 | if (status != connector_status_unknown) | |
449 | return status; | |
01fe9dbd | 450 | |
6ee3b5a1 | 451 | return connector_status_connected; |
79e53945 JB |
452 | } |
453 | ||
454 | /** | |
455 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
456 | */ | |
457 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
458 | { | |
62165e0d | 459 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 460 | struct drm_device *dev = connector->dev; |
788319d4 | 461 | struct drm_display_mode *mode; |
79e53945 | 462 | |
9cd300e0 | 463 | /* use cached edid if we have one */ |
2aa4f099 | 464 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 465 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 466 | |
dd06f90e | 467 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 468 | if (mode == NULL) |
788319d4 | 469 | return 0; |
79e53945 | 470 | |
788319d4 CW |
471 | drm_mode_probed_add(connector, mode); |
472 | return 1; | |
79e53945 JB |
473 | } |
474 | ||
0544edfd TB |
475 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
476 | { | |
bc0daf48 | 477 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
478 | return 1; |
479 | } | |
480 | ||
481 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
482 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
483 | { | |
484 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
485 | .ident = "Toshiba Tecra A11", | |
486 | .matches = { | |
487 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
488 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
489 | }, | |
490 | }, | |
491 | ||
492 | { } /* terminating entry */ | |
493 | }; | |
494 | ||
c9354c85 LT |
495 | /* |
496 | * Lid events. Note the use of 'modeset_on_lid': | |
497 | * - we set it on lid close, and reset it on open | |
498 | * - we use it as a "only once" bit (ie we ignore | |
499 | * duplicate events where it was already properly | |
500 | * set/reset) | |
501 | * - the suspend/resume paths will also set it to | |
502 | * zero, since they restore the mode ("lid open"). | |
503 | */ | |
c1c7af60 JB |
504 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
505 | void *unused) | |
506 | { | |
db1740a0 JN |
507 | struct intel_lvds_connector *lvds_connector = |
508 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
509 | struct drm_connector *connector = &lvds_connector->base.base; | |
510 | struct drm_device *dev = connector->dev; | |
511 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 512 | |
2fb4e61d AW |
513 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
514 | return NOTIFY_OK; | |
515 | ||
a2565377 ZY |
516 | /* |
517 | * check and update the status of LVDS connector after receiving | |
518 | * the LID nofication event. | |
519 | */ | |
db1740a0 | 520 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 521 | |
0544edfd TB |
522 | /* Don't force modeset on machines where it causes a GPU lockup */ |
523 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
524 | return NOTIFY_OK; | |
c9354c85 LT |
525 | if (!acpi_lid_open()) { |
526 | dev_priv->modeset_on_lid = 1; | |
527 | return NOTIFY_OK; | |
06891e27 | 528 | } |
c1c7af60 | 529 | |
c9354c85 LT |
530 | if (!dev_priv->modeset_on_lid) |
531 | return NOTIFY_OK; | |
532 | ||
533 | dev_priv->modeset_on_lid = 0; | |
534 | ||
535 | mutex_lock(&dev->mode_config.mutex); | |
45e2b5f6 | 536 | intel_modeset_setup_hw_state(dev, true); |
c9354c85 | 537 | mutex_unlock(&dev->mode_config.mutex); |
06324194 | 538 | |
c1c7af60 JB |
539 | return NOTIFY_OK; |
540 | } | |
541 | ||
79e53945 JB |
542 | /** |
543 | * intel_lvds_destroy - unregister and free LVDS structures | |
544 | * @connector: connector to free | |
545 | * | |
546 | * Unregister the DDC bus for this connector then free the driver private | |
547 | * structure. | |
548 | */ | |
549 | static void intel_lvds_destroy(struct drm_connector *connector) | |
550 | { | |
db1740a0 JN |
551 | struct intel_lvds_connector *lvds_connector = |
552 | to_lvds_connector(connector); | |
79e53945 | 553 | |
db1740a0 JN |
554 | if (lvds_connector->lid_notifier.notifier_call) |
555 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 556 | |
9cd300e0 JN |
557 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
558 | kfree(lvds_connector->base.edid); | |
559 | ||
db1740a0 | 560 | intel_panel_destroy_backlight(connector->dev); |
1d508706 | 561 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 562 | |
79e53945 JB |
563 | drm_sysfs_connector_remove(connector); |
564 | drm_connector_cleanup(connector); | |
565 | kfree(connector); | |
566 | } | |
567 | ||
335041ed JB |
568 | static int intel_lvds_set_property(struct drm_connector *connector, |
569 | struct drm_property *property, | |
570 | uint64_t value) | |
571 | { | |
4d891523 | 572 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 573 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 574 | |
788319d4 | 575 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 576 | struct drm_crtc *crtc; |
bb8a3560 | 577 | |
53bd8389 JB |
578 | if (value == DRM_MODE_SCALE_NONE) { |
579 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 580 | return -EINVAL; |
3fbe18d6 | 581 | } |
788319d4 | 582 | |
4d891523 | 583 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
584 | /* the LVDS scaling property is not changed */ |
585 | return 0; | |
586 | } | |
4d891523 | 587 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
588 | |
589 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
590 | if (crtc && crtc->enabled) { |
591 | /* | |
592 | * If the CRTC is enabled, the display will be changed | |
593 | * according to the new panel fitting mode. | |
594 | */ | |
a6778b3c DV |
595 | intel_set_mode(crtc, &crtc->mode, |
596 | crtc->x, crtc->y, crtc->fb); | |
3fbe18d6 ZY |
597 | } |
598 | } | |
599 | ||
335041ed JB |
600 | return 0; |
601 | } | |
602 | ||
79e53945 | 603 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 604 | .mode_fixup = intel_lvds_mode_fixup, |
79e53945 | 605 | .mode_set = intel_lvds_mode_set, |
1f703855 | 606 | .disable = intel_encoder_noop, |
79e53945 JB |
607 | }; |
608 | ||
609 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
610 | .get_modes = intel_lvds_get_modes, | |
611 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 612 | .best_encoder = intel_best_encoder, |
79e53945 JB |
613 | }; |
614 | ||
615 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 616 | .dpms = intel_connector_dpms, |
79e53945 JB |
617 | .detect = intel_lvds_detect, |
618 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 619 | .set_property = intel_lvds_set_property, |
79e53945 JB |
620 | .destroy = intel_lvds_destroy, |
621 | }; | |
622 | ||
79e53945 | 623 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 624 | .destroy = intel_encoder_destroy, |
79e53945 JB |
625 | }; |
626 | ||
425d244c JW |
627 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
628 | { | |
bc0daf48 | 629 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
630 | return 1; |
631 | } | |
79e53945 | 632 | |
425d244c | 633 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 634 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
635 | { |
636 | .callback = intel_no_lvds_dmi_callback, | |
637 | .ident = "Apple Mac Mini (Core series)", | |
638 | .matches = { | |
98acd46f | 639 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
640 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
641 | }, | |
642 | }, | |
643 | { | |
644 | .callback = intel_no_lvds_dmi_callback, | |
645 | .ident = "Apple Mac Mini (Core 2 series)", | |
646 | .matches = { | |
98acd46f | 647 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
648 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
649 | }, | |
650 | }, | |
651 | { | |
652 | .callback = intel_no_lvds_dmi_callback, | |
653 | .ident = "MSI IM-945GSE-A", | |
654 | .matches = { | |
655 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
656 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
657 | }, | |
658 | }, | |
659 | { | |
660 | .callback = intel_no_lvds_dmi_callback, | |
661 | .ident = "Dell Studio Hybrid", | |
662 | .matches = { | |
663 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
664 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
665 | }, | |
666 | }, | |
70aa96ca JW |
667 | { |
668 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
669 | .ident = "Dell OptiPlex FX170", |
670 | .matches = { | |
671 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
672 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
673 | }, | |
674 | }, | |
675 | { | |
676 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
677 | .ident = "AOpen Mini PC", |
678 | .matches = { | |
679 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
680 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
681 | }, | |
682 | }, | |
ed8c754b TV |
683 | { |
684 | .callback = intel_no_lvds_dmi_callback, | |
685 | .ident = "AOpen Mini PC MP915", | |
686 | .matches = { | |
687 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
688 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
689 | }, | |
690 | }, | |
22ab70d3 KP |
691 | { |
692 | .callback = intel_no_lvds_dmi_callback, | |
693 | .ident = "AOpen i915GMm-HFS", | |
694 | .matches = { | |
695 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
696 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
697 | }, | |
698 | }, | |
e57b6886 DV |
699 | { |
700 | .callback = intel_no_lvds_dmi_callback, | |
701 | .ident = "AOpen i45GMx-I", | |
702 | .matches = { | |
703 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
704 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
705 | }, | |
706 | }, | |
fa0864b2 MC |
707 | { |
708 | .callback = intel_no_lvds_dmi_callback, | |
709 | .ident = "Aopen i945GTt-VFA", | |
710 | .matches = { | |
711 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
712 | }, | |
713 | }, | |
9875557e SB |
714 | { |
715 | .callback = intel_no_lvds_dmi_callback, | |
716 | .ident = "Clientron U800", | |
717 | .matches = { | |
718 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
719 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
720 | }, | |
721 | }, | |
6a574b5b | 722 | { |
44306ab3 JS |
723 | .callback = intel_no_lvds_dmi_callback, |
724 | .ident = "Clientron E830", | |
725 | .matches = { | |
726 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
727 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
728 | }, | |
729 | }, | |
730 | { | |
6a574b5b HG |
731 | .callback = intel_no_lvds_dmi_callback, |
732 | .ident = "Asus EeeBox PC EB1007", | |
733 | .matches = { | |
734 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
735 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
736 | }, | |
737 | }, | |
0999bbe0 AJ |
738 | { |
739 | .callback = intel_no_lvds_dmi_callback, | |
740 | .ident = "Asus AT5NM10T-I", | |
741 | .matches = { | |
742 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
743 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
744 | }, | |
745 | }, | |
33471119 JBG |
746 | { |
747 | .callback = intel_no_lvds_dmi_callback, | |
748 | .ident = "Hewlett-Packard HP t5740e Thin Client", | |
749 | .matches = { | |
750 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
751 | DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"), | |
752 | }, | |
753 | }, | |
f5b8a7ed MG |
754 | { |
755 | .callback = intel_no_lvds_dmi_callback, | |
756 | .ident = "Hewlett-Packard t5745", | |
757 | .matches = { | |
758 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 759 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
760 | }, |
761 | }, | |
762 | { | |
763 | .callback = intel_no_lvds_dmi_callback, | |
764 | .ident = "Hewlett-Packard st5747", | |
765 | .matches = { | |
766 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 767 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
768 | }, |
769 | }, | |
97effadb AA |
770 | { |
771 | .callback = intel_no_lvds_dmi_callback, | |
772 | .ident = "MSI Wind Box DC500", | |
773 | .matches = { | |
774 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
775 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
776 | }, | |
777 | }, | |
9756fe38 SS |
778 | { |
779 | .callback = intel_no_lvds_dmi_callback, | |
780 | .ident = "ZOTAC ZBOXSD-ID12/ID13", | |
781 | .matches = { | |
782 | DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"), | |
783 | DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"), | |
784 | }, | |
785 | }, | |
a51d4ed0 CW |
786 | { |
787 | .callback = intel_no_lvds_dmi_callback, | |
788 | .ident = "Gigabyte GA-D525TUD", | |
789 | .matches = { | |
790 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
791 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
792 | }, | |
793 | }, | |
c31407a3 CW |
794 | { |
795 | .callback = intel_no_lvds_dmi_callback, | |
796 | .ident = "Supermicro X7SPA-H", | |
797 | .matches = { | |
798 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
799 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
800 | }, | |
801 | }, | |
425d244c JW |
802 | |
803 | { } /* terminating entry */ | |
804 | }; | |
79e53945 | 805 | |
18f9ed12 ZY |
806 | /** |
807 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
808 | * @dev: drm device | |
809 | * @connector: LVDS connector | |
810 | * | |
811 | * Find the reduced downclock for LVDS in EDID. | |
812 | */ | |
813 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
814 | struct drm_display_mode *fixed_mode, |
815 | struct drm_connector *connector) | |
18f9ed12 ZY |
816 | { |
817 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 818 | struct drm_display_mode *scan; |
18f9ed12 ZY |
819 | int temp_downclock; |
820 | ||
788319d4 | 821 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
822 | list_for_each_entry(scan, &connector->probed_modes, head) { |
823 | /* | |
824 | * If one mode has the same resolution with the fixed_panel | |
825 | * mode while they have the different refresh rate, it means | |
826 | * that the reduced downclock is found for the LVDS. In such | |
827 | * case we can set the different FPx0/1 to dynamically select | |
828 | * between low and high frequency. | |
829 | */ | |
788319d4 CW |
830 | if (scan->hdisplay == fixed_mode->hdisplay && |
831 | scan->hsync_start == fixed_mode->hsync_start && | |
832 | scan->hsync_end == fixed_mode->hsync_end && | |
833 | scan->htotal == fixed_mode->htotal && | |
834 | scan->vdisplay == fixed_mode->vdisplay && | |
835 | scan->vsync_start == fixed_mode->vsync_start && | |
836 | scan->vsync_end == fixed_mode->vsync_end && | |
837 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
838 | if (scan->clock < temp_downclock) { |
839 | /* | |
840 | * The downclock is already found. But we | |
841 | * expect to find the lower downclock. | |
842 | */ | |
843 | temp_downclock = scan->clock; | |
844 | } | |
845 | } | |
846 | } | |
788319d4 | 847 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
848 | /* We found the downclock for LVDS. */ |
849 | dev_priv->lvds_downclock_avail = 1; | |
850 | dev_priv->lvds_downclock = temp_downclock; | |
851 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
852 | "Normal clock %dKhz, downclock %dKhz\n", |
853 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 854 | } |
18f9ed12 ZY |
855 | } |
856 | ||
7cf4f69d ZY |
857 | /* |
858 | * Enumerate the child dev array parsed from VBT to check whether | |
859 | * the LVDS is present. | |
860 | * If it is present, return 1. | |
861 | * If it is not present, return false. | |
862 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 863 | */ |
270eea0f CW |
864 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
865 | u8 *i2c_pin) | |
7cf4f69d ZY |
866 | { |
867 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 868 | int i; |
7cf4f69d ZY |
869 | |
870 | if (!dev_priv->child_dev_num) | |
425904dd | 871 | return true; |
7cf4f69d | 872 | |
7cf4f69d | 873 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
874 | struct child_device_config *child = dev_priv->child_dev + i; |
875 | ||
876 | /* If the device type is not LFP, continue. | |
877 | * We have to check both the new identifiers as well as the | |
878 | * old for compatibility with some BIOSes. | |
7cf4f69d | 879 | */ |
425904dd CW |
880 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
881 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
882 | continue; |
883 | ||
3bd7d909 DK |
884 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
885 | *i2c_pin = child->i2c_pin; | |
270eea0f | 886 | |
425904dd CW |
887 | /* However, we cannot trust the BIOS writers to populate |
888 | * the VBT correctly. Since LVDS requires additional | |
889 | * information from AIM blocks, a non-zero addin offset is | |
890 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 891 | */ |
425904dd CW |
892 | if (child->addin_offset) |
893 | return true; | |
894 | ||
895 | /* But even then some BIOS writers perform some black magic | |
896 | * and instantiate the device without reference to any | |
897 | * additional data. Trust that if the VBT was written into | |
898 | * the OpRegion then they have validated the LVDS's existence. | |
899 | */ | |
900 | if (dev_priv->opregion.vbt) | |
901 | return true; | |
7cf4f69d | 902 | } |
425904dd CW |
903 | |
904 | return false; | |
7cf4f69d ZY |
905 | } |
906 | ||
1974cad0 DV |
907 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
908 | { | |
909 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
910 | return 1; | |
911 | } | |
912 | ||
913 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
914 | { | |
915 | .callback = intel_dual_link_lvds_callback, | |
916 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
917 | .matches = { | |
918 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
919 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
920 | }, | |
921 | }, | |
922 | { } /* terminating entry */ | |
923 | }; | |
924 | ||
925 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
926 | { |
927 | struct intel_encoder *encoder; | |
928 | struct intel_lvds_encoder *lvds_encoder; | |
929 | ||
930 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
931 | base.head) { | |
932 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
933 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
934 | ||
935 | return lvds_encoder->is_dual_link; | |
936 | } | |
937 | } | |
938 | ||
939 | return false; | |
940 | } | |
941 | ||
942 | static bool compute_is_dual_link_lvds(struct drm_device *dev) | |
1974cad0 DV |
943 | { |
944 | unsigned int val; | |
945 | struct drm_i915_private *dev_priv = dev->dev_private; | |
946 | u32 lvds_reg; | |
947 | ||
948 | if (HAS_PCH_SPLIT(dev)) { | |
949 | lvds_reg = PCH_LVDS; | |
950 | } else { | |
951 | lvds_reg = LVDS; | |
952 | } | |
953 | ||
954 | /* use the module option value if specified */ | |
955 | if (i915_lvds_channel_mode > 0) | |
956 | return i915_lvds_channel_mode == 2; | |
957 | ||
958 | if (dmi_check_system(intel_dual_link_lvds)) | |
959 | return true; | |
960 | ||
13c7d870 DV |
961 | /* BIOS should set the proper LVDS register value at boot, but |
962 | * in reality, it doesn't set the value when the lid is closed; | |
963 | * we need to check "the value to be set" in VBT when LVDS | |
964 | * register is uninitialized. | |
965 | */ | |
966 | val = I915_READ(lvds_reg); | |
967 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) | |
968 | val = dev_priv->bios_lvds_val; | |
969 | ||
1974cad0 DV |
970 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
971 | } | |
972 | ||
f3cfcba6 CW |
973 | static bool intel_lvds_supported(struct drm_device *dev) |
974 | { | |
975 | /* With the introduction of the PCH we gained a dedicated | |
976 | * LVDS presence pin, use it. */ | |
977 | if (HAS_PCH_SPLIT(dev)) | |
978 | return true; | |
979 | ||
980 | /* Otherwise LVDS was only attached to mobile products, | |
981 | * except for the inglorious 830gm */ | |
982 | return IS_MOBILE(dev) && !IS_I830(dev); | |
983 | } | |
984 | ||
79e53945 JB |
985 | /** |
986 | * intel_lvds_init - setup LVDS connectors on this device | |
987 | * @dev: drm device | |
988 | * | |
989 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
990 | * modes we can display on the LVDS panel (if present). | |
991 | */ | |
c5d1b51d | 992 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
993 | { |
994 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 995 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 996 | struct intel_encoder *intel_encoder; |
c7362c4d | 997 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 998 | struct intel_connector *intel_connector; |
79e53945 JB |
999 | struct drm_connector *connector; |
1000 | struct drm_encoder *encoder; | |
1001 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 1002 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 1003 | struct edid *edid; |
79e53945 JB |
1004 | struct drm_crtc *crtc; |
1005 | u32 lvds; | |
270eea0f CW |
1006 | int pipe; |
1007 | u8 pin; | |
79e53945 | 1008 | |
f3cfcba6 CW |
1009 | if (!intel_lvds_supported(dev)) |
1010 | return false; | |
1011 | ||
425d244c JW |
1012 | /* Skip init on machines we know falsely report LVDS */ |
1013 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 1014 | return false; |
565dcd46 | 1015 | |
270eea0f CW |
1016 | pin = GMBUS_PORT_PANEL; |
1017 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 1018 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 1019 | return false; |
38b3037e | 1020 | } |
e99da35f | 1021 | |
c619eed4 | 1022 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1023 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 1024 | return false; |
5ceb0f9b | 1025 | if (dev_priv->edp.support) { |
28c97730 | 1026 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 1027 | return false; |
32f9d658 | 1028 | } |
541998a1 ZW |
1029 | } |
1030 | ||
29b99b48 JN |
1031 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
1032 | if (!lvds_encoder) | |
c5d1b51d | 1033 | return false; |
79e53945 | 1034 | |
c7362c4d JN |
1035 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
1036 | if (!lvds_connector) { | |
29b99b48 | 1037 | kfree(lvds_encoder); |
c5d1b51d | 1038 | return false; |
bb8a3560 ZW |
1039 | } |
1040 | ||
62165e0d JN |
1041 | lvds_encoder->attached_connector = lvds_connector; |
1042 | ||
e9e331a8 | 1043 | if (!HAS_PCH_SPLIT(dev)) { |
29b99b48 | 1044 | lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); |
e9e331a8 CW |
1045 | } |
1046 | ||
29b99b48 | 1047 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1048 | encoder = &intel_encoder->base; |
c7362c4d | 1049 | intel_connector = &lvds_connector->base; |
ea5b213a | 1050 | connector = &intel_connector->base; |
bb8a3560 | 1051 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1052 | DRM_MODE_CONNECTOR_LVDS); |
1053 | ||
4ef69c7a | 1054 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
1055 | DRM_MODE_ENCODER_LVDS); |
1056 | ||
c22834ec DV |
1057 | intel_encoder->enable = intel_enable_lvds; |
1058 | intel_encoder->disable = intel_disable_lvds; | |
b1dc332c DV |
1059 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
1060 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
c22834ec | 1061 | |
df0e9248 | 1062 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1063 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1064 | |
66a9278e | 1065 | intel_encoder->cloneable = false; |
27f8227b JB |
1066 | if (HAS_PCH_SPLIT(dev)) |
1067 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1068 | else if (IS_GEN4(dev)) |
1069 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1070 | else |
1071 | intel_encoder->crtc_mask = (1 << 1); | |
1072 | ||
79e53945 JB |
1073 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1074 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1075 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1076 | connector->interlace_allowed = false; | |
1077 | connector->doublescan_allowed = false; | |
1078 | ||
3fbe18d6 ZY |
1079 | /* create the scaling mode property */ |
1080 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1081 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1082 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1083 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1084 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1085 | /* |
1086 | * LVDS discovery: | |
1087 | * 1) check for EDID on DDC | |
1088 | * 2) check for VBT data | |
1089 | * 3) check to see if LVDS is already on | |
1090 | * if none of the above, no panel | |
1091 | * 4) make sure lid is open | |
1092 | * if closed, act like it's not there for now | |
1093 | */ | |
1094 | ||
79e53945 JB |
1095 | /* |
1096 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1097 | * preferred mode is the right one. | |
1098 | */ | |
9cd300e0 JN |
1099 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1100 | if (edid) { | |
1101 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1102 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1103 | edid); |
3f8ff0e7 | 1104 | } else { |
9cd300e0 JN |
1105 | kfree(edid); |
1106 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1107 | } |
9cd300e0 JN |
1108 | } else { |
1109 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1110 | } |
9cd300e0 JN |
1111 | lvds_connector->base.edid = edid; |
1112 | ||
1113 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1114 | /* Didn't get an EDID, so |
1115 | * Set wide sync ranges so we get all modes | |
1116 | * handed to valid_mode for checking | |
1117 | */ | |
1118 | connector->display_info.min_vfreq = 0; | |
1119 | connector->display_info.max_vfreq = 200; | |
1120 | connector->display_info.min_hfreq = 0; | |
1121 | connector->display_info.max_hfreq = 200; | |
1122 | } | |
79e53945 JB |
1123 | |
1124 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1125 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1126 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1127 | drm_mode_debug_printmodeline(scan); | |
1128 | ||
dd06f90e | 1129 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1130 | if (fixed_mode) { |
1131 | intel_find_lvds_downclock(dev, fixed_mode, | |
1132 | connector); | |
1133 | goto out; | |
1134 | } | |
79e53945 | 1135 | } |
79e53945 JB |
1136 | } |
1137 | ||
1138 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1139 | if (dev_priv->lfp_lvds_vbt_mode) { |
6a9d51b7 CW |
1140 | DRM_DEBUG_KMS("using mode from VBT: "); |
1141 | drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); | |
1142 | ||
dd06f90e JN |
1143 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
1144 | if (fixed_mode) { | |
1145 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1146 | goto out; |
1147 | } | |
79e53945 JB |
1148 | } |
1149 | ||
1150 | /* | |
1151 | * If we didn't get EDID, try checking if the panel is already turned | |
1152 | * on. If so, assume that whatever is currently programmed is the | |
1153 | * correct mode. | |
1154 | */ | |
541998a1 | 1155 | |
f2b115e6 | 1156 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1157 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1158 | goto failed; |
1159 | ||
79e53945 JB |
1160 | lvds = I915_READ(LVDS); |
1161 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1162 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1163 | |
1164 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1165 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1166 | if (fixed_mode) { | |
6a9d51b7 CW |
1167 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1168 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1169 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1170 | goto out; |
79e53945 JB |
1171 | } |
1172 | } | |
1173 | ||
1174 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1175 | if (!fixed_mode) |
79e53945 JB |
1176 | goto failed; |
1177 | ||
79e53945 | 1178 | out: |
13c7d870 DV |
1179 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(dev); |
1180 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", | |
1181 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1182 | ||
24ded204 DV |
1183 | /* |
1184 | * Unlock registers and just | |
1185 | * leave them unlocked | |
1186 | */ | |
c619eed4 | 1187 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1188 | I915_WRITE(PCH_PP_CONTROL, |
1189 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1190 | } else { | |
ed10fca9 KP |
1191 | I915_WRITE(PP_CONTROL, |
1192 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1193 | } |
db1740a0 JN |
1194 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1195 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1196 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1197 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1198 | } |
79e53945 | 1199 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1200 | |
dd06f90e | 1201 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1202 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1203 | |
c5d1b51d | 1204 | return true; |
79e53945 JB |
1205 | |
1206 | failed: | |
8a4c47f3 | 1207 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1208 | drm_connector_cleanup(connector); |
1991bdfa | 1209 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1210 | if (fixed_mode) |
1211 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1212 | kfree(lvds_encoder); |
c7362c4d | 1213 | kfree(lvds_connector); |
c5d1b51d | 1214 | return false; |
79e53945 | 1215 | } |