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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
788319d4 | 46 | |
219adae1 | 47 | struct edid *edid; |
788319d4 | 48 | |
3fbe18d6 ZY |
49 | int fitting_mode; |
50 | u32 pfit_control; | |
51 | u32 pfit_pgm_ratios; | |
e9e331a8 | 52 | bool pfit_dirty; |
788319d4 CW |
53 | |
54 | struct drm_display_mode *fixed_mode; | |
3fbe18d6 ZY |
55 | }; |
56 | ||
788319d4 | 57 | static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
60 | } |
61 | ||
788319d4 CW |
62 | static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_lvds, base); | |
66 | } | |
67 | ||
79e53945 JB |
68 | /** |
69 | * Sets the power state for the panel. | |
70 | */ | |
2a1292fd | 71 | static void intel_lvds_enable(struct intel_lvds *intel_lvds) |
79e53945 | 72 | { |
e9e331a8 | 73 | struct drm_device *dev = intel_lvds->base.base.dev; |
79e53945 | 74 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9e331a8 | 75 | u32 ctl_reg, lvds_reg; |
541998a1 | 76 | |
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 78 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 79 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
80 | } else { |
81 | ctl_reg = PP_CONTROL; | |
469d1296 | 82 | lvds_reg = LVDS; |
541998a1 | 83 | } |
79e53945 | 84 | |
2a1292fd | 85 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
e9e331a8 | 86 | |
2a1292fd CW |
87 | if (intel_lvds->pfit_dirty) { |
88 | /* | |
89 | * Enable automatic panel scaling so that non-native modes | |
90 | * fill the screen. The panel fitter should only be | |
91 | * adjusted whilst the pipe is disabled, according to | |
92 | * register description and PRM. | |
93 | */ | |
94 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
95 | intel_lvds->pfit_control, | |
96 | intel_lvds->pfit_pgm_ratios); | |
97 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) { | |
98 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
99 | } else { | |
100 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); | |
101 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
4fd21dc8 | 102 | intel_lvds->pfit_dirty = false; |
e9e331a8 | 103 | } |
2a1292fd CW |
104 | } |
105 | ||
106 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); | |
107 | POSTING_READ(lvds_reg); | |
108 | ||
47356eb6 | 109 | intel_panel_enable_backlight(dev); |
2a1292fd CW |
110 | } |
111 | ||
112 | static void intel_lvds_disable(struct intel_lvds *intel_lvds) | |
113 | { | |
114 | struct drm_device *dev = intel_lvds->base.base.dev; | |
115 | struct drm_i915_private *dev_priv = dev->dev_private; | |
116 | u32 ctl_reg, lvds_reg; | |
117 | ||
118 | if (HAS_PCH_SPLIT(dev)) { | |
119 | ctl_reg = PCH_PP_CONTROL; | |
120 | lvds_reg = PCH_LVDS; | |
121 | } else { | |
122 | ctl_reg = PP_CONTROL; | |
123 | lvds_reg = LVDS; | |
124 | } | |
125 | ||
47356eb6 | 126 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
127 | |
128 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
129 | ||
130 | if (intel_lvds->pfit_control) { | |
131 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) | |
132 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
e9e331a8 | 133 | |
2a1292fd CW |
134 | I915_WRITE(PFIT_CONTROL, 0); |
135 | intel_lvds->pfit_dirty = true; | |
79e53945 | 136 | } |
2a1292fd CW |
137 | |
138 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); | |
c9f9ccc1 | 139 | POSTING_READ(lvds_reg); |
79e53945 JB |
140 | } |
141 | ||
142 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
143 | { | |
788319d4 | 144 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
145 | |
146 | if (mode == DRM_MODE_DPMS_ON) | |
2a1292fd | 147 | intel_lvds_enable(intel_lvds); |
79e53945 | 148 | else |
2a1292fd | 149 | intel_lvds_disable(intel_lvds); |
79e53945 JB |
150 | |
151 | /* XXX: We never power down the LVDS pairs. */ | |
152 | } | |
153 | ||
79e53945 JB |
154 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
155 | struct drm_display_mode *mode) | |
156 | { | |
788319d4 CW |
157 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
158 | struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; | |
79e53945 | 159 | |
788319d4 CW |
160 | if (mode->hdisplay > fixed_mode->hdisplay) |
161 | return MODE_PANEL; | |
162 | if (mode->vdisplay > fixed_mode->vdisplay) | |
163 | return MODE_PANEL; | |
79e53945 JB |
164 | |
165 | return MODE_OK; | |
166 | } | |
167 | ||
49be663f CW |
168 | static void |
169 | centre_horizontally(struct drm_display_mode *mode, | |
170 | int width) | |
171 | { | |
172 | u32 border, sync_pos, blank_width, sync_width; | |
173 | ||
174 | /* keep the hsync and hblank widths constant */ | |
175 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
176 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
177 | sync_pos = (blank_width - sync_width + 1) / 2; | |
178 | ||
179 | border = (mode->hdisplay - width + 1) / 2; | |
180 | border += border & 1; /* make the border even */ | |
181 | ||
182 | mode->crtc_hdisplay = width; | |
183 | mode->crtc_hblank_start = width + border; | |
184 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
185 | ||
186 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
187 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
188 | } | |
189 | ||
190 | static void | |
191 | centre_vertically(struct drm_display_mode *mode, | |
192 | int height) | |
193 | { | |
194 | u32 border, sync_pos, blank_width, sync_width; | |
195 | ||
196 | /* keep the vsync and vblank widths constant */ | |
197 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
198 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
199 | sync_pos = (blank_width - sync_width + 1) / 2; | |
200 | ||
201 | border = (mode->vdisplay - height + 1) / 2; | |
202 | ||
203 | mode->crtc_vdisplay = height; | |
204 | mode->crtc_vblank_start = height + border; | |
205 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
206 | ||
207 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
208 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
209 | } | |
210 | ||
211 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
212 | { | |
213 | /* | |
214 | * Floating point operation is not supported. So the FACTOR | |
215 | * is defined, which can avoid the floating point computation | |
216 | * when calculating the panel ratio. | |
217 | */ | |
218 | #define ACCURACY 12 | |
219 | #define FACTOR (1 << ACCURACY) | |
220 | u32 ratio = source * FACTOR / target; | |
221 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
222 | } | |
223 | ||
79e53945 JB |
224 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
225 | struct drm_display_mode *mode, | |
226 | struct drm_display_mode *adjusted_mode) | |
227 | { | |
228 | struct drm_device *dev = encoder->dev; | |
229 | struct drm_i915_private *dev_priv = dev->dev_private; | |
230 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
788319d4 | 231 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 232 | struct drm_encoder *tmp_encoder; |
49be663f | 233 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
79e53945 JB |
234 | |
235 | /* Should never happen!! */ | |
a6c45cf0 | 236 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 237 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
238 | return false; |
239 | } | |
240 | ||
241 | /* Should never happen!! */ | |
242 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
243 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 244 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
245 | "encoder on the same pipe\n"); |
246 | return false; | |
247 | } | |
248 | } | |
1d8e1c75 | 249 | |
79e53945 | 250 | /* |
71677043 | 251 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
252 | * to the adjusted mode. The CRTC will be set up for this mode, |
253 | * with the panel scaling set up to source from the H/VDisplay | |
254 | * of the original mode. | |
255 | */ | |
788319d4 | 256 | intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); |
1d8e1c75 CW |
257 | |
258 | if (HAS_PCH_SPLIT(dev)) { | |
259 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
260 | mode, adjusted_mode); | |
261 | return true; | |
262 | } | |
79e53945 | 263 | |
3fbe18d6 | 264 | /* Make sure pre-965s set dither correctly */ |
a6c45cf0 | 265 | if (INTEL_INFO(dev)->gen < 4) { |
d3849ede | 266 | if (dev_priv->lvds_dither) |
3fbe18d6 ZY |
267 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
268 | } | |
269 | ||
270 | /* Native modes don't need fitting */ | |
271 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 272 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 273 | goto out; |
3fbe18d6 ZY |
274 | |
275 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 276 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
277 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
278 | PFIT_FILTER_FUZZY); | |
279 | ||
3fbe18d6 ZY |
280 | /* |
281 | * Enable automatic panel scaling for non-native modes so that they fill | |
282 | * the screen. Should be enabled before the pipe is enabled, according | |
283 | * to register description and PRM. | |
284 | * Change the value here to see the borders for debugging | |
285 | */ | |
1d8e1c75 CW |
286 | I915_WRITE(BCLRPAT_A, 0); |
287 | I915_WRITE(BCLRPAT_B, 0); | |
3fbe18d6 | 288 | |
ea5b213a | 289 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 290 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
291 | /* |
292 | * For centered modes, we have to calculate border widths & | |
293 | * heights and modify the values programmed into the CRTC. | |
294 | */ | |
49be663f CW |
295 | centre_horizontally(adjusted_mode, mode->hdisplay); |
296 | centre_vertically(adjusted_mode, mode->vdisplay); | |
297 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 298 | break; |
49be663f | 299 | |
3fbe18d6 | 300 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 301 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 302 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
303 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
304 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
305 | ||
3fbe18d6 | 306 | /* 965+ is easy, it does everything in hw */ |
49be663f | 307 | if (scaled_width > scaled_height) |
257e48f1 | 308 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 309 | else if (scaled_width < scaled_height) |
257e48f1 CW |
310 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
311 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
312 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 313 | } else { |
49be663f CW |
314 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
315 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
316 | /* |
317 | * For earlier chips we have to calculate the scaling | |
318 | * ratio by hand and program it into the | |
319 | * PFIT_PGM_RATIO register | |
320 | */ | |
49be663f CW |
321 | if (scaled_width > scaled_height) { /* pillar */ |
322 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
323 | ||
324 | border = LVDS_BORDER_ENABLE; | |
325 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
326 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
327 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
328 | bits << PFIT_VERT_SCALE_SHIFT); | |
329 | pfit_control |= (PFIT_ENABLE | | |
330 | VERT_INTERP_BILINEAR | | |
331 | HORIZ_INTERP_BILINEAR); | |
332 | } | |
333 | } else if (scaled_width < scaled_height) { /* letter */ | |
334 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
335 | ||
336 | border = LVDS_BORDER_ENABLE; | |
337 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
338 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
339 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
340 | bits << PFIT_VERT_SCALE_SHIFT); | |
341 | pfit_control |= (PFIT_ENABLE | | |
342 | VERT_INTERP_BILINEAR | | |
343 | HORIZ_INTERP_BILINEAR); | |
344 | } | |
345 | } else | |
346 | /* Aspects match, Let hw scale both directions */ | |
347 | pfit_control |= (PFIT_ENABLE | | |
348 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
349 | VERT_INTERP_BILINEAR | |
350 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
351 | } |
352 | break; | |
353 | ||
354 | case DRM_MODE_SCALE_FULLSCREEN: | |
355 | /* | |
356 | * Full scaling, even if it changes the aspect ratio. | |
357 | * Fortunately this is all done for us in hw. | |
358 | */ | |
257e48f1 CW |
359 | if (mode->vdisplay != adjusted_mode->vdisplay || |
360 | mode->hdisplay != adjusted_mode->hdisplay) { | |
361 | pfit_control |= PFIT_ENABLE; | |
362 | if (INTEL_INFO(dev)->gen >= 4) | |
363 | pfit_control |= PFIT_SCALING_AUTO; | |
364 | else | |
365 | pfit_control |= (VERT_AUTO_SCALE | | |
366 | VERT_INTERP_BILINEAR | | |
367 | HORIZ_AUTO_SCALE | | |
368 | HORIZ_INTERP_BILINEAR); | |
369 | } | |
3fbe18d6 | 370 | break; |
49be663f | 371 | |
3fbe18d6 ZY |
372 | default: |
373 | break; | |
374 | } | |
375 | ||
376 | out: | |
bee17e5a CW |
377 | if ((pfit_control & PFIT_ENABLE) == 0) { |
378 | pfit_control = 0; | |
379 | pfit_pgm_ratios = 0; | |
380 | } | |
e9e331a8 CW |
381 | if (pfit_control != intel_lvds->pfit_control || |
382 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | |
383 | intel_lvds->pfit_control = pfit_control; | |
384 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
385 | intel_lvds->pfit_dirty = true; | |
386 | } | |
49be663f CW |
387 | dev_priv->lvds_border_bits = border; |
388 | ||
79e53945 JB |
389 | /* |
390 | * XXX: It would be nice to support lower refresh rates on the | |
391 | * panels to reduce power consumption, and perhaps match the | |
392 | * user's requested refresh rate. | |
393 | */ | |
394 | ||
395 | return true; | |
396 | } | |
397 | ||
398 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
399 | { | |
400 | struct drm_device *dev = encoder->dev; | |
401 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 402 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 403 | |
e9e331a8 CW |
404 | /* We try to do the minimum that is necessary in order to unlock |
405 | * the registers for mode setting. | |
406 | * | |
407 | * On Ironlake, this is quite simple as we just set the unlock key | |
408 | * and ignore all subtleties. (This may cause some issues...) | |
409 | * | |
410 | * Prior to Ironlake, we must disable the pipe if we want to adjust | |
411 | * the panel fitter. However at all other times we can just reset | |
412 | * the registers regardless. | |
413 | */ | |
414 | ||
415 | if (HAS_PCH_SPLIT(dev)) { | |
416 | I915_WRITE(PCH_PP_CONTROL, | |
417 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
418 | } else if (intel_lvds->pfit_dirty) { | |
419 | I915_WRITE(PP_CONTROL, | |
4fd21dc8 CW |
420 | (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS) |
421 | & ~POWER_TARGET_ON); | |
e9e331a8 CW |
422 | } else { |
423 | I915_WRITE(PP_CONTROL, | |
424 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
425 | } | |
79e53945 JB |
426 | } |
427 | ||
e9e331a8 | 428 | static void intel_lvds_commit(struct drm_encoder *encoder) |
79e53945 JB |
429 | { |
430 | struct drm_device *dev = encoder->dev; | |
431 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 432 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 433 | |
e9e331a8 CW |
434 | /* Undo any unlocking done in prepare to prevent accidental |
435 | * adjustment of the registers. | |
436 | */ | |
437 | if (HAS_PCH_SPLIT(dev)) { | |
438 | u32 val = I915_READ(PCH_PP_CONTROL); | |
439 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
440 | I915_WRITE(PCH_PP_CONTROL, val & 0x3); | |
441 | } else { | |
442 | u32 val = I915_READ(PP_CONTROL); | |
443 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
444 | I915_WRITE(PP_CONTROL, val & 0x3); | |
445 | } | |
446 | ||
447 | /* Always do a full power on as we do not know what state | |
448 | * we were left in. | |
449 | */ | |
2a1292fd | 450 | intel_lvds_enable(intel_lvds); |
79e53945 JB |
451 | } |
452 | ||
453 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
454 | struct drm_display_mode *mode, | |
455 | struct drm_display_mode *adjusted_mode) | |
456 | { | |
79e53945 JB |
457 | /* |
458 | * The LVDS pin pair will already have been turned on in the | |
459 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
460 | * settings. | |
461 | */ | |
79e53945 JB |
462 | } |
463 | ||
464 | /** | |
465 | * Detect the LVDS connection. | |
466 | * | |
b42d4c5c JB |
467 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
468 | * connected and closed means disconnected. We also send hotplug events as | |
469 | * needed, using lid status notification from the input layer. | |
79e53945 | 470 | */ |
7b334fcb | 471 | static enum drm_connector_status |
930a9e28 | 472 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 473 | { |
7b9c5abe | 474 | struct drm_device *dev = connector->dev; |
01fe9dbd | 475 | struct drm_i915_private *dev_priv = dev->dev_private; |
b42d4c5c JB |
476 | enum drm_connector_status status = connector_status_connected; |
477 | ||
01fe9dbd CW |
478 | /* Assume that the BIOS does not lie through the OpRegion... */ |
479 | if (dev_priv->opregion.lid_state) | |
480 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? | |
481 | connector_status_connected : | |
482 | connector_status_disconnected; | |
483 | ||
7b9c5abe JB |
484 | /* ACPI lid methods were generally unreliable in this generation, so |
485 | * don't even bother. | |
486 | */ | |
6e6c8228 | 487 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
488 | return connector_status_connected; |
489 | ||
b42d4c5c | 490 | return status; |
79e53945 JB |
491 | } |
492 | ||
493 | /** | |
494 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
495 | */ | |
496 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
497 | { | |
788319d4 | 498 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
79e53945 | 499 | struct drm_device *dev = connector->dev; |
788319d4 | 500 | struct drm_display_mode *mode; |
79e53945 | 501 | |
3f8ff0e7 | 502 | if (intel_lvds->edid) |
219adae1 | 503 | return drm_add_edid_modes(connector, intel_lvds->edid); |
79e53945 | 504 | |
788319d4 CW |
505 | mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); |
506 | if (mode == 0) | |
507 | return 0; | |
79e53945 | 508 | |
788319d4 CW |
509 | drm_mode_probed_add(connector, mode); |
510 | return 1; | |
79e53945 JB |
511 | } |
512 | ||
0544edfd TB |
513 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
514 | { | |
515 | DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); | |
516 | return 1; | |
517 | } | |
518 | ||
519 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
520 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
521 | { | |
522 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
523 | .ident = "Toshiba Tecra A11", | |
524 | .matches = { | |
525 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
526 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
527 | }, | |
528 | }, | |
529 | ||
530 | { } /* terminating entry */ | |
531 | }; | |
532 | ||
c9354c85 LT |
533 | /* |
534 | * Lid events. Note the use of 'modeset_on_lid': | |
535 | * - we set it on lid close, and reset it on open | |
536 | * - we use it as a "only once" bit (ie we ignore | |
537 | * duplicate events where it was already properly | |
538 | * set/reset) | |
539 | * - the suspend/resume paths will also set it to | |
540 | * zero, since they restore the mode ("lid open"). | |
541 | */ | |
c1c7af60 JB |
542 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
543 | void *unused) | |
544 | { | |
545 | struct drm_i915_private *dev_priv = | |
546 | container_of(nb, struct drm_i915_private, lid_notifier); | |
547 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 548 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 549 | |
a2565377 ZY |
550 | /* |
551 | * check and update the status of LVDS connector after receiving | |
552 | * the LID nofication event. | |
553 | */ | |
554 | if (connector) | |
7b334fcb | 555 | connector->status = connector->funcs->detect(connector, |
930a9e28 | 556 | false); |
7b334fcb | 557 | |
0544edfd TB |
558 | /* Don't force modeset on machines where it causes a GPU lockup */ |
559 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
560 | return NOTIFY_OK; | |
c9354c85 LT |
561 | if (!acpi_lid_open()) { |
562 | dev_priv->modeset_on_lid = 1; | |
563 | return NOTIFY_OK; | |
06891e27 | 564 | } |
c1c7af60 | 565 | |
c9354c85 LT |
566 | if (!dev_priv->modeset_on_lid) |
567 | return NOTIFY_OK; | |
568 | ||
569 | dev_priv->modeset_on_lid = 0; | |
570 | ||
571 | mutex_lock(&dev->mode_config.mutex); | |
572 | drm_helper_resume_force_mode(dev); | |
573 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 574 | |
c1c7af60 JB |
575 | return NOTIFY_OK; |
576 | } | |
577 | ||
79e53945 JB |
578 | /** |
579 | * intel_lvds_destroy - unregister and free LVDS structures | |
580 | * @connector: connector to free | |
581 | * | |
582 | * Unregister the DDC bus for this connector then free the driver private | |
583 | * structure. | |
584 | */ | |
585 | static void intel_lvds_destroy(struct drm_connector *connector) | |
586 | { | |
c1c7af60 | 587 | struct drm_device *dev = connector->dev; |
c1c7af60 | 588 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 589 | |
c1c7af60 JB |
590 | if (dev_priv->lid_notifier.notifier_call) |
591 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
592 | drm_sysfs_connector_remove(connector); |
593 | drm_connector_cleanup(connector); | |
594 | kfree(connector); | |
595 | } | |
596 | ||
335041ed JB |
597 | static int intel_lvds_set_property(struct drm_connector *connector, |
598 | struct drm_property *property, | |
599 | uint64_t value) | |
600 | { | |
788319d4 | 601 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
3fbe18d6 | 602 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 603 | |
788319d4 CW |
604 | if (property == dev->mode_config.scaling_mode_property) { |
605 | struct drm_crtc *crtc = intel_lvds->base.base.crtc; | |
bb8a3560 | 606 | |
53bd8389 JB |
607 | if (value == DRM_MODE_SCALE_NONE) { |
608 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 609 | return -EINVAL; |
3fbe18d6 | 610 | } |
788319d4 | 611 | |
ea5b213a | 612 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
613 | /* the LVDS scaling property is not changed */ |
614 | return 0; | |
615 | } | |
ea5b213a | 616 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
617 | if (crtc && crtc->enabled) { |
618 | /* | |
619 | * If the CRTC is enabled, the display will be changed | |
620 | * according to the new panel fitting mode. | |
621 | */ | |
622 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
623 | crtc->x, crtc->y, crtc->fb); | |
624 | } | |
625 | } | |
626 | ||
335041ed JB |
627 | return 0; |
628 | } | |
629 | ||
79e53945 JB |
630 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
631 | .dpms = intel_lvds_dpms, | |
632 | .mode_fixup = intel_lvds_mode_fixup, | |
633 | .prepare = intel_lvds_prepare, | |
634 | .mode_set = intel_lvds_mode_set, | |
635 | .commit = intel_lvds_commit, | |
636 | }; | |
637 | ||
638 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
639 | .get_modes = intel_lvds_get_modes, | |
640 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 641 | .best_encoder = intel_best_encoder, |
79e53945 JB |
642 | }; |
643 | ||
644 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 645 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
646 | .detect = intel_lvds_detect, |
647 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 648 | .set_property = intel_lvds_set_property, |
79e53945 JB |
649 | .destroy = intel_lvds_destroy, |
650 | }; | |
651 | ||
79e53945 | 652 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 653 | .destroy = intel_encoder_destroy, |
79e53945 JB |
654 | }; |
655 | ||
425d244c JW |
656 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
657 | { | |
8a4c47f3 | 658 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
659 | return 1; |
660 | } | |
79e53945 | 661 | |
425d244c | 662 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 663 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
664 | { |
665 | .callback = intel_no_lvds_dmi_callback, | |
666 | .ident = "Apple Mac Mini (Core series)", | |
667 | .matches = { | |
98acd46f | 668 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
669 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
670 | }, | |
671 | }, | |
672 | { | |
673 | .callback = intel_no_lvds_dmi_callback, | |
674 | .ident = "Apple Mac Mini (Core 2 series)", | |
675 | .matches = { | |
98acd46f | 676 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
677 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
678 | }, | |
679 | }, | |
680 | { | |
681 | .callback = intel_no_lvds_dmi_callback, | |
682 | .ident = "MSI IM-945GSE-A", | |
683 | .matches = { | |
684 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
685 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
686 | }, | |
687 | }, | |
688 | { | |
689 | .callback = intel_no_lvds_dmi_callback, | |
690 | .ident = "Dell Studio Hybrid", | |
691 | .matches = { | |
692 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
693 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
694 | }, | |
695 | }, | |
70aa96ca JW |
696 | { |
697 | .callback = intel_no_lvds_dmi_callback, | |
698 | .ident = "AOpen Mini PC", | |
699 | .matches = { | |
700 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
701 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
702 | }, | |
703 | }, | |
ed8c754b TV |
704 | { |
705 | .callback = intel_no_lvds_dmi_callback, | |
706 | .ident = "AOpen Mini PC MP915", | |
707 | .matches = { | |
708 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
709 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
710 | }, | |
711 | }, | |
22ab70d3 KP |
712 | { |
713 | .callback = intel_no_lvds_dmi_callback, | |
714 | .ident = "AOpen i915GMm-HFS", | |
715 | .matches = { | |
716 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
717 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
718 | }, | |
719 | }, | |
fa0864b2 MC |
720 | { |
721 | .callback = intel_no_lvds_dmi_callback, | |
722 | .ident = "Aopen i945GTt-VFA", | |
723 | .matches = { | |
724 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
725 | }, | |
726 | }, | |
9875557e SB |
727 | { |
728 | .callback = intel_no_lvds_dmi_callback, | |
729 | .ident = "Clientron U800", | |
730 | .matches = { | |
731 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
732 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
733 | }, | |
734 | }, | |
425d244c JW |
735 | |
736 | { } /* terminating entry */ | |
737 | }; | |
79e53945 | 738 | |
18f9ed12 ZY |
739 | /** |
740 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
741 | * @dev: drm device | |
742 | * @connector: LVDS connector | |
743 | * | |
744 | * Find the reduced downclock for LVDS in EDID. | |
745 | */ | |
746 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
747 | struct drm_display_mode *fixed_mode, |
748 | struct drm_connector *connector) | |
18f9ed12 ZY |
749 | { |
750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 751 | struct drm_display_mode *scan; |
18f9ed12 ZY |
752 | int temp_downclock; |
753 | ||
788319d4 | 754 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
755 | list_for_each_entry(scan, &connector->probed_modes, head) { |
756 | /* | |
757 | * If one mode has the same resolution with the fixed_panel | |
758 | * mode while they have the different refresh rate, it means | |
759 | * that the reduced downclock is found for the LVDS. In such | |
760 | * case we can set the different FPx0/1 to dynamically select | |
761 | * between low and high frequency. | |
762 | */ | |
788319d4 CW |
763 | if (scan->hdisplay == fixed_mode->hdisplay && |
764 | scan->hsync_start == fixed_mode->hsync_start && | |
765 | scan->hsync_end == fixed_mode->hsync_end && | |
766 | scan->htotal == fixed_mode->htotal && | |
767 | scan->vdisplay == fixed_mode->vdisplay && | |
768 | scan->vsync_start == fixed_mode->vsync_start && | |
769 | scan->vsync_end == fixed_mode->vsync_end && | |
770 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
771 | if (scan->clock < temp_downclock) { |
772 | /* | |
773 | * The downclock is already found. But we | |
774 | * expect to find the lower downclock. | |
775 | */ | |
776 | temp_downclock = scan->clock; | |
777 | } | |
778 | } | |
779 | } | |
788319d4 | 780 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
781 | /* We found the downclock for LVDS. */ |
782 | dev_priv->lvds_downclock_avail = 1; | |
783 | dev_priv->lvds_downclock = temp_downclock; | |
784 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
785 | "Normal clock %dKhz, downclock %dKhz\n", |
786 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 787 | } |
18f9ed12 ZY |
788 | } |
789 | ||
7cf4f69d ZY |
790 | /* |
791 | * Enumerate the child dev array parsed from VBT to check whether | |
792 | * the LVDS is present. | |
793 | * If it is present, return 1. | |
794 | * If it is not present, return false. | |
795 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 796 | */ |
270eea0f CW |
797 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
798 | u8 *i2c_pin) | |
7cf4f69d ZY |
799 | { |
800 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 801 | int i; |
7cf4f69d ZY |
802 | |
803 | if (!dev_priv->child_dev_num) | |
425904dd | 804 | return true; |
7cf4f69d | 805 | |
7cf4f69d | 806 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
807 | struct child_device_config *child = dev_priv->child_dev + i; |
808 | ||
809 | /* If the device type is not LFP, continue. | |
810 | * We have to check both the new identifiers as well as the | |
811 | * old for compatibility with some BIOSes. | |
7cf4f69d | 812 | */ |
425904dd CW |
813 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
814 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
815 | continue; |
816 | ||
270eea0f CW |
817 | if (child->i2c_pin) |
818 | *i2c_pin = child->i2c_pin; | |
819 | ||
425904dd CW |
820 | /* However, we cannot trust the BIOS writers to populate |
821 | * the VBT correctly. Since LVDS requires additional | |
822 | * information from AIM blocks, a non-zero addin offset is | |
823 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 824 | */ |
425904dd CW |
825 | if (child->addin_offset) |
826 | return true; | |
827 | ||
828 | /* But even then some BIOS writers perform some black magic | |
829 | * and instantiate the device without reference to any | |
830 | * additional data. Trust that if the VBT was written into | |
831 | * the OpRegion then they have validated the LVDS's existence. | |
832 | */ | |
833 | if (dev_priv->opregion.vbt) | |
834 | return true; | |
7cf4f69d | 835 | } |
425904dd CW |
836 | |
837 | return false; | |
7cf4f69d ZY |
838 | } |
839 | ||
270eea0f | 840 | static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin) |
428d2e82 CW |
841 | { |
842 | struct drm_i915_private *dev_priv = dev->dev_private; | |
843 | u8 buf = 0; | |
844 | struct i2c_msg msgs[] = { | |
845 | { | |
846 | .addr = 0xA0, | |
847 | .flags = 0, | |
848 | .len = 1, | |
849 | .buf = &buf, | |
850 | }, | |
851 | }; | |
270eea0f | 852 | struct i2c_adapter *i2c = &dev_priv->gmbus[pin].adapter; |
b8232e90 CW |
853 | /* XXX this only appears to work when using GMBUS */ |
854 | if (intel_gmbus_is_forced_bit(i2c)) | |
855 | return true; | |
428d2e82 CW |
856 | return i2c_transfer(i2c, msgs, 1) == 1; |
857 | } | |
858 | ||
79e53945 JB |
859 | /** |
860 | * intel_lvds_init - setup LVDS connectors on this device | |
861 | * @dev: drm device | |
862 | * | |
863 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
864 | * modes we can display on the LVDS panel (if present). | |
865 | */ | |
c5d1b51d | 866 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
867 | { |
868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 869 | struct intel_lvds *intel_lvds; |
21d40d37 | 870 | struct intel_encoder *intel_encoder; |
bb8a3560 | 871 | struct intel_connector *intel_connector; |
79e53945 JB |
872 | struct drm_connector *connector; |
873 | struct drm_encoder *encoder; | |
874 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
875 | struct drm_crtc *crtc; | |
876 | u32 lvds; | |
270eea0f CW |
877 | int pipe; |
878 | u8 pin; | |
79e53945 | 879 | |
425d244c JW |
880 | /* Skip init on machines we know falsely report LVDS */ |
881 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 882 | return false; |
565dcd46 | 883 | |
270eea0f CW |
884 | pin = GMBUS_PORT_PANEL; |
885 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 886 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 887 | return false; |
38b3037e | 888 | } |
e99da35f | 889 | |
c619eed4 | 890 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 891 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 892 | return false; |
5ceb0f9b | 893 | if (dev_priv->edp.support) { |
28c97730 | 894 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 895 | return false; |
32f9d658 | 896 | } |
541998a1 ZW |
897 | } |
898 | ||
270eea0f | 899 | if (!intel_lvds_ddc_probe(dev, pin)) { |
428d2e82 | 900 | DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n"); |
c5d1b51d | 901 | return false; |
428d2e82 CW |
902 | } |
903 | ||
ea5b213a CW |
904 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
905 | if (!intel_lvds) { | |
c5d1b51d | 906 | return false; |
79e53945 JB |
907 | } |
908 | ||
bb8a3560 ZW |
909 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
910 | if (!intel_connector) { | |
ea5b213a | 911 | kfree(intel_lvds); |
c5d1b51d | 912 | return false; |
bb8a3560 ZW |
913 | } |
914 | ||
e9e331a8 CW |
915 | if (!HAS_PCH_SPLIT(dev)) { |
916 | intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); | |
917 | } | |
918 | ||
ea5b213a | 919 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 920 | encoder = &intel_encoder->base; |
ea5b213a | 921 | connector = &intel_connector->base; |
bb8a3560 | 922 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
923 | DRM_MODE_CONNECTOR_LVDS); |
924 | ||
4ef69c7a | 925 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
926 | DRM_MODE_ENCODER_LVDS); |
927 | ||
df0e9248 | 928 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 929 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 930 | |
21d40d37 EA |
931 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
932 | intel_encoder->crtc_mask = (1 << 1); | |
4add75c4 CW |
933 | if (INTEL_INFO(dev)->gen >= 5) |
934 | intel_encoder->crtc_mask |= (1 << 0); | |
79e53945 JB |
935 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
936 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
937 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
938 | connector->interlace_allowed = false; | |
939 | connector->doublescan_allowed = false; | |
940 | ||
3fbe18d6 ZY |
941 | /* create the scaling mode property */ |
942 | drm_mode_create_scaling_mode_property(dev); | |
943 | /* | |
944 | * the initial panel fitting mode will be FULL_SCREEN. | |
945 | */ | |
79e53945 | 946 | |
bb8a3560 | 947 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 948 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 949 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 950 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
951 | /* |
952 | * LVDS discovery: | |
953 | * 1) check for EDID on DDC | |
954 | * 2) check for VBT data | |
955 | * 3) check to see if LVDS is already on | |
956 | * if none of the above, no panel | |
957 | * 4) make sure lid is open | |
958 | * if closed, act like it's not there for now | |
959 | */ | |
960 | ||
79e53945 JB |
961 | /* |
962 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
963 | * preferred mode is the right one. | |
964 | */ | |
219adae1 | 965 | intel_lvds->edid = drm_get_edid(connector, |
270eea0f | 966 | &dev_priv->gmbus[pin].adapter); |
3f8ff0e7 CW |
967 | if (intel_lvds->edid) { |
968 | if (drm_add_edid_modes(connector, | |
969 | intel_lvds->edid)) { | |
970 | drm_mode_connector_update_edid_property(connector, | |
971 | intel_lvds->edid); | |
972 | } else { | |
973 | kfree(intel_lvds->edid); | |
974 | intel_lvds->edid = NULL; | |
975 | } | |
976 | } | |
219adae1 | 977 | if (!intel_lvds->edid) { |
788319d4 CW |
978 | /* Didn't get an EDID, so |
979 | * Set wide sync ranges so we get all modes | |
980 | * handed to valid_mode for checking | |
981 | */ | |
982 | connector->display_info.min_vfreq = 0; | |
983 | connector->display_info.max_vfreq = 200; | |
984 | connector->display_info.min_hfreq = 0; | |
985 | connector->display_info.max_hfreq = 200; | |
986 | } | |
79e53945 JB |
987 | |
988 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 989 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
788319d4 | 990 | intel_lvds->fixed_mode = |
79e53945 | 991 | drm_mode_duplicate(dev, scan); |
788319d4 CW |
992 | intel_find_lvds_downclock(dev, |
993 | intel_lvds->fixed_mode, | |
994 | connector); | |
565dcd46 | 995 | goto out; |
79e53945 | 996 | } |
79e53945 JB |
997 | } |
998 | ||
999 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1000 | if (dev_priv->lfp_lvds_vbt_mode) { |
788319d4 | 1001 | intel_lvds->fixed_mode = |
88631706 | 1002 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
788319d4 CW |
1003 | if (intel_lvds->fixed_mode) { |
1004 | intel_lvds->fixed_mode->type |= | |
e285f3cd | 1005 | DRM_MODE_TYPE_PREFERRED; |
e285f3cd JB |
1006 | goto out; |
1007 | } | |
79e53945 JB |
1008 | } |
1009 | ||
1010 | /* | |
1011 | * If we didn't get EDID, try checking if the panel is already turned | |
1012 | * on. If so, assume that whatever is currently programmed is the | |
1013 | * correct mode. | |
1014 | */ | |
541998a1 | 1015 | |
f2b115e6 | 1016 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1017 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1018 | goto failed; |
1019 | ||
79e53945 JB |
1020 | lvds = I915_READ(LVDS); |
1021 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1022 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1023 | |
1024 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
788319d4 CW |
1025 | intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); |
1026 | if (intel_lvds->fixed_mode) { | |
1027 | intel_lvds->fixed_mode->type |= | |
79e53945 | 1028 | DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1029 | goto out; |
79e53945 JB |
1030 | } |
1031 | } | |
1032 | ||
1033 | /* If we still don't have a mode after all that, give up. */ | |
788319d4 | 1034 | if (!intel_lvds->fixed_mode) |
79e53945 JB |
1035 | goto failed; |
1036 | ||
79e53945 | 1037 | out: |
c619eed4 | 1038 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1039 | u32 pwm; |
17fe6981 CW |
1040 | |
1041 | pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1042 | ||
1043 | /* make sure PWM is enabled and locked to the LVDS pipe */ | |
541998a1 | 1044 | pwm = I915_READ(BLC_PWM_CPU_CTL2); |
17fe6981 CW |
1045 | if (pipe == 0 && (pwm & PWM_PIPE_B)) |
1046 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); | |
1047 | if (pipe) | |
1048 | pwm |= PWM_PIPE_B; | |
1049 | else | |
1050 | pwm &= ~PWM_PIPE_B; | |
1051 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); | |
541998a1 ZW |
1052 | |
1053 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1054 | pwm |= PWM_PCH_ENABLE; | |
1055 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
1056 | } | |
c1c7af60 JB |
1057 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1058 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1059 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1060 | dev_priv->lid_notifier.notifier_call = NULL; |
1061 | } | |
a2565377 ZY |
1062 | /* keep the LVDS connector */ |
1063 | dev_priv->int_lvds_connector = connector; | |
79e53945 | 1064 | drm_sysfs_connector_add(connector); |
c5d1b51d | 1065 | return true; |
79e53945 JB |
1066 | |
1067 | failed: | |
8a4c47f3 | 1068 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1069 | drm_connector_cleanup(connector); |
1991bdfa | 1070 | drm_encoder_cleanup(encoder); |
ea5b213a | 1071 | kfree(intel_lvds); |
bb8a3560 | 1072 | kfree(intel_connector); |
c5d1b51d | 1073 | return false; |
79e53945 | 1074 | } |