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drm/i915: factor out GMCH panel fitting code and use for eDP v3
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
fc683091
DV
89/* The LVDS pin pair needs to be on before the DPLLs are enabled.
90 * This is an exception to the general rule that mode_set doesn't turn
91 * things on.
92 */
93static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
94{
95 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
96 struct drm_device *dev = encoder->base.dev;
97 struct drm_i915_private *dev_priv = dev->dev_private;
98 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
99 struct drm_display_mode *fixed_mode =
100 lvds_encoder->attached_connector->base.panel.fixed_mode;
101 int pipe = intel_crtc->pipe;
102 u32 temp;
103
fc683091
DV
104 temp = I915_READ(lvds_encoder->reg);
105 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
106
107 if (HAS_PCH_CPT(dev)) {
108 temp &= ~PORT_TRANS_SEL_MASK;
109 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 110 } else {
62810e5a
DV
111 if (pipe == 1) {
112 temp |= LVDS_PIPEB_SELECT;
113 } else {
114 temp &= ~LVDS_PIPEB_SELECT;
115 }
fc683091 116 }
62810e5a 117
fc683091
DV
118 /* set the corresponsding LVDS_BORDER bit */
119 temp |= dev_priv->lvds_border_bits;
120 /* Set the B0-B3 data pairs corresponding to whether we're going to
121 * set the DPLLs for dual-channel mode or not.
122 */
123 if (lvds_encoder->is_dual_link)
124 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
125 else
126 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
127
128 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
129 * appropriately here, but we need to look more thoroughly into how
130 * panels behave in the two modes.
131 */
62810e5a
DV
132
133 /* Set the dithering flag on LVDS as needed, note that there is no
134 * special lvds dither control bit on pch-split platforms, dithering is
135 * only controlled through the PIPECONF reg. */
136 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
137 /* Bspec wording suggests that LVDS port dithering only exists
138 * for 18bpp panels. */
139 if (intel_crtc->config.dither &&
140 intel_crtc->config.pipe_bpp == 18)
fc683091
DV
141 temp |= LVDS_ENABLE_DITHER;
142 else
143 temp &= ~LVDS_ENABLE_DITHER;
144 }
145 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
146 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
147 temp |= LVDS_HSYNC_POLARITY;
148 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
149 temp |= LVDS_VSYNC_POLARITY;
150
151 I915_WRITE(lvds_encoder->reg, temp);
152}
153
79e53945
JB
154/**
155 * Sets the power state for the panel.
156 */
c22834ec 157static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 158{
c22834ec 159 struct drm_device *dev = encoder->base.dev;
29b99b48 160 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 161 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 162 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 163 u32 ctl_reg, stat_reg;
541998a1 164
c619eed4 165 if (HAS_PCH_SPLIT(dev)) {
541998a1 166 ctl_reg = PCH_PP_CONTROL;
de842eff 167 stat_reg = PCH_PP_STATUS;
541998a1
ZW
168 } else {
169 ctl_reg = PP_CONTROL;
de842eff 170 stat_reg = PP_STATUS;
541998a1 171 }
79e53945 172
7dec0606 173 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 174
2a1292fd 175 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 176 POSTING_READ(lvds_encoder->reg);
de842eff
KP
177 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
178 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 179
24ded204 180 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
181}
182
c22834ec 183static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 184{
c22834ec 185 struct drm_device *dev = encoder->base.dev;
29b99b48 186 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 187 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 188 u32 ctl_reg, stat_reg;
2a1292fd
CW
189
190 if (HAS_PCH_SPLIT(dev)) {
191 ctl_reg = PCH_PP_CONTROL;
de842eff 192 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
193 } else {
194 ctl_reg = PP_CONTROL;
de842eff 195 stat_reg = PP_STATUS;
2a1292fd
CW
196 }
197
47356eb6 198 intel_panel_disable_backlight(dev);
2a1292fd
CW
199
200 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
201 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
202 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 203
7dec0606
DV
204 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
205 POSTING_READ(lvds_encoder->reg);
79e53945
JB
206}
207
79e53945
JB
208static int intel_lvds_mode_valid(struct drm_connector *connector,
209 struct drm_display_mode *mode)
210{
dd06f90e
JN
211 struct intel_connector *intel_connector = to_intel_connector(connector);
212 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 213
788319d4
CW
214 if (mode->hdisplay > fixed_mode->hdisplay)
215 return MODE_PANEL;
216 if (mode->vdisplay > fixed_mode->vdisplay)
217 return MODE_PANEL;
79e53945
JB
218
219 return MODE_OK;
220}
221
7ae89233
DV
222static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
223 struct intel_crtc_config *pipe_config)
79e53945 224{
7ae89233 225 struct drm_device *dev = intel_encoder->base.dev;
79e53945 226 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
227 struct intel_lvds_encoder *lvds_encoder =
228 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
229 struct intel_connector *intel_connector =
230 &lvds_encoder->attached_connector->base;
7ae89233
DV
231 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
232 struct drm_display_mode *mode = &pipe_config->requested_mode;
29b99b48 233 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 234 unsigned int lvds_bpp;
9db4a9c7 235 int pipe;
79e53945
JB
236
237 /* Should never happen!! */
a6c45cf0 238 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 239 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
240 return false;
241 }
242
29b99b48 243 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 244 return false;
1d8e1c75 245
4e53c2e0
DV
246 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
247 LVDS_A3_POWER_UP)
248 lvds_bpp = 8*3;
249 else
250 lvds_bpp = 6*3;
251
252 if (lvds_bpp != pipe_config->pipe_bpp) {
253 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
254 pipe_config->pipe_bpp, lvds_bpp);
255 pipe_config->pipe_bpp = lvds_bpp;
256 }
d8b32247 257
79e53945 258 /*
71677043 259 * We have timings from the BIOS for the panel, put them in
79e53945
JB
260 * to the adjusted mode. The CRTC will be set up for this mode,
261 * with the panel scaling set up to source from the H/VDisplay
262 * of the original mode.
263 */
4d891523 264 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 265 adjusted_mode);
1d8e1c75
CW
266
267 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
268 pipe_config->has_pch_encoder = true;
269
4d891523
JN
270 intel_pch_panel_fitting(dev,
271 intel_connector->panel.fitting_mode,
1d8e1c75
CW
272 mode, adjusted_mode);
273 return true;
2dd24552
JB
274 } else {
275 intel_gmch_panel_fitting(intel_crtc, pipe_config,
276 intel_connector->panel.fitting_mode);
1d8e1c75 277 }
79e53945 278
3fbe18d6
ZY
279 /*
280 * Enable automatic panel scaling for non-native modes so that they fill
281 * the screen. Should be enabled before the pipe is enabled, according
282 * to register description and PRM.
283 * Change the value here to see the borders for debugging
284 */
9db4a9c7
JB
285 for_each_pipe(pipe)
286 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 287
f9bef081 288 drm_mode_set_crtcinfo(adjusted_mode, 0);
7ae89233 289 pipe_config->timings_set = true;
f9bef081 290
79e53945
JB
291 /*
292 * XXX: It would be nice to support lower refresh rates on the
293 * panels to reduce power consumption, and perhaps match the
294 * user's requested refresh rate.
295 */
296
297 return true;
298}
299
79e53945
JB
300static void intel_lvds_mode_set(struct drm_encoder *encoder,
301 struct drm_display_mode *mode,
302 struct drm_display_mode *adjusted_mode)
303{
79e53945
JB
304 /*
305 * The LVDS pin pair will already have been turned on in the
306 * intel_crtc_mode_set since it has a large impact on the DPLL
307 * settings.
308 */
79e53945
JB
309}
310
311/**
312 * Detect the LVDS connection.
313 *
b42d4c5c
JB
314 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
315 * connected and closed means disconnected. We also send hotplug events as
316 * needed, using lid status notification from the input layer.
79e53945 317 */
7b334fcb 318static enum drm_connector_status
930a9e28 319intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 320{
7b9c5abe 321 struct drm_device *dev = connector->dev;
6ee3b5a1 322 enum drm_connector_status status;
b42d4c5c 323
fe16d949
CW
324 status = intel_panel_detect(dev);
325 if (status != connector_status_unknown)
326 return status;
01fe9dbd 327
6ee3b5a1 328 return connector_status_connected;
79e53945
JB
329}
330
331/**
332 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
333 */
334static int intel_lvds_get_modes(struct drm_connector *connector)
335{
62165e0d 336 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 337 struct drm_device *dev = connector->dev;
788319d4 338 struct drm_display_mode *mode;
79e53945 339
9cd300e0 340 /* use cached edid if we have one */
2aa4f099 341 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 342 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 343
dd06f90e 344 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 345 if (mode == NULL)
788319d4 346 return 0;
79e53945 347
788319d4
CW
348 drm_mode_probed_add(connector, mode);
349 return 1;
79e53945
JB
350}
351
0544edfd
TB
352static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
353{
bc0daf48 354 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
355 return 1;
356}
357
358/* The GPU hangs up on these systems if modeset is performed on LID open */
359static const struct dmi_system_id intel_no_modeset_on_lid[] = {
360 {
361 .callback = intel_no_modeset_on_lid_dmi_callback,
362 .ident = "Toshiba Tecra A11",
363 .matches = {
364 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
365 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
366 },
367 },
368
369 { } /* terminating entry */
370};
371
c9354c85 372/*
b8efb17b
ZR
373 * Lid events. Note the use of 'modeset':
374 * - we set it to MODESET_ON_LID_OPEN on lid close,
375 * and set it to MODESET_DONE on open
c9354c85 376 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
377 * duplicate events where it was already properly set)
378 * - the suspend/resume paths will set it to
379 * MODESET_SUSPENDED and ignore the lid open event,
380 * because they restore the mode ("lid open").
c9354c85 381 */
c1c7af60
JB
382static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
383 void *unused)
384{
db1740a0
JN
385 struct intel_lvds_connector *lvds_connector =
386 container_of(nb, struct intel_lvds_connector, lid_notifier);
387 struct drm_connector *connector = &lvds_connector->base.base;
388 struct drm_device *dev = connector->dev;
389 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 390
2fb4e61d
AW
391 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
392 return NOTIFY_OK;
393
b8efb17b
ZR
394 mutex_lock(&dev_priv->modeset_restore_lock);
395 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
396 goto exit;
a2565377
ZY
397 /*
398 * check and update the status of LVDS connector after receiving
399 * the LID nofication event.
400 */
db1740a0 401 connector->status = connector->funcs->detect(connector, false);
7b334fcb 402
0544edfd
TB
403 /* Don't force modeset on machines where it causes a GPU lockup */
404 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 405 goto exit;
c9354c85 406 if (!acpi_lid_open()) {
b8efb17b
ZR
407 /* do modeset on next lid open event */
408 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
409 goto exit;
06891e27 410 }
c1c7af60 411
b8efb17b
ZR
412 if (dev_priv->modeset_restore == MODESET_DONE)
413 goto exit;
c9354c85 414
a0e99e68 415 drm_modeset_lock_all(dev);
45e2b5f6 416 intel_modeset_setup_hw_state(dev, true);
a0e99e68 417 drm_modeset_unlock_all(dev);
06324194 418
b8efb17b
ZR
419 dev_priv->modeset_restore = MODESET_DONE;
420
421exit:
422 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
423 return NOTIFY_OK;
424}
425
79e53945
JB
426/**
427 * intel_lvds_destroy - unregister and free LVDS structures
428 * @connector: connector to free
429 *
430 * Unregister the DDC bus for this connector then free the driver private
431 * structure.
432 */
433static void intel_lvds_destroy(struct drm_connector *connector)
434{
db1740a0
JN
435 struct intel_lvds_connector *lvds_connector =
436 to_lvds_connector(connector);
79e53945 437
db1740a0
JN
438 if (lvds_connector->lid_notifier.notifier_call)
439 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 440
9cd300e0
JN
441 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
442 kfree(lvds_connector->base.edid);
443
1d508706 444 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 445
79e53945
JB
446 drm_sysfs_connector_remove(connector);
447 drm_connector_cleanup(connector);
448 kfree(connector);
449}
450
335041ed
JB
451static int intel_lvds_set_property(struct drm_connector *connector,
452 struct drm_property *property,
453 uint64_t value)
454{
4d891523 455 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 456 struct drm_device *dev = connector->dev;
3fbe18d6 457
788319d4 458 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 459 struct drm_crtc *crtc;
bb8a3560 460
53bd8389
JB
461 if (value == DRM_MODE_SCALE_NONE) {
462 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 463 return -EINVAL;
3fbe18d6 464 }
788319d4 465
4d891523 466 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
467 /* the LVDS scaling property is not changed */
468 return 0;
469 }
4d891523 470 intel_connector->panel.fitting_mode = value;
62165e0d
JN
471
472 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
473 if (crtc && crtc->enabled) {
474 /*
475 * If the CRTC is enabled, the display will be changed
476 * according to the new panel fitting mode.
477 */
c0c36b94 478 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
479 }
480 }
481
335041ed
JB
482 return 0;
483}
484
79e53945 485static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 486 .mode_set = intel_lvds_mode_set,
79e53945
JB
487};
488
489static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
490 .get_modes = intel_lvds_get_modes,
491 .mode_valid = intel_lvds_mode_valid,
df0e9248 492 .best_encoder = intel_best_encoder,
79e53945
JB
493};
494
495static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 496 .dpms = intel_connector_dpms,
79e53945
JB
497 .detect = intel_lvds_detect,
498 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 499 .set_property = intel_lvds_set_property,
79e53945
JB
500 .destroy = intel_lvds_destroy,
501};
502
79e53945 503static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 504 .destroy = intel_encoder_destroy,
79e53945
JB
505};
506
425d244c
JW
507static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
508{
bc0daf48 509 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
510 return 1;
511}
79e53945 512
425d244c 513/* These systems claim to have LVDS, but really don't */
93c05f22 514static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
515 {
516 .callback = intel_no_lvds_dmi_callback,
517 .ident = "Apple Mac Mini (Core series)",
518 .matches = {
98acd46f 519 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
520 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
521 },
522 },
523 {
524 .callback = intel_no_lvds_dmi_callback,
525 .ident = "Apple Mac Mini (Core 2 series)",
526 .matches = {
98acd46f 527 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
528 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
529 },
530 },
531 {
532 .callback = intel_no_lvds_dmi_callback,
533 .ident = "MSI IM-945GSE-A",
534 .matches = {
535 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
536 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
537 },
538 },
539 {
540 .callback = intel_no_lvds_dmi_callback,
541 .ident = "Dell Studio Hybrid",
542 .matches = {
543 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
544 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
545 },
546 },
70aa96ca
JW
547 {
548 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
549 .ident = "Dell OptiPlex FX170",
550 .matches = {
551 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
552 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
553 },
554 },
555 {
556 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
557 .ident = "AOpen Mini PC",
558 .matches = {
559 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
560 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
561 },
562 },
ed8c754b
TV
563 {
564 .callback = intel_no_lvds_dmi_callback,
565 .ident = "AOpen Mini PC MP915",
566 .matches = {
567 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
568 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
569 },
570 },
22ab70d3
KP
571 {
572 .callback = intel_no_lvds_dmi_callback,
573 .ident = "AOpen i915GMm-HFS",
574 .matches = {
575 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
576 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
577 },
578 },
e57b6886
DV
579 {
580 .callback = intel_no_lvds_dmi_callback,
581 .ident = "AOpen i45GMx-I",
582 .matches = {
583 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
584 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
585 },
586 },
fa0864b2
MC
587 {
588 .callback = intel_no_lvds_dmi_callback,
589 .ident = "Aopen i945GTt-VFA",
590 .matches = {
591 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
592 },
593 },
9875557e
SB
594 {
595 .callback = intel_no_lvds_dmi_callback,
596 .ident = "Clientron U800",
597 .matches = {
598 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
599 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
600 },
601 },
6a574b5b 602 {
44306ab3
JS
603 .callback = intel_no_lvds_dmi_callback,
604 .ident = "Clientron E830",
605 .matches = {
606 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
607 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
608 },
609 },
610 {
6a574b5b
HG
611 .callback = intel_no_lvds_dmi_callback,
612 .ident = "Asus EeeBox PC EB1007",
613 .matches = {
614 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
615 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
616 },
617 },
0999bbe0
AJ
618 {
619 .callback = intel_no_lvds_dmi_callback,
620 .ident = "Asus AT5NM10T-I",
621 .matches = {
622 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
623 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
624 },
625 },
33471119
JBG
626 {
627 .callback = intel_no_lvds_dmi_callback,
628 .ident = "Hewlett-Packard HP t5740e Thin Client",
629 .matches = {
630 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
631 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
632 },
633 },
f5b8a7ed
MG
634 {
635 .callback = intel_no_lvds_dmi_callback,
636 .ident = "Hewlett-Packard t5745",
637 .matches = {
638 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 639 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
640 },
641 },
642 {
643 .callback = intel_no_lvds_dmi_callback,
644 .ident = "Hewlett-Packard st5747",
645 .matches = {
646 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 647 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
648 },
649 },
97effadb
AA
650 {
651 .callback = intel_no_lvds_dmi_callback,
652 .ident = "MSI Wind Box DC500",
653 .matches = {
654 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
655 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
656 },
657 },
a51d4ed0
CW
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Gigabyte GA-D525TUD",
661 .matches = {
662 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
663 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
664 },
665 },
c31407a3
CW
666 {
667 .callback = intel_no_lvds_dmi_callback,
668 .ident = "Supermicro X7SPA-H",
669 .matches = {
670 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
671 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
672 },
673 },
9e9dd0e8
CL
674 {
675 .callback = intel_no_lvds_dmi_callback,
676 .ident = "Fujitsu Esprimo Q900",
677 .matches = {
678 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
679 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
680 },
681 },
425d244c
JW
682
683 { } /* terminating entry */
684};
79e53945 685
18f9ed12
ZY
686/**
687 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
688 * @dev: drm device
689 * @connector: LVDS connector
690 *
691 * Find the reduced downclock for LVDS in EDID.
692 */
693static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
694 struct drm_display_mode *fixed_mode,
695 struct drm_connector *connector)
18f9ed12
ZY
696{
697 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 698 struct drm_display_mode *scan;
18f9ed12
ZY
699 int temp_downclock;
700
788319d4 701 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
702 list_for_each_entry(scan, &connector->probed_modes, head) {
703 /*
704 * If one mode has the same resolution with the fixed_panel
705 * mode while they have the different refresh rate, it means
706 * that the reduced downclock is found for the LVDS. In such
707 * case we can set the different FPx0/1 to dynamically select
708 * between low and high frequency.
709 */
788319d4
CW
710 if (scan->hdisplay == fixed_mode->hdisplay &&
711 scan->hsync_start == fixed_mode->hsync_start &&
712 scan->hsync_end == fixed_mode->hsync_end &&
713 scan->htotal == fixed_mode->htotal &&
714 scan->vdisplay == fixed_mode->vdisplay &&
715 scan->vsync_start == fixed_mode->vsync_start &&
716 scan->vsync_end == fixed_mode->vsync_end &&
717 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
718 if (scan->clock < temp_downclock) {
719 /*
720 * The downclock is already found. But we
721 * expect to find the lower downclock.
722 */
723 temp_downclock = scan->clock;
724 }
725 }
726 }
788319d4 727 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
728 /* We found the downclock for LVDS. */
729 dev_priv->lvds_downclock_avail = 1;
730 dev_priv->lvds_downclock = temp_downclock;
731 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
732 "Normal clock %dKhz, downclock %dKhz\n",
733 fixed_mode->clock, temp_downclock);
18f9ed12 734 }
18f9ed12
ZY
735}
736
7cf4f69d
ZY
737/*
738 * Enumerate the child dev array parsed from VBT to check whether
739 * the LVDS is present.
740 * If it is present, return 1.
741 * If it is not present, return false.
742 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 743 */
270eea0f
CW
744static bool lvds_is_present_in_vbt(struct drm_device *dev,
745 u8 *i2c_pin)
7cf4f69d
ZY
746{
747 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 748 int i;
7cf4f69d
ZY
749
750 if (!dev_priv->child_dev_num)
425904dd 751 return true;
7cf4f69d 752
7cf4f69d 753 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
754 struct child_device_config *child = dev_priv->child_dev + i;
755
756 /* If the device type is not LFP, continue.
757 * We have to check both the new identifiers as well as the
758 * old for compatibility with some BIOSes.
7cf4f69d 759 */
425904dd
CW
760 if (child->device_type != DEVICE_TYPE_INT_LFP &&
761 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
762 continue;
763
3bd7d909
DK
764 if (intel_gmbus_is_port_valid(child->i2c_pin))
765 *i2c_pin = child->i2c_pin;
270eea0f 766
425904dd
CW
767 /* However, we cannot trust the BIOS writers to populate
768 * the VBT correctly. Since LVDS requires additional
769 * information from AIM blocks, a non-zero addin offset is
770 * a good indicator that the LVDS is actually present.
7cf4f69d 771 */
425904dd
CW
772 if (child->addin_offset)
773 return true;
774
775 /* But even then some BIOS writers perform some black magic
776 * and instantiate the device without reference to any
777 * additional data. Trust that if the VBT was written into
778 * the OpRegion then they have validated the LVDS's existence.
779 */
780 if (dev_priv->opregion.vbt)
781 return true;
7cf4f69d 782 }
425904dd
CW
783
784 return false;
7cf4f69d
ZY
785}
786
1974cad0
DV
787static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
788{
789 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
790 return 1;
791}
792
793static const struct dmi_system_id intel_dual_link_lvds[] = {
794 {
795 .callback = intel_dual_link_lvds_callback,
796 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
797 .matches = {
798 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
799 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
800 },
801 },
802 { } /* terminating entry */
803};
804
805bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
806{
807 struct intel_encoder *encoder;
808 struct intel_lvds_encoder *lvds_encoder;
809
810 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
811 base.head) {
812 if (encoder->type == INTEL_OUTPUT_LVDS) {
813 lvds_encoder = to_lvds_encoder(&encoder->base);
814
815 return lvds_encoder->is_dual_link;
816 }
817 }
818
819 return false;
820}
821
7dec0606 822static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 823{
7dec0606 824 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
825 unsigned int val;
826 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
827
828 /* use the module option value if specified */
829 if (i915_lvds_channel_mode > 0)
830 return i915_lvds_channel_mode == 2;
831
832 if (dmi_check_system(intel_dual_link_lvds))
833 return true;
834
13c7d870
DV
835 /* BIOS should set the proper LVDS register value at boot, but
836 * in reality, it doesn't set the value when the lid is closed;
837 * we need to check "the value to be set" in VBT when LVDS
838 * register is uninitialized.
839 */
7dec0606 840 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
841 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
842 val = dev_priv->bios_lvds_val;
843
1974cad0
DV
844 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
845}
846
f3cfcba6
CW
847static bool intel_lvds_supported(struct drm_device *dev)
848{
849 /* With the introduction of the PCH we gained a dedicated
850 * LVDS presence pin, use it. */
311e359c 851 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
852 return true;
853
854 /* Otherwise LVDS was only attached to mobile products,
855 * except for the inglorious 830gm */
311e359c
PZ
856 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
857 return true;
858
859 return false;
f3cfcba6
CW
860}
861
79e53945
JB
862/**
863 * intel_lvds_init - setup LVDS connectors on this device
864 * @dev: drm device
865 *
866 * Create the connector, register the LVDS DDC bus, and try to figure out what
867 * modes we can display on the LVDS panel (if present).
868 */
c5d1b51d 869bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
870{
871 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 872 struct intel_lvds_encoder *lvds_encoder;
21d40d37 873 struct intel_encoder *intel_encoder;
c7362c4d 874 struct intel_lvds_connector *lvds_connector;
bb8a3560 875 struct intel_connector *intel_connector;
79e53945
JB
876 struct drm_connector *connector;
877 struct drm_encoder *encoder;
878 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 879 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 880 struct edid *edid;
79e53945
JB
881 struct drm_crtc *crtc;
882 u32 lvds;
270eea0f
CW
883 int pipe;
884 u8 pin;
79e53945 885
f3cfcba6
CW
886 if (!intel_lvds_supported(dev))
887 return false;
888
425d244c
JW
889 /* Skip init on machines we know falsely report LVDS */
890 if (dmi_check_system(intel_no_lvds))
c5d1b51d 891 return false;
565dcd46 892
270eea0f
CW
893 pin = GMBUS_PORT_PANEL;
894 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 895 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 896 return false;
38b3037e 897 }
e99da35f 898
c619eed4 899 if (HAS_PCH_SPLIT(dev)) {
541998a1 900 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 901 return false;
5ceb0f9b 902 if (dev_priv->edp.support) {
28c97730 903 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 904 return false;
32f9d658 905 }
541998a1
ZW
906 }
907
29b99b48
JN
908 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
909 if (!lvds_encoder)
c5d1b51d 910 return false;
79e53945 911
c7362c4d
JN
912 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
913 if (!lvds_connector) {
29b99b48 914 kfree(lvds_encoder);
c5d1b51d 915 return false;
bb8a3560
ZW
916 }
917
62165e0d
JN
918 lvds_encoder->attached_connector = lvds_connector;
919
29b99b48 920 intel_encoder = &lvds_encoder->base;
4ef69c7a 921 encoder = &intel_encoder->base;
c7362c4d 922 intel_connector = &lvds_connector->base;
ea5b213a 923 connector = &intel_connector->base;
bb8a3560 924 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
925 DRM_MODE_CONNECTOR_LVDS);
926
4ef69c7a 927 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
928 DRM_MODE_ENCODER_LVDS);
929
c22834ec 930 intel_encoder->enable = intel_enable_lvds;
fc683091 931 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
7ae89233 932 intel_encoder->compute_config = intel_lvds_compute_config;
c22834ec 933 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
934 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
935 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 936
df0e9248 937 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 938 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 939
66a9278e 940 intel_encoder->cloneable = false;
27f8227b
JB
941 if (HAS_PCH_SPLIT(dev))
942 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
943 else if (IS_GEN4(dev))
944 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
945 else
946 intel_encoder->crtc_mask = (1 << 1);
947
79e53945
JB
948 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
949 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
950 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
951 connector->interlace_allowed = false;
952 connector->doublescan_allowed = false;
953
7dec0606
DV
954 if (HAS_PCH_SPLIT(dev)) {
955 lvds_encoder->reg = PCH_LVDS;
956 } else {
957 lvds_encoder->reg = LVDS;
958 }
959
3fbe18d6
ZY
960 /* create the scaling mode property */
961 drm_mode_create_scaling_mode_property(dev);
662595df 962 drm_object_attach_property(&connector->base,
3fbe18d6 963 dev->mode_config.scaling_mode_property,
dd1ea37d 964 DRM_MODE_SCALE_ASPECT);
4d891523 965 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
966 /*
967 * LVDS discovery:
968 * 1) check for EDID on DDC
969 * 2) check for VBT data
970 * 3) check to see if LVDS is already on
971 * if none of the above, no panel
972 * 4) make sure lid is open
973 * if closed, act like it's not there for now
974 */
975
79e53945
JB
976 /*
977 * Attempt to get the fixed panel mode from DDC. Assume that the
978 * preferred mode is the right one.
979 */
9cd300e0
JN
980 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
981 if (edid) {
982 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 983 drm_mode_connector_update_edid_property(connector,
9cd300e0 984 edid);
3f8ff0e7 985 } else {
9cd300e0
JN
986 kfree(edid);
987 edid = ERR_PTR(-EINVAL);
3f8ff0e7 988 }
9cd300e0
JN
989 } else {
990 edid = ERR_PTR(-ENOENT);
3f8ff0e7 991 }
9cd300e0
JN
992 lvds_connector->base.edid = edid;
993
994 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
995 /* Didn't get an EDID, so
996 * Set wide sync ranges so we get all modes
997 * handed to valid_mode for checking
998 */
999 connector->display_info.min_vfreq = 0;
1000 connector->display_info.max_vfreq = 200;
1001 connector->display_info.min_hfreq = 0;
1002 connector->display_info.max_hfreq = 200;
1003 }
79e53945
JB
1004
1005 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1006 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1007 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1008 drm_mode_debug_printmodeline(scan);
1009
dd06f90e 1010 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1011 if (fixed_mode) {
1012 intel_find_lvds_downclock(dev, fixed_mode,
1013 connector);
1014 goto out;
1015 }
79e53945 1016 }
79e53945
JB
1017 }
1018
1019 /* Failed to get EDID, what about VBT? */
88631706 1020 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1021 DRM_DEBUG_KMS("using mode from VBT: ");
1022 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1023
dd06f90e
JN
1024 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1025 if (fixed_mode) {
1026 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1027 goto out;
1028 }
79e53945
JB
1029 }
1030
1031 /*
1032 * If we didn't get EDID, try checking if the panel is already turned
1033 * on. If so, assume that whatever is currently programmed is the
1034 * correct mode.
1035 */
541998a1 1036
f2b115e6 1037 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1038 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1039 goto failed;
1040
79e53945
JB
1041 lvds = I915_READ(LVDS);
1042 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1043 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1044
1045 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1046 fixed_mode = intel_crtc_mode_get(dev, crtc);
1047 if (fixed_mode) {
6a9d51b7
CW
1048 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1049 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1050 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1051 goto out;
79e53945
JB
1052 }
1053 }
1054
1055 /* If we still don't have a mode after all that, give up. */
dd06f90e 1056 if (!fixed_mode)
79e53945
JB
1057 goto failed;
1058
79e53945 1059out:
7dec0606 1060 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1061 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1062 lvds_encoder->is_dual_link ? "dual" : "single");
1063
24ded204
DV
1064 /*
1065 * Unlock registers and just
1066 * leave them unlocked
1067 */
c619eed4 1068 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1069 I915_WRITE(PCH_PP_CONTROL,
1070 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1071 } else {
ed10fca9
KP
1072 I915_WRITE(PP_CONTROL,
1073 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1074 }
db1740a0
JN
1075 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1076 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1077 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1078 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1079 }
79e53945 1080 drm_sysfs_connector_add(connector);
aaa6fd2a 1081
dd06f90e 1082 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1083 intel_panel_setup_backlight(connector);
aaa6fd2a 1084
c5d1b51d 1085 return true;
79e53945
JB
1086
1087failed:
8a4c47f3 1088 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1089 drm_connector_cleanup(connector);
1991bdfa 1090 drm_encoder_cleanup(encoder);
dd06f90e
JN
1091 if (fixed_mode)
1092 drm_mode_destroy(dev, fixed_mode);
29b99b48 1093 kfree(lvds_encoder);
c7362c4d 1094 kfree(lvds_connector);
c5d1b51d 1095 return false;
79e53945 1096}