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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
13c7d870 | 52 | bool is_dual_link; |
7dec0606 | 53 | u32 reg; |
788319d4 | 54 | |
62165e0d | 55 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
56 | }; |
57 | ||
29b99b48 | 58 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
29b99b48 | 60 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
61 | } |
62 | ||
c7362c4d | 63 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 64 | { |
c7362c4d | 65 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
66 | } |
67 | ||
b1dc332c DV |
68 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
69 | enum pipe *pipe) | |
70 | { | |
71 | struct drm_device *dev = encoder->base.dev; | |
72 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 | 73 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 74 | enum intel_display_power_domain power_domain; |
7dec0606 | 75 | u32 tmp; |
b1dc332c | 76 | |
34a6c70f PZ |
77 | power_domain = intel_display_port_power_domain(encoder); |
78 | if (!intel_display_power_enabled(dev_priv, power_domain)) | |
79 | return false; | |
80 | ||
7dec0606 | 81 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
82 | |
83 | if (!(tmp & LVDS_PORT_EN)) | |
84 | return false; | |
85 | ||
86 | if (HAS_PCH_CPT(dev)) | |
87 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
88 | else | |
89 | *pipe = PORT_TO_PIPE(tmp); | |
90 | ||
91 | return true; | |
92 | } | |
93 | ||
045ac3b5 JB |
94 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
95 | struct intel_crtc_config *pipe_config) | |
96 | { | |
97 | struct drm_device *dev = encoder->base.dev; | |
98 | struct drm_i915_private *dev_priv = dev->dev_private; | |
99 | u32 lvds_reg, tmp, flags = 0; | |
18442d08 | 100 | int dotclock; |
045ac3b5 JB |
101 | |
102 | if (HAS_PCH_SPLIT(dev)) | |
103 | lvds_reg = PCH_LVDS; | |
104 | else | |
105 | lvds_reg = LVDS; | |
106 | ||
107 | tmp = I915_READ(lvds_reg); | |
108 | if (tmp & LVDS_HSYNC_POLARITY) | |
109 | flags |= DRM_MODE_FLAG_NHSYNC; | |
110 | else | |
111 | flags |= DRM_MODE_FLAG_PHSYNC; | |
112 | if (tmp & LVDS_VSYNC_POLARITY) | |
113 | flags |= DRM_MODE_FLAG_NVSYNC; | |
114 | else | |
115 | flags |= DRM_MODE_FLAG_PVSYNC; | |
116 | ||
117 | pipe_config->adjusted_mode.flags |= flags; | |
06922821 | 118 | |
18442d08 VS |
119 | dotclock = pipe_config->port_clock; |
120 | ||
121 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
122 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
123 | ||
241bfc38 | 124 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
125 | } |
126 | ||
f6736a1a | 127 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
128 | { |
129 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
130 | struct drm_device *dev = encoder->base.dev; | |
131 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 132 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
4c6df4b4 VS |
133 | const struct drm_display_mode *adjusted_mode = |
134 | &crtc->config.adjusted_mode; | |
55607e8a | 135 | int pipe = crtc->pipe; |
fc683091 DV |
136 | u32 temp; |
137 | ||
55607e8a DV |
138 | if (HAS_PCH_SPLIT(dev)) { |
139 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
140 | assert_shared_dpll_disabled(dev_priv, | |
141 | intel_crtc_to_shared_dpll(crtc)); | |
142 | } else { | |
143 | assert_pll_disabled(dev_priv, pipe); | |
144 | } | |
145 | ||
fc683091 DV |
146 | temp = I915_READ(lvds_encoder->reg); |
147 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
148 | |
149 | if (HAS_PCH_CPT(dev)) { | |
150 | temp &= ~PORT_TRANS_SEL_MASK; | |
151 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 152 | } else { |
62810e5a DV |
153 | if (pipe == 1) { |
154 | temp |= LVDS_PIPEB_SELECT; | |
155 | } else { | |
156 | temp &= ~LVDS_PIPEB_SELECT; | |
157 | } | |
fc683091 | 158 | } |
62810e5a | 159 | |
fc683091 | 160 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 161 | temp &= ~LVDS_BORDER_ENABLE; |
55607e8a | 162 | temp |= crtc->config.gmch_pfit.lvds_border_bits; |
fc683091 DV |
163 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
164 | * set the DPLLs for dual-channel mode or not. | |
165 | */ | |
166 | if (lvds_encoder->is_dual_link) | |
167 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
168 | else | |
169 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
170 | ||
171 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
172 | * appropriately here, but we need to look more thoroughly into how | |
173 | * panels behave in the two modes. | |
174 | */ | |
62810e5a DV |
175 | |
176 | /* Set the dithering flag on LVDS as needed, note that there is no | |
177 | * special lvds dither control bit on pch-split platforms, dithering is | |
178 | * only controlled through the PIPECONF reg. */ | |
179 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
180 | /* Bspec wording suggests that LVDS port dithering only exists |
181 | * for 18bpp panels. */ | |
55607e8a | 182 | if (crtc->config.dither && crtc->config.pipe_bpp == 18) |
fc683091 DV |
183 | temp |= LVDS_ENABLE_DITHER; |
184 | else | |
185 | temp &= ~LVDS_ENABLE_DITHER; | |
186 | } | |
187 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 188 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 189 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 190 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
191 | temp |= LVDS_VSYNC_POLARITY; |
192 | ||
193 | I915_WRITE(lvds_encoder->reg, temp); | |
194 | } | |
195 | ||
79e53945 JB |
196 | /** |
197 | * Sets the power state for the panel. | |
198 | */ | |
c22834ec | 199 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 200 | { |
c22834ec | 201 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 202 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
203 | struct intel_connector *intel_connector = |
204 | &lvds_encoder->attached_connector->base; | |
79e53945 | 205 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 206 | u32 ctl_reg, stat_reg; |
541998a1 | 207 | |
c619eed4 | 208 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 209 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 210 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
211 | } else { |
212 | ctl_reg = PP_CONTROL; | |
de842eff | 213 | stat_reg = PP_STATUS; |
541998a1 | 214 | } |
79e53945 | 215 | |
7dec0606 | 216 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 217 | |
2a1292fd | 218 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 219 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
220 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
221 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 222 | |
752aa88a | 223 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
224 | } |
225 | ||
c22834ec | 226 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 227 | { |
c22834ec | 228 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 229 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
230 | struct intel_connector *intel_connector = |
231 | &lvds_encoder->attached_connector->base; | |
2a1292fd | 232 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 233 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
234 | |
235 | if (HAS_PCH_SPLIT(dev)) { | |
236 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 237 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
238 | } else { |
239 | ctl_reg = PP_CONTROL; | |
de842eff | 240 | stat_reg = PP_STATUS; |
2a1292fd CW |
241 | } |
242 | ||
752aa88a | 243 | intel_panel_disable_backlight(intel_connector); |
2a1292fd CW |
244 | |
245 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
246 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
247 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 248 | |
7dec0606 DV |
249 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
250 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
251 | } |
252 | ||
c19de8eb DL |
253 | static enum drm_mode_status |
254 | intel_lvds_mode_valid(struct drm_connector *connector, | |
255 | struct drm_display_mode *mode) | |
79e53945 | 256 | { |
dd06f90e JN |
257 | struct intel_connector *intel_connector = to_intel_connector(connector); |
258 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 259 | |
788319d4 CW |
260 | if (mode->hdisplay > fixed_mode->hdisplay) |
261 | return MODE_PANEL; | |
262 | if (mode->vdisplay > fixed_mode->vdisplay) | |
263 | return MODE_PANEL; | |
79e53945 JB |
264 | |
265 | return MODE_OK; | |
266 | } | |
267 | ||
7ae89233 DV |
268 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
269 | struct intel_crtc_config *pipe_config) | |
79e53945 | 270 | { |
7ae89233 | 271 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 272 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
273 | struct intel_lvds_encoder *lvds_encoder = |
274 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
275 | struct intel_connector *intel_connector = |
276 | &lvds_encoder->attached_connector->base; | |
7ae89233 | 277 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
29b99b48 | 278 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
4e53c2e0 | 279 | unsigned int lvds_bpp; |
79e53945 JB |
280 | |
281 | /* Should never happen!! */ | |
a6c45cf0 | 282 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 283 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
284 | return false; |
285 | } | |
286 | ||
4e53c2e0 DV |
287 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
288 | LVDS_A3_POWER_UP) | |
289 | lvds_bpp = 8*3; | |
290 | else | |
291 | lvds_bpp = 6*3; | |
292 | ||
e29c22c0 | 293 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
294 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
295 | pipe_config->pipe_bpp, lvds_bpp); | |
296 | pipe_config->pipe_bpp = lvds_bpp; | |
297 | } | |
d8b32247 | 298 | |
79e53945 | 299 | /* |
71677043 | 300 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
301 | * to the adjusted mode. The CRTC will be set up for this mode, |
302 | * with the panel scaling set up to source from the H/VDisplay | |
303 | * of the original mode. | |
304 | */ | |
4d891523 | 305 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 306 | adjusted_mode); |
1d8e1c75 CW |
307 | |
308 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
309 | pipe_config->has_pch_encoder = true; |
310 | ||
b074cec8 JB |
311 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
312 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
313 | } else { |
314 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
315 | intel_connector->panel.fitting_mode); | |
79e53945 | 316 | |
21d8a475 | 317 | } |
f9bef081 | 318 | |
79e53945 JB |
319 | /* |
320 | * XXX: It would be nice to support lower refresh rates on the | |
321 | * panels to reduce power consumption, and perhaps match the | |
322 | * user's requested refresh rate. | |
323 | */ | |
324 | ||
325 | return true; | |
326 | } | |
327 | ||
79e53945 JB |
328 | /** |
329 | * Detect the LVDS connection. | |
330 | * | |
b42d4c5c JB |
331 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
332 | * connected and closed means disconnected. We also send hotplug events as | |
333 | * needed, using lid status notification from the input layer. | |
79e53945 | 334 | */ |
7b334fcb | 335 | static enum drm_connector_status |
930a9e28 | 336 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 337 | { |
7b9c5abe | 338 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 339 | enum drm_connector_status status; |
b42d4c5c | 340 | |
164c8598 | 341 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 342 | connector->base.id, connector->name); |
164c8598 | 343 | |
fe16d949 CW |
344 | status = intel_panel_detect(dev); |
345 | if (status != connector_status_unknown) | |
346 | return status; | |
01fe9dbd | 347 | |
6ee3b5a1 | 348 | return connector_status_connected; |
79e53945 JB |
349 | } |
350 | ||
351 | /** | |
352 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
353 | */ | |
354 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
355 | { | |
62165e0d | 356 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 357 | struct drm_device *dev = connector->dev; |
788319d4 | 358 | struct drm_display_mode *mode; |
79e53945 | 359 | |
9cd300e0 | 360 | /* use cached edid if we have one */ |
2aa4f099 | 361 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 362 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 363 | |
dd06f90e | 364 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 365 | if (mode == NULL) |
788319d4 | 366 | return 0; |
79e53945 | 367 | |
788319d4 CW |
368 | drm_mode_probed_add(connector, mode); |
369 | return 1; | |
79e53945 JB |
370 | } |
371 | ||
0544edfd TB |
372 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
373 | { | |
bc0daf48 | 374 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
375 | return 1; |
376 | } | |
377 | ||
378 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
379 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
380 | { | |
381 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
382 | .ident = "Toshiba Tecra A11", | |
383 | .matches = { | |
384 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
385 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
386 | }, | |
387 | }, | |
388 | ||
389 | { } /* terminating entry */ | |
390 | }; | |
391 | ||
c9354c85 | 392 | /* |
b8efb17b ZR |
393 | * Lid events. Note the use of 'modeset': |
394 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
395 | * and set it to MODESET_DONE on open | |
c9354c85 | 396 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
397 | * duplicate events where it was already properly set) |
398 | * - the suspend/resume paths will set it to | |
399 | * MODESET_SUSPENDED and ignore the lid open event, | |
400 | * because they restore the mode ("lid open"). | |
c9354c85 | 401 | */ |
c1c7af60 JB |
402 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
403 | void *unused) | |
404 | { | |
db1740a0 JN |
405 | struct intel_lvds_connector *lvds_connector = |
406 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
407 | struct drm_connector *connector = &lvds_connector->base.base; | |
408 | struct drm_device *dev = connector->dev; | |
409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 410 | |
2fb4e61d AW |
411 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
412 | return NOTIFY_OK; | |
413 | ||
b8efb17b ZR |
414 | mutex_lock(&dev_priv->modeset_restore_lock); |
415 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
416 | goto exit; | |
a2565377 ZY |
417 | /* |
418 | * check and update the status of LVDS connector after receiving | |
419 | * the LID nofication event. | |
420 | */ | |
db1740a0 | 421 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 422 | |
0544edfd TB |
423 | /* Don't force modeset on machines where it causes a GPU lockup */ |
424 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 425 | goto exit; |
c9354c85 | 426 | if (!acpi_lid_open()) { |
b8efb17b ZR |
427 | /* do modeset on next lid open event */ |
428 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
429 | goto exit; | |
06891e27 | 430 | } |
c1c7af60 | 431 | |
b8efb17b ZR |
432 | if (dev_priv->modeset_restore == MODESET_DONE) |
433 | goto exit; | |
c9354c85 | 434 | |
5be19d91 DV |
435 | /* |
436 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
437 | * We try to detect this here and undo any damage. The split for PCH | |
438 | * platforms is rather conservative and a bit arbitrary expect that on | |
439 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
440 | * and as part of the cleanup in the hw state restore we also redisable | |
441 | * the vga plane. | |
442 | */ | |
443 | if (!HAS_PCH_SPLIT(dev)) { | |
444 | drm_modeset_lock_all(dev); | |
445 | intel_modeset_setup_hw_state(dev, true); | |
446 | drm_modeset_unlock_all(dev); | |
447 | } | |
06324194 | 448 | |
b8efb17b ZR |
449 | dev_priv->modeset_restore = MODESET_DONE; |
450 | ||
451 | exit: | |
452 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
453 | return NOTIFY_OK; |
454 | } | |
455 | ||
79e53945 JB |
456 | /** |
457 | * intel_lvds_destroy - unregister and free LVDS structures | |
458 | * @connector: connector to free | |
459 | * | |
460 | * Unregister the DDC bus for this connector then free the driver private | |
461 | * structure. | |
462 | */ | |
463 | static void intel_lvds_destroy(struct drm_connector *connector) | |
464 | { | |
db1740a0 JN |
465 | struct intel_lvds_connector *lvds_connector = |
466 | to_lvds_connector(connector); | |
79e53945 | 467 | |
db1740a0 JN |
468 | if (lvds_connector->lid_notifier.notifier_call) |
469 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 470 | |
9cd300e0 JN |
471 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
472 | kfree(lvds_connector->base.edid); | |
473 | ||
1d508706 | 474 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 475 | |
79e53945 JB |
476 | drm_connector_cleanup(connector); |
477 | kfree(connector); | |
478 | } | |
479 | ||
335041ed JB |
480 | static int intel_lvds_set_property(struct drm_connector *connector, |
481 | struct drm_property *property, | |
482 | uint64_t value) | |
483 | { | |
4d891523 | 484 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 485 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 486 | |
788319d4 | 487 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 488 | struct drm_crtc *crtc; |
bb8a3560 | 489 | |
53bd8389 JB |
490 | if (value == DRM_MODE_SCALE_NONE) { |
491 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 492 | return -EINVAL; |
3fbe18d6 | 493 | } |
788319d4 | 494 | |
4d891523 | 495 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
496 | /* the LVDS scaling property is not changed */ |
497 | return 0; | |
498 | } | |
4d891523 | 499 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
500 | |
501 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
502 | if (crtc && crtc->enabled) { |
503 | /* | |
504 | * If the CRTC is enabled, the display will be changed | |
505 | * according to the new panel fitting mode. | |
506 | */ | |
c0c36b94 | 507 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
508 | } |
509 | } | |
510 | ||
335041ed JB |
511 | return 0; |
512 | } | |
513 | ||
79e53945 JB |
514 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
515 | .get_modes = intel_lvds_get_modes, | |
516 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 517 | .best_encoder = intel_best_encoder, |
79e53945 JB |
518 | }; |
519 | ||
520 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 521 | .dpms = intel_connector_dpms, |
79e53945 JB |
522 | .detect = intel_lvds_detect, |
523 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 524 | .set_property = intel_lvds_set_property, |
79e53945 JB |
525 | .destroy = intel_lvds_destroy, |
526 | }; | |
527 | ||
79e53945 | 528 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 529 | .destroy = intel_encoder_destroy, |
79e53945 JB |
530 | }; |
531 | ||
425d244c JW |
532 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
533 | { | |
bc0daf48 | 534 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
535 | return 1; |
536 | } | |
79e53945 | 537 | |
425d244c | 538 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 539 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
540 | { |
541 | .callback = intel_no_lvds_dmi_callback, | |
542 | .ident = "Apple Mac Mini (Core series)", | |
543 | .matches = { | |
98acd46f | 544 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
545 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
546 | }, | |
547 | }, | |
548 | { | |
549 | .callback = intel_no_lvds_dmi_callback, | |
550 | .ident = "Apple Mac Mini (Core 2 series)", | |
551 | .matches = { | |
98acd46f | 552 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
553 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
554 | }, | |
555 | }, | |
556 | { | |
557 | .callback = intel_no_lvds_dmi_callback, | |
558 | .ident = "MSI IM-945GSE-A", | |
559 | .matches = { | |
560 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
561 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
562 | }, | |
563 | }, | |
564 | { | |
565 | .callback = intel_no_lvds_dmi_callback, | |
566 | .ident = "Dell Studio Hybrid", | |
567 | .matches = { | |
568 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
569 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
570 | }, | |
571 | }, | |
70aa96ca JW |
572 | { |
573 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
574 | .ident = "Dell OptiPlex FX170", |
575 | .matches = { | |
576 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
577 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
578 | }, | |
579 | }, | |
580 | { | |
581 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
582 | .ident = "AOpen Mini PC", |
583 | .matches = { | |
584 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
585 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
586 | }, | |
587 | }, | |
ed8c754b TV |
588 | { |
589 | .callback = intel_no_lvds_dmi_callback, | |
590 | .ident = "AOpen Mini PC MP915", | |
591 | .matches = { | |
592 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
593 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
594 | }, | |
595 | }, | |
22ab70d3 KP |
596 | { |
597 | .callback = intel_no_lvds_dmi_callback, | |
598 | .ident = "AOpen i915GMm-HFS", | |
599 | .matches = { | |
600 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
601 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
602 | }, | |
603 | }, | |
e57b6886 DV |
604 | { |
605 | .callback = intel_no_lvds_dmi_callback, | |
606 | .ident = "AOpen i45GMx-I", | |
607 | .matches = { | |
608 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
609 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
610 | }, | |
611 | }, | |
fa0864b2 MC |
612 | { |
613 | .callback = intel_no_lvds_dmi_callback, | |
614 | .ident = "Aopen i945GTt-VFA", | |
615 | .matches = { | |
616 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
617 | }, | |
618 | }, | |
9875557e SB |
619 | { |
620 | .callback = intel_no_lvds_dmi_callback, | |
621 | .ident = "Clientron U800", | |
622 | .matches = { | |
623 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
624 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
625 | }, | |
626 | }, | |
6a574b5b | 627 | { |
44306ab3 JS |
628 | .callback = intel_no_lvds_dmi_callback, |
629 | .ident = "Clientron E830", | |
630 | .matches = { | |
631 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
632 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
633 | }, | |
634 | }, | |
635 | { | |
6a574b5b HG |
636 | .callback = intel_no_lvds_dmi_callback, |
637 | .ident = "Asus EeeBox PC EB1007", | |
638 | .matches = { | |
639 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
640 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
641 | }, | |
642 | }, | |
0999bbe0 AJ |
643 | { |
644 | .callback = intel_no_lvds_dmi_callback, | |
645 | .ident = "Asus AT5NM10T-I", | |
646 | .matches = { | |
647 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
648 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
649 | }, | |
650 | }, | |
33471119 JBG |
651 | { |
652 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 653 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
654 | .matches = { |
655 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 656 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
657 | }, |
658 | }, | |
f5b8a7ed MG |
659 | { |
660 | .callback = intel_no_lvds_dmi_callback, | |
661 | .ident = "Hewlett-Packard t5745", | |
662 | .matches = { | |
663 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 664 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
665 | }, |
666 | }, | |
667 | { | |
668 | .callback = intel_no_lvds_dmi_callback, | |
669 | .ident = "Hewlett-Packard st5747", | |
670 | .matches = { | |
671 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 672 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
673 | }, |
674 | }, | |
97effadb AA |
675 | { |
676 | .callback = intel_no_lvds_dmi_callback, | |
677 | .ident = "MSI Wind Box DC500", | |
678 | .matches = { | |
679 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
680 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
681 | }, | |
682 | }, | |
a51d4ed0 CW |
683 | { |
684 | .callback = intel_no_lvds_dmi_callback, | |
685 | .ident = "Gigabyte GA-D525TUD", | |
686 | .matches = { | |
687 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
688 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
689 | }, | |
690 | }, | |
c31407a3 CW |
691 | { |
692 | .callback = intel_no_lvds_dmi_callback, | |
693 | .ident = "Supermicro X7SPA-H", | |
694 | .matches = { | |
695 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
696 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
697 | }, | |
698 | }, | |
9e9dd0e8 CL |
699 | { |
700 | .callback = intel_no_lvds_dmi_callback, | |
701 | .ident = "Fujitsu Esprimo Q900", | |
702 | .matches = { | |
703 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
704 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
705 | }, | |
706 | }, | |
645378d8 RP |
707 | { |
708 | .callback = intel_no_lvds_dmi_callback, | |
709 | .ident = "Intel D410PT", | |
710 | .matches = { | |
711 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
712 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
713 | }, | |
714 | }, | |
715 | { | |
716 | .callback = intel_no_lvds_dmi_callback, | |
717 | .ident = "Intel D425KT", | |
718 | .matches = { | |
719 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
720 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
721 | }, | |
722 | }, | |
e5614f0c CW |
723 | { |
724 | .callback = intel_no_lvds_dmi_callback, | |
725 | .ident = "Intel D510MO", | |
726 | .matches = { | |
727 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
728 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
729 | }, | |
730 | }, | |
dcf6d294 JN |
731 | { |
732 | .callback = intel_no_lvds_dmi_callback, | |
733 | .ident = "Intel D525MW", | |
734 | .matches = { | |
735 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
736 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
737 | }, | |
738 | }, | |
425d244c JW |
739 | |
740 | { } /* terminating entry */ | |
741 | }; | |
79e53945 | 742 | |
7cf4f69d ZY |
743 | /* |
744 | * Enumerate the child dev array parsed from VBT to check whether | |
745 | * the LVDS is present. | |
746 | * If it is present, return 1. | |
747 | * If it is not present, return false. | |
748 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 749 | */ |
270eea0f CW |
750 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
751 | u8 *i2c_pin) | |
7cf4f69d ZY |
752 | { |
753 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 754 | int i; |
7cf4f69d | 755 | |
41aa3448 | 756 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 757 | return true; |
7cf4f69d | 758 | |
41aa3448 | 759 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
760 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
761 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
762 | |
763 | /* If the device type is not LFP, continue. | |
764 | * We have to check both the new identifiers as well as the | |
765 | * old for compatibility with some BIOSes. | |
7cf4f69d | 766 | */ |
425904dd CW |
767 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
768 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
769 | continue; |
770 | ||
3bd7d909 DK |
771 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
772 | *i2c_pin = child->i2c_pin; | |
270eea0f | 773 | |
425904dd CW |
774 | /* However, we cannot trust the BIOS writers to populate |
775 | * the VBT correctly. Since LVDS requires additional | |
776 | * information from AIM blocks, a non-zero addin offset is | |
777 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 778 | */ |
425904dd CW |
779 | if (child->addin_offset) |
780 | return true; | |
781 | ||
782 | /* But even then some BIOS writers perform some black magic | |
783 | * and instantiate the device without reference to any | |
784 | * additional data. Trust that if the VBT was written into | |
785 | * the OpRegion then they have validated the LVDS's existence. | |
786 | */ | |
787 | if (dev_priv->opregion.vbt) | |
788 | return true; | |
7cf4f69d | 789 | } |
425904dd CW |
790 | |
791 | return false; | |
7cf4f69d ZY |
792 | } |
793 | ||
1974cad0 DV |
794 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
795 | { | |
796 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
797 | return 1; | |
798 | } | |
799 | ||
800 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
801 | { | |
802 | .callback = intel_dual_link_lvds_callback, | |
803 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
804 | .matches = { | |
805 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
806 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
807 | }, | |
808 | }, | |
809 | { } /* terminating entry */ | |
810 | }; | |
811 | ||
812 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
813 | { |
814 | struct intel_encoder *encoder; | |
815 | struct intel_lvds_encoder *lvds_encoder; | |
816 | ||
817 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
818 | base.head) { | |
819 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
820 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
821 | ||
822 | return lvds_encoder->is_dual_link; | |
823 | } | |
824 | } | |
825 | ||
826 | return false; | |
827 | } | |
828 | ||
7dec0606 | 829 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 830 | { |
7dec0606 | 831 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
832 | unsigned int val; |
833 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
834 | |
835 | /* use the module option value if specified */ | |
d330a953 JN |
836 | if (i915.lvds_channel_mode > 0) |
837 | return i915.lvds_channel_mode == 2; | |
1974cad0 DV |
838 | |
839 | if (dmi_check_system(intel_dual_link_lvds)) | |
840 | return true; | |
841 | ||
13c7d870 DV |
842 | /* BIOS should set the proper LVDS register value at boot, but |
843 | * in reality, it doesn't set the value when the lid is closed; | |
844 | * we need to check "the value to be set" in VBT when LVDS | |
845 | * register is uninitialized. | |
846 | */ | |
7dec0606 | 847 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 848 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 849 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 850 | |
1974cad0 DV |
851 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
852 | } | |
853 | ||
f3cfcba6 CW |
854 | static bool intel_lvds_supported(struct drm_device *dev) |
855 | { | |
856 | /* With the introduction of the PCH we gained a dedicated | |
857 | * LVDS presence pin, use it. */ | |
311e359c | 858 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
859 | return true; |
860 | ||
861 | /* Otherwise LVDS was only attached to mobile products, | |
862 | * except for the inglorious 830gm */ | |
311e359c PZ |
863 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
864 | return true; | |
865 | ||
866 | return false; | |
f3cfcba6 CW |
867 | } |
868 | ||
79e53945 JB |
869 | /** |
870 | * intel_lvds_init - setup LVDS connectors on this device | |
871 | * @dev: drm device | |
872 | * | |
873 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
874 | * modes we can display on the LVDS panel (if present). | |
875 | */ | |
c9093354 | 876 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
877 | { |
878 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 879 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 880 | struct intel_encoder *intel_encoder; |
c7362c4d | 881 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 882 | struct intel_connector *intel_connector; |
79e53945 JB |
883 | struct drm_connector *connector; |
884 | struct drm_encoder *encoder; | |
885 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 886 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 887 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 888 | struct edid *edid; |
79e53945 JB |
889 | struct drm_crtc *crtc; |
890 | u32 lvds; | |
270eea0f CW |
891 | int pipe; |
892 | u8 pin; | |
79e53945 | 893 | |
f3cfcba6 | 894 | if (!intel_lvds_supported(dev)) |
c9093354 | 895 | return; |
f3cfcba6 | 896 | |
425d244c JW |
897 | /* Skip init on machines we know falsely report LVDS */ |
898 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 899 | return; |
565dcd46 | 900 | |
270eea0f CW |
901 | pin = GMBUS_PORT_PANEL; |
902 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 903 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 904 | return; |
38b3037e | 905 | } |
e99da35f | 906 | |
c619eed4 | 907 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 908 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 909 | return; |
41aa3448 | 910 | if (dev_priv->vbt.edp_support) { |
28c97730 | 911 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 912 | return; |
32f9d658 | 913 | } |
541998a1 ZW |
914 | } |
915 | ||
b14c5679 | 916 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 917 | if (!lvds_encoder) |
c9093354 | 918 | return; |
79e53945 | 919 | |
b14c5679 | 920 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 921 | if (!lvds_connector) { |
29b99b48 | 922 | kfree(lvds_encoder); |
c9093354 | 923 | return; |
bb8a3560 ZW |
924 | } |
925 | ||
62165e0d JN |
926 | lvds_encoder->attached_connector = lvds_connector; |
927 | ||
29b99b48 | 928 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 929 | encoder = &intel_encoder->base; |
c7362c4d | 930 | intel_connector = &lvds_connector->base; |
ea5b213a | 931 | connector = &intel_connector->base; |
bb8a3560 | 932 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
933 | DRM_MODE_CONNECTOR_LVDS); |
934 | ||
4ef69c7a | 935 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
936 | DRM_MODE_ENCODER_LVDS); |
937 | ||
c22834ec | 938 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 939 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 940 | intel_encoder->compute_config = intel_lvds_compute_config; |
c22834ec | 941 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 942 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 943 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 944 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
4932e2c3 | 945 | intel_connector->unregister = intel_connector_unregister; |
c22834ec | 946 | |
df0e9248 | 947 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 948 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 949 | |
bc079e8b | 950 | intel_encoder->cloneable = 0; |
27f8227b JB |
951 | if (HAS_PCH_SPLIT(dev)) |
952 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
953 | else if (IS_GEN4(dev)) |
954 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
955 | else |
956 | intel_encoder->crtc_mask = (1 << 1); | |
957 | ||
79e53945 JB |
958 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
959 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
960 | connector->interlace_allowed = false; | |
961 | connector->doublescan_allowed = false; | |
962 | ||
7dec0606 DV |
963 | if (HAS_PCH_SPLIT(dev)) { |
964 | lvds_encoder->reg = PCH_LVDS; | |
965 | } else { | |
966 | lvds_encoder->reg = LVDS; | |
967 | } | |
968 | ||
3fbe18d6 ZY |
969 | /* create the scaling mode property */ |
970 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 971 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 972 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 973 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 974 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
975 | /* |
976 | * LVDS discovery: | |
977 | * 1) check for EDID on DDC | |
978 | * 2) check for VBT data | |
979 | * 3) check to see if LVDS is already on | |
980 | * if none of the above, no panel | |
981 | * 4) make sure lid is open | |
982 | * if closed, act like it's not there for now | |
983 | */ | |
984 | ||
79e53945 JB |
985 | /* |
986 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
987 | * preferred mode is the right one. | |
988 | */ | |
4da98541 | 989 | mutex_lock(&dev->mode_config.mutex); |
9cd300e0 JN |
990 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
991 | if (edid) { | |
992 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 993 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 994 | edid); |
3f8ff0e7 | 995 | } else { |
9cd300e0 JN |
996 | kfree(edid); |
997 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 998 | } |
9cd300e0 JN |
999 | } else { |
1000 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1001 | } |
9cd300e0 JN |
1002 | lvds_connector->base.edid = edid; |
1003 | ||
1004 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1005 | /* Didn't get an EDID, so |
1006 | * Set wide sync ranges so we get all modes | |
1007 | * handed to valid_mode for checking | |
1008 | */ | |
1009 | connector->display_info.min_vfreq = 0; | |
1010 | connector->display_info.max_vfreq = 200; | |
1011 | connector->display_info.min_hfreq = 0; | |
1012 | connector->display_info.max_hfreq = 200; | |
1013 | } | |
79e53945 JB |
1014 | |
1015 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1016 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1017 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1018 | drm_mode_debug_printmodeline(scan); | |
1019 | ||
dd06f90e | 1020 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 | 1021 | if (fixed_mode) { |
4b6ed685 | 1022 | downclock_mode = |
ec9ed197 VK |
1023 | intel_find_panel_downclock(dev, |
1024 | fixed_mode, connector); | |
4b6ed685 VK |
1025 | if (downclock_mode != NULL && |
1026 | i915.lvds_downclock) { | |
ec9ed197 VK |
1027 | /* We found the downclock for LVDS. */ |
1028 | dev_priv->lvds_downclock_avail = true; | |
1029 | dev_priv->lvds_downclock = | |
ec9ed197 VK |
1030 | downclock_mode->clock; |
1031 | DRM_DEBUG_KMS("LVDS downclock is found" | |
1032 | " in EDID. Normal clock %dKhz, " | |
1033 | "downclock %dKhz\n", | |
1034 | fixed_mode->clock, | |
1035 | dev_priv->lvds_downclock); | |
1036 | } | |
6a9d51b7 CW |
1037 | goto out; |
1038 | } | |
79e53945 | 1039 | } |
79e53945 JB |
1040 | } |
1041 | ||
1042 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1043 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1044 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1045 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1046 | |
41aa3448 | 1047 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1048 | if (fixed_mode) { |
1049 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1050 | goto out; |
1051 | } | |
79e53945 JB |
1052 | } |
1053 | ||
1054 | /* | |
1055 | * If we didn't get EDID, try checking if the panel is already turned | |
1056 | * on. If so, assume that whatever is currently programmed is the | |
1057 | * correct mode. | |
1058 | */ | |
541998a1 | 1059 | |
f2b115e6 | 1060 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1061 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1062 | goto failed; |
1063 | ||
79e53945 JB |
1064 | lvds = I915_READ(LVDS); |
1065 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1066 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1067 | |
1068 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1069 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1070 | if (fixed_mode) { | |
6a9d51b7 CW |
1071 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1072 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1073 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1074 | goto out; |
79e53945 JB |
1075 | } |
1076 | } | |
1077 | ||
1078 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1079 | if (!fixed_mode) |
79e53945 JB |
1080 | goto failed; |
1081 | ||
79e53945 | 1082 | out: |
4da98541 DV |
1083 | mutex_unlock(&dev->mode_config.mutex); |
1084 | ||
7dec0606 | 1085 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1086 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1087 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1088 | ||
24ded204 DV |
1089 | /* |
1090 | * Unlock registers and just | |
1091 | * leave them unlocked | |
1092 | */ | |
c619eed4 | 1093 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1094 | I915_WRITE(PCH_PP_CONTROL, |
1095 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1096 | } else { | |
ed10fca9 KP |
1097 | I915_WRITE(PP_CONTROL, |
1098 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1099 | } |
db1740a0 JN |
1100 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1101 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1102 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1103 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1104 | } |
79e53945 | 1105 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1106 | |
4b6ed685 | 1107 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
0657b6b1 | 1108 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1109 | |
c9093354 | 1110 | return; |
79e53945 JB |
1111 | |
1112 | failed: | |
4da98541 DV |
1113 | mutex_unlock(&dev->mode_config.mutex); |
1114 | ||
8a4c47f3 | 1115 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1116 | drm_connector_cleanup(connector); |
1991bdfa | 1117 | drm_encoder_cleanup(encoder); |
29b99b48 | 1118 | kfree(lvds_encoder); |
c7362c4d | 1119 | kfree(lvds_connector); |
c9093354 | 1120 | return; |
79e53945 | 1121 | } |