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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
3fbe18d6 ZY |
52 | u32 pfit_control; |
53 | u32 pfit_pgm_ratios; | |
13c7d870 | 54 | bool is_dual_link; |
7dec0606 | 55 | u32 reg; |
788319d4 | 56 | |
62165e0d | 57 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
58 | }; |
59 | ||
29b99b48 | 60 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 61 | { |
29b99b48 | 62 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
63 | } |
64 | ||
c7362c4d | 65 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 66 | { |
c7362c4d | 67 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
68 | } |
69 | ||
b1dc332c DV |
70 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
71 | enum pipe *pipe) | |
72 | { | |
73 | struct drm_device *dev = encoder->base.dev; | |
74 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
75 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
76 | u32 tmp; | |
b1dc332c | 77 | |
7dec0606 | 78 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
79 | |
80 | if (!(tmp & LVDS_PORT_EN)) | |
81 | return false; | |
82 | ||
83 | if (HAS_PCH_CPT(dev)) | |
84 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
85 | else | |
86 | *pipe = PORT_TO_PIPE(tmp); | |
87 | ||
88 | return true; | |
89 | } | |
90 | ||
fc683091 DV |
91 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
92 | * This is an exception to the general rule that mode_set doesn't turn | |
93 | * things on. | |
94 | */ | |
95 | static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder) | |
96 | { | |
97 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
98 | struct drm_device *dev = encoder->base.dev; | |
99 | struct drm_i915_private *dev_priv = dev->dev_private; | |
100 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); | |
101 | struct drm_display_mode *fixed_mode = | |
102 | lvds_encoder->attached_connector->base.panel.fixed_mode; | |
103 | int pipe = intel_crtc->pipe; | |
104 | u32 temp; | |
105 | ||
fc683091 DV |
106 | temp = I915_READ(lvds_encoder->reg); |
107 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
108 | |
109 | if (HAS_PCH_CPT(dev)) { | |
110 | temp &= ~PORT_TRANS_SEL_MASK; | |
111 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 112 | } else { |
62810e5a DV |
113 | if (pipe == 1) { |
114 | temp |= LVDS_PIPEB_SELECT; | |
115 | } else { | |
116 | temp &= ~LVDS_PIPEB_SELECT; | |
117 | } | |
fc683091 | 118 | } |
62810e5a | 119 | |
fc683091 DV |
120 | /* set the corresponsding LVDS_BORDER bit */ |
121 | temp |= dev_priv->lvds_border_bits; | |
122 | /* Set the B0-B3 data pairs corresponding to whether we're going to | |
123 | * set the DPLLs for dual-channel mode or not. | |
124 | */ | |
125 | if (lvds_encoder->is_dual_link) | |
126 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
127 | else | |
128 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
129 | ||
130 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
131 | * appropriately here, but we need to look more thoroughly into how | |
132 | * panels behave in the two modes. | |
133 | */ | |
62810e5a DV |
134 | |
135 | /* Set the dithering flag on LVDS as needed, note that there is no | |
136 | * special lvds dither control bit on pch-split platforms, dithering is | |
137 | * only controlled through the PIPECONF reg. */ | |
138 | if (INTEL_INFO(dev)->gen == 4) { | |
fc683091 DV |
139 | if (dev_priv->lvds_dither) |
140 | temp |= LVDS_ENABLE_DITHER; | |
141 | else | |
142 | temp &= ~LVDS_ENABLE_DITHER; | |
143 | } | |
144 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
145 | if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC) | |
146 | temp |= LVDS_HSYNC_POLARITY; | |
147 | if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC) | |
148 | temp |= LVDS_VSYNC_POLARITY; | |
149 | ||
150 | I915_WRITE(lvds_encoder->reg, temp); | |
151 | } | |
152 | ||
9d6d9f19 MK |
153 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
154 | { | |
155 | struct drm_device *dev = encoder->base.dev; | |
156 | struct intel_lvds_encoder *enc = to_lvds_encoder(&encoder->base); | |
157 | struct drm_i915_private *dev_priv = dev->dev_private; | |
158 | ||
159 | if (HAS_PCH_SPLIT(dev) || !enc->pfit_control) | |
160 | return; | |
161 | ||
162 | /* | |
163 | * Enable automatic panel scaling so that non-native modes | |
164 | * fill the screen. The panel fitter should only be | |
165 | * adjusted whilst the pipe is disabled, according to | |
166 | * register description and PRM. | |
167 | */ | |
168 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", | |
169 | enc->pfit_control, | |
170 | enc->pfit_pgm_ratios); | |
171 | ||
172 | I915_WRITE(PFIT_PGM_RATIOS, enc->pfit_pgm_ratios); | |
173 | I915_WRITE(PFIT_CONTROL, enc->pfit_control); | |
174 | } | |
175 | ||
79e53945 JB |
176 | /** |
177 | * Sets the power state for the panel. | |
178 | */ | |
c22834ec | 179 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 180 | { |
c22834ec | 181 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 182 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
c22834ec | 183 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc); |
79e53945 | 184 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 185 | u32 ctl_reg, stat_reg; |
541998a1 | 186 | |
c619eed4 | 187 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 188 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 189 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
190 | } else { |
191 | ctl_reg = PP_CONTROL; | |
de842eff | 192 | stat_reg = PP_STATUS; |
541998a1 | 193 | } |
79e53945 | 194 | |
7dec0606 | 195 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 196 | |
2a1292fd | 197 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 198 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
199 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
200 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 201 | |
24ded204 | 202 | intel_panel_enable_backlight(dev, intel_crtc->pipe); |
2a1292fd CW |
203 | } |
204 | ||
c22834ec | 205 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 206 | { |
c22834ec | 207 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 208 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
2a1292fd | 209 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 210 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
211 | |
212 | if (HAS_PCH_SPLIT(dev)) { | |
213 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 214 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
215 | } else { |
216 | ctl_reg = PP_CONTROL; | |
de842eff | 217 | stat_reg = PP_STATUS; |
2a1292fd CW |
218 | } |
219 | ||
47356eb6 | 220 | intel_panel_disable_backlight(dev); |
2a1292fd CW |
221 | |
222 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
223 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
224 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 225 | |
7dec0606 DV |
226 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
227 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
228 | } |
229 | ||
79e53945 JB |
230 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
231 | struct drm_display_mode *mode) | |
232 | { | |
dd06f90e JN |
233 | struct intel_connector *intel_connector = to_intel_connector(connector); |
234 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 235 | |
788319d4 CW |
236 | if (mode->hdisplay > fixed_mode->hdisplay) |
237 | return MODE_PANEL; | |
238 | if (mode->vdisplay > fixed_mode->vdisplay) | |
239 | return MODE_PANEL; | |
79e53945 JB |
240 | |
241 | return MODE_OK; | |
242 | } | |
243 | ||
49be663f CW |
244 | static void |
245 | centre_horizontally(struct drm_display_mode *mode, | |
246 | int width) | |
247 | { | |
248 | u32 border, sync_pos, blank_width, sync_width; | |
249 | ||
250 | /* keep the hsync and hblank widths constant */ | |
251 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
252 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
253 | sync_pos = (blank_width - sync_width + 1) / 2; | |
254 | ||
255 | border = (mode->hdisplay - width + 1) / 2; | |
256 | border += border & 1; /* make the border even */ | |
257 | ||
258 | mode->crtc_hdisplay = width; | |
259 | mode->crtc_hblank_start = width + border; | |
260 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
261 | ||
262 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
263 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
f9bef081 DV |
264 | |
265 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
266 | } |
267 | ||
268 | static void | |
269 | centre_vertically(struct drm_display_mode *mode, | |
270 | int height) | |
271 | { | |
272 | u32 border, sync_pos, blank_width, sync_width; | |
273 | ||
274 | /* keep the vsync and vblank widths constant */ | |
275 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
276 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
277 | sync_pos = (blank_width - sync_width + 1) / 2; | |
278 | ||
279 | border = (mode->vdisplay - height + 1) / 2; | |
280 | ||
281 | mode->crtc_vdisplay = height; | |
282 | mode->crtc_vblank_start = height + border; | |
283 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
284 | ||
285 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
286 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
f9bef081 DV |
287 | |
288 | mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET; | |
49be663f CW |
289 | } |
290 | ||
291 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
292 | { | |
293 | /* | |
294 | * Floating point operation is not supported. So the FACTOR | |
295 | * is defined, which can avoid the floating point computation | |
296 | * when calculating the panel ratio. | |
297 | */ | |
298 | #define ACCURACY 12 | |
299 | #define FACTOR (1 << ACCURACY) | |
300 | u32 ratio = source * FACTOR / target; | |
301 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
302 | } | |
303 | ||
79e53945 | 304 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
e811f5ae | 305 | const struct drm_display_mode *mode, |
79e53945 JB |
306 | struct drm_display_mode *adjusted_mode) |
307 | { | |
308 | struct drm_device *dev = encoder->dev; | |
309 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 310 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder); |
4d891523 JN |
311 | struct intel_connector *intel_connector = |
312 | &lvds_encoder->attached_connector->base; | |
29b99b48 | 313 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
49be663f | 314 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
9db4a9c7 | 315 | int pipe; |
79e53945 JB |
316 | |
317 | /* Should never happen!! */ | |
a6c45cf0 | 318 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 319 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
320 | return false; |
321 | } | |
322 | ||
29b99b48 | 323 | if (intel_encoder_check_is_cloned(&lvds_encoder->base)) |
e24c5c29 | 324 | return false; |
1d8e1c75 | 325 | |
79e53945 | 326 | /* |
71677043 | 327 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
328 | * to the adjusted mode. The CRTC will be set up for this mode, |
329 | * with the panel scaling set up to source from the H/VDisplay | |
330 | * of the original mode. | |
331 | */ | |
4d891523 | 332 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 333 | adjusted_mode); |
1d8e1c75 CW |
334 | |
335 | if (HAS_PCH_SPLIT(dev)) { | |
4d891523 JN |
336 | intel_pch_panel_fitting(dev, |
337 | intel_connector->panel.fitting_mode, | |
1d8e1c75 CW |
338 | mode, adjusted_mode); |
339 | return true; | |
340 | } | |
79e53945 | 341 | |
3fbe18d6 ZY |
342 | /* Native modes don't need fitting */ |
343 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 344 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 345 | goto out; |
3fbe18d6 ZY |
346 | |
347 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 348 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
349 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
350 | PFIT_FILTER_FUZZY); | |
351 | ||
3fbe18d6 ZY |
352 | /* |
353 | * Enable automatic panel scaling for non-native modes so that they fill | |
354 | * the screen. Should be enabled before the pipe is enabled, according | |
355 | * to register description and PRM. | |
356 | * Change the value here to see the borders for debugging | |
357 | */ | |
9db4a9c7 JB |
358 | for_each_pipe(pipe) |
359 | I915_WRITE(BCLRPAT(pipe), 0); | |
3fbe18d6 | 360 | |
f9bef081 DV |
361 | drm_mode_set_crtcinfo(adjusted_mode, 0); |
362 | ||
4d891523 | 363 | switch (intel_connector->panel.fitting_mode) { |
53bd8389 | 364 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
365 | /* |
366 | * For centered modes, we have to calculate border widths & | |
367 | * heights and modify the values programmed into the CRTC. | |
368 | */ | |
49be663f CW |
369 | centre_horizontally(adjusted_mode, mode->hdisplay); |
370 | centre_vertically(adjusted_mode, mode->vdisplay); | |
371 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 372 | break; |
49be663f | 373 | |
3fbe18d6 | 374 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 375 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 376 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
377 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
378 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
379 | ||
3fbe18d6 | 380 | /* 965+ is easy, it does everything in hw */ |
49be663f | 381 | if (scaled_width > scaled_height) |
257e48f1 | 382 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 383 | else if (scaled_width < scaled_height) |
257e48f1 CW |
384 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
385 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
386 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 387 | } else { |
49be663f CW |
388 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
389 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
390 | /* |
391 | * For earlier chips we have to calculate the scaling | |
392 | * ratio by hand and program it into the | |
393 | * PFIT_PGM_RATIO register | |
394 | */ | |
49be663f CW |
395 | if (scaled_width > scaled_height) { /* pillar */ |
396 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
397 | ||
398 | border = LVDS_BORDER_ENABLE; | |
399 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
400 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
401 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
402 | bits << PFIT_VERT_SCALE_SHIFT); | |
403 | pfit_control |= (PFIT_ENABLE | | |
404 | VERT_INTERP_BILINEAR | | |
405 | HORIZ_INTERP_BILINEAR); | |
406 | } | |
407 | } else if (scaled_width < scaled_height) { /* letter */ | |
408 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
409 | ||
410 | border = LVDS_BORDER_ENABLE; | |
411 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
412 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
413 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
414 | bits << PFIT_VERT_SCALE_SHIFT); | |
415 | pfit_control |= (PFIT_ENABLE | | |
416 | VERT_INTERP_BILINEAR | | |
417 | HORIZ_INTERP_BILINEAR); | |
418 | } | |
419 | } else | |
420 | /* Aspects match, Let hw scale both directions */ | |
421 | pfit_control |= (PFIT_ENABLE | | |
422 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
423 | VERT_INTERP_BILINEAR | |
424 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
425 | } |
426 | break; | |
427 | ||
428 | case DRM_MODE_SCALE_FULLSCREEN: | |
429 | /* | |
430 | * Full scaling, even if it changes the aspect ratio. | |
431 | * Fortunately this is all done for us in hw. | |
432 | */ | |
257e48f1 CW |
433 | if (mode->vdisplay != adjusted_mode->vdisplay || |
434 | mode->hdisplay != adjusted_mode->hdisplay) { | |
435 | pfit_control |= PFIT_ENABLE; | |
436 | if (INTEL_INFO(dev)->gen >= 4) | |
437 | pfit_control |= PFIT_SCALING_AUTO; | |
438 | else | |
439 | pfit_control |= (VERT_AUTO_SCALE | | |
440 | VERT_INTERP_BILINEAR | | |
441 | HORIZ_AUTO_SCALE | | |
442 | HORIZ_INTERP_BILINEAR); | |
443 | } | |
3fbe18d6 | 444 | break; |
49be663f | 445 | |
3fbe18d6 ZY |
446 | default: |
447 | break; | |
448 | } | |
449 | ||
450 | out: | |
72389a33 | 451 | /* If not enabling scaling, be consistent and always use 0. */ |
bee17e5a CW |
452 | if ((pfit_control & PFIT_ENABLE) == 0) { |
453 | pfit_control = 0; | |
454 | pfit_pgm_ratios = 0; | |
455 | } | |
72389a33 CW |
456 | |
457 | /* Make sure pre-965 set dither correctly */ | |
458 | if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither) | |
459 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; | |
460 | ||
29b99b48 JN |
461 | if (pfit_control != lvds_encoder->pfit_control || |
462 | pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) { | |
463 | lvds_encoder->pfit_control = pfit_control; | |
464 | lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios; | |
e9e331a8 | 465 | } |
49be663f CW |
466 | dev_priv->lvds_border_bits = border; |
467 | ||
79e53945 JB |
468 | /* |
469 | * XXX: It would be nice to support lower refresh rates on the | |
470 | * panels to reduce power consumption, and perhaps match the | |
471 | * user's requested refresh rate. | |
472 | */ | |
473 | ||
474 | return true; | |
475 | } | |
476 | ||
79e53945 JB |
477 | static void intel_lvds_mode_set(struct drm_encoder *encoder, |
478 | struct drm_display_mode *mode, | |
479 | struct drm_display_mode *adjusted_mode) | |
480 | { | |
79e53945 JB |
481 | /* |
482 | * The LVDS pin pair will already have been turned on in the | |
483 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
484 | * settings. | |
485 | */ | |
79e53945 JB |
486 | } |
487 | ||
488 | /** | |
489 | * Detect the LVDS connection. | |
490 | * | |
b42d4c5c JB |
491 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
492 | * connected and closed means disconnected. We also send hotplug events as | |
493 | * needed, using lid status notification from the input layer. | |
79e53945 | 494 | */ |
7b334fcb | 495 | static enum drm_connector_status |
930a9e28 | 496 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 497 | { |
7b9c5abe | 498 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 499 | enum drm_connector_status status; |
b42d4c5c | 500 | |
fe16d949 CW |
501 | status = intel_panel_detect(dev); |
502 | if (status != connector_status_unknown) | |
503 | return status; | |
01fe9dbd | 504 | |
6ee3b5a1 | 505 | return connector_status_connected; |
79e53945 JB |
506 | } |
507 | ||
508 | /** | |
509 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
510 | */ | |
511 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
512 | { | |
62165e0d | 513 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 514 | struct drm_device *dev = connector->dev; |
788319d4 | 515 | struct drm_display_mode *mode; |
79e53945 | 516 | |
9cd300e0 | 517 | /* use cached edid if we have one */ |
2aa4f099 | 518 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 519 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 520 | |
dd06f90e | 521 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 522 | if (mode == NULL) |
788319d4 | 523 | return 0; |
79e53945 | 524 | |
788319d4 CW |
525 | drm_mode_probed_add(connector, mode); |
526 | return 1; | |
79e53945 JB |
527 | } |
528 | ||
0544edfd TB |
529 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
530 | { | |
bc0daf48 | 531 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
532 | return 1; |
533 | } | |
534 | ||
535 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
536 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
537 | { | |
538 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
539 | .ident = "Toshiba Tecra A11", | |
540 | .matches = { | |
541 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
542 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
543 | }, | |
544 | }, | |
545 | ||
546 | { } /* terminating entry */ | |
547 | }; | |
548 | ||
c9354c85 | 549 | /* |
b8efb17b ZR |
550 | * Lid events. Note the use of 'modeset': |
551 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
552 | * and set it to MODESET_DONE on open | |
c9354c85 | 553 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
554 | * duplicate events where it was already properly set) |
555 | * - the suspend/resume paths will set it to | |
556 | * MODESET_SUSPENDED and ignore the lid open event, | |
557 | * because they restore the mode ("lid open"). | |
c9354c85 | 558 | */ |
c1c7af60 JB |
559 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
560 | void *unused) | |
561 | { | |
db1740a0 JN |
562 | struct intel_lvds_connector *lvds_connector = |
563 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
564 | struct drm_connector *connector = &lvds_connector->base.base; | |
565 | struct drm_device *dev = connector->dev; | |
566 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 567 | |
2fb4e61d AW |
568 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
569 | return NOTIFY_OK; | |
570 | ||
b8efb17b ZR |
571 | mutex_lock(&dev_priv->modeset_restore_lock); |
572 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
573 | goto exit; | |
a2565377 ZY |
574 | /* |
575 | * check and update the status of LVDS connector after receiving | |
576 | * the LID nofication event. | |
577 | */ | |
db1740a0 | 578 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 579 | |
0544edfd TB |
580 | /* Don't force modeset on machines where it causes a GPU lockup */ |
581 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 582 | goto exit; |
c9354c85 | 583 | if (!acpi_lid_open()) { |
b8efb17b ZR |
584 | /* do modeset on next lid open event */ |
585 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
586 | goto exit; | |
06891e27 | 587 | } |
c1c7af60 | 588 | |
b8efb17b ZR |
589 | if (dev_priv->modeset_restore == MODESET_DONE) |
590 | goto exit; | |
c9354c85 | 591 | |
a0e99e68 | 592 | drm_modeset_lock_all(dev); |
45e2b5f6 | 593 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 594 | drm_modeset_unlock_all(dev); |
06324194 | 595 | |
b8efb17b ZR |
596 | dev_priv->modeset_restore = MODESET_DONE; |
597 | ||
598 | exit: | |
599 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
600 | return NOTIFY_OK; |
601 | } | |
602 | ||
79e53945 JB |
603 | /** |
604 | * intel_lvds_destroy - unregister and free LVDS structures | |
605 | * @connector: connector to free | |
606 | * | |
607 | * Unregister the DDC bus for this connector then free the driver private | |
608 | * structure. | |
609 | */ | |
610 | static void intel_lvds_destroy(struct drm_connector *connector) | |
611 | { | |
db1740a0 JN |
612 | struct intel_lvds_connector *lvds_connector = |
613 | to_lvds_connector(connector); | |
79e53945 | 614 | |
db1740a0 JN |
615 | if (lvds_connector->lid_notifier.notifier_call) |
616 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 617 | |
9cd300e0 JN |
618 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
619 | kfree(lvds_connector->base.edid); | |
620 | ||
db1740a0 | 621 | intel_panel_destroy_backlight(connector->dev); |
1d508706 | 622 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 623 | |
79e53945 JB |
624 | drm_sysfs_connector_remove(connector); |
625 | drm_connector_cleanup(connector); | |
626 | kfree(connector); | |
627 | } | |
628 | ||
335041ed JB |
629 | static int intel_lvds_set_property(struct drm_connector *connector, |
630 | struct drm_property *property, | |
631 | uint64_t value) | |
632 | { | |
4d891523 | 633 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 634 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 635 | |
788319d4 | 636 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 637 | struct drm_crtc *crtc; |
bb8a3560 | 638 | |
53bd8389 JB |
639 | if (value == DRM_MODE_SCALE_NONE) { |
640 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 641 | return -EINVAL; |
3fbe18d6 | 642 | } |
788319d4 | 643 | |
4d891523 | 644 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
645 | /* the LVDS scaling property is not changed */ |
646 | return 0; | |
647 | } | |
4d891523 | 648 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
649 | |
650 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
651 | if (crtc && crtc->enabled) { |
652 | /* | |
653 | * If the CRTC is enabled, the display will be changed | |
654 | * according to the new panel fitting mode. | |
655 | */ | |
c0c36b94 | 656 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
657 | } |
658 | } | |
659 | ||
335041ed JB |
660 | return 0; |
661 | } | |
662 | ||
79e53945 | 663 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
79e53945 | 664 | .mode_fixup = intel_lvds_mode_fixup, |
79e53945 | 665 | .mode_set = intel_lvds_mode_set, |
79e53945 JB |
666 | }; |
667 | ||
668 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
669 | .get_modes = intel_lvds_get_modes, | |
670 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 671 | .best_encoder = intel_best_encoder, |
79e53945 JB |
672 | }; |
673 | ||
674 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 675 | .dpms = intel_connector_dpms, |
79e53945 JB |
676 | .detect = intel_lvds_detect, |
677 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 678 | .set_property = intel_lvds_set_property, |
79e53945 JB |
679 | .destroy = intel_lvds_destroy, |
680 | }; | |
681 | ||
79e53945 | 682 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 683 | .destroy = intel_encoder_destroy, |
79e53945 JB |
684 | }; |
685 | ||
425d244c JW |
686 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
687 | { | |
bc0daf48 | 688 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
689 | return 1; |
690 | } | |
79e53945 | 691 | |
425d244c | 692 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 693 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
694 | { |
695 | .callback = intel_no_lvds_dmi_callback, | |
696 | .ident = "Apple Mac Mini (Core series)", | |
697 | .matches = { | |
98acd46f | 698 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
699 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
700 | }, | |
701 | }, | |
702 | { | |
703 | .callback = intel_no_lvds_dmi_callback, | |
704 | .ident = "Apple Mac Mini (Core 2 series)", | |
705 | .matches = { | |
98acd46f | 706 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
707 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
708 | }, | |
709 | }, | |
710 | { | |
711 | .callback = intel_no_lvds_dmi_callback, | |
712 | .ident = "MSI IM-945GSE-A", | |
713 | .matches = { | |
714 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
715 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
716 | }, | |
717 | }, | |
718 | { | |
719 | .callback = intel_no_lvds_dmi_callback, | |
720 | .ident = "Dell Studio Hybrid", | |
721 | .matches = { | |
722 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
723 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
724 | }, | |
725 | }, | |
70aa96ca JW |
726 | { |
727 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
728 | .ident = "Dell OptiPlex FX170", |
729 | .matches = { | |
730 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
731 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
732 | }, | |
733 | }, | |
734 | { | |
735 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
736 | .ident = "AOpen Mini PC", |
737 | .matches = { | |
738 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
739 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
740 | }, | |
741 | }, | |
ed8c754b TV |
742 | { |
743 | .callback = intel_no_lvds_dmi_callback, | |
744 | .ident = "AOpen Mini PC MP915", | |
745 | .matches = { | |
746 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
747 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
748 | }, | |
749 | }, | |
22ab70d3 KP |
750 | { |
751 | .callback = intel_no_lvds_dmi_callback, | |
752 | .ident = "AOpen i915GMm-HFS", | |
753 | .matches = { | |
754 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
755 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
756 | }, | |
757 | }, | |
e57b6886 DV |
758 | { |
759 | .callback = intel_no_lvds_dmi_callback, | |
760 | .ident = "AOpen i45GMx-I", | |
761 | .matches = { | |
762 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
763 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
764 | }, | |
765 | }, | |
fa0864b2 MC |
766 | { |
767 | .callback = intel_no_lvds_dmi_callback, | |
768 | .ident = "Aopen i945GTt-VFA", | |
769 | .matches = { | |
770 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
771 | }, | |
772 | }, | |
9875557e SB |
773 | { |
774 | .callback = intel_no_lvds_dmi_callback, | |
775 | .ident = "Clientron U800", | |
776 | .matches = { | |
777 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
778 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
779 | }, | |
780 | }, | |
6a574b5b | 781 | { |
44306ab3 JS |
782 | .callback = intel_no_lvds_dmi_callback, |
783 | .ident = "Clientron E830", | |
784 | .matches = { | |
785 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
786 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
787 | }, | |
788 | }, | |
789 | { | |
6a574b5b HG |
790 | .callback = intel_no_lvds_dmi_callback, |
791 | .ident = "Asus EeeBox PC EB1007", | |
792 | .matches = { | |
793 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
794 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
795 | }, | |
796 | }, | |
0999bbe0 AJ |
797 | { |
798 | .callback = intel_no_lvds_dmi_callback, | |
799 | .ident = "Asus AT5NM10T-I", | |
800 | .matches = { | |
801 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
802 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
803 | }, | |
804 | }, | |
33471119 JBG |
805 | { |
806 | .callback = intel_no_lvds_dmi_callback, | |
807 | .ident = "Hewlett-Packard HP t5740e Thin Client", | |
808 | .matches = { | |
809 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
810 | DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"), | |
811 | }, | |
812 | }, | |
f5b8a7ed MG |
813 | { |
814 | .callback = intel_no_lvds_dmi_callback, | |
815 | .ident = "Hewlett-Packard t5745", | |
816 | .matches = { | |
817 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 818 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
819 | }, |
820 | }, | |
821 | { | |
822 | .callback = intel_no_lvds_dmi_callback, | |
823 | .ident = "Hewlett-Packard st5747", | |
824 | .matches = { | |
825 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 826 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
827 | }, |
828 | }, | |
97effadb AA |
829 | { |
830 | .callback = intel_no_lvds_dmi_callback, | |
831 | .ident = "MSI Wind Box DC500", | |
832 | .matches = { | |
833 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
834 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
835 | }, | |
836 | }, | |
a51d4ed0 CW |
837 | { |
838 | .callback = intel_no_lvds_dmi_callback, | |
839 | .ident = "Gigabyte GA-D525TUD", | |
840 | .matches = { | |
841 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
842 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
843 | }, | |
844 | }, | |
c31407a3 CW |
845 | { |
846 | .callback = intel_no_lvds_dmi_callback, | |
847 | .ident = "Supermicro X7SPA-H", | |
848 | .matches = { | |
849 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
850 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
851 | }, | |
852 | }, | |
425d244c JW |
853 | |
854 | { } /* terminating entry */ | |
855 | }; | |
79e53945 | 856 | |
18f9ed12 ZY |
857 | /** |
858 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
859 | * @dev: drm device | |
860 | * @connector: LVDS connector | |
861 | * | |
862 | * Find the reduced downclock for LVDS in EDID. | |
863 | */ | |
864 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
865 | struct drm_display_mode *fixed_mode, |
866 | struct drm_connector *connector) | |
18f9ed12 ZY |
867 | { |
868 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 869 | struct drm_display_mode *scan; |
18f9ed12 ZY |
870 | int temp_downclock; |
871 | ||
788319d4 | 872 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
873 | list_for_each_entry(scan, &connector->probed_modes, head) { |
874 | /* | |
875 | * If one mode has the same resolution with the fixed_panel | |
876 | * mode while they have the different refresh rate, it means | |
877 | * that the reduced downclock is found for the LVDS. In such | |
878 | * case we can set the different FPx0/1 to dynamically select | |
879 | * between low and high frequency. | |
880 | */ | |
788319d4 CW |
881 | if (scan->hdisplay == fixed_mode->hdisplay && |
882 | scan->hsync_start == fixed_mode->hsync_start && | |
883 | scan->hsync_end == fixed_mode->hsync_end && | |
884 | scan->htotal == fixed_mode->htotal && | |
885 | scan->vdisplay == fixed_mode->vdisplay && | |
886 | scan->vsync_start == fixed_mode->vsync_start && | |
887 | scan->vsync_end == fixed_mode->vsync_end && | |
888 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
889 | if (scan->clock < temp_downclock) { |
890 | /* | |
891 | * The downclock is already found. But we | |
892 | * expect to find the lower downclock. | |
893 | */ | |
894 | temp_downclock = scan->clock; | |
895 | } | |
896 | } | |
897 | } | |
788319d4 | 898 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
899 | /* We found the downclock for LVDS. */ |
900 | dev_priv->lvds_downclock_avail = 1; | |
901 | dev_priv->lvds_downclock = temp_downclock; | |
902 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
903 | "Normal clock %dKhz, downclock %dKhz\n", |
904 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 905 | } |
18f9ed12 ZY |
906 | } |
907 | ||
7cf4f69d ZY |
908 | /* |
909 | * Enumerate the child dev array parsed from VBT to check whether | |
910 | * the LVDS is present. | |
911 | * If it is present, return 1. | |
912 | * If it is not present, return false. | |
913 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 914 | */ |
270eea0f CW |
915 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
916 | u8 *i2c_pin) | |
7cf4f69d ZY |
917 | { |
918 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 919 | int i; |
7cf4f69d ZY |
920 | |
921 | if (!dev_priv->child_dev_num) | |
425904dd | 922 | return true; |
7cf4f69d | 923 | |
7cf4f69d | 924 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
925 | struct child_device_config *child = dev_priv->child_dev + i; |
926 | ||
927 | /* If the device type is not LFP, continue. | |
928 | * We have to check both the new identifiers as well as the | |
929 | * old for compatibility with some BIOSes. | |
7cf4f69d | 930 | */ |
425904dd CW |
931 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
932 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
933 | continue; |
934 | ||
3bd7d909 DK |
935 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
936 | *i2c_pin = child->i2c_pin; | |
270eea0f | 937 | |
425904dd CW |
938 | /* However, we cannot trust the BIOS writers to populate |
939 | * the VBT correctly. Since LVDS requires additional | |
940 | * information from AIM blocks, a non-zero addin offset is | |
941 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 942 | */ |
425904dd CW |
943 | if (child->addin_offset) |
944 | return true; | |
945 | ||
946 | /* But even then some BIOS writers perform some black magic | |
947 | * and instantiate the device without reference to any | |
948 | * additional data. Trust that if the VBT was written into | |
949 | * the OpRegion then they have validated the LVDS's existence. | |
950 | */ | |
951 | if (dev_priv->opregion.vbt) | |
952 | return true; | |
7cf4f69d | 953 | } |
425904dd CW |
954 | |
955 | return false; | |
7cf4f69d ZY |
956 | } |
957 | ||
1974cad0 DV |
958 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
959 | { | |
960 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
961 | return 1; | |
962 | } | |
963 | ||
964 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
965 | { | |
966 | .callback = intel_dual_link_lvds_callback, | |
967 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
968 | .matches = { | |
969 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
970 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
971 | }, | |
972 | }, | |
973 | { } /* terminating entry */ | |
974 | }; | |
975 | ||
976 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
977 | { |
978 | struct intel_encoder *encoder; | |
979 | struct intel_lvds_encoder *lvds_encoder; | |
980 | ||
981 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
982 | base.head) { | |
983 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
984 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
985 | ||
986 | return lvds_encoder->is_dual_link; | |
987 | } | |
988 | } | |
989 | ||
990 | return false; | |
991 | } | |
992 | ||
7dec0606 | 993 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 994 | { |
7dec0606 | 995 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
996 | unsigned int val; |
997 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
998 | |
999 | /* use the module option value if specified */ | |
1000 | if (i915_lvds_channel_mode > 0) | |
1001 | return i915_lvds_channel_mode == 2; | |
1002 | ||
1003 | if (dmi_check_system(intel_dual_link_lvds)) | |
1004 | return true; | |
1005 | ||
13c7d870 DV |
1006 | /* BIOS should set the proper LVDS register value at boot, but |
1007 | * in reality, it doesn't set the value when the lid is closed; | |
1008 | * we need to check "the value to be set" in VBT when LVDS | |
1009 | * register is uninitialized. | |
1010 | */ | |
7dec0606 | 1011 | val = I915_READ(lvds_encoder->reg); |
13c7d870 DV |
1012 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
1013 | val = dev_priv->bios_lvds_val; | |
1014 | ||
1974cad0 DV |
1015 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
1016 | } | |
1017 | ||
f3cfcba6 CW |
1018 | static bool intel_lvds_supported(struct drm_device *dev) |
1019 | { | |
1020 | /* With the introduction of the PCH we gained a dedicated | |
1021 | * LVDS presence pin, use it. */ | |
311e359c | 1022 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
1023 | return true; |
1024 | ||
1025 | /* Otherwise LVDS was only attached to mobile products, | |
1026 | * except for the inglorious 830gm */ | |
311e359c PZ |
1027 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
1028 | return true; | |
1029 | ||
1030 | return false; | |
f3cfcba6 CW |
1031 | } |
1032 | ||
79e53945 JB |
1033 | /** |
1034 | * intel_lvds_init - setup LVDS connectors on this device | |
1035 | * @dev: drm device | |
1036 | * | |
1037 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
1038 | * modes we can display on the LVDS panel (if present). | |
1039 | */ | |
c5d1b51d | 1040 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
1041 | { |
1042 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 1043 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 1044 | struct intel_encoder *intel_encoder; |
c7362c4d | 1045 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 1046 | struct intel_connector *intel_connector; |
79e53945 JB |
1047 | struct drm_connector *connector; |
1048 | struct drm_encoder *encoder; | |
1049 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 1050 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 1051 | struct edid *edid; |
79e53945 JB |
1052 | struct drm_crtc *crtc; |
1053 | u32 lvds; | |
270eea0f CW |
1054 | int pipe; |
1055 | u8 pin; | |
79e53945 | 1056 | |
f3cfcba6 CW |
1057 | if (!intel_lvds_supported(dev)) |
1058 | return false; | |
1059 | ||
425d244c JW |
1060 | /* Skip init on machines we know falsely report LVDS */ |
1061 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 1062 | return false; |
565dcd46 | 1063 | |
270eea0f CW |
1064 | pin = GMBUS_PORT_PANEL; |
1065 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 1066 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 1067 | return false; |
38b3037e | 1068 | } |
e99da35f | 1069 | |
c619eed4 | 1070 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1071 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 1072 | return false; |
5ceb0f9b | 1073 | if (dev_priv->edp.support) { |
28c97730 | 1074 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 1075 | return false; |
32f9d658 | 1076 | } |
541998a1 ZW |
1077 | } |
1078 | ||
29b99b48 JN |
1079 | lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL); |
1080 | if (!lvds_encoder) | |
c5d1b51d | 1081 | return false; |
79e53945 | 1082 | |
c7362c4d JN |
1083 | lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL); |
1084 | if (!lvds_connector) { | |
29b99b48 | 1085 | kfree(lvds_encoder); |
c5d1b51d | 1086 | return false; |
bb8a3560 ZW |
1087 | } |
1088 | ||
62165e0d JN |
1089 | lvds_encoder->attached_connector = lvds_connector; |
1090 | ||
e9e331a8 | 1091 | if (!HAS_PCH_SPLIT(dev)) { |
29b99b48 | 1092 | lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL); |
e9e331a8 CW |
1093 | } |
1094 | ||
29b99b48 | 1095 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1096 | encoder = &intel_encoder->base; |
c7362c4d | 1097 | intel_connector = &lvds_connector->base; |
ea5b213a | 1098 | connector = &intel_connector->base; |
bb8a3560 | 1099 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1100 | DRM_MODE_CONNECTOR_LVDS); |
1101 | ||
4ef69c7a | 1102 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
1103 | DRM_MODE_ENCODER_LVDS); |
1104 | ||
c22834ec | 1105 | intel_encoder->enable = intel_enable_lvds; |
9d6d9f19 | 1106 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
fc683091 | 1107 | intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds; |
c22834ec | 1108 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c DV |
1109 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
1110 | intel_connector->get_hw_state = intel_connector_get_hw_state; | |
c22834ec | 1111 | |
df0e9248 | 1112 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1113 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1114 | |
66a9278e | 1115 | intel_encoder->cloneable = false; |
27f8227b JB |
1116 | if (HAS_PCH_SPLIT(dev)) |
1117 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1118 | else if (IS_GEN4(dev)) |
1119 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1120 | else |
1121 | intel_encoder->crtc_mask = (1 << 1); | |
1122 | ||
79e53945 JB |
1123 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
1124 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
1125 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1126 | connector->interlace_allowed = false; | |
1127 | connector->doublescan_allowed = false; | |
1128 | ||
7dec0606 DV |
1129 | if (HAS_PCH_SPLIT(dev)) { |
1130 | lvds_encoder->reg = PCH_LVDS; | |
1131 | } else { | |
1132 | lvds_encoder->reg = LVDS; | |
1133 | } | |
1134 | ||
3fbe18d6 ZY |
1135 | /* create the scaling mode property */ |
1136 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1137 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1138 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1139 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1140 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1141 | /* |
1142 | * LVDS discovery: | |
1143 | * 1) check for EDID on DDC | |
1144 | * 2) check for VBT data | |
1145 | * 3) check to see if LVDS is already on | |
1146 | * if none of the above, no panel | |
1147 | * 4) make sure lid is open | |
1148 | * if closed, act like it's not there for now | |
1149 | */ | |
1150 | ||
79e53945 JB |
1151 | /* |
1152 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1153 | * preferred mode is the right one. | |
1154 | */ | |
9cd300e0 JN |
1155 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1156 | if (edid) { | |
1157 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1158 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1159 | edid); |
3f8ff0e7 | 1160 | } else { |
9cd300e0 JN |
1161 | kfree(edid); |
1162 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1163 | } |
9cd300e0 JN |
1164 | } else { |
1165 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1166 | } |
9cd300e0 JN |
1167 | lvds_connector->base.edid = edid; |
1168 | ||
1169 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1170 | /* Didn't get an EDID, so |
1171 | * Set wide sync ranges so we get all modes | |
1172 | * handed to valid_mode for checking | |
1173 | */ | |
1174 | connector->display_info.min_vfreq = 0; | |
1175 | connector->display_info.max_vfreq = 200; | |
1176 | connector->display_info.min_hfreq = 0; | |
1177 | connector->display_info.max_hfreq = 200; | |
1178 | } | |
79e53945 JB |
1179 | |
1180 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1181 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1182 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1183 | drm_mode_debug_printmodeline(scan); | |
1184 | ||
dd06f90e | 1185 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1186 | if (fixed_mode) { |
1187 | intel_find_lvds_downclock(dev, fixed_mode, | |
1188 | connector); | |
1189 | goto out; | |
1190 | } | |
79e53945 | 1191 | } |
79e53945 JB |
1192 | } |
1193 | ||
1194 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 1195 | if (dev_priv->lfp_lvds_vbt_mode) { |
6a9d51b7 CW |
1196 | DRM_DEBUG_KMS("using mode from VBT: "); |
1197 | drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode); | |
1198 | ||
dd06f90e JN |
1199 | fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
1200 | if (fixed_mode) { | |
1201 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1202 | goto out; |
1203 | } | |
79e53945 JB |
1204 | } |
1205 | ||
1206 | /* | |
1207 | * If we didn't get EDID, try checking if the panel is already turned | |
1208 | * on. If so, assume that whatever is currently programmed is the | |
1209 | * correct mode. | |
1210 | */ | |
541998a1 | 1211 | |
f2b115e6 | 1212 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1213 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1214 | goto failed; |
1215 | ||
79e53945 JB |
1216 | lvds = I915_READ(LVDS); |
1217 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1218 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1219 | |
1220 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1221 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1222 | if (fixed_mode) { | |
6a9d51b7 CW |
1223 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1224 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1225 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1226 | goto out; |
79e53945 JB |
1227 | } |
1228 | } | |
1229 | ||
1230 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1231 | if (!fixed_mode) |
79e53945 JB |
1232 | goto failed; |
1233 | ||
79e53945 | 1234 | out: |
7dec0606 | 1235 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1236 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1237 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1238 | ||
24ded204 DV |
1239 | /* |
1240 | * Unlock registers and just | |
1241 | * leave them unlocked | |
1242 | */ | |
c619eed4 | 1243 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1244 | I915_WRITE(PCH_PP_CONTROL, |
1245 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1246 | } else { | |
ed10fca9 KP |
1247 | I915_WRITE(PP_CONTROL, |
1248 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1249 | } |
db1740a0 JN |
1250 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1251 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1252 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1253 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1254 | } |
79e53945 | 1255 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1256 | |
dd06f90e | 1257 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1258 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1259 | |
c5d1b51d | 1260 | return true; |
79e53945 JB |
1261 | |
1262 | failed: | |
8a4c47f3 | 1263 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1264 | drm_connector_cleanup(connector); |
1991bdfa | 1265 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1266 | if (fixed_mode) |
1267 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1268 | kfree(lvds_encoder); |
c7362c4d | 1269 | kfree(lvds_connector); |
c5d1b51d | 1270 | return false; |
79e53945 | 1271 | } |