]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_lvds.c
drm/i915: add a display info file to debugfs v2
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
045ac3b5
JB
89static void intel_lvds_get_config(struct intel_encoder *encoder,
90 struct intel_crtc_config *pipe_config)
91{
92 struct drm_device *dev = encoder->base.dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 u32 lvds_reg, tmp, flags = 0;
18442d08 95 int dotclock;
045ac3b5
JB
96
97 if (HAS_PCH_SPLIT(dev))
98 lvds_reg = PCH_LVDS;
99 else
100 lvds_reg = LVDS;
101
102 tmp = I915_READ(lvds_reg);
103 if (tmp & LVDS_HSYNC_POLARITY)
104 flags |= DRM_MODE_FLAG_NHSYNC;
105 else
106 flags |= DRM_MODE_FLAG_PHSYNC;
107 if (tmp & LVDS_VSYNC_POLARITY)
108 flags |= DRM_MODE_FLAG_NVSYNC;
109 else
110 flags |= DRM_MODE_FLAG_PVSYNC;
111
112 pipe_config->adjusted_mode.flags |= flags;
06922821
DV
113
114 /* gen2/3 store dither state in pfit control, needs to match */
115 if (INTEL_INFO(dev)->gen < 4) {
116 tmp = I915_READ(PFIT_CONTROL);
117
118 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
119 }
18442d08
VS
120
121 dotclock = pipe_config->port_clock;
122
123 if (HAS_PCH_SPLIT(dev_priv->dev))
124 ironlake_check_encoder_dotclock(pipe_config, dotclock);
125
241bfc38 126 pipe_config->adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB
127}
128
fc683091
DV
129/* The LVDS pin pair needs to be on before the DPLLs are enabled.
130 * This is an exception to the general rule that mode_set doesn't turn
131 * things on.
132 */
f6736a1a 133static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
134{
135 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
136 struct drm_device *dev = encoder->base.dev;
137 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 138 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4c6df4b4
VS
139 const struct drm_display_mode *adjusted_mode =
140 &crtc->config.adjusted_mode;
55607e8a 141 int pipe = crtc->pipe;
fc683091
DV
142 u32 temp;
143
55607e8a
DV
144 if (HAS_PCH_SPLIT(dev)) {
145 assert_fdi_rx_pll_disabled(dev_priv, pipe);
146 assert_shared_dpll_disabled(dev_priv,
147 intel_crtc_to_shared_dpll(crtc));
148 } else {
149 assert_pll_disabled(dev_priv, pipe);
150 }
151
fc683091
DV
152 temp = I915_READ(lvds_encoder->reg);
153 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
154
155 if (HAS_PCH_CPT(dev)) {
156 temp &= ~PORT_TRANS_SEL_MASK;
157 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 158 } else {
62810e5a
DV
159 if (pipe == 1) {
160 temp |= LVDS_PIPEB_SELECT;
161 } else {
162 temp &= ~LVDS_PIPEB_SELECT;
163 }
fc683091 164 }
62810e5a 165
fc683091 166 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 167 temp &= ~LVDS_BORDER_ENABLE;
55607e8a 168 temp |= crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
169 /* Set the B0-B3 data pairs corresponding to whether we're going to
170 * set the DPLLs for dual-channel mode or not.
171 */
172 if (lvds_encoder->is_dual_link)
173 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
174 else
175 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
176
177 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
178 * appropriately here, but we need to look more thoroughly into how
179 * panels behave in the two modes.
180 */
62810e5a
DV
181
182 /* Set the dithering flag on LVDS as needed, note that there is no
183 * special lvds dither control bit on pch-split platforms, dithering is
184 * only controlled through the PIPECONF reg. */
185 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
186 /* Bspec wording suggests that LVDS port dithering only exists
187 * for 18bpp panels. */
55607e8a 188 if (crtc->config.dither && crtc->config.pipe_bpp == 18)
fc683091
DV
189 temp |= LVDS_ENABLE_DITHER;
190 else
191 temp &= ~LVDS_ENABLE_DITHER;
192 }
193 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 194 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 195 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 196 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
197 temp |= LVDS_VSYNC_POLARITY;
198
199 I915_WRITE(lvds_encoder->reg, temp);
200}
201
79e53945
JB
202/**
203 * Sets the power state for the panel.
204 */
c22834ec 205static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 206{
c22834ec 207 struct drm_device *dev = encoder->base.dev;
29b99b48 208 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
209 struct intel_connector *intel_connector =
210 &lvds_encoder->attached_connector->base;
79e53945 211 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 212 u32 ctl_reg, stat_reg;
541998a1 213
c619eed4 214 if (HAS_PCH_SPLIT(dev)) {
541998a1 215 ctl_reg = PCH_PP_CONTROL;
de842eff 216 stat_reg = PCH_PP_STATUS;
541998a1
ZW
217 } else {
218 ctl_reg = PP_CONTROL;
de842eff 219 stat_reg = PP_STATUS;
541998a1 220 }
79e53945 221
7dec0606 222 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 223
2a1292fd 224 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 225 POSTING_READ(lvds_encoder->reg);
de842eff
KP
226 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
227 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 228
752aa88a 229 intel_panel_enable_backlight(intel_connector);
2a1292fd
CW
230}
231
c22834ec 232static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 233{
c22834ec 234 struct drm_device *dev = encoder->base.dev;
29b99b48 235 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
236 struct intel_connector *intel_connector =
237 &lvds_encoder->attached_connector->base;
2a1292fd 238 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 239 u32 ctl_reg, stat_reg;
2a1292fd
CW
240
241 if (HAS_PCH_SPLIT(dev)) {
242 ctl_reg = PCH_PP_CONTROL;
de842eff 243 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
244 } else {
245 ctl_reg = PP_CONTROL;
de842eff 246 stat_reg = PP_STATUS;
2a1292fd
CW
247 }
248
752aa88a 249 intel_panel_disable_backlight(intel_connector);
2a1292fd
CW
250
251 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
252 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
253 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 254
7dec0606
DV
255 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
256 POSTING_READ(lvds_encoder->reg);
79e53945
JB
257}
258
c19de8eb
DL
259static enum drm_mode_status
260intel_lvds_mode_valid(struct drm_connector *connector,
261 struct drm_display_mode *mode)
79e53945 262{
dd06f90e
JN
263 struct intel_connector *intel_connector = to_intel_connector(connector);
264 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 265
788319d4
CW
266 if (mode->hdisplay > fixed_mode->hdisplay)
267 return MODE_PANEL;
268 if (mode->vdisplay > fixed_mode->vdisplay)
269 return MODE_PANEL;
79e53945
JB
270
271 return MODE_OK;
272}
273
7ae89233
DV
274static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
275 struct intel_crtc_config *pipe_config)
79e53945 276{
7ae89233 277 struct drm_device *dev = intel_encoder->base.dev;
79e53945 278 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
279 struct intel_lvds_encoder *lvds_encoder =
280 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
281 struct intel_connector *intel_connector =
282 &lvds_encoder->attached_connector->base;
7ae89233 283 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 284 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 285 unsigned int lvds_bpp;
79e53945
JB
286
287 /* Should never happen!! */
a6c45cf0 288 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 289 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
290 return false;
291 }
292
4e53c2e0
DV
293 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
294 LVDS_A3_POWER_UP)
295 lvds_bpp = 8*3;
296 else
297 lvds_bpp = 6*3;
298
e29c22c0 299 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
300 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
301 pipe_config->pipe_bpp, lvds_bpp);
302 pipe_config->pipe_bpp = lvds_bpp;
303 }
d8b32247 304
79e53945 305 /*
71677043 306 * We have timings from the BIOS for the panel, put them in
79e53945
JB
307 * to the adjusted mode. The CRTC will be set up for this mode,
308 * with the panel scaling set up to source from the H/VDisplay
309 * of the original mode.
310 */
4d891523 311 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 312 adjusted_mode);
1d8e1c75
CW
313
314 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
315 pipe_config->has_pch_encoder = true;
316
b074cec8
JB
317 intel_pch_panel_fitting(intel_crtc, pipe_config,
318 intel_connector->panel.fitting_mode);
2dd24552
JB
319 } else {
320 intel_gmch_panel_fitting(intel_crtc, pipe_config,
321 intel_connector->panel.fitting_mode);
79e53945 322
21d8a475 323 }
f9bef081 324
79e53945
JB
325 /*
326 * XXX: It would be nice to support lower refresh rates on the
327 * panels to reduce power consumption, and perhaps match the
328 * user's requested refresh rate.
329 */
330
331 return true;
332}
333
66df24d9 334static void intel_lvds_mode_set(struct intel_encoder *encoder)
79e53945 335{
79e53945 336 /*
66df24d9
DV
337 * We don't do anything here, the LVDS port is fully set up in the pre
338 * enable hook - the ordering constraints for enabling the lvds port vs.
339 * enabling the display pll are too strict.
79e53945 340 */
79e53945
JB
341}
342
343/**
344 * Detect the LVDS connection.
345 *
b42d4c5c
JB
346 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
347 * connected and closed means disconnected. We also send hotplug events as
348 * needed, using lid status notification from the input layer.
79e53945 349 */
7b334fcb 350static enum drm_connector_status
930a9e28 351intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 352{
7b9c5abe 353 struct drm_device *dev = connector->dev;
6ee3b5a1 354 enum drm_connector_status status;
b42d4c5c 355
164c8598
CW
356 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
357 connector->base.id, drm_get_connector_name(connector));
358
fe16d949
CW
359 status = intel_panel_detect(dev);
360 if (status != connector_status_unknown)
361 return status;
01fe9dbd 362
6ee3b5a1 363 return connector_status_connected;
79e53945
JB
364}
365
366/**
367 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
368 */
369static int intel_lvds_get_modes(struct drm_connector *connector)
370{
62165e0d 371 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 372 struct drm_device *dev = connector->dev;
788319d4 373 struct drm_display_mode *mode;
79e53945 374
9cd300e0 375 /* use cached edid if we have one */
2aa4f099 376 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 377 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 378
dd06f90e 379 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 380 if (mode == NULL)
788319d4 381 return 0;
79e53945 382
788319d4
CW
383 drm_mode_probed_add(connector, mode);
384 return 1;
79e53945
JB
385}
386
0544edfd
TB
387static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
388{
bc0daf48 389 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
390 return 1;
391}
392
393/* The GPU hangs up on these systems if modeset is performed on LID open */
394static const struct dmi_system_id intel_no_modeset_on_lid[] = {
395 {
396 .callback = intel_no_modeset_on_lid_dmi_callback,
397 .ident = "Toshiba Tecra A11",
398 .matches = {
399 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
400 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
401 },
402 },
403
404 { } /* terminating entry */
405};
406
c9354c85 407/*
b8efb17b
ZR
408 * Lid events. Note the use of 'modeset':
409 * - we set it to MODESET_ON_LID_OPEN on lid close,
410 * and set it to MODESET_DONE on open
c9354c85 411 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
412 * duplicate events where it was already properly set)
413 * - the suspend/resume paths will set it to
414 * MODESET_SUSPENDED and ignore the lid open event,
415 * because they restore the mode ("lid open").
c9354c85 416 */
c1c7af60
JB
417static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
418 void *unused)
419{
db1740a0
JN
420 struct intel_lvds_connector *lvds_connector =
421 container_of(nb, struct intel_lvds_connector, lid_notifier);
422 struct drm_connector *connector = &lvds_connector->base.base;
423 struct drm_device *dev = connector->dev;
424 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 425
2fb4e61d
AW
426 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
427 return NOTIFY_OK;
428
b8efb17b
ZR
429 mutex_lock(&dev_priv->modeset_restore_lock);
430 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
431 goto exit;
a2565377
ZY
432 /*
433 * check and update the status of LVDS connector after receiving
434 * the LID nofication event.
435 */
db1740a0 436 connector->status = connector->funcs->detect(connector, false);
7b334fcb 437
0544edfd
TB
438 /* Don't force modeset on machines where it causes a GPU lockup */
439 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 440 goto exit;
c9354c85 441 if (!acpi_lid_open()) {
b8efb17b
ZR
442 /* do modeset on next lid open event */
443 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
444 goto exit;
06891e27 445 }
c1c7af60 446
b8efb17b
ZR
447 if (dev_priv->modeset_restore == MODESET_DONE)
448 goto exit;
c9354c85 449
5be19d91
DV
450 /*
451 * Some old platform's BIOS love to wreak havoc while the lid is closed.
452 * We try to detect this here and undo any damage. The split for PCH
453 * platforms is rather conservative and a bit arbitrary expect that on
454 * those platforms VGA disabling requires actual legacy VGA I/O access,
455 * and as part of the cleanup in the hw state restore we also redisable
456 * the vga plane.
457 */
458 if (!HAS_PCH_SPLIT(dev)) {
459 drm_modeset_lock_all(dev);
460 intel_modeset_setup_hw_state(dev, true);
461 drm_modeset_unlock_all(dev);
462 }
06324194 463
b8efb17b
ZR
464 dev_priv->modeset_restore = MODESET_DONE;
465
466exit:
467 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
468 return NOTIFY_OK;
469}
470
79e53945
JB
471/**
472 * intel_lvds_destroy - unregister and free LVDS structures
473 * @connector: connector to free
474 *
475 * Unregister the DDC bus for this connector then free the driver private
476 * structure.
477 */
478static void intel_lvds_destroy(struct drm_connector *connector)
479{
db1740a0
JN
480 struct intel_lvds_connector *lvds_connector =
481 to_lvds_connector(connector);
79e53945 482
db1740a0
JN
483 if (lvds_connector->lid_notifier.notifier_call)
484 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 485
9cd300e0
JN
486 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
487 kfree(lvds_connector->base.edid);
488
1d508706 489 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 490
79e53945
JB
491 drm_connector_cleanup(connector);
492 kfree(connector);
493}
494
335041ed
JB
495static int intel_lvds_set_property(struct drm_connector *connector,
496 struct drm_property *property,
497 uint64_t value)
498{
4d891523 499 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 500 struct drm_device *dev = connector->dev;
3fbe18d6 501
788319d4 502 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 503 struct drm_crtc *crtc;
bb8a3560 504
53bd8389
JB
505 if (value == DRM_MODE_SCALE_NONE) {
506 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 507 return -EINVAL;
3fbe18d6 508 }
788319d4 509
4d891523 510 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
511 /* the LVDS scaling property is not changed */
512 return 0;
513 }
4d891523 514 intel_connector->panel.fitting_mode = value;
62165e0d
JN
515
516 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
517 if (crtc && crtc->enabled) {
518 /*
519 * If the CRTC is enabled, the display will be changed
520 * according to the new panel fitting mode.
521 */
c0c36b94 522 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
523 }
524 }
525
335041ed
JB
526 return 0;
527}
528
79e53945
JB
529static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
530 .get_modes = intel_lvds_get_modes,
531 .mode_valid = intel_lvds_mode_valid,
df0e9248 532 .best_encoder = intel_best_encoder,
79e53945
JB
533};
534
535static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 536 .dpms = intel_connector_dpms,
79e53945
JB
537 .detect = intel_lvds_detect,
538 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 539 .set_property = intel_lvds_set_property,
79e53945
JB
540 .destroy = intel_lvds_destroy,
541};
542
79e53945 543static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 544 .destroy = intel_encoder_destroy,
79e53945
JB
545};
546
425d244c
JW
547static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
548{
bc0daf48 549 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
550 return 1;
551}
79e53945 552
425d244c 553/* These systems claim to have LVDS, but really don't */
93c05f22 554static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
555 {
556 .callback = intel_no_lvds_dmi_callback,
557 .ident = "Apple Mac Mini (Core series)",
558 .matches = {
98acd46f 559 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
560 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
561 },
562 },
563 {
564 .callback = intel_no_lvds_dmi_callback,
565 .ident = "Apple Mac Mini (Core 2 series)",
566 .matches = {
98acd46f 567 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
568 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
569 },
570 },
571 {
572 .callback = intel_no_lvds_dmi_callback,
573 .ident = "MSI IM-945GSE-A",
574 .matches = {
575 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
576 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
577 },
578 },
579 {
580 .callback = intel_no_lvds_dmi_callback,
581 .ident = "Dell Studio Hybrid",
582 .matches = {
583 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
584 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
585 },
586 },
70aa96ca
JW
587 {
588 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
589 .ident = "Dell OptiPlex FX170",
590 .matches = {
591 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
592 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
593 },
594 },
595 {
596 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
597 .ident = "AOpen Mini PC",
598 .matches = {
599 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
600 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
601 },
602 },
ed8c754b
TV
603 {
604 .callback = intel_no_lvds_dmi_callback,
605 .ident = "AOpen Mini PC MP915",
606 .matches = {
607 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
608 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
609 },
610 },
22ab70d3
KP
611 {
612 .callback = intel_no_lvds_dmi_callback,
613 .ident = "AOpen i915GMm-HFS",
614 .matches = {
615 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
616 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
617 },
618 },
e57b6886
DV
619 {
620 .callback = intel_no_lvds_dmi_callback,
621 .ident = "AOpen i45GMx-I",
622 .matches = {
623 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
624 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
625 },
626 },
fa0864b2
MC
627 {
628 .callback = intel_no_lvds_dmi_callback,
629 .ident = "Aopen i945GTt-VFA",
630 .matches = {
631 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
632 },
633 },
9875557e
SB
634 {
635 .callback = intel_no_lvds_dmi_callback,
636 .ident = "Clientron U800",
637 .matches = {
638 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
639 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
640 },
641 },
6a574b5b 642 {
44306ab3
JS
643 .callback = intel_no_lvds_dmi_callback,
644 .ident = "Clientron E830",
645 .matches = {
646 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
647 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
648 },
649 },
650 {
6a574b5b
HG
651 .callback = intel_no_lvds_dmi_callback,
652 .ident = "Asus EeeBox PC EB1007",
653 .matches = {
654 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
655 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
656 },
657 },
0999bbe0
AJ
658 {
659 .callback = intel_no_lvds_dmi_callback,
660 .ident = "Asus AT5NM10T-I",
661 .matches = {
662 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
663 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
664 },
665 },
33471119
JBG
666 {
667 .callback = intel_no_lvds_dmi_callback,
45a211d7 668 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
669 .matches = {
670 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 671 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
672 },
673 },
f5b8a7ed
MG
674 {
675 .callback = intel_no_lvds_dmi_callback,
676 .ident = "Hewlett-Packard t5745",
677 .matches = {
678 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 679 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
680 },
681 },
682 {
683 .callback = intel_no_lvds_dmi_callback,
684 .ident = "Hewlett-Packard st5747",
685 .matches = {
686 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 687 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
688 },
689 },
97effadb
AA
690 {
691 .callback = intel_no_lvds_dmi_callback,
692 .ident = "MSI Wind Box DC500",
693 .matches = {
694 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
695 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
696 },
697 },
a51d4ed0
CW
698 {
699 .callback = intel_no_lvds_dmi_callback,
700 .ident = "Gigabyte GA-D525TUD",
701 .matches = {
702 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
703 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
704 },
705 },
c31407a3
CW
706 {
707 .callback = intel_no_lvds_dmi_callback,
708 .ident = "Supermicro X7SPA-H",
709 .matches = {
710 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
711 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
712 },
713 },
9e9dd0e8
CL
714 {
715 .callback = intel_no_lvds_dmi_callback,
716 .ident = "Fujitsu Esprimo Q900",
717 .matches = {
718 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
719 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
720 },
721 },
645378d8
RP
722 {
723 .callback = intel_no_lvds_dmi_callback,
724 .ident = "Intel D410PT",
725 .matches = {
726 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
727 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
728 },
729 },
730 {
731 .callback = intel_no_lvds_dmi_callback,
732 .ident = "Intel D425KT",
733 .matches = {
734 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
735 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
736 },
737 },
e5614f0c
CW
738 {
739 .callback = intel_no_lvds_dmi_callback,
740 .ident = "Intel D510MO",
741 .matches = {
742 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
743 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
744 },
745 },
dcf6d294
JN
746 {
747 .callback = intel_no_lvds_dmi_callback,
748 .ident = "Intel D525MW",
749 .matches = {
750 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
751 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
752 },
753 },
425d244c
JW
754
755 { } /* terminating entry */
756};
79e53945 757
7cf4f69d
ZY
758/*
759 * Enumerate the child dev array parsed from VBT to check whether
760 * the LVDS is present.
761 * If it is present, return 1.
762 * If it is not present, return false.
763 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 764 */
270eea0f
CW
765static bool lvds_is_present_in_vbt(struct drm_device *dev,
766 u8 *i2c_pin)
7cf4f69d
ZY
767{
768 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 769 int i;
7cf4f69d 770
41aa3448 771 if (!dev_priv->vbt.child_dev_num)
425904dd 772 return true;
7cf4f69d 773
41aa3448 774 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
768f69c9
PZ
775 union child_device_config *uchild = dev_priv->vbt.child_dev + i;
776 struct old_child_dev_config *child = &uchild->old;
425904dd
CW
777
778 /* If the device type is not LFP, continue.
779 * We have to check both the new identifiers as well as the
780 * old for compatibility with some BIOSes.
7cf4f69d 781 */
425904dd
CW
782 if (child->device_type != DEVICE_TYPE_INT_LFP &&
783 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
784 continue;
785
3bd7d909
DK
786 if (intel_gmbus_is_port_valid(child->i2c_pin))
787 *i2c_pin = child->i2c_pin;
270eea0f 788
425904dd
CW
789 /* However, we cannot trust the BIOS writers to populate
790 * the VBT correctly. Since LVDS requires additional
791 * information from AIM blocks, a non-zero addin offset is
792 * a good indicator that the LVDS is actually present.
7cf4f69d 793 */
425904dd
CW
794 if (child->addin_offset)
795 return true;
796
797 /* But even then some BIOS writers perform some black magic
798 * and instantiate the device without reference to any
799 * additional data. Trust that if the VBT was written into
800 * the OpRegion then they have validated the LVDS's existence.
801 */
802 if (dev_priv->opregion.vbt)
803 return true;
7cf4f69d 804 }
425904dd
CW
805
806 return false;
7cf4f69d
ZY
807}
808
1974cad0
DV
809static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
810{
811 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
812 return 1;
813}
814
815static const struct dmi_system_id intel_dual_link_lvds[] = {
816 {
817 .callback = intel_dual_link_lvds_callback,
818 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
819 .matches = {
820 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
821 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
822 },
823 },
824 { } /* terminating entry */
825};
826
827bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
828{
829 struct intel_encoder *encoder;
830 struct intel_lvds_encoder *lvds_encoder;
831
832 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
833 base.head) {
834 if (encoder->type == INTEL_OUTPUT_LVDS) {
835 lvds_encoder = to_lvds_encoder(&encoder->base);
836
837 return lvds_encoder->is_dual_link;
838 }
839 }
840
841 return false;
842}
843
7dec0606 844static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 845{
7dec0606 846 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
847 unsigned int val;
848 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
849
850 /* use the module option value if specified */
d330a953
JN
851 if (i915.lvds_channel_mode > 0)
852 return i915.lvds_channel_mode == 2;
1974cad0
DV
853
854 if (dmi_check_system(intel_dual_link_lvds))
855 return true;
856
13c7d870
DV
857 /* BIOS should set the proper LVDS register value at boot, but
858 * in reality, it doesn't set the value when the lid is closed;
859 * we need to check "the value to be set" in VBT when LVDS
860 * register is uninitialized.
861 */
7dec0606 862 val = I915_READ(lvds_encoder->reg);
13c7d870 863 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 864 val = dev_priv->vbt.bios_lvds_val;
13c7d870 865
1974cad0
DV
866 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
867}
868
f3cfcba6
CW
869static bool intel_lvds_supported(struct drm_device *dev)
870{
871 /* With the introduction of the PCH we gained a dedicated
872 * LVDS presence pin, use it. */
311e359c 873 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
874 return true;
875
876 /* Otherwise LVDS was only attached to mobile products,
877 * except for the inglorious 830gm */
311e359c
PZ
878 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
879 return true;
880
881 return false;
f3cfcba6
CW
882}
883
79e53945
JB
884/**
885 * intel_lvds_init - setup LVDS connectors on this device
886 * @dev: drm device
887 *
888 * Create the connector, register the LVDS DDC bus, and try to figure out what
889 * modes we can display on the LVDS panel (if present).
890 */
c9093354 891void intel_lvds_init(struct drm_device *dev)
79e53945
JB
892{
893 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 894 struct intel_lvds_encoder *lvds_encoder;
21d40d37 895 struct intel_encoder *intel_encoder;
c7362c4d 896 struct intel_lvds_connector *lvds_connector;
bb8a3560 897 struct intel_connector *intel_connector;
79e53945
JB
898 struct drm_connector *connector;
899 struct drm_encoder *encoder;
900 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 901 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 902 struct edid *edid;
79e53945
JB
903 struct drm_crtc *crtc;
904 u32 lvds;
270eea0f
CW
905 int pipe;
906 u8 pin;
79e53945 907
f3cfcba6 908 if (!intel_lvds_supported(dev))
c9093354 909 return;
f3cfcba6 910
425d244c
JW
911 /* Skip init on machines we know falsely report LVDS */
912 if (dmi_check_system(intel_no_lvds))
c9093354 913 return;
565dcd46 914
270eea0f
CW
915 pin = GMBUS_PORT_PANEL;
916 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 917 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c9093354 918 return;
38b3037e 919 }
e99da35f 920
c619eed4 921 if (HAS_PCH_SPLIT(dev)) {
541998a1 922 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 923 return;
41aa3448 924 if (dev_priv->vbt.edp_support) {
28c97730 925 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 926 return;
32f9d658 927 }
541998a1
ZW
928 }
929
b14c5679 930 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
29b99b48 931 if (!lvds_encoder)
c9093354 932 return;
79e53945 933
b14c5679 934 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
c7362c4d 935 if (!lvds_connector) {
29b99b48 936 kfree(lvds_encoder);
c9093354 937 return;
bb8a3560
ZW
938 }
939
62165e0d
JN
940 lvds_encoder->attached_connector = lvds_connector;
941
29b99b48 942 intel_encoder = &lvds_encoder->base;
4ef69c7a 943 encoder = &intel_encoder->base;
c7362c4d 944 intel_connector = &lvds_connector->base;
ea5b213a 945 connector = &intel_connector->base;
bb8a3560 946 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
947 DRM_MODE_CONNECTOR_LVDS);
948
4ef69c7a 949 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
950 DRM_MODE_ENCODER_LVDS);
951
c22834ec 952 intel_encoder->enable = intel_enable_lvds;
f6736a1a 953 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 954 intel_encoder->compute_config = intel_lvds_compute_config;
66df24d9 955 intel_encoder->mode_set = intel_lvds_mode_set;
c22834ec 956 intel_encoder->disable = intel_disable_lvds;
b1dc332c 957 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 958 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 959 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 960
df0e9248 961 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 962 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 963
66a9278e 964 intel_encoder->cloneable = false;
27f8227b
JB
965 if (HAS_PCH_SPLIT(dev))
966 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
967 else if (IS_GEN4(dev))
968 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
969 else
970 intel_encoder->crtc_mask = (1 << 1);
971
79e53945
JB
972 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
973 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
974 connector->interlace_allowed = false;
975 connector->doublescan_allowed = false;
976
7dec0606
DV
977 if (HAS_PCH_SPLIT(dev)) {
978 lvds_encoder->reg = PCH_LVDS;
979 } else {
980 lvds_encoder->reg = LVDS;
981 }
982
3fbe18d6
ZY
983 /* create the scaling mode property */
984 drm_mode_create_scaling_mode_property(dev);
662595df 985 drm_object_attach_property(&connector->base,
3fbe18d6 986 dev->mode_config.scaling_mode_property,
dd1ea37d 987 DRM_MODE_SCALE_ASPECT);
4d891523 988 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
989 /*
990 * LVDS discovery:
991 * 1) check for EDID on DDC
992 * 2) check for VBT data
993 * 3) check to see if LVDS is already on
994 * if none of the above, no panel
995 * 4) make sure lid is open
996 * if closed, act like it's not there for now
997 */
998
79e53945
JB
999 /*
1000 * Attempt to get the fixed panel mode from DDC. Assume that the
1001 * preferred mode is the right one.
1002 */
9cd300e0
JN
1003 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1004 if (edid) {
1005 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1006 drm_mode_connector_update_edid_property(connector,
9cd300e0 1007 edid);
3f8ff0e7 1008 } else {
9cd300e0
JN
1009 kfree(edid);
1010 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1011 }
9cd300e0
JN
1012 } else {
1013 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1014 }
9cd300e0
JN
1015 lvds_connector->base.edid = edid;
1016
1017 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1018 /* Didn't get an EDID, so
1019 * Set wide sync ranges so we get all modes
1020 * handed to valid_mode for checking
1021 */
1022 connector->display_info.min_vfreq = 0;
1023 connector->display_info.max_vfreq = 200;
1024 connector->display_info.min_hfreq = 0;
1025 connector->display_info.max_hfreq = 200;
1026 }
79e53945
JB
1027
1028 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1029 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1030 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1031 drm_mode_debug_printmodeline(scan);
1032
dd06f90e 1033 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7 1034 if (fixed_mode) {
ec9ed197
VK
1035 intel_connector->panel.downclock_mode =
1036 intel_find_panel_downclock(dev,
1037 fixed_mode, connector);
1038 if (intel_connector->panel.downclock_mode !=
d330a953 1039 NULL && i915.lvds_downclock) {
ec9ed197
VK
1040 /* We found the downclock for LVDS. */
1041 dev_priv->lvds_downclock_avail = true;
1042 dev_priv->lvds_downclock =
1043 intel_connector->panel.
1044 downclock_mode->clock;
1045 DRM_DEBUG_KMS("LVDS downclock is found"
1046 " in EDID. Normal clock %dKhz, "
1047 "downclock %dKhz\n",
1048 fixed_mode->clock,
1049 dev_priv->lvds_downclock);
1050 }
6a9d51b7
CW
1051 goto out;
1052 }
79e53945 1053 }
79e53945
JB
1054 }
1055
1056 /* Failed to get EDID, what about VBT? */
41aa3448 1057 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1058 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1059 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1060
41aa3448 1061 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1062 if (fixed_mode) {
1063 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1064 goto out;
1065 }
79e53945
JB
1066 }
1067
1068 /*
1069 * If we didn't get EDID, try checking if the panel is already turned
1070 * on. If so, assume that whatever is currently programmed is the
1071 * correct mode.
1072 */
541998a1 1073
f2b115e6 1074 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1075 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1076 goto failed;
1077
79e53945
JB
1078 lvds = I915_READ(LVDS);
1079 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1080 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1081
1082 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1083 fixed_mode = intel_crtc_mode_get(dev, crtc);
1084 if (fixed_mode) {
6a9d51b7
CW
1085 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1086 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1087 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1088 goto out;
79e53945
JB
1089 }
1090 }
1091
1092 /* If we still don't have a mode after all that, give up. */
dd06f90e 1093 if (!fixed_mode)
79e53945
JB
1094 goto failed;
1095
79e53945 1096out:
7dec0606 1097 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1098 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1099 lvds_encoder->is_dual_link ? "dual" : "single");
1100
24ded204
DV
1101 /*
1102 * Unlock registers and just
1103 * leave them unlocked
1104 */
c619eed4 1105 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1106 I915_WRITE(PCH_PP_CONTROL,
1107 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1108 } else {
ed10fca9
KP
1109 I915_WRITE(PP_CONTROL,
1110 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1111 }
db1740a0
JN
1112 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1113 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1114 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1115 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1116 }
79e53945 1117 drm_sysfs_connector_add(connector);
aaa6fd2a 1118
dd06f90e 1119 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1120 intel_panel_setup_backlight(connector);
aaa6fd2a 1121
c9093354 1122 return;
79e53945
JB
1123
1124failed:
8a4c47f3 1125 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1126 drm_connector_cleanup(connector);
1991bdfa 1127 drm_encoder_cleanup(encoder);
dd06f90e
JN
1128 if (fixed_mode)
1129 drm_mode_destroy(dev, fixed_mode);
29b99b48 1130 kfree(lvds_encoder);
c7362c4d 1131 kfree(lvds_connector);
c9093354 1132 return;
79e53945 1133}