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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
4eddaeec | 34 | #include <linux/vga_switcheroo.h> |
760285e7 | 35 | #include <drm/drmP.h> |
c6f95f27 | 36 | #include <drm/drm_atomic_helper.h> |
760285e7 DH |
37 | #include <drm/drm_crtc.h> |
38 | #include <drm/drm_edid.h> | |
79e53945 | 39 | #include "intel_drv.h" |
760285e7 | 40 | #include <drm/i915_drm.h> |
79e53945 | 41 | #include "i915_drv.h" |
e99da35f | 42 | #include <linux/acpi.h> |
79e53945 | 43 | |
3fbe18d6 | 44 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
45 | struct intel_lvds_connector { |
46 | struct intel_connector base; | |
788319d4 | 47 | |
db1740a0 | 48 | struct notifier_block lid_notifier; |
c7362c4d JN |
49 | }; |
50 | ||
ed6143b8 ID |
51 | struct intel_lvds_pps { |
52 | /* 100us units */ | |
53 | int t1_t2; | |
54 | int t3; | |
55 | int t4; | |
56 | int t5; | |
57 | int tx; | |
58 | ||
59 | int divider; | |
60 | ||
61 | int port; | |
62 | bool powerdown_on_reset; | |
63 | }; | |
64 | ||
29b99b48 | 65 | struct intel_lvds_encoder { |
ea5b213a | 66 | struct intel_encoder base; |
788319d4 | 67 | |
13c7d870 | 68 | bool is_dual_link; |
f0f59a00 | 69 | i915_reg_t reg; |
1f835a77 | 70 | u32 a3_power; |
788319d4 | 71 | |
ed6143b8 ID |
72 | struct intel_lvds_pps init_pps; |
73 | u32 init_lvds_val; | |
74 | ||
62165e0d | 75 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
76 | }; |
77 | ||
29b99b48 | 78 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 79 | { |
29b99b48 | 80 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
81 | } |
82 | ||
c7362c4d | 83 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 84 | { |
c7362c4d | 85 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
86 | } |
87 | ||
b1dc332c DV |
88 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
89 | enum pipe *pipe) | |
90 | { | |
91 | struct drm_device *dev = encoder->base.dev; | |
fac5e23e | 92 | struct drm_i915_private *dev_priv = to_i915(dev); |
7dec0606 | 93 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
34a6c70f | 94 | enum intel_display_power_domain power_domain; |
7dec0606 | 95 | u32 tmp; |
ecb24482 | 96 | bool ret; |
b1dc332c | 97 | |
34a6c70f | 98 | power_domain = intel_display_port_power_domain(encoder); |
ecb24482 | 99 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) |
34a6c70f PZ |
100 | return false; |
101 | ||
ecb24482 ID |
102 | ret = false; |
103 | ||
7dec0606 | 104 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
105 | |
106 | if (!(tmp & LVDS_PORT_EN)) | |
ecb24482 | 107 | goto out; |
b1dc332c | 108 | |
6e266956 | 109 | if (HAS_PCH_CPT(dev_priv)) |
b1dc332c DV |
110 | *pipe = PORT_TO_PIPE_CPT(tmp); |
111 | else | |
112 | *pipe = PORT_TO_PIPE(tmp); | |
113 | ||
ecb24482 ID |
114 | ret = true; |
115 | ||
116 | out: | |
117 | intel_display_power_put(dev_priv, power_domain); | |
118 | ||
119 | return ret; | |
b1dc332c DV |
120 | } |
121 | ||
045ac3b5 | 122 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
5cec258b | 123 | struct intel_crtc_state *pipe_config) |
045ac3b5 | 124 | { |
66478475 | 125 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
d0669d00 VS |
126 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
127 | u32 tmp, flags = 0; | |
045ac3b5 | 128 | |
d0669d00 | 129 | tmp = I915_READ(lvds_encoder->reg); |
045ac3b5 JB |
130 | if (tmp & LVDS_HSYNC_POLARITY) |
131 | flags |= DRM_MODE_FLAG_NHSYNC; | |
132 | else | |
133 | flags |= DRM_MODE_FLAG_PHSYNC; | |
134 | if (tmp & LVDS_VSYNC_POLARITY) | |
135 | flags |= DRM_MODE_FLAG_NVSYNC; | |
136 | else | |
137 | flags |= DRM_MODE_FLAG_PVSYNC; | |
138 | ||
2d112de7 | 139 | pipe_config->base.adjusted_mode.flags |= flags; |
06922821 | 140 | |
66478475 | 141 | if (INTEL_GEN(dev_priv) < 5) |
a0cbe6a3 JN |
142 | pipe_config->gmch_pfit.lvds_border_bits = |
143 | tmp & LVDS_BORDER_ENABLE; | |
144 | ||
6b89cdde | 145 | /* gen2/3 store dither state in pfit control, needs to match */ |
66478475 | 146 | if (INTEL_GEN(dev_priv) < 4) { |
6b89cdde DV |
147 | tmp = I915_READ(PFIT_CONTROL); |
148 | ||
149 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
150 | } | |
151 | ||
e3b247da | 152 | pipe_config->base.adjusted_mode.crtc_clock = pipe_config->port_clock; |
045ac3b5 JB |
153 | } |
154 | ||
ed6143b8 ID |
155 | static void intel_lvds_pps_get_hw_state(struct drm_i915_private *dev_priv, |
156 | struct intel_lvds_pps *pps) | |
157 | { | |
158 | u32 val; | |
159 | ||
160 | pps->powerdown_on_reset = I915_READ(PP_CONTROL(0)) & PANEL_POWER_RESET; | |
161 | ||
162 | val = I915_READ(PP_ON_DELAYS(0)); | |
163 | pps->port = (val & PANEL_PORT_SELECT_MASK) >> | |
164 | PANEL_PORT_SELECT_SHIFT; | |
165 | pps->t1_t2 = (val & PANEL_POWER_UP_DELAY_MASK) >> | |
166 | PANEL_POWER_UP_DELAY_SHIFT; | |
167 | pps->t5 = (val & PANEL_LIGHT_ON_DELAY_MASK) >> | |
168 | PANEL_LIGHT_ON_DELAY_SHIFT; | |
169 | ||
170 | val = I915_READ(PP_OFF_DELAYS(0)); | |
171 | pps->t3 = (val & PANEL_POWER_DOWN_DELAY_MASK) >> | |
172 | PANEL_POWER_DOWN_DELAY_SHIFT; | |
173 | pps->tx = (val & PANEL_LIGHT_OFF_DELAY_MASK) >> | |
174 | PANEL_LIGHT_OFF_DELAY_SHIFT; | |
175 | ||
176 | val = I915_READ(PP_DIVISOR(0)); | |
177 | pps->divider = (val & PP_REFERENCE_DIVIDER_MASK) >> | |
178 | PP_REFERENCE_DIVIDER_SHIFT; | |
179 | val = (val & PANEL_POWER_CYCLE_DELAY_MASK) >> | |
180 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
181 | /* | |
182 | * Remove the BSpec specified +1 (100ms) offset that accounts for a | |
183 | * too short power-cycle delay due to the asynchronous programming of | |
184 | * the register. | |
185 | */ | |
186 | if (val) | |
187 | val--; | |
188 | /* Convert from 100ms to 100us units */ | |
189 | pps->t4 = val * 1000; | |
190 | ||
191 | if (INTEL_INFO(dev_priv)->gen <= 4 && | |
192 | pps->t1_t2 == 0 && pps->t5 == 0 && pps->t3 == 0 && pps->tx == 0) { | |
193 | DRM_DEBUG_KMS("Panel power timings uninitialized, " | |
194 | "setting defaults\n"); | |
195 | /* Set T2 to 40ms and T5 to 200ms in 100 usec units */ | |
196 | pps->t1_t2 = 40 * 10; | |
197 | pps->t5 = 200 * 10; | |
198 | /* Set T3 to 35ms and Tx to 200ms in 100 usec units */ | |
199 | pps->t3 = 35 * 10; | |
200 | pps->tx = 200 * 10; | |
201 | } | |
202 | ||
203 | DRM_DEBUG_DRIVER("LVDS PPS:t1+t2 %d t3 %d t4 %d t5 %d tx %d " | |
204 | "divider %d port %d powerdown_on_reset %d\n", | |
205 | pps->t1_t2, pps->t3, pps->t4, pps->t5, pps->tx, | |
206 | pps->divider, pps->port, pps->powerdown_on_reset); | |
207 | } | |
208 | ||
209 | static void intel_lvds_pps_init_hw(struct drm_i915_private *dev_priv, | |
210 | struct intel_lvds_pps *pps) | |
211 | { | |
212 | u32 val; | |
213 | ||
214 | val = I915_READ(PP_CONTROL(0)); | |
215 | WARN_ON((val & PANEL_UNLOCK_MASK) != PANEL_UNLOCK_REGS); | |
216 | if (pps->powerdown_on_reset) | |
217 | val |= PANEL_POWER_RESET; | |
218 | I915_WRITE(PP_CONTROL(0), val); | |
219 | ||
220 | I915_WRITE(PP_ON_DELAYS(0), (pps->port << PANEL_PORT_SELECT_SHIFT) | | |
221 | (pps->t1_t2 << PANEL_POWER_UP_DELAY_SHIFT) | | |
222 | (pps->t5 << PANEL_LIGHT_ON_DELAY_SHIFT)); | |
223 | I915_WRITE(PP_OFF_DELAYS(0), (pps->t3 << PANEL_POWER_DOWN_DELAY_SHIFT) | | |
224 | (pps->tx << PANEL_LIGHT_OFF_DELAY_SHIFT)); | |
225 | ||
226 | val = pps->divider << PP_REFERENCE_DIVIDER_SHIFT; | |
227 | val |= (DIV_ROUND_UP(pps->t4, 1000) + 1) << | |
228 | PANEL_POWER_CYCLE_DELAY_SHIFT; | |
229 | I915_WRITE(PP_DIVISOR(0), val); | |
230 | } | |
231 | ||
fd6bbda9 ML |
232 | static void intel_pre_enable_lvds(struct intel_encoder *encoder, |
233 | struct intel_crtc_state *pipe_config, | |
234 | struct drm_connector_state *conn_state) | |
fc683091 DV |
235 | { |
236 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
d468e21e ML |
237 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
238 | struct intel_crtc *crtc = to_intel_crtc(pipe_config->base.crtc); | |
239 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; | |
55607e8a | 240 | int pipe = crtc->pipe; |
fc683091 DV |
241 | u32 temp; |
242 | ||
d468e21e | 243 | if (HAS_PCH_SPLIT(dev_priv)) { |
55607e8a DV |
244 | assert_fdi_rx_pll_disabled(dev_priv, pipe); |
245 | assert_shared_dpll_disabled(dev_priv, | |
d468e21e | 246 | pipe_config->shared_dpll); |
55607e8a DV |
247 | } else { |
248 | assert_pll_disabled(dev_priv, pipe); | |
249 | } | |
250 | ||
ed6143b8 ID |
251 | intel_lvds_pps_init_hw(dev_priv, &lvds_encoder->init_pps); |
252 | ||
253 | temp = lvds_encoder->init_lvds_val; | |
fc683091 | 254 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; |
62810e5a | 255 | |
d468e21e | 256 | if (HAS_PCH_CPT(dev_priv)) { |
62810e5a DV |
257 | temp &= ~PORT_TRANS_SEL_MASK; |
258 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 259 | } else { |
62810e5a DV |
260 | if (pipe == 1) { |
261 | temp |= LVDS_PIPEB_SELECT; | |
262 | } else { | |
263 | temp &= ~LVDS_PIPEB_SELECT; | |
264 | } | |
fc683091 | 265 | } |
62810e5a | 266 | |
fc683091 | 267 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 268 | temp &= ~LVDS_BORDER_ENABLE; |
d468e21e | 269 | temp |= pipe_config->gmch_pfit.lvds_border_bits; |
fc683091 DV |
270 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
271 | * set the DPLLs for dual-channel mode or not. | |
272 | */ | |
273 | if (lvds_encoder->is_dual_link) | |
274 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
275 | else | |
276 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
277 | ||
278 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
279 | * appropriately here, but we need to look more thoroughly into how | |
1f835a77 PZ |
280 | * panels behave in the two modes. For now, let's just maintain the |
281 | * value we got from the BIOS. | |
fc683091 | 282 | */ |
f1fda745 CW |
283 | temp &= ~LVDS_A3_POWER_MASK; |
284 | temp |= lvds_encoder->a3_power; | |
62810e5a DV |
285 | |
286 | /* Set the dithering flag on LVDS as needed, note that there is no | |
287 | * special lvds dither control bit on pch-split platforms, dithering is | |
288 | * only controlled through the PIPECONF reg. */ | |
7e22dbbb | 289 | if (IS_GEN4(dev_priv)) { |
d8b32247 DV |
290 | /* Bspec wording suggests that LVDS port dithering only exists |
291 | * for 18bpp panels. */ | |
d468e21e | 292 | if (pipe_config->dither && pipe_config->pipe_bpp == 18) |
fc683091 DV |
293 | temp |= LVDS_ENABLE_DITHER; |
294 | else | |
295 | temp &= ~LVDS_ENABLE_DITHER; | |
296 | } | |
297 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 298 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 299 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 300 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
301 | temp |= LVDS_VSYNC_POLARITY; |
302 | ||
303 | I915_WRITE(lvds_encoder->reg, temp); | |
304 | } | |
305 | ||
79e53945 JB |
306 | /** |
307 | * Sets the power state for the panel. | |
308 | */ | |
fd6bbda9 ML |
309 | static void intel_enable_lvds(struct intel_encoder *encoder, |
310 | struct intel_crtc_state *pipe_config, | |
311 | struct drm_connector_state *conn_state) | |
79e53945 | 312 | { |
c22834ec | 313 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 314 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
315 | struct intel_connector *intel_connector = |
316 | &lvds_encoder->attached_connector->base; | |
fac5e23e | 317 | struct drm_i915_private *dev_priv = to_i915(dev); |
79e53945 | 318 | |
7dec0606 | 319 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 320 | |
5a162e22 | 321 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) | PANEL_POWER_ON); |
7dec0606 | 322 | POSTING_READ(lvds_encoder->reg); |
44cb734c | 323 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, PP_ON, 1000)) |
de842eff | 324 | DRM_ERROR("timed out waiting for panel to power on\n"); |
2a1292fd | 325 | |
752aa88a | 326 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
327 | } |
328 | ||
fd6bbda9 ML |
329 | static void intel_disable_lvds(struct intel_encoder *encoder, |
330 | struct intel_crtc_state *old_crtc_state, | |
331 | struct drm_connector_state *old_conn_state) | |
2a1292fd | 332 | { |
29b99b48 | 333 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
d468e21e | 334 | struct drm_i915_private *dev_priv = to_i915(encoder->base.dev); |
2a1292fd | 335 | |
5a162e22 | 336 | I915_WRITE(PP_CONTROL(0), I915_READ(PP_CONTROL(0)) & ~PANEL_POWER_ON); |
44cb734c | 337 | if (intel_wait_for_register(dev_priv, PP_STATUS(0), PP_ON, 0, 1000)) |
de842eff | 338 | DRM_ERROR("timed out waiting for panel to power off\n"); |
2a1292fd | 339 | |
7dec0606 DV |
340 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
341 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
342 | } |
343 | ||
fd6bbda9 ML |
344 | static void gmch_disable_lvds(struct intel_encoder *encoder, |
345 | struct intel_crtc_state *old_crtc_state, | |
346 | struct drm_connector_state *old_conn_state) | |
347 | ||
d26a5b6e VS |
348 | { |
349 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
350 | struct intel_connector *intel_connector = | |
351 | &lvds_encoder->attached_connector->base; | |
352 | ||
353 | intel_panel_disable_backlight(intel_connector); | |
354 | ||
fd6bbda9 | 355 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); |
d26a5b6e VS |
356 | } |
357 | ||
fd6bbda9 ML |
358 | static void pch_disable_lvds(struct intel_encoder *encoder, |
359 | struct intel_crtc_state *old_crtc_state, | |
360 | struct drm_connector_state *old_conn_state) | |
d26a5b6e VS |
361 | { |
362 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
363 | struct intel_connector *intel_connector = | |
364 | &lvds_encoder->attached_connector->base; | |
365 | ||
366 | intel_panel_disable_backlight(intel_connector); | |
367 | } | |
368 | ||
fd6bbda9 ML |
369 | static void pch_post_disable_lvds(struct intel_encoder *encoder, |
370 | struct intel_crtc_state *old_crtc_state, | |
371 | struct drm_connector_state *old_conn_state) | |
d26a5b6e | 372 | { |
fd6bbda9 | 373 | intel_disable_lvds(encoder, old_crtc_state, old_conn_state); |
d26a5b6e VS |
374 | } |
375 | ||
c19de8eb DL |
376 | static enum drm_mode_status |
377 | intel_lvds_mode_valid(struct drm_connector *connector, | |
378 | struct drm_display_mode *mode) | |
79e53945 | 379 | { |
dd06f90e JN |
380 | struct intel_connector *intel_connector = to_intel_connector(connector); |
381 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
7f7b58cc | 382 | int max_pixclk = to_i915(connector->dev)->max_dotclk_freq; |
79e53945 | 383 | |
788319d4 CW |
384 | if (mode->hdisplay > fixed_mode->hdisplay) |
385 | return MODE_PANEL; | |
386 | if (mode->vdisplay > fixed_mode->vdisplay) | |
387 | return MODE_PANEL; | |
7f7b58cc MK |
388 | if (fixed_mode->clock > max_pixclk) |
389 | return MODE_CLOCK_HIGH; | |
79e53945 JB |
390 | |
391 | return MODE_OK; | |
392 | } | |
393 | ||
7ae89233 | 394 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
0a478c27 ML |
395 | struct intel_crtc_state *pipe_config, |
396 | struct drm_connector_state *conn_state) | |
79e53945 | 397 | { |
6e266956 | 398 | struct drm_i915_private *dev_priv = to_i915(intel_encoder->base.dev); |
7ae89233 DV |
399 | struct intel_lvds_encoder *lvds_encoder = |
400 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
401 | struct intel_connector *intel_connector = |
402 | &lvds_encoder->attached_connector->base; | |
2d112de7 | 403 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
d21bd67b | 404 | struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc); |
4e53c2e0 | 405 | unsigned int lvds_bpp; |
79e53945 JB |
406 | |
407 | /* Should never happen!! */ | |
6e266956 | 408 | if (INTEL_GEN(dev_priv) < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 409 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
410 | return false; |
411 | } | |
412 | ||
1f835a77 | 413 | if (lvds_encoder->a3_power == LVDS_A3_POWER_UP) |
4e53c2e0 DV |
414 | lvds_bpp = 8*3; |
415 | else | |
416 | lvds_bpp = 6*3; | |
417 | ||
e29c22c0 | 418 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
419 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
420 | pipe_config->pipe_bpp, lvds_bpp); | |
421 | pipe_config->pipe_bpp = lvds_bpp; | |
422 | } | |
d8b32247 | 423 | |
79e53945 | 424 | /* |
71677043 | 425 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
426 | * to the adjusted mode. The CRTC will be set up for this mode, |
427 | * with the panel scaling set up to source from the H/VDisplay | |
428 | * of the original mode. | |
429 | */ | |
4d891523 | 430 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 431 | adjusted_mode); |
1d8e1c75 | 432 | |
6e266956 | 433 | if (HAS_PCH_SPLIT(dev_priv)) { |
5bfe2ac0 DV |
434 | pipe_config->has_pch_encoder = true; |
435 | ||
b074cec8 JB |
436 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
437 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
438 | } else { |
439 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
440 | intel_connector->panel.fitting_mode); | |
79e53945 | 441 | |
21d8a475 | 442 | } |
f9bef081 | 443 | |
79e53945 JB |
444 | /* |
445 | * XXX: It would be nice to support lower refresh rates on the | |
446 | * panels to reduce power consumption, and perhaps match the | |
447 | * user's requested refresh rate. | |
448 | */ | |
449 | ||
450 | return true; | |
451 | } | |
452 | ||
79e53945 JB |
453 | /** |
454 | * Detect the LVDS connection. | |
455 | * | |
b42d4c5c JB |
456 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
457 | * connected and closed means disconnected. We also send hotplug events as | |
458 | * needed, using lid status notification from the input layer. | |
79e53945 | 459 | */ |
7b334fcb | 460 | static enum drm_connector_status |
930a9e28 | 461 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 462 | { |
7b9c5abe | 463 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 464 | enum drm_connector_status status; |
b42d4c5c | 465 | |
164c8598 | 466 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
c23cc417 | 467 | connector->base.id, connector->name); |
164c8598 | 468 | |
fe16d949 CW |
469 | status = intel_panel_detect(dev); |
470 | if (status != connector_status_unknown) | |
471 | return status; | |
01fe9dbd | 472 | |
6ee3b5a1 | 473 | return connector_status_connected; |
79e53945 JB |
474 | } |
475 | ||
476 | /** | |
477 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
478 | */ | |
479 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
480 | { | |
62165e0d | 481 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 482 | struct drm_device *dev = connector->dev; |
788319d4 | 483 | struct drm_display_mode *mode; |
79e53945 | 484 | |
9cd300e0 | 485 | /* use cached edid if we have one */ |
2aa4f099 | 486 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 487 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 488 | |
dd06f90e | 489 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 490 | if (mode == NULL) |
788319d4 | 491 | return 0; |
79e53945 | 492 | |
788319d4 CW |
493 | drm_mode_probed_add(connector, mode); |
494 | return 1; | |
79e53945 JB |
495 | } |
496 | ||
0544edfd TB |
497 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
498 | { | |
bc0daf48 | 499 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
500 | return 1; |
501 | } | |
502 | ||
503 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
504 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
505 | { | |
506 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
507 | .ident = "Toshiba Tecra A11", | |
508 | .matches = { | |
509 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
510 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
511 | }, | |
512 | }, | |
513 | ||
514 | { } /* terminating entry */ | |
515 | }; | |
516 | ||
c9354c85 | 517 | /* |
b8efb17b ZR |
518 | * Lid events. Note the use of 'modeset': |
519 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
520 | * and set it to MODESET_DONE on open | |
c9354c85 | 521 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
522 | * duplicate events where it was already properly set) |
523 | * - the suspend/resume paths will set it to | |
524 | * MODESET_SUSPENDED and ignore the lid open event, | |
525 | * because they restore the mode ("lid open"). | |
c9354c85 | 526 | */ |
c1c7af60 JB |
527 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
528 | void *unused) | |
529 | { | |
db1740a0 JN |
530 | struct intel_lvds_connector *lvds_connector = |
531 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
532 | struct drm_connector *connector = &lvds_connector->base.base; | |
533 | struct drm_device *dev = connector->dev; | |
fac5e23e | 534 | struct drm_i915_private *dev_priv = to_i915(dev); |
c1c7af60 | 535 | |
2fb4e61d AW |
536 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
537 | return NOTIFY_OK; | |
538 | ||
b8efb17b ZR |
539 | mutex_lock(&dev_priv->modeset_restore_lock); |
540 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
541 | goto exit; | |
a2565377 ZY |
542 | /* |
543 | * check and update the status of LVDS connector after receiving | |
544 | * the LID nofication event. | |
545 | */ | |
db1740a0 | 546 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 547 | |
0544edfd TB |
548 | /* Don't force modeset on machines where it causes a GPU lockup */ |
549 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 550 | goto exit; |
c9354c85 | 551 | if (!acpi_lid_open()) { |
b8efb17b ZR |
552 | /* do modeset on next lid open event */ |
553 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
554 | goto exit; | |
06891e27 | 555 | } |
c1c7af60 | 556 | |
b8efb17b ZR |
557 | if (dev_priv->modeset_restore == MODESET_DONE) |
558 | goto exit; | |
c9354c85 | 559 | |
5be19d91 DV |
560 | /* |
561 | * Some old platform's BIOS love to wreak havoc while the lid is closed. | |
562 | * We try to detect this here and undo any damage. The split for PCH | |
563 | * platforms is rather conservative and a bit arbitrary expect that on | |
564 | * those platforms VGA disabling requires actual legacy VGA I/O access, | |
565 | * and as part of the cleanup in the hw state restore we also redisable | |
566 | * the vga plane. | |
567 | */ | |
6e266956 | 568 | if (!HAS_PCH_SPLIT(dev_priv)) |
043e9bda | 569 | intel_display_resume(dev); |
06324194 | 570 | |
b8efb17b ZR |
571 | dev_priv->modeset_restore = MODESET_DONE; |
572 | ||
573 | exit: | |
574 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
575 | return NOTIFY_OK; |
576 | } | |
577 | ||
79e53945 JB |
578 | /** |
579 | * intel_lvds_destroy - unregister and free LVDS structures | |
580 | * @connector: connector to free | |
581 | * | |
582 | * Unregister the DDC bus for this connector then free the driver private | |
583 | * structure. | |
584 | */ | |
585 | static void intel_lvds_destroy(struct drm_connector *connector) | |
586 | { | |
db1740a0 JN |
587 | struct intel_lvds_connector *lvds_connector = |
588 | to_lvds_connector(connector); | |
79e53945 | 589 | |
db1740a0 JN |
590 | if (lvds_connector->lid_notifier.notifier_call) |
591 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 592 | |
9cd300e0 JN |
593 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
594 | kfree(lvds_connector->base.edid); | |
595 | ||
1d508706 | 596 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 597 | |
79e53945 JB |
598 | drm_connector_cleanup(connector); |
599 | kfree(connector); | |
600 | } | |
601 | ||
335041ed JB |
602 | static int intel_lvds_set_property(struct drm_connector *connector, |
603 | struct drm_property *property, | |
604 | uint64_t value) | |
605 | { | |
4d891523 | 606 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 607 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 608 | |
788319d4 | 609 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 610 | struct drm_crtc *crtc; |
bb8a3560 | 611 | |
53bd8389 JB |
612 | if (value == DRM_MODE_SCALE_NONE) { |
613 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 614 | return -EINVAL; |
3fbe18d6 | 615 | } |
788319d4 | 616 | |
4d891523 | 617 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
618 | /* the LVDS scaling property is not changed */ |
619 | return 0; | |
620 | } | |
4d891523 | 621 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
622 | |
623 | crtc = intel_attached_encoder(connector)->base.crtc; | |
83d65738 | 624 | if (crtc && crtc->state->enable) { |
3fbe18d6 ZY |
625 | /* |
626 | * If the CRTC is enabled, the display will be changed | |
627 | * according to the new panel fitting mode. | |
628 | */ | |
c0c36b94 | 629 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
630 | } |
631 | } | |
632 | ||
335041ed JB |
633 | return 0; |
634 | } | |
635 | ||
79e53945 JB |
636 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
637 | .get_modes = intel_lvds_get_modes, | |
638 | .mode_valid = intel_lvds_mode_valid, | |
79e53945 JB |
639 | }; |
640 | ||
641 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
4d688a2a | 642 | .dpms = drm_atomic_helper_connector_dpms, |
79e53945 JB |
643 | .detect = intel_lvds_detect, |
644 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 645 | .set_property = intel_lvds_set_property, |
2545e4a6 | 646 | .atomic_get_property = intel_connector_atomic_get_property, |
1ebaa0b9 | 647 | .late_register = intel_connector_register, |
c191eca1 | 648 | .early_unregister = intel_connector_unregister, |
79e53945 | 649 | .destroy = intel_lvds_destroy, |
c6f95f27 | 650 | .atomic_destroy_state = drm_atomic_helper_connector_destroy_state, |
98969725 | 651 | .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state, |
79e53945 JB |
652 | }; |
653 | ||
79e53945 | 654 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 655 | .destroy = intel_encoder_destroy, |
79e53945 JB |
656 | }; |
657 | ||
bbe1c274 | 658 | static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
425d244c | 659 | { |
bc0daf48 | 660 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
661 | return 1; |
662 | } | |
79e53945 | 663 | |
425d244c | 664 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 665 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
666 | { |
667 | .callback = intel_no_lvds_dmi_callback, | |
668 | .ident = "Apple Mac Mini (Core series)", | |
669 | .matches = { | |
98acd46f | 670 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
671 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
672 | }, | |
673 | }, | |
674 | { | |
675 | .callback = intel_no_lvds_dmi_callback, | |
676 | .ident = "Apple Mac Mini (Core 2 series)", | |
677 | .matches = { | |
98acd46f | 678 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
679 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
680 | }, | |
681 | }, | |
682 | { | |
683 | .callback = intel_no_lvds_dmi_callback, | |
684 | .ident = "MSI IM-945GSE-A", | |
685 | .matches = { | |
686 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
687 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
688 | }, | |
689 | }, | |
690 | { | |
691 | .callback = intel_no_lvds_dmi_callback, | |
692 | .ident = "Dell Studio Hybrid", | |
693 | .matches = { | |
694 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
695 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
696 | }, | |
697 | }, | |
70aa96ca JW |
698 | { |
699 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
700 | .ident = "Dell OptiPlex FX170", |
701 | .matches = { | |
702 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
703 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
704 | }, | |
705 | }, | |
706 | { | |
707 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
708 | .ident = "AOpen Mini PC", |
709 | .matches = { | |
710 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
711 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
712 | }, | |
713 | }, | |
ed8c754b TV |
714 | { |
715 | .callback = intel_no_lvds_dmi_callback, | |
716 | .ident = "AOpen Mini PC MP915", | |
717 | .matches = { | |
718 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
719 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
720 | }, | |
721 | }, | |
22ab70d3 KP |
722 | { |
723 | .callback = intel_no_lvds_dmi_callback, | |
724 | .ident = "AOpen i915GMm-HFS", | |
725 | .matches = { | |
726 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
727 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
728 | }, | |
729 | }, | |
e57b6886 DV |
730 | { |
731 | .callback = intel_no_lvds_dmi_callback, | |
732 | .ident = "AOpen i45GMx-I", | |
733 | .matches = { | |
734 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
735 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
736 | }, | |
737 | }, | |
fa0864b2 MC |
738 | { |
739 | .callback = intel_no_lvds_dmi_callback, | |
740 | .ident = "Aopen i945GTt-VFA", | |
741 | .matches = { | |
742 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
743 | }, | |
744 | }, | |
9875557e SB |
745 | { |
746 | .callback = intel_no_lvds_dmi_callback, | |
747 | .ident = "Clientron U800", | |
748 | .matches = { | |
749 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
750 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
751 | }, | |
752 | }, | |
6a574b5b | 753 | { |
44306ab3 JS |
754 | .callback = intel_no_lvds_dmi_callback, |
755 | .ident = "Clientron E830", | |
756 | .matches = { | |
757 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
758 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
759 | }, | |
760 | }, | |
761 | { | |
6a574b5b HG |
762 | .callback = intel_no_lvds_dmi_callback, |
763 | .ident = "Asus EeeBox PC EB1007", | |
764 | .matches = { | |
765 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
766 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
767 | }, | |
768 | }, | |
0999bbe0 AJ |
769 | { |
770 | .callback = intel_no_lvds_dmi_callback, | |
771 | .ident = "Asus AT5NM10T-I", | |
772 | .matches = { | |
773 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
774 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
775 | }, | |
776 | }, | |
33471119 JBG |
777 | { |
778 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 779 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
780 | .matches = { |
781 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 782 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
783 | }, |
784 | }, | |
f5b8a7ed MG |
785 | { |
786 | .callback = intel_no_lvds_dmi_callback, | |
787 | .ident = "Hewlett-Packard t5745", | |
788 | .matches = { | |
789 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 790 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
791 | }, |
792 | }, | |
793 | { | |
794 | .callback = intel_no_lvds_dmi_callback, | |
795 | .ident = "Hewlett-Packard st5747", | |
796 | .matches = { | |
797 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 798 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
799 | }, |
800 | }, | |
97effadb AA |
801 | { |
802 | .callback = intel_no_lvds_dmi_callback, | |
803 | .ident = "MSI Wind Box DC500", | |
804 | .matches = { | |
805 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
806 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
807 | }, | |
808 | }, | |
a51d4ed0 CW |
809 | { |
810 | .callback = intel_no_lvds_dmi_callback, | |
811 | .ident = "Gigabyte GA-D525TUD", | |
812 | .matches = { | |
813 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
814 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
815 | }, | |
816 | }, | |
c31407a3 CW |
817 | { |
818 | .callback = intel_no_lvds_dmi_callback, | |
819 | .ident = "Supermicro X7SPA-H", | |
820 | .matches = { | |
821 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
822 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
823 | }, | |
824 | }, | |
9e9dd0e8 CL |
825 | { |
826 | .callback = intel_no_lvds_dmi_callback, | |
827 | .ident = "Fujitsu Esprimo Q900", | |
828 | .matches = { | |
829 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
830 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
831 | }, | |
832 | }, | |
645378d8 RP |
833 | { |
834 | .callback = intel_no_lvds_dmi_callback, | |
835 | .ident = "Intel D410PT", | |
836 | .matches = { | |
837 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
838 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
839 | }, | |
840 | }, | |
841 | { | |
842 | .callback = intel_no_lvds_dmi_callback, | |
843 | .ident = "Intel D425KT", | |
844 | .matches = { | |
845 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
846 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
847 | }, | |
848 | }, | |
e5614f0c CW |
849 | { |
850 | .callback = intel_no_lvds_dmi_callback, | |
851 | .ident = "Intel D510MO", | |
852 | .matches = { | |
853 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
854 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
855 | }, | |
856 | }, | |
dcf6d294 JN |
857 | { |
858 | .callback = intel_no_lvds_dmi_callback, | |
859 | .ident = "Intel D525MW", | |
860 | .matches = { | |
861 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
862 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
863 | }, | |
864 | }, | |
425d244c JW |
865 | |
866 | { } /* terminating entry */ | |
867 | }; | |
79e53945 | 868 | |
1974cad0 DV |
869 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
870 | { | |
871 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
872 | return 1; | |
873 | } | |
874 | ||
875 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
876 | { | |
877 | .callback = intel_dual_link_lvds_callback, | |
3916e3fd LW |
878 | .ident = "Apple MacBook Pro 15\" (2010)", |
879 | .matches = { | |
880 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
881 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"), | |
882 | }, | |
883 | }, | |
884 | { | |
885 | .callback = intel_dual_link_lvds_callback, | |
886 | .ident = "Apple MacBook Pro 15\" (2011)", | |
1974cad0 DV |
887 | .matches = { |
888 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
889 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
890 | }, | |
891 | }, | |
3916e3fd LW |
892 | { |
893 | .callback = intel_dual_link_lvds_callback, | |
894 | .ident = "Apple MacBook Pro 15\" (2012)", | |
895 | .matches = { | |
896 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
897 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"), | |
898 | }, | |
899 | }, | |
1974cad0 DV |
900 | { } /* terminating entry */ |
901 | }; | |
902 | ||
97a824e1 | 903 | struct intel_encoder *intel_get_lvds_encoder(struct drm_device *dev) |
13c7d870 | 904 | { |
97a824e1 | 905 | struct intel_encoder *intel_encoder; |
13c7d870 | 906 | |
97a824e1 ID |
907 | for_each_intel_encoder(dev, intel_encoder) |
908 | if (intel_encoder->type == INTEL_OUTPUT_LVDS) | |
909 | return intel_encoder; | |
13c7d870 | 910 | |
97a824e1 ID |
911 | return NULL; |
912 | } | |
913 | ||
914 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
915 | { | |
916 | struct intel_encoder *encoder = intel_get_lvds_encoder(dev); | |
13c7d870 | 917 | |
97a824e1 | 918 | return encoder && to_lvds_encoder(&encoder->base)->is_dual_link; |
13c7d870 DV |
919 | } |
920 | ||
7dec0606 | 921 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 922 | { |
7dec0606 | 923 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 | 924 | unsigned int val; |
fac5e23e | 925 | struct drm_i915_private *dev_priv = to_i915(dev); |
1974cad0 DV |
926 | |
927 | /* use the module option value if specified */ | |
d330a953 JN |
928 | if (i915.lvds_channel_mode > 0) |
929 | return i915.lvds_channel_mode == 2; | |
1974cad0 | 930 | |
6f317cfe LW |
931 | /* single channel LVDS is limited to 112 MHz */ |
932 | if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock | |
933 | > 112999) | |
934 | return true; | |
935 | ||
1974cad0 DV |
936 | if (dmi_check_system(intel_dual_link_lvds)) |
937 | return true; | |
938 | ||
13c7d870 DV |
939 | /* BIOS should set the proper LVDS register value at boot, but |
940 | * in reality, it doesn't set the value when the lid is closed; | |
941 | * we need to check "the value to be set" in VBT when LVDS | |
942 | * register is uninitialized. | |
943 | */ | |
7dec0606 | 944 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 945 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 946 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 947 | |
1974cad0 DV |
948 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
949 | } | |
950 | ||
50a0bc90 | 951 | static bool intel_lvds_supported(struct drm_i915_private *dev_priv) |
f3cfcba6 CW |
952 | { |
953 | /* With the introduction of the PCH we gained a dedicated | |
954 | * LVDS presence pin, use it. */ | |
6e266956 | 955 | if (HAS_PCH_IBX(dev_priv) || HAS_PCH_CPT(dev_priv)) |
f3cfcba6 CW |
956 | return true; |
957 | ||
958 | /* Otherwise LVDS was only attached to mobile products, | |
959 | * except for the inglorious 830gm */ | |
50a0bc90 TU |
960 | if (INTEL_GEN(dev_priv) <= 4 && |
961 | IS_MOBILE(dev_priv) && !IS_I830(dev_priv)) | |
311e359c PZ |
962 | return true; |
963 | ||
964 | return false; | |
f3cfcba6 CW |
965 | } |
966 | ||
79e53945 JB |
967 | /** |
968 | * intel_lvds_init - setup LVDS connectors on this device | |
969 | * @dev: drm device | |
970 | * | |
971 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
972 | * modes we can display on the LVDS panel (if present). | |
973 | */ | |
c9093354 | 974 | void intel_lvds_init(struct drm_device *dev) |
79e53945 | 975 | { |
fac5e23e | 976 | struct drm_i915_private *dev_priv = to_i915(dev); |
29b99b48 | 977 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 978 | struct intel_encoder *intel_encoder; |
c7362c4d | 979 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 980 | struct intel_connector *intel_connector; |
79e53945 JB |
981 | struct drm_connector *connector; |
982 | struct drm_encoder *encoder; | |
983 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 984 | struct drm_display_mode *fixed_mode = NULL; |
4b6ed685 | 985 | struct drm_display_mode *downclock_mode = NULL; |
9cd300e0 | 986 | struct edid *edid; |
e2af48c6 | 987 | struct intel_crtc *crtc; |
f0f59a00 | 988 | i915_reg_t lvds_reg; |
79e53945 | 989 | u32 lvds; |
270eea0f CW |
990 | int pipe; |
991 | u8 pin; | |
79e53945 | 992 | |
50a0bc90 | 993 | if (!intel_lvds_supported(dev_priv)) |
c9093354 | 994 | return; |
f3cfcba6 | 995 | |
425d244c JW |
996 | /* Skip init on machines we know falsely report LVDS */ |
997 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 998 | return; |
565dcd46 | 999 | |
6e266956 | 1000 | if (HAS_PCH_SPLIT(dev_priv)) |
d0669d00 VS |
1001 | lvds_reg = PCH_LVDS; |
1002 | else | |
1003 | lvds_reg = LVDS; | |
1004 | ||
1005 | lvds = I915_READ(lvds_reg); | |
1006 | ||
6e266956 | 1007 | if (HAS_PCH_SPLIT(dev_priv)) { |
d0669d00 | 1008 | if ((lvds & LVDS_DETECTED) == 0) |
c9093354 | 1009 | return; |
6aa23e65 | 1010 | if (dev_priv->vbt.edp.support) { |
28c97730 | 1011 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 1012 | return; |
32f9d658 | 1013 | } |
541998a1 ZW |
1014 | } |
1015 | ||
eebaed64 | 1016 | pin = GMBUS_PIN_PANEL; |
5a69d13d | 1017 | if (!intel_bios_is_lvds_present(dev_priv, &pin)) { |
d0669d00 | 1018 | if ((lvds & LVDS_PORT_EN) == 0) { |
eebaed64 CW |
1019 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
1020 | return; | |
1021 | } | |
1022 | DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n"); | |
1023 | } | |
1024 | ||
b14c5679 | 1025 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 1026 | if (!lvds_encoder) |
c9093354 | 1027 | return; |
79e53945 | 1028 | |
b14c5679 | 1029 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 1030 | if (!lvds_connector) { |
29b99b48 | 1031 | kfree(lvds_encoder); |
c9093354 | 1032 | return; |
bb8a3560 ZW |
1033 | } |
1034 | ||
9bdbd0b9 ACO |
1035 | if (intel_connector_init(&lvds_connector->base) < 0) { |
1036 | kfree(lvds_connector); | |
1037 | kfree(lvds_encoder); | |
1038 | return; | |
1039 | } | |
1040 | ||
62165e0d JN |
1041 | lvds_encoder->attached_connector = lvds_connector; |
1042 | ||
29b99b48 | 1043 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 1044 | encoder = &intel_encoder->base; |
c7362c4d | 1045 | intel_connector = &lvds_connector->base; |
ea5b213a | 1046 | connector = &intel_connector->base; |
bb8a3560 | 1047 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
1048 | DRM_MODE_CONNECTOR_LVDS); |
1049 | ||
4ef69c7a | 1050 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
580d8ed5 | 1051 | DRM_MODE_ENCODER_LVDS, "LVDS"); |
79e53945 | 1052 | |
c22834ec | 1053 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 1054 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 1055 | intel_encoder->compute_config = intel_lvds_compute_config; |
d26a5b6e VS |
1056 | if (HAS_PCH_SPLIT(dev_priv)) { |
1057 | intel_encoder->disable = pch_disable_lvds; | |
1058 | intel_encoder->post_disable = pch_post_disable_lvds; | |
1059 | } else { | |
1060 | intel_encoder->disable = gmch_disable_lvds; | |
1061 | } | |
b1dc332c | 1062 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 1063 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 1064 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
c22834ec | 1065 | |
df0e9248 | 1066 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
79e53945 | 1067 | |
03cdc1d4 PD |
1068 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
1069 | intel_encoder->port = PORT_NONE; | |
bc079e8b | 1070 | intel_encoder->cloneable = 0; |
6e266956 | 1071 | if (HAS_PCH_SPLIT(dev_priv)) |
27f8227b | 1072 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); |
5db94019 | 1073 | else if (IS_GEN4(dev_priv)) |
0b9f43a0 | 1074 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); |
27f8227b JB |
1075 | else |
1076 | intel_encoder->crtc_mask = (1 << 1); | |
1077 | ||
79e53945 JB |
1078 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1079 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1080 | connector->interlace_allowed = false; | |
1081 | connector->doublescan_allowed = false; | |
1082 | ||
d0669d00 | 1083 | lvds_encoder->reg = lvds_reg; |
7dec0606 | 1084 | |
3fbe18d6 ZY |
1085 | /* create the scaling mode property */ |
1086 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1087 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1088 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1089 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1090 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
ed6143b8 ID |
1091 | |
1092 | intel_lvds_pps_get_hw_state(dev_priv, &lvds_encoder->init_pps); | |
1093 | lvds_encoder->init_lvds_val = lvds; | |
1094 | ||
79e53945 JB |
1095 | /* |
1096 | * LVDS discovery: | |
1097 | * 1) check for EDID on DDC | |
1098 | * 2) check for VBT data | |
1099 | * 3) check to see if LVDS is already on | |
1100 | * if none of the above, no panel | |
1101 | * 4) make sure lid is open | |
1102 | * if closed, act like it's not there for now | |
1103 | */ | |
1104 | ||
79e53945 JB |
1105 | /* |
1106 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1107 | * preferred mode is the right one. | |
1108 | */ | |
4da98541 | 1109 | mutex_lock(&dev->mode_config.mutex); |
4eddaeec LW |
1110 | if (vga_switcheroo_handler_flags() & VGA_SWITCHEROO_CAN_SWITCH_DDC) |
1111 | edid = drm_get_edid_switcheroo(connector, | |
1112 | intel_gmbus_get_adapter(dev_priv, pin)); | |
1113 | else | |
1114 | edid = drm_get_edid(connector, | |
1115 | intel_gmbus_get_adapter(dev_priv, pin)); | |
9cd300e0 JN |
1116 | if (edid) { |
1117 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1118 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1119 | edid); |
3f8ff0e7 | 1120 | } else { |
9cd300e0 JN |
1121 | kfree(edid); |
1122 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1123 | } |
9cd300e0 JN |
1124 | } else { |
1125 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1126 | } |
9cd300e0 JN |
1127 | lvds_connector->base.edid = edid; |
1128 | ||
79e53945 | 1129 | list_for_each_entry(scan, &connector->probed_modes, head) { |
79e53945 | 1130 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1131 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1132 | drm_mode_debug_printmodeline(scan); | |
1133 | ||
dd06f90e | 1134 | fixed_mode = drm_mode_duplicate(dev, scan); |
c329a4ec | 1135 | if (fixed_mode) |
6a9d51b7 | 1136 | goto out; |
79e53945 | 1137 | } |
79e53945 JB |
1138 | } |
1139 | ||
1140 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1141 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1142 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1143 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1144 | |
41aa3448 | 1145 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1146 | if (fixed_mode) { |
1147 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
df457245 VS |
1148 | connector->display_info.width_mm = fixed_mode->width_mm; |
1149 | connector->display_info.height_mm = fixed_mode->height_mm; | |
e285f3cd JB |
1150 | goto out; |
1151 | } | |
79e53945 JB |
1152 | } |
1153 | ||
1154 | /* | |
1155 | * If we didn't get EDID, try checking if the panel is already turned | |
1156 | * on. If so, assume that whatever is currently programmed is the | |
1157 | * correct mode. | |
1158 | */ | |
541998a1 | 1159 | |
f2b115e6 | 1160 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
6e266956 | 1161 | if (HAS_PCH_SPLIT(dev_priv)) |
541998a1 ZW |
1162 | goto failed; |
1163 | ||
79e53945 | 1164 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; |
b91eb5cc | 1165 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
79e53945 JB |
1166 | |
1167 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
e2af48c6 | 1168 | fixed_mode = intel_crtc_mode_get(dev, &crtc->base); |
dd06f90e | 1169 | if (fixed_mode) { |
6a9d51b7 CW |
1170 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1171 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1172 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1173 | goto out; |
79e53945 JB |
1174 | } |
1175 | } | |
1176 | ||
1177 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1178 | if (!fixed_mode) |
79e53945 JB |
1179 | goto failed; |
1180 | ||
79e53945 | 1181 | out: |
4da98541 DV |
1182 | mutex_unlock(&dev->mode_config.mutex); |
1183 | ||
6f317cfe | 1184 | intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode); |
fda9ee98 | 1185 | intel_panel_setup_backlight(connector, INVALID_PIPE); |
6f317cfe | 1186 | |
7dec0606 | 1187 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1188 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1189 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1190 | ||
af9b9c19 | 1191 | lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK; |
1f835a77 | 1192 | |
db1740a0 JN |
1193 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1194 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1195 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1196 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1197 | } |
aaa6fd2a | 1198 | |
c9093354 | 1199 | return; |
79e53945 JB |
1200 | |
1201 | failed: | |
4da98541 DV |
1202 | mutex_unlock(&dev->mode_config.mutex); |
1203 | ||
8a4c47f3 | 1204 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1205 | drm_connector_cleanup(connector); |
1991bdfa | 1206 | drm_encoder_cleanup(encoder); |
29b99b48 | 1207 | kfree(lvds_encoder); |
c7362c4d | 1208 | kfree(lvds_connector); |
c9093354 | 1209 | return; |
79e53945 | 1210 | } |