]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_lvds.c
drm/i915: use staged outuput config in tv->mode_fixup
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
79e53945
JB
34#include "drmP.h"
35#include "drm.h"
36#include "drm_crtc.h"
37#include "drm_edid.h"
38#include "intel_drv.h"
39#include "i915_drm.h"
40#include "i915_drv.h"
e99da35f 41#include <linux/acpi.h>
79e53945 42
3fbe18d6 43/* Private structure for the integrated LVDS support */
ea5b213a
CW
44struct intel_lvds {
45 struct intel_encoder base;
788319d4 46
219adae1 47 struct edid *edid;
788319d4 48
3fbe18d6
ZY
49 int fitting_mode;
50 u32 pfit_control;
51 u32 pfit_pgm_ratios;
e9e331a8 52 bool pfit_dirty;
788319d4
CW
53
54 struct drm_display_mode *fixed_mode;
3fbe18d6
ZY
55};
56
788319d4 57static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder)
ea5b213a 58{
4ef69c7a 59 return container_of(encoder, struct intel_lvds, base.base);
ea5b213a
CW
60}
61
788319d4
CW
62static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector)
63{
64 return container_of(intel_attached_encoder(connector),
65 struct intel_lvds, base);
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
73 u32 lvds_reg, tmp;
74
75 if (HAS_PCH_SPLIT(dev)) {
76 lvds_reg = PCH_LVDS;
77 } else {
78 lvds_reg = LVDS;
79 }
80
81 tmp = I915_READ(lvds_reg);
82
83 if (!(tmp & LVDS_PORT_EN))
84 return false;
85
86 if (HAS_PCH_CPT(dev))
87 *pipe = PORT_TO_PIPE_CPT(tmp);
88 else
89 *pipe = PORT_TO_PIPE(tmp);
90
91 return true;
92}
93
79e53945
JB
94/**
95 * Sets the power state for the panel.
96 */
c22834ec 97static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 98{
c22834ec
DV
99 struct drm_device *dev = encoder->base.dev;
100 struct intel_lvds *intel_lvds = to_intel_lvds(&encoder->base);
101 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 102 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 103 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 104
c619eed4 105 if (HAS_PCH_SPLIT(dev)) {
541998a1 106 ctl_reg = PCH_PP_CONTROL;
469d1296 107 lvds_reg = PCH_LVDS;
de842eff 108 stat_reg = PCH_PP_STATUS;
541998a1
ZW
109 } else {
110 ctl_reg = PP_CONTROL;
469d1296 111 lvds_reg = LVDS;
de842eff 112 stat_reg = PP_STATUS;
541998a1 113 }
79e53945 114
2a1292fd 115 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 116
2a1292fd
CW
117 if (intel_lvds->pfit_dirty) {
118 /*
119 * Enable automatic panel scaling so that non-native modes
120 * fill the screen. The panel fitter should only be
121 * adjusted whilst the pipe is disabled, according to
122 * register description and PRM.
123 */
124 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
125 intel_lvds->pfit_control,
126 intel_lvds->pfit_pgm_ratios);
de842eff
KP
127
128 I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios);
129 I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control);
130 intel_lvds->pfit_dirty = false;
2a1292fd
CW
131 }
132
133 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
134 POSTING_READ(lvds_reg);
de842eff
KP
135 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
136 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 137
24ded204 138 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
139}
140
c22834ec 141static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 142{
c22834ec
DV
143 struct drm_device *dev = encoder->base.dev;
144 struct intel_lvds *intel_lvds = to_intel_lvds(&encoder->base);
2a1292fd 145 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 146 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
147
148 if (HAS_PCH_SPLIT(dev)) {
149 ctl_reg = PCH_PP_CONTROL;
150 lvds_reg = PCH_LVDS;
de842eff 151 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
152 } else {
153 ctl_reg = PP_CONTROL;
154 lvds_reg = LVDS;
de842eff 155 stat_reg = PP_STATUS;
2a1292fd
CW
156 }
157
47356eb6 158 intel_panel_disable_backlight(dev);
2a1292fd
CW
159
160 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
161 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
162 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd
CW
163
164 if (intel_lvds->pfit_control) {
2a1292fd
CW
165 I915_WRITE(PFIT_CONTROL, 0);
166 intel_lvds->pfit_dirty = true;
79e53945 167 }
2a1292fd
CW
168
169 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 170 POSTING_READ(lvds_reg);
79e53945
JB
171}
172
79e53945
JB
173static int intel_lvds_mode_valid(struct drm_connector *connector,
174 struct drm_display_mode *mode)
175{
788319d4
CW
176 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
177 struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode;
79e53945 178
788319d4
CW
179 if (mode->hdisplay > fixed_mode->hdisplay)
180 return MODE_PANEL;
181 if (mode->vdisplay > fixed_mode->vdisplay)
182 return MODE_PANEL;
79e53945
JB
183
184 return MODE_OK;
185}
186
49be663f
CW
187static void
188centre_horizontally(struct drm_display_mode *mode,
189 int width)
190{
191 u32 border, sync_pos, blank_width, sync_width;
192
193 /* keep the hsync and hblank widths constant */
194 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
195 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
196 sync_pos = (blank_width - sync_width + 1) / 2;
197
198 border = (mode->hdisplay - width + 1) / 2;
199 border += border & 1; /* make the border even */
200
201 mode->crtc_hdisplay = width;
202 mode->crtc_hblank_start = width + border;
203 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
204
205 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
206 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
207
208 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
209}
210
211static void
212centre_vertically(struct drm_display_mode *mode,
213 int height)
214{
215 u32 border, sync_pos, blank_width, sync_width;
216
217 /* keep the vsync and vblank widths constant */
218 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
219 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
220 sync_pos = (blank_width - sync_width + 1) / 2;
221
222 border = (mode->vdisplay - height + 1) / 2;
223
224 mode->crtc_vdisplay = height;
225 mode->crtc_vblank_start = height + border;
226 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
227
228 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
229 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
230
231 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
232}
233
234static inline u32 panel_fitter_scaling(u32 source, u32 target)
235{
236 /*
237 * Floating point operation is not supported. So the FACTOR
238 * is defined, which can avoid the floating point computation
239 * when calculating the panel ratio.
240 */
241#define ACCURACY 12
242#define FACTOR (1 << ACCURACY)
243 u32 ratio = source * FACTOR / target;
244 return (FACTOR * ratio + FACTOR/2) / FACTOR;
245}
246
79e53945 247static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 248 const struct drm_display_mode *mode,
79e53945
JB
249 struct drm_display_mode *adjusted_mode)
250{
251 struct drm_device *dev = encoder->dev;
252 struct drm_i915_private *dev_priv = dev->dev_private;
253 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
788319d4 254 struct intel_lvds *intel_lvds = to_intel_lvds(encoder);
6c2b7c12 255 struct intel_encoder *tmp_encoder;
49be663f 256 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 257 int pipe;
79e53945
JB
258
259 /* Should never happen!! */
a6c45cf0 260 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 261 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
262 return false;
263 }
264
265 /* Should never happen!! */
6c2b7c12
DV
266 for_each_encoder_on_crtc(dev, encoder->crtc, tmp_encoder) {
267 if (&tmp_encoder->base != encoder) {
1ae8c0a5 268 DRM_ERROR("Can't enable LVDS and another "
79e53945
JB
269 "encoder on the same pipe\n");
270 return false;
271 }
272 }
1d8e1c75 273
79e53945 274 /*
71677043 275 * We have timings from the BIOS for the panel, put them in
79e53945
JB
276 * to the adjusted mode. The CRTC will be set up for this mode,
277 * with the panel scaling set up to source from the H/VDisplay
278 * of the original mode.
279 */
788319d4 280 intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode);
1d8e1c75
CW
281
282 if (HAS_PCH_SPLIT(dev)) {
283 intel_pch_panel_fitting(dev, intel_lvds->fitting_mode,
284 mode, adjusted_mode);
285 return true;
286 }
79e53945 287
3fbe18d6
ZY
288 /* Native modes don't need fitting */
289 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 290 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 291 goto out;
3fbe18d6
ZY
292
293 /* 965+ wants fuzzy fitting */
a6c45cf0 294 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
295 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
296 PFIT_FILTER_FUZZY);
297
3fbe18d6
ZY
298 /*
299 * Enable automatic panel scaling for non-native modes so that they fill
300 * the screen. Should be enabled before the pipe is enabled, according
301 * to register description and PRM.
302 * Change the value here to see the borders for debugging
303 */
9db4a9c7
JB
304 for_each_pipe(pipe)
305 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 306
f9bef081
DV
307 drm_mode_set_crtcinfo(adjusted_mode, 0);
308
ea5b213a 309 switch (intel_lvds->fitting_mode) {
53bd8389 310 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
311 /*
312 * For centered modes, we have to calculate border widths &
313 * heights and modify the values programmed into the CRTC.
314 */
49be663f
CW
315 centre_horizontally(adjusted_mode, mode->hdisplay);
316 centre_vertically(adjusted_mode, mode->vdisplay);
317 border = LVDS_BORDER_ENABLE;
3fbe18d6 318 break;
49be663f 319
3fbe18d6 320 case DRM_MODE_SCALE_ASPECT:
49be663f 321 /* Scale but preserve the aspect ratio */
a6c45cf0 322 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
323 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
324 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
325
3fbe18d6 326 /* 965+ is easy, it does everything in hw */
49be663f 327 if (scaled_width > scaled_height)
257e48f1 328 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 329 else if (scaled_width < scaled_height)
257e48f1
CW
330 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
331 else if (adjusted_mode->hdisplay != mode->hdisplay)
332 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 333 } else {
49be663f
CW
334 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
335 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
336 /*
337 * For earlier chips we have to calculate the scaling
338 * ratio by hand and program it into the
339 * PFIT_PGM_RATIO register
340 */
49be663f
CW
341 if (scaled_width > scaled_height) { /* pillar */
342 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
343
344 border = LVDS_BORDER_ENABLE;
345 if (mode->vdisplay != adjusted_mode->vdisplay) {
346 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
347 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
348 bits << PFIT_VERT_SCALE_SHIFT);
349 pfit_control |= (PFIT_ENABLE |
350 VERT_INTERP_BILINEAR |
351 HORIZ_INTERP_BILINEAR);
352 }
353 } else if (scaled_width < scaled_height) { /* letter */
354 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
355
356 border = LVDS_BORDER_ENABLE;
357 if (mode->hdisplay != adjusted_mode->hdisplay) {
358 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
359 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
360 bits << PFIT_VERT_SCALE_SHIFT);
361 pfit_control |= (PFIT_ENABLE |
362 VERT_INTERP_BILINEAR |
363 HORIZ_INTERP_BILINEAR);
364 }
365 } else
366 /* Aspects match, Let hw scale both directions */
367 pfit_control |= (PFIT_ENABLE |
368 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
369 VERT_INTERP_BILINEAR |
370 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
371 }
372 break;
373
374 case DRM_MODE_SCALE_FULLSCREEN:
375 /*
376 * Full scaling, even if it changes the aspect ratio.
377 * Fortunately this is all done for us in hw.
378 */
257e48f1
CW
379 if (mode->vdisplay != adjusted_mode->vdisplay ||
380 mode->hdisplay != adjusted_mode->hdisplay) {
381 pfit_control |= PFIT_ENABLE;
382 if (INTEL_INFO(dev)->gen >= 4)
383 pfit_control |= PFIT_SCALING_AUTO;
384 else
385 pfit_control |= (VERT_AUTO_SCALE |
386 VERT_INTERP_BILINEAR |
387 HORIZ_AUTO_SCALE |
388 HORIZ_INTERP_BILINEAR);
389 }
3fbe18d6 390 break;
49be663f 391
3fbe18d6
ZY
392 default:
393 break;
394 }
395
396out:
72389a33 397 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
398 if ((pfit_control & PFIT_ENABLE) == 0) {
399 pfit_control = 0;
400 pfit_pgm_ratios = 0;
401 }
72389a33
CW
402
403 /* Make sure pre-965 set dither correctly */
404 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
405 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
406
e9e331a8
CW
407 if (pfit_control != intel_lvds->pfit_control ||
408 pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) {
409 intel_lvds->pfit_control = pfit_control;
410 intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios;
411 intel_lvds->pfit_dirty = true;
412 }
49be663f
CW
413 dev_priv->lvds_border_bits = border;
414
79e53945
JB
415 /*
416 * XXX: It would be nice to support lower refresh rates on the
417 * panels to reduce power consumption, and perhaps match the
418 * user's requested refresh rate.
419 */
420
421 return true;
422}
423
79e53945
JB
424static void intel_lvds_mode_set(struct drm_encoder *encoder,
425 struct drm_display_mode *mode,
426 struct drm_display_mode *adjusted_mode)
427{
79e53945
JB
428 /*
429 * The LVDS pin pair will already have been turned on in the
430 * intel_crtc_mode_set since it has a large impact on the DPLL
431 * settings.
432 */
79e53945
JB
433}
434
435/**
436 * Detect the LVDS connection.
437 *
b42d4c5c
JB
438 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
439 * connected and closed means disconnected. We also send hotplug events as
440 * needed, using lid status notification from the input layer.
79e53945 441 */
7b334fcb 442static enum drm_connector_status
930a9e28 443intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 444{
7b9c5abe 445 struct drm_device *dev = connector->dev;
6ee3b5a1 446 enum drm_connector_status status;
b42d4c5c 447
fe16d949
CW
448 status = intel_panel_detect(dev);
449 if (status != connector_status_unknown)
450 return status;
01fe9dbd 451
6ee3b5a1 452 return connector_status_connected;
79e53945
JB
453}
454
455/**
456 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
457 */
458static int intel_lvds_get_modes(struct drm_connector *connector)
459{
788319d4 460 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
79e53945 461 struct drm_device *dev = connector->dev;
788319d4 462 struct drm_display_mode *mode;
79e53945 463
3f8ff0e7 464 if (intel_lvds->edid)
219adae1 465 return drm_add_edid_modes(connector, intel_lvds->edid);
79e53945 466
788319d4 467 mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode);
311bd68e 468 if (mode == NULL)
788319d4 469 return 0;
79e53945 470
788319d4
CW
471 drm_mode_probed_add(connector, mode);
472 return 1;
79e53945
JB
473}
474
0544edfd
TB
475static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
476{
bc0daf48 477 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
478 return 1;
479}
480
481/* The GPU hangs up on these systems if modeset is performed on LID open */
482static const struct dmi_system_id intel_no_modeset_on_lid[] = {
483 {
484 .callback = intel_no_modeset_on_lid_dmi_callback,
485 .ident = "Toshiba Tecra A11",
486 .matches = {
487 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
488 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
489 },
490 },
491
492 { } /* terminating entry */
493};
494
c9354c85
LT
495/*
496 * Lid events. Note the use of 'modeset_on_lid':
497 * - we set it on lid close, and reset it on open
498 * - we use it as a "only once" bit (ie we ignore
499 * duplicate events where it was already properly
500 * set/reset)
501 * - the suspend/resume paths will also set it to
502 * zero, since they restore the mode ("lid open").
503 */
c1c7af60
JB
504static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
505 void *unused)
506{
507 struct drm_i915_private *dev_priv =
508 container_of(nb, struct drm_i915_private, lid_notifier);
509 struct drm_device *dev = dev_priv->dev;
a2565377 510 struct drm_connector *connector = dev_priv->int_lvds_connector;
c1c7af60 511
2fb4e61d
AW
512 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
513 return NOTIFY_OK;
514
a2565377
ZY
515 /*
516 * check and update the status of LVDS connector after receiving
517 * the LID nofication event.
518 */
519 if (connector)
7b334fcb 520 connector->status = connector->funcs->detect(connector,
930a9e28 521 false);
7b334fcb 522
0544edfd
TB
523 /* Don't force modeset on machines where it causes a GPU lockup */
524 if (dmi_check_system(intel_no_modeset_on_lid))
525 return NOTIFY_OK;
c9354c85
LT
526 if (!acpi_lid_open()) {
527 dev_priv->modeset_on_lid = 1;
528 return NOTIFY_OK;
06891e27 529 }
c1c7af60 530
c9354c85
LT
531 if (!dev_priv->modeset_on_lid)
532 return NOTIFY_OK;
533
534 dev_priv->modeset_on_lid = 0;
535
536 mutex_lock(&dev->mode_config.mutex);
537 drm_helper_resume_force_mode(dev);
538 mutex_unlock(&dev->mode_config.mutex);
06324194 539
c1c7af60
JB
540 return NOTIFY_OK;
541}
542
79e53945
JB
543/**
544 * intel_lvds_destroy - unregister and free LVDS structures
545 * @connector: connector to free
546 *
547 * Unregister the DDC bus for this connector then free the driver private
548 * structure.
549 */
550static void intel_lvds_destroy(struct drm_connector *connector)
551{
c1c7af60 552 struct drm_device *dev = connector->dev;
c1c7af60 553 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945 554
aaa6fd2a
MG
555 intel_panel_destroy_backlight(dev);
556
c1c7af60
JB
557 if (dev_priv->lid_notifier.notifier_call)
558 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
559 drm_sysfs_connector_remove(connector);
560 drm_connector_cleanup(connector);
561 kfree(connector);
562}
563
335041ed
JB
564static int intel_lvds_set_property(struct drm_connector *connector,
565 struct drm_property *property,
566 uint64_t value)
567{
788319d4 568 struct intel_lvds *intel_lvds = intel_attached_lvds(connector);
3fbe18d6 569 struct drm_device *dev = connector->dev;
3fbe18d6 570
788319d4
CW
571 if (property == dev->mode_config.scaling_mode_property) {
572 struct drm_crtc *crtc = intel_lvds->base.base.crtc;
bb8a3560 573
53bd8389
JB
574 if (value == DRM_MODE_SCALE_NONE) {
575 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 576 return -EINVAL;
3fbe18d6 577 }
788319d4 578
ea5b213a 579 if (intel_lvds->fitting_mode == value) {
3fbe18d6
ZY
580 /* the LVDS scaling property is not changed */
581 return 0;
582 }
ea5b213a 583 intel_lvds->fitting_mode = value;
3fbe18d6
ZY
584 if (crtc && crtc->enabled) {
585 /*
586 * If the CRTC is enabled, the display will be changed
587 * according to the new panel fitting mode.
588 */
a6778b3c
DV
589 intel_set_mode(crtc, &crtc->mode,
590 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
591 }
592 }
593
335041ed
JB
594 return 0;
595}
596
79e53945 597static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 598 .mode_fixup = intel_lvds_mode_fixup,
79e53945 599 .mode_set = intel_lvds_mode_set,
c22834ec 600 .disable = intel_encoder_disable,
79e53945
JB
601};
602
603static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
604 .get_modes = intel_lvds_get_modes,
605 .mode_valid = intel_lvds_mode_valid,
df0e9248 606 .best_encoder = intel_best_encoder,
79e53945
JB
607};
608
609static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 610 .dpms = intel_connector_dpms,
79e53945
JB
611 .detect = intel_lvds_detect,
612 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 613 .set_property = intel_lvds_set_property,
79e53945
JB
614 .destroy = intel_lvds_destroy,
615};
616
79e53945 617static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 618 .destroy = intel_encoder_destroy,
79e53945
JB
619};
620
425d244c
JW
621static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
622{
bc0daf48 623 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
624 return 1;
625}
79e53945 626
425d244c 627/* These systems claim to have LVDS, but really don't */
93c05f22 628static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
629 {
630 .callback = intel_no_lvds_dmi_callback,
631 .ident = "Apple Mac Mini (Core series)",
632 .matches = {
98acd46f 633 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
634 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
635 },
636 },
637 {
638 .callback = intel_no_lvds_dmi_callback,
639 .ident = "Apple Mac Mini (Core 2 series)",
640 .matches = {
98acd46f 641 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
642 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
643 },
644 },
645 {
646 .callback = intel_no_lvds_dmi_callback,
647 .ident = "MSI IM-945GSE-A",
648 .matches = {
649 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
650 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
651 },
652 },
653 {
654 .callback = intel_no_lvds_dmi_callback,
655 .ident = "Dell Studio Hybrid",
656 .matches = {
657 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
658 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
659 },
660 },
70aa96ca
JW
661 {
662 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
663 .ident = "Dell OptiPlex FX170",
664 .matches = {
665 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
666 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
667 },
668 },
669 {
670 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
671 .ident = "AOpen Mini PC",
672 .matches = {
673 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
674 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
675 },
676 },
ed8c754b
TV
677 {
678 .callback = intel_no_lvds_dmi_callback,
679 .ident = "AOpen Mini PC MP915",
680 .matches = {
681 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
682 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
683 },
684 },
22ab70d3
KP
685 {
686 .callback = intel_no_lvds_dmi_callback,
687 .ident = "AOpen i915GMm-HFS",
688 .matches = {
689 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
690 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
691 },
692 },
e57b6886
DV
693 {
694 .callback = intel_no_lvds_dmi_callback,
695 .ident = "AOpen i45GMx-I",
696 .matches = {
697 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
698 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
699 },
700 },
fa0864b2
MC
701 {
702 .callback = intel_no_lvds_dmi_callback,
703 .ident = "Aopen i945GTt-VFA",
704 .matches = {
705 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
706 },
707 },
9875557e
SB
708 {
709 .callback = intel_no_lvds_dmi_callback,
710 .ident = "Clientron U800",
711 .matches = {
712 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
713 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
714 },
715 },
6a574b5b 716 {
44306ab3
JS
717 .callback = intel_no_lvds_dmi_callback,
718 .ident = "Clientron E830",
719 .matches = {
720 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
721 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
722 },
723 },
724 {
6a574b5b
HG
725 .callback = intel_no_lvds_dmi_callback,
726 .ident = "Asus EeeBox PC EB1007",
727 .matches = {
728 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
729 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
730 },
731 },
0999bbe0
AJ
732 {
733 .callback = intel_no_lvds_dmi_callback,
734 .ident = "Asus AT5NM10T-I",
735 .matches = {
736 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
737 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
738 },
739 },
33471119
JBG
740 {
741 .callback = intel_no_lvds_dmi_callback,
742 .ident = "Hewlett-Packard HP t5740e Thin Client",
743 .matches = {
744 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
745 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
746 },
747 },
f5b8a7ed
MG
748 {
749 .callback = intel_no_lvds_dmi_callback,
750 .ident = "Hewlett-Packard t5745",
751 .matches = {
752 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 753 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
754 },
755 },
756 {
757 .callback = intel_no_lvds_dmi_callback,
758 .ident = "Hewlett-Packard st5747",
759 .matches = {
760 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 761 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
762 },
763 },
97effadb
AA
764 {
765 .callback = intel_no_lvds_dmi_callback,
766 .ident = "MSI Wind Box DC500",
767 .matches = {
768 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
769 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
770 },
771 },
9756fe38
SS
772 {
773 .callback = intel_no_lvds_dmi_callback,
774 .ident = "ZOTAC ZBOXSD-ID12/ID13",
775 .matches = {
776 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
777 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
778 },
779 },
425d244c
JW
780
781 { } /* terminating entry */
782};
79e53945 783
18f9ed12
ZY
784/**
785 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
786 * @dev: drm device
787 * @connector: LVDS connector
788 *
789 * Find the reduced downclock for LVDS in EDID.
790 */
791static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
792 struct drm_display_mode *fixed_mode,
793 struct drm_connector *connector)
18f9ed12
ZY
794{
795 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 796 struct drm_display_mode *scan;
18f9ed12
ZY
797 int temp_downclock;
798
788319d4 799 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
800 list_for_each_entry(scan, &connector->probed_modes, head) {
801 /*
802 * If one mode has the same resolution with the fixed_panel
803 * mode while they have the different refresh rate, it means
804 * that the reduced downclock is found for the LVDS. In such
805 * case we can set the different FPx0/1 to dynamically select
806 * between low and high frequency.
807 */
788319d4
CW
808 if (scan->hdisplay == fixed_mode->hdisplay &&
809 scan->hsync_start == fixed_mode->hsync_start &&
810 scan->hsync_end == fixed_mode->hsync_end &&
811 scan->htotal == fixed_mode->htotal &&
812 scan->vdisplay == fixed_mode->vdisplay &&
813 scan->vsync_start == fixed_mode->vsync_start &&
814 scan->vsync_end == fixed_mode->vsync_end &&
815 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
816 if (scan->clock < temp_downclock) {
817 /*
818 * The downclock is already found. But we
819 * expect to find the lower downclock.
820 */
821 temp_downclock = scan->clock;
822 }
823 }
824 }
788319d4 825 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
826 /* We found the downclock for LVDS. */
827 dev_priv->lvds_downclock_avail = 1;
828 dev_priv->lvds_downclock = temp_downclock;
829 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
830 "Normal clock %dKhz, downclock %dKhz\n",
831 fixed_mode->clock, temp_downclock);
18f9ed12 832 }
18f9ed12
ZY
833}
834
7cf4f69d
ZY
835/*
836 * Enumerate the child dev array parsed from VBT to check whether
837 * the LVDS is present.
838 * If it is present, return 1.
839 * If it is not present, return false.
840 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 841 */
270eea0f
CW
842static bool lvds_is_present_in_vbt(struct drm_device *dev,
843 u8 *i2c_pin)
7cf4f69d
ZY
844{
845 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 846 int i;
7cf4f69d
ZY
847
848 if (!dev_priv->child_dev_num)
425904dd 849 return true;
7cf4f69d 850
7cf4f69d 851 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
852 struct child_device_config *child = dev_priv->child_dev + i;
853
854 /* If the device type is not LFP, continue.
855 * We have to check both the new identifiers as well as the
856 * old for compatibility with some BIOSes.
7cf4f69d 857 */
425904dd
CW
858 if (child->device_type != DEVICE_TYPE_INT_LFP &&
859 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
860 continue;
861
3bd7d909
DK
862 if (intel_gmbus_is_port_valid(child->i2c_pin))
863 *i2c_pin = child->i2c_pin;
270eea0f 864
425904dd
CW
865 /* However, we cannot trust the BIOS writers to populate
866 * the VBT correctly. Since LVDS requires additional
867 * information from AIM blocks, a non-zero addin offset is
868 * a good indicator that the LVDS is actually present.
7cf4f69d 869 */
425904dd
CW
870 if (child->addin_offset)
871 return true;
872
873 /* But even then some BIOS writers perform some black magic
874 * and instantiate the device without reference to any
875 * additional data. Trust that if the VBT was written into
876 * the OpRegion then they have validated the LVDS's existence.
877 */
878 if (dev_priv->opregion.vbt)
879 return true;
7cf4f69d 880 }
425904dd
CW
881
882 return false;
7cf4f69d
ZY
883}
884
f3cfcba6
CW
885static bool intel_lvds_supported(struct drm_device *dev)
886{
887 /* With the introduction of the PCH we gained a dedicated
888 * LVDS presence pin, use it. */
889 if (HAS_PCH_SPLIT(dev))
890 return true;
891
892 /* Otherwise LVDS was only attached to mobile products,
893 * except for the inglorious 830gm */
894 return IS_MOBILE(dev) && !IS_I830(dev);
895}
896
79e53945
JB
897/**
898 * intel_lvds_init - setup LVDS connectors on this device
899 * @dev: drm device
900 *
901 * Create the connector, register the LVDS DDC bus, and try to figure out what
902 * modes we can display on the LVDS panel (if present).
903 */
c5d1b51d 904bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
905{
906 struct drm_i915_private *dev_priv = dev->dev_private;
ea5b213a 907 struct intel_lvds *intel_lvds;
21d40d37 908 struct intel_encoder *intel_encoder;
bb8a3560 909 struct intel_connector *intel_connector;
79e53945
JB
910 struct drm_connector *connector;
911 struct drm_encoder *encoder;
912 struct drm_display_mode *scan; /* *modes, *bios_mode; */
913 struct drm_crtc *crtc;
914 u32 lvds;
270eea0f
CW
915 int pipe;
916 u8 pin;
79e53945 917
f3cfcba6
CW
918 if (!intel_lvds_supported(dev))
919 return false;
920
425d244c
JW
921 /* Skip init on machines we know falsely report LVDS */
922 if (dmi_check_system(intel_no_lvds))
c5d1b51d 923 return false;
565dcd46 924
270eea0f
CW
925 pin = GMBUS_PORT_PANEL;
926 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 927 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 928 return false;
38b3037e 929 }
e99da35f 930
c619eed4 931 if (HAS_PCH_SPLIT(dev)) {
541998a1 932 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 933 return false;
5ceb0f9b 934 if (dev_priv->edp.support) {
28c97730 935 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 936 return false;
32f9d658 937 }
541998a1
ZW
938 }
939
ea5b213a
CW
940 intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL);
941 if (!intel_lvds) {
c5d1b51d 942 return false;
79e53945
JB
943 }
944
bb8a3560
ZW
945 intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL);
946 if (!intel_connector) {
ea5b213a 947 kfree(intel_lvds);
c5d1b51d 948 return false;
bb8a3560
ZW
949 }
950
e9e331a8
CW
951 if (!HAS_PCH_SPLIT(dev)) {
952 intel_lvds->pfit_control = I915_READ(PFIT_CONTROL);
953 }
954
ea5b213a 955 intel_encoder = &intel_lvds->base;
4ef69c7a 956 encoder = &intel_encoder->base;
ea5b213a 957 connector = &intel_connector->base;
bb8a3560 958 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
959 DRM_MODE_CONNECTOR_LVDS);
960
4ef69c7a 961 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
962 DRM_MODE_ENCODER_LVDS);
963
c22834ec
DV
964 intel_encoder->enable = intel_enable_lvds;
965 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
966 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
967 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 968
df0e9248 969 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 970 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 971
66a9278e 972 intel_encoder->cloneable = false;
27f8227b
JB
973 if (HAS_PCH_SPLIT(dev))
974 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
975 else if (IS_GEN4(dev))
976 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
977 else
978 intel_encoder->crtc_mask = (1 << 1);
979
79e53945
JB
980 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
981 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
982 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
983 connector->interlace_allowed = false;
984 connector->doublescan_allowed = false;
985
3fbe18d6
ZY
986 /* create the scaling mode property */
987 drm_mode_create_scaling_mode_property(dev);
988 /*
989 * the initial panel fitting mode will be FULL_SCREEN.
990 */
79e53945 991
bb8a3560 992 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 993 dev->mode_config.scaling_mode_property,
dd1ea37d 994 DRM_MODE_SCALE_ASPECT);
ea5b213a 995 intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
996 /*
997 * LVDS discovery:
998 * 1) check for EDID on DDC
999 * 2) check for VBT data
1000 * 3) check to see if LVDS is already on
1001 * if none of the above, no panel
1002 * 4) make sure lid is open
1003 * if closed, act like it's not there for now
1004 */
1005
79e53945
JB
1006 /*
1007 * Attempt to get the fixed panel mode from DDC. Assume that the
1008 * preferred mode is the right one.
1009 */
219adae1 1010 intel_lvds->edid = drm_get_edid(connector,
3bd7d909
DK
1011 intel_gmbus_get_adapter(dev_priv,
1012 pin));
3f8ff0e7
CW
1013 if (intel_lvds->edid) {
1014 if (drm_add_edid_modes(connector,
1015 intel_lvds->edid)) {
1016 drm_mode_connector_update_edid_property(connector,
1017 intel_lvds->edid);
1018 } else {
1019 kfree(intel_lvds->edid);
1020 intel_lvds->edid = NULL;
1021 }
1022 }
219adae1 1023 if (!intel_lvds->edid) {
788319d4
CW
1024 /* Didn't get an EDID, so
1025 * Set wide sync ranges so we get all modes
1026 * handed to valid_mode for checking
1027 */
1028 connector->display_info.min_vfreq = 0;
1029 connector->display_info.max_vfreq = 200;
1030 connector->display_info.min_hfreq = 0;
1031 connector->display_info.max_hfreq = 200;
1032 }
79e53945
JB
1033
1034 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1035 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
788319d4 1036 intel_lvds->fixed_mode =
79e53945 1037 drm_mode_duplicate(dev, scan);
788319d4
CW
1038 intel_find_lvds_downclock(dev,
1039 intel_lvds->fixed_mode,
1040 connector);
565dcd46 1041 goto out;
79e53945 1042 }
79e53945
JB
1043 }
1044
1045 /* Failed to get EDID, what about VBT? */
88631706 1046 if (dev_priv->lfp_lvds_vbt_mode) {
788319d4 1047 intel_lvds->fixed_mode =
88631706 1048 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
788319d4
CW
1049 if (intel_lvds->fixed_mode) {
1050 intel_lvds->fixed_mode->type |=
e285f3cd 1051 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1052 goto out;
1053 }
79e53945
JB
1054 }
1055
1056 /*
1057 * If we didn't get EDID, try checking if the panel is already turned
1058 * on. If so, assume that whatever is currently programmed is the
1059 * correct mode.
1060 */
541998a1 1061
f2b115e6 1062 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1063 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1064 goto failed;
1065
79e53945
JB
1066 lvds = I915_READ(LVDS);
1067 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1068 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1069
1070 if (crtc && (lvds & LVDS_PORT_EN)) {
788319d4
CW
1071 intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc);
1072 if (intel_lvds->fixed_mode) {
1073 intel_lvds->fixed_mode->type |=
79e53945 1074 DRM_MODE_TYPE_PREFERRED;
565dcd46 1075 goto out;
79e53945
JB
1076 }
1077 }
1078
1079 /* If we still don't have a mode after all that, give up. */
788319d4 1080 if (!intel_lvds->fixed_mode)
79e53945
JB
1081 goto failed;
1082
79e53945 1083out:
24ded204
DV
1084 /*
1085 * Unlock registers and just
1086 * leave them unlocked
1087 */
c619eed4 1088 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1089 I915_WRITE(PCH_PP_CONTROL,
1090 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1091 } else {
ed10fca9
KP
1092 I915_WRITE(PP_CONTROL,
1093 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1094 }
c1c7af60
JB
1095 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1096 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
28c97730 1097 DRM_DEBUG_KMS("lid notifier registration failed\n");
c1c7af60
JB
1098 dev_priv->lid_notifier.notifier_call = NULL;
1099 }
a2565377
ZY
1100 /* keep the LVDS connector */
1101 dev_priv->int_lvds_connector = connector;
79e53945 1102 drm_sysfs_connector_add(connector);
aaa6fd2a
MG
1103
1104 intel_panel_setup_backlight(dev);
1105
c5d1b51d 1106 return true;
79e53945
JB
1107
1108failed:
8a4c47f3 1109 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1110 drm_connector_cleanup(connector);
1991bdfa 1111 drm_encoder_cleanup(encoder);
ea5b213a 1112 kfree(intel_lvds);
bb8a3560 1113 kfree(intel_connector);
c5d1b51d 1114 return false;
79e53945 1115}