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CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
db1740a0
JN
45
46 struct notifier_block lid_notifier;
62165e0d 47 int fitting_mode;
c7362c4d
JN
48};
49
29b99b48 50struct intel_lvds_encoder {
ea5b213a 51 struct intel_encoder base;
788319d4 52
3fbe18d6
ZY
53 u32 pfit_control;
54 u32 pfit_pgm_ratios;
e9e331a8 55 bool pfit_dirty;
788319d4 56
62165e0d 57 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
58};
59
29b99b48 60static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 61{
29b99b48 62 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
63}
64
c7362c4d
JN
65static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
66{
67 return container_of(connector, struct intel_lvds_connector, base.base);
68}
69
b1dc332c
DV
70static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
71 enum pipe *pipe)
72{
73 struct drm_device *dev = encoder->base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
75 u32 lvds_reg, tmp;
76
77 if (HAS_PCH_SPLIT(dev)) {
78 lvds_reg = PCH_LVDS;
79 } else {
80 lvds_reg = LVDS;
81 }
82
83 tmp = I915_READ(lvds_reg);
84
85 if (!(tmp & LVDS_PORT_EN))
86 return false;
87
88 if (HAS_PCH_CPT(dev))
89 *pipe = PORT_TO_PIPE_CPT(tmp);
90 else
91 *pipe = PORT_TO_PIPE(tmp);
92
93 return true;
94}
95
79e53945
JB
96/**
97 * Sets the power state for the panel.
98 */
c22834ec 99static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 100{
c22834ec 101 struct drm_device *dev = encoder->base.dev;
29b99b48 102 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 103 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 104 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 105 u32 ctl_reg, lvds_reg, stat_reg;
541998a1 106
c619eed4 107 if (HAS_PCH_SPLIT(dev)) {
541998a1 108 ctl_reg = PCH_PP_CONTROL;
469d1296 109 lvds_reg = PCH_LVDS;
de842eff 110 stat_reg = PCH_PP_STATUS;
541998a1
ZW
111 } else {
112 ctl_reg = PP_CONTROL;
469d1296 113 lvds_reg = LVDS;
de842eff 114 stat_reg = PP_STATUS;
541998a1 115 }
79e53945 116
2a1292fd 117 I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN);
e9e331a8 118
29b99b48 119 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
120 /*
121 * Enable automatic panel scaling so that non-native modes
122 * fill the screen. The panel fitter should only be
123 * adjusted whilst the pipe is disabled, according to
124 * register description and PRM.
125 */
126 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
127 lvds_encoder->pfit_control,
128 lvds_encoder->pfit_pgm_ratios);
de842eff 129
29b99b48
JN
130 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
131 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
132 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
133 }
134
135 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
136 POSTING_READ(lvds_reg);
de842eff
KP
137 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
138 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 139
24ded204 140 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
141}
142
c22834ec 143static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 144{
c22834ec 145 struct drm_device *dev = encoder->base.dev;
29b99b48 146 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 147 struct drm_i915_private *dev_priv = dev->dev_private;
de842eff 148 u32 ctl_reg, lvds_reg, stat_reg;
2a1292fd
CW
149
150 if (HAS_PCH_SPLIT(dev)) {
151 ctl_reg = PCH_PP_CONTROL;
152 lvds_reg = PCH_LVDS;
de842eff 153 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
154 } else {
155 ctl_reg = PP_CONTROL;
156 lvds_reg = LVDS;
de842eff 157 stat_reg = PP_STATUS;
2a1292fd
CW
158 }
159
47356eb6 160 intel_panel_disable_backlight(dev);
2a1292fd
CW
161
162 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
163 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
164 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 165
29b99b48 166 if (lvds_encoder->pfit_control) {
2a1292fd 167 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 168 lvds_encoder->pfit_dirty = true;
79e53945 169 }
2a1292fd
CW
170
171 I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN);
c9f9ccc1 172 POSTING_READ(lvds_reg);
79e53945
JB
173}
174
79e53945
JB
175static int intel_lvds_mode_valid(struct drm_connector *connector,
176 struct drm_display_mode *mode)
177{
dd06f90e
JN
178 struct intel_connector *intel_connector = to_intel_connector(connector);
179 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 180
788319d4
CW
181 if (mode->hdisplay > fixed_mode->hdisplay)
182 return MODE_PANEL;
183 if (mode->vdisplay > fixed_mode->vdisplay)
184 return MODE_PANEL;
79e53945
JB
185
186 return MODE_OK;
187}
188
49be663f
CW
189static void
190centre_horizontally(struct drm_display_mode *mode,
191 int width)
192{
193 u32 border, sync_pos, blank_width, sync_width;
194
195 /* keep the hsync and hblank widths constant */
196 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
197 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
198 sync_pos = (blank_width - sync_width + 1) / 2;
199
200 border = (mode->hdisplay - width + 1) / 2;
201 border += border & 1; /* make the border even */
202
203 mode->crtc_hdisplay = width;
204 mode->crtc_hblank_start = width + border;
205 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
206
207 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
208 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
209
210 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
211}
212
213static void
214centre_vertically(struct drm_display_mode *mode,
215 int height)
216{
217 u32 border, sync_pos, blank_width, sync_width;
218
219 /* keep the vsync and vblank widths constant */
220 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
221 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
222 sync_pos = (blank_width - sync_width + 1) / 2;
223
224 border = (mode->vdisplay - height + 1) / 2;
225
226 mode->crtc_vdisplay = height;
227 mode->crtc_vblank_start = height + border;
228 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
229
230 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
231 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
232
233 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
234}
235
236static inline u32 panel_fitter_scaling(u32 source, u32 target)
237{
238 /*
239 * Floating point operation is not supported. So the FACTOR
240 * is defined, which can avoid the floating point computation
241 * when calculating the panel ratio.
242 */
243#define ACCURACY 12
244#define FACTOR (1 << ACCURACY)
245 u32 ratio = source * FACTOR / target;
246 return (FACTOR * ratio + FACTOR/2) / FACTOR;
247}
248
79e53945 249static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 250 const struct drm_display_mode *mode,
79e53945
JB
251 struct drm_display_mode *adjusted_mode)
252{
253 struct drm_device *dev = encoder->dev;
254 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 255 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
62165e0d
JN
256 struct intel_lvds_connector *lvds_connector =
257 lvds_encoder->attached_connector;
29b99b48 258 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 259 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 260 int pipe;
79e53945
JB
261
262 /* Should never happen!! */
a6c45cf0 263 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 264 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
265 return false;
266 }
267
29b99b48 268 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 269 return false;
1d8e1c75 270
79e53945 271 /*
71677043 272 * We have timings from the BIOS for the panel, put them in
79e53945
JB
273 * to the adjusted mode. The CRTC will be set up for this mode,
274 * with the panel scaling set up to source from the H/VDisplay
275 * of the original mode.
276 */
dd06f90e
JN
277 intel_fixed_panel_mode(lvds_connector->base.panel.fixed_mode,
278 adjusted_mode);
1d8e1c75
CW
279
280 if (HAS_PCH_SPLIT(dev)) {
62165e0d 281 intel_pch_panel_fitting(dev, lvds_connector->fitting_mode,
1d8e1c75
CW
282 mode, adjusted_mode);
283 return true;
284 }
79e53945 285
3fbe18d6
ZY
286 /* Native modes don't need fitting */
287 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 288 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 289 goto out;
3fbe18d6
ZY
290
291 /* 965+ wants fuzzy fitting */
a6c45cf0 292 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
293 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
294 PFIT_FILTER_FUZZY);
295
3fbe18d6
ZY
296 /*
297 * Enable automatic panel scaling for non-native modes so that they fill
298 * the screen. Should be enabled before the pipe is enabled, according
299 * to register description and PRM.
300 * Change the value here to see the borders for debugging
301 */
9db4a9c7
JB
302 for_each_pipe(pipe)
303 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 304
f9bef081
DV
305 drm_mode_set_crtcinfo(adjusted_mode, 0);
306
62165e0d 307 switch (lvds_connector->fitting_mode) {
53bd8389 308 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
309 /*
310 * For centered modes, we have to calculate border widths &
311 * heights and modify the values programmed into the CRTC.
312 */
49be663f
CW
313 centre_horizontally(adjusted_mode, mode->hdisplay);
314 centre_vertically(adjusted_mode, mode->vdisplay);
315 border = LVDS_BORDER_ENABLE;
3fbe18d6 316 break;
49be663f 317
3fbe18d6 318 case DRM_MODE_SCALE_ASPECT:
49be663f 319 /* Scale but preserve the aspect ratio */
a6c45cf0 320 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
321 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
322 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
323
3fbe18d6 324 /* 965+ is easy, it does everything in hw */
49be663f 325 if (scaled_width > scaled_height)
257e48f1 326 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 327 else if (scaled_width < scaled_height)
257e48f1
CW
328 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
329 else if (adjusted_mode->hdisplay != mode->hdisplay)
330 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 331 } else {
49be663f
CW
332 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
333 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
334 /*
335 * For earlier chips we have to calculate the scaling
336 * ratio by hand and program it into the
337 * PFIT_PGM_RATIO register
338 */
49be663f
CW
339 if (scaled_width > scaled_height) { /* pillar */
340 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
341
342 border = LVDS_BORDER_ENABLE;
343 if (mode->vdisplay != adjusted_mode->vdisplay) {
344 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
345 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
346 bits << PFIT_VERT_SCALE_SHIFT);
347 pfit_control |= (PFIT_ENABLE |
348 VERT_INTERP_BILINEAR |
349 HORIZ_INTERP_BILINEAR);
350 }
351 } else if (scaled_width < scaled_height) { /* letter */
352 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
353
354 border = LVDS_BORDER_ENABLE;
355 if (mode->hdisplay != adjusted_mode->hdisplay) {
356 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
357 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
358 bits << PFIT_VERT_SCALE_SHIFT);
359 pfit_control |= (PFIT_ENABLE |
360 VERT_INTERP_BILINEAR |
361 HORIZ_INTERP_BILINEAR);
362 }
363 } else
364 /* Aspects match, Let hw scale both directions */
365 pfit_control |= (PFIT_ENABLE |
366 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
367 VERT_INTERP_BILINEAR |
368 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
369 }
370 break;
371
372 case DRM_MODE_SCALE_FULLSCREEN:
373 /*
374 * Full scaling, even if it changes the aspect ratio.
375 * Fortunately this is all done for us in hw.
376 */
257e48f1
CW
377 if (mode->vdisplay != adjusted_mode->vdisplay ||
378 mode->hdisplay != adjusted_mode->hdisplay) {
379 pfit_control |= PFIT_ENABLE;
380 if (INTEL_INFO(dev)->gen >= 4)
381 pfit_control |= PFIT_SCALING_AUTO;
382 else
383 pfit_control |= (VERT_AUTO_SCALE |
384 VERT_INTERP_BILINEAR |
385 HORIZ_AUTO_SCALE |
386 HORIZ_INTERP_BILINEAR);
387 }
3fbe18d6 388 break;
49be663f 389
3fbe18d6
ZY
390 default:
391 break;
392 }
393
394out:
72389a33 395 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
396 if ((pfit_control & PFIT_ENABLE) == 0) {
397 pfit_control = 0;
398 pfit_pgm_ratios = 0;
399 }
72389a33
CW
400
401 /* Make sure pre-965 set dither correctly */
402 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
403 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
404
29b99b48
JN
405 if (pfit_control != lvds_encoder->pfit_control ||
406 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
407 lvds_encoder->pfit_control = pfit_control;
408 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
409 lvds_encoder->pfit_dirty = true;
e9e331a8 410 }
49be663f
CW
411 dev_priv->lvds_border_bits = border;
412
79e53945
JB
413 /*
414 * XXX: It would be nice to support lower refresh rates on the
415 * panels to reduce power consumption, and perhaps match the
416 * user's requested refresh rate.
417 */
418
419 return true;
420}
421
79e53945
JB
422static void intel_lvds_mode_set(struct drm_encoder *encoder,
423 struct drm_display_mode *mode,
424 struct drm_display_mode *adjusted_mode)
425{
79e53945
JB
426 /*
427 * The LVDS pin pair will already have been turned on in the
428 * intel_crtc_mode_set since it has a large impact on the DPLL
429 * settings.
430 */
79e53945
JB
431}
432
433/**
434 * Detect the LVDS connection.
435 *
b42d4c5c
JB
436 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
437 * connected and closed means disconnected. We also send hotplug events as
438 * needed, using lid status notification from the input layer.
79e53945 439 */
7b334fcb 440static enum drm_connector_status
930a9e28 441intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 442{
7b9c5abe 443 struct drm_device *dev = connector->dev;
6ee3b5a1 444 enum drm_connector_status status;
b42d4c5c 445
fe16d949
CW
446 status = intel_panel_detect(dev);
447 if (status != connector_status_unknown)
448 return status;
01fe9dbd 449
6ee3b5a1 450 return connector_status_connected;
79e53945
JB
451}
452
453/**
454 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
455 */
456static int intel_lvds_get_modes(struct drm_connector *connector)
457{
62165e0d 458 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 459 struct drm_device *dev = connector->dev;
788319d4 460 struct drm_display_mode *mode;
79e53945 461
9cd300e0
JN
462 /* use cached edid if we have one */
463 if (lvds_connector->base.edid) {
464 /* invalid edid */
465 if (IS_ERR(lvds_connector->base.edid))
466 return 0;
467
468 return drm_add_edid_modes(connector, lvds_connector->base.edid);
469 }
79e53945 470
dd06f90e 471 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 472 if (mode == NULL)
788319d4 473 return 0;
79e53945 474
788319d4
CW
475 drm_mode_probed_add(connector, mode);
476 return 1;
79e53945
JB
477}
478
0544edfd
TB
479static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
480{
bc0daf48 481 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
482 return 1;
483}
484
485/* The GPU hangs up on these systems if modeset is performed on LID open */
486static const struct dmi_system_id intel_no_modeset_on_lid[] = {
487 {
488 .callback = intel_no_modeset_on_lid_dmi_callback,
489 .ident = "Toshiba Tecra A11",
490 .matches = {
491 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
492 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
493 },
494 },
495
496 { } /* terminating entry */
497};
498
c9354c85
LT
499/*
500 * Lid events. Note the use of 'modeset_on_lid':
501 * - we set it on lid close, and reset it on open
502 * - we use it as a "only once" bit (ie we ignore
503 * duplicate events where it was already properly
504 * set/reset)
505 * - the suspend/resume paths will also set it to
506 * zero, since they restore the mode ("lid open").
507 */
c1c7af60
JB
508static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
509 void *unused)
510{
db1740a0
JN
511 struct intel_lvds_connector *lvds_connector =
512 container_of(nb, struct intel_lvds_connector, lid_notifier);
513 struct drm_connector *connector = &lvds_connector->base.base;
514 struct drm_device *dev = connector->dev;
515 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 516
2fb4e61d
AW
517 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
518 return NOTIFY_OK;
519
a2565377
ZY
520 /*
521 * check and update the status of LVDS connector after receiving
522 * the LID nofication event.
523 */
db1740a0 524 connector->status = connector->funcs->detect(connector, false);
7b334fcb 525
0544edfd
TB
526 /* Don't force modeset on machines where it causes a GPU lockup */
527 if (dmi_check_system(intel_no_modeset_on_lid))
528 return NOTIFY_OK;
c9354c85
LT
529 if (!acpi_lid_open()) {
530 dev_priv->modeset_on_lid = 1;
531 return NOTIFY_OK;
06891e27 532 }
c1c7af60 533
c9354c85
LT
534 if (!dev_priv->modeset_on_lid)
535 return NOTIFY_OK;
536
537 dev_priv->modeset_on_lid = 0;
538
539 mutex_lock(&dev->mode_config.mutex);
3b7a89fc 540 intel_modeset_check_state(dev);
c9354c85 541 mutex_unlock(&dev->mode_config.mutex);
06324194 542
c1c7af60
JB
543 return NOTIFY_OK;
544}
545
79e53945
JB
546/**
547 * intel_lvds_destroy - unregister and free LVDS structures
548 * @connector: connector to free
549 *
550 * Unregister the DDC bus for this connector then free the driver private
551 * structure.
552 */
553static void intel_lvds_destroy(struct drm_connector *connector)
554{
db1740a0
JN
555 struct intel_lvds_connector *lvds_connector =
556 to_lvds_connector(connector);
557
558 if (lvds_connector->lid_notifier.notifier_call)
559 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 560
9cd300e0
JN
561 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
562 kfree(lvds_connector->base.edid);
563
db1740a0 564 intel_panel_destroy_backlight(connector->dev);
1d508706 565 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 566
79e53945
JB
567 drm_sysfs_connector_remove(connector);
568 drm_connector_cleanup(connector);
569 kfree(connector);
570}
571
335041ed
JB
572static int intel_lvds_set_property(struct drm_connector *connector,
573 struct drm_property *property,
574 uint64_t value)
575{
62165e0d 576 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
3fbe18d6 577 struct drm_device *dev = connector->dev;
3fbe18d6 578
788319d4 579 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 580 struct drm_crtc *crtc;
bb8a3560 581
53bd8389
JB
582 if (value == DRM_MODE_SCALE_NONE) {
583 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 584 return -EINVAL;
3fbe18d6 585 }
788319d4 586
62165e0d 587 if (lvds_connector->fitting_mode == value) {
3fbe18d6
ZY
588 /* the LVDS scaling property is not changed */
589 return 0;
590 }
62165e0d
JN
591 lvds_connector->fitting_mode = value;
592
593 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
594 if (crtc && crtc->enabled) {
595 /*
596 * If the CRTC is enabled, the display will be changed
597 * according to the new panel fitting mode.
598 */
a6778b3c
DV
599 intel_set_mode(crtc, &crtc->mode,
600 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
601 }
602 }
603
335041ed
JB
604 return 0;
605}
606
79e53945 607static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 608 .mode_fixup = intel_lvds_mode_fixup,
79e53945 609 .mode_set = intel_lvds_mode_set,
1f703855 610 .disable = intel_encoder_noop,
79e53945
JB
611};
612
613static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
614 .get_modes = intel_lvds_get_modes,
615 .mode_valid = intel_lvds_mode_valid,
df0e9248 616 .best_encoder = intel_best_encoder,
79e53945
JB
617};
618
619static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 620 .dpms = intel_connector_dpms,
79e53945
JB
621 .detect = intel_lvds_detect,
622 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 623 .set_property = intel_lvds_set_property,
79e53945
JB
624 .destroy = intel_lvds_destroy,
625};
626
79e53945 627static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 628 .destroy = intel_encoder_destroy,
79e53945
JB
629};
630
425d244c
JW
631static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
632{
bc0daf48 633 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
634 return 1;
635}
79e53945 636
425d244c 637/* These systems claim to have LVDS, but really don't */
93c05f22 638static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
639 {
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "Apple Mac Mini (Core series)",
642 .matches = {
98acd46f 643 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
644 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
645 },
646 },
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "Apple Mac Mini (Core 2 series)",
650 .matches = {
98acd46f 651 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
652 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
653 },
654 },
655 {
656 .callback = intel_no_lvds_dmi_callback,
657 .ident = "MSI IM-945GSE-A",
658 .matches = {
659 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
660 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
661 },
662 },
663 {
664 .callback = intel_no_lvds_dmi_callback,
665 .ident = "Dell Studio Hybrid",
666 .matches = {
667 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
668 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
669 },
670 },
70aa96ca
JW
671 {
672 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
673 .ident = "Dell OptiPlex FX170",
674 .matches = {
675 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
676 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
677 },
678 },
679 {
680 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
681 .ident = "AOpen Mini PC",
682 .matches = {
683 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
684 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
685 },
686 },
ed8c754b
TV
687 {
688 .callback = intel_no_lvds_dmi_callback,
689 .ident = "AOpen Mini PC MP915",
690 .matches = {
691 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
692 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
693 },
694 },
22ab70d3
KP
695 {
696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "AOpen i915GMm-HFS",
698 .matches = {
699 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
700 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
701 },
702 },
e57b6886
DV
703 {
704 .callback = intel_no_lvds_dmi_callback,
705 .ident = "AOpen i45GMx-I",
706 .matches = {
707 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
708 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
709 },
710 },
fa0864b2
MC
711 {
712 .callback = intel_no_lvds_dmi_callback,
713 .ident = "Aopen i945GTt-VFA",
714 .matches = {
715 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
716 },
717 },
9875557e
SB
718 {
719 .callback = intel_no_lvds_dmi_callback,
720 .ident = "Clientron U800",
721 .matches = {
722 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
723 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
724 },
725 },
6a574b5b 726 {
44306ab3
JS
727 .callback = intel_no_lvds_dmi_callback,
728 .ident = "Clientron E830",
729 .matches = {
730 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
731 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
732 },
733 },
734 {
6a574b5b
HG
735 .callback = intel_no_lvds_dmi_callback,
736 .ident = "Asus EeeBox PC EB1007",
737 .matches = {
738 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
739 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
740 },
741 },
0999bbe0
AJ
742 {
743 .callback = intel_no_lvds_dmi_callback,
744 .ident = "Asus AT5NM10T-I",
745 .matches = {
746 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
747 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
748 },
749 },
33471119
JBG
750 {
751 .callback = intel_no_lvds_dmi_callback,
752 .ident = "Hewlett-Packard HP t5740e Thin Client",
753 .matches = {
754 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
755 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
756 },
757 },
f5b8a7ed
MG
758 {
759 .callback = intel_no_lvds_dmi_callback,
760 .ident = "Hewlett-Packard t5745",
761 .matches = {
762 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 763 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
764 },
765 },
766 {
767 .callback = intel_no_lvds_dmi_callback,
768 .ident = "Hewlett-Packard st5747",
769 .matches = {
770 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 771 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
772 },
773 },
97effadb
AA
774 {
775 .callback = intel_no_lvds_dmi_callback,
776 .ident = "MSI Wind Box DC500",
777 .matches = {
778 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
779 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
780 },
781 },
9756fe38
SS
782 {
783 .callback = intel_no_lvds_dmi_callback,
784 .ident = "ZOTAC ZBOXSD-ID12/ID13",
785 .matches = {
786 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
787 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
788 },
789 },
a51d4ed0
CW
790 {
791 .callback = intel_no_lvds_dmi_callback,
792 .ident = "Gigabyte GA-D525TUD",
793 .matches = {
794 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
795 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
796 },
797 },
425d244c
JW
798
799 { } /* terminating entry */
800};
79e53945 801
18f9ed12
ZY
802/**
803 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
804 * @dev: drm device
805 * @connector: LVDS connector
806 *
807 * Find the reduced downclock for LVDS in EDID.
808 */
809static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
810 struct drm_display_mode *fixed_mode,
811 struct drm_connector *connector)
18f9ed12
ZY
812{
813 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 814 struct drm_display_mode *scan;
18f9ed12
ZY
815 int temp_downclock;
816
788319d4 817 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
818 list_for_each_entry(scan, &connector->probed_modes, head) {
819 /*
820 * If one mode has the same resolution with the fixed_panel
821 * mode while they have the different refresh rate, it means
822 * that the reduced downclock is found for the LVDS. In such
823 * case we can set the different FPx0/1 to dynamically select
824 * between low and high frequency.
825 */
788319d4
CW
826 if (scan->hdisplay == fixed_mode->hdisplay &&
827 scan->hsync_start == fixed_mode->hsync_start &&
828 scan->hsync_end == fixed_mode->hsync_end &&
829 scan->htotal == fixed_mode->htotal &&
830 scan->vdisplay == fixed_mode->vdisplay &&
831 scan->vsync_start == fixed_mode->vsync_start &&
832 scan->vsync_end == fixed_mode->vsync_end &&
833 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
834 if (scan->clock < temp_downclock) {
835 /*
836 * The downclock is already found. But we
837 * expect to find the lower downclock.
838 */
839 temp_downclock = scan->clock;
840 }
841 }
842 }
788319d4 843 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
844 /* We found the downclock for LVDS. */
845 dev_priv->lvds_downclock_avail = 1;
846 dev_priv->lvds_downclock = temp_downclock;
847 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
848 "Normal clock %dKhz, downclock %dKhz\n",
849 fixed_mode->clock, temp_downclock);
18f9ed12 850 }
18f9ed12
ZY
851}
852
7cf4f69d
ZY
853/*
854 * Enumerate the child dev array parsed from VBT to check whether
855 * the LVDS is present.
856 * If it is present, return 1.
857 * If it is not present, return false.
858 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 859 */
270eea0f
CW
860static bool lvds_is_present_in_vbt(struct drm_device *dev,
861 u8 *i2c_pin)
7cf4f69d
ZY
862{
863 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 864 int i;
7cf4f69d
ZY
865
866 if (!dev_priv->child_dev_num)
425904dd 867 return true;
7cf4f69d 868
7cf4f69d 869 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
870 struct child_device_config *child = dev_priv->child_dev + i;
871
872 /* If the device type is not LFP, continue.
873 * We have to check both the new identifiers as well as the
874 * old for compatibility with some BIOSes.
7cf4f69d 875 */
425904dd
CW
876 if (child->device_type != DEVICE_TYPE_INT_LFP &&
877 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
878 continue;
879
3bd7d909
DK
880 if (intel_gmbus_is_port_valid(child->i2c_pin))
881 *i2c_pin = child->i2c_pin;
270eea0f 882
425904dd
CW
883 /* However, we cannot trust the BIOS writers to populate
884 * the VBT correctly. Since LVDS requires additional
885 * information from AIM blocks, a non-zero addin offset is
886 * a good indicator that the LVDS is actually present.
7cf4f69d 887 */
425904dd
CW
888 if (child->addin_offset)
889 return true;
890
891 /* But even then some BIOS writers perform some black magic
892 * and instantiate the device without reference to any
893 * additional data. Trust that if the VBT was written into
894 * the OpRegion then they have validated the LVDS's existence.
895 */
896 if (dev_priv->opregion.vbt)
897 return true;
7cf4f69d 898 }
425904dd
CW
899
900 return false;
7cf4f69d
ZY
901}
902
f3cfcba6
CW
903static bool intel_lvds_supported(struct drm_device *dev)
904{
905 /* With the introduction of the PCH we gained a dedicated
906 * LVDS presence pin, use it. */
907 if (HAS_PCH_SPLIT(dev))
908 return true;
909
910 /* Otherwise LVDS was only attached to mobile products,
911 * except for the inglorious 830gm */
912 return IS_MOBILE(dev) && !IS_I830(dev);
913}
914
79e53945
JB
915/**
916 * intel_lvds_init - setup LVDS connectors on this device
917 * @dev: drm device
918 *
919 * Create the connector, register the LVDS DDC bus, and try to figure out what
920 * modes we can display on the LVDS panel (if present).
921 */
c5d1b51d 922bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
923{
924 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 925 struct intel_lvds_encoder *lvds_encoder;
21d40d37 926 struct intel_encoder *intel_encoder;
c7362c4d 927 struct intel_lvds_connector *lvds_connector;
bb8a3560 928 struct intel_connector *intel_connector;
79e53945
JB
929 struct drm_connector *connector;
930 struct drm_encoder *encoder;
931 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 932 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 933 struct edid *edid;
79e53945
JB
934 struct drm_crtc *crtc;
935 u32 lvds;
270eea0f
CW
936 int pipe;
937 u8 pin;
79e53945 938
f3cfcba6
CW
939 if (!intel_lvds_supported(dev))
940 return false;
941
425d244c
JW
942 /* Skip init on machines we know falsely report LVDS */
943 if (dmi_check_system(intel_no_lvds))
c5d1b51d 944 return false;
565dcd46 945
270eea0f
CW
946 pin = GMBUS_PORT_PANEL;
947 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 948 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 949 return false;
38b3037e 950 }
e99da35f 951
c619eed4 952 if (HAS_PCH_SPLIT(dev)) {
541998a1 953 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 954 return false;
5ceb0f9b 955 if (dev_priv->edp.support) {
28c97730 956 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 957 return false;
32f9d658 958 }
541998a1
ZW
959 }
960
29b99b48
JN
961 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
962 if (!lvds_encoder)
c5d1b51d 963 return false;
79e53945 964
c7362c4d
JN
965 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
966 if (!lvds_connector) {
29b99b48 967 kfree(lvds_encoder);
c5d1b51d 968 return false;
bb8a3560
ZW
969 }
970
62165e0d
JN
971 lvds_encoder->attached_connector = lvds_connector;
972
e9e331a8 973 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 974 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
975 }
976
29b99b48 977 intel_encoder = &lvds_encoder->base;
4ef69c7a 978 encoder = &intel_encoder->base;
c7362c4d 979 intel_connector = &lvds_connector->base;
ea5b213a 980 connector = &intel_connector->base;
bb8a3560 981 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
982 DRM_MODE_CONNECTOR_LVDS);
983
4ef69c7a 984 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
985 DRM_MODE_ENCODER_LVDS);
986
c22834ec
DV
987 intel_encoder->enable = intel_enable_lvds;
988 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
989 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
990 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 991
df0e9248 992 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 993 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 994
66a9278e 995 intel_encoder->cloneable = false;
27f8227b
JB
996 if (HAS_PCH_SPLIT(dev))
997 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
998 else if (IS_GEN4(dev))
999 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1000 else
1001 intel_encoder->crtc_mask = (1 << 1);
1002
79e53945
JB
1003 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1004 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1005 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1006 connector->interlace_allowed = false;
1007 connector->doublescan_allowed = false;
1008
3fbe18d6
ZY
1009 /* create the scaling mode property */
1010 drm_mode_create_scaling_mode_property(dev);
1011 /*
1012 * the initial panel fitting mode will be FULL_SCREEN.
1013 */
79e53945 1014
bb8a3560 1015 drm_connector_attach_property(&intel_connector->base,
3fbe18d6 1016 dev->mode_config.scaling_mode_property,
dd1ea37d 1017 DRM_MODE_SCALE_ASPECT);
62165e0d 1018 lvds_connector->fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1019 /*
1020 * LVDS discovery:
1021 * 1) check for EDID on DDC
1022 * 2) check for VBT data
1023 * 3) check to see if LVDS is already on
1024 * if none of the above, no panel
1025 * 4) make sure lid is open
1026 * if closed, act like it's not there for now
1027 */
1028
79e53945
JB
1029 /*
1030 * Attempt to get the fixed panel mode from DDC. Assume that the
1031 * preferred mode is the right one.
1032 */
9cd300e0
JN
1033 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1034 if (edid) {
1035 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1036 drm_mode_connector_update_edid_property(connector,
9cd300e0 1037 edid);
3f8ff0e7 1038 } else {
9cd300e0
JN
1039 kfree(edid);
1040 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1041 }
9cd300e0
JN
1042 } else {
1043 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1044 }
9cd300e0
JN
1045 lvds_connector->base.edid = edid;
1046
1047 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1048 /* Didn't get an EDID, so
1049 * Set wide sync ranges so we get all modes
1050 * handed to valid_mode for checking
1051 */
1052 connector->display_info.min_vfreq = 0;
1053 connector->display_info.max_vfreq = 200;
1054 connector->display_info.min_hfreq = 0;
1055 connector->display_info.max_hfreq = 200;
1056 }
79e53945
JB
1057
1058 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1059 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
dd06f90e
JN
1060 fixed_mode = drm_mode_duplicate(dev, scan);
1061 intel_find_lvds_downclock(dev, fixed_mode, connector);
565dcd46 1062 goto out;
79e53945 1063 }
79e53945
JB
1064 }
1065
1066 /* Failed to get EDID, what about VBT? */
88631706 1067 if (dev_priv->lfp_lvds_vbt_mode) {
dd06f90e
JN
1068 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1069 if (fixed_mode) {
1070 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1071 goto out;
1072 }
79e53945
JB
1073 }
1074
1075 /*
1076 * If we didn't get EDID, try checking if the panel is already turned
1077 * on. If so, assume that whatever is currently programmed is the
1078 * correct mode.
1079 */
541998a1 1080
f2b115e6 1081 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1082 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1083 goto failed;
1084
79e53945
JB
1085 lvds = I915_READ(LVDS);
1086 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1087 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1088
1089 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1090 fixed_mode = intel_crtc_mode_get(dev, crtc);
1091 if (fixed_mode) {
1092 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1093 goto out;
79e53945
JB
1094 }
1095 }
1096
1097 /* If we still don't have a mode after all that, give up. */
dd06f90e 1098 if (!fixed_mode)
79e53945
JB
1099 goto failed;
1100
79e53945 1101out:
24ded204
DV
1102 /*
1103 * Unlock registers and just
1104 * leave them unlocked
1105 */
c619eed4 1106 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1107 I915_WRITE(PCH_PP_CONTROL,
1108 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1109 } else {
ed10fca9
KP
1110 I915_WRITE(PP_CONTROL,
1111 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1112 }
db1740a0
JN
1113 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1114 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1115 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1116 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1117 }
79e53945 1118 drm_sysfs_connector_add(connector);
aaa6fd2a 1119
dd06f90e 1120 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1121 intel_panel_setup_backlight(connector);
aaa6fd2a 1122
c5d1b51d 1123 return true;
79e53945
JB
1124
1125failed:
8a4c47f3 1126 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1127 drm_connector_cleanup(connector);
1991bdfa 1128 drm_encoder_cleanup(encoder);
dd06f90e
JN
1129 if (fixed_mode)
1130 drm_mode_destroy(dev, fixed_mode);
29b99b48 1131 kfree(lvds_encoder);
c7362c4d 1132 kfree(lvds_connector);
c5d1b51d 1133 return false;
79e53945 1134}