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drm/i915: use ACPI LID status for LVDS ->detect hook
[mirror_ubuntu-zesty-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
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79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945
JB
32#include <linux/i2c.h>
33#include "drmP.h"
34#include "drm.h"
35#include "drm_crtc.h"
36#include "drm_edid.h"
37#include "intel_drv.h"
38#include "i915_drm.h"
39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6
ZY
42/* Private structure for the integrated LVDS support */
43struct intel_lvds_priv {
44 int fitting_mode;
45 u32 pfit_control;
46 u32 pfit_pgm_ratios;
47};
48
79e53945
JB
49/**
50 * Sets the backlight level.
51 *
52 * \param level backlight level, from 0 to intel_lvds_get_max_backlight().
53 */
54static void intel_lvds_set_backlight(struct drm_device *dev, int level)
55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 57 u32 blc_pwm_ctl, reg;
79e53945 58
541998a1
ZW
59 if (IS_IGDNG(dev))
60 reg = BLC_PWM_CPU_CTL;
61 else
62 reg = BLC_PWM_CTL;
79e53945 63
541998a1
ZW
64 blc_pwm_ctl = I915_READ(reg) & ~BACKLIGHT_DUTY_CYCLE_MASK;
65 I915_WRITE(reg, (blc_pwm_ctl |
79e53945
JB
66 (level << BACKLIGHT_DUTY_CYCLE_SHIFT)));
67}
68
69/**
70 * Returns the maximum level of the backlight duty cycle field.
71 */
72static u32 intel_lvds_get_max_backlight(struct drm_device *dev)
73{
74 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
75 u32 reg;
76
77 if (IS_IGDNG(dev))
78 reg = BLC_PWM_PCH_CTL2;
79 else
80 reg = BLC_PWM_CTL;
79e53945 81
541998a1 82 return ((I915_READ(reg) & BACKLIGHT_MODULATION_FREQ_MASK) >>
79e53945
JB
83 BACKLIGHT_MODULATION_FREQ_SHIFT) * 2;
84}
85
86/**
87 * Sets the power state for the panel.
88 */
89static void intel_lvds_set_power(struct drm_device *dev, bool on)
90{
91 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
92 u32 pp_status, ctl_reg, status_reg;
93
94 if (IS_IGDNG(dev)) {
95 ctl_reg = PCH_PP_CONTROL;
96 status_reg = PCH_PP_STATUS;
97 } else {
98 ctl_reg = PP_CONTROL;
99 status_reg = PP_STATUS;
100 }
79e53945
JB
101
102 if (on) {
541998a1 103 I915_WRITE(ctl_reg, I915_READ(ctl_reg) |
79e53945
JB
104 POWER_TARGET_ON);
105 do {
541998a1 106 pp_status = I915_READ(status_reg);
79e53945
JB
107 } while ((pp_status & PP_ON) == 0);
108
109 intel_lvds_set_backlight(dev, dev_priv->backlight_duty_cycle);
110 } else {
111 intel_lvds_set_backlight(dev, 0);
112
541998a1 113 I915_WRITE(ctl_reg, I915_READ(ctl_reg) &
79e53945
JB
114 ~POWER_TARGET_ON);
115 do {
541998a1 116 pp_status = I915_READ(status_reg);
79e53945
JB
117 } while (pp_status & PP_ON);
118 }
119}
120
121static void intel_lvds_dpms(struct drm_encoder *encoder, int mode)
122{
123 struct drm_device *dev = encoder->dev;
124
125 if (mode == DRM_MODE_DPMS_ON)
126 intel_lvds_set_power(dev, true);
127 else
128 intel_lvds_set_power(dev, false);
129
130 /* XXX: We never power down the LVDS pairs. */
131}
132
133static void intel_lvds_save(struct drm_connector *connector)
134{
135 struct drm_device *dev = connector->dev;
136 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
137 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
138 u32 pwm_ctl_reg;
139
140 if (IS_IGDNG(dev)) {
141 pp_on_reg = PCH_PP_ON_DELAYS;
142 pp_off_reg = PCH_PP_OFF_DELAYS;
143 pp_ctl_reg = PCH_PP_CONTROL;
144 pp_div_reg = PCH_PP_DIVISOR;
145 pwm_ctl_reg = BLC_PWM_CPU_CTL;
146 } else {
147 pp_on_reg = PP_ON_DELAYS;
148 pp_off_reg = PP_OFF_DELAYS;
149 pp_ctl_reg = PP_CONTROL;
150 pp_div_reg = PP_DIVISOR;
151 pwm_ctl_reg = BLC_PWM_CTL;
152 }
79e53945 153
541998a1
ZW
154 dev_priv->savePP_ON = I915_READ(pp_on_reg);
155 dev_priv->savePP_OFF = I915_READ(pp_off_reg);
156 dev_priv->savePP_CONTROL = I915_READ(pp_ctl_reg);
157 dev_priv->savePP_DIVISOR = I915_READ(pp_div_reg);
158 dev_priv->saveBLC_PWM_CTL = I915_READ(pwm_ctl_reg);
79e53945
JB
159 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
160 BACKLIGHT_DUTY_CYCLE_MASK);
161
162 /*
163 * If the light is off at server startup, just make it full brightness
164 */
165 if (dev_priv->backlight_duty_cycle == 0)
166 dev_priv->backlight_duty_cycle =
167 intel_lvds_get_max_backlight(dev);
168}
169
170static void intel_lvds_restore(struct drm_connector *connector)
171{
172 struct drm_device *dev = connector->dev;
173 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1
ZW
174 u32 pp_on_reg, pp_off_reg, pp_ctl_reg, pp_div_reg;
175 u32 pwm_ctl_reg;
176
177 if (IS_IGDNG(dev)) {
178 pp_on_reg = PCH_PP_ON_DELAYS;
179 pp_off_reg = PCH_PP_OFF_DELAYS;
180 pp_ctl_reg = PCH_PP_CONTROL;
181 pp_div_reg = PCH_PP_DIVISOR;
182 pwm_ctl_reg = BLC_PWM_CPU_CTL;
183 } else {
184 pp_on_reg = PP_ON_DELAYS;
185 pp_off_reg = PP_OFF_DELAYS;
186 pp_ctl_reg = PP_CONTROL;
187 pp_div_reg = PP_DIVISOR;
188 pwm_ctl_reg = BLC_PWM_CTL;
189 }
79e53945 190
541998a1
ZW
191 I915_WRITE(pwm_ctl_reg, dev_priv->saveBLC_PWM_CTL);
192 I915_WRITE(pp_on_reg, dev_priv->savePP_ON);
193 I915_WRITE(pp_off_reg, dev_priv->savePP_OFF);
194 I915_WRITE(pp_div_reg, dev_priv->savePP_DIVISOR);
195 I915_WRITE(pp_ctl_reg, dev_priv->savePP_CONTROL);
79e53945
JB
196 if (dev_priv->savePP_CONTROL & POWER_TARGET_ON)
197 intel_lvds_set_power(dev, true);
198 else
199 intel_lvds_set_power(dev, false);
200}
201
202static int intel_lvds_mode_valid(struct drm_connector *connector,
203 struct drm_display_mode *mode)
204{
205 struct drm_device *dev = connector->dev;
206 struct drm_i915_private *dev_priv = dev->dev_private;
207 struct drm_display_mode *fixed_mode = dev_priv->panel_fixed_mode;
208
209 if (fixed_mode) {
210 if (mode->hdisplay > fixed_mode->hdisplay)
211 return MODE_PANEL;
212 if (mode->vdisplay > fixed_mode->vdisplay)
213 return MODE_PANEL;
214 }
215
216 return MODE_OK;
217}
218
219static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
220 struct drm_display_mode *mode,
221 struct drm_display_mode *adjusted_mode)
222{
3fbe18d6
ZY
223 /*
224 * float point operation is not supported . So the PANEL_RATIO_FACTOR
225 * is defined, which can avoid the float point computation when
226 * calculating the panel ratio.
227 */
228#define PANEL_RATIO_FACTOR 8192
79e53945
JB
229 struct drm_device *dev = encoder->dev;
230 struct drm_i915_private *dev_priv = dev->dev_private;
231 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc);
232 struct drm_encoder *tmp_encoder;
3fbe18d6
ZY
233 struct intel_output *intel_output = enc_to_intel_output(encoder);
234 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
235 u32 pfit_control = 0, pfit_pgm_ratios = 0;
236 int left_border = 0, right_border = 0, top_border = 0;
237 int bottom_border = 0;
238 bool border = 0;
239 int panel_ratio, desired_ratio, vert_scale, horiz_scale;
240 int horiz_ratio, vert_ratio;
aa0261f2
ZY
241 u32 hsync_width, vsync_width;
242 u32 hblank_width, vblank_width;
243 u32 hsync_pos, vsync_pos;
79e53945
JB
244
245 /* Should never happen!! */
246 if (!IS_I965G(dev) && intel_crtc->pipe == 0) {
1ae8c0a5 247 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
248 return false;
249 }
250
251 /* Should never happen!! */
252 list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) {
253 if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) {
1ae8c0a5 254 DRM_ERROR("Can't enable LVDS and another "
79e53945
JB
255 "encoder on the same pipe\n");
256 return false;
257 }
258 }
3fbe18d6
ZY
259 /* If we don't have a panel mode, there is nothing we can do */
260 if (dev_priv->panel_fixed_mode == NULL)
261 return true;
79e53945
JB
262 /*
263 * If we have timings from the BIOS for the panel, put them in
264 * to the adjusted mode. The CRTC will be set up for this mode,
265 * with the panel scaling set up to source from the H/VDisplay
266 * of the original mode.
267 */
268 if (dev_priv->panel_fixed_mode != NULL) {
269 adjusted_mode->hdisplay = dev_priv->panel_fixed_mode->hdisplay;
270 adjusted_mode->hsync_start =
271 dev_priv->panel_fixed_mode->hsync_start;
272 adjusted_mode->hsync_end =
273 dev_priv->panel_fixed_mode->hsync_end;
274 adjusted_mode->htotal = dev_priv->panel_fixed_mode->htotal;
275 adjusted_mode->vdisplay = dev_priv->panel_fixed_mode->vdisplay;
276 adjusted_mode->vsync_start =
277 dev_priv->panel_fixed_mode->vsync_start;
278 adjusted_mode->vsync_end =
279 dev_priv->panel_fixed_mode->vsync_end;
280 adjusted_mode->vtotal = dev_priv->panel_fixed_mode->vtotal;
281 adjusted_mode->clock = dev_priv->panel_fixed_mode->clock;
282 drm_mode_set_crtcinfo(adjusted_mode, CRTC_INTERLACE_HALVE_V);
283 }
284
3fbe18d6
ZY
285 /* Make sure pre-965s set dither correctly */
286 if (!IS_I965G(dev)) {
287 if (dev_priv->panel_wants_dither || dev_priv->lvds_dither)
288 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
289 }
290
291 /* Native modes don't need fitting */
292 if (adjusted_mode->hdisplay == mode->hdisplay &&
293 adjusted_mode->vdisplay == mode->vdisplay) {
294 pfit_pgm_ratios = 0;
295 border = 0;
296 goto out;
297 }
298
299 /* 965+ wants fuzzy fitting */
300 if (IS_I965G(dev))
301 pfit_control |= (intel_crtc->pipe << PFIT_PIPE_SHIFT) |
302 PFIT_FILTER_FUZZY;
303
aa0261f2
ZY
304 hsync_width = adjusted_mode->crtc_hsync_end -
305 adjusted_mode->crtc_hsync_start;
306 vsync_width = adjusted_mode->crtc_vsync_end -
307 adjusted_mode->crtc_vsync_start;
308 hblank_width = adjusted_mode->crtc_hblank_end -
309 adjusted_mode->crtc_hblank_start;
310 vblank_width = adjusted_mode->crtc_vblank_end -
311 adjusted_mode->crtc_vblank_start;
3fbe18d6
ZY
312 /*
313 * Deal with panel fitting options. Figure out how to stretch the
314 * image based on its aspect ratio & the current panel fitting mode.
315 */
316 panel_ratio = adjusted_mode->hdisplay * PANEL_RATIO_FACTOR /
317 adjusted_mode->vdisplay;
318 desired_ratio = mode->hdisplay * PANEL_RATIO_FACTOR /
319 mode->vdisplay;
320 /*
321 * Enable automatic panel scaling for non-native modes so that they fill
322 * the screen. Should be enabled before the pipe is enabled, according
323 * to register description and PRM.
324 * Change the value here to see the borders for debugging
325 */
326 I915_WRITE(BCLRPAT_A, 0);
327 I915_WRITE(BCLRPAT_B, 0);
328
329 switch (lvds_priv->fitting_mode) {
53bd8389 330 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
331 /*
332 * For centered modes, we have to calculate border widths &
333 * heights and modify the values programmed into the CRTC.
334 */
335 left_border = (adjusted_mode->hdisplay - mode->hdisplay) / 2;
336 right_border = left_border;
337 if (mode->hdisplay & 1)
338 right_border++;
339 top_border = (adjusted_mode->vdisplay - mode->vdisplay) / 2;
340 bottom_border = top_border;
341 if (mode->vdisplay & 1)
342 bottom_border++;
343 /* Set active & border values */
344 adjusted_mode->crtc_hdisplay = mode->hdisplay;
aa0261f2
ZY
345 /* Keep the boder be even */
346 if (right_border & 1)
347 right_border++;
348 /* use the border directly instead of border minuse one */
3fbe18d6 349 adjusted_mode->crtc_hblank_start = mode->hdisplay +
aa0261f2
ZY
350 right_border;
351 /* keep the blank width constant */
352 adjusted_mode->crtc_hblank_end =
353 adjusted_mode->crtc_hblank_start + hblank_width;
354 /* get the hsync pos relative to hblank start */
355 hsync_pos = (hblank_width - hsync_width) / 2;
356 /* keep the hsync pos be even */
357 if (hsync_pos & 1)
358 hsync_pos++;
3fbe18d6 359 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY
360 adjusted_mode->crtc_hblank_start + hsync_pos;
361 /* keep the hsync width constant */
3fbe18d6 362 adjusted_mode->crtc_hsync_end =
aa0261f2 363 adjusted_mode->crtc_hsync_start + hsync_width;
3fbe18d6 364 adjusted_mode->crtc_vdisplay = mode->vdisplay;
aa0261f2 365 /* use the border instead of border minus one */
3fbe18d6 366 adjusted_mode->crtc_vblank_start = mode->vdisplay +
aa0261f2
ZY
367 bottom_border;
368 /* keep the vblank width constant */
369 adjusted_mode->crtc_vblank_end =
370 adjusted_mode->crtc_vblank_start + vblank_width;
371 /* get the vsync start postion relative to vblank start */
372 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 373 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY
374 adjusted_mode->crtc_vblank_start + vsync_pos;
375 /* keep the vsync width constant */
3fbe18d6 376 adjusted_mode->crtc_vsync_end =
aa0261f2 377 adjusted_mode->crtc_vblank_start + vsync_width;
3fbe18d6
ZY
378 border = 1;
379 break;
380 case DRM_MODE_SCALE_ASPECT:
381 /* Scale but preserve the spect ratio */
382 pfit_control |= PFIT_ENABLE;
383 if (IS_I965G(dev)) {
384 /* 965+ is easy, it does everything in hw */
385 if (panel_ratio > desired_ratio)
386 pfit_control |= PFIT_SCALING_PILLAR;
387 else if (panel_ratio < desired_ratio)
388 pfit_control |= PFIT_SCALING_LETTER;
389 else
390 pfit_control |= PFIT_SCALING_AUTO;
391 } else {
392 /*
393 * For earlier chips we have to calculate the scaling
394 * ratio by hand and program it into the
395 * PFIT_PGM_RATIO register
396 */
397 u32 horiz_bits, vert_bits, bits = 12;
398 horiz_ratio = mode->hdisplay * PANEL_RATIO_FACTOR/
399 adjusted_mode->hdisplay;
400 vert_ratio = mode->vdisplay * PANEL_RATIO_FACTOR/
401 adjusted_mode->vdisplay;
402 horiz_scale = adjusted_mode->hdisplay *
403 PANEL_RATIO_FACTOR / mode->hdisplay;
404 vert_scale = adjusted_mode->vdisplay *
405 PANEL_RATIO_FACTOR / mode->vdisplay;
406
407 /* retain aspect ratio */
408 if (panel_ratio > desired_ratio) { /* Pillar */
409 u32 scaled_width;
410 scaled_width = mode->hdisplay * vert_scale /
411 PANEL_RATIO_FACTOR;
412 horiz_ratio = vert_ratio;
413 pfit_control |= (VERT_AUTO_SCALE |
414 VERT_INTERP_BILINEAR |
415 HORIZ_INTERP_BILINEAR);
416 /* Pillar will have left/right borders */
417 left_border = (adjusted_mode->hdisplay -
418 scaled_width) / 2;
419 right_border = left_border;
420 if (mode->hdisplay & 1) /* odd resolutions */
421 right_border++;
aa0261f2
ZY
422 /* keep the border be even */
423 if (right_border & 1)
424 right_border++;
3fbe18d6 425 adjusted_mode->crtc_hdisplay = scaled_width;
aa0261f2 426 /* use border instead of border minus one */
3fbe18d6 427 adjusted_mode->crtc_hblank_start =
aa0261f2
ZY
428 scaled_width + right_border;
429 /* keep the hblank width constant */
3fbe18d6 430 adjusted_mode->crtc_hblank_end =
aa0261f2
ZY
431 adjusted_mode->crtc_hblank_start +
432 hblank_width;
433 /*
434 * get the hsync start pos relative to
435 * hblank start
436 */
437 hsync_pos = (hblank_width - hsync_width) / 2;
438 /* keep the hsync_pos be even */
439 if (hsync_pos & 1)
440 hsync_pos++;
3fbe18d6 441 adjusted_mode->crtc_hsync_start =
aa0261f2
ZY
442 adjusted_mode->crtc_hblank_start +
443 hsync_pos;
444 /* keept hsync width constant */
3fbe18d6 445 adjusted_mode->crtc_hsync_end =
aa0261f2
ZY
446 adjusted_mode->crtc_hsync_start +
447 hsync_width;
3fbe18d6
ZY
448 border = 1;
449 } else if (panel_ratio < desired_ratio) { /* letter */
450 u32 scaled_height = mode->vdisplay *
451 horiz_scale / PANEL_RATIO_FACTOR;
452 vert_ratio = horiz_ratio;
453 pfit_control |= (HORIZ_AUTO_SCALE |
454 VERT_INTERP_BILINEAR |
455 HORIZ_INTERP_BILINEAR);
456 /* Letterbox will have top/bottom border */
457 top_border = (adjusted_mode->vdisplay -
458 scaled_height) / 2;
459 bottom_border = top_border;
460 if (mode->vdisplay & 1)
461 bottom_border++;
462 adjusted_mode->crtc_vdisplay = scaled_height;
aa0261f2 463 /* use border instead of border minus one */
3fbe18d6 464 adjusted_mode->crtc_vblank_start =
aa0261f2
ZY
465 scaled_height + bottom_border;
466 /* keep the vblank width constant */
3fbe18d6 467 adjusted_mode->crtc_vblank_end =
aa0261f2
ZY
468 adjusted_mode->crtc_vblank_start +
469 vblank_width;
470 /*
471 * get the vsync start pos relative to
472 * vblank start
473 */
474 vsync_pos = (vblank_width - vsync_width) / 2;
3fbe18d6 475 adjusted_mode->crtc_vsync_start =
aa0261f2
ZY
476 adjusted_mode->crtc_vblank_start +
477 vsync_pos;
478 /* keep the vsync width constant */
3fbe18d6 479 adjusted_mode->crtc_vsync_end =
aa0261f2
ZY
480 adjusted_mode->crtc_vsync_start +
481 vsync_width;
3fbe18d6
ZY
482 border = 1;
483 } else {
484 /* Aspects match, Let hw scale both directions */
485 pfit_control |= (VERT_AUTO_SCALE |
486 HORIZ_AUTO_SCALE |
487 VERT_INTERP_BILINEAR |
488 HORIZ_INTERP_BILINEAR);
489 }
490 horiz_bits = (1 << bits) * horiz_ratio /
491 PANEL_RATIO_FACTOR;
492 vert_bits = (1 << bits) * vert_ratio /
493 PANEL_RATIO_FACTOR;
494 pfit_pgm_ratios =
495 ((vert_bits << PFIT_VERT_SCALE_SHIFT) &
496 PFIT_VERT_SCALE_MASK) |
497 ((horiz_bits << PFIT_HORIZ_SCALE_SHIFT) &
498 PFIT_HORIZ_SCALE_MASK);
499 }
500 break;
501
502 case DRM_MODE_SCALE_FULLSCREEN:
503 /*
504 * Full scaling, even if it changes the aspect ratio.
505 * Fortunately this is all done for us in hw.
506 */
507 pfit_control |= PFIT_ENABLE;
508 if (IS_I965G(dev))
509 pfit_control |= PFIT_SCALING_AUTO;
510 else
511 pfit_control |= (VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
512 VERT_INTERP_BILINEAR |
513 HORIZ_INTERP_BILINEAR);
514 break;
515 default:
516 break;
517 }
518
519out:
520 lvds_priv->pfit_control = pfit_control;
521 lvds_priv->pfit_pgm_ratios = pfit_pgm_ratios;
79e53945
JB
522 /*
523 * XXX: It would be nice to support lower refresh rates on the
524 * panels to reduce power consumption, and perhaps match the
525 * user's requested refresh rate.
526 */
527
528 return true;
529}
530
531static void intel_lvds_prepare(struct drm_encoder *encoder)
532{
533 struct drm_device *dev = encoder->dev;
534 struct drm_i915_private *dev_priv = dev->dev_private;
541998a1 535 u32 reg;
79e53945 536
541998a1
ZW
537 if (IS_IGDNG(dev))
538 reg = BLC_PWM_CPU_CTL;
539 else
540 reg = BLC_PWM_CTL;
79e53945 541
541998a1 542 dev_priv->saveBLC_PWM_CTL = I915_READ(reg);
79e53945
JB
543 dev_priv->backlight_duty_cycle = (dev_priv->saveBLC_PWM_CTL &
544 BACKLIGHT_DUTY_CYCLE_MASK);
545
546 intel_lvds_set_power(dev, false);
547}
548
549static void intel_lvds_commit( struct drm_encoder *encoder)
550{
551 struct drm_device *dev = encoder->dev;
552 struct drm_i915_private *dev_priv = dev->dev_private;
553
554 if (dev_priv->backlight_duty_cycle == 0)
555 dev_priv->backlight_duty_cycle =
556 intel_lvds_get_max_backlight(dev);
557
558 intel_lvds_set_power(dev, true);
559}
560
561static void intel_lvds_mode_set(struct drm_encoder *encoder,
562 struct drm_display_mode *mode,
563 struct drm_display_mode *adjusted_mode)
564{
565 struct drm_device *dev = encoder->dev;
566 struct drm_i915_private *dev_priv = dev->dev_private;
3fbe18d6
ZY
567 struct intel_output *intel_output = enc_to_intel_output(encoder);
568 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
79e53945
JB
569
570 /*
571 * The LVDS pin pair will already have been turned on in the
572 * intel_crtc_mode_set since it has a large impact on the DPLL
573 * settings.
574 */
575
541998a1
ZW
576 /* No panel fitting yet, fixme */
577 if (IS_IGDNG(dev))
578 return;
579
79e53945
JB
580 /*
581 * Enable automatic panel scaling so that non-native modes fill the
582 * screen. Should be enabled before the pipe is enabled, according to
583 * register description and PRM.
584 */
3fbe18d6
ZY
585 I915_WRITE(PFIT_PGM_RATIOS, lvds_priv->pfit_pgm_ratios);
586 I915_WRITE(PFIT_CONTROL, lvds_priv->pfit_control);
79e53945
JB
587}
588
589/**
590 * Detect the LVDS connection.
591 *
b42d4c5c
JB
592 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
593 * connected and closed means disconnected. We also send hotplug events as
594 * needed, using lid status notification from the input layer.
79e53945
JB
595 */
596static enum drm_connector_status intel_lvds_detect(struct drm_connector *connector)
597{
b42d4c5c
JB
598 enum drm_connector_status status = connector_status_connected;
599
600 if (!acpi_lid_open())
601 status = connector_status_disconnected;
602
603 return status;
79e53945
JB
604}
605
606/**
607 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
608 */
609static int intel_lvds_get_modes(struct drm_connector *connector)
610{
611 struct drm_device *dev = connector->dev;
612 struct intel_output *intel_output = to_intel_output(connector);
613 struct drm_i915_private *dev_priv = dev->dev_private;
614 int ret = 0;
615
616 ret = intel_ddc_get_modes(intel_output);
617
618 if (ret)
619 return ret;
620
621 /* Didn't get an EDID, so
622 * Set wide sync ranges so we get all modes
623 * handed to valid_mode for checking
624 */
625 connector->display_info.min_vfreq = 0;
626 connector->display_info.max_vfreq = 200;
627 connector->display_info.min_hfreq = 0;
628 connector->display_info.max_hfreq = 200;
629
630 if (dev_priv->panel_fixed_mode != NULL) {
631 struct drm_display_mode *mode;
632
79e53945
JB
633 mode = drm_mode_duplicate(dev, dev_priv->panel_fixed_mode);
634 drm_mode_probed_add(connector, mode);
79e53945
JB
635
636 return 1;
637 }
638
639 return 0;
640}
641
c1c7af60
JB
642static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
643 void *unused)
644{
645 struct drm_i915_private *dev_priv =
646 container_of(nb, struct drm_i915_private, lid_notifier);
647 struct drm_device *dev = dev_priv->dev;
648
649 if (acpi_lid_open())
650 drm_helper_resume_force_mode(dev);
651
652 return NOTIFY_OK;
653}
654
79e53945
JB
655/**
656 * intel_lvds_destroy - unregister and free LVDS structures
657 * @connector: connector to free
658 *
659 * Unregister the DDC bus for this connector then free the driver private
660 * structure.
661 */
662static void intel_lvds_destroy(struct drm_connector *connector)
663{
c1c7af60 664 struct drm_device *dev = connector->dev;
79e53945 665 struct intel_output *intel_output = to_intel_output(connector);
c1c7af60 666 struct drm_i915_private *dev_priv = dev->dev_private;
79e53945
JB
667
668 if (intel_output->ddc_bus)
669 intel_i2c_destroy(intel_output->ddc_bus);
c1c7af60
JB
670 if (dev_priv->lid_notifier.notifier_call)
671 acpi_lid_notifier_unregister(&dev_priv->lid_notifier);
79e53945
JB
672 drm_sysfs_connector_remove(connector);
673 drm_connector_cleanup(connector);
674 kfree(connector);
675}
676
335041ed
JB
677static int intel_lvds_set_property(struct drm_connector *connector,
678 struct drm_property *property,
679 uint64_t value)
680{
3fbe18d6
ZY
681 struct drm_device *dev = connector->dev;
682 struct intel_output *intel_output =
683 to_intel_output(connector);
684
685 if (property == dev->mode_config.scaling_mode_property &&
686 connector->encoder) {
687 struct drm_crtc *crtc = connector->encoder->crtc;
688 struct intel_lvds_priv *lvds_priv = intel_output->dev_priv;
53bd8389
JB
689 if (value == DRM_MODE_SCALE_NONE) {
690 DRM_DEBUG_KMS("no scaling not supported\n");
3fbe18d6
ZY
691 return 0;
692 }
693 if (lvds_priv->fitting_mode == value) {
694 /* the LVDS scaling property is not changed */
695 return 0;
696 }
697 lvds_priv->fitting_mode = value;
698 if (crtc && crtc->enabled) {
699 /*
700 * If the CRTC is enabled, the display will be changed
701 * according to the new panel fitting mode.
702 */
703 drm_crtc_helper_set_mode(crtc, &crtc->mode,
704 crtc->x, crtc->y, crtc->fb);
705 }
706 }
707
335041ed
JB
708 return 0;
709}
710
79e53945
JB
711static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
712 .dpms = intel_lvds_dpms,
713 .mode_fixup = intel_lvds_mode_fixup,
714 .prepare = intel_lvds_prepare,
715 .mode_set = intel_lvds_mode_set,
716 .commit = intel_lvds_commit,
717};
718
719static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
720 .get_modes = intel_lvds_get_modes,
721 .mode_valid = intel_lvds_mode_valid,
722 .best_encoder = intel_best_encoder,
723};
724
725static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c9fb15f6 726 .dpms = drm_helper_connector_dpms,
79e53945
JB
727 .save = intel_lvds_save,
728 .restore = intel_lvds_restore,
729 .detect = intel_lvds_detect,
730 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 731 .set_property = intel_lvds_set_property,
79e53945
JB
732 .destroy = intel_lvds_destroy,
733};
734
735
736static void intel_lvds_enc_destroy(struct drm_encoder *encoder)
737{
738 drm_encoder_cleanup(encoder);
739}
740
741static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
742 .destroy = intel_lvds_enc_destroy,
743};
744
425d244c
JW
745static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
746{
8a4c47f3 747 DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
748 return 1;
749}
79e53945 750
425d244c 751/* These systems claim to have LVDS, but really don't */
93c05f22 752static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
753 {
754 .callback = intel_no_lvds_dmi_callback,
755 .ident = "Apple Mac Mini (Core series)",
756 .matches = {
98acd46f 757 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
758 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
759 },
760 },
761 {
762 .callback = intel_no_lvds_dmi_callback,
763 .ident = "Apple Mac Mini (Core 2 series)",
764 .matches = {
98acd46f 765 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
766 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
767 },
768 },
769 {
770 .callback = intel_no_lvds_dmi_callback,
771 .ident = "MSI IM-945GSE-A",
772 .matches = {
773 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
774 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
775 },
776 },
777 {
778 .callback = intel_no_lvds_dmi_callback,
779 .ident = "Dell Studio Hybrid",
780 .matches = {
781 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
782 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
783 },
784 },
70aa96ca
JW
785 {
786 .callback = intel_no_lvds_dmi_callback,
787 .ident = "AOpen Mini PC",
788 .matches = {
789 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
790 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
791 },
792 },
ed8c754b
TV
793 {
794 .callback = intel_no_lvds_dmi_callback,
795 .ident = "AOpen Mini PC MP915",
796 .matches = {
797 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
798 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
799 },
800 },
fa0864b2
MC
801 {
802 .callback = intel_no_lvds_dmi_callback,
803 .ident = "Aopen i945GTt-VFA",
804 .matches = {
805 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
806 },
807 },
425d244c
JW
808
809 { } /* terminating entry */
810};
79e53945 811
e99da35f
ZY
812#ifdef CONFIG_ACPI
813/*
814 * check_lid_device -- check whether @handle is an ACPI LID device.
815 * @handle: ACPI device handle
816 * @level : depth in the ACPI namespace tree
817 * @context: the number of LID device when we find the device
818 * @rv: a return value to fill if desired (Not use)
819 */
820static acpi_status
821check_lid_device(acpi_handle handle, u32 level, void *context,
822 void **return_value)
823{
824 struct acpi_device *acpi_dev;
825 int *lid_present = context;
826
827 acpi_dev = NULL;
828 /* Get the acpi device for device handle */
829 if (acpi_bus_get_device(handle, &acpi_dev) || !acpi_dev) {
830 /* If there is no ACPI device for handle, return */
831 return AE_OK;
832 }
833
834 if (!strncmp(acpi_device_hid(acpi_dev), "PNP0C0D", 7))
835 *lid_present = 1;
836
837 return AE_OK;
838}
839
840/**
841 * check whether there exists the ACPI LID device by enumerating the ACPI
842 * device tree.
843 */
844static int intel_lid_present(void)
845{
846 int lid_present = 0;
847
848 if (acpi_disabled) {
849 /* If ACPI is disabled, there is no ACPI device tree to
850 * check, so assume the LID device would have been present.
851 */
852 return 1;
853 }
854
855 acpi_walk_namespace(ACPI_TYPE_DEVICE, ACPI_ROOT_OBJECT,
856 ACPI_UINT32_MAX,
857 check_lid_device, &lid_present, NULL);
858
859 return lid_present;
860}
861#else
862static int intel_lid_present(void)
863{
864 /* In the absence of ACPI built in, assume that the LID device would
865 * have been present.
866 */
867 return 1;
868}
869#endif
870
79e53945
JB
871/**
872 * intel_lvds_init - setup LVDS connectors on this device
873 * @dev: drm device
874 *
875 * Create the connector, register the LVDS DDC bus, and try to figure out what
876 * modes we can display on the LVDS panel (if present).
877 */
878void intel_lvds_init(struct drm_device *dev)
879{
880 struct drm_i915_private *dev_priv = dev->dev_private;
881 struct intel_output *intel_output;
882 struct drm_connector *connector;
883 struct drm_encoder *encoder;
884 struct drm_display_mode *scan; /* *modes, *bios_mode; */
885 struct drm_crtc *crtc;
3fbe18d6 886 struct intel_lvds_priv *lvds_priv;
79e53945 887 u32 lvds;
541998a1 888 int pipe, gpio = GPIOC;
79e53945 889
425d244c
JW
890 /* Skip init on machines we know falsely report LVDS */
891 if (dmi_check_system(intel_no_lvds))
565dcd46 892 return;
565dcd46 893
e99da35f
ZY
894 /* Assume that any device without an ACPI LID device also doesn't
895 * have an integrated LVDS. We would be better off parsing the BIOS
896 * to get a reliable indicator, but that code isn't written yet.
897 *
898 * In the case of all-in-one desktops using LVDS that we've seen,
899 * they're using SDVO LVDS.
900 */
901 if (!intel_lid_present())
902 return;
903
541998a1
ZW
904 if (IS_IGDNG(dev)) {
905 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
906 return;
32f9d658
ZW
907 if (dev_priv->edp_support) {
908 DRM_DEBUG("disable LVDS for eDP support\n");
909 return;
910 }
541998a1
ZW
911 gpio = PCH_GPIOC;
912 }
913
3fbe18d6
ZY
914 intel_output = kzalloc(sizeof(struct intel_output) +
915 sizeof(struct intel_lvds_priv), GFP_KERNEL);
79e53945
JB
916 if (!intel_output) {
917 return;
918 }
919
920 connector = &intel_output->base;
921 encoder = &intel_output->enc;
922 drm_connector_init(dev, &intel_output->base, &intel_lvds_connector_funcs,
923 DRM_MODE_CONNECTOR_LVDS);
924
925 drm_encoder_init(dev, &intel_output->enc, &intel_lvds_enc_funcs,
926 DRM_MODE_ENCODER_LVDS);
927
928 drm_mode_connector_attach_encoder(&intel_output->base, &intel_output->enc);
929 intel_output->type = INTEL_OUTPUT_LVDS;
930
f8aed700
ML
931 intel_output->clone_mask = (1 << INTEL_LVDS_CLONE_BIT);
932 intel_output->crtc_mask = (1 << 1);
79e53945
JB
933 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
934 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
935 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
936 connector->interlace_allowed = false;
937 connector->doublescan_allowed = false;
938
3fbe18d6
ZY
939 lvds_priv = (struct intel_lvds_priv *)(intel_output + 1);
940 intel_output->dev_priv = lvds_priv;
941 /* create the scaling mode property */
942 drm_mode_create_scaling_mode_property(dev);
943 /*
944 * the initial panel fitting mode will be FULL_SCREEN.
945 */
79e53945 946
3fbe18d6
ZY
947 drm_connector_attach_property(&intel_output->base,
948 dev->mode_config.scaling_mode_property,
949 DRM_MODE_SCALE_FULLSCREEN);
950 lvds_priv->fitting_mode = DRM_MODE_SCALE_FULLSCREEN;
79e53945
JB
951 /*
952 * LVDS discovery:
953 * 1) check for EDID on DDC
954 * 2) check for VBT data
955 * 3) check to see if LVDS is already on
956 * if none of the above, no panel
957 * 4) make sure lid is open
958 * if closed, act like it's not there for now
959 */
960
961 /* Set up the DDC bus. */
541998a1 962 intel_output->ddc_bus = intel_i2c_create(dev, gpio, "LVDSDDC_C");
79e53945
JB
963 if (!intel_output->ddc_bus) {
964 dev_printk(KERN_ERR, &dev->pdev->dev, "DDC bus registration "
965 "failed.\n");
966 goto failed;
967 }
968
969 /*
970 * Attempt to get the fixed panel mode from DDC. Assume that the
971 * preferred mode is the right one.
972 */
973 intel_ddc_get_modes(intel_output);
974
975 list_for_each_entry(scan, &connector->probed_modes, head) {
976 mutex_lock(&dev->mode_config.mutex);
977 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
978 dev_priv->panel_fixed_mode =
979 drm_mode_duplicate(dev, scan);
980 mutex_unlock(&dev->mode_config.mutex);
565dcd46 981 goto out;
79e53945
JB
982 }
983 mutex_unlock(&dev->mode_config.mutex);
984 }
985
986 /* Failed to get EDID, what about VBT? */
88631706 987 if (dev_priv->lfp_lvds_vbt_mode) {
79e53945
JB
988 mutex_lock(&dev->mode_config.mutex);
989 dev_priv->panel_fixed_mode =
88631706 990 drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
79e53945 991 mutex_unlock(&dev->mode_config.mutex);
e285f3cd
JB
992 if (dev_priv->panel_fixed_mode) {
993 dev_priv->panel_fixed_mode->type |=
994 DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
995 goto out;
996 }
79e53945
JB
997 }
998
999 /*
1000 * If we didn't get EDID, try checking if the panel is already turned
1001 * on. If so, assume that whatever is currently programmed is the
1002 * correct mode.
1003 */
541998a1
ZW
1004
1005 /* IGDNG: FIXME if still fail, not try pipe mode now */
1006 if (IS_IGDNG(dev))
1007 goto failed;
1008
79e53945
JB
1009 lvds = I915_READ(LVDS);
1010 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
1011 crtc = intel_get_crtc_from_pipe(dev, pipe);
1012
1013 if (crtc && (lvds & LVDS_PORT_EN)) {
1014 dev_priv->panel_fixed_mode = intel_crtc_mode_get(dev, crtc);
1015 if (dev_priv->panel_fixed_mode) {
1016 dev_priv->panel_fixed_mode->type |=
1017 DRM_MODE_TYPE_PREFERRED;
565dcd46 1018 goto out;
79e53945
JB
1019 }
1020 }
1021
1022 /* If we still don't have a mode after all that, give up. */
1023 if (!dev_priv->panel_fixed_mode)
1024 goto failed;
1025
79e53945 1026out:
541998a1
ZW
1027 if (IS_IGDNG(dev)) {
1028 u32 pwm;
1029 /* make sure PWM is enabled */
1030 pwm = I915_READ(BLC_PWM_CPU_CTL2);
1031 pwm |= (PWM_ENABLE | PWM_PIPE_B);
1032 I915_WRITE(BLC_PWM_CPU_CTL2, pwm);
1033
1034 pwm = I915_READ(BLC_PWM_PCH_CTL1);
1035 pwm |= PWM_PCH_ENABLE;
1036 I915_WRITE(BLC_PWM_PCH_CTL1, pwm);
1037 }
c1c7af60
JB
1038 dev_priv->lid_notifier.notifier_call = intel_lid_notify;
1039 if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) {
1040 DRM_DEBUG("lid notifier registration failed\n");
1041 dev_priv->lid_notifier.notifier_call = NULL;
1042 }
79e53945
JB
1043 drm_sysfs_connector_add(connector);
1044 return;
1045
1046failed:
8a4c47f3 1047 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945
JB
1048 if (intel_output->ddc_bus)
1049 intel_i2c_destroy(intel_output->ddc_bus);
1050 drm_connector_cleanup(connector);
3fbe18d6 1051 kfree(intel_output);
79e53945 1052}