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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
760285e7 DH |
34 | #include <drm/drmP.h> |
35 | #include <drm/drm_crtc.h> | |
36 | #include <drm/drm_edid.h> | |
79e53945 | 37 | #include "intel_drv.h" |
760285e7 | 38 | #include <drm/i915_drm.h> |
79e53945 | 39 | #include "i915_drv.h" |
e99da35f | 40 | #include <linux/acpi.h> |
79e53945 | 41 | |
3fbe18d6 | 42 | /* Private structure for the integrated LVDS support */ |
c7362c4d JN |
43 | struct intel_lvds_connector { |
44 | struct intel_connector base; | |
788319d4 | 45 | |
db1740a0 | 46 | struct notifier_block lid_notifier; |
c7362c4d JN |
47 | }; |
48 | ||
29b99b48 | 49 | struct intel_lvds_encoder { |
ea5b213a | 50 | struct intel_encoder base; |
788319d4 | 51 | |
13c7d870 | 52 | bool is_dual_link; |
7dec0606 | 53 | u32 reg; |
788319d4 | 54 | |
62165e0d | 55 | struct intel_lvds_connector *attached_connector; |
3fbe18d6 ZY |
56 | }; |
57 | ||
29b99b48 | 58 | static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder) |
ea5b213a | 59 | { |
29b99b48 | 60 | return container_of(encoder, struct intel_lvds_encoder, base.base); |
ea5b213a CW |
61 | } |
62 | ||
c7362c4d | 63 | static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector) |
788319d4 | 64 | { |
c7362c4d | 65 | return container_of(connector, struct intel_lvds_connector, base.base); |
788319d4 CW |
66 | } |
67 | ||
b1dc332c DV |
68 | static bool intel_lvds_get_hw_state(struct intel_encoder *encoder, |
69 | enum pipe *pipe) | |
70 | { | |
71 | struct drm_device *dev = encoder->base.dev; | |
72 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7dec0606 DV |
73 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
74 | u32 tmp; | |
b1dc332c | 75 | |
7dec0606 | 76 | tmp = I915_READ(lvds_encoder->reg); |
b1dc332c DV |
77 | |
78 | if (!(tmp & LVDS_PORT_EN)) | |
79 | return false; | |
80 | ||
81 | if (HAS_PCH_CPT(dev)) | |
82 | *pipe = PORT_TO_PIPE_CPT(tmp); | |
83 | else | |
84 | *pipe = PORT_TO_PIPE(tmp); | |
85 | ||
86 | return true; | |
87 | } | |
88 | ||
045ac3b5 JB |
89 | static void intel_lvds_get_config(struct intel_encoder *encoder, |
90 | struct intel_crtc_config *pipe_config) | |
91 | { | |
92 | struct drm_device *dev = encoder->base.dev; | |
93 | struct drm_i915_private *dev_priv = dev->dev_private; | |
94 | u32 lvds_reg, tmp, flags = 0; | |
18442d08 | 95 | int dotclock; |
045ac3b5 JB |
96 | |
97 | if (HAS_PCH_SPLIT(dev)) | |
98 | lvds_reg = PCH_LVDS; | |
99 | else | |
100 | lvds_reg = LVDS; | |
101 | ||
102 | tmp = I915_READ(lvds_reg); | |
103 | if (tmp & LVDS_HSYNC_POLARITY) | |
104 | flags |= DRM_MODE_FLAG_NHSYNC; | |
105 | else | |
106 | flags |= DRM_MODE_FLAG_PHSYNC; | |
107 | if (tmp & LVDS_VSYNC_POLARITY) | |
108 | flags |= DRM_MODE_FLAG_NVSYNC; | |
109 | else | |
110 | flags |= DRM_MODE_FLAG_PVSYNC; | |
111 | ||
112 | pipe_config->adjusted_mode.flags |= flags; | |
06922821 DV |
113 | |
114 | /* gen2/3 store dither state in pfit control, needs to match */ | |
115 | if (INTEL_INFO(dev)->gen < 4) { | |
116 | tmp = I915_READ(PFIT_CONTROL); | |
117 | ||
118 | pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE; | |
119 | } | |
18442d08 VS |
120 | |
121 | dotclock = pipe_config->port_clock; | |
122 | ||
123 | if (HAS_PCH_SPLIT(dev_priv->dev)) | |
124 | ironlake_check_encoder_dotclock(pipe_config, dotclock); | |
125 | ||
241bfc38 | 126 | pipe_config->adjusted_mode.crtc_clock = dotclock; |
045ac3b5 JB |
127 | } |
128 | ||
fc683091 DV |
129 | /* The LVDS pin pair needs to be on before the DPLLs are enabled. |
130 | * This is an exception to the general rule that mode_set doesn't turn | |
131 | * things on. | |
132 | */ | |
f6736a1a | 133 | static void intel_pre_enable_lvds(struct intel_encoder *encoder) |
fc683091 DV |
134 | { |
135 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); | |
136 | struct drm_device *dev = encoder->base.dev; | |
137 | struct drm_i915_private *dev_priv = dev->dev_private; | |
55607e8a | 138 | struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc); |
4c6df4b4 VS |
139 | const struct drm_display_mode *adjusted_mode = |
140 | &crtc->config.adjusted_mode; | |
55607e8a | 141 | int pipe = crtc->pipe; |
fc683091 DV |
142 | u32 temp; |
143 | ||
55607e8a DV |
144 | if (HAS_PCH_SPLIT(dev)) { |
145 | assert_fdi_rx_pll_disabled(dev_priv, pipe); | |
146 | assert_shared_dpll_disabled(dev_priv, | |
147 | intel_crtc_to_shared_dpll(crtc)); | |
148 | } else { | |
149 | assert_pll_disabled(dev_priv, pipe); | |
150 | } | |
151 | ||
fc683091 DV |
152 | temp = I915_READ(lvds_encoder->reg); |
153 | temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP; | |
62810e5a DV |
154 | |
155 | if (HAS_PCH_CPT(dev)) { | |
156 | temp &= ~PORT_TRANS_SEL_MASK; | |
157 | temp |= PORT_TRANS_SEL_CPT(pipe); | |
fc683091 | 158 | } else { |
62810e5a DV |
159 | if (pipe == 1) { |
160 | temp |= LVDS_PIPEB_SELECT; | |
161 | } else { | |
162 | temp &= ~LVDS_PIPEB_SELECT; | |
163 | } | |
fc683091 | 164 | } |
62810e5a | 165 | |
fc683091 | 166 | /* set the corresponsding LVDS_BORDER bit */ |
2fa2fe9a | 167 | temp &= ~LVDS_BORDER_ENABLE; |
55607e8a | 168 | temp |= crtc->config.gmch_pfit.lvds_border_bits; |
fc683091 DV |
169 | /* Set the B0-B3 data pairs corresponding to whether we're going to |
170 | * set the DPLLs for dual-channel mode or not. | |
171 | */ | |
172 | if (lvds_encoder->is_dual_link) | |
173 | temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP; | |
174 | else | |
175 | temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP); | |
176 | ||
177 | /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP) | |
178 | * appropriately here, but we need to look more thoroughly into how | |
179 | * panels behave in the two modes. | |
180 | */ | |
62810e5a DV |
181 | |
182 | /* Set the dithering flag on LVDS as needed, note that there is no | |
183 | * special lvds dither control bit on pch-split platforms, dithering is | |
184 | * only controlled through the PIPECONF reg. */ | |
185 | if (INTEL_INFO(dev)->gen == 4) { | |
d8b32247 DV |
186 | /* Bspec wording suggests that LVDS port dithering only exists |
187 | * for 18bpp panels. */ | |
55607e8a | 188 | if (crtc->config.dither && crtc->config.pipe_bpp == 18) |
fc683091 DV |
189 | temp |= LVDS_ENABLE_DITHER; |
190 | else | |
191 | temp &= ~LVDS_ENABLE_DITHER; | |
192 | } | |
193 | temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY); | |
4c6df4b4 | 194 | if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC) |
fc683091 | 195 | temp |= LVDS_HSYNC_POLARITY; |
4c6df4b4 | 196 | if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC) |
fc683091 DV |
197 | temp |= LVDS_VSYNC_POLARITY; |
198 | ||
199 | I915_WRITE(lvds_encoder->reg, temp); | |
200 | } | |
201 | ||
79e53945 JB |
202 | /** |
203 | * Sets the power state for the panel. | |
204 | */ | |
c22834ec | 205 | static void intel_enable_lvds(struct intel_encoder *encoder) |
79e53945 | 206 | { |
c22834ec | 207 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 208 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
209 | struct intel_connector *intel_connector = |
210 | &lvds_encoder->attached_connector->base; | |
79e53945 | 211 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 212 | u32 ctl_reg, stat_reg; |
541998a1 | 213 | |
c619eed4 | 214 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 215 | ctl_reg = PCH_PP_CONTROL; |
de842eff | 216 | stat_reg = PCH_PP_STATUS; |
541998a1 ZW |
217 | } else { |
218 | ctl_reg = PP_CONTROL; | |
de842eff | 219 | stat_reg = PP_STATUS; |
541998a1 | 220 | } |
79e53945 | 221 | |
7dec0606 | 222 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN); |
e9e331a8 | 223 | |
2a1292fd | 224 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
7dec0606 | 225 | POSTING_READ(lvds_encoder->reg); |
de842eff KP |
226 | if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000)) |
227 | DRM_ERROR("timed out waiting for panel to power on\n"); | |
2a1292fd | 228 | |
752aa88a | 229 | intel_panel_enable_backlight(intel_connector); |
2a1292fd CW |
230 | } |
231 | ||
c22834ec | 232 | static void intel_disable_lvds(struct intel_encoder *encoder) |
2a1292fd | 233 | { |
c22834ec | 234 | struct drm_device *dev = encoder->base.dev; |
29b99b48 | 235 | struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base); |
752aa88a JB |
236 | struct intel_connector *intel_connector = |
237 | &lvds_encoder->attached_connector->base; | |
2a1292fd | 238 | struct drm_i915_private *dev_priv = dev->dev_private; |
7dec0606 | 239 | u32 ctl_reg, stat_reg; |
2a1292fd CW |
240 | |
241 | if (HAS_PCH_SPLIT(dev)) { | |
242 | ctl_reg = PCH_PP_CONTROL; | |
de842eff | 243 | stat_reg = PCH_PP_STATUS; |
2a1292fd CW |
244 | } else { |
245 | ctl_reg = PP_CONTROL; | |
de842eff | 246 | stat_reg = PP_STATUS; |
2a1292fd CW |
247 | } |
248 | ||
752aa88a | 249 | intel_panel_disable_backlight(intel_connector); |
2a1292fd CW |
250 | |
251 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); | |
de842eff KP |
252 | if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000)) |
253 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
2a1292fd | 254 | |
7dec0606 DV |
255 | I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN); |
256 | POSTING_READ(lvds_encoder->reg); | |
79e53945 JB |
257 | } |
258 | ||
c19de8eb DL |
259 | static enum drm_mode_status |
260 | intel_lvds_mode_valid(struct drm_connector *connector, | |
261 | struct drm_display_mode *mode) | |
79e53945 | 262 | { |
dd06f90e JN |
263 | struct intel_connector *intel_connector = to_intel_connector(connector); |
264 | struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode; | |
79e53945 | 265 | |
788319d4 CW |
266 | if (mode->hdisplay > fixed_mode->hdisplay) |
267 | return MODE_PANEL; | |
268 | if (mode->vdisplay > fixed_mode->vdisplay) | |
269 | return MODE_PANEL; | |
79e53945 JB |
270 | |
271 | return MODE_OK; | |
272 | } | |
273 | ||
7ae89233 DV |
274 | static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder, |
275 | struct intel_crtc_config *pipe_config) | |
79e53945 | 276 | { |
7ae89233 | 277 | struct drm_device *dev = intel_encoder->base.dev; |
79e53945 | 278 | struct drm_i915_private *dev_priv = dev->dev_private; |
7ae89233 DV |
279 | struct intel_lvds_encoder *lvds_encoder = |
280 | to_lvds_encoder(&intel_encoder->base); | |
4d891523 JN |
281 | struct intel_connector *intel_connector = |
282 | &lvds_encoder->attached_connector->base; | |
7ae89233 | 283 | struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode; |
29b99b48 | 284 | struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc; |
4e53c2e0 | 285 | unsigned int lvds_bpp; |
79e53945 JB |
286 | |
287 | /* Should never happen!! */ | |
a6c45cf0 | 288 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 289 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
290 | return false; |
291 | } | |
292 | ||
4e53c2e0 DV |
293 | if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) == |
294 | LVDS_A3_POWER_UP) | |
295 | lvds_bpp = 8*3; | |
296 | else | |
297 | lvds_bpp = 6*3; | |
298 | ||
e29c22c0 | 299 | if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) { |
4e53c2e0 DV |
300 | DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n", |
301 | pipe_config->pipe_bpp, lvds_bpp); | |
302 | pipe_config->pipe_bpp = lvds_bpp; | |
303 | } | |
d8b32247 | 304 | |
79e53945 | 305 | /* |
71677043 | 306 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
307 | * to the adjusted mode. The CRTC will be set up for this mode, |
308 | * with the panel scaling set up to source from the H/VDisplay | |
309 | * of the original mode. | |
310 | */ | |
4d891523 | 311 | intel_fixed_panel_mode(intel_connector->panel.fixed_mode, |
dd06f90e | 312 | adjusted_mode); |
1d8e1c75 CW |
313 | |
314 | if (HAS_PCH_SPLIT(dev)) { | |
5bfe2ac0 DV |
315 | pipe_config->has_pch_encoder = true; |
316 | ||
b074cec8 JB |
317 | intel_pch_panel_fitting(intel_crtc, pipe_config, |
318 | intel_connector->panel.fitting_mode); | |
2dd24552 JB |
319 | } else { |
320 | intel_gmch_panel_fitting(intel_crtc, pipe_config, | |
321 | intel_connector->panel.fitting_mode); | |
79e53945 | 322 | |
21d8a475 | 323 | } |
f9bef081 | 324 | |
79e53945 JB |
325 | /* |
326 | * XXX: It would be nice to support lower refresh rates on the | |
327 | * panels to reduce power consumption, and perhaps match the | |
328 | * user's requested refresh rate. | |
329 | */ | |
330 | ||
331 | return true; | |
332 | } | |
333 | ||
66df24d9 | 334 | static void intel_lvds_mode_set(struct intel_encoder *encoder) |
79e53945 | 335 | { |
79e53945 | 336 | /* |
66df24d9 DV |
337 | * We don't do anything here, the LVDS port is fully set up in the pre |
338 | * enable hook - the ordering constraints for enabling the lvds port vs. | |
339 | * enabling the display pll are too strict. | |
79e53945 | 340 | */ |
79e53945 JB |
341 | } |
342 | ||
343 | /** | |
344 | * Detect the LVDS connection. | |
345 | * | |
b42d4c5c JB |
346 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
347 | * connected and closed means disconnected. We also send hotplug events as | |
348 | * needed, using lid status notification from the input layer. | |
79e53945 | 349 | */ |
7b334fcb | 350 | static enum drm_connector_status |
930a9e28 | 351 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 352 | { |
7b9c5abe | 353 | struct drm_device *dev = connector->dev; |
6ee3b5a1 | 354 | enum drm_connector_status status; |
b42d4c5c | 355 | |
164c8598 CW |
356 | DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n", |
357 | connector->base.id, drm_get_connector_name(connector)); | |
358 | ||
fe16d949 CW |
359 | status = intel_panel_detect(dev); |
360 | if (status != connector_status_unknown) | |
361 | return status; | |
01fe9dbd | 362 | |
6ee3b5a1 | 363 | return connector_status_connected; |
79e53945 JB |
364 | } |
365 | ||
366 | /** | |
367 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
368 | */ | |
369 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
370 | { | |
62165e0d | 371 | struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector); |
79e53945 | 372 | struct drm_device *dev = connector->dev; |
788319d4 | 373 | struct drm_display_mode *mode; |
79e53945 | 374 | |
9cd300e0 | 375 | /* use cached edid if we have one */ |
2aa4f099 | 376 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
9cd300e0 | 377 | return drm_add_edid_modes(connector, lvds_connector->base.edid); |
79e53945 | 378 | |
dd06f90e | 379 | mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode); |
311bd68e | 380 | if (mode == NULL) |
788319d4 | 381 | return 0; |
79e53945 | 382 | |
788319d4 CW |
383 | drm_mode_probed_add(connector, mode); |
384 | return 1; | |
79e53945 JB |
385 | } |
386 | ||
0544edfd TB |
387 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
388 | { | |
bc0daf48 | 389 | DRM_INFO("Skipping forced modeset for %s\n", id->ident); |
0544edfd TB |
390 | return 1; |
391 | } | |
392 | ||
393 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
394 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
395 | { | |
396 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
397 | .ident = "Toshiba Tecra A11", | |
398 | .matches = { | |
399 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
400 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
401 | }, | |
402 | }, | |
403 | ||
404 | { } /* terminating entry */ | |
405 | }; | |
406 | ||
c9354c85 | 407 | /* |
b8efb17b ZR |
408 | * Lid events. Note the use of 'modeset': |
409 | * - we set it to MODESET_ON_LID_OPEN on lid close, | |
410 | * and set it to MODESET_DONE on open | |
c9354c85 | 411 | * - we use it as a "only once" bit (ie we ignore |
b8efb17b ZR |
412 | * duplicate events where it was already properly set) |
413 | * - the suspend/resume paths will set it to | |
414 | * MODESET_SUSPENDED and ignore the lid open event, | |
415 | * because they restore the mode ("lid open"). | |
c9354c85 | 416 | */ |
c1c7af60 JB |
417 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
418 | void *unused) | |
419 | { | |
db1740a0 JN |
420 | struct intel_lvds_connector *lvds_connector = |
421 | container_of(nb, struct intel_lvds_connector, lid_notifier); | |
422 | struct drm_connector *connector = &lvds_connector->base.base; | |
423 | struct drm_device *dev = connector->dev; | |
424 | struct drm_i915_private *dev_priv = dev->dev_private; | |
c1c7af60 | 425 | |
2fb4e61d AW |
426 | if (dev->switch_power_state != DRM_SWITCH_POWER_ON) |
427 | return NOTIFY_OK; | |
428 | ||
b8efb17b ZR |
429 | mutex_lock(&dev_priv->modeset_restore_lock); |
430 | if (dev_priv->modeset_restore == MODESET_SUSPENDED) | |
431 | goto exit; | |
a2565377 ZY |
432 | /* |
433 | * check and update the status of LVDS connector after receiving | |
434 | * the LID nofication event. | |
435 | */ | |
db1740a0 | 436 | connector->status = connector->funcs->detect(connector, false); |
7b334fcb | 437 | |
0544edfd TB |
438 | /* Don't force modeset on machines where it causes a GPU lockup */ |
439 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
b8efb17b | 440 | goto exit; |
c9354c85 | 441 | if (!acpi_lid_open()) { |
b8efb17b ZR |
442 | /* do modeset on next lid open event */ |
443 | dev_priv->modeset_restore = MODESET_ON_LID_OPEN; | |
444 | goto exit; | |
06891e27 | 445 | } |
c1c7af60 | 446 | |
b8efb17b ZR |
447 | if (dev_priv->modeset_restore == MODESET_DONE) |
448 | goto exit; | |
c9354c85 | 449 | |
a0e99e68 | 450 | drm_modeset_lock_all(dev); |
45e2b5f6 | 451 | intel_modeset_setup_hw_state(dev, true); |
a0e99e68 | 452 | drm_modeset_unlock_all(dev); |
06324194 | 453 | |
b8efb17b ZR |
454 | dev_priv->modeset_restore = MODESET_DONE; |
455 | ||
456 | exit: | |
457 | mutex_unlock(&dev_priv->modeset_restore_lock); | |
c1c7af60 JB |
458 | return NOTIFY_OK; |
459 | } | |
460 | ||
79e53945 JB |
461 | /** |
462 | * intel_lvds_destroy - unregister and free LVDS structures | |
463 | * @connector: connector to free | |
464 | * | |
465 | * Unregister the DDC bus for this connector then free the driver private | |
466 | * structure. | |
467 | */ | |
468 | static void intel_lvds_destroy(struct drm_connector *connector) | |
469 | { | |
db1740a0 JN |
470 | struct intel_lvds_connector *lvds_connector = |
471 | to_lvds_connector(connector); | |
79e53945 | 472 | |
db1740a0 JN |
473 | if (lvds_connector->lid_notifier.notifier_call) |
474 | acpi_lid_notifier_unregister(&lvds_connector->lid_notifier); | |
79e53945 | 475 | |
9cd300e0 JN |
476 | if (!IS_ERR_OR_NULL(lvds_connector->base.edid)) |
477 | kfree(lvds_connector->base.edid); | |
478 | ||
1d508706 | 479 | intel_panel_fini(&lvds_connector->base.panel); |
aaa6fd2a | 480 | |
79e53945 JB |
481 | drm_connector_cleanup(connector); |
482 | kfree(connector); | |
483 | } | |
484 | ||
335041ed JB |
485 | static int intel_lvds_set_property(struct drm_connector *connector, |
486 | struct drm_property *property, | |
487 | uint64_t value) | |
488 | { | |
4d891523 | 489 | struct intel_connector *intel_connector = to_intel_connector(connector); |
3fbe18d6 | 490 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 491 | |
788319d4 | 492 | if (property == dev->mode_config.scaling_mode_property) { |
62165e0d | 493 | struct drm_crtc *crtc; |
bb8a3560 | 494 | |
53bd8389 JB |
495 | if (value == DRM_MODE_SCALE_NONE) { |
496 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 497 | return -EINVAL; |
3fbe18d6 | 498 | } |
788319d4 | 499 | |
4d891523 | 500 | if (intel_connector->panel.fitting_mode == value) { |
3fbe18d6 ZY |
501 | /* the LVDS scaling property is not changed */ |
502 | return 0; | |
503 | } | |
4d891523 | 504 | intel_connector->panel.fitting_mode = value; |
62165e0d JN |
505 | |
506 | crtc = intel_attached_encoder(connector)->base.crtc; | |
3fbe18d6 ZY |
507 | if (crtc && crtc->enabled) { |
508 | /* | |
509 | * If the CRTC is enabled, the display will be changed | |
510 | * according to the new panel fitting mode. | |
511 | */ | |
c0c36b94 | 512 | intel_crtc_restore_mode(crtc); |
3fbe18d6 ZY |
513 | } |
514 | } | |
515 | ||
335041ed JB |
516 | return 0; |
517 | } | |
518 | ||
79e53945 JB |
519 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { |
520 | .get_modes = intel_lvds_get_modes, | |
521 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 522 | .best_encoder = intel_best_encoder, |
79e53945 JB |
523 | }; |
524 | ||
525 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c22834ec | 526 | .dpms = intel_connector_dpms, |
79e53945 JB |
527 | .detect = intel_lvds_detect, |
528 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 529 | .set_property = intel_lvds_set_property, |
79e53945 JB |
530 | .destroy = intel_lvds_destroy, |
531 | }; | |
532 | ||
79e53945 | 533 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 534 | .destroy = intel_encoder_destroy, |
79e53945 JB |
535 | }; |
536 | ||
425d244c JW |
537 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
538 | { | |
bc0daf48 | 539 | DRM_INFO("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
540 | return 1; |
541 | } | |
79e53945 | 542 | |
425d244c | 543 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 544 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
545 | { |
546 | .callback = intel_no_lvds_dmi_callback, | |
547 | .ident = "Apple Mac Mini (Core series)", | |
548 | .matches = { | |
98acd46f | 549 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
550 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
551 | }, | |
552 | }, | |
553 | { | |
554 | .callback = intel_no_lvds_dmi_callback, | |
555 | .ident = "Apple Mac Mini (Core 2 series)", | |
556 | .matches = { | |
98acd46f | 557 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
558 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
559 | }, | |
560 | }, | |
561 | { | |
562 | .callback = intel_no_lvds_dmi_callback, | |
563 | .ident = "MSI IM-945GSE-A", | |
564 | .matches = { | |
565 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
566 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
567 | }, | |
568 | }, | |
569 | { | |
570 | .callback = intel_no_lvds_dmi_callback, | |
571 | .ident = "Dell Studio Hybrid", | |
572 | .matches = { | |
573 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
574 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
575 | }, | |
576 | }, | |
70aa96ca JW |
577 | { |
578 | .callback = intel_no_lvds_dmi_callback, | |
b066254f PC |
579 | .ident = "Dell OptiPlex FX170", |
580 | .matches = { | |
581 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
582 | DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"), | |
583 | }, | |
584 | }, | |
585 | { | |
586 | .callback = intel_no_lvds_dmi_callback, | |
70aa96ca JW |
587 | .ident = "AOpen Mini PC", |
588 | .matches = { | |
589 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
590 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
591 | }, | |
592 | }, | |
ed8c754b TV |
593 | { |
594 | .callback = intel_no_lvds_dmi_callback, | |
595 | .ident = "AOpen Mini PC MP915", | |
596 | .matches = { | |
597 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
598 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
599 | }, | |
600 | }, | |
22ab70d3 KP |
601 | { |
602 | .callback = intel_no_lvds_dmi_callback, | |
603 | .ident = "AOpen i915GMm-HFS", | |
604 | .matches = { | |
605 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
606 | DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"), | |
607 | }, | |
608 | }, | |
e57b6886 DV |
609 | { |
610 | .callback = intel_no_lvds_dmi_callback, | |
611 | .ident = "AOpen i45GMx-I", | |
612 | .matches = { | |
613 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
614 | DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"), | |
615 | }, | |
616 | }, | |
fa0864b2 MC |
617 | { |
618 | .callback = intel_no_lvds_dmi_callback, | |
619 | .ident = "Aopen i945GTt-VFA", | |
620 | .matches = { | |
621 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
622 | }, | |
623 | }, | |
9875557e SB |
624 | { |
625 | .callback = intel_no_lvds_dmi_callback, | |
626 | .ident = "Clientron U800", | |
627 | .matches = { | |
628 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
629 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
630 | }, | |
631 | }, | |
6a574b5b | 632 | { |
44306ab3 JS |
633 | .callback = intel_no_lvds_dmi_callback, |
634 | .ident = "Clientron E830", | |
635 | .matches = { | |
636 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
637 | DMI_MATCH(DMI_PRODUCT_NAME, "E830"), | |
638 | }, | |
639 | }, | |
640 | { | |
6a574b5b HG |
641 | .callback = intel_no_lvds_dmi_callback, |
642 | .ident = "Asus EeeBox PC EB1007", | |
643 | .matches = { | |
644 | DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."), | |
645 | DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"), | |
646 | }, | |
647 | }, | |
0999bbe0 AJ |
648 | { |
649 | .callback = intel_no_lvds_dmi_callback, | |
650 | .ident = "Asus AT5NM10T-I", | |
651 | .matches = { | |
652 | DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."), | |
653 | DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"), | |
654 | }, | |
655 | }, | |
33471119 JBG |
656 | { |
657 | .callback = intel_no_lvds_dmi_callback, | |
45a211d7 | 658 | .ident = "Hewlett-Packard HP t5740", |
33471119 JBG |
659 | .matches = { |
660 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
45a211d7 | 661 | DMI_MATCH(DMI_PRODUCT_NAME, " t5740"), |
33471119 JBG |
662 | }, |
663 | }, | |
f5b8a7ed MG |
664 | { |
665 | .callback = intel_no_lvds_dmi_callback, | |
666 | .ident = "Hewlett-Packard t5745", | |
667 | .matches = { | |
668 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 669 | DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"), |
f5b8a7ed MG |
670 | }, |
671 | }, | |
672 | { | |
673 | .callback = intel_no_lvds_dmi_callback, | |
674 | .ident = "Hewlett-Packard st5747", | |
675 | .matches = { | |
676 | DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"), | |
62004978 | 677 | DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"), |
f5b8a7ed MG |
678 | }, |
679 | }, | |
97effadb AA |
680 | { |
681 | .callback = intel_no_lvds_dmi_callback, | |
682 | .ident = "MSI Wind Box DC500", | |
683 | .matches = { | |
684 | DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"), | |
685 | DMI_MATCH(DMI_BOARD_NAME, "MS-7469"), | |
686 | }, | |
687 | }, | |
a51d4ed0 CW |
688 | { |
689 | .callback = intel_no_lvds_dmi_callback, | |
690 | .ident = "Gigabyte GA-D525TUD", | |
691 | .matches = { | |
692 | DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."), | |
693 | DMI_MATCH(DMI_BOARD_NAME, "D525TUD"), | |
694 | }, | |
695 | }, | |
c31407a3 CW |
696 | { |
697 | .callback = intel_no_lvds_dmi_callback, | |
698 | .ident = "Supermicro X7SPA-H", | |
699 | .matches = { | |
700 | DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"), | |
701 | DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"), | |
702 | }, | |
703 | }, | |
9e9dd0e8 CL |
704 | { |
705 | .callback = intel_no_lvds_dmi_callback, | |
706 | .ident = "Fujitsu Esprimo Q900", | |
707 | .matches = { | |
708 | DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"), | |
709 | DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"), | |
710 | }, | |
711 | }, | |
645378d8 RP |
712 | { |
713 | .callback = intel_no_lvds_dmi_callback, | |
714 | .ident = "Intel D410PT", | |
715 | .matches = { | |
716 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
717 | DMI_MATCH(DMI_BOARD_NAME, "D410PT"), | |
718 | }, | |
719 | }, | |
720 | { | |
721 | .callback = intel_no_lvds_dmi_callback, | |
722 | .ident = "Intel D425KT", | |
723 | .matches = { | |
724 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
725 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"), | |
726 | }, | |
727 | }, | |
e5614f0c CW |
728 | { |
729 | .callback = intel_no_lvds_dmi_callback, | |
730 | .ident = "Intel D510MO", | |
731 | .matches = { | |
732 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
733 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"), | |
734 | }, | |
735 | }, | |
dcf6d294 JN |
736 | { |
737 | .callback = intel_no_lvds_dmi_callback, | |
738 | .ident = "Intel D525MW", | |
739 | .matches = { | |
740 | DMI_MATCH(DMI_BOARD_VENDOR, "Intel"), | |
741 | DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"), | |
742 | }, | |
743 | }, | |
425d244c JW |
744 | |
745 | { } /* terminating entry */ | |
746 | }; | |
79e53945 | 747 | |
18f9ed12 ZY |
748 | /** |
749 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
750 | * @dev: drm device | |
751 | * @connector: LVDS connector | |
752 | * | |
753 | * Find the reduced downclock for LVDS in EDID. | |
754 | */ | |
755 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
756 | struct drm_display_mode *fixed_mode, |
757 | struct drm_connector *connector) | |
18f9ed12 ZY |
758 | { |
759 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 760 | struct drm_display_mode *scan; |
18f9ed12 ZY |
761 | int temp_downclock; |
762 | ||
788319d4 | 763 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
764 | list_for_each_entry(scan, &connector->probed_modes, head) { |
765 | /* | |
766 | * If one mode has the same resolution with the fixed_panel | |
767 | * mode while they have the different refresh rate, it means | |
768 | * that the reduced downclock is found for the LVDS. In such | |
769 | * case we can set the different FPx0/1 to dynamically select | |
770 | * between low and high frequency. | |
771 | */ | |
788319d4 CW |
772 | if (scan->hdisplay == fixed_mode->hdisplay && |
773 | scan->hsync_start == fixed_mode->hsync_start && | |
774 | scan->hsync_end == fixed_mode->hsync_end && | |
775 | scan->htotal == fixed_mode->htotal && | |
776 | scan->vdisplay == fixed_mode->vdisplay && | |
777 | scan->vsync_start == fixed_mode->vsync_start && | |
778 | scan->vsync_end == fixed_mode->vsync_end && | |
779 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
780 | if (scan->clock < temp_downclock) { |
781 | /* | |
782 | * The downclock is already found. But we | |
783 | * expect to find the lower downclock. | |
784 | */ | |
785 | temp_downclock = scan->clock; | |
786 | } | |
787 | } | |
788 | } | |
788319d4 | 789 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
790 | /* We found the downclock for LVDS. */ |
791 | dev_priv->lvds_downclock_avail = 1; | |
792 | dev_priv->lvds_downclock = temp_downclock; | |
793 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
794 | "Normal clock %dKhz, downclock %dKhz\n", |
795 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 796 | } |
18f9ed12 ZY |
797 | } |
798 | ||
7cf4f69d ZY |
799 | /* |
800 | * Enumerate the child dev array parsed from VBT to check whether | |
801 | * the LVDS is present. | |
802 | * If it is present, return 1. | |
803 | * If it is not present, return false. | |
804 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 805 | */ |
270eea0f CW |
806 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
807 | u8 *i2c_pin) | |
7cf4f69d ZY |
808 | { |
809 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 810 | int i; |
7cf4f69d | 811 | |
41aa3448 | 812 | if (!dev_priv->vbt.child_dev_num) |
425904dd | 813 | return true; |
7cf4f69d | 814 | |
41aa3448 | 815 | for (i = 0; i < dev_priv->vbt.child_dev_num; i++) { |
768f69c9 PZ |
816 | union child_device_config *uchild = dev_priv->vbt.child_dev + i; |
817 | struct old_child_dev_config *child = &uchild->old; | |
425904dd CW |
818 | |
819 | /* If the device type is not LFP, continue. | |
820 | * We have to check both the new identifiers as well as the | |
821 | * old for compatibility with some BIOSes. | |
7cf4f69d | 822 | */ |
425904dd CW |
823 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
824 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
825 | continue; |
826 | ||
3bd7d909 DK |
827 | if (intel_gmbus_is_port_valid(child->i2c_pin)) |
828 | *i2c_pin = child->i2c_pin; | |
270eea0f | 829 | |
425904dd CW |
830 | /* However, we cannot trust the BIOS writers to populate |
831 | * the VBT correctly. Since LVDS requires additional | |
832 | * information from AIM blocks, a non-zero addin offset is | |
833 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 834 | */ |
425904dd CW |
835 | if (child->addin_offset) |
836 | return true; | |
837 | ||
838 | /* But even then some BIOS writers perform some black magic | |
839 | * and instantiate the device without reference to any | |
840 | * additional data. Trust that if the VBT was written into | |
841 | * the OpRegion then they have validated the LVDS's existence. | |
842 | */ | |
843 | if (dev_priv->opregion.vbt) | |
844 | return true; | |
7cf4f69d | 845 | } |
425904dd CW |
846 | |
847 | return false; | |
7cf4f69d ZY |
848 | } |
849 | ||
1974cad0 DV |
850 | static int intel_dual_link_lvds_callback(const struct dmi_system_id *id) |
851 | { | |
852 | DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident); | |
853 | return 1; | |
854 | } | |
855 | ||
856 | static const struct dmi_system_id intel_dual_link_lvds[] = { | |
857 | { | |
858 | .callback = intel_dual_link_lvds_callback, | |
859 | .ident = "Apple MacBook Pro (Core i5/i7 Series)", | |
860 | .matches = { | |
861 | DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."), | |
862 | DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"), | |
863 | }, | |
864 | }, | |
865 | { } /* terminating entry */ | |
866 | }; | |
867 | ||
868 | bool intel_is_dual_link_lvds(struct drm_device *dev) | |
13c7d870 DV |
869 | { |
870 | struct intel_encoder *encoder; | |
871 | struct intel_lvds_encoder *lvds_encoder; | |
872 | ||
873 | list_for_each_entry(encoder, &dev->mode_config.encoder_list, | |
874 | base.head) { | |
875 | if (encoder->type == INTEL_OUTPUT_LVDS) { | |
876 | lvds_encoder = to_lvds_encoder(&encoder->base); | |
877 | ||
878 | return lvds_encoder->is_dual_link; | |
879 | } | |
880 | } | |
881 | ||
882 | return false; | |
883 | } | |
884 | ||
7dec0606 | 885 | static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder) |
1974cad0 | 886 | { |
7dec0606 | 887 | struct drm_device *dev = lvds_encoder->base.base.dev; |
1974cad0 DV |
888 | unsigned int val; |
889 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1974cad0 DV |
890 | |
891 | /* use the module option value if specified */ | |
892 | if (i915_lvds_channel_mode > 0) | |
893 | return i915_lvds_channel_mode == 2; | |
894 | ||
895 | if (dmi_check_system(intel_dual_link_lvds)) | |
896 | return true; | |
897 | ||
13c7d870 DV |
898 | /* BIOS should set the proper LVDS register value at boot, but |
899 | * in reality, it doesn't set the value when the lid is closed; | |
900 | * we need to check "the value to be set" in VBT when LVDS | |
901 | * register is uninitialized. | |
902 | */ | |
7dec0606 | 903 | val = I915_READ(lvds_encoder->reg); |
13c7d870 | 904 | if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED))) |
41aa3448 | 905 | val = dev_priv->vbt.bios_lvds_val; |
13c7d870 | 906 | |
1974cad0 DV |
907 | return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP; |
908 | } | |
909 | ||
f3cfcba6 CW |
910 | static bool intel_lvds_supported(struct drm_device *dev) |
911 | { | |
912 | /* With the introduction of the PCH we gained a dedicated | |
913 | * LVDS presence pin, use it. */ | |
311e359c | 914 | if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev)) |
f3cfcba6 CW |
915 | return true; |
916 | ||
917 | /* Otherwise LVDS was only attached to mobile products, | |
918 | * except for the inglorious 830gm */ | |
311e359c PZ |
919 | if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev)) |
920 | return true; | |
921 | ||
922 | return false; | |
f3cfcba6 CW |
923 | } |
924 | ||
79e53945 JB |
925 | /** |
926 | * intel_lvds_init - setup LVDS connectors on this device | |
927 | * @dev: drm device | |
928 | * | |
929 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
930 | * modes we can display on the LVDS panel (if present). | |
931 | */ | |
c9093354 | 932 | void intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
933 | { |
934 | struct drm_i915_private *dev_priv = dev->dev_private; | |
29b99b48 | 935 | struct intel_lvds_encoder *lvds_encoder; |
21d40d37 | 936 | struct intel_encoder *intel_encoder; |
c7362c4d | 937 | struct intel_lvds_connector *lvds_connector; |
bb8a3560 | 938 | struct intel_connector *intel_connector; |
79e53945 JB |
939 | struct drm_connector *connector; |
940 | struct drm_encoder *encoder; | |
941 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
dd06f90e | 942 | struct drm_display_mode *fixed_mode = NULL; |
9cd300e0 | 943 | struct edid *edid; |
79e53945 JB |
944 | struct drm_crtc *crtc; |
945 | u32 lvds; | |
270eea0f CW |
946 | int pipe; |
947 | u8 pin; | |
79e53945 | 948 | |
f3cfcba6 | 949 | if (!intel_lvds_supported(dev)) |
c9093354 | 950 | return; |
f3cfcba6 | 951 | |
425d244c JW |
952 | /* Skip init on machines we know falsely report LVDS */ |
953 | if (dmi_check_system(intel_no_lvds)) | |
c9093354 | 954 | return; |
565dcd46 | 955 | |
270eea0f CW |
956 | pin = GMBUS_PORT_PANEL; |
957 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 958 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c9093354 | 959 | return; |
38b3037e | 960 | } |
e99da35f | 961 | |
c619eed4 | 962 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 963 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c9093354 | 964 | return; |
41aa3448 | 965 | if (dev_priv->vbt.edp_support) { |
28c97730 | 966 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c9093354 | 967 | return; |
32f9d658 | 968 | } |
541998a1 ZW |
969 | } |
970 | ||
b14c5679 | 971 | lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL); |
29b99b48 | 972 | if (!lvds_encoder) |
c9093354 | 973 | return; |
79e53945 | 974 | |
b14c5679 | 975 | lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL); |
c7362c4d | 976 | if (!lvds_connector) { |
29b99b48 | 977 | kfree(lvds_encoder); |
c9093354 | 978 | return; |
bb8a3560 ZW |
979 | } |
980 | ||
62165e0d JN |
981 | lvds_encoder->attached_connector = lvds_connector; |
982 | ||
29b99b48 | 983 | intel_encoder = &lvds_encoder->base; |
4ef69c7a | 984 | encoder = &intel_encoder->base; |
c7362c4d | 985 | intel_connector = &lvds_connector->base; |
ea5b213a | 986 | connector = &intel_connector->base; |
bb8a3560 | 987 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
988 | DRM_MODE_CONNECTOR_LVDS); |
989 | ||
4ef69c7a | 990 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
991 | DRM_MODE_ENCODER_LVDS); |
992 | ||
c22834ec | 993 | intel_encoder->enable = intel_enable_lvds; |
f6736a1a | 994 | intel_encoder->pre_enable = intel_pre_enable_lvds; |
7ae89233 | 995 | intel_encoder->compute_config = intel_lvds_compute_config; |
66df24d9 | 996 | intel_encoder->mode_set = intel_lvds_mode_set; |
c22834ec | 997 | intel_encoder->disable = intel_disable_lvds; |
b1dc332c | 998 | intel_encoder->get_hw_state = intel_lvds_get_hw_state; |
045ac3b5 | 999 | intel_encoder->get_config = intel_lvds_get_config; |
b1dc332c | 1000 | intel_connector->get_hw_state = intel_connector_get_hw_state; |
c22834ec | 1001 | |
df0e9248 | 1002 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 1003 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 1004 | |
66a9278e | 1005 | intel_encoder->cloneable = false; |
27f8227b JB |
1006 | if (HAS_PCH_SPLIT(dev)) |
1007 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2); | |
0b9f43a0 DV |
1008 | else if (IS_GEN4(dev)) |
1009 | intel_encoder->crtc_mask = (1 << 0) | (1 << 1); | |
27f8227b JB |
1010 | else |
1011 | intel_encoder->crtc_mask = (1 << 1); | |
1012 | ||
79e53945 JB |
1013 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); |
1014 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
1015 | connector->interlace_allowed = false; | |
1016 | connector->doublescan_allowed = false; | |
1017 | ||
7dec0606 DV |
1018 | if (HAS_PCH_SPLIT(dev)) { |
1019 | lvds_encoder->reg = PCH_LVDS; | |
1020 | } else { | |
1021 | lvds_encoder->reg = LVDS; | |
1022 | } | |
1023 | ||
3fbe18d6 ZY |
1024 | /* create the scaling mode property */ |
1025 | drm_mode_create_scaling_mode_property(dev); | |
662595df | 1026 | drm_object_attach_property(&connector->base, |
3fbe18d6 | 1027 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 1028 | DRM_MODE_SCALE_ASPECT); |
4d891523 | 1029 | intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
1030 | /* |
1031 | * LVDS discovery: | |
1032 | * 1) check for EDID on DDC | |
1033 | * 2) check for VBT data | |
1034 | * 3) check to see if LVDS is already on | |
1035 | * if none of the above, no panel | |
1036 | * 4) make sure lid is open | |
1037 | * if closed, act like it's not there for now | |
1038 | */ | |
1039 | ||
79e53945 JB |
1040 | /* |
1041 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
1042 | * preferred mode is the right one. | |
1043 | */ | |
9cd300e0 JN |
1044 | edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin)); |
1045 | if (edid) { | |
1046 | if (drm_add_edid_modes(connector, edid)) { | |
3f8ff0e7 | 1047 | drm_mode_connector_update_edid_property(connector, |
9cd300e0 | 1048 | edid); |
3f8ff0e7 | 1049 | } else { |
9cd300e0 JN |
1050 | kfree(edid); |
1051 | edid = ERR_PTR(-EINVAL); | |
3f8ff0e7 | 1052 | } |
9cd300e0 JN |
1053 | } else { |
1054 | edid = ERR_PTR(-ENOENT); | |
3f8ff0e7 | 1055 | } |
9cd300e0 JN |
1056 | lvds_connector->base.edid = edid; |
1057 | ||
1058 | if (IS_ERR_OR_NULL(edid)) { | |
788319d4 CW |
1059 | /* Didn't get an EDID, so |
1060 | * Set wide sync ranges so we get all modes | |
1061 | * handed to valid_mode for checking | |
1062 | */ | |
1063 | connector->display_info.min_vfreq = 0; | |
1064 | connector->display_info.max_vfreq = 200; | |
1065 | connector->display_info.min_hfreq = 0; | |
1066 | connector->display_info.max_hfreq = 200; | |
1067 | } | |
79e53945 JB |
1068 | |
1069 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 1070 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
6a9d51b7 CW |
1071 | DRM_DEBUG_KMS("using preferred mode from EDID: "); |
1072 | drm_mode_debug_printmodeline(scan); | |
1073 | ||
dd06f90e | 1074 | fixed_mode = drm_mode_duplicate(dev, scan); |
6a9d51b7 CW |
1075 | if (fixed_mode) { |
1076 | intel_find_lvds_downclock(dev, fixed_mode, | |
1077 | connector); | |
1078 | goto out; | |
1079 | } | |
79e53945 | 1080 | } |
79e53945 JB |
1081 | } |
1082 | ||
1083 | /* Failed to get EDID, what about VBT? */ | |
41aa3448 | 1084 | if (dev_priv->vbt.lfp_lvds_vbt_mode) { |
6a9d51b7 | 1085 | DRM_DEBUG_KMS("using mode from VBT: "); |
41aa3448 | 1086 | drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode); |
6a9d51b7 | 1087 | |
41aa3448 | 1088 | fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode); |
dd06f90e JN |
1089 | if (fixed_mode) { |
1090 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; | |
e285f3cd JB |
1091 | goto out; |
1092 | } | |
79e53945 JB |
1093 | } |
1094 | ||
1095 | /* | |
1096 | * If we didn't get EDID, try checking if the panel is already turned | |
1097 | * on. If so, assume that whatever is currently programmed is the | |
1098 | * correct mode. | |
1099 | */ | |
541998a1 | 1100 | |
f2b115e6 | 1101 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 1102 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
1103 | goto failed; |
1104 | ||
79e53945 JB |
1105 | lvds = I915_READ(LVDS); |
1106 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 1107 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
1108 | |
1109 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
dd06f90e JN |
1110 | fixed_mode = intel_crtc_mode_get(dev, crtc); |
1111 | if (fixed_mode) { | |
6a9d51b7 CW |
1112 | DRM_DEBUG_KMS("using current (BIOS) mode: "); |
1113 | drm_mode_debug_printmodeline(fixed_mode); | |
dd06f90e | 1114 | fixed_mode->type |= DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1115 | goto out; |
79e53945 JB |
1116 | } |
1117 | } | |
1118 | ||
1119 | /* If we still don't have a mode after all that, give up. */ | |
dd06f90e | 1120 | if (!fixed_mode) |
79e53945 JB |
1121 | goto failed; |
1122 | ||
79e53945 | 1123 | out: |
7dec0606 | 1124 | lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder); |
13c7d870 DV |
1125 | DRM_DEBUG_KMS("detected %s-link lvds configuration\n", |
1126 | lvds_encoder->is_dual_link ? "dual" : "single"); | |
1127 | ||
24ded204 DV |
1128 | /* |
1129 | * Unlock registers and just | |
1130 | * leave them unlocked | |
1131 | */ | |
c619eed4 | 1132 | if (HAS_PCH_SPLIT(dev)) { |
ed10fca9 KP |
1133 | I915_WRITE(PCH_PP_CONTROL, |
1134 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
1135 | } else { | |
ed10fca9 KP |
1136 | I915_WRITE(PP_CONTROL, |
1137 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
541998a1 | 1138 | } |
db1740a0 JN |
1139 | lvds_connector->lid_notifier.notifier_call = intel_lid_notify; |
1140 | if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) { | |
28c97730 | 1141 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
db1740a0 | 1142 | lvds_connector->lid_notifier.notifier_call = NULL; |
c1c7af60 | 1143 | } |
79e53945 | 1144 | drm_sysfs_connector_add(connector); |
aaa6fd2a | 1145 | |
dd06f90e | 1146 | intel_panel_init(&intel_connector->panel, fixed_mode); |
0657b6b1 | 1147 | intel_panel_setup_backlight(connector); |
aaa6fd2a | 1148 | |
c9093354 | 1149 | return; |
79e53945 JB |
1150 | |
1151 | failed: | |
8a4c47f3 | 1152 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1153 | drm_connector_cleanup(connector); |
1991bdfa | 1154 | drm_encoder_cleanup(encoder); |
dd06f90e JN |
1155 | if (fixed_mode) |
1156 | drm_mode_destroy(dev, fixed_mode); | |
29b99b48 | 1157 | kfree(lvds_encoder); |
c7362c4d | 1158 | kfree(lvds_connector); |
c9093354 | 1159 | return; |
79e53945 | 1160 | } |