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drm/i915: add intel_display_power_enabled_sw() for use in atomic ctx
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
13c7d870 52 bool is_dual_link;
7dec0606 53 u32 reg;
788319d4 54
62165e0d 55 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
56};
57
29b99b48 58static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 59{
29b99b48 60 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
61}
62
c7362c4d 63static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 64{
c7362c4d 65 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
66}
67
b1dc332c
DV
68static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
69 enum pipe *pipe)
70{
71 struct drm_device *dev = encoder->base.dev;
72 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
73 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
74 u32 tmp;
b1dc332c 75
7dec0606 76 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
77
78 if (!(tmp & LVDS_PORT_EN))
79 return false;
80
81 if (HAS_PCH_CPT(dev))
82 *pipe = PORT_TO_PIPE_CPT(tmp);
83 else
84 *pipe = PORT_TO_PIPE(tmp);
85
86 return true;
87}
88
045ac3b5
JB
89static void intel_lvds_get_config(struct intel_encoder *encoder,
90 struct intel_crtc_config *pipe_config)
91{
92 struct drm_device *dev = encoder->base.dev;
93 struct drm_i915_private *dev_priv = dev->dev_private;
94 u32 lvds_reg, tmp, flags = 0;
18442d08 95 int dotclock;
045ac3b5
JB
96
97 if (HAS_PCH_SPLIT(dev))
98 lvds_reg = PCH_LVDS;
99 else
100 lvds_reg = LVDS;
101
102 tmp = I915_READ(lvds_reg);
103 if (tmp & LVDS_HSYNC_POLARITY)
104 flags |= DRM_MODE_FLAG_NHSYNC;
105 else
106 flags |= DRM_MODE_FLAG_PHSYNC;
107 if (tmp & LVDS_VSYNC_POLARITY)
108 flags |= DRM_MODE_FLAG_NVSYNC;
109 else
110 flags |= DRM_MODE_FLAG_PVSYNC;
111
112 pipe_config->adjusted_mode.flags |= flags;
06922821
DV
113
114 /* gen2/3 store dither state in pfit control, needs to match */
115 if (INTEL_INFO(dev)->gen < 4) {
116 tmp = I915_READ(PFIT_CONTROL);
117
118 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
119 }
18442d08
VS
120
121 dotclock = pipe_config->port_clock;
122
123 if (HAS_PCH_SPLIT(dev_priv->dev))
124 ironlake_check_encoder_dotclock(pipe_config, dotclock);
125
241bfc38 126 pipe_config->adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB
127}
128
fc683091
DV
129/* The LVDS pin pair needs to be on before the DPLLs are enabled.
130 * This is an exception to the general rule that mode_set doesn't turn
131 * things on.
132 */
f6736a1a 133static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
134{
135 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
136 struct drm_device *dev = encoder->base.dev;
137 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 138 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
4c6df4b4
VS
139 const struct drm_display_mode *adjusted_mode =
140 &crtc->config.adjusted_mode;
55607e8a 141 int pipe = crtc->pipe;
fc683091
DV
142 u32 temp;
143
55607e8a
DV
144 if (HAS_PCH_SPLIT(dev)) {
145 assert_fdi_rx_pll_disabled(dev_priv, pipe);
146 assert_shared_dpll_disabled(dev_priv,
147 intel_crtc_to_shared_dpll(crtc));
148 } else {
149 assert_pll_disabled(dev_priv, pipe);
150 }
151
fc683091
DV
152 temp = I915_READ(lvds_encoder->reg);
153 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
154
155 if (HAS_PCH_CPT(dev)) {
156 temp &= ~PORT_TRANS_SEL_MASK;
157 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 158 } else {
62810e5a
DV
159 if (pipe == 1) {
160 temp |= LVDS_PIPEB_SELECT;
161 } else {
162 temp &= ~LVDS_PIPEB_SELECT;
163 }
fc683091 164 }
62810e5a 165
fc683091 166 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 167 temp &= ~LVDS_BORDER_ENABLE;
55607e8a 168 temp |= crtc->config.gmch_pfit.lvds_border_bits;
fc683091
DV
169 /* Set the B0-B3 data pairs corresponding to whether we're going to
170 * set the DPLLs for dual-channel mode or not.
171 */
172 if (lvds_encoder->is_dual_link)
173 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
174 else
175 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
176
177 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
178 * appropriately here, but we need to look more thoroughly into how
179 * panels behave in the two modes.
180 */
62810e5a
DV
181
182 /* Set the dithering flag on LVDS as needed, note that there is no
183 * special lvds dither control bit on pch-split platforms, dithering is
184 * only controlled through the PIPECONF reg. */
185 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
186 /* Bspec wording suggests that LVDS port dithering only exists
187 * for 18bpp panels. */
55607e8a 188 if (crtc->config.dither && crtc->config.pipe_bpp == 18)
fc683091
DV
189 temp |= LVDS_ENABLE_DITHER;
190 else
191 temp &= ~LVDS_ENABLE_DITHER;
192 }
193 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 194 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 195 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 196 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
197 temp |= LVDS_VSYNC_POLARITY;
198
199 I915_WRITE(lvds_encoder->reg, temp);
200}
201
79e53945
JB
202/**
203 * Sets the power state for the panel.
204 */
c22834ec 205static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 206{
c22834ec 207 struct drm_device *dev = encoder->base.dev;
29b99b48 208 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
209 struct intel_connector *intel_connector =
210 &lvds_encoder->attached_connector->base;
79e53945 211 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 212 u32 ctl_reg, stat_reg;
541998a1 213
c619eed4 214 if (HAS_PCH_SPLIT(dev)) {
541998a1 215 ctl_reg = PCH_PP_CONTROL;
de842eff 216 stat_reg = PCH_PP_STATUS;
541998a1
ZW
217 } else {
218 ctl_reg = PP_CONTROL;
de842eff 219 stat_reg = PP_STATUS;
541998a1 220 }
79e53945 221
7dec0606 222 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 223
2a1292fd 224 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 225 POSTING_READ(lvds_encoder->reg);
de842eff
KP
226 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
227 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 228
752aa88a 229 intel_panel_enable_backlight(intel_connector);
2a1292fd
CW
230}
231
c22834ec 232static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 233{
c22834ec 234 struct drm_device *dev = encoder->base.dev;
29b99b48 235 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
236 struct intel_connector *intel_connector =
237 &lvds_encoder->attached_connector->base;
2a1292fd 238 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 239 u32 ctl_reg, stat_reg;
2a1292fd
CW
240
241 if (HAS_PCH_SPLIT(dev)) {
242 ctl_reg = PCH_PP_CONTROL;
de842eff 243 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
244 } else {
245 ctl_reg = PP_CONTROL;
de842eff 246 stat_reg = PP_STATUS;
2a1292fd
CW
247 }
248
752aa88a 249 intel_panel_disable_backlight(intel_connector);
2a1292fd
CW
250
251 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
252 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
253 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 254
7dec0606
DV
255 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
256 POSTING_READ(lvds_encoder->reg);
79e53945
JB
257}
258
79e53945
JB
259static int intel_lvds_mode_valid(struct drm_connector *connector,
260 struct drm_display_mode *mode)
261{
dd06f90e
JN
262 struct intel_connector *intel_connector = to_intel_connector(connector);
263 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 264
788319d4
CW
265 if (mode->hdisplay > fixed_mode->hdisplay)
266 return MODE_PANEL;
267 if (mode->vdisplay > fixed_mode->vdisplay)
268 return MODE_PANEL;
79e53945
JB
269
270 return MODE_OK;
271}
272
7ae89233
DV
273static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
274 struct intel_crtc_config *pipe_config)
79e53945 275{
7ae89233 276 struct drm_device *dev = intel_encoder->base.dev;
79e53945 277 struct drm_i915_private *dev_priv = dev->dev_private;
7ae89233
DV
278 struct intel_lvds_encoder *lvds_encoder =
279 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
280 struct intel_connector *intel_connector =
281 &lvds_encoder->attached_connector->base;
7ae89233 282 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
29b99b48 283 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
4e53c2e0 284 unsigned int lvds_bpp;
79e53945
JB
285
286 /* Should never happen!! */
a6c45cf0 287 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 288 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
289 return false;
290 }
291
4e53c2e0
DV
292 if ((I915_READ(lvds_encoder->reg) & LVDS_A3_POWER_MASK) ==
293 LVDS_A3_POWER_UP)
294 lvds_bpp = 8*3;
295 else
296 lvds_bpp = 6*3;
297
e29c22c0 298 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
299 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
300 pipe_config->pipe_bpp, lvds_bpp);
301 pipe_config->pipe_bpp = lvds_bpp;
302 }
d8b32247 303
79e53945 304 /*
71677043 305 * We have timings from the BIOS for the panel, put them in
79e53945
JB
306 * to the adjusted mode. The CRTC will be set up for this mode,
307 * with the panel scaling set up to source from the H/VDisplay
308 * of the original mode.
309 */
4d891523 310 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 311 adjusted_mode);
1d8e1c75
CW
312
313 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
314 pipe_config->has_pch_encoder = true;
315
b074cec8
JB
316 intel_pch_panel_fitting(intel_crtc, pipe_config,
317 intel_connector->panel.fitting_mode);
2dd24552
JB
318 } else {
319 intel_gmch_panel_fitting(intel_crtc, pipe_config,
320 intel_connector->panel.fitting_mode);
79e53945 321
21d8a475 322 }
f9bef081 323
79e53945
JB
324 /*
325 * XXX: It would be nice to support lower refresh rates on the
326 * panels to reduce power consumption, and perhaps match the
327 * user's requested refresh rate.
328 */
329
330 return true;
331}
332
66df24d9 333static void intel_lvds_mode_set(struct intel_encoder *encoder)
79e53945 334{
79e53945 335 /*
66df24d9
DV
336 * We don't do anything here, the LVDS port is fully set up in the pre
337 * enable hook - the ordering constraints for enabling the lvds port vs.
338 * enabling the display pll are too strict.
79e53945 339 */
79e53945
JB
340}
341
342/**
343 * Detect the LVDS connection.
344 *
b42d4c5c
JB
345 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
346 * connected and closed means disconnected. We also send hotplug events as
347 * needed, using lid status notification from the input layer.
79e53945 348 */
7b334fcb 349static enum drm_connector_status
930a9e28 350intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 351{
7b9c5abe 352 struct drm_device *dev = connector->dev;
6ee3b5a1 353 enum drm_connector_status status;
b42d4c5c 354
164c8598
CW
355 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
356 connector->base.id, drm_get_connector_name(connector));
357
fe16d949
CW
358 status = intel_panel_detect(dev);
359 if (status != connector_status_unknown)
360 return status;
01fe9dbd 361
6ee3b5a1 362 return connector_status_connected;
79e53945
JB
363}
364
365/**
366 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
367 */
368static int intel_lvds_get_modes(struct drm_connector *connector)
369{
62165e0d 370 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 371 struct drm_device *dev = connector->dev;
788319d4 372 struct drm_display_mode *mode;
79e53945 373
9cd300e0 374 /* use cached edid if we have one */
2aa4f099 375 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 376 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 377
dd06f90e 378 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 379 if (mode == NULL)
788319d4 380 return 0;
79e53945 381
788319d4
CW
382 drm_mode_probed_add(connector, mode);
383 return 1;
79e53945
JB
384}
385
0544edfd
TB
386static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
387{
bc0daf48 388 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
389 return 1;
390}
391
392/* The GPU hangs up on these systems if modeset is performed on LID open */
393static const struct dmi_system_id intel_no_modeset_on_lid[] = {
394 {
395 .callback = intel_no_modeset_on_lid_dmi_callback,
396 .ident = "Toshiba Tecra A11",
397 .matches = {
398 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
399 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
400 },
401 },
402
403 { } /* terminating entry */
404};
405
c9354c85 406/*
b8efb17b
ZR
407 * Lid events. Note the use of 'modeset':
408 * - we set it to MODESET_ON_LID_OPEN on lid close,
409 * and set it to MODESET_DONE on open
c9354c85 410 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
411 * duplicate events where it was already properly set)
412 * - the suspend/resume paths will set it to
413 * MODESET_SUSPENDED and ignore the lid open event,
414 * because they restore the mode ("lid open").
c9354c85 415 */
c1c7af60
JB
416static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
417 void *unused)
418{
db1740a0
JN
419 struct intel_lvds_connector *lvds_connector =
420 container_of(nb, struct intel_lvds_connector, lid_notifier);
421 struct drm_connector *connector = &lvds_connector->base.base;
422 struct drm_device *dev = connector->dev;
423 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 424
2fb4e61d
AW
425 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
426 return NOTIFY_OK;
427
b8efb17b
ZR
428 mutex_lock(&dev_priv->modeset_restore_lock);
429 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
430 goto exit;
a2565377
ZY
431 /*
432 * check and update the status of LVDS connector after receiving
433 * the LID nofication event.
434 */
db1740a0 435 connector->status = connector->funcs->detect(connector, false);
7b334fcb 436
0544edfd
TB
437 /* Don't force modeset on machines where it causes a GPU lockup */
438 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 439 goto exit;
c9354c85 440 if (!acpi_lid_open()) {
b8efb17b
ZR
441 /* do modeset on next lid open event */
442 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
443 goto exit;
06891e27 444 }
c1c7af60 445
b8efb17b
ZR
446 if (dev_priv->modeset_restore == MODESET_DONE)
447 goto exit;
c9354c85 448
a0e99e68 449 drm_modeset_lock_all(dev);
45e2b5f6 450 intel_modeset_setup_hw_state(dev, true);
a0e99e68 451 drm_modeset_unlock_all(dev);
06324194 452
b8efb17b
ZR
453 dev_priv->modeset_restore = MODESET_DONE;
454
455exit:
456 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
457 return NOTIFY_OK;
458}
459
79e53945
JB
460/**
461 * intel_lvds_destroy - unregister and free LVDS structures
462 * @connector: connector to free
463 *
464 * Unregister the DDC bus for this connector then free the driver private
465 * structure.
466 */
467static void intel_lvds_destroy(struct drm_connector *connector)
468{
db1740a0
JN
469 struct intel_lvds_connector *lvds_connector =
470 to_lvds_connector(connector);
79e53945 471
db1740a0
JN
472 if (lvds_connector->lid_notifier.notifier_call)
473 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 474
9cd300e0
JN
475 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
476 kfree(lvds_connector->base.edid);
477
1d508706 478 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 479
79e53945
JB
480 drm_connector_cleanup(connector);
481 kfree(connector);
482}
483
335041ed
JB
484static int intel_lvds_set_property(struct drm_connector *connector,
485 struct drm_property *property,
486 uint64_t value)
487{
4d891523 488 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 489 struct drm_device *dev = connector->dev;
3fbe18d6 490
788319d4 491 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 492 struct drm_crtc *crtc;
bb8a3560 493
53bd8389
JB
494 if (value == DRM_MODE_SCALE_NONE) {
495 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 496 return -EINVAL;
3fbe18d6 497 }
788319d4 498
4d891523 499 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
500 /* the LVDS scaling property is not changed */
501 return 0;
502 }
4d891523 503 intel_connector->panel.fitting_mode = value;
62165e0d
JN
504
505 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
506 if (crtc && crtc->enabled) {
507 /*
508 * If the CRTC is enabled, the display will be changed
509 * according to the new panel fitting mode.
510 */
c0c36b94 511 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
512 }
513 }
514
335041ed
JB
515 return 0;
516}
517
79e53945
JB
518static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
519 .get_modes = intel_lvds_get_modes,
520 .mode_valid = intel_lvds_mode_valid,
df0e9248 521 .best_encoder = intel_best_encoder,
79e53945
JB
522};
523
524static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 525 .dpms = intel_connector_dpms,
79e53945
JB
526 .detect = intel_lvds_detect,
527 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 528 .set_property = intel_lvds_set_property,
79e53945
JB
529 .destroy = intel_lvds_destroy,
530};
531
79e53945 532static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 533 .destroy = intel_encoder_destroy,
79e53945
JB
534};
535
425d244c
JW
536static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
537{
bc0daf48 538 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
539 return 1;
540}
79e53945 541
425d244c 542/* These systems claim to have LVDS, but really don't */
93c05f22 543static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
544 {
545 .callback = intel_no_lvds_dmi_callback,
546 .ident = "Apple Mac Mini (Core series)",
547 .matches = {
98acd46f 548 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
549 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
550 },
551 },
552 {
553 .callback = intel_no_lvds_dmi_callback,
554 .ident = "Apple Mac Mini (Core 2 series)",
555 .matches = {
98acd46f 556 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
557 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
558 },
559 },
560 {
561 .callback = intel_no_lvds_dmi_callback,
562 .ident = "MSI IM-945GSE-A",
563 .matches = {
564 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
565 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
566 },
567 },
568 {
569 .callback = intel_no_lvds_dmi_callback,
570 .ident = "Dell Studio Hybrid",
571 .matches = {
572 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
573 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
574 },
575 },
70aa96ca
JW
576 {
577 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
578 .ident = "Dell OptiPlex FX170",
579 .matches = {
580 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
581 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
582 },
583 },
584 {
585 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
586 .ident = "AOpen Mini PC",
587 .matches = {
588 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
589 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
590 },
591 },
ed8c754b
TV
592 {
593 .callback = intel_no_lvds_dmi_callback,
594 .ident = "AOpen Mini PC MP915",
595 .matches = {
596 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
597 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
598 },
599 },
22ab70d3
KP
600 {
601 .callback = intel_no_lvds_dmi_callback,
602 .ident = "AOpen i915GMm-HFS",
603 .matches = {
604 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
605 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
606 },
607 },
e57b6886
DV
608 {
609 .callback = intel_no_lvds_dmi_callback,
610 .ident = "AOpen i45GMx-I",
611 .matches = {
612 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
613 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
614 },
615 },
fa0864b2
MC
616 {
617 .callback = intel_no_lvds_dmi_callback,
618 .ident = "Aopen i945GTt-VFA",
619 .matches = {
620 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
621 },
622 },
9875557e
SB
623 {
624 .callback = intel_no_lvds_dmi_callback,
625 .ident = "Clientron U800",
626 .matches = {
627 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
628 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
629 },
630 },
6a574b5b 631 {
44306ab3
JS
632 .callback = intel_no_lvds_dmi_callback,
633 .ident = "Clientron E830",
634 .matches = {
635 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
636 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
637 },
638 },
639 {
6a574b5b
HG
640 .callback = intel_no_lvds_dmi_callback,
641 .ident = "Asus EeeBox PC EB1007",
642 .matches = {
643 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
644 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
645 },
646 },
0999bbe0
AJ
647 {
648 .callback = intel_no_lvds_dmi_callback,
649 .ident = "Asus AT5NM10T-I",
650 .matches = {
651 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
652 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
653 },
654 },
33471119
JBG
655 {
656 .callback = intel_no_lvds_dmi_callback,
45a211d7 657 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
658 .matches = {
659 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 660 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
661 },
662 },
f5b8a7ed
MG
663 {
664 .callback = intel_no_lvds_dmi_callback,
665 .ident = "Hewlett-Packard t5745",
666 .matches = {
667 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 668 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
669 },
670 },
671 {
672 .callback = intel_no_lvds_dmi_callback,
673 .ident = "Hewlett-Packard st5747",
674 .matches = {
675 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 676 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
677 },
678 },
97effadb
AA
679 {
680 .callback = intel_no_lvds_dmi_callback,
681 .ident = "MSI Wind Box DC500",
682 .matches = {
683 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
684 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
685 },
686 },
a51d4ed0
CW
687 {
688 .callback = intel_no_lvds_dmi_callback,
689 .ident = "Gigabyte GA-D525TUD",
690 .matches = {
691 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
692 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
693 },
694 },
c31407a3
CW
695 {
696 .callback = intel_no_lvds_dmi_callback,
697 .ident = "Supermicro X7SPA-H",
698 .matches = {
699 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
700 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
701 },
702 },
9e9dd0e8
CL
703 {
704 .callback = intel_no_lvds_dmi_callback,
705 .ident = "Fujitsu Esprimo Q900",
706 .matches = {
707 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
708 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
709 },
710 },
645378d8
RP
711 {
712 .callback = intel_no_lvds_dmi_callback,
713 .ident = "Intel D410PT",
714 .matches = {
715 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
716 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
717 },
718 },
719 {
720 .callback = intel_no_lvds_dmi_callback,
721 .ident = "Intel D425KT",
722 .matches = {
723 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
724 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
725 },
726 },
e5614f0c
CW
727 {
728 .callback = intel_no_lvds_dmi_callback,
729 .ident = "Intel D510MO",
730 .matches = {
731 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
732 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
733 },
734 },
dcf6d294
JN
735 {
736 .callback = intel_no_lvds_dmi_callback,
737 .ident = "Intel D525MW",
738 .matches = {
739 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
740 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
741 },
742 },
425d244c
JW
743
744 { } /* terminating entry */
745};
79e53945 746
18f9ed12
ZY
747/**
748 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
749 * @dev: drm device
750 * @connector: LVDS connector
751 *
752 * Find the reduced downclock for LVDS in EDID.
753 */
754static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
755 struct drm_display_mode *fixed_mode,
756 struct drm_connector *connector)
18f9ed12
ZY
757{
758 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 759 struct drm_display_mode *scan;
18f9ed12
ZY
760 int temp_downclock;
761
788319d4 762 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
763 list_for_each_entry(scan, &connector->probed_modes, head) {
764 /*
765 * If one mode has the same resolution with the fixed_panel
766 * mode while they have the different refresh rate, it means
767 * that the reduced downclock is found for the LVDS. In such
768 * case we can set the different FPx0/1 to dynamically select
769 * between low and high frequency.
770 */
788319d4
CW
771 if (scan->hdisplay == fixed_mode->hdisplay &&
772 scan->hsync_start == fixed_mode->hsync_start &&
773 scan->hsync_end == fixed_mode->hsync_end &&
774 scan->htotal == fixed_mode->htotal &&
775 scan->vdisplay == fixed_mode->vdisplay &&
776 scan->vsync_start == fixed_mode->vsync_start &&
777 scan->vsync_end == fixed_mode->vsync_end &&
778 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
779 if (scan->clock < temp_downclock) {
780 /*
781 * The downclock is already found. But we
782 * expect to find the lower downclock.
783 */
784 temp_downclock = scan->clock;
785 }
786 }
787 }
788319d4 788 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
789 /* We found the downclock for LVDS. */
790 dev_priv->lvds_downclock_avail = 1;
791 dev_priv->lvds_downclock = temp_downclock;
792 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
793 "Normal clock %dKhz, downclock %dKhz\n",
794 fixed_mode->clock, temp_downclock);
18f9ed12 795 }
18f9ed12
ZY
796}
797
7cf4f69d
ZY
798/*
799 * Enumerate the child dev array parsed from VBT to check whether
800 * the LVDS is present.
801 * If it is present, return 1.
802 * If it is not present, return false.
803 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 804 */
270eea0f
CW
805static bool lvds_is_present_in_vbt(struct drm_device *dev,
806 u8 *i2c_pin)
7cf4f69d
ZY
807{
808 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 809 int i;
7cf4f69d 810
41aa3448 811 if (!dev_priv->vbt.child_dev_num)
425904dd 812 return true;
7cf4f69d 813
41aa3448 814 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
768f69c9
PZ
815 union child_device_config *uchild = dev_priv->vbt.child_dev + i;
816 struct old_child_dev_config *child = &uchild->old;
425904dd
CW
817
818 /* If the device type is not LFP, continue.
819 * We have to check both the new identifiers as well as the
820 * old for compatibility with some BIOSes.
7cf4f69d 821 */
425904dd
CW
822 if (child->device_type != DEVICE_TYPE_INT_LFP &&
823 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
824 continue;
825
3bd7d909
DK
826 if (intel_gmbus_is_port_valid(child->i2c_pin))
827 *i2c_pin = child->i2c_pin;
270eea0f 828
425904dd
CW
829 /* However, we cannot trust the BIOS writers to populate
830 * the VBT correctly. Since LVDS requires additional
831 * information from AIM blocks, a non-zero addin offset is
832 * a good indicator that the LVDS is actually present.
7cf4f69d 833 */
425904dd
CW
834 if (child->addin_offset)
835 return true;
836
837 /* But even then some BIOS writers perform some black magic
838 * and instantiate the device without reference to any
839 * additional data. Trust that if the VBT was written into
840 * the OpRegion then they have validated the LVDS's existence.
841 */
842 if (dev_priv->opregion.vbt)
843 return true;
7cf4f69d 844 }
425904dd
CW
845
846 return false;
7cf4f69d
ZY
847}
848
1974cad0
DV
849static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
850{
851 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
852 return 1;
853}
854
855static const struct dmi_system_id intel_dual_link_lvds[] = {
856 {
857 .callback = intel_dual_link_lvds_callback,
858 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
859 .matches = {
860 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
861 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
862 },
863 },
864 { } /* terminating entry */
865};
866
867bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
868{
869 struct intel_encoder *encoder;
870 struct intel_lvds_encoder *lvds_encoder;
871
872 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
873 base.head) {
874 if (encoder->type == INTEL_OUTPUT_LVDS) {
875 lvds_encoder = to_lvds_encoder(&encoder->base);
876
877 return lvds_encoder->is_dual_link;
878 }
879 }
880
881 return false;
882}
883
7dec0606 884static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 885{
7dec0606 886 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
887 unsigned int val;
888 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
889
890 /* use the module option value if specified */
891 if (i915_lvds_channel_mode > 0)
892 return i915_lvds_channel_mode == 2;
893
894 if (dmi_check_system(intel_dual_link_lvds))
895 return true;
896
13c7d870
DV
897 /* BIOS should set the proper LVDS register value at boot, but
898 * in reality, it doesn't set the value when the lid is closed;
899 * we need to check "the value to be set" in VBT when LVDS
900 * register is uninitialized.
901 */
7dec0606 902 val = I915_READ(lvds_encoder->reg);
13c7d870 903 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 904 val = dev_priv->vbt.bios_lvds_val;
13c7d870 905
1974cad0
DV
906 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
907}
908
f3cfcba6
CW
909static bool intel_lvds_supported(struct drm_device *dev)
910{
911 /* With the introduction of the PCH we gained a dedicated
912 * LVDS presence pin, use it. */
311e359c 913 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
914 return true;
915
916 /* Otherwise LVDS was only attached to mobile products,
917 * except for the inglorious 830gm */
311e359c
PZ
918 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
919 return true;
920
921 return false;
f3cfcba6
CW
922}
923
79e53945
JB
924/**
925 * intel_lvds_init - setup LVDS connectors on this device
926 * @dev: drm device
927 *
928 * Create the connector, register the LVDS DDC bus, and try to figure out what
929 * modes we can display on the LVDS panel (if present).
930 */
c9093354 931void intel_lvds_init(struct drm_device *dev)
79e53945
JB
932{
933 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 934 struct intel_lvds_encoder *lvds_encoder;
21d40d37 935 struct intel_encoder *intel_encoder;
c7362c4d 936 struct intel_lvds_connector *lvds_connector;
bb8a3560 937 struct intel_connector *intel_connector;
79e53945
JB
938 struct drm_connector *connector;
939 struct drm_encoder *encoder;
940 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 941 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 942 struct edid *edid;
79e53945
JB
943 struct drm_crtc *crtc;
944 u32 lvds;
270eea0f
CW
945 int pipe;
946 u8 pin;
79e53945 947
f3cfcba6 948 if (!intel_lvds_supported(dev))
c9093354 949 return;
f3cfcba6 950
425d244c
JW
951 /* Skip init on machines we know falsely report LVDS */
952 if (dmi_check_system(intel_no_lvds))
c9093354 953 return;
565dcd46 954
270eea0f
CW
955 pin = GMBUS_PORT_PANEL;
956 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 957 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c9093354 958 return;
38b3037e 959 }
e99da35f 960
c619eed4 961 if (HAS_PCH_SPLIT(dev)) {
541998a1 962 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c9093354 963 return;
41aa3448 964 if (dev_priv->vbt.edp_support) {
28c97730 965 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 966 return;
32f9d658 967 }
541998a1
ZW
968 }
969
b14c5679 970 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
29b99b48 971 if (!lvds_encoder)
c9093354 972 return;
79e53945 973
b14c5679 974 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
c7362c4d 975 if (!lvds_connector) {
29b99b48 976 kfree(lvds_encoder);
c9093354 977 return;
bb8a3560
ZW
978 }
979
62165e0d
JN
980 lvds_encoder->attached_connector = lvds_connector;
981
29b99b48 982 intel_encoder = &lvds_encoder->base;
4ef69c7a 983 encoder = &intel_encoder->base;
c7362c4d 984 intel_connector = &lvds_connector->base;
ea5b213a 985 connector = &intel_connector->base;
bb8a3560 986 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
987 DRM_MODE_CONNECTOR_LVDS);
988
4ef69c7a 989 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
990 DRM_MODE_ENCODER_LVDS);
991
c22834ec 992 intel_encoder->enable = intel_enable_lvds;
f6736a1a 993 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 994 intel_encoder->compute_config = intel_lvds_compute_config;
66df24d9 995 intel_encoder->mode_set = intel_lvds_mode_set;
c22834ec 996 intel_encoder->disable = intel_disable_lvds;
b1dc332c 997 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 998 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 999 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 1000
df0e9248 1001 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1002 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1003
66a9278e 1004 intel_encoder->cloneable = false;
27f8227b
JB
1005 if (HAS_PCH_SPLIT(dev))
1006 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1007 else if (IS_GEN4(dev))
1008 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1009 else
1010 intel_encoder->crtc_mask = (1 << 1);
1011
79e53945
JB
1012 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1013 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1014 connector->interlace_allowed = false;
1015 connector->doublescan_allowed = false;
1016
7dec0606
DV
1017 if (HAS_PCH_SPLIT(dev)) {
1018 lvds_encoder->reg = PCH_LVDS;
1019 } else {
1020 lvds_encoder->reg = LVDS;
1021 }
1022
3fbe18d6
ZY
1023 /* create the scaling mode property */
1024 drm_mode_create_scaling_mode_property(dev);
662595df 1025 drm_object_attach_property(&connector->base,
3fbe18d6 1026 dev->mode_config.scaling_mode_property,
dd1ea37d 1027 DRM_MODE_SCALE_ASPECT);
4d891523 1028 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1029 /*
1030 * LVDS discovery:
1031 * 1) check for EDID on DDC
1032 * 2) check for VBT data
1033 * 3) check to see if LVDS is already on
1034 * if none of the above, no panel
1035 * 4) make sure lid is open
1036 * if closed, act like it's not there for now
1037 */
1038
79e53945
JB
1039 /*
1040 * Attempt to get the fixed panel mode from DDC. Assume that the
1041 * preferred mode is the right one.
1042 */
9cd300e0
JN
1043 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1044 if (edid) {
1045 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1046 drm_mode_connector_update_edid_property(connector,
9cd300e0 1047 edid);
3f8ff0e7 1048 } else {
9cd300e0
JN
1049 kfree(edid);
1050 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1051 }
9cd300e0
JN
1052 } else {
1053 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1054 }
9cd300e0
JN
1055 lvds_connector->base.edid = edid;
1056
1057 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1058 /* Didn't get an EDID, so
1059 * Set wide sync ranges so we get all modes
1060 * handed to valid_mode for checking
1061 */
1062 connector->display_info.min_vfreq = 0;
1063 connector->display_info.max_vfreq = 200;
1064 connector->display_info.min_hfreq = 0;
1065 connector->display_info.max_hfreq = 200;
1066 }
79e53945
JB
1067
1068 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1069 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1070 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1071 drm_mode_debug_printmodeline(scan);
1072
dd06f90e 1073 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1074 if (fixed_mode) {
1075 intel_find_lvds_downclock(dev, fixed_mode,
1076 connector);
1077 goto out;
1078 }
79e53945 1079 }
79e53945
JB
1080 }
1081
1082 /* Failed to get EDID, what about VBT? */
41aa3448 1083 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1084 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1085 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1086
41aa3448 1087 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1088 if (fixed_mode) {
1089 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1090 goto out;
1091 }
79e53945
JB
1092 }
1093
1094 /*
1095 * If we didn't get EDID, try checking if the panel is already turned
1096 * on. If so, assume that whatever is currently programmed is the
1097 * correct mode.
1098 */
541998a1 1099
f2b115e6 1100 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1101 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1102 goto failed;
1103
79e53945
JB
1104 lvds = I915_READ(LVDS);
1105 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1106 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1107
1108 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1109 fixed_mode = intel_crtc_mode_get(dev, crtc);
1110 if (fixed_mode) {
6a9d51b7
CW
1111 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1112 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1113 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1114 goto out;
79e53945
JB
1115 }
1116 }
1117
1118 /* If we still don't have a mode after all that, give up. */
dd06f90e 1119 if (!fixed_mode)
79e53945
JB
1120 goto failed;
1121
79e53945 1122out:
7dec0606 1123 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1124 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1125 lvds_encoder->is_dual_link ? "dual" : "single");
1126
24ded204
DV
1127 /*
1128 * Unlock registers and just
1129 * leave them unlocked
1130 */
c619eed4 1131 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1132 I915_WRITE(PCH_PP_CONTROL,
1133 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1134 } else {
ed10fca9
KP
1135 I915_WRITE(PP_CONTROL,
1136 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1137 }
db1740a0
JN
1138 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1139 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1140 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1141 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1142 }
79e53945 1143 drm_sysfs_connector_add(connector);
aaa6fd2a 1144
dd06f90e 1145 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1146 intel_panel_setup_backlight(connector);
aaa6fd2a 1147
c9093354 1148 return;
79e53945
JB
1149
1150failed:
8a4c47f3 1151 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1152 drm_connector_cleanup(connector);
1991bdfa 1153 drm_encoder_cleanup(encoder);
dd06f90e
JN
1154 if (fixed_mode)
1155 drm_mode_destroy(dev, fixed_mode);
29b99b48 1156 kfree(lvds_encoder);
c7362c4d 1157 kfree(lvds_connector);
c9093354 1158 return;
79e53945 1159}