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CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7 34#include <drm/drmP.h>
c6f95f27 35#include <drm/drm_atomic_helper.h>
760285e7
DH
36#include <drm/drm_crtc.h>
37#include <drm/drm_edid.h>
79e53945 38#include "intel_drv.h"
760285e7 39#include <drm/i915_drm.h>
79e53945 40#include "i915_drv.h"
e99da35f 41#include <linux/acpi.h>
79e53945 42
3fbe18d6 43/* Private structure for the integrated LVDS support */
c7362c4d
JN
44struct intel_lvds_connector {
45 struct intel_connector base;
788319d4 46
db1740a0 47 struct notifier_block lid_notifier;
c7362c4d
JN
48};
49
29b99b48 50struct intel_lvds_encoder {
ea5b213a 51 struct intel_encoder base;
788319d4 52
13c7d870 53 bool is_dual_link;
f0f59a00 54 i915_reg_t reg;
1f835a77 55 u32 a3_power;
788319d4 56
62165e0d 57 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
58};
59
29b99b48 60static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 61{
29b99b48 62 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
63}
64
c7362c4d 65static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 66{
c7362c4d 67 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
68}
69
b1dc332c
DV
70static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
71 enum pipe *pipe)
72{
73 struct drm_device *dev = encoder->base.dev;
74 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 75 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
34a6c70f 76 enum intel_display_power_domain power_domain;
7dec0606 77 u32 tmp;
380bdff2 78 bool ret;
b1dc332c 79
34a6c70f 80 power_domain = intel_display_port_power_domain(encoder);
380bdff2 81 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
34a6c70f
PZ
82 return false;
83
380bdff2
ID
84 ret = false;
85
7dec0606 86 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
87
88 if (!(tmp & LVDS_PORT_EN))
380bdff2 89 goto out;
b1dc332c
DV
90
91 if (HAS_PCH_CPT(dev))
92 *pipe = PORT_TO_PIPE_CPT(tmp);
93 else
94 *pipe = PORT_TO_PIPE(tmp);
95
380bdff2
ID
96 ret = true;
97
98out:
99 intel_display_power_put(dev_priv, power_domain);
100
101 return ret;
b1dc332c
DV
102}
103
045ac3b5 104static void intel_lvds_get_config(struct intel_encoder *encoder,
5cec258b 105 struct intel_crtc_state *pipe_config)
045ac3b5
JB
106{
107 struct drm_device *dev = encoder->base.dev;
108 struct drm_i915_private *dev_priv = dev->dev_private;
d0669d00
VS
109 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
110 u32 tmp, flags = 0;
18442d08 111 int dotclock;
045ac3b5 112
d0669d00 113 tmp = I915_READ(lvds_encoder->reg);
045ac3b5
JB
114 if (tmp & LVDS_HSYNC_POLARITY)
115 flags |= DRM_MODE_FLAG_NHSYNC;
116 else
117 flags |= DRM_MODE_FLAG_PHSYNC;
118 if (tmp & LVDS_VSYNC_POLARITY)
119 flags |= DRM_MODE_FLAG_NVSYNC;
120 else
121 flags |= DRM_MODE_FLAG_PVSYNC;
122
2d112de7 123 pipe_config->base.adjusted_mode.flags |= flags;
06922821 124
6b89cdde
DV
125 /* gen2/3 store dither state in pfit control, needs to match */
126 if (INTEL_INFO(dev)->gen < 4) {
127 tmp = I915_READ(PFIT_CONTROL);
128
129 pipe_config->gmch_pfit.control |= tmp & PANEL_8TO6_DITHER_ENABLE;
130 }
131
18442d08
VS
132 dotclock = pipe_config->port_clock;
133
134 if (HAS_PCH_SPLIT(dev_priv->dev))
135 ironlake_check_encoder_dotclock(pipe_config, dotclock);
136
2d112de7 137 pipe_config->base.adjusted_mode.crtc_clock = dotclock;
045ac3b5
JB
138}
139
f6736a1a 140static void intel_pre_enable_lvds(struct intel_encoder *encoder)
fc683091
DV
141{
142 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
143 struct drm_device *dev = encoder->base.dev;
144 struct drm_i915_private *dev_priv = dev->dev_private;
55607e8a 145 struct intel_crtc *crtc = to_intel_crtc(encoder->base.crtc);
124abe07 146 const struct drm_display_mode *adjusted_mode = &crtc->config->base.adjusted_mode;
55607e8a 147 int pipe = crtc->pipe;
fc683091
DV
148 u32 temp;
149
55607e8a
DV
150 if (HAS_PCH_SPLIT(dev)) {
151 assert_fdi_rx_pll_disabled(dev_priv, pipe);
152 assert_shared_dpll_disabled(dev_priv,
153 intel_crtc_to_shared_dpll(crtc));
154 } else {
155 assert_pll_disabled(dev_priv, pipe);
156 }
157
fc683091
DV
158 temp = I915_READ(lvds_encoder->reg);
159 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
62810e5a
DV
160
161 if (HAS_PCH_CPT(dev)) {
162 temp &= ~PORT_TRANS_SEL_MASK;
163 temp |= PORT_TRANS_SEL_CPT(pipe);
fc683091 164 } else {
62810e5a
DV
165 if (pipe == 1) {
166 temp |= LVDS_PIPEB_SELECT;
167 } else {
168 temp &= ~LVDS_PIPEB_SELECT;
169 }
fc683091 170 }
62810e5a 171
fc683091 172 /* set the corresponsding LVDS_BORDER bit */
2fa2fe9a 173 temp &= ~LVDS_BORDER_ENABLE;
6e3c9717 174 temp |= crtc->config->gmch_pfit.lvds_border_bits;
fc683091
DV
175 /* Set the B0-B3 data pairs corresponding to whether we're going to
176 * set the DPLLs for dual-channel mode or not.
177 */
178 if (lvds_encoder->is_dual_link)
179 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
180 else
181 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
182
183 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
184 * appropriately here, but we need to look more thoroughly into how
1f835a77
PZ
185 * panels behave in the two modes. For now, let's just maintain the
186 * value we got from the BIOS.
fc683091 187 */
1f835a77
PZ
188 temp &= ~LVDS_A3_POWER_MASK;
189 temp |= lvds_encoder->a3_power;
62810e5a
DV
190
191 /* Set the dithering flag on LVDS as needed, note that there is no
192 * special lvds dither control bit on pch-split platforms, dithering is
193 * only controlled through the PIPECONF reg. */
194 if (INTEL_INFO(dev)->gen == 4) {
d8b32247
DV
195 /* Bspec wording suggests that LVDS port dithering only exists
196 * for 18bpp panels. */
6e3c9717 197 if (crtc->config->dither && crtc->config->pipe_bpp == 18)
fc683091
DV
198 temp |= LVDS_ENABLE_DITHER;
199 else
200 temp &= ~LVDS_ENABLE_DITHER;
201 }
202 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
4c6df4b4 203 if (adjusted_mode->flags & DRM_MODE_FLAG_NHSYNC)
fc683091 204 temp |= LVDS_HSYNC_POLARITY;
4c6df4b4 205 if (adjusted_mode->flags & DRM_MODE_FLAG_NVSYNC)
fc683091
DV
206 temp |= LVDS_VSYNC_POLARITY;
207
208 I915_WRITE(lvds_encoder->reg, temp);
209}
210
79e53945
JB
211/**
212 * Sets the power state for the panel.
213 */
c22834ec 214static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 215{
c22834ec 216 struct drm_device *dev = encoder->base.dev;
29b99b48 217 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
752aa88a
JB
218 struct intel_connector *intel_connector =
219 &lvds_encoder->attached_connector->base;
79e53945 220 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 221 i915_reg_t ctl_reg, stat_reg;
541998a1 222
c619eed4 223 if (HAS_PCH_SPLIT(dev)) {
541998a1 224 ctl_reg = PCH_PP_CONTROL;
de842eff 225 stat_reg = PCH_PP_STATUS;
541998a1
ZW
226 } else {
227 ctl_reg = PP_CONTROL;
de842eff 228 stat_reg = PP_STATUS;
541998a1 229 }
79e53945 230
7dec0606 231 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 232
2a1292fd 233 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 234 POSTING_READ(lvds_encoder->reg);
de842eff
KP
235 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
236 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 237
752aa88a 238 intel_panel_enable_backlight(intel_connector);
2a1292fd
CW
239}
240
c22834ec 241static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 242{
c22834ec 243 struct drm_device *dev = encoder->base.dev;
29b99b48 244 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 245 struct drm_i915_private *dev_priv = dev->dev_private;
f0f59a00 246 i915_reg_t ctl_reg, stat_reg;
2a1292fd
CW
247
248 if (HAS_PCH_SPLIT(dev)) {
249 ctl_reg = PCH_PP_CONTROL;
de842eff 250 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
251 } else {
252 ctl_reg = PP_CONTROL;
de842eff 253 stat_reg = PP_STATUS;
2a1292fd
CW
254 }
255
2a1292fd 256 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
257 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
258 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 259
7dec0606
DV
260 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
261 POSTING_READ(lvds_encoder->reg);
79e53945
JB
262}
263
d26a5b6e
VS
264static void gmch_disable_lvds(struct intel_encoder *encoder)
265{
266 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
267 struct intel_connector *intel_connector =
268 &lvds_encoder->attached_connector->base;
269
270 intel_panel_disable_backlight(intel_connector);
271
272 intel_disable_lvds(encoder);
273}
274
275static void pch_disable_lvds(struct intel_encoder *encoder)
276{
277 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
278 struct intel_connector *intel_connector =
279 &lvds_encoder->attached_connector->base;
280
281 intel_panel_disable_backlight(intel_connector);
282}
283
284static void pch_post_disable_lvds(struct intel_encoder *encoder)
285{
286 intel_disable_lvds(encoder);
287}
288
c19de8eb
DL
289static enum drm_mode_status
290intel_lvds_mode_valid(struct drm_connector *connector,
291 struct drm_display_mode *mode)
79e53945 292{
dd06f90e
JN
293 struct intel_connector *intel_connector = to_intel_connector(connector);
294 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
7f7b58cc 295 int max_pixclk = to_i915(connector->dev)->max_dotclk_freq;
79e53945 296
788319d4
CW
297 if (mode->hdisplay > fixed_mode->hdisplay)
298 return MODE_PANEL;
299 if (mode->vdisplay > fixed_mode->vdisplay)
300 return MODE_PANEL;
7f7b58cc
MK
301 if (fixed_mode->clock > max_pixclk)
302 return MODE_CLOCK_HIGH;
79e53945
JB
303
304 return MODE_OK;
305}
306
7ae89233 307static bool intel_lvds_compute_config(struct intel_encoder *intel_encoder,
5cec258b 308 struct intel_crtc_state *pipe_config)
79e53945 309{
7ae89233 310 struct drm_device *dev = intel_encoder->base.dev;
7ae89233
DV
311 struct intel_lvds_encoder *lvds_encoder =
312 to_lvds_encoder(&intel_encoder->base);
4d891523
JN
313 struct intel_connector *intel_connector =
314 &lvds_encoder->attached_connector->base;
2d112de7 315 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
d21bd67b 316 struct intel_crtc *intel_crtc = to_intel_crtc(pipe_config->base.crtc);
4e53c2e0 317 unsigned int lvds_bpp;
79e53945
JB
318
319 /* Should never happen!! */
a6c45cf0 320 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 321 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
322 return false;
323 }
324
1f835a77 325 if (lvds_encoder->a3_power == LVDS_A3_POWER_UP)
4e53c2e0
DV
326 lvds_bpp = 8*3;
327 else
328 lvds_bpp = 6*3;
329
e29c22c0 330 if (lvds_bpp != pipe_config->pipe_bpp && !pipe_config->bw_constrained) {
4e53c2e0
DV
331 DRM_DEBUG_KMS("forcing display bpp (was %d) to LVDS (%d)\n",
332 pipe_config->pipe_bpp, lvds_bpp);
333 pipe_config->pipe_bpp = lvds_bpp;
334 }
d8b32247 335
79e53945 336 /*
71677043 337 * We have timings from the BIOS for the panel, put them in
79e53945
JB
338 * to the adjusted mode. The CRTC will be set up for this mode,
339 * with the panel scaling set up to source from the H/VDisplay
340 * of the original mode.
341 */
4d891523 342 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 343 adjusted_mode);
1d8e1c75
CW
344
345 if (HAS_PCH_SPLIT(dev)) {
5bfe2ac0
DV
346 pipe_config->has_pch_encoder = true;
347
b074cec8
JB
348 intel_pch_panel_fitting(intel_crtc, pipe_config,
349 intel_connector->panel.fitting_mode);
2dd24552
JB
350 } else {
351 intel_gmch_panel_fitting(intel_crtc, pipe_config,
352 intel_connector->panel.fitting_mode);
79e53945 353
21d8a475 354 }
f9bef081 355
79e53945
JB
356 /*
357 * XXX: It would be nice to support lower refresh rates on the
358 * panels to reduce power consumption, and perhaps match the
359 * user's requested refresh rate.
360 */
361
362 return true;
363}
364
79e53945
JB
365/**
366 * Detect the LVDS connection.
367 *
b42d4c5c
JB
368 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
369 * connected and closed means disconnected. We also send hotplug events as
370 * needed, using lid status notification from the input layer.
79e53945 371 */
7b334fcb 372static enum drm_connector_status
930a9e28 373intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 374{
7b9c5abe 375 struct drm_device *dev = connector->dev;
6ee3b5a1 376 enum drm_connector_status status;
b42d4c5c 377
164c8598 378 DRM_DEBUG_KMS("[CONNECTOR:%d:%s]\n",
c23cc417 379 connector->base.id, connector->name);
164c8598 380
fe16d949
CW
381 status = intel_panel_detect(dev);
382 if (status != connector_status_unknown)
383 return status;
01fe9dbd 384
6ee3b5a1 385 return connector_status_connected;
79e53945
JB
386}
387
388/**
389 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
390 */
391static int intel_lvds_get_modes(struct drm_connector *connector)
392{
62165e0d 393 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 394 struct drm_device *dev = connector->dev;
788319d4 395 struct drm_display_mode *mode;
79e53945 396
9cd300e0 397 /* use cached edid if we have one */
2aa4f099 398 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 399 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 400
dd06f90e 401 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 402 if (mode == NULL)
788319d4 403 return 0;
79e53945 404
788319d4
CW
405 drm_mode_probed_add(connector, mode);
406 return 1;
79e53945
JB
407}
408
0544edfd
TB
409static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
410{
bc0daf48 411 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
412 return 1;
413}
414
415/* The GPU hangs up on these systems if modeset is performed on LID open */
416static const struct dmi_system_id intel_no_modeset_on_lid[] = {
417 {
418 .callback = intel_no_modeset_on_lid_dmi_callback,
419 .ident = "Toshiba Tecra A11",
420 .matches = {
421 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
422 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
423 },
424 },
425
426 { } /* terminating entry */
427};
428
c9354c85 429/*
b8efb17b
ZR
430 * Lid events. Note the use of 'modeset':
431 * - we set it to MODESET_ON_LID_OPEN on lid close,
432 * and set it to MODESET_DONE on open
c9354c85 433 * - we use it as a "only once" bit (ie we ignore
b8efb17b
ZR
434 * duplicate events where it was already properly set)
435 * - the suspend/resume paths will set it to
436 * MODESET_SUSPENDED and ignore the lid open event,
437 * because they restore the mode ("lid open").
c9354c85 438 */
c1c7af60
JB
439static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
440 void *unused)
441{
db1740a0
JN
442 struct intel_lvds_connector *lvds_connector =
443 container_of(nb, struct intel_lvds_connector, lid_notifier);
444 struct drm_connector *connector = &lvds_connector->base.base;
445 struct drm_device *dev = connector->dev;
446 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 447
2fb4e61d
AW
448 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
449 return NOTIFY_OK;
450
b8efb17b
ZR
451 mutex_lock(&dev_priv->modeset_restore_lock);
452 if (dev_priv->modeset_restore == MODESET_SUSPENDED)
453 goto exit;
a2565377
ZY
454 /*
455 * check and update the status of LVDS connector after receiving
456 * the LID nofication event.
457 */
db1740a0 458 connector->status = connector->funcs->detect(connector, false);
7b334fcb 459
0544edfd
TB
460 /* Don't force modeset on machines where it causes a GPU lockup */
461 if (dmi_check_system(intel_no_modeset_on_lid))
b8efb17b 462 goto exit;
c9354c85 463 if (!acpi_lid_open()) {
b8efb17b
ZR
464 /* do modeset on next lid open event */
465 dev_priv->modeset_restore = MODESET_ON_LID_OPEN;
466 goto exit;
06891e27 467 }
c1c7af60 468
b8efb17b
ZR
469 if (dev_priv->modeset_restore == MODESET_DONE)
470 goto exit;
c9354c85 471
5be19d91
DV
472 /*
473 * Some old platform's BIOS love to wreak havoc while the lid is closed.
474 * We try to detect this here and undo any damage. The split for PCH
475 * platforms is rather conservative and a bit arbitrary expect that on
476 * those platforms VGA disabling requires actual legacy VGA I/O access,
477 * and as part of the cleanup in the hw state restore we also redisable
478 * the vga plane.
479 */
480 if (!HAS_PCH_SPLIT(dev)) {
481 drm_modeset_lock_all(dev);
043e9bda 482 intel_display_resume(dev);
5be19d91
DV
483 drm_modeset_unlock_all(dev);
484 }
06324194 485
b8efb17b
ZR
486 dev_priv->modeset_restore = MODESET_DONE;
487
488exit:
489 mutex_unlock(&dev_priv->modeset_restore_lock);
c1c7af60
JB
490 return NOTIFY_OK;
491}
492
79e53945
JB
493/**
494 * intel_lvds_destroy - unregister and free LVDS structures
495 * @connector: connector to free
496 *
497 * Unregister the DDC bus for this connector then free the driver private
498 * structure.
499 */
500static void intel_lvds_destroy(struct drm_connector *connector)
501{
db1740a0
JN
502 struct intel_lvds_connector *lvds_connector =
503 to_lvds_connector(connector);
79e53945 504
db1740a0
JN
505 if (lvds_connector->lid_notifier.notifier_call)
506 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 507
9cd300e0
JN
508 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
509 kfree(lvds_connector->base.edid);
510
1d508706 511 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 512
79e53945
JB
513 drm_connector_cleanup(connector);
514 kfree(connector);
515}
516
335041ed
JB
517static int intel_lvds_set_property(struct drm_connector *connector,
518 struct drm_property *property,
519 uint64_t value)
520{
4d891523 521 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 522 struct drm_device *dev = connector->dev;
3fbe18d6 523
788319d4 524 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 525 struct drm_crtc *crtc;
bb8a3560 526
53bd8389
JB
527 if (value == DRM_MODE_SCALE_NONE) {
528 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 529 return -EINVAL;
3fbe18d6 530 }
788319d4 531
4d891523 532 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
533 /* the LVDS scaling property is not changed */
534 return 0;
535 }
4d891523 536 intel_connector->panel.fitting_mode = value;
62165e0d
JN
537
538 crtc = intel_attached_encoder(connector)->base.crtc;
83d65738 539 if (crtc && crtc->state->enable) {
3fbe18d6
ZY
540 /*
541 * If the CRTC is enabled, the display will be changed
542 * according to the new panel fitting mode.
543 */
c0c36b94 544 intel_crtc_restore_mode(crtc);
3fbe18d6
ZY
545 }
546 }
547
335041ed
JB
548 return 0;
549}
550
79e53945
JB
551static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
552 .get_modes = intel_lvds_get_modes,
553 .mode_valid = intel_lvds_mode_valid,
df0e9248 554 .best_encoder = intel_best_encoder,
79e53945
JB
555};
556
557static const struct drm_connector_funcs intel_lvds_connector_funcs = {
4d688a2a 558 .dpms = drm_atomic_helper_connector_dpms,
79e53945
JB
559 .detect = intel_lvds_detect,
560 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 561 .set_property = intel_lvds_set_property,
2545e4a6 562 .atomic_get_property = intel_connector_atomic_get_property,
79e53945 563 .destroy = intel_lvds_destroy,
c6f95f27 564 .atomic_destroy_state = drm_atomic_helper_connector_destroy_state,
98969725 565 .atomic_duplicate_state = drm_atomic_helper_connector_duplicate_state,
79e53945
JB
566};
567
79e53945 568static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 569 .destroy = intel_encoder_destroy,
79e53945
JB
570};
571
bbe1c274 572static int intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
425d244c 573{
bc0daf48 574 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
575 return 1;
576}
79e53945 577
425d244c 578/* These systems claim to have LVDS, but really don't */
93c05f22 579static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
580 {
581 .callback = intel_no_lvds_dmi_callback,
582 .ident = "Apple Mac Mini (Core series)",
583 .matches = {
98acd46f 584 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
585 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
586 },
587 },
588 {
589 .callback = intel_no_lvds_dmi_callback,
590 .ident = "Apple Mac Mini (Core 2 series)",
591 .matches = {
98acd46f 592 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
593 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
594 },
595 },
596 {
597 .callback = intel_no_lvds_dmi_callback,
598 .ident = "MSI IM-945GSE-A",
599 .matches = {
600 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
601 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
602 },
603 },
604 {
605 .callback = intel_no_lvds_dmi_callback,
606 .ident = "Dell Studio Hybrid",
607 .matches = {
608 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
609 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
610 },
611 },
70aa96ca
JW
612 {
613 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
614 .ident = "Dell OptiPlex FX170",
615 .matches = {
616 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
617 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
618 },
619 },
620 {
621 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
622 .ident = "AOpen Mini PC",
623 .matches = {
624 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
625 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
626 },
627 },
ed8c754b
TV
628 {
629 .callback = intel_no_lvds_dmi_callback,
630 .ident = "AOpen Mini PC MP915",
631 .matches = {
632 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
633 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
634 },
635 },
22ab70d3
KP
636 {
637 .callback = intel_no_lvds_dmi_callback,
638 .ident = "AOpen i915GMm-HFS",
639 .matches = {
640 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
641 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
642 },
643 },
e57b6886
DV
644 {
645 .callback = intel_no_lvds_dmi_callback,
646 .ident = "AOpen i45GMx-I",
647 .matches = {
648 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
649 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
650 },
651 },
fa0864b2
MC
652 {
653 .callback = intel_no_lvds_dmi_callback,
654 .ident = "Aopen i945GTt-VFA",
655 .matches = {
656 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
657 },
658 },
9875557e
SB
659 {
660 .callback = intel_no_lvds_dmi_callback,
661 .ident = "Clientron U800",
662 .matches = {
663 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
664 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
665 },
666 },
6a574b5b 667 {
44306ab3
JS
668 .callback = intel_no_lvds_dmi_callback,
669 .ident = "Clientron E830",
670 .matches = {
671 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
672 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
673 },
674 },
675 {
6a574b5b
HG
676 .callback = intel_no_lvds_dmi_callback,
677 .ident = "Asus EeeBox PC EB1007",
678 .matches = {
679 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
680 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
681 },
682 },
0999bbe0
AJ
683 {
684 .callback = intel_no_lvds_dmi_callback,
685 .ident = "Asus AT5NM10T-I",
686 .matches = {
687 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
688 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
689 },
690 },
33471119
JBG
691 {
692 .callback = intel_no_lvds_dmi_callback,
45a211d7 693 .ident = "Hewlett-Packard HP t5740",
33471119
JBG
694 .matches = {
695 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
45a211d7 696 DMI_MATCH(DMI_PRODUCT_NAME, " t5740"),
33471119
JBG
697 },
698 },
f5b8a7ed
MG
699 {
700 .callback = intel_no_lvds_dmi_callback,
701 .ident = "Hewlett-Packard t5745",
702 .matches = {
703 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 704 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
705 },
706 },
707 {
708 .callback = intel_no_lvds_dmi_callback,
709 .ident = "Hewlett-Packard st5747",
710 .matches = {
711 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 712 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
713 },
714 },
97effadb
AA
715 {
716 .callback = intel_no_lvds_dmi_callback,
717 .ident = "MSI Wind Box DC500",
718 .matches = {
719 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
720 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
721 },
722 },
a51d4ed0
CW
723 {
724 .callback = intel_no_lvds_dmi_callback,
725 .ident = "Gigabyte GA-D525TUD",
726 .matches = {
727 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
728 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
729 },
730 },
c31407a3
CW
731 {
732 .callback = intel_no_lvds_dmi_callback,
733 .ident = "Supermicro X7SPA-H",
734 .matches = {
735 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
736 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
737 },
738 },
9e9dd0e8
CL
739 {
740 .callback = intel_no_lvds_dmi_callback,
741 .ident = "Fujitsu Esprimo Q900",
742 .matches = {
743 DMI_MATCH(DMI_SYS_VENDOR, "FUJITSU"),
744 DMI_MATCH(DMI_PRODUCT_NAME, "ESPRIMO Q900"),
745 },
746 },
645378d8
RP
747 {
748 .callback = intel_no_lvds_dmi_callback,
749 .ident = "Intel D410PT",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
752 DMI_MATCH(DMI_BOARD_NAME, "D410PT"),
753 },
754 },
755 {
756 .callback = intel_no_lvds_dmi_callback,
757 .ident = "Intel D425KT",
758 .matches = {
759 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
760 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D425KT"),
761 },
762 },
e5614f0c
CW
763 {
764 .callback = intel_no_lvds_dmi_callback,
765 .ident = "Intel D510MO",
766 .matches = {
767 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
768 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D510MO"),
769 },
770 },
dcf6d294
JN
771 {
772 .callback = intel_no_lvds_dmi_callback,
773 .ident = "Intel D525MW",
774 .matches = {
775 DMI_MATCH(DMI_BOARD_VENDOR, "Intel"),
776 DMI_EXACT_MATCH(DMI_BOARD_NAME, "D525MW"),
777 },
778 },
425d244c
JW
779
780 { } /* terminating entry */
781};
79e53945 782
7cf4f69d
ZY
783/*
784 * Enumerate the child dev array parsed from VBT to check whether
785 * the LVDS is present.
786 * If it is present, return 1.
787 * If it is not present, return false.
788 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 789 */
270eea0f
CW
790static bool lvds_is_present_in_vbt(struct drm_device *dev,
791 u8 *i2c_pin)
7cf4f69d
ZY
792{
793 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 794 int i;
7cf4f69d 795
41aa3448 796 if (!dev_priv->vbt.child_dev_num)
425904dd 797 return true;
7cf4f69d 798
41aa3448 799 for (i = 0; i < dev_priv->vbt.child_dev_num; i++) {
768f69c9
PZ
800 union child_device_config *uchild = dev_priv->vbt.child_dev + i;
801 struct old_child_dev_config *child = &uchild->old;
425904dd
CW
802
803 /* If the device type is not LFP, continue.
804 * We have to check both the new identifiers as well as the
805 * old for compatibility with some BIOSes.
7cf4f69d 806 */
425904dd
CW
807 if (child->device_type != DEVICE_TYPE_INT_LFP &&
808 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
809 continue;
810
88ac7939 811 if (intel_gmbus_is_valid_pin(dev_priv, child->i2c_pin))
3bd7d909 812 *i2c_pin = child->i2c_pin;
270eea0f 813
425904dd
CW
814 /* However, we cannot trust the BIOS writers to populate
815 * the VBT correctly. Since LVDS requires additional
816 * information from AIM blocks, a non-zero addin offset is
817 * a good indicator that the LVDS is actually present.
7cf4f69d 818 */
425904dd
CW
819 if (child->addin_offset)
820 return true;
821
822 /* But even then some BIOS writers perform some black magic
823 * and instantiate the device without reference to any
824 * additional data. Trust that if the VBT was written into
825 * the OpRegion then they have validated the LVDS's existence.
826 */
827 if (dev_priv->opregion.vbt)
828 return true;
7cf4f69d 829 }
425904dd
CW
830
831 return false;
7cf4f69d
ZY
832}
833
1974cad0
DV
834static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
835{
836 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
837 return 1;
838}
839
840static const struct dmi_system_id intel_dual_link_lvds[] = {
841 {
842 .callback = intel_dual_link_lvds_callback,
3916e3fd
LW
843 .ident = "Apple MacBook Pro 15\" (2010)",
844 .matches = {
845 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
846 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro6,2"),
847 },
848 },
849 {
850 .callback = intel_dual_link_lvds_callback,
851 .ident = "Apple MacBook Pro 15\" (2011)",
1974cad0
DV
852 .matches = {
853 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
854 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
855 },
856 },
3916e3fd
LW
857 {
858 .callback = intel_dual_link_lvds_callback,
859 .ident = "Apple MacBook Pro 15\" (2012)",
860 .matches = {
861 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
862 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro9,1"),
863 },
864 },
1974cad0
DV
865 { } /* terminating entry */
866};
867
868bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
869{
870 struct intel_encoder *encoder;
871 struct intel_lvds_encoder *lvds_encoder;
872
b2784e15 873 for_each_intel_encoder(dev, encoder) {
13c7d870
DV
874 if (encoder->type == INTEL_OUTPUT_LVDS) {
875 lvds_encoder = to_lvds_encoder(&encoder->base);
876
877 return lvds_encoder->is_dual_link;
878 }
879 }
880
881 return false;
882}
883
7dec0606 884static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 885{
7dec0606 886 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
887 unsigned int val;
888 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
889
890 /* use the module option value if specified */
d330a953
JN
891 if (i915.lvds_channel_mode > 0)
892 return i915.lvds_channel_mode == 2;
1974cad0 893
6f317cfe
LW
894 /* single channel LVDS is limited to 112 MHz */
895 if (lvds_encoder->attached_connector->base.panel.fixed_mode->clock
896 > 112999)
897 return true;
898
1974cad0
DV
899 if (dmi_check_system(intel_dual_link_lvds))
900 return true;
901
13c7d870
DV
902 /* BIOS should set the proper LVDS register value at boot, but
903 * in reality, it doesn't set the value when the lid is closed;
904 * we need to check "the value to be set" in VBT when LVDS
905 * register is uninitialized.
906 */
7dec0606 907 val = I915_READ(lvds_encoder->reg);
13c7d870 908 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
41aa3448 909 val = dev_priv->vbt.bios_lvds_val;
13c7d870 910
1974cad0
DV
911 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
912}
913
f3cfcba6
CW
914static bool intel_lvds_supported(struct drm_device *dev)
915{
916 /* With the introduction of the PCH we gained a dedicated
917 * LVDS presence pin, use it. */
311e359c 918 if (HAS_PCH_IBX(dev) || HAS_PCH_CPT(dev))
f3cfcba6
CW
919 return true;
920
921 /* Otherwise LVDS was only attached to mobile products,
922 * except for the inglorious 830gm */
311e359c
PZ
923 if (INTEL_INFO(dev)->gen <= 4 && IS_MOBILE(dev) && !IS_I830(dev))
924 return true;
925
926 return false;
f3cfcba6
CW
927}
928
79e53945
JB
929/**
930 * intel_lvds_init - setup LVDS connectors on this device
931 * @dev: drm device
932 *
933 * Create the connector, register the LVDS DDC bus, and try to figure out what
934 * modes we can display on the LVDS panel (if present).
935 */
c9093354 936void intel_lvds_init(struct drm_device *dev)
79e53945
JB
937{
938 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 939 struct intel_lvds_encoder *lvds_encoder;
21d40d37 940 struct intel_encoder *intel_encoder;
c7362c4d 941 struct intel_lvds_connector *lvds_connector;
bb8a3560 942 struct intel_connector *intel_connector;
79e53945
JB
943 struct drm_connector *connector;
944 struct drm_encoder *encoder;
945 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 946 struct drm_display_mode *fixed_mode = NULL;
4b6ed685 947 struct drm_display_mode *downclock_mode = NULL;
9cd300e0 948 struct edid *edid;
79e53945 949 struct drm_crtc *crtc;
f0f59a00 950 i915_reg_t lvds_reg;
79e53945 951 u32 lvds;
270eea0f
CW
952 int pipe;
953 u8 pin;
79e53945 954
b0616c53
DV
955 /*
956 * Unlock registers and just leave them unlocked. Do this before
957 * checking quirk lists to avoid bogus WARNINGs.
958 */
959 if (HAS_PCH_SPLIT(dev)) {
960 I915_WRITE(PCH_PP_CONTROL,
961 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
c5796b71 962 } else if (INTEL_INFO(dev_priv)->gen < 5) {
b0616c53
DV
963 I915_WRITE(PP_CONTROL,
964 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
965 }
f3cfcba6 966 if (!intel_lvds_supported(dev))
c9093354 967 return;
f3cfcba6 968
425d244c
JW
969 /* Skip init on machines we know falsely report LVDS */
970 if (dmi_check_system(intel_no_lvds))
c9093354 971 return;
565dcd46 972
d0669d00
VS
973 if (HAS_PCH_SPLIT(dev))
974 lvds_reg = PCH_LVDS;
975 else
976 lvds_reg = LVDS;
977
978 lvds = I915_READ(lvds_reg);
979
c619eed4 980 if (HAS_PCH_SPLIT(dev)) {
d0669d00 981 if ((lvds & LVDS_DETECTED) == 0)
c9093354 982 return;
41aa3448 983 if (dev_priv->vbt.edp_support) {
28c97730 984 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c9093354 985 return;
32f9d658 986 }
541998a1
ZW
987 }
988
eebaed64
CW
989 pin = GMBUS_PIN_PANEL;
990 if (!lvds_is_present_in_vbt(dev, &pin)) {
d0669d00 991 if ((lvds & LVDS_PORT_EN) == 0) {
eebaed64
CW
992 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
993 return;
994 }
995 DRM_DEBUG_KMS("LVDS is not present in VBT, but enabled anyway\n");
996 }
997
96d12cbd
ID
998 /* Set the Panel Power On/Off timings if uninitialized. */
999 if (INTEL_INFO(dev_priv)->gen < 5 &&
1000 I915_READ(PP_ON_DELAYS) == 0 && I915_READ(PP_OFF_DELAYS) == 0) {
1001 /* Set T2 to 40ms and T5 to 200ms */
1002 I915_WRITE(PP_ON_DELAYS, 0x019007d0);
1003
1004 /* Set T3 to 35ms and Tx to 200ms */
1005 I915_WRITE(PP_OFF_DELAYS, 0x015e07d0);
1006
1007 DRM_DEBUG_KMS("Panel power timings uninitialized, setting defaults\n");
1008 }
1009
b14c5679 1010 lvds_encoder = kzalloc(sizeof(*lvds_encoder), GFP_KERNEL);
29b99b48 1011 if (!lvds_encoder)
c9093354 1012 return;
79e53945 1013
b14c5679 1014 lvds_connector = kzalloc(sizeof(*lvds_connector), GFP_KERNEL);
c7362c4d 1015 if (!lvds_connector) {
29b99b48 1016 kfree(lvds_encoder);
c9093354 1017 return;
bb8a3560
ZW
1018 }
1019
9bdbd0b9
ACO
1020 if (intel_connector_init(&lvds_connector->base) < 0) {
1021 kfree(lvds_connector);
1022 kfree(lvds_encoder);
1023 return;
1024 }
1025
62165e0d
JN
1026 lvds_encoder->attached_connector = lvds_connector;
1027
29b99b48 1028 intel_encoder = &lvds_encoder->base;
4ef69c7a 1029 encoder = &intel_encoder->base;
c7362c4d 1030 intel_connector = &lvds_connector->base;
ea5b213a 1031 connector = &intel_connector->base;
bb8a3560 1032 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
1033 DRM_MODE_CONNECTOR_LVDS);
1034
4ef69c7a 1035 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
13a3d91f 1036 DRM_MODE_ENCODER_LVDS, NULL);
79e53945 1037
c22834ec 1038 intel_encoder->enable = intel_enable_lvds;
f6736a1a 1039 intel_encoder->pre_enable = intel_pre_enable_lvds;
7ae89233 1040 intel_encoder->compute_config = intel_lvds_compute_config;
d26a5b6e
VS
1041 if (HAS_PCH_SPLIT(dev_priv)) {
1042 intel_encoder->disable = pch_disable_lvds;
1043 intel_encoder->post_disable = pch_post_disable_lvds;
1044 } else {
1045 intel_encoder->disable = gmch_disable_lvds;
1046 }
b1dc332c 1047 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
045ac3b5 1048 intel_encoder->get_config = intel_lvds_get_config;
b1dc332c 1049 intel_connector->get_hw_state = intel_connector_get_hw_state;
4932e2c3 1050 intel_connector->unregister = intel_connector_unregister;
c22834ec 1051
df0e9248 1052 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1053 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1054
bc079e8b 1055 intel_encoder->cloneable = 0;
27f8227b
JB
1056 if (HAS_PCH_SPLIT(dev))
1057 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1058 else if (IS_GEN4(dev))
1059 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1060 else
1061 intel_encoder->crtc_mask = (1 << 1);
1062
79e53945
JB
1063 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1064 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1065 connector->interlace_allowed = false;
1066 connector->doublescan_allowed = false;
1067
d0669d00 1068 lvds_encoder->reg = lvds_reg;
7dec0606 1069
3fbe18d6
ZY
1070 /* create the scaling mode property */
1071 drm_mode_create_scaling_mode_property(dev);
662595df 1072 drm_object_attach_property(&connector->base,
3fbe18d6 1073 dev->mode_config.scaling_mode_property,
dd1ea37d 1074 DRM_MODE_SCALE_ASPECT);
4d891523 1075 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1076 /*
1077 * LVDS discovery:
1078 * 1) check for EDID on DDC
1079 * 2) check for VBT data
1080 * 3) check to see if LVDS is already on
1081 * if none of the above, no panel
1082 * 4) make sure lid is open
1083 * if closed, act like it's not there for now
1084 */
1085
79e53945
JB
1086 /*
1087 * Attempt to get the fixed panel mode from DDC. Assume that the
1088 * preferred mode is the right one.
1089 */
4da98541 1090 mutex_lock(&dev->mode_config.mutex);
9cd300e0
JN
1091 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1092 if (edid) {
1093 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1094 drm_mode_connector_update_edid_property(connector,
9cd300e0 1095 edid);
3f8ff0e7 1096 } else {
9cd300e0
JN
1097 kfree(edid);
1098 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1099 }
9cd300e0
JN
1100 } else {
1101 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1102 }
9cd300e0
JN
1103 lvds_connector->base.edid = edid;
1104
1105 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1106 /* Didn't get an EDID, so
1107 * Set wide sync ranges so we get all modes
1108 * handed to valid_mode for checking
1109 */
1110 connector->display_info.min_vfreq = 0;
1111 connector->display_info.max_vfreq = 200;
1112 connector->display_info.min_hfreq = 0;
1113 connector->display_info.max_hfreq = 200;
1114 }
79e53945
JB
1115
1116 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1117 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1118 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1119 drm_mode_debug_printmodeline(scan);
1120
dd06f90e 1121 fixed_mode = drm_mode_duplicate(dev, scan);
c329a4ec 1122 if (fixed_mode)
6a9d51b7 1123 goto out;
79e53945 1124 }
79e53945
JB
1125 }
1126
1127 /* Failed to get EDID, what about VBT? */
41aa3448 1128 if (dev_priv->vbt.lfp_lvds_vbt_mode) {
6a9d51b7 1129 DRM_DEBUG_KMS("using mode from VBT: ");
41aa3448 1130 drm_mode_debug_printmodeline(dev_priv->vbt.lfp_lvds_vbt_mode);
6a9d51b7 1131
41aa3448 1132 fixed_mode = drm_mode_duplicate(dev, dev_priv->vbt.lfp_lvds_vbt_mode);
dd06f90e
JN
1133 if (fixed_mode) {
1134 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1135 goto out;
1136 }
79e53945
JB
1137 }
1138
1139 /*
1140 * If we didn't get EDID, try checking if the panel is already turned
1141 * on. If so, assume that whatever is currently programmed is the
1142 * correct mode.
1143 */
541998a1 1144
f2b115e6 1145 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1146 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1147 goto failed;
1148
79e53945 1149 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1150 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1151
1152 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1153 fixed_mode = intel_crtc_mode_get(dev, crtc);
1154 if (fixed_mode) {
6a9d51b7
CW
1155 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1156 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1157 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1158 goto out;
79e53945
JB
1159 }
1160 }
1161
1162 /* If we still don't have a mode after all that, give up. */
dd06f90e 1163 if (!fixed_mode)
79e53945
JB
1164 goto failed;
1165
79e53945 1166out:
4da98541
DV
1167 mutex_unlock(&dev->mode_config.mutex);
1168
6f317cfe
LW
1169 intel_panel_init(&intel_connector->panel, fixed_mode, downclock_mode);
1170
7dec0606 1171 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1172 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1173 lvds_encoder->is_dual_link ? "dual" : "single");
1174
af9b9c19 1175 lvds_encoder->a3_power = lvds & LVDS_A3_POWER_MASK;
1f835a77 1176
db1740a0
JN
1177 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1178 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1179 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1180 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1181 }
34ea3d38 1182 drm_connector_register(connector);
aaa6fd2a 1183
6517d273 1184 intel_panel_setup_backlight(connector, INVALID_PIPE);
aaa6fd2a 1185
c9093354 1186 return;
79e53945
JB
1187
1188failed:
4da98541
DV
1189 mutex_unlock(&dev->mode_config.mutex);
1190
8a4c47f3 1191 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1192 drm_connector_cleanup(connector);
1991bdfa 1193 drm_encoder_cleanup(encoder);
29b99b48 1194 kfree(lvds_encoder);
c7362c4d 1195 kfree(lvds_connector);
c9093354 1196 return;
79e53945 1197}