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79e53945 JB |
1 | /* |
2 | * Copyright © 2006-2007 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | */ | |
29 | ||
c1c7af60 | 30 | #include <acpi/button.h> |
565dcd46 | 31 | #include <linux/dmi.h> |
79e53945 | 32 | #include <linux/i2c.h> |
5a0e3ad6 | 33 | #include <linux/slab.h> |
79e53945 JB |
34 | #include "drmP.h" |
35 | #include "drm.h" | |
36 | #include "drm_crtc.h" | |
37 | #include "drm_edid.h" | |
38 | #include "intel_drv.h" | |
39 | #include "i915_drm.h" | |
40 | #include "i915_drv.h" | |
e99da35f | 41 | #include <linux/acpi.h> |
79e53945 | 42 | |
3fbe18d6 | 43 | /* Private structure for the integrated LVDS support */ |
ea5b213a CW |
44 | struct intel_lvds { |
45 | struct intel_encoder base; | |
788319d4 | 46 | |
219adae1 | 47 | struct edid *edid; |
788319d4 | 48 | |
3fbe18d6 ZY |
49 | int fitting_mode; |
50 | u32 pfit_control; | |
51 | u32 pfit_pgm_ratios; | |
e9e331a8 | 52 | bool pfit_dirty; |
788319d4 CW |
53 | |
54 | struct drm_display_mode *fixed_mode; | |
3fbe18d6 ZY |
55 | }; |
56 | ||
788319d4 | 57 | static struct intel_lvds *to_intel_lvds(struct drm_encoder *encoder) |
ea5b213a | 58 | { |
4ef69c7a | 59 | return container_of(encoder, struct intel_lvds, base.base); |
ea5b213a CW |
60 | } |
61 | ||
788319d4 CW |
62 | static struct intel_lvds *intel_attached_lvds(struct drm_connector *connector) |
63 | { | |
64 | return container_of(intel_attached_encoder(connector), | |
65 | struct intel_lvds, base); | |
66 | } | |
67 | ||
79e53945 JB |
68 | /** |
69 | * Sets the power state for the panel. | |
70 | */ | |
e9e331a8 | 71 | static void intel_lvds_set_power(struct intel_lvds *intel_lvds, bool on) |
79e53945 | 72 | { |
e9e331a8 | 73 | struct drm_device *dev = intel_lvds->base.base.dev; |
79e53945 | 74 | struct drm_i915_private *dev_priv = dev->dev_private; |
e9e331a8 | 75 | u32 ctl_reg, lvds_reg; |
541998a1 | 76 | |
c619eed4 | 77 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 78 | ctl_reg = PCH_PP_CONTROL; |
469d1296 | 79 | lvds_reg = PCH_LVDS; |
541998a1 ZW |
80 | } else { |
81 | ctl_reg = PP_CONTROL; | |
469d1296 | 82 | lvds_reg = LVDS; |
541998a1 | 83 | } |
79e53945 JB |
84 | |
85 | if (on) { | |
469d1296 | 86 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) | LVDS_PORT_EN); |
77d07fd9 | 87 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON); |
a9573556 | 88 | intel_panel_set_backlight(dev, dev_priv->backlight_level); |
79e53945 | 89 | } else { |
e9e331a8 CW |
90 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
91 | ||
a9573556 | 92 | intel_panel_set_backlight(dev, 0); |
77d07fd9 | 93 | I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON); |
e9e331a8 CW |
94 | |
95 | if (intel_lvds->pfit_control) { | |
96 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) | |
97 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
98 | I915_WRITE(PFIT_CONTROL, 0); | |
99 | intel_lvds->pfit_control = 0; | |
4fd21dc8 | 100 | intel_lvds->pfit_dirty = false; |
e9e331a8 CW |
101 | } |
102 | ||
469d1296 | 103 | I915_WRITE(lvds_reg, I915_READ(lvds_reg) & ~LVDS_PORT_EN); |
79e53945 | 104 | } |
c9f9ccc1 | 105 | POSTING_READ(lvds_reg); |
79e53945 JB |
106 | } |
107 | ||
108 | static void intel_lvds_dpms(struct drm_encoder *encoder, int mode) | |
109 | { | |
788319d4 | 110 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
111 | |
112 | if (mode == DRM_MODE_DPMS_ON) | |
e9e331a8 | 113 | intel_lvds_set_power(intel_lvds, true); |
79e53945 | 114 | else |
e9e331a8 | 115 | intel_lvds_set_power(intel_lvds, false); |
79e53945 JB |
116 | |
117 | /* XXX: We never power down the LVDS pairs. */ | |
118 | } | |
119 | ||
79e53945 JB |
120 | static int intel_lvds_mode_valid(struct drm_connector *connector, |
121 | struct drm_display_mode *mode) | |
122 | { | |
788319d4 CW |
123 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
124 | struct drm_display_mode *fixed_mode = intel_lvds->fixed_mode; | |
79e53945 | 125 | |
788319d4 CW |
126 | if (mode->hdisplay > fixed_mode->hdisplay) |
127 | return MODE_PANEL; | |
128 | if (mode->vdisplay > fixed_mode->vdisplay) | |
129 | return MODE_PANEL; | |
79e53945 JB |
130 | |
131 | return MODE_OK; | |
132 | } | |
133 | ||
49be663f CW |
134 | static void |
135 | centre_horizontally(struct drm_display_mode *mode, | |
136 | int width) | |
137 | { | |
138 | u32 border, sync_pos, blank_width, sync_width; | |
139 | ||
140 | /* keep the hsync and hblank widths constant */ | |
141 | sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start; | |
142 | blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start; | |
143 | sync_pos = (blank_width - sync_width + 1) / 2; | |
144 | ||
145 | border = (mode->hdisplay - width + 1) / 2; | |
146 | border += border & 1; /* make the border even */ | |
147 | ||
148 | mode->crtc_hdisplay = width; | |
149 | mode->crtc_hblank_start = width + border; | |
150 | mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width; | |
151 | ||
152 | mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos; | |
153 | mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width; | |
154 | } | |
155 | ||
156 | static void | |
157 | centre_vertically(struct drm_display_mode *mode, | |
158 | int height) | |
159 | { | |
160 | u32 border, sync_pos, blank_width, sync_width; | |
161 | ||
162 | /* keep the vsync and vblank widths constant */ | |
163 | sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start; | |
164 | blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start; | |
165 | sync_pos = (blank_width - sync_width + 1) / 2; | |
166 | ||
167 | border = (mode->vdisplay - height + 1) / 2; | |
168 | ||
169 | mode->crtc_vdisplay = height; | |
170 | mode->crtc_vblank_start = height + border; | |
171 | mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width; | |
172 | ||
173 | mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos; | |
174 | mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width; | |
175 | } | |
176 | ||
177 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
178 | { | |
179 | /* | |
180 | * Floating point operation is not supported. So the FACTOR | |
181 | * is defined, which can avoid the floating point computation | |
182 | * when calculating the panel ratio. | |
183 | */ | |
184 | #define ACCURACY 12 | |
185 | #define FACTOR (1 << ACCURACY) | |
186 | u32 ratio = source * FACTOR / target; | |
187 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
188 | } | |
189 | ||
79e53945 JB |
190 | static bool intel_lvds_mode_fixup(struct drm_encoder *encoder, |
191 | struct drm_display_mode *mode, | |
192 | struct drm_display_mode *adjusted_mode) | |
193 | { | |
194 | struct drm_device *dev = encoder->dev; | |
195 | struct drm_i915_private *dev_priv = dev->dev_private; | |
196 | struct intel_crtc *intel_crtc = to_intel_crtc(encoder->crtc); | |
788319d4 | 197 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 198 | struct drm_encoder *tmp_encoder; |
49be663f | 199 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
79e53945 JB |
200 | |
201 | /* Should never happen!! */ | |
a6c45cf0 | 202 | if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) { |
1ae8c0a5 | 203 | DRM_ERROR("Can't support LVDS on pipe A\n"); |
79e53945 JB |
204 | return false; |
205 | } | |
206 | ||
207 | /* Should never happen!! */ | |
208 | list_for_each_entry(tmp_encoder, &dev->mode_config.encoder_list, head) { | |
209 | if (tmp_encoder != encoder && tmp_encoder->crtc == encoder->crtc) { | |
1ae8c0a5 | 210 | DRM_ERROR("Can't enable LVDS and another " |
79e53945 JB |
211 | "encoder on the same pipe\n"); |
212 | return false; | |
213 | } | |
214 | } | |
1d8e1c75 | 215 | |
79e53945 | 216 | /* |
71677043 | 217 | * We have timings from the BIOS for the panel, put them in |
79e53945 JB |
218 | * to the adjusted mode. The CRTC will be set up for this mode, |
219 | * with the panel scaling set up to source from the H/VDisplay | |
220 | * of the original mode. | |
221 | */ | |
788319d4 | 222 | intel_fixed_panel_mode(intel_lvds->fixed_mode, adjusted_mode); |
1d8e1c75 CW |
223 | |
224 | if (HAS_PCH_SPLIT(dev)) { | |
225 | intel_pch_panel_fitting(dev, intel_lvds->fitting_mode, | |
226 | mode, adjusted_mode); | |
227 | return true; | |
228 | } | |
79e53945 | 229 | |
3fbe18d6 | 230 | /* Make sure pre-965s set dither correctly */ |
a6c45cf0 | 231 | if (INTEL_INFO(dev)->gen < 4) { |
d3849ede | 232 | if (dev_priv->lvds_dither) |
3fbe18d6 ZY |
233 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
234 | } | |
235 | ||
236 | /* Native modes don't need fitting */ | |
237 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
49be663f | 238 | adjusted_mode->vdisplay == mode->vdisplay) |
3fbe18d6 | 239 | goto out; |
3fbe18d6 ZY |
240 | |
241 | /* 965+ wants fuzzy fitting */ | |
a6c45cf0 | 242 | if (INTEL_INFO(dev)->gen >= 4) |
49be663f CW |
243 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
244 | PFIT_FILTER_FUZZY); | |
245 | ||
3fbe18d6 ZY |
246 | /* |
247 | * Enable automatic panel scaling for non-native modes so that they fill | |
248 | * the screen. Should be enabled before the pipe is enabled, according | |
249 | * to register description and PRM. | |
250 | * Change the value here to see the borders for debugging | |
251 | */ | |
1d8e1c75 CW |
252 | I915_WRITE(BCLRPAT_A, 0); |
253 | I915_WRITE(BCLRPAT_B, 0); | |
3fbe18d6 | 254 | |
ea5b213a | 255 | switch (intel_lvds->fitting_mode) { |
53bd8389 | 256 | case DRM_MODE_SCALE_CENTER: |
3fbe18d6 ZY |
257 | /* |
258 | * For centered modes, we have to calculate border widths & | |
259 | * heights and modify the values programmed into the CRTC. | |
260 | */ | |
49be663f CW |
261 | centre_horizontally(adjusted_mode, mode->hdisplay); |
262 | centre_vertically(adjusted_mode, mode->vdisplay); | |
263 | border = LVDS_BORDER_ENABLE; | |
3fbe18d6 | 264 | break; |
49be663f | 265 | |
3fbe18d6 | 266 | case DRM_MODE_SCALE_ASPECT: |
49be663f | 267 | /* Scale but preserve the aspect ratio */ |
a6c45cf0 | 268 | if (INTEL_INFO(dev)->gen >= 4) { |
49be663f CW |
269 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
270 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
271 | ||
3fbe18d6 | 272 | /* 965+ is easy, it does everything in hw */ |
49be663f | 273 | if (scaled_width > scaled_height) |
257e48f1 | 274 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR; |
49be663f | 275 | else if (scaled_width < scaled_height) |
257e48f1 CW |
276 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER; |
277 | else if (adjusted_mode->hdisplay != mode->hdisplay) | |
278 | pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; | |
3fbe18d6 | 279 | } else { |
49be663f CW |
280 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; |
281 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
3fbe18d6 ZY |
282 | /* |
283 | * For earlier chips we have to calculate the scaling | |
284 | * ratio by hand and program it into the | |
285 | * PFIT_PGM_RATIO register | |
286 | */ | |
49be663f CW |
287 | if (scaled_width > scaled_height) { /* pillar */ |
288 | centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay); | |
289 | ||
290 | border = LVDS_BORDER_ENABLE; | |
291 | if (mode->vdisplay != adjusted_mode->vdisplay) { | |
292 | u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay); | |
293 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
294 | bits << PFIT_VERT_SCALE_SHIFT); | |
295 | pfit_control |= (PFIT_ENABLE | | |
296 | VERT_INTERP_BILINEAR | | |
297 | HORIZ_INTERP_BILINEAR); | |
298 | } | |
299 | } else if (scaled_width < scaled_height) { /* letter */ | |
300 | centre_vertically(adjusted_mode, scaled_width / mode->hdisplay); | |
301 | ||
302 | border = LVDS_BORDER_ENABLE; | |
303 | if (mode->hdisplay != adjusted_mode->hdisplay) { | |
304 | u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay); | |
305 | pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
306 | bits << PFIT_VERT_SCALE_SHIFT); | |
307 | pfit_control |= (PFIT_ENABLE | | |
308 | VERT_INTERP_BILINEAR | | |
309 | HORIZ_INTERP_BILINEAR); | |
310 | } | |
311 | } else | |
312 | /* Aspects match, Let hw scale both directions */ | |
313 | pfit_control |= (PFIT_ENABLE | | |
314 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
3fbe18d6 ZY |
315 | VERT_INTERP_BILINEAR | |
316 | HORIZ_INTERP_BILINEAR); | |
3fbe18d6 ZY |
317 | } |
318 | break; | |
319 | ||
320 | case DRM_MODE_SCALE_FULLSCREEN: | |
321 | /* | |
322 | * Full scaling, even if it changes the aspect ratio. | |
323 | * Fortunately this is all done for us in hw. | |
324 | */ | |
257e48f1 CW |
325 | if (mode->vdisplay != adjusted_mode->vdisplay || |
326 | mode->hdisplay != adjusted_mode->hdisplay) { | |
327 | pfit_control |= PFIT_ENABLE; | |
328 | if (INTEL_INFO(dev)->gen >= 4) | |
329 | pfit_control |= PFIT_SCALING_AUTO; | |
330 | else | |
331 | pfit_control |= (VERT_AUTO_SCALE | | |
332 | VERT_INTERP_BILINEAR | | |
333 | HORIZ_AUTO_SCALE | | |
334 | HORIZ_INTERP_BILINEAR); | |
335 | } | |
3fbe18d6 | 336 | break; |
49be663f | 337 | |
3fbe18d6 ZY |
338 | default: |
339 | break; | |
340 | } | |
341 | ||
342 | out: | |
e9e331a8 CW |
343 | if (pfit_control != intel_lvds->pfit_control || |
344 | pfit_pgm_ratios != intel_lvds->pfit_pgm_ratios) { | |
345 | intel_lvds->pfit_control = pfit_control; | |
346 | intel_lvds->pfit_pgm_ratios = pfit_pgm_ratios; | |
347 | intel_lvds->pfit_dirty = true; | |
348 | } | |
49be663f CW |
349 | dev_priv->lvds_border_bits = border; |
350 | ||
79e53945 JB |
351 | /* |
352 | * XXX: It would be nice to support lower refresh rates on the | |
353 | * panels to reduce power consumption, and perhaps match the | |
354 | * user's requested refresh rate. | |
355 | */ | |
356 | ||
357 | return true; | |
358 | } | |
359 | ||
360 | static void intel_lvds_prepare(struct drm_encoder *encoder) | |
361 | { | |
362 | struct drm_device *dev = encoder->dev; | |
363 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 364 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 365 | |
a9573556 | 366 | dev_priv->backlight_level = intel_panel_get_backlight(dev); |
79e53945 | 367 | |
e9e331a8 CW |
368 | /* We try to do the minimum that is necessary in order to unlock |
369 | * the registers for mode setting. | |
370 | * | |
371 | * On Ironlake, this is quite simple as we just set the unlock key | |
372 | * and ignore all subtleties. (This may cause some issues...) | |
373 | * | |
374 | * Prior to Ironlake, we must disable the pipe if we want to adjust | |
375 | * the panel fitter. However at all other times we can just reset | |
376 | * the registers regardless. | |
377 | */ | |
378 | ||
379 | if (HAS_PCH_SPLIT(dev)) { | |
380 | I915_WRITE(PCH_PP_CONTROL, | |
381 | I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS); | |
382 | } else if (intel_lvds->pfit_dirty) { | |
383 | I915_WRITE(PP_CONTROL, | |
4fd21dc8 CW |
384 | (I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS) |
385 | & ~POWER_TARGET_ON); | |
e9e331a8 CW |
386 | } else { |
387 | I915_WRITE(PP_CONTROL, | |
388 | I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS); | |
389 | } | |
79e53945 JB |
390 | } |
391 | ||
e9e331a8 | 392 | static void intel_lvds_commit(struct drm_encoder *encoder) |
79e53945 JB |
393 | { |
394 | struct drm_device *dev = encoder->dev; | |
395 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 396 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 | 397 | |
a9573556 CW |
398 | if (dev_priv->backlight_level == 0) |
399 | dev_priv->backlight_level = intel_panel_get_max_backlight(dev); | |
79e53945 | 400 | |
e9e331a8 CW |
401 | /* Undo any unlocking done in prepare to prevent accidental |
402 | * adjustment of the registers. | |
403 | */ | |
404 | if (HAS_PCH_SPLIT(dev)) { | |
405 | u32 val = I915_READ(PCH_PP_CONTROL); | |
406 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
407 | I915_WRITE(PCH_PP_CONTROL, val & 0x3); | |
408 | } else { | |
409 | u32 val = I915_READ(PP_CONTROL); | |
410 | if ((val & PANEL_UNLOCK_REGS) == PANEL_UNLOCK_REGS) | |
411 | I915_WRITE(PP_CONTROL, val & 0x3); | |
412 | } | |
413 | ||
414 | /* Always do a full power on as we do not know what state | |
415 | * we were left in. | |
416 | */ | |
417 | intel_lvds_set_power(intel_lvds, true); | |
79e53945 JB |
418 | } |
419 | ||
420 | static void intel_lvds_mode_set(struct drm_encoder *encoder, | |
421 | struct drm_display_mode *mode, | |
422 | struct drm_display_mode *adjusted_mode) | |
423 | { | |
424 | struct drm_device *dev = encoder->dev; | |
425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 426 | struct intel_lvds *intel_lvds = to_intel_lvds(encoder); |
79e53945 JB |
427 | |
428 | /* | |
429 | * The LVDS pin pair will already have been turned on in the | |
430 | * intel_crtc_mode_set since it has a large impact on the DPLL | |
431 | * settings. | |
432 | */ | |
433 | ||
c619eed4 | 434 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
435 | return; |
436 | ||
e9e331a8 CW |
437 | if (!intel_lvds->pfit_dirty) |
438 | return; | |
439 | ||
79e53945 JB |
440 | /* |
441 | * Enable automatic panel scaling so that non-native modes fill the | |
442 | * screen. Should be enabled before the pipe is enabled, according to | |
443 | * register description and PRM. | |
444 | */ | |
4fd21dc8 CW |
445 | DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n", |
446 | intel_lvds->pfit_control, | |
447 | intel_lvds->pfit_pgm_ratios); | |
e9e331a8 CW |
448 | if (wait_for((I915_READ(PP_STATUS) & PP_ON) == 0, 1000)) |
449 | DRM_ERROR("timed out waiting for panel to power off\n"); | |
450 | ||
ea5b213a CW |
451 | I915_WRITE(PFIT_PGM_RATIOS, intel_lvds->pfit_pgm_ratios); |
452 | I915_WRITE(PFIT_CONTROL, intel_lvds->pfit_control); | |
e9e331a8 | 453 | intel_lvds->pfit_dirty = false; |
79e53945 JB |
454 | } |
455 | ||
456 | /** | |
457 | * Detect the LVDS connection. | |
458 | * | |
b42d4c5c JB |
459 | * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means |
460 | * connected and closed means disconnected. We also send hotplug events as | |
461 | * needed, using lid status notification from the input layer. | |
79e53945 | 462 | */ |
7b334fcb | 463 | static enum drm_connector_status |
930a9e28 | 464 | intel_lvds_detect(struct drm_connector *connector, bool force) |
79e53945 | 465 | { |
7b9c5abe | 466 | struct drm_device *dev = connector->dev; |
b42d4c5c JB |
467 | enum drm_connector_status status = connector_status_connected; |
468 | ||
7b9c5abe JB |
469 | /* ACPI lid methods were generally unreliable in this generation, so |
470 | * don't even bother. | |
471 | */ | |
6e6c8228 | 472 | if (IS_GEN2(dev) || IS_GEN3(dev)) |
7b9c5abe JB |
473 | return connector_status_connected; |
474 | ||
b42d4c5c | 475 | return status; |
79e53945 JB |
476 | } |
477 | ||
478 | /** | |
479 | * Return the list of DDC modes if available, or the BIOS fixed mode otherwise. | |
480 | */ | |
481 | static int intel_lvds_get_modes(struct drm_connector *connector) | |
482 | { | |
788319d4 | 483 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
79e53945 | 484 | struct drm_device *dev = connector->dev; |
788319d4 | 485 | struct drm_display_mode *mode; |
79e53945 | 486 | |
3f8ff0e7 | 487 | if (intel_lvds->edid) |
219adae1 | 488 | return drm_add_edid_modes(connector, intel_lvds->edid); |
79e53945 | 489 | |
788319d4 CW |
490 | mode = drm_mode_duplicate(dev, intel_lvds->fixed_mode); |
491 | if (mode == 0) | |
492 | return 0; | |
79e53945 | 493 | |
788319d4 CW |
494 | drm_mode_probed_add(connector, mode); |
495 | return 1; | |
79e53945 JB |
496 | } |
497 | ||
0544edfd TB |
498 | static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id) |
499 | { | |
500 | DRM_DEBUG_KMS("Skipping forced modeset for %s\n", id->ident); | |
501 | return 1; | |
502 | } | |
503 | ||
504 | /* The GPU hangs up on these systems if modeset is performed on LID open */ | |
505 | static const struct dmi_system_id intel_no_modeset_on_lid[] = { | |
506 | { | |
507 | .callback = intel_no_modeset_on_lid_dmi_callback, | |
508 | .ident = "Toshiba Tecra A11", | |
509 | .matches = { | |
510 | DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"), | |
511 | DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"), | |
512 | }, | |
513 | }, | |
514 | ||
515 | { } /* terminating entry */ | |
516 | }; | |
517 | ||
c9354c85 LT |
518 | /* |
519 | * Lid events. Note the use of 'modeset_on_lid': | |
520 | * - we set it on lid close, and reset it on open | |
521 | * - we use it as a "only once" bit (ie we ignore | |
522 | * duplicate events where it was already properly | |
523 | * set/reset) | |
524 | * - the suspend/resume paths will also set it to | |
525 | * zero, since they restore the mode ("lid open"). | |
526 | */ | |
c1c7af60 JB |
527 | static int intel_lid_notify(struct notifier_block *nb, unsigned long val, |
528 | void *unused) | |
529 | { | |
530 | struct drm_i915_private *dev_priv = | |
531 | container_of(nb, struct drm_i915_private, lid_notifier); | |
532 | struct drm_device *dev = dev_priv->dev; | |
a2565377 | 533 | struct drm_connector *connector = dev_priv->int_lvds_connector; |
c1c7af60 | 534 | |
a2565377 ZY |
535 | /* |
536 | * check and update the status of LVDS connector after receiving | |
537 | * the LID nofication event. | |
538 | */ | |
539 | if (connector) | |
7b334fcb | 540 | connector->status = connector->funcs->detect(connector, |
930a9e28 | 541 | false); |
7b334fcb | 542 | |
0544edfd TB |
543 | /* Don't force modeset on machines where it causes a GPU lockup */ |
544 | if (dmi_check_system(intel_no_modeset_on_lid)) | |
545 | return NOTIFY_OK; | |
c9354c85 LT |
546 | if (!acpi_lid_open()) { |
547 | dev_priv->modeset_on_lid = 1; | |
548 | return NOTIFY_OK; | |
06891e27 | 549 | } |
c1c7af60 | 550 | |
c9354c85 LT |
551 | if (!dev_priv->modeset_on_lid) |
552 | return NOTIFY_OK; | |
553 | ||
554 | dev_priv->modeset_on_lid = 0; | |
555 | ||
556 | mutex_lock(&dev->mode_config.mutex); | |
557 | drm_helper_resume_force_mode(dev); | |
558 | mutex_unlock(&dev->mode_config.mutex); | |
06324194 | 559 | |
c1c7af60 JB |
560 | return NOTIFY_OK; |
561 | } | |
562 | ||
79e53945 JB |
563 | /** |
564 | * intel_lvds_destroy - unregister and free LVDS structures | |
565 | * @connector: connector to free | |
566 | * | |
567 | * Unregister the DDC bus for this connector then free the driver private | |
568 | * structure. | |
569 | */ | |
570 | static void intel_lvds_destroy(struct drm_connector *connector) | |
571 | { | |
c1c7af60 | 572 | struct drm_device *dev = connector->dev; |
c1c7af60 | 573 | struct drm_i915_private *dev_priv = dev->dev_private; |
79e53945 | 574 | |
c1c7af60 JB |
575 | if (dev_priv->lid_notifier.notifier_call) |
576 | acpi_lid_notifier_unregister(&dev_priv->lid_notifier); | |
79e53945 JB |
577 | drm_sysfs_connector_remove(connector); |
578 | drm_connector_cleanup(connector); | |
579 | kfree(connector); | |
580 | } | |
581 | ||
335041ed JB |
582 | static int intel_lvds_set_property(struct drm_connector *connector, |
583 | struct drm_property *property, | |
584 | uint64_t value) | |
585 | { | |
788319d4 | 586 | struct intel_lvds *intel_lvds = intel_attached_lvds(connector); |
3fbe18d6 | 587 | struct drm_device *dev = connector->dev; |
3fbe18d6 | 588 | |
788319d4 CW |
589 | if (property == dev->mode_config.scaling_mode_property) { |
590 | struct drm_crtc *crtc = intel_lvds->base.base.crtc; | |
bb8a3560 | 591 | |
53bd8389 JB |
592 | if (value == DRM_MODE_SCALE_NONE) { |
593 | DRM_DEBUG_KMS("no scaling not supported\n"); | |
788319d4 | 594 | return -EINVAL; |
3fbe18d6 | 595 | } |
788319d4 | 596 | |
ea5b213a | 597 | if (intel_lvds->fitting_mode == value) { |
3fbe18d6 ZY |
598 | /* the LVDS scaling property is not changed */ |
599 | return 0; | |
600 | } | |
ea5b213a | 601 | intel_lvds->fitting_mode = value; |
3fbe18d6 ZY |
602 | if (crtc && crtc->enabled) { |
603 | /* | |
604 | * If the CRTC is enabled, the display will be changed | |
605 | * according to the new panel fitting mode. | |
606 | */ | |
607 | drm_crtc_helper_set_mode(crtc, &crtc->mode, | |
608 | crtc->x, crtc->y, crtc->fb); | |
609 | } | |
610 | } | |
611 | ||
335041ed JB |
612 | return 0; |
613 | } | |
614 | ||
79e53945 JB |
615 | static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = { |
616 | .dpms = intel_lvds_dpms, | |
617 | .mode_fixup = intel_lvds_mode_fixup, | |
618 | .prepare = intel_lvds_prepare, | |
619 | .mode_set = intel_lvds_mode_set, | |
620 | .commit = intel_lvds_commit, | |
621 | }; | |
622 | ||
623 | static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = { | |
624 | .get_modes = intel_lvds_get_modes, | |
625 | .mode_valid = intel_lvds_mode_valid, | |
df0e9248 | 626 | .best_encoder = intel_best_encoder, |
79e53945 JB |
627 | }; |
628 | ||
629 | static const struct drm_connector_funcs intel_lvds_connector_funcs = { | |
c9fb15f6 | 630 | .dpms = drm_helper_connector_dpms, |
79e53945 JB |
631 | .detect = intel_lvds_detect, |
632 | .fill_modes = drm_helper_probe_single_connector_modes, | |
335041ed | 633 | .set_property = intel_lvds_set_property, |
79e53945 JB |
634 | .destroy = intel_lvds_destroy, |
635 | }; | |
636 | ||
79e53945 | 637 | static const struct drm_encoder_funcs intel_lvds_enc_funcs = { |
ea5b213a | 638 | .destroy = intel_encoder_destroy, |
79e53945 JB |
639 | }; |
640 | ||
425d244c JW |
641 | static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id) |
642 | { | |
8a4c47f3 | 643 | DRM_DEBUG_KMS("Skipping LVDS initialization for %s\n", id->ident); |
425d244c JW |
644 | return 1; |
645 | } | |
79e53945 | 646 | |
425d244c | 647 | /* These systems claim to have LVDS, but really don't */ |
93c05f22 | 648 | static const struct dmi_system_id intel_no_lvds[] = { |
425d244c JW |
649 | { |
650 | .callback = intel_no_lvds_dmi_callback, | |
651 | .ident = "Apple Mac Mini (Core series)", | |
652 | .matches = { | |
98acd46f | 653 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
654 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"), |
655 | }, | |
656 | }, | |
657 | { | |
658 | .callback = intel_no_lvds_dmi_callback, | |
659 | .ident = "Apple Mac Mini (Core 2 series)", | |
660 | .matches = { | |
98acd46f | 661 | DMI_MATCH(DMI_SYS_VENDOR, "Apple"), |
425d244c JW |
662 | DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"), |
663 | }, | |
664 | }, | |
665 | { | |
666 | .callback = intel_no_lvds_dmi_callback, | |
667 | .ident = "MSI IM-945GSE-A", | |
668 | .matches = { | |
669 | DMI_MATCH(DMI_SYS_VENDOR, "MSI"), | |
670 | DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"), | |
671 | }, | |
672 | }, | |
673 | { | |
674 | .callback = intel_no_lvds_dmi_callback, | |
675 | .ident = "Dell Studio Hybrid", | |
676 | .matches = { | |
677 | DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."), | |
678 | DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"), | |
679 | }, | |
680 | }, | |
70aa96ca JW |
681 | { |
682 | .callback = intel_no_lvds_dmi_callback, | |
683 | .ident = "AOpen Mini PC", | |
684 | .matches = { | |
685 | DMI_MATCH(DMI_SYS_VENDOR, "AOpen"), | |
686 | DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"), | |
687 | }, | |
688 | }, | |
ed8c754b TV |
689 | { |
690 | .callback = intel_no_lvds_dmi_callback, | |
691 | .ident = "AOpen Mini PC MP915", | |
692 | .matches = { | |
693 | DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"), | |
694 | DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"), | |
695 | }, | |
696 | }, | |
fa0864b2 MC |
697 | { |
698 | .callback = intel_no_lvds_dmi_callback, | |
699 | .ident = "Aopen i945GTt-VFA", | |
700 | .matches = { | |
701 | DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"), | |
702 | }, | |
703 | }, | |
9875557e SB |
704 | { |
705 | .callback = intel_no_lvds_dmi_callback, | |
706 | .ident = "Clientron U800", | |
707 | .matches = { | |
708 | DMI_MATCH(DMI_SYS_VENDOR, "Clientron"), | |
709 | DMI_MATCH(DMI_PRODUCT_NAME, "U800"), | |
710 | }, | |
711 | }, | |
425d244c JW |
712 | |
713 | { } /* terminating entry */ | |
714 | }; | |
79e53945 | 715 | |
18f9ed12 ZY |
716 | /** |
717 | * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID | |
718 | * @dev: drm device | |
719 | * @connector: LVDS connector | |
720 | * | |
721 | * Find the reduced downclock for LVDS in EDID. | |
722 | */ | |
723 | static void intel_find_lvds_downclock(struct drm_device *dev, | |
788319d4 CW |
724 | struct drm_display_mode *fixed_mode, |
725 | struct drm_connector *connector) | |
18f9ed12 ZY |
726 | { |
727 | struct drm_i915_private *dev_priv = dev->dev_private; | |
788319d4 | 728 | struct drm_display_mode *scan; |
18f9ed12 ZY |
729 | int temp_downclock; |
730 | ||
788319d4 | 731 | temp_downclock = fixed_mode->clock; |
18f9ed12 ZY |
732 | list_for_each_entry(scan, &connector->probed_modes, head) { |
733 | /* | |
734 | * If one mode has the same resolution with the fixed_panel | |
735 | * mode while they have the different refresh rate, it means | |
736 | * that the reduced downclock is found for the LVDS. In such | |
737 | * case we can set the different FPx0/1 to dynamically select | |
738 | * between low and high frequency. | |
739 | */ | |
788319d4 CW |
740 | if (scan->hdisplay == fixed_mode->hdisplay && |
741 | scan->hsync_start == fixed_mode->hsync_start && | |
742 | scan->hsync_end == fixed_mode->hsync_end && | |
743 | scan->htotal == fixed_mode->htotal && | |
744 | scan->vdisplay == fixed_mode->vdisplay && | |
745 | scan->vsync_start == fixed_mode->vsync_start && | |
746 | scan->vsync_end == fixed_mode->vsync_end && | |
747 | scan->vtotal == fixed_mode->vtotal) { | |
18f9ed12 ZY |
748 | if (scan->clock < temp_downclock) { |
749 | /* | |
750 | * The downclock is already found. But we | |
751 | * expect to find the lower downclock. | |
752 | */ | |
753 | temp_downclock = scan->clock; | |
754 | } | |
755 | } | |
756 | } | |
788319d4 | 757 | if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) { |
18f9ed12 ZY |
758 | /* We found the downclock for LVDS. */ |
759 | dev_priv->lvds_downclock_avail = 1; | |
760 | dev_priv->lvds_downclock = temp_downclock; | |
761 | DRM_DEBUG_KMS("LVDS downclock is found in EDID. " | |
788319d4 CW |
762 | "Normal clock %dKhz, downclock %dKhz\n", |
763 | fixed_mode->clock, temp_downclock); | |
18f9ed12 | 764 | } |
18f9ed12 ZY |
765 | } |
766 | ||
7cf4f69d ZY |
767 | /* |
768 | * Enumerate the child dev array parsed from VBT to check whether | |
769 | * the LVDS is present. | |
770 | * If it is present, return 1. | |
771 | * If it is not present, return false. | |
772 | * If no child dev is parsed from VBT, it assumes that the LVDS is present. | |
7cf4f69d | 773 | */ |
270eea0f CW |
774 | static bool lvds_is_present_in_vbt(struct drm_device *dev, |
775 | u8 *i2c_pin) | |
7cf4f69d ZY |
776 | { |
777 | struct drm_i915_private *dev_priv = dev->dev_private; | |
425904dd | 778 | int i; |
7cf4f69d ZY |
779 | |
780 | if (!dev_priv->child_dev_num) | |
425904dd | 781 | return true; |
7cf4f69d | 782 | |
7cf4f69d | 783 | for (i = 0; i < dev_priv->child_dev_num; i++) { |
425904dd CW |
784 | struct child_device_config *child = dev_priv->child_dev + i; |
785 | ||
786 | /* If the device type is not LFP, continue. | |
787 | * We have to check both the new identifiers as well as the | |
788 | * old for compatibility with some BIOSes. | |
7cf4f69d | 789 | */ |
425904dd CW |
790 | if (child->device_type != DEVICE_TYPE_INT_LFP && |
791 | child->device_type != DEVICE_TYPE_LFP) | |
7cf4f69d ZY |
792 | continue; |
793 | ||
270eea0f CW |
794 | if (child->i2c_pin) |
795 | *i2c_pin = child->i2c_pin; | |
796 | ||
425904dd CW |
797 | /* However, we cannot trust the BIOS writers to populate |
798 | * the VBT correctly. Since LVDS requires additional | |
799 | * information from AIM blocks, a non-zero addin offset is | |
800 | * a good indicator that the LVDS is actually present. | |
7cf4f69d | 801 | */ |
425904dd CW |
802 | if (child->addin_offset) |
803 | return true; | |
804 | ||
805 | /* But even then some BIOS writers perform some black magic | |
806 | * and instantiate the device without reference to any | |
807 | * additional data. Trust that if the VBT was written into | |
808 | * the OpRegion then they have validated the LVDS's existence. | |
809 | */ | |
810 | if (dev_priv->opregion.vbt) | |
811 | return true; | |
7cf4f69d | 812 | } |
425904dd CW |
813 | |
814 | return false; | |
7cf4f69d ZY |
815 | } |
816 | ||
270eea0f | 817 | static bool intel_lvds_ddc_probe(struct drm_device *dev, u8 pin) |
428d2e82 CW |
818 | { |
819 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820 | u8 buf = 0; | |
821 | struct i2c_msg msgs[] = { | |
822 | { | |
823 | .addr = 0xA0, | |
824 | .flags = 0, | |
825 | .len = 1, | |
826 | .buf = &buf, | |
827 | }, | |
828 | }; | |
270eea0f | 829 | struct i2c_adapter *i2c = &dev_priv->gmbus[pin].adapter; |
b8232e90 CW |
830 | /* XXX this only appears to work when using GMBUS */ |
831 | if (intel_gmbus_is_forced_bit(i2c)) | |
832 | return true; | |
428d2e82 CW |
833 | return i2c_transfer(i2c, msgs, 1) == 1; |
834 | } | |
835 | ||
79e53945 JB |
836 | /** |
837 | * intel_lvds_init - setup LVDS connectors on this device | |
838 | * @dev: drm device | |
839 | * | |
840 | * Create the connector, register the LVDS DDC bus, and try to figure out what | |
841 | * modes we can display on the LVDS panel (if present). | |
842 | */ | |
c5d1b51d | 843 | bool intel_lvds_init(struct drm_device *dev) |
79e53945 JB |
844 | { |
845 | struct drm_i915_private *dev_priv = dev->dev_private; | |
ea5b213a | 846 | struct intel_lvds *intel_lvds; |
21d40d37 | 847 | struct intel_encoder *intel_encoder; |
bb8a3560 | 848 | struct intel_connector *intel_connector; |
79e53945 JB |
849 | struct drm_connector *connector; |
850 | struct drm_encoder *encoder; | |
851 | struct drm_display_mode *scan; /* *modes, *bios_mode; */ | |
852 | struct drm_crtc *crtc; | |
853 | u32 lvds; | |
270eea0f CW |
854 | int pipe; |
855 | u8 pin; | |
79e53945 | 856 | |
425d244c JW |
857 | /* Skip init on machines we know falsely report LVDS */ |
858 | if (dmi_check_system(intel_no_lvds)) | |
c5d1b51d | 859 | return false; |
565dcd46 | 860 | |
270eea0f CW |
861 | pin = GMBUS_PORT_PANEL; |
862 | if (!lvds_is_present_in_vbt(dev, &pin)) { | |
11ba1592 | 863 | DRM_DEBUG_KMS("LVDS is not present in VBT\n"); |
c5d1b51d | 864 | return false; |
38b3037e | 865 | } |
e99da35f | 866 | |
c619eed4 | 867 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 868 | if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0) |
c5d1b51d | 869 | return false; |
5ceb0f9b | 870 | if (dev_priv->edp.support) { |
28c97730 | 871 | DRM_DEBUG_KMS("disable LVDS for eDP support\n"); |
c5d1b51d | 872 | return false; |
32f9d658 | 873 | } |
541998a1 ZW |
874 | } |
875 | ||
270eea0f | 876 | if (!intel_lvds_ddc_probe(dev, pin)) { |
428d2e82 | 877 | DRM_DEBUG_KMS("LVDS did not respond to DDC probe\n"); |
c5d1b51d | 878 | return false; |
428d2e82 CW |
879 | } |
880 | ||
ea5b213a CW |
881 | intel_lvds = kzalloc(sizeof(struct intel_lvds), GFP_KERNEL); |
882 | if (!intel_lvds) { | |
c5d1b51d | 883 | return false; |
79e53945 JB |
884 | } |
885 | ||
bb8a3560 ZW |
886 | intel_connector = kzalloc(sizeof(struct intel_connector), GFP_KERNEL); |
887 | if (!intel_connector) { | |
ea5b213a | 888 | kfree(intel_lvds); |
c5d1b51d | 889 | return false; |
bb8a3560 ZW |
890 | } |
891 | ||
e9e331a8 CW |
892 | if (!HAS_PCH_SPLIT(dev)) { |
893 | intel_lvds->pfit_control = I915_READ(PFIT_CONTROL); | |
894 | } | |
895 | ||
ea5b213a | 896 | intel_encoder = &intel_lvds->base; |
4ef69c7a | 897 | encoder = &intel_encoder->base; |
ea5b213a | 898 | connector = &intel_connector->base; |
bb8a3560 | 899 | drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs, |
79e53945 JB |
900 | DRM_MODE_CONNECTOR_LVDS); |
901 | ||
4ef69c7a | 902 | drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs, |
79e53945 JB |
903 | DRM_MODE_ENCODER_LVDS); |
904 | ||
df0e9248 | 905 | intel_connector_attach_encoder(intel_connector, intel_encoder); |
21d40d37 | 906 | intel_encoder->type = INTEL_OUTPUT_LVDS; |
79e53945 | 907 | |
21d40d37 EA |
908 | intel_encoder->clone_mask = (1 << INTEL_LVDS_CLONE_BIT); |
909 | intel_encoder->crtc_mask = (1 << 1); | |
79e53945 JB |
910 | drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs); |
911 | drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs); | |
912 | connector->display_info.subpixel_order = SubPixelHorizontalRGB; | |
913 | connector->interlace_allowed = false; | |
914 | connector->doublescan_allowed = false; | |
915 | ||
3fbe18d6 ZY |
916 | /* create the scaling mode property */ |
917 | drm_mode_create_scaling_mode_property(dev); | |
918 | /* | |
919 | * the initial panel fitting mode will be FULL_SCREEN. | |
920 | */ | |
79e53945 | 921 | |
bb8a3560 | 922 | drm_connector_attach_property(&intel_connector->base, |
3fbe18d6 | 923 | dev->mode_config.scaling_mode_property, |
dd1ea37d | 924 | DRM_MODE_SCALE_ASPECT); |
ea5b213a | 925 | intel_lvds->fitting_mode = DRM_MODE_SCALE_ASPECT; |
79e53945 JB |
926 | /* |
927 | * LVDS discovery: | |
928 | * 1) check for EDID on DDC | |
929 | * 2) check for VBT data | |
930 | * 3) check to see if LVDS is already on | |
931 | * if none of the above, no panel | |
932 | * 4) make sure lid is open | |
933 | * if closed, act like it's not there for now | |
934 | */ | |
935 | ||
79e53945 JB |
936 | /* |
937 | * Attempt to get the fixed panel mode from DDC. Assume that the | |
938 | * preferred mode is the right one. | |
939 | */ | |
219adae1 | 940 | intel_lvds->edid = drm_get_edid(connector, |
270eea0f | 941 | &dev_priv->gmbus[pin].adapter); |
3f8ff0e7 CW |
942 | if (intel_lvds->edid) { |
943 | if (drm_add_edid_modes(connector, | |
944 | intel_lvds->edid)) { | |
945 | drm_mode_connector_update_edid_property(connector, | |
946 | intel_lvds->edid); | |
947 | } else { | |
948 | kfree(intel_lvds->edid); | |
949 | intel_lvds->edid = NULL; | |
950 | } | |
951 | } | |
219adae1 | 952 | if (!intel_lvds->edid) { |
788319d4 CW |
953 | /* Didn't get an EDID, so |
954 | * Set wide sync ranges so we get all modes | |
955 | * handed to valid_mode for checking | |
956 | */ | |
957 | connector->display_info.min_vfreq = 0; | |
958 | connector->display_info.max_vfreq = 200; | |
959 | connector->display_info.min_hfreq = 0; | |
960 | connector->display_info.max_hfreq = 200; | |
961 | } | |
79e53945 JB |
962 | |
963 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
79e53945 | 964 | if (scan->type & DRM_MODE_TYPE_PREFERRED) { |
788319d4 | 965 | intel_lvds->fixed_mode = |
79e53945 | 966 | drm_mode_duplicate(dev, scan); |
788319d4 CW |
967 | intel_find_lvds_downclock(dev, |
968 | intel_lvds->fixed_mode, | |
969 | connector); | |
565dcd46 | 970 | goto out; |
79e53945 | 971 | } |
79e53945 JB |
972 | } |
973 | ||
974 | /* Failed to get EDID, what about VBT? */ | |
88631706 | 975 | if (dev_priv->lfp_lvds_vbt_mode) { |
788319d4 | 976 | intel_lvds->fixed_mode = |
88631706 | 977 | drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode); |
788319d4 CW |
978 | if (intel_lvds->fixed_mode) { |
979 | intel_lvds->fixed_mode->type |= | |
e285f3cd | 980 | DRM_MODE_TYPE_PREFERRED; |
e285f3cd JB |
981 | goto out; |
982 | } | |
79e53945 JB |
983 | } |
984 | ||
985 | /* | |
986 | * If we didn't get EDID, try checking if the panel is already turned | |
987 | * on. If so, assume that whatever is currently programmed is the | |
988 | * correct mode. | |
989 | */ | |
541998a1 | 990 | |
f2b115e6 | 991 | /* Ironlake: FIXME if still fail, not try pipe mode now */ |
c619eed4 | 992 | if (HAS_PCH_SPLIT(dev)) |
541998a1 ZW |
993 | goto failed; |
994 | ||
79e53945 JB |
995 | lvds = I915_READ(LVDS); |
996 | pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0; | |
f875c15a | 997 | crtc = intel_get_crtc_for_pipe(dev, pipe); |
79e53945 JB |
998 | |
999 | if (crtc && (lvds & LVDS_PORT_EN)) { | |
788319d4 CW |
1000 | intel_lvds->fixed_mode = intel_crtc_mode_get(dev, crtc); |
1001 | if (intel_lvds->fixed_mode) { | |
1002 | intel_lvds->fixed_mode->type |= | |
79e53945 | 1003 | DRM_MODE_TYPE_PREFERRED; |
565dcd46 | 1004 | goto out; |
79e53945 JB |
1005 | } |
1006 | } | |
1007 | ||
1008 | /* If we still don't have a mode after all that, give up. */ | |
788319d4 | 1009 | if (!intel_lvds->fixed_mode) |
79e53945 JB |
1010 | goto failed; |
1011 | ||
79e53945 | 1012 | out: |
c619eed4 | 1013 | if (HAS_PCH_SPLIT(dev)) { |
541998a1 | 1014 | u32 pwm; |
17fe6981 CW |
1015 | |
1016 | pipe = (I915_READ(PCH_LVDS) & LVDS_PIPEB_SELECT) ? 1 : 0; | |
1017 | ||
1018 | /* make sure PWM is enabled and locked to the LVDS pipe */ | |
541998a1 | 1019 | pwm = I915_READ(BLC_PWM_CPU_CTL2); |
17fe6981 CW |
1020 | if (pipe == 0 && (pwm & PWM_PIPE_B)) |
1021 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm & ~PWM_ENABLE); | |
1022 | if (pipe) | |
1023 | pwm |= PWM_PIPE_B; | |
1024 | else | |
1025 | pwm &= ~PWM_PIPE_B; | |
1026 | I915_WRITE(BLC_PWM_CPU_CTL2, pwm | PWM_ENABLE); | |
541998a1 ZW |
1027 | |
1028 | pwm = I915_READ(BLC_PWM_PCH_CTL1); | |
1029 | pwm |= PWM_PCH_ENABLE; | |
1030 | I915_WRITE(BLC_PWM_PCH_CTL1, pwm); | |
1031 | } | |
c1c7af60 JB |
1032 | dev_priv->lid_notifier.notifier_call = intel_lid_notify; |
1033 | if (acpi_lid_notifier_register(&dev_priv->lid_notifier)) { | |
28c97730 | 1034 | DRM_DEBUG_KMS("lid notifier registration failed\n"); |
c1c7af60 JB |
1035 | dev_priv->lid_notifier.notifier_call = NULL; |
1036 | } | |
a2565377 ZY |
1037 | /* keep the LVDS connector */ |
1038 | dev_priv->int_lvds_connector = connector; | |
79e53945 | 1039 | drm_sysfs_connector_add(connector); |
c5d1b51d | 1040 | return true; |
79e53945 JB |
1041 | |
1042 | failed: | |
8a4c47f3 | 1043 | DRM_DEBUG_KMS("No LVDS modes found, disabling.\n"); |
79e53945 | 1044 | drm_connector_cleanup(connector); |
1991bdfa | 1045 | drm_encoder_cleanup(encoder); |
ea5b213a | 1046 | kfree(intel_lvds); |
bb8a3560 | 1047 | kfree(intel_connector); |
c5d1b51d | 1048 | return false; |
79e53945 | 1049 | } |