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drm/i915: move intel_update_lvds to intel_lvds->pre_pll_enable
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_lvds.c
CommitLineData
79e53945
JB
1/*
2 * Copyright © 2006-2007 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 */
29
c1c7af60 30#include <acpi/button.h>
565dcd46 31#include <linux/dmi.h>
79e53945 32#include <linux/i2c.h>
5a0e3ad6 33#include <linux/slab.h>
760285e7
DH
34#include <drm/drmP.h>
35#include <drm/drm_crtc.h>
36#include <drm/drm_edid.h>
79e53945 37#include "intel_drv.h"
760285e7 38#include <drm/i915_drm.h>
79e53945 39#include "i915_drv.h"
e99da35f 40#include <linux/acpi.h>
79e53945 41
3fbe18d6 42/* Private structure for the integrated LVDS support */
c7362c4d
JN
43struct intel_lvds_connector {
44 struct intel_connector base;
788319d4 45
db1740a0 46 struct notifier_block lid_notifier;
c7362c4d
JN
47};
48
29b99b48 49struct intel_lvds_encoder {
ea5b213a 50 struct intel_encoder base;
788319d4 51
3fbe18d6
ZY
52 u32 pfit_control;
53 u32 pfit_pgm_ratios;
e9e331a8 54 bool pfit_dirty;
13c7d870 55 bool is_dual_link;
7dec0606 56 u32 reg;
788319d4 57
62165e0d 58 struct intel_lvds_connector *attached_connector;
3fbe18d6
ZY
59};
60
29b99b48 61static struct intel_lvds_encoder *to_lvds_encoder(struct drm_encoder *encoder)
ea5b213a 62{
29b99b48 63 return container_of(encoder, struct intel_lvds_encoder, base.base);
ea5b213a
CW
64}
65
c7362c4d 66static struct intel_lvds_connector *to_lvds_connector(struct drm_connector *connector)
788319d4 67{
c7362c4d 68 return container_of(connector, struct intel_lvds_connector, base.base);
788319d4
CW
69}
70
b1dc332c
DV
71static bool intel_lvds_get_hw_state(struct intel_encoder *encoder,
72 enum pipe *pipe)
73{
74 struct drm_device *dev = encoder->base.dev;
75 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606
DV
76 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
77 u32 tmp;
b1dc332c 78
7dec0606 79 tmp = I915_READ(lvds_encoder->reg);
b1dc332c
DV
80
81 if (!(tmp & LVDS_PORT_EN))
82 return false;
83
84 if (HAS_PCH_CPT(dev))
85 *pipe = PORT_TO_PIPE_CPT(tmp);
86 else
87 *pipe = PORT_TO_PIPE(tmp);
88
89 return true;
90}
91
fc683091
DV
92/* The LVDS pin pair needs to be on before the DPLLs are enabled.
93 * This is an exception to the general rule that mode_set doesn't turn
94 * things on.
95 */
96static void intel_pre_pll_enable_lvds(struct intel_encoder *encoder)
97{
98 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
99 struct drm_device *dev = encoder->base.dev;
100 struct drm_i915_private *dev_priv = dev->dev_private;
101 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
102 struct drm_display_mode *fixed_mode =
103 lvds_encoder->attached_connector->base.panel.fixed_mode;
104 int pipe = intel_crtc->pipe;
105 u32 temp;
106
107 /* pch split platforms are not yet converted. */
108 if (HAS_PCH_SPLIT(dev))
109 return;
110
111 temp = I915_READ(lvds_encoder->reg);
112 temp |= LVDS_PORT_EN | LVDS_A0A2_CLKA_POWER_UP;
113 if (pipe == 1) {
114 temp |= LVDS_PIPEB_SELECT;
115 } else {
116 temp &= ~LVDS_PIPEB_SELECT;
117 }
118 /* set the corresponsding LVDS_BORDER bit */
119 temp |= dev_priv->lvds_border_bits;
120 /* Set the B0-B3 data pairs corresponding to whether we're going to
121 * set the DPLLs for dual-channel mode or not.
122 */
123 if (lvds_encoder->is_dual_link)
124 temp |= LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP;
125 else
126 temp &= ~(LVDS_B0B3_POWER_UP | LVDS_CLKB_POWER_UP);
127
128 /* It would be nice to set 24 vs 18-bit mode (LVDS_A3_POWER_UP)
129 * appropriately here, but we need to look more thoroughly into how
130 * panels behave in the two modes.
131 */
132 /* set the dithering flag on LVDS as needed */
133 if (INTEL_INFO(dev)->gen >= 4) {
134 if (dev_priv->lvds_dither)
135 temp |= LVDS_ENABLE_DITHER;
136 else
137 temp &= ~LVDS_ENABLE_DITHER;
138 }
139 temp &= ~(LVDS_HSYNC_POLARITY | LVDS_VSYNC_POLARITY);
140 if (fixed_mode->flags & DRM_MODE_FLAG_NHSYNC)
141 temp |= LVDS_HSYNC_POLARITY;
142 if (fixed_mode->flags & DRM_MODE_FLAG_NVSYNC)
143 temp |= LVDS_VSYNC_POLARITY;
144
145 I915_WRITE(lvds_encoder->reg, temp);
146}
147
79e53945
JB
148/**
149 * Sets the power state for the panel.
150 */
c22834ec 151static void intel_enable_lvds(struct intel_encoder *encoder)
79e53945 152{
c22834ec 153 struct drm_device *dev = encoder->base.dev;
29b99b48 154 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
c22834ec 155 struct intel_crtc *intel_crtc = to_intel_crtc(encoder->base.crtc);
79e53945 156 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 157 u32 ctl_reg, stat_reg;
541998a1 158
c619eed4 159 if (HAS_PCH_SPLIT(dev)) {
541998a1 160 ctl_reg = PCH_PP_CONTROL;
de842eff 161 stat_reg = PCH_PP_STATUS;
541998a1
ZW
162 } else {
163 ctl_reg = PP_CONTROL;
de842eff 164 stat_reg = PP_STATUS;
541998a1 165 }
79e53945 166
7dec0606 167 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) | LVDS_PORT_EN);
e9e331a8 168
29b99b48 169 if (lvds_encoder->pfit_dirty) {
2a1292fd
CW
170 /*
171 * Enable automatic panel scaling so that non-native modes
172 * fill the screen. The panel fitter should only be
173 * adjusted whilst the pipe is disabled, according to
174 * register description and PRM.
175 */
176 DRM_DEBUG_KMS("applying panel-fitter: %x, %x\n",
29b99b48
JN
177 lvds_encoder->pfit_control,
178 lvds_encoder->pfit_pgm_ratios);
de842eff 179
29b99b48
JN
180 I915_WRITE(PFIT_PGM_RATIOS, lvds_encoder->pfit_pgm_ratios);
181 I915_WRITE(PFIT_CONTROL, lvds_encoder->pfit_control);
182 lvds_encoder->pfit_dirty = false;
2a1292fd
CW
183 }
184
185 I915_WRITE(ctl_reg, I915_READ(ctl_reg) | POWER_TARGET_ON);
7dec0606 186 POSTING_READ(lvds_encoder->reg);
de842eff
KP
187 if (wait_for((I915_READ(stat_reg) & PP_ON) != 0, 1000))
188 DRM_ERROR("timed out waiting for panel to power on\n");
2a1292fd 189
24ded204 190 intel_panel_enable_backlight(dev, intel_crtc->pipe);
2a1292fd
CW
191}
192
c22834ec 193static void intel_disable_lvds(struct intel_encoder *encoder)
2a1292fd 194{
c22834ec 195 struct drm_device *dev = encoder->base.dev;
29b99b48 196 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(&encoder->base);
2a1292fd 197 struct drm_i915_private *dev_priv = dev->dev_private;
7dec0606 198 u32 ctl_reg, stat_reg;
2a1292fd
CW
199
200 if (HAS_PCH_SPLIT(dev)) {
201 ctl_reg = PCH_PP_CONTROL;
de842eff 202 stat_reg = PCH_PP_STATUS;
2a1292fd
CW
203 } else {
204 ctl_reg = PP_CONTROL;
de842eff 205 stat_reg = PP_STATUS;
2a1292fd
CW
206 }
207
47356eb6 208 intel_panel_disable_backlight(dev);
2a1292fd
CW
209
210 I915_WRITE(ctl_reg, I915_READ(ctl_reg) & ~POWER_TARGET_ON);
de842eff
KP
211 if (wait_for((I915_READ(stat_reg) & PP_ON) == 0, 1000))
212 DRM_ERROR("timed out waiting for panel to power off\n");
2a1292fd 213
29b99b48 214 if (lvds_encoder->pfit_control) {
2a1292fd 215 I915_WRITE(PFIT_CONTROL, 0);
29b99b48 216 lvds_encoder->pfit_dirty = true;
79e53945 217 }
2a1292fd 218
7dec0606
DV
219 I915_WRITE(lvds_encoder->reg, I915_READ(lvds_encoder->reg) & ~LVDS_PORT_EN);
220 POSTING_READ(lvds_encoder->reg);
79e53945
JB
221}
222
79e53945
JB
223static int intel_lvds_mode_valid(struct drm_connector *connector,
224 struct drm_display_mode *mode)
225{
dd06f90e
JN
226 struct intel_connector *intel_connector = to_intel_connector(connector);
227 struct drm_display_mode *fixed_mode = intel_connector->panel.fixed_mode;
79e53945 228
788319d4
CW
229 if (mode->hdisplay > fixed_mode->hdisplay)
230 return MODE_PANEL;
231 if (mode->vdisplay > fixed_mode->vdisplay)
232 return MODE_PANEL;
79e53945
JB
233
234 return MODE_OK;
235}
236
49be663f
CW
237static void
238centre_horizontally(struct drm_display_mode *mode,
239 int width)
240{
241 u32 border, sync_pos, blank_width, sync_width;
242
243 /* keep the hsync and hblank widths constant */
244 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
245 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
246 sync_pos = (blank_width - sync_width + 1) / 2;
247
248 border = (mode->hdisplay - width + 1) / 2;
249 border += border & 1; /* make the border even */
250
251 mode->crtc_hdisplay = width;
252 mode->crtc_hblank_start = width + border;
253 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
254
255 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
256 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
f9bef081
DV
257
258 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
259}
260
261static void
262centre_vertically(struct drm_display_mode *mode,
263 int height)
264{
265 u32 border, sync_pos, blank_width, sync_width;
266
267 /* keep the vsync and vblank widths constant */
268 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
269 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
270 sync_pos = (blank_width - sync_width + 1) / 2;
271
272 border = (mode->vdisplay - height + 1) / 2;
273
274 mode->crtc_vdisplay = height;
275 mode->crtc_vblank_start = height + border;
276 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
277
278 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
279 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
f9bef081
DV
280
281 mode->private_flags |= INTEL_MODE_CRTC_TIMINGS_SET;
49be663f
CW
282}
283
284static inline u32 panel_fitter_scaling(u32 source, u32 target)
285{
286 /*
287 * Floating point operation is not supported. So the FACTOR
288 * is defined, which can avoid the floating point computation
289 * when calculating the panel ratio.
290 */
291#define ACCURACY 12
292#define FACTOR (1 << ACCURACY)
293 u32 ratio = source * FACTOR / target;
294 return (FACTOR * ratio + FACTOR/2) / FACTOR;
295}
296
79e53945 297static bool intel_lvds_mode_fixup(struct drm_encoder *encoder,
e811f5ae 298 const struct drm_display_mode *mode,
79e53945
JB
299 struct drm_display_mode *adjusted_mode)
300{
301 struct drm_device *dev = encoder->dev;
302 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 303 struct intel_lvds_encoder *lvds_encoder = to_lvds_encoder(encoder);
4d891523
JN
304 struct intel_connector *intel_connector =
305 &lvds_encoder->attached_connector->base;
29b99b48 306 struct intel_crtc *intel_crtc = lvds_encoder->base.new_crtc;
49be663f 307 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
9db4a9c7 308 int pipe;
79e53945
JB
309
310 /* Should never happen!! */
a6c45cf0 311 if (INTEL_INFO(dev)->gen < 4 && intel_crtc->pipe == 0) {
1ae8c0a5 312 DRM_ERROR("Can't support LVDS on pipe A\n");
79e53945
JB
313 return false;
314 }
315
29b99b48 316 if (intel_encoder_check_is_cloned(&lvds_encoder->base))
e24c5c29 317 return false;
1d8e1c75 318
79e53945 319 /*
71677043 320 * We have timings from the BIOS for the panel, put them in
79e53945
JB
321 * to the adjusted mode. The CRTC will be set up for this mode,
322 * with the panel scaling set up to source from the H/VDisplay
323 * of the original mode.
324 */
4d891523 325 intel_fixed_panel_mode(intel_connector->panel.fixed_mode,
dd06f90e 326 adjusted_mode);
1d8e1c75
CW
327
328 if (HAS_PCH_SPLIT(dev)) {
4d891523
JN
329 intel_pch_panel_fitting(dev,
330 intel_connector->panel.fitting_mode,
1d8e1c75
CW
331 mode, adjusted_mode);
332 return true;
333 }
79e53945 334
3fbe18d6
ZY
335 /* Native modes don't need fitting */
336 if (adjusted_mode->hdisplay == mode->hdisplay &&
49be663f 337 adjusted_mode->vdisplay == mode->vdisplay)
3fbe18d6 338 goto out;
3fbe18d6
ZY
339
340 /* 965+ wants fuzzy fitting */
a6c45cf0 341 if (INTEL_INFO(dev)->gen >= 4)
49be663f
CW
342 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
343 PFIT_FILTER_FUZZY);
344
3fbe18d6
ZY
345 /*
346 * Enable automatic panel scaling for non-native modes so that they fill
347 * the screen. Should be enabled before the pipe is enabled, according
348 * to register description and PRM.
349 * Change the value here to see the borders for debugging
350 */
9db4a9c7
JB
351 for_each_pipe(pipe)
352 I915_WRITE(BCLRPAT(pipe), 0);
3fbe18d6 353
f9bef081
DV
354 drm_mode_set_crtcinfo(adjusted_mode, 0);
355
4d891523 356 switch (intel_connector->panel.fitting_mode) {
53bd8389 357 case DRM_MODE_SCALE_CENTER:
3fbe18d6
ZY
358 /*
359 * For centered modes, we have to calculate border widths &
360 * heights and modify the values programmed into the CRTC.
361 */
49be663f
CW
362 centre_horizontally(adjusted_mode, mode->hdisplay);
363 centre_vertically(adjusted_mode, mode->vdisplay);
364 border = LVDS_BORDER_ENABLE;
3fbe18d6 365 break;
49be663f 366
3fbe18d6 367 case DRM_MODE_SCALE_ASPECT:
49be663f 368 /* Scale but preserve the aspect ratio */
a6c45cf0 369 if (INTEL_INFO(dev)->gen >= 4) {
49be663f
CW
370 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
371 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
372
3fbe18d6 373 /* 965+ is easy, it does everything in hw */
49be663f 374 if (scaled_width > scaled_height)
257e48f1 375 pfit_control |= PFIT_ENABLE | PFIT_SCALING_PILLAR;
49be663f 376 else if (scaled_width < scaled_height)
257e48f1
CW
377 pfit_control |= PFIT_ENABLE | PFIT_SCALING_LETTER;
378 else if (adjusted_mode->hdisplay != mode->hdisplay)
379 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
3fbe18d6 380 } else {
49be663f
CW
381 u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay;
382 u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay;
3fbe18d6
ZY
383 /*
384 * For earlier chips we have to calculate the scaling
385 * ratio by hand and program it into the
386 * PFIT_PGM_RATIO register
387 */
49be663f
CW
388 if (scaled_width > scaled_height) { /* pillar */
389 centre_horizontally(adjusted_mode, scaled_height / mode->vdisplay);
390
391 border = LVDS_BORDER_ENABLE;
392 if (mode->vdisplay != adjusted_mode->vdisplay) {
393 u32 bits = panel_fitter_scaling(mode->vdisplay, adjusted_mode->vdisplay);
394 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
395 bits << PFIT_VERT_SCALE_SHIFT);
396 pfit_control |= (PFIT_ENABLE |
397 VERT_INTERP_BILINEAR |
398 HORIZ_INTERP_BILINEAR);
399 }
400 } else if (scaled_width < scaled_height) { /* letter */
401 centre_vertically(adjusted_mode, scaled_width / mode->hdisplay);
402
403 border = LVDS_BORDER_ENABLE;
404 if (mode->hdisplay != adjusted_mode->hdisplay) {
405 u32 bits = panel_fitter_scaling(mode->hdisplay, adjusted_mode->hdisplay);
406 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
407 bits << PFIT_VERT_SCALE_SHIFT);
408 pfit_control |= (PFIT_ENABLE |
409 VERT_INTERP_BILINEAR |
410 HORIZ_INTERP_BILINEAR);
411 }
412 } else
413 /* Aspects match, Let hw scale both directions */
414 pfit_control |= (PFIT_ENABLE |
415 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
3fbe18d6
ZY
416 VERT_INTERP_BILINEAR |
417 HORIZ_INTERP_BILINEAR);
3fbe18d6
ZY
418 }
419 break;
420
421 case DRM_MODE_SCALE_FULLSCREEN:
422 /*
423 * Full scaling, even if it changes the aspect ratio.
424 * Fortunately this is all done for us in hw.
425 */
257e48f1
CW
426 if (mode->vdisplay != adjusted_mode->vdisplay ||
427 mode->hdisplay != adjusted_mode->hdisplay) {
428 pfit_control |= PFIT_ENABLE;
429 if (INTEL_INFO(dev)->gen >= 4)
430 pfit_control |= PFIT_SCALING_AUTO;
431 else
432 pfit_control |= (VERT_AUTO_SCALE |
433 VERT_INTERP_BILINEAR |
434 HORIZ_AUTO_SCALE |
435 HORIZ_INTERP_BILINEAR);
436 }
3fbe18d6 437 break;
49be663f 438
3fbe18d6
ZY
439 default:
440 break;
441 }
442
443out:
72389a33 444 /* If not enabling scaling, be consistent and always use 0. */
bee17e5a
CW
445 if ((pfit_control & PFIT_ENABLE) == 0) {
446 pfit_control = 0;
447 pfit_pgm_ratios = 0;
448 }
72389a33
CW
449
450 /* Make sure pre-965 set dither correctly */
451 if (INTEL_INFO(dev)->gen < 4 && dev_priv->lvds_dither)
452 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
453
29b99b48
JN
454 if (pfit_control != lvds_encoder->pfit_control ||
455 pfit_pgm_ratios != lvds_encoder->pfit_pgm_ratios) {
456 lvds_encoder->pfit_control = pfit_control;
457 lvds_encoder->pfit_pgm_ratios = pfit_pgm_ratios;
458 lvds_encoder->pfit_dirty = true;
e9e331a8 459 }
49be663f
CW
460 dev_priv->lvds_border_bits = border;
461
79e53945
JB
462 /*
463 * XXX: It would be nice to support lower refresh rates on the
464 * panels to reduce power consumption, and perhaps match the
465 * user's requested refresh rate.
466 */
467
468 return true;
469}
470
79e53945
JB
471static void intel_lvds_mode_set(struct drm_encoder *encoder,
472 struct drm_display_mode *mode,
473 struct drm_display_mode *adjusted_mode)
474{
79e53945
JB
475 /*
476 * The LVDS pin pair will already have been turned on in the
477 * intel_crtc_mode_set since it has a large impact on the DPLL
478 * settings.
479 */
79e53945
JB
480}
481
482/**
483 * Detect the LVDS connection.
484 *
b42d4c5c
JB
485 * Since LVDS doesn't have hotlug, we use the lid as a proxy. Open means
486 * connected and closed means disconnected. We also send hotplug events as
487 * needed, using lid status notification from the input layer.
79e53945 488 */
7b334fcb 489static enum drm_connector_status
930a9e28 490intel_lvds_detect(struct drm_connector *connector, bool force)
79e53945 491{
7b9c5abe 492 struct drm_device *dev = connector->dev;
6ee3b5a1 493 enum drm_connector_status status;
b42d4c5c 494
fe16d949
CW
495 status = intel_panel_detect(dev);
496 if (status != connector_status_unknown)
497 return status;
01fe9dbd 498
6ee3b5a1 499 return connector_status_connected;
79e53945
JB
500}
501
502/**
503 * Return the list of DDC modes if available, or the BIOS fixed mode otherwise.
504 */
505static int intel_lvds_get_modes(struct drm_connector *connector)
506{
62165e0d 507 struct intel_lvds_connector *lvds_connector = to_lvds_connector(connector);
79e53945 508 struct drm_device *dev = connector->dev;
788319d4 509 struct drm_display_mode *mode;
79e53945 510
9cd300e0 511 /* use cached edid if we have one */
2aa4f099 512 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
9cd300e0 513 return drm_add_edid_modes(connector, lvds_connector->base.edid);
79e53945 514
dd06f90e 515 mode = drm_mode_duplicate(dev, lvds_connector->base.panel.fixed_mode);
311bd68e 516 if (mode == NULL)
788319d4 517 return 0;
79e53945 518
788319d4
CW
519 drm_mode_probed_add(connector, mode);
520 return 1;
79e53945
JB
521}
522
0544edfd
TB
523static int intel_no_modeset_on_lid_dmi_callback(const struct dmi_system_id *id)
524{
bc0daf48 525 DRM_INFO("Skipping forced modeset for %s\n", id->ident);
0544edfd
TB
526 return 1;
527}
528
529/* The GPU hangs up on these systems if modeset is performed on LID open */
530static const struct dmi_system_id intel_no_modeset_on_lid[] = {
531 {
532 .callback = intel_no_modeset_on_lid_dmi_callback,
533 .ident = "Toshiba Tecra A11",
534 .matches = {
535 DMI_MATCH(DMI_SYS_VENDOR, "TOSHIBA"),
536 DMI_MATCH(DMI_PRODUCT_NAME, "TECRA A11"),
537 },
538 },
539
540 { } /* terminating entry */
541};
542
c9354c85
LT
543/*
544 * Lid events. Note the use of 'modeset_on_lid':
545 * - we set it on lid close, and reset it on open
546 * - we use it as a "only once" bit (ie we ignore
547 * duplicate events where it was already properly
548 * set/reset)
549 * - the suspend/resume paths will also set it to
550 * zero, since they restore the mode ("lid open").
551 */
c1c7af60
JB
552static int intel_lid_notify(struct notifier_block *nb, unsigned long val,
553 void *unused)
554{
db1740a0
JN
555 struct intel_lvds_connector *lvds_connector =
556 container_of(nb, struct intel_lvds_connector, lid_notifier);
557 struct drm_connector *connector = &lvds_connector->base.base;
558 struct drm_device *dev = connector->dev;
559 struct drm_i915_private *dev_priv = dev->dev_private;
c1c7af60 560
2fb4e61d
AW
561 if (dev->switch_power_state != DRM_SWITCH_POWER_ON)
562 return NOTIFY_OK;
563
a2565377
ZY
564 /*
565 * check and update the status of LVDS connector after receiving
566 * the LID nofication event.
567 */
db1740a0 568 connector->status = connector->funcs->detect(connector, false);
7b334fcb 569
0544edfd
TB
570 /* Don't force modeset on machines where it causes a GPU lockup */
571 if (dmi_check_system(intel_no_modeset_on_lid))
572 return NOTIFY_OK;
c9354c85
LT
573 if (!acpi_lid_open()) {
574 dev_priv->modeset_on_lid = 1;
575 return NOTIFY_OK;
06891e27 576 }
c1c7af60 577
c9354c85
LT
578 if (!dev_priv->modeset_on_lid)
579 return NOTIFY_OK;
580
581 dev_priv->modeset_on_lid = 0;
582
583 mutex_lock(&dev->mode_config.mutex);
45e2b5f6 584 intel_modeset_setup_hw_state(dev, true);
c9354c85 585 mutex_unlock(&dev->mode_config.mutex);
06324194 586
c1c7af60
JB
587 return NOTIFY_OK;
588}
589
79e53945
JB
590/**
591 * intel_lvds_destroy - unregister and free LVDS structures
592 * @connector: connector to free
593 *
594 * Unregister the DDC bus for this connector then free the driver private
595 * structure.
596 */
597static void intel_lvds_destroy(struct drm_connector *connector)
598{
db1740a0
JN
599 struct intel_lvds_connector *lvds_connector =
600 to_lvds_connector(connector);
79e53945 601
db1740a0
JN
602 if (lvds_connector->lid_notifier.notifier_call)
603 acpi_lid_notifier_unregister(&lvds_connector->lid_notifier);
79e53945 604
9cd300e0
JN
605 if (!IS_ERR_OR_NULL(lvds_connector->base.edid))
606 kfree(lvds_connector->base.edid);
607
db1740a0 608 intel_panel_destroy_backlight(connector->dev);
1d508706 609 intel_panel_fini(&lvds_connector->base.panel);
aaa6fd2a 610
79e53945
JB
611 drm_sysfs_connector_remove(connector);
612 drm_connector_cleanup(connector);
613 kfree(connector);
614}
615
335041ed
JB
616static int intel_lvds_set_property(struct drm_connector *connector,
617 struct drm_property *property,
618 uint64_t value)
619{
4d891523 620 struct intel_connector *intel_connector = to_intel_connector(connector);
3fbe18d6 621 struct drm_device *dev = connector->dev;
3fbe18d6 622
788319d4 623 if (property == dev->mode_config.scaling_mode_property) {
62165e0d 624 struct drm_crtc *crtc;
bb8a3560 625
53bd8389
JB
626 if (value == DRM_MODE_SCALE_NONE) {
627 DRM_DEBUG_KMS("no scaling not supported\n");
788319d4 628 return -EINVAL;
3fbe18d6 629 }
788319d4 630
4d891523 631 if (intel_connector->panel.fitting_mode == value) {
3fbe18d6
ZY
632 /* the LVDS scaling property is not changed */
633 return 0;
634 }
4d891523 635 intel_connector->panel.fitting_mode = value;
62165e0d
JN
636
637 crtc = intel_attached_encoder(connector)->base.crtc;
3fbe18d6
ZY
638 if (crtc && crtc->enabled) {
639 /*
640 * If the CRTC is enabled, the display will be changed
641 * according to the new panel fitting mode.
642 */
a6778b3c
DV
643 intel_set_mode(crtc, &crtc->mode,
644 crtc->x, crtc->y, crtc->fb);
3fbe18d6
ZY
645 }
646 }
647
335041ed
JB
648 return 0;
649}
650
79e53945 651static const struct drm_encoder_helper_funcs intel_lvds_helper_funcs = {
79e53945 652 .mode_fixup = intel_lvds_mode_fixup,
79e53945 653 .mode_set = intel_lvds_mode_set,
1f703855 654 .disable = intel_encoder_noop,
79e53945
JB
655};
656
657static const struct drm_connector_helper_funcs intel_lvds_connector_helper_funcs = {
658 .get_modes = intel_lvds_get_modes,
659 .mode_valid = intel_lvds_mode_valid,
df0e9248 660 .best_encoder = intel_best_encoder,
79e53945
JB
661};
662
663static const struct drm_connector_funcs intel_lvds_connector_funcs = {
c22834ec 664 .dpms = intel_connector_dpms,
79e53945
JB
665 .detect = intel_lvds_detect,
666 .fill_modes = drm_helper_probe_single_connector_modes,
335041ed 667 .set_property = intel_lvds_set_property,
79e53945
JB
668 .destroy = intel_lvds_destroy,
669};
670
79e53945 671static const struct drm_encoder_funcs intel_lvds_enc_funcs = {
ea5b213a 672 .destroy = intel_encoder_destroy,
79e53945
JB
673};
674
425d244c
JW
675static int __init intel_no_lvds_dmi_callback(const struct dmi_system_id *id)
676{
bc0daf48 677 DRM_INFO("Skipping LVDS initialization for %s\n", id->ident);
425d244c
JW
678 return 1;
679}
79e53945 680
425d244c 681/* These systems claim to have LVDS, but really don't */
93c05f22 682static const struct dmi_system_id intel_no_lvds[] = {
425d244c
JW
683 {
684 .callback = intel_no_lvds_dmi_callback,
685 .ident = "Apple Mac Mini (Core series)",
686 .matches = {
98acd46f 687 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
688 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini1,1"),
689 },
690 },
691 {
692 .callback = intel_no_lvds_dmi_callback,
693 .ident = "Apple Mac Mini (Core 2 series)",
694 .matches = {
98acd46f 695 DMI_MATCH(DMI_SYS_VENDOR, "Apple"),
425d244c
JW
696 DMI_MATCH(DMI_PRODUCT_NAME, "Macmini2,1"),
697 },
698 },
699 {
700 .callback = intel_no_lvds_dmi_callback,
701 .ident = "MSI IM-945GSE-A",
702 .matches = {
703 DMI_MATCH(DMI_SYS_VENDOR, "MSI"),
704 DMI_MATCH(DMI_PRODUCT_NAME, "A9830IMS"),
705 },
706 },
707 {
708 .callback = intel_no_lvds_dmi_callback,
709 .ident = "Dell Studio Hybrid",
710 .matches = {
711 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
712 DMI_MATCH(DMI_PRODUCT_NAME, "Studio Hybrid 140g"),
713 },
714 },
70aa96ca
JW
715 {
716 .callback = intel_no_lvds_dmi_callback,
b066254f
PC
717 .ident = "Dell OptiPlex FX170",
718 .matches = {
719 DMI_MATCH(DMI_SYS_VENDOR, "Dell Inc."),
720 DMI_MATCH(DMI_PRODUCT_NAME, "OptiPlex FX170"),
721 },
722 },
723 {
724 .callback = intel_no_lvds_dmi_callback,
70aa96ca
JW
725 .ident = "AOpen Mini PC",
726 .matches = {
727 DMI_MATCH(DMI_SYS_VENDOR, "AOpen"),
728 DMI_MATCH(DMI_PRODUCT_NAME, "i965GMx-IF"),
729 },
730 },
ed8c754b
TV
731 {
732 .callback = intel_no_lvds_dmi_callback,
733 .ident = "AOpen Mini PC MP915",
734 .matches = {
735 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
736 DMI_MATCH(DMI_BOARD_NAME, "i915GMx-F"),
737 },
738 },
22ab70d3
KP
739 {
740 .callback = intel_no_lvds_dmi_callback,
741 .ident = "AOpen i915GMm-HFS",
742 .matches = {
743 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
744 DMI_MATCH(DMI_BOARD_NAME, "i915GMm-HFS"),
745 },
746 },
e57b6886
DV
747 {
748 .callback = intel_no_lvds_dmi_callback,
749 .ident = "AOpen i45GMx-I",
750 .matches = {
751 DMI_MATCH(DMI_BOARD_VENDOR, "AOpen"),
752 DMI_MATCH(DMI_BOARD_NAME, "i45GMx-I"),
753 },
754 },
fa0864b2
MC
755 {
756 .callback = intel_no_lvds_dmi_callback,
757 .ident = "Aopen i945GTt-VFA",
758 .matches = {
759 DMI_MATCH(DMI_PRODUCT_VERSION, "AO00001JW"),
760 },
761 },
9875557e
SB
762 {
763 .callback = intel_no_lvds_dmi_callback,
764 .ident = "Clientron U800",
765 .matches = {
766 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
767 DMI_MATCH(DMI_PRODUCT_NAME, "U800"),
768 },
769 },
6a574b5b 770 {
44306ab3
JS
771 .callback = intel_no_lvds_dmi_callback,
772 .ident = "Clientron E830",
773 .matches = {
774 DMI_MATCH(DMI_SYS_VENDOR, "Clientron"),
775 DMI_MATCH(DMI_PRODUCT_NAME, "E830"),
776 },
777 },
778 {
6a574b5b
HG
779 .callback = intel_no_lvds_dmi_callback,
780 .ident = "Asus EeeBox PC EB1007",
781 .matches = {
782 DMI_MATCH(DMI_SYS_VENDOR, "ASUSTeK Computer INC."),
783 DMI_MATCH(DMI_PRODUCT_NAME, "EB1007"),
784 },
785 },
0999bbe0
AJ
786 {
787 .callback = intel_no_lvds_dmi_callback,
788 .ident = "Asus AT5NM10T-I",
789 .matches = {
790 DMI_MATCH(DMI_BOARD_VENDOR, "ASUSTeK Computer INC."),
791 DMI_MATCH(DMI_BOARD_NAME, "AT5NM10T-I"),
792 },
793 },
33471119
JBG
794 {
795 .callback = intel_no_lvds_dmi_callback,
796 .ident = "Hewlett-Packard HP t5740e Thin Client",
797 .matches = {
798 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
799 DMI_MATCH(DMI_PRODUCT_NAME, "HP t5740e Thin Client"),
800 },
801 },
f5b8a7ed
MG
802 {
803 .callback = intel_no_lvds_dmi_callback,
804 .ident = "Hewlett-Packard t5745",
805 .matches = {
806 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 807 DMI_MATCH(DMI_PRODUCT_NAME, "hp t5745"),
f5b8a7ed
MG
808 },
809 },
810 {
811 .callback = intel_no_lvds_dmi_callback,
812 .ident = "Hewlett-Packard st5747",
813 .matches = {
814 DMI_MATCH(DMI_BOARD_VENDOR, "Hewlett-Packard"),
62004978 815 DMI_MATCH(DMI_PRODUCT_NAME, "hp st5747"),
f5b8a7ed
MG
816 },
817 },
97effadb
AA
818 {
819 .callback = intel_no_lvds_dmi_callback,
820 .ident = "MSI Wind Box DC500",
821 .matches = {
822 DMI_MATCH(DMI_BOARD_VENDOR, "MICRO-STAR INTERNATIONAL CO., LTD"),
823 DMI_MATCH(DMI_BOARD_NAME, "MS-7469"),
824 },
825 },
9756fe38
SS
826 {
827 .callback = intel_no_lvds_dmi_callback,
828 .ident = "ZOTAC ZBOXSD-ID12/ID13",
829 .matches = {
830 DMI_MATCH(DMI_BOARD_VENDOR, "ZOTAC"),
831 DMI_MATCH(DMI_BOARD_NAME, "ZBOXSD-ID12/ID13"),
832 },
833 },
a51d4ed0
CW
834 {
835 .callback = intel_no_lvds_dmi_callback,
836 .ident = "Gigabyte GA-D525TUD",
837 .matches = {
838 DMI_MATCH(DMI_BOARD_VENDOR, "Gigabyte Technology Co., Ltd."),
839 DMI_MATCH(DMI_BOARD_NAME, "D525TUD"),
840 },
841 },
c31407a3
CW
842 {
843 .callback = intel_no_lvds_dmi_callback,
844 .ident = "Supermicro X7SPA-H",
845 .matches = {
846 DMI_MATCH(DMI_SYS_VENDOR, "Supermicro"),
847 DMI_MATCH(DMI_PRODUCT_NAME, "X7SPA-H"),
848 },
849 },
425d244c
JW
850
851 { } /* terminating entry */
852};
79e53945 853
18f9ed12
ZY
854/**
855 * intel_find_lvds_downclock - find the reduced downclock for LVDS in EDID
856 * @dev: drm device
857 * @connector: LVDS connector
858 *
859 * Find the reduced downclock for LVDS in EDID.
860 */
861static void intel_find_lvds_downclock(struct drm_device *dev,
788319d4
CW
862 struct drm_display_mode *fixed_mode,
863 struct drm_connector *connector)
18f9ed12
ZY
864{
865 struct drm_i915_private *dev_priv = dev->dev_private;
788319d4 866 struct drm_display_mode *scan;
18f9ed12
ZY
867 int temp_downclock;
868
788319d4 869 temp_downclock = fixed_mode->clock;
18f9ed12
ZY
870 list_for_each_entry(scan, &connector->probed_modes, head) {
871 /*
872 * If one mode has the same resolution with the fixed_panel
873 * mode while they have the different refresh rate, it means
874 * that the reduced downclock is found for the LVDS. In such
875 * case we can set the different FPx0/1 to dynamically select
876 * between low and high frequency.
877 */
788319d4
CW
878 if (scan->hdisplay == fixed_mode->hdisplay &&
879 scan->hsync_start == fixed_mode->hsync_start &&
880 scan->hsync_end == fixed_mode->hsync_end &&
881 scan->htotal == fixed_mode->htotal &&
882 scan->vdisplay == fixed_mode->vdisplay &&
883 scan->vsync_start == fixed_mode->vsync_start &&
884 scan->vsync_end == fixed_mode->vsync_end &&
885 scan->vtotal == fixed_mode->vtotal) {
18f9ed12
ZY
886 if (scan->clock < temp_downclock) {
887 /*
888 * The downclock is already found. But we
889 * expect to find the lower downclock.
890 */
891 temp_downclock = scan->clock;
892 }
893 }
894 }
788319d4 895 if (temp_downclock < fixed_mode->clock && i915_lvds_downclock) {
18f9ed12
ZY
896 /* We found the downclock for LVDS. */
897 dev_priv->lvds_downclock_avail = 1;
898 dev_priv->lvds_downclock = temp_downclock;
899 DRM_DEBUG_KMS("LVDS downclock is found in EDID. "
788319d4
CW
900 "Normal clock %dKhz, downclock %dKhz\n",
901 fixed_mode->clock, temp_downclock);
18f9ed12 902 }
18f9ed12
ZY
903}
904
7cf4f69d
ZY
905/*
906 * Enumerate the child dev array parsed from VBT to check whether
907 * the LVDS is present.
908 * If it is present, return 1.
909 * If it is not present, return false.
910 * If no child dev is parsed from VBT, it assumes that the LVDS is present.
7cf4f69d 911 */
270eea0f
CW
912static bool lvds_is_present_in_vbt(struct drm_device *dev,
913 u8 *i2c_pin)
7cf4f69d
ZY
914{
915 struct drm_i915_private *dev_priv = dev->dev_private;
425904dd 916 int i;
7cf4f69d
ZY
917
918 if (!dev_priv->child_dev_num)
425904dd 919 return true;
7cf4f69d 920
7cf4f69d 921 for (i = 0; i < dev_priv->child_dev_num; i++) {
425904dd
CW
922 struct child_device_config *child = dev_priv->child_dev + i;
923
924 /* If the device type is not LFP, continue.
925 * We have to check both the new identifiers as well as the
926 * old for compatibility with some BIOSes.
7cf4f69d 927 */
425904dd
CW
928 if (child->device_type != DEVICE_TYPE_INT_LFP &&
929 child->device_type != DEVICE_TYPE_LFP)
7cf4f69d
ZY
930 continue;
931
3bd7d909
DK
932 if (intel_gmbus_is_port_valid(child->i2c_pin))
933 *i2c_pin = child->i2c_pin;
270eea0f 934
425904dd
CW
935 /* However, we cannot trust the BIOS writers to populate
936 * the VBT correctly. Since LVDS requires additional
937 * information from AIM blocks, a non-zero addin offset is
938 * a good indicator that the LVDS is actually present.
7cf4f69d 939 */
425904dd
CW
940 if (child->addin_offset)
941 return true;
942
943 /* But even then some BIOS writers perform some black magic
944 * and instantiate the device without reference to any
945 * additional data. Trust that if the VBT was written into
946 * the OpRegion then they have validated the LVDS's existence.
947 */
948 if (dev_priv->opregion.vbt)
949 return true;
7cf4f69d 950 }
425904dd
CW
951
952 return false;
7cf4f69d
ZY
953}
954
1974cad0
DV
955static int intel_dual_link_lvds_callback(const struct dmi_system_id *id)
956{
957 DRM_INFO("Forcing lvds to dual link mode on %s\n", id->ident);
958 return 1;
959}
960
961static const struct dmi_system_id intel_dual_link_lvds[] = {
962 {
963 .callback = intel_dual_link_lvds_callback,
964 .ident = "Apple MacBook Pro (Core i5/i7 Series)",
965 .matches = {
966 DMI_MATCH(DMI_SYS_VENDOR, "Apple Inc."),
967 DMI_MATCH(DMI_PRODUCT_NAME, "MacBookPro8,2"),
968 },
969 },
970 { } /* terminating entry */
971};
972
973bool intel_is_dual_link_lvds(struct drm_device *dev)
13c7d870
DV
974{
975 struct intel_encoder *encoder;
976 struct intel_lvds_encoder *lvds_encoder;
977
978 list_for_each_entry(encoder, &dev->mode_config.encoder_list,
979 base.head) {
980 if (encoder->type == INTEL_OUTPUT_LVDS) {
981 lvds_encoder = to_lvds_encoder(&encoder->base);
982
983 return lvds_encoder->is_dual_link;
984 }
985 }
986
987 return false;
988}
989
7dec0606 990static bool compute_is_dual_link_lvds(struct intel_lvds_encoder *lvds_encoder)
1974cad0 991{
7dec0606 992 struct drm_device *dev = lvds_encoder->base.base.dev;
1974cad0
DV
993 unsigned int val;
994 struct drm_i915_private *dev_priv = dev->dev_private;
1974cad0
DV
995
996 /* use the module option value if specified */
997 if (i915_lvds_channel_mode > 0)
998 return i915_lvds_channel_mode == 2;
999
1000 if (dmi_check_system(intel_dual_link_lvds))
1001 return true;
1002
13c7d870
DV
1003 /* BIOS should set the proper LVDS register value at boot, but
1004 * in reality, it doesn't set the value when the lid is closed;
1005 * we need to check "the value to be set" in VBT when LVDS
1006 * register is uninitialized.
1007 */
7dec0606 1008 val = I915_READ(lvds_encoder->reg);
13c7d870
DV
1009 if (!(val & ~(LVDS_PIPE_MASK | LVDS_DETECTED)))
1010 val = dev_priv->bios_lvds_val;
1011
1974cad0
DV
1012 return (val & LVDS_CLKB_POWER_MASK) == LVDS_CLKB_POWER_UP;
1013}
1014
f3cfcba6
CW
1015static bool intel_lvds_supported(struct drm_device *dev)
1016{
1017 /* With the introduction of the PCH we gained a dedicated
1018 * LVDS presence pin, use it. */
1019 if (HAS_PCH_SPLIT(dev))
1020 return true;
1021
1022 /* Otherwise LVDS was only attached to mobile products,
1023 * except for the inglorious 830gm */
1024 return IS_MOBILE(dev) && !IS_I830(dev);
1025}
1026
79e53945
JB
1027/**
1028 * intel_lvds_init - setup LVDS connectors on this device
1029 * @dev: drm device
1030 *
1031 * Create the connector, register the LVDS DDC bus, and try to figure out what
1032 * modes we can display on the LVDS panel (if present).
1033 */
c5d1b51d 1034bool intel_lvds_init(struct drm_device *dev)
79e53945
JB
1035{
1036 struct drm_i915_private *dev_priv = dev->dev_private;
29b99b48 1037 struct intel_lvds_encoder *lvds_encoder;
21d40d37 1038 struct intel_encoder *intel_encoder;
c7362c4d 1039 struct intel_lvds_connector *lvds_connector;
bb8a3560 1040 struct intel_connector *intel_connector;
79e53945
JB
1041 struct drm_connector *connector;
1042 struct drm_encoder *encoder;
1043 struct drm_display_mode *scan; /* *modes, *bios_mode; */
dd06f90e 1044 struct drm_display_mode *fixed_mode = NULL;
9cd300e0 1045 struct edid *edid;
79e53945
JB
1046 struct drm_crtc *crtc;
1047 u32 lvds;
270eea0f
CW
1048 int pipe;
1049 u8 pin;
79e53945 1050
f3cfcba6
CW
1051 if (!intel_lvds_supported(dev))
1052 return false;
1053
425d244c
JW
1054 /* Skip init on machines we know falsely report LVDS */
1055 if (dmi_check_system(intel_no_lvds))
c5d1b51d 1056 return false;
565dcd46 1057
270eea0f
CW
1058 pin = GMBUS_PORT_PANEL;
1059 if (!lvds_is_present_in_vbt(dev, &pin)) {
11ba1592 1060 DRM_DEBUG_KMS("LVDS is not present in VBT\n");
c5d1b51d 1061 return false;
38b3037e 1062 }
e99da35f 1063
c619eed4 1064 if (HAS_PCH_SPLIT(dev)) {
541998a1 1065 if ((I915_READ(PCH_LVDS) & LVDS_DETECTED) == 0)
c5d1b51d 1066 return false;
5ceb0f9b 1067 if (dev_priv->edp.support) {
28c97730 1068 DRM_DEBUG_KMS("disable LVDS for eDP support\n");
c5d1b51d 1069 return false;
32f9d658 1070 }
541998a1
ZW
1071 }
1072
29b99b48
JN
1073 lvds_encoder = kzalloc(sizeof(struct intel_lvds_encoder), GFP_KERNEL);
1074 if (!lvds_encoder)
c5d1b51d 1075 return false;
79e53945 1076
c7362c4d
JN
1077 lvds_connector = kzalloc(sizeof(struct intel_lvds_connector), GFP_KERNEL);
1078 if (!lvds_connector) {
29b99b48 1079 kfree(lvds_encoder);
c5d1b51d 1080 return false;
bb8a3560
ZW
1081 }
1082
62165e0d
JN
1083 lvds_encoder->attached_connector = lvds_connector;
1084
e9e331a8 1085 if (!HAS_PCH_SPLIT(dev)) {
29b99b48 1086 lvds_encoder->pfit_control = I915_READ(PFIT_CONTROL);
e9e331a8
CW
1087 }
1088
29b99b48 1089 intel_encoder = &lvds_encoder->base;
4ef69c7a 1090 encoder = &intel_encoder->base;
c7362c4d 1091 intel_connector = &lvds_connector->base;
ea5b213a 1092 connector = &intel_connector->base;
bb8a3560 1093 drm_connector_init(dev, &intel_connector->base, &intel_lvds_connector_funcs,
79e53945
JB
1094 DRM_MODE_CONNECTOR_LVDS);
1095
4ef69c7a 1096 drm_encoder_init(dev, &intel_encoder->base, &intel_lvds_enc_funcs,
79e53945
JB
1097 DRM_MODE_ENCODER_LVDS);
1098
c22834ec 1099 intel_encoder->enable = intel_enable_lvds;
fc683091 1100 intel_encoder->pre_pll_enable = intel_pre_pll_enable_lvds;
c22834ec 1101 intel_encoder->disable = intel_disable_lvds;
b1dc332c
DV
1102 intel_encoder->get_hw_state = intel_lvds_get_hw_state;
1103 intel_connector->get_hw_state = intel_connector_get_hw_state;
c22834ec 1104
df0e9248 1105 intel_connector_attach_encoder(intel_connector, intel_encoder);
21d40d37 1106 intel_encoder->type = INTEL_OUTPUT_LVDS;
79e53945 1107
66a9278e 1108 intel_encoder->cloneable = false;
27f8227b
JB
1109 if (HAS_PCH_SPLIT(dev))
1110 intel_encoder->crtc_mask = (1 << 0) | (1 << 1) | (1 << 2);
0b9f43a0
DV
1111 else if (IS_GEN4(dev))
1112 intel_encoder->crtc_mask = (1 << 0) | (1 << 1);
27f8227b
JB
1113 else
1114 intel_encoder->crtc_mask = (1 << 1);
1115
79e53945
JB
1116 drm_encoder_helper_add(encoder, &intel_lvds_helper_funcs);
1117 drm_connector_helper_add(connector, &intel_lvds_connector_helper_funcs);
1118 connector->display_info.subpixel_order = SubPixelHorizontalRGB;
1119 connector->interlace_allowed = false;
1120 connector->doublescan_allowed = false;
1121
7dec0606
DV
1122 if (HAS_PCH_SPLIT(dev)) {
1123 lvds_encoder->reg = PCH_LVDS;
1124 } else {
1125 lvds_encoder->reg = LVDS;
1126 }
1127
3fbe18d6
ZY
1128 /* create the scaling mode property */
1129 drm_mode_create_scaling_mode_property(dev);
662595df 1130 drm_object_attach_property(&connector->base,
3fbe18d6 1131 dev->mode_config.scaling_mode_property,
dd1ea37d 1132 DRM_MODE_SCALE_ASPECT);
4d891523 1133 intel_connector->panel.fitting_mode = DRM_MODE_SCALE_ASPECT;
79e53945
JB
1134 /*
1135 * LVDS discovery:
1136 * 1) check for EDID on DDC
1137 * 2) check for VBT data
1138 * 3) check to see if LVDS is already on
1139 * if none of the above, no panel
1140 * 4) make sure lid is open
1141 * if closed, act like it's not there for now
1142 */
1143
79e53945
JB
1144 /*
1145 * Attempt to get the fixed panel mode from DDC. Assume that the
1146 * preferred mode is the right one.
1147 */
9cd300e0
JN
1148 edid = drm_get_edid(connector, intel_gmbus_get_adapter(dev_priv, pin));
1149 if (edid) {
1150 if (drm_add_edid_modes(connector, edid)) {
3f8ff0e7 1151 drm_mode_connector_update_edid_property(connector,
9cd300e0 1152 edid);
3f8ff0e7 1153 } else {
9cd300e0
JN
1154 kfree(edid);
1155 edid = ERR_PTR(-EINVAL);
3f8ff0e7 1156 }
9cd300e0
JN
1157 } else {
1158 edid = ERR_PTR(-ENOENT);
3f8ff0e7 1159 }
9cd300e0
JN
1160 lvds_connector->base.edid = edid;
1161
1162 if (IS_ERR_OR_NULL(edid)) {
788319d4
CW
1163 /* Didn't get an EDID, so
1164 * Set wide sync ranges so we get all modes
1165 * handed to valid_mode for checking
1166 */
1167 connector->display_info.min_vfreq = 0;
1168 connector->display_info.max_vfreq = 200;
1169 connector->display_info.min_hfreq = 0;
1170 connector->display_info.max_hfreq = 200;
1171 }
79e53945
JB
1172
1173 list_for_each_entry(scan, &connector->probed_modes, head) {
79e53945 1174 if (scan->type & DRM_MODE_TYPE_PREFERRED) {
6a9d51b7
CW
1175 DRM_DEBUG_KMS("using preferred mode from EDID: ");
1176 drm_mode_debug_printmodeline(scan);
1177
dd06f90e 1178 fixed_mode = drm_mode_duplicate(dev, scan);
6a9d51b7
CW
1179 if (fixed_mode) {
1180 intel_find_lvds_downclock(dev, fixed_mode,
1181 connector);
1182 goto out;
1183 }
79e53945 1184 }
79e53945
JB
1185 }
1186
1187 /* Failed to get EDID, what about VBT? */
88631706 1188 if (dev_priv->lfp_lvds_vbt_mode) {
6a9d51b7
CW
1189 DRM_DEBUG_KMS("using mode from VBT: ");
1190 drm_mode_debug_printmodeline(dev_priv->lfp_lvds_vbt_mode);
1191
dd06f90e
JN
1192 fixed_mode = drm_mode_duplicate(dev, dev_priv->lfp_lvds_vbt_mode);
1193 if (fixed_mode) {
1194 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
e285f3cd
JB
1195 goto out;
1196 }
79e53945
JB
1197 }
1198
1199 /*
1200 * If we didn't get EDID, try checking if the panel is already turned
1201 * on. If so, assume that whatever is currently programmed is the
1202 * correct mode.
1203 */
541998a1 1204
f2b115e6 1205 /* Ironlake: FIXME if still fail, not try pipe mode now */
c619eed4 1206 if (HAS_PCH_SPLIT(dev))
541998a1
ZW
1207 goto failed;
1208
79e53945
JB
1209 lvds = I915_READ(LVDS);
1210 pipe = (lvds & LVDS_PIPEB_SELECT) ? 1 : 0;
f875c15a 1211 crtc = intel_get_crtc_for_pipe(dev, pipe);
79e53945
JB
1212
1213 if (crtc && (lvds & LVDS_PORT_EN)) {
dd06f90e
JN
1214 fixed_mode = intel_crtc_mode_get(dev, crtc);
1215 if (fixed_mode) {
6a9d51b7
CW
1216 DRM_DEBUG_KMS("using current (BIOS) mode: ");
1217 drm_mode_debug_printmodeline(fixed_mode);
dd06f90e 1218 fixed_mode->type |= DRM_MODE_TYPE_PREFERRED;
565dcd46 1219 goto out;
79e53945
JB
1220 }
1221 }
1222
1223 /* If we still don't have a mode after all that, give up. */
dd06f90e 1224 if (!fixed_mode)
79e53945
JB
1225 goto failed;
1226
79e53945 1227out:
7dec0606 1228 lvds_encoder->is_dual_link = compute_is_dual_link_lvds(lvds_encoder);
13c7d870
DV
1229 DRM_DEBUG_KMS("detected %s-link lvds configuration\n",
1230 lvds_encoder->is_dual_link ? "dual" : "single");
1231
24ded204
DV
1232 /*
1233 * Unlock registers and just
1234 * leave them unlocked
1235 */
c619eed4 1236 if (HAS_PCH_SPLIT(dev)) {
ed10fca9
KP
1237 I915_WRITE(PCH_PP_CONTROL,
1238 I915_READ(PCH_PP_CONTROL) | PANEL_UNLOCK_REGS);
1239 } else {
ed10fca9
KP
1240 I915_WRITE(PP_CONTROL,
1241 I915_READ(PP_CONTROL) | PANEL_UNLOCK_REGS);
541998a1 1242 }
db1740a0
JN
1243 lvds_connector->lid_notifier.notifier_call = intel_lid_notify;
1244 if (acpi_lid_notifier_register(&lvds_connector->lid_notifier)) {
28c97730 1245 DRM_DEBUG_KMS("lid notifier registration failed\n");
db1740a0 1246 lvds_connector->lid_notifier.notifier_call = NULL;
c1c7af60 1247 }
79e53945 1248 drm_sysfs_connector_add(connector);
aaa6fd2a 1249
dd06f90e 1250 intel_panel_init(&intel_connector->panel, fixed_mode);
0657b6b1 1251 intel_panel_setup_backlight(connector);
aaa6fd2a 1252
c5d1b51d 1253 return true;
79e53945
JB
1254
1255failed:
8a4c47f3 1256 DRM_DEBUG_KMS("No LVDS modes found, disabling.\n");
79e53945 1257 drm_connector_cleanup(connector);
1991bdfa 1258 drm_encoder_cleanup(encoder);
dd06f90e
JN
1259 if (fixed_mode)
1260 drm_mode_destroy(dev, fixed_mode);
29b99b48 1261 kfree(lvds_encoder);
c7362c4d 1262 kfree(lvds_connector);
c5d1b51d 1263 return false;
79e53945 1264}