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drm/i915: Share crtc setup and teardown between dpms and disable/enable
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
23f09ce3
CW		 173struct intel_overlay {
174 struct drm_device *dev;
175 struct intel_crtc *crtc;
176 struct drm_i915_gem_object *vid_bo;
177 struct drm_i915_gem_object *old_vid_bo;
178 int active;
179 int pfit_active;
180 u32 pfit_vscale_ratio; /* shifted-point number, (1<<12) == 1.0 */
181 u32 color_key;
182 u32 brightness, contrast, saturation;
183 u32 old_xscale, old_yscale;
184 /* register access */
185 u32 flip_addr;
186 struct drm_i915_gem_object *reg_bo;
187 /* flip handling */
188 uint32_t last_flip_req;
b303cf95 189 void (*flip_tail)(struct intel_overlay *);
23f09ce3
CW		 190};
191
8d74f656
CW		 192static struct overlay_registers *
193intel_overlay_map_regs(struct intel_overlay *overlay)
194{
195 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
196 struct overlay_registers *regs;
197
9bb2ff73 198 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
8d74f656 199 regs = overlay->reg_bo->phys_obj->handle->vaddr;
9bb2ff73 200 else
8d74f656
CW		 201 regs = io_mapping_map_wc(dev_priv->mm.gtt_mapping,
202 overlay->reg_bo->gtt_offset);
203
9bb2ff73 204 return regs;
8d74f656
CW		 205}
206
9bb2ff73
CW		 207static void intel_overlay_unmap_regs(struct intel_overlay *overlay,
208 struct overlay_registers *regs)
8d74f656
CW		 209{
210 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
9bb2ff73 211 io_mapping_unmap(regs);
02e792fb
DV		 212}
213
b6c028e0 214static int intel_overlay_do_wait_request(struct intel_overlay *overlay,
8dc5d147 215 struct drm_i915_gem_request *request,
b6c028e0 216 bool interruptible,
b303cf95 217 void (*tail)(struct intel_overlay *))
02e792fb
DV		 218{
219 struct drm_device *dev = overlay->dev;
852835f3 220 drm_i915_private_t *dev_priv = dev->dev_private;
b6c028e0 221 int ret;
02e792fb 222
b303cf95 223 BUG_ON(overlay->last_flip_req);
852835f3 224 overlay->last_flip_req =
8dc5d147 225 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
03f77ea5
DV		 226 if (overlay->last_flip_req == 0)
227 return -ENOMEM;
02e792fb 228
b303cf95 229 overlay->flip_tail = tail;
852835f3 230 ret = i915_do_wait_request(dev,
722506f0
CW		 231 overlay->last_flip_req, true,
232 &dev_priv->render_ring);
b6c028e0 233 if (ret)
03f77ea5 234 return ret;
02e792fb 235
03f77ea5 236 overlay->last_flip_req = 0;
02e792fb
DV		 237 return 0;
238}
239
106dadac
CW		 240/* Workaround for i830 bug where pipe a must be enable to change control regs */
241static int
242i830_activate_pipe_a(struct drm_device *dev)
243{
244 drm_i915_private_t *dev_priv = dev->dev_private;
245 struct intel_crtc *crtc;
246 struct drm_crtc_helper_funcs *crtc_funcs;
247 struct drm_display_mode vesa_640x480 = {
248 DRM_MODE("640x480", DRM_MODE_TYPE_DRIVER, 25175, 640, 656,
249 752, 800, 0, 480, 489, 492, 525, 0,
250 DRM_MODE_FLAG_NHSYNC | DRM_MODE_FLAG_NVSYNC)
251 }, *mode;
252
253 crtc = to_intel_crtc(dev_priv->pipe_to_crtc_mapping[0]);
254 if (crtc->dpms_mode == DRM_MODE_DPMS_ON)
255 return 0;
256
257 /* most i8xx have pipe a forced on, so don't trust dpms mode */
5eddb70b 258 if (I915_READ(PIPEACONF) & PIPECONF_ENABLE)
106dadac
CW		 259 return 0;
260
261 crtc_funcs = crtc->base.helper_private;
262 if (crtc_funcs->dpms == NULL)
263 return 0;
264
265 DRM_DEBUG_DRIVER("Enabling pipe A in order to enable overlay\n");
266
267 mode = drm_mode_duplicate(dev, &vesa_640x480);
268 drm_mode_set_crtcinfo(mode, CRTC_INTERLACE_HALVE_V);
269 if(!drm_crtc_helper_set_mode(&crtc->base, mode,
270 crtc->base.x, crtc->base.y,
271 crtc->base.fb))
272 return 0;
273
274 crtc_funcs->dpms(&crtc->base, DRM_MODE_DPMS_ON);
275 return 1;
276}
277
278static void
279i830_deactivate_pipe_a(struct drm_device *dev)
280{
281 drm_i915_private_t *dev_priv = dev->dev_private;
282 struct drm_crtc *crtc = dev_priv->pipe_to_crtc_mapping[0];
283 struct drm_crtc_helper_funcs *crtc_funcs = crtc->helper_private;
284
285 crtc_funcs->dpms(crtc, DRM_MODE_DPMS_OFF);
286}
287
b6c028e0
CW		 288/* overlay needs to be disable in OCMD reg */
289static int intel_overlay_on(struct intel_overlay *overlay)
290{
291 struct drm_device *dev = overlay->dev;
8dc5d147 292 struct drm_i915_gem_request *request;
106dadac
CW		 293 int pipe_a_quirk = 0;
294 int ret;
b6c028e0
CW		 295
296 BUG_ON(overlay->active);
b6c028e0
CW		 297 overlay->active = 1;
298
106dadac
CW		 299 if (IS_I830(dev)) {
300 pipe_a_quirk = i830_activate_pipe_a(dev);
301 if (pipe_a_quirk < 0)
302 return pipe_a_quirk;
303 }
304
8dc5d147 305 request = kzalloc(sizeof(*request), GFP_KERNEL);
106dadac
CW		 306 if (request == NULL) {
307 ret = -ENOMEM;
308 goto out;
309 }
8dc5d147 310
b6c028e0
CW		 311 BEGIN_LP_RING(4);
312 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
313 OUT_RING(overlay->flip_addr | OFC_UPDATE);
314 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
315 OUT_RING(MI_NOOP);
316 ADVANCE_LP_RING();
317
b303cf95 318 ret = intel_overlay_do_wait_request(overlay, request, true, NULL);
106dadac
CW		 319out:
320 if (pipe_a_quirk)
321 i830_deactivate_pipe_a(dev);
322
323 return ret;
b6c028e0
CW		 324}
325
02e792fb 326/* overlay needs to be enabled in OCMD reg */
8dc5d147
CW		 327static int intel_overlay_continue(struct intel_overlay *overlay,
328 bool load_polyphase_filter)
02e792fb
DV		 329{
330 struct drm_device *dev = overlay->dev;
331 drm_i915_private_t *dev_priv = dev->dev_private;
8dc5d147 332 struct drm_i915_gem_request *request;
02e792fb
DV		 333 u32 flip_addr = overlay->flip_addr;
334 u32 tmp;
02e792fb
DV		 335
336 BUG_ON(!overlay->active);
337
8dc5d147
CW		 338 request = kzalloc(sizeof(*request), GFP_KERNEL);
339 if (request == NULL)
340 return -ENOMEM;
341
02e792fb
DV		 342 if (load_polyphase_filter)
343 flip_addr |= OFC_UPDATE;
344
345 /* check for underruns */
346 tmp = I915_READ(DOVSTA);
347 if (tmp & (1 << 17))
348 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
349
4f8a567c 350 BEGIN_LP_RING(2);
02e792fb
DV		 351 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
352 OUT_RING(flip_addr);
5a5a0c64
DV		 353 ADVANCE_LP_RING();
354
852835f3 355 overlay->last_flip_req =
8dc5d147
CW		 356 i915_add_request(dev, NULL, request, &dev_priv->render_ring);
357 return 0;
5a5a0c64
DV		 358}
359
b303cf95
CW		 360static void intel_overlay_release_old_vid_tail(struct intel_overlay *overlay)
361{
362 struct drm_gem_object *obj = &overlay->old_vid_bo->base;
363
364 i915_gem_object_unpin(obj);
365 drm_gem_object_unreference(obj);
366
367 overlay->old_vid_bo = NULL;
368}
369
370static void intel_overlay_off_tail(struct intel_overlay *overlay)
371{
372 struct drm_gem_object *obj;
373
374 /* never have the overlay hw on without showing a frame */
375 BUG_ON(!overlay->vid_bo);
376 obj = &overlay->vid_bo->base;
377
378 i915_gem_object_unpin(obj);
379 drm_gem_object_unreference(obj);
380 overlay->vid_bo = NULL;
381
382 overlay->crtc->overlay = NULL;
383 overlay->crtc = NULL;
384 overlay->active = 0;
385}
386
02e792fb 387/* overlay needs to be disabled in OCMD reg */
5dcdbcb0
CW		 388static int intel_overlay_off(struct intel_overlay *overlay,
389 bool interruptible)
02e792fb 390{
02e792fb 391 struct drm_device *dev = overlay->dev;
8dc5d147
CW		 392 u32 flip_addr = overlay->flip_addr;
393 struct drm_i915_gem_request *request;
02e792fb
DV		 394
395 BUG_ON(!overlay->active);
396
8dc5d147
CW		 397 request = kzalloc(sizeof(*request), GFP_KERNEL);
398 if (request == NULL)
399 return -ENOMEM;
400
02e792fb
DV		 401 /* According to intel docs the overlay hw may hang (when switching
402 * off) without loading the filter coeffs. It is however unclear whether
403 * this applies to the disabling of the overlay or to the switching off
404 * of the hw. Do it in both cases */
405 flip_addr |= OFC_UPDATE;
406
8dfbc340 407 BEGIN_LP_RING(6);
02e792fb 408 /* wait for overlay to go idle */
02e792fb
DV		 409 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
410 OUT_RING(flip_addr);
722506f0 411 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb 412 /* turn overlay off */
722506f0 413 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 414 OUT_RING(flip_addr);
722506f0 415 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
02e792fb
DV		 416 ADVANCE_LP_RING();
417
5dcdbcb0 418 return intel_overlay_do_wait_request(overlay, request, interruptible,
b303cf95 419 intel_overlay_off_tail);
12ca45fe
DV		 420}
421
03f77ea5
DV		 422/* recover from an interruption due to a signal
423 * We have to be careful not to repeat work forever an make forward progess. */
5dcdbcb0
CW		 424static int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
425 bool interruptible)
03f77ea5
DV		 426{
427 struct drm_device *dev = overlay->dev;
852835f3 428 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5 429 int ret;
03f77ea5 430
b303cf95
CW		 431 if (overlay->last_flip_req == 0)
432 return 0;
03f77ea5 433
852835f3 434 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 435 interruptible, &dev_priv->render_ring);
b6c028e0 436 if (ret)
03f77ea5
DV		 437 return ret;
438
b303cf95
CW		 439 if (overlay->flip_tail)
440 overlay->flip_tail(overlay);
b6c028e0 441
03f77ea5
DV		 442 overlay->last_flip_req = 0;
443 return 0;
444}
445
5a5a0c64
DV		 446/* Wait for pending overlay flip and release old frame.
447 * Needs to be called before the overlay register are changed
8d74f656
CW		 448 * via intel_overlay_(un)map_regs
449 */
02e792fb
DV		 450static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
451{
5cd68c98
CW		 452 struct drm_device *dev = overlay->dev;
453 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 454 int ret;
02e792fb 455
5cd68c98
CW		 456 /* Only wait if there is actually an old frame to release to
457 * guarantee forward progress.
458 */
03f77ea5
DV		 459 if (!overlay->old_vid_bo)
460 return 0;
461
5cd68c98 462 if (I915_READ(ISR) & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT) {
8dc5d147
CW		 463 struct drm_i915_gem_request *request;
464
5cd68c98 465 /* synchronous slowpath */
8dc5d147
CW		 466 request = kzalloc(sizeof(*request), GFP_KERNEL);
467 if (request == NULL)
468 return -ENOMEM;
469
5cd68c98
CW		 470 BEGIN_LP_RING(2);
471 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
472 OUT_RING(MI_NOOP);
473 ADVANCE_LP_RING();
474
8dc5d147 475 ret = intel_overlay_do_wait_request(overlay, request, true,
b303cf95 476 intel_overlay_release_old_vid_tail);
5cd68c98
CW		 477 if (ret)
478 return ret;
479 }
02e792fb 480
5cd68c98 481 intel_overlay_release_old_vid_tail(overlay);
02e792fb
DV		 482 return 0;
483}
484
485struct put_image_params {
486 int format;
487 short dst_x;
488 short dst_y;
489 short dst_w;
490 short dst_h;
491 short src_w;
492 short src_scan_h;
493 short src_scan_w;
494 short src_h;
495 short stride_Y;
496 short stride_UV;
497 int offset_Y;
498 int offset_U;
499 int offset_V;
500};
501
502static int packed_depth_bytes(u32 format)
503{
504 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 505 case I915_OVERLAY_YUV422:
506 return 4;
507 case I915_OVERLAY_YUV411:
508 /* return 6; not implemented */
509 default:
510 return -EINVAL;
02e792fb
DV		 511 }
512}
513
514static int packed_width_bytes(u32 format, short width)
515{
516 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 517 case I915_OVERLAY_YUV422:
518 return width << 1;
519 default:
520 return -EINVAL;
02e792fb
DV		 521 }
522}
523
524static int uv_hsubsampling(u32 format)
525{
526 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 527 case I915_OVERLAY_YUV422:
528 case I915_OVERLAY_YUV420:
529 return 2;
530 case I915_OVERLAY_YUV411:
531 case I915_OVERLAY_YUV410:
532 return 4;
533 default:
534 return -EINVAL;
02e792fb
DV		 535 }
536}
537
538static int uv_vsubsampling(u32 format)
539{
540 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 541 case I915_OVERLAY_YUV420:
542 case I915_OVERLAY_YUV410:
543 return 2;
544 case I915_OVERLAY_YUV422:
545 case I915_OVERLAY_YUV411:
546 return 1;
547 default:
548 return -EINVAL;
02e792fb
DV		 549 }
550}
551
552static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
553{
554 u32 mask, shift, ret;
555 if (IS_I9XX(dev)) {
556 mask = 0x3f;
557 shift = 6;
558 } else {
559 mask = 0x1f;
560 shift = 5;
561 }
562 ret = ((offset + width + mask) >> shift) - (offset >> shift);
563 if (IS_I9XX(dev))
564 ret <<= 1;
565 ret -=1;
566 return ret << 2;
567}
568
569static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
570 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
571 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
572 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
573 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
574 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
575 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
576 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
577 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
578 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
579 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
580 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
581 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
582 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
583 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
584 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
585 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 586 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
587};
588
02e792fb
DV		 589static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
590 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
591 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
592 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
593 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
594 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
595 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
596 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
597 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 598 0x3000, 0x0800, 0x3000
599};
02e792fb
DV		 600
601static void update_polyphase_filter(struct overlay_registers *regs)
602{
603 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
604 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
605}
606
607static bool update_scaling_factors(struct intel_overlay *overlay,
608 struct overlay_registers *regs,
609 struct put_image_params *params)
610{
611 /* fixed point with a 12 bit shift */
612 u32 xscale, yscale, xscale_UV, yscale_UV;
613#define FP_SHIFT 12
614#define FRACT_MASK 0xfff
615 bool scale_changed = false;
616 int uv_hscale = uv_hsubsampling(params->format);
617 int uv_vscale = uv_vsubsampling(params->format);
618
619 if (params->dst_w > 1)
620 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
621 /(params->dst_w);
622 else
623 xscale = 1 << FP_SHIFT;
624
625 if (params->dst_h > 1)
626 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
627 /(params->dst_h);
628 else
629 yscale = 1 << FP_SHIFT;
630
631 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 632 xscale_UV = xscale/uv_hscale;
633 yscale_UV = yscale/uv_vscale;
634 /* make the Y scale to UV scale ratio an exact multiply */
635 xscale = xscale_UV * uv_hscale;
636 yscale = yscale_UV * uv_vscale;
02e792fb 637 /*} else {
722506f0
CW		 638 xscale_UV = 0;
639 yscale_UV = 0;
640 }*/
02e792fb
DV		 641
642 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
643 scale_changed = true;
644 overlay->old_xscale = xscale;
645 overlay->old_yscale = yscale;
646
722506f0
CW		 647 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
648 ((xscale >> FP_SHIFT) << 16) |
649 ((xscale & FRACT_MASK) << 3));
650
651 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
652 ((xscale_UV >> FP_SHIFT) << 16) |
653 ((xscale_UV & FRACT_MASK) << 3));
654
655 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
656 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 657
658 if (scale_changed)
659 update_polyphase_filter(regs);
660
661 return scale_changed;
662}
663
664static void update_colorkey(struct intel_overlay *overlay,
665 struct overlay_registers *regs)
666{
667 u32 key = overlay->color_key;
6ba3ddd9 668
02e792fb 669 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 670 case 8:
671 regs->DCLRKV = 0;
672 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 673 break;
674
722506f0
CW		 675 case 16:
676 if (overlay->crtc->base.fb->depth == 15) {
677 regs->DCLRKV = RGB15_TO_COLORKEY(key);
678 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
679 } else {
680 regs->DCLRKV = RGB16_TO_COLORKEY(key);
681 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
682 }
6ba3ddd9
CW		 683 break;
684
722506f0
CW		 685 case 24:
686 case 32:
687 regs->DCLRKV = key;
688 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 689 break;
02e792fb
DV		 690 }
691}
692
693static u32 overlay_cmd_reg(struct put_image_params *params)
694{
695 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
696
697 if (params->format & I915_OVERLAY_YUV_PLANAR) {
698 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 699 case I915_OVERLAY_YUV422:
700 cmd |= OCMD_YUV_422_PLANAR;
701 break;
702 case I915_OVERLAY_YUV420:
703 cmd |= OCMD_YUV_420_PLANAR;
704 break;
705 case I915_OVERLAY_YUV411:
706 case I915_OVERLAY_YUV410:
707 cmd |= OCMD_YUV_410_PLANAR;
708 break;
02e792fb
DV		 709 }
710 } else { /* YUV packed */
711 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 712 case I915_OVERLAY_YUV422:
713 cmd |= OCMD_YUV_422_PACKED;
714 break;
715 case I915_OVERLAY_YUV411:
716 cmd |= OCMD_YUV_411_PACKED;
717 break;
02e792fb
DV		 718 }
719
720 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 721 case I915_OVERLAY_NO_SWAP:
722 break;
723 case I915_OVERLAY_UV_SWAP:
724 cmd |= OCMD_UV_SWAP;
725 break;
726 case I915_OVERLAY_Y_SWAP:
727 cmd |= OCMD_Y_SWAP;
728 break;
729 case I915_OVERLAY_Y_AND_UV_SWAP:
730 cmd |= OCMD_Y_AND_UV_SWAP;
731 break;
02e792fb
DV		 732 }
733 }
734
735 return cmd;
736}
737
5fe82c5e
CW		 738static int intel_overlay_do_put_image(struct intel_overlay *overlay,
739 struct drm_gem_object *new_bo,
740 struct put_image_params *params)
02e792fb
DV		 741{
742 int ret, tmp_width;
743 struct overlay_registers *regs;
744 bool scale_changed = false;
23010e43 745 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 746 struct drm_device *dev = overlay->dev;
747
748 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
749 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
750 BUG_ON(!overlay);
751
02e792fb
DV		 752 ret = intel_overlay_release_old_vid(overlay);
753 if (ret != 0)
754 return ret;
755
756 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
757 if (ret != 0)
758 return ret;
759
760 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
761 if (ret != 0)
762 goto out_unpin;
763
764 if (!overlay->active) {
8d74f656 765 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 766 if (!regs) {
767 ret = -ENOMEM;
768 goto out_unpin;
769 }
770 regs->OCONFIG = OCONF_CC_OUT_8BIT;
771 if (IS_I965GM(overlay->dev))
772 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
773 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
774 OCONF_PIPE_A : OCONF_PIPE_B;
9bb2ff73 775 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 776
777 ret = intel_overlay_on(overlay);
778 if (ret != 0)
779 goto out_unpin;
780 }
781
8d74f656 782 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 783 if (!regs) {
784 ret = -ENOMEM;
785 goto out_unpin;
786 }
787
788 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
789 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
790
791 if (params->format & I915_OVERLAY_YUV_PACKED)
792 tmp_width = packed_width_bytes(params->format, params->src_w);
793 else
794 tmp_width = params->src_w;
795
796 regs->SWIDTH = params->src_w;
797 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 798 params->offset_Y, tmp_width);
02e792fb
DV		 799 regs->SHEIGHT = params->src_h;
800 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
801 regs->OSTRIDE = params->stride_Y;
802
803 if (params->format & I915_OVERLAY_YUV_PLANAR) {
804 int uv_hscale = uv_hsubsampling(params->format);
805 int uv_vscale = uv_vsubsampling(params->format);
806 u32 tmp_U, tmp_V;
807 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
808 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 809 params->src_w/uv_hscale);
02e792fb 810 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 811 params->src_w/uv_hscale);
02e792fb
DV		 812 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
813 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
814 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
815 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
816 regs->OSTRIDE |= params->stride_UV << 16;
817 }
818
819 scale_changed = update_scaling_factors(overlay, regs, params);
820
821 update_colorkey(overlay, regs);
822
823 regs->OCMD = overlay_cmd_reg(params);
824
9bb2ff73 825 intel_overlay_unmap_regs(overlay, regs);
02e792fb 826
8dc5d147
CW		 827 ret = intel_overlay_continue(overlay, scale_changed);
828 if (ret)
829 goto out_unpin;
02e792fb
DV		 830
831 overlay->old_vid_bo = overlay->vid_bo;
23010e43 832 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 833
834 return 0;
835
836out_unpin:
837 i915_gem_object_unpin(new_bo);
838 return ret;
839}
840
5dcdbcb0
CW		 841int intel_overlay_switch_off(struct intel_overlay *overlay,
842 bool interruptible)
02e792fb 843{
02e792fb 844 struct overlay_registers *regs;
02e792fb 845 struct drm_device *dev = overlay->dev;
5dcdbcb0 846 int ret;
02e792fb
DV		 847
848 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
849 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
850
b303cf95
CW		 851 ret = intel_overlay_recover_from_interrupt(overlay, interruptible);
852 if (ret != 0)
853 return ret;
9bedb974 854
02e792fb
DV		 855 if (!overlay->active)
856 return 0;
857
02e792fb
DV		 858 ret = intel_overlay_release_old_vid(overlay);
859 if (ret != 0)
860 return ret;
861
8d74f656 862 regs = intel_overlay_map_regs(overlay);
02e792fb 863 regs->OCMD = 0;
9bb2ff73 864 intel_overlay_unmap_regs(overlay, regs);
02e792fb 865
5dcdbcb0 866 ret = intel_overlay_off(overlay, interruptible);
03f77ea5
DV		 867 if (ret != 0)
868 return ret;
869
12ca45fe 870 intel_overlay_off_tail(overlay);
02e792fb
DV		 871 return 0;
872}
873
874static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
875 struct intel_crtc *crtc)
876{
722506f0 877 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb 878 u32 pipeconf;
02e792fb
DV		 879
880 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
881 return -EINVAL;
882
5eddb70b 883 pipeconf = I915_READ(PIPECONF(crtc->pipe));
02e792fb
DV		 884
885 /* can't use the overlay with double wide pipe */
5eddb70b 886 if (!IS_I965G(overlay->dev) && pipeconf & PIPECONF_DOUBLE_WIDE)
02e792fb
DV		 887 return -EINVAL;
888
889 return 0;
890}
891
892static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
893{
894 struct drm_device *dev = overlay->dev;
722506f0 895 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 896 u32 pfit_control = I915_READ(PFIT_CONTROL);
446d2183 897 u32 ratio;
02e792fb
DV		 898
899 /* XXX: This is not the same logic as in the xorg driver, but more in
446d2183
CW		 900 * line with the intel documentation for the i965
901 */
902 if (!IS_I965G(dev)) {
903 if (pfit_control & VERT_AUTO_SCALE)
904 ratio = I915_READ(PFIT_AUTO_RATIOS);
02e792fb 905 else
446d2183
CW		 906 ratio = I915_READ(PFIT_PGM_RATIOS);
907 ratio >>= PFIT_VERT_SCALE_SHIFT;
908 } else { /* on i965 use the PGM reg to read out the autoscaler values */
909 ratio = I915_READ(PFIT_PGM_RATIOS) >> PFIT_VERT_SCALE_SHIFT_965;
02e792fb
DV		 910 }
911
912 overlay->pfit_vscale_ratio = ratio;
913}
914
915static int check_overlay_dst(struct intel_overlay *overlay,
916 struct drm_intel_overlay_put_image *rec)
917{
918 struct drm_display_mode *mode = &overlay->crtc->base.mode;
919
722506f0
CW		 920 if (rec->dst_x < mode->crtc_hdisplay &&
921 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
922 rec->dst_y < mode->crtc_vdisplay &&
923 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 924 return 0;
925 else
926 return -EINVAL;
927}
928
929static int check_overlay_scaling(struct put_image_params *rec)
930{
931 u32 tmp;
932
933 /* downscaling limit is 8.0 */
934 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
935 if (tmp > 7)
936 return -EINVAL;
937 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
938 if (tmp > 7)
939 return -EINVAL;
940
941 return 0;
942}
943
944static int check_overlay_src(struct drm_device *dev,
945 struct drm_intel_overlay_put_image *rec,
946 struct drm_gem_object *new_bo)
947{
02e792fb
DV		 948 int uv_hscale = uv_hsubsampling(rec->flags);
949 int uv_vscale = uv_vsubsampling(rec->flags);
9f7c3f44 950 u32 stride_mask, depth, tmp;
02e792fb
DV		 951
952 /* check src dimensions */
953 if (IS_845G(dev) || IS_I830(dev)) {
722506f0 954 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
9f7c3f44 955 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 956 return -EINVAL;
957 } else {
722506f0 958 if (rec->src_height > IMAGE_MAX_HEIGHT ||
9f7c3f44 959 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 960 return -EINVAL;
961 }
9f7c3f44 962
02e792fb 963 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0 964 if (rec->src_height < N_VERT_Y_TAPS*4 ||
9f7c3f44 965 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 966 return -EINVAL;
967
a1efd14a 968 /* check alignment constraints */
02e792fb 969 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 970 case I915_OVERLAY_RGB:
971 /* not implemented */
972 return -EINVAL;
9f7c3f44 973
722506f0 974 case I915_OVERLAY_YUV_PACKED:
722506f0 975 if (uv_vscale != 1)
02e792fb 976 return -EINVAL;
9f7c3f44
CW		 977
978 depth = packed_depth_bytes(rec->flags);
722506f0
CW		 979 if (depth < 0)
980 return depth;
9f7c3f44 981
722506f0
CW		 982 /* ignore UV planes */
983 rec->stride_UV = 0;
984 rec->offset_U = 0;
985 rec->offset_V = 0;
986 /* check pixel alignment */
987 if (rec->offset_Y % depth)
988 return -EINVAL;
989 break;
9f7c3f44 990
722506f0
CW		 991 case I915_OVERLAY_YUV_PLANAR:
992 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 993 return -EINVAL;
722506f0
CW		 994 /* no offset restrictions for planar formats */
995 break;
9f7c3f44 996
722506f0
CW		 997 default:
998 return -EINVAL;
02e792fb
DV		 999 }
1000
1001 if (rec->src_width % uv_hscale)
1002 return -EINVAL;
1003
1004 /* stride checking */
a1efd14a
CW		 1005 if (IS_I830(dev) || IS_845G(dev))
1006 stride_mask = 255;
1007 else
1008 stride_mask = 63;
02e792fb
DV		 1009
1010 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1011 return -EINVAL;
1012 if (IS_I965G(dev) && rec->stride_Y < 512)
1013 return -EINVAL;
1014
1015 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
9f7c3f44
CW		 1016 4096 : 8192;
1017 if (rec->stride_Y > tmp || rec->stride_UV > 2*1024)
02e792fb
DV		 1018 return -EINVAL;
1019
1020 /* check buffer dimensions */
1021 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1022 case I915_OVERLAY_RGB:
1023 case I915_OVERLAY_YUV_PACKED:
1024 /* always 4 Y values per depth pixels */
1025 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1026 return -EINVAL;
1027
1028 tmp = rec->stride_Y*rec->src_height;
1029 if (rec->offset_Y + tmp > new_bo->size)
1030 return -EINVAL;
1031 break;
1032
1033 case I915_OVERLAY_YUV_PLANAR:
1034 if (rec->src_width > rec->stride_Y)
1035 return -EINVAL;
1036 if (rec->src_width/uv_hscale > rec->stride_UV)
1037 return -EINVAL;
1038
9f7c3f44 1039 tmp = rec->stride_Y * rec->src_height;
722506f0
CW		 1040 if (rec->offset_Y + tmp > new_bo->size)
1041 return -EINVAL;
9f7c3f44
CW		 1042
1043 tmp = rec->stride_UV * (rec->src_height / uv_vscale);
722506f0
CW		 1044 if (rec->offset_U + tmp > new_bo->size ||
1045 rec->offset_V + tmp > new_bo->size)
1046 return -EINVAL;
1047 break;
02e792fb
DV		 1048 }
1049
1050 return 0;
1051}
1052
e9e331a8
CW		 1053/**
1054 * Return the pipe currently connected to the panel fitter,
1055 * or -1 if the panel fitter is not present or not in use
1056 */
1057static int intel_panel_fitter_pipe(struct drm_device *dev)
1058{
1059 struct drm_i915_private *dev_priv = dev->dev_private;
1060 u32 pfit_control;
1061
1062 /* i830 doesn't have a panel fitter */
1063 if (IS_I830(dev))
1064 return -1;
1065
1066 pfit_control = I915_READ(PFIT_CONTROL);
1067
1068 /* See if the panel fitter is in use */
1069 if ((pfit_control & PFIT_ENABLE) == 0)
1070 return -1;
1071
1072 /* 965 can place panel fitter on either pipe */
1073 if (IS_I965G(dev))
1074 return (pfit_control >> 29) & 0x3;
1075
1076 /* older chips can only use pipe 1 */
1077 return 1;
1078}
1079
02e792fb
DV		 1080int intel_overlay_put_image(struct drm_device *dev, void *data,
1081 struct drm_file *file_priv)
1082{
1083 struct drm_intel_overlay_put_image *put_image_rec = data;
1084 drm_i915_private_t *dev_priv = dev->dev_private;
1085 struct intel_overlay *overlay;
1086 struct drm_mode_object *drmmode_obj;
1087 struct intel_crtc *crtc;
1088 struct drm_gem_object *new_bo;
1089 struct put_image_params *params;
1090 int ret;
1091
1092 if (!dev_priv) {
1093 DRM_ERROR("called with no initialization\n");
1094 return -EINVAL;
1095 }
1096
1097 overlay = dev_priv->overlay;
1098 if (!overlay) {
1099 DRM_DEBUG("userspace bug: no overlay\n");
1100 return -ENODEV;
1101 }
1102
1103 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1104 mutex_lock(&dev->mode_config.mutex);
1105 mutex_lock(&dev->struct_mutex);
1106
5dcdbcb0 1107 ret = intel_overlay_switch_off(overlay, true);
02e792fb
DV		 1108
1109 mutex_unlock(&dev->struct_mutex);
1110 mutex_unlock(&dev->mode_config.mutex);
1111
1112 return ret;
1113 }
1114
1115 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1116 if (!params)
1117 return -ENOMEM;
1118
1119 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1120 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1121 if (!drmmode_obj) {
1122 ret = -ENOENT;
1123 goto out_free;
1124 }
02e792fb
DV		 1125 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1126
1127 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1128 put_image_rec->bo_handle);
915a428e
DC		 1129 if (!new_bo) {
1130 ret = -ENOENT;
1131 goto out_free;
1132 }
02e792fb
DV		 1133
1134 mutex_lock(&dev->mode_config.mutex);
1135 mutex_lock(&dev->struct_mutex);
1136
b303cf95
CW		 1137 ret = intel_overlay_recover_from_interrupt(overlay, true);
1138 if (ret != 0)
1139 goto out_unlock;
03f77ea5 1140
02e792fb
DV		 1141 if (overlay->crtc != crtc) {
1142 struct drm_display_mode *mode = &crtc->base.mode;
5dcdbcb0 1143 ret = intel_overlay_switch_off(overlay, true);
02e792fb
DV		 1144 if (ret != 0)
1145 goto out_unlock;
1146
1147 ret = check_overlay_possible_on_crtc(overlay, crtc);
1148 if (ret != 0)
1149 goto out_unlock;
1150
1151 overlay->crtc = crtc;
1152 crtc->overlay = overlay;
1153
e9e331a8
CW		 1154 /* line too wide, i.e. one-line-mode */
1155 if (mode->hdisplay > 1024 &&
1156 intel_panel_fitter_pipe(dev) == crtc->pipe) {
02e792fb
DV		 1157 overlay->pfit_active = 1;
1158 update_pfit_vscale_ratio(overlay);
1159 } else
1160 overlay->pfit_active = 0;
1161 }
1162
1163 ret = check_overlay_dst(overlay, put_image_rec);
1164 if (ret != 0)
1165 goto out_unlock;
1166
1167 if (overlay->pfit_active) {
1168 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1169 overlay->pfit_vscale_ratio);
02e792fb
DV		 1170 /* shifting right rounds downwards, so add 1 */
1171 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1172 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1173 } else {
1174 params->dst_y = put_image_rec->dst_y;
1175 params->dst_h = put_image_rec->dst_height;
1176 }
1177 params->dst_x = put_image_rec->dst_x;
1178 params->dst_w = put_image_rec->dst_width;
1179
1180 params->src_w = put_image_rec->src_width;
1181 params->src_h = put_image_rec->src_height;
1182 params->src_scan_w = put_image_rec->src_scan_width;
1183 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1184 if (params->src_scan_h > params->src_h ||
1185 params->src_scan_w > params->src_w) {
02e792fb
DV		 1186 ret = -EINVAL;
1187 goto out_unlock;
1188 }
1189
1190 ret = check_overlay_src(dev, put_image_rec, new_bo);
1191 if (ret != 0)
1192 goto out_unlock;
1193 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1194 params->stride_Y = put_image_rec->stride_Y;
1195 params->stride_UV = put_image_rec->stride_UV;
1196 params->offset_Y = put_image_rec->offset_Y;
1197 params->offset_U = put_image_rec->offset_U;
1198 params->offset_V = put_image_rec->offset_V;
1199
1200 /* Check scaling after src size to prevent a divide-by-zero. */
1201 ret = check_overlay_scaling(params);
1202 if (ret != 0)
1203 goto out_unlock;
1204
1205 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1206 if (ret != 0)
1207 goto out_unlock;
1208
1209 mutex_unlock(&dev->struct_mutex);
1210 mutex_unlock(&dev->mode_config.mutex);
1211
1212 kfree(params);
1213
1214 return 0;
1215
1216out_unlock:
1217 mutex_unlock(&dev->struct_mutex);
1218 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1219 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1220out_free:
02e792fb
DV		 1221 kfree(params);
1222
1223 return ret;
1224}
1225
1226static void update_reg_attrs(struct intel_overlay *overlay,
1227 struct overlay_registers *regs)
1228{
1229 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1230 regs->OCLRC1 = overlay->saturation;
1231}
1232
1233static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1234{
1235 int i;
1236
1237 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1238 return false;
1239
1240 for (i = 0; i < 3; i++) {
722506f0 1241 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1242 return false;
1243 }
1244
1245 return true;
1246}
1247
1248static bool check_gamma5_errata(u32 gamma5)
1249{
1250 int i;
1251
1252 for (i = 0; i < 3; i++) {
1253 if (((gamma5 >> i*8) & 0xff) == 0x80)
1254 return false;
1255 }
1256
1257 return true;
1258}
1259
1260static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1261{
722506f0
CW		 1262 if (!check_gamma_bounds(0, attrs->gamma0) ||
1263 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1264 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1265 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1266 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1267 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1268 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1269 return -EINVAL;
722506f0 1270
02e792fb
DV		 1271 if (!check_gamma5_errata(attrs->gamma5))
1272 return -EINVAL;
722506f0 1273
02e792fb
DV		 1274 return 0;
1275}
1276
1277int intel_overlay_attrs(struct drm_device *dev, void *data,
1278 struct drm_file *file_priv)
1279{
1280 struct drm_intel_overlay_attrs *attrs = data;
1281 drm_i915_private_t *dev_priv = dev->dev_private;
1282 struct intel_overlay *overlay;
1283 struct overlay_registers *regs;
1284 int ret;
1285
1286 if (!dev_priv) {
1287 DRM_ERROR("called with no initialization\n");
1288 return -EINVAL;
1289 }
1290
1291 overlay = dev_priv->overlay;
1292 if (!overlay) {
1293 DRM_DEBUG("userspace bug: no overlay\n");
1294 return -ENODEV;
1295 }
1296
1297 mutex_lock(&dev->mode_config.mutex);
1298 mutex_lock(&dev->struct_mutex);
1299
60fc332c 1300 ret = -EINVAL;
02e792fb 1301 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
60fc332c 1302 attrs->color_key = overlay->color_key;
02e792fb 1303 attrs->brightness = overlay->brightness;
60fc332c 1304 attrs->contrast = overlay->contrast;
02e792fb
DV		 1305 attrs->saturation = overlay->saturation;
1306
1307 if (IS_I9XX(dev)) {
1308 attrs->gamma0 = I915_READ(OGAMC0);
1309 attrs->gamma1 = I915_READ(OGAMC1);
1310 attrs->gamma2 = I915_READ(OGAMC2);
1311 attrs->gamma3 = I915_READ(OGAMC3);
1312 attrs->gamma4 = I915_READ(OGAMC4);
1313 attrs->gamma5 = I915_READ(OGAMC5);
1314 }
02e792fb 1315 } else {
60fc332c 1316 if (attrs->brightness < -128 || attrs->brightness > 127)
02e792fb 1317 goto out_unlock;
60fc332c 1318 if (attrs->contrast > 255)
02e792fb 1319 goto out_unlock;
60fc332c 1320 if (attrs->saturation > 1023)
02e792fb 1321 goto out_unlock;
60fc332c
CW		 1322
1323 overlay->color_key = attrs->color_key;
1324 overlay->brightness = attrs->brightness;
1325 overlay->contrast = attrs->contrast;
1326 overlay->saturation = attrs->saturation;
02e792fb 1327
8d74f656 1328 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1329 if (!regs) {
1330 ret = -ENOMEM;
1331 goto out_unlock;
1332 }
1333
1334 update_reg_attrs(overlay, regs);
1335
9bb2ff73 1336 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1337
1338 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
60fc332c 1339 if (!IS_I9XX(dev))
02e792fb 1340 goto out_unlock;
02e792fb
DV		 1341
1342 if (overlay->active) {
1343 ret = -EBUSY;
1344 goto out_unlock;
1345 }
1346
1347 ret = check_gamma(attrs);
60fc332c 1348 if (ret)
02e792fb
DV		 1349 goto out_unlock;
1350
1351 I915_WRITE(OGAMC0, attrs->gamma0);
1352 I915_WRITE(OGAMC1, attrs->gamma1);
1353 I915_WRITE(OGAMC2, attrs->gamma2);
1354 I915_WRITE(OGAMC3, attrs->gamma3);
1355 I915_WRITE(OGAMC4, attrs->gamma4);
1356 I915_WRITE(OGAMC5, attrs->gamma5);
1357 }
02e792fb
DV		 1358 }
1359
60fc332c 1360 ret = 0;
02e792fb
DV		 1361out_unlock:
1362 mutex_unlock(&dev->struct_mutex);
1363 mutex_unlock(&dev->mode_config.mutex);
1364
1365 return ret;
1366}
1367
1368void intel_setup_overlay(struct drm_device *dev)
1369{
1370 drm_i915_private_t *dev_priv = dev->dev_private;
1371 struct intel_overlay *overlay;
1372 struct drm_gem_object *reg_bo;
1373 struct overlay_registers *regs;
1374 int ret;
1375
31578148 1376 if (!HAS_OVERLAY(dev))
02e792fb
DV		 1377 return;
1378
1379 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1380 if (!overlay)
1381 return;
1382 overlay->dev = dev;
1383
ac52bc56 1384 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1385 if (!reg_bo)
1386 goto out_free;
23010e43 1387 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb 1388
31578148
CW		 1389 if (OVERLAY_NEEDS_PHYSICAL(dev)) {
1390 ret = i915_gem_attach_phys_object(dev, reg_bo,
1391 I915_GEM_PHYS_OVERLAY_REGS,
a2930128 1392 PAGE_SIZE);
31578148
CW		 1393 if (ret) {
1394 DRM_ERROR("failed to attach phys overlay regs\n");
1395 goto out_free_bo;
1396 }
1397 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1398 } else {
02e792fb
DV		 1399 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1400 if (ret) {
1401 DRM_ERROR("failed to pin overlay register bo\n");
1402 goto out_free_bo;
1403 }
1404 overlay->flip_addr = overlay->reg_bo->gtt_offset;
0ddc1289
CW		 1405
1406 ret = i915_gem_object_set_to_gtt_domain(reg_bo, true);
1407 if (ret) {
1408 DRM_ERROR("failed to move overlay register bo into the GTT\n");
1409 goto out_unpin_bo;
1410 }
02e792fb
DV		 1411 }
1412
1413 /* init all values */
1414 overlay->color_key = 0x0101fe;
1415 overlay->brightness = -19;
1416 overlay->contrast = 75;
1417 overlay->saturation = 146;
1418
8d74f656 1419 regs = intel_overlay_map_regs(overlay);
02e792fb
DV		 1420 if (!regs)
1421 goto out_free_bo;
1422
1423 memset(regs, 0, sizeof(struct overlay_registers));
1424 update_polyphase_filter(regs);
02e792fb
DV		 1425 update_reg_attrs(overlay, regs);
1426
9bb2ff73 1427 intel_overlay_unmap_regs(overlay, regs);
02e792fb
DV		 1428
1429 dev_priv->overlay = overlay;
1430 DRM_INFO("initialized overlay support\n");
1431 return;
1432
0ddc1289
CW		 1433out_unpin_bo:
1434 i915_gem_object_unpin(reg_bo);
02e792fb
DV		 1435out_free_bo:
1436 drm_gem_object_unreference(reg_bo);
1437out_free:
1438 kfree(overlay);
1439 return;
1440}
1441
1442void intel_cleanup_overlay(struct drm_device *dev)
1443{
722506f0 1444 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 1445
62cf4e6f
CW		 1446 if (!dev_priv->overlay)
1447 return;
02e792fb 1448
62cf4e6f
CW		 1449 /* The bo's should be free'd by the generic code already.
1450 * Furthermore modesetting teardown happens beforehand so the
1451 * hardware should be off already */
1452 BUG_ON(dev_priv->overlay->active);
1453
1454 drm_gem_object_unreference_unlocked(&dev_priv->overlay->reg_bo->base);
1455 kfree(dev_priv->overlay);
02e792fb 1456}
6ef3d427 1457
3bd3c932
CW		 1458#ifdef CONFIG_DEBUG_FS
1459#include <linux/seq_file.h>
1460
6ef3d427
CW		 1461struct intel_overlay_error_state {
1462 struct overlay_registers regs;
1463 unsigned long base;
1464 u32 dovsta;
1465 u32 isr;
1466};
1467
3bd3c932
CW		 1468static struct overlay_registers *
1469intel_overlay_map_regs_atomic(struct intel_overlay *overlay,
1470 int slot)
1471{
1472 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
1473 struct overlay_registers *regs;
1474
1475 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1476 regs = overlay->reg_bo->phys_obj->handle->vaddr;
1477 else
1478 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
1479 overlay->reg_bo->gtt_offset,
1480 slot);
1481
1482 return regs;
1483}
1484
1485static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay,
1486 int slot,
1487 struct overlay_registers *regs)
1488{
1489 if (!OVERLAY_NEEDS_PHYSICAL(overlay->dev))
1490 io_mapping_unmap_atomic(regs, slot);
1491}
1492
1493
6ef3d427
CW		 1494struct intel_overlay_error_state *
1495intel_overlay_capture_error_state(struct drm_device *dev)
1496{
1497 drm_i915_private_t *dev_priv = dev->dev_private;
1498 struct intel_overlay *overlay = dev_priv->overlay;
1499 struct intel_overlay_error_state *error;
1500 struct overlay_registers __iomem *regs;
1501
1502 if (!overlay || !overlay->active)
1503 return NULL;
1504
1505 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1506 if (error == NULL)
1507 return NULL;
1508
1509 error->dovsta = I915_READ(DOVSTA);
1510 error->isr = I915_READ(ISR);
31578148 1511 if (OVERLAY_NEEDS_PHYSICAL(overlay->dev))
6ef3d427 1512 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
31578148
CW		 1513 else
1514 error->base = (long) overlay->reg_bo->gtt_offset;
6ef3d427 1515
8d74f656 1516 regs = intel_overlay_map_regs_atomic(overlay, KM_IRQ0);
6ef3d427
CW		 1517 if (!regs)
1518 goto err;
1519
1520 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
9bb2ff73 1521 intel_overlay_unmap_regs_atomic(overlay, KM_IRQ0, regs);
6ef3d427
CW		 1522
1523 return error;
1524
1525err:
1526 kfree(error);
1527 return NULL;
1528}
1529
1530void
1531intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1532{
1533 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1534 error->dovsta, error->isr);
1535 seq_printf(m, " Register file at 0x%08lx:\n",
1536 error->base);
1537
1538#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1539 P(OBUF_0Y);
1540 P(OBUF_1Y);
1541 P(OBUF_0U);
1542 P(OBUF_0V);
1543 P(OBUF_1U);
1544 P(OBUF_1V);
1545 P(OSTRIDE);
1546 P(YRGB_VPH);
1547 P(UV_VPH);
1548 P(HORZ_PH);
1549 P(INIT_PHS);
1550 P(DWINPOS);
1551 P(DWINSZ);
1552 P(SWIDTH);
1553 P(SWIDTHSW);
1554 P(SHEIGHT);
1555 P(YRGBSCALE);
1556 P(UVSCALE);
1557 P(OCLRC0);
1558 P(OCLRC1);
1559 P(DCLRKV);
1560 P(DCLRKM);
1561 P(SCLRKVH);
1562 P(SCLRKVL);
1563 P(SCLRKEN);
1564 P(OCONFIG);
1565 P(OCMD);
1566 P(OSTART_0Y);
1567 P(OSTART_1Y);
1568 P(OSTART_0U);
1569 P(OSTART_0V);
1570 P(OSTART_1U);
1571 P(OSTART_1V);
1572 P(OTILEOFF_0Y);
1573 P(OTILEOFF_1Y);
1574 P(OTILEOFF_0U);
1575 P(OTILEOFF_0V);
1576 P(OTILEOFF_1U);
1577 P(OTILEOFF_1V);
1578 P(FASTHSCALE);
1579 P(UVSCALEV);
1580#undef P
1581}
3bd3c932 1582#endif
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