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drm/i915/overlay: Missing breaks between case statements for color depth
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_overlay.c
CommitLineData
02e792fb
DV		 1/*
2 * Copyright © 2009
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Daniel Vetter <daniel@ffwll.ch>
25 *
26 * Derived from Xorg ddx, xf86-video-intel, src/i830_video.c
27 */
e167976e
AM		 28
29#include <linux/seq_file.h>
02e792fb
DV		 30#include "drmP.h"
31#include "drm.h"
32#include "i915_drm.h"
33#include "i915_drv.h"
34#include "i915_reg.h"
35#include "intel_drv.h"
36
37/* Limits for overlay size. According to intel doc, the real limits are:
38 * Y width: 4095, UV width (planar): 2047, Y height: 2047,
39 * UV width (planar): * 1023. But the xorg thinks 2048 for height and width. Use
40 * the mininum of both. */
41#define IMAGE_MAX_WIDTH 2048
42#define IMAGE_MAX_HEIGHT 2046 /* 2 * 1023 */
43/* on 830 and 845 these large limits result in the card hanging */
44#define IMAGE_MAX_WIDTH_LEGACY 1024
45#define IMAGE_MAX_HEIGHT_LEGACY 1088
46
47/* overlay register definitions */
48/* OCMD register */
49#define OCMD_TILED_SURFACE (0x1<<19)
50#define OCMD_MIRROR_MASK (0x3<<17)
51#define OCMD_MIRROR_MODE (0x3<<17)
52#define OCMD_MIRROR_HORIZONTAL (0x1<<17)
53#define OCMD_MIRROR_VERTICAL (0x2<<17)
54#define OCMD_MIRROR_BOTH (0x3<<17)
55#define OCMD_BYTEORDER_MASK (0x3<<14) /* zero for YUYV or FOURCC YUY2 */
56#define OCMD_UV_SWAP (0x1<<14) /* YVYU */
57#define OCMD_Y_SWAP (0x2<<14) /* UYVY or FOURCC UYVY */
58#define OCMD_Y_AND_UV_SWAP (0x3<<14) /* VYUY */
59#define OCMD_SOURCE_FORMAT_MASK (0xf<<10)
60#define OCMD_RGB_888 (0x1<<10) /* not in i965 Intel docs */
61#define OCMD_RGB_555 (0x2<<10) /* not in i965 Intel docs */
62#define OCMD_RGB_565 (0x3<<10) /* not in i965 Intel docs */
63#define OCMD_YUV_422_PACKED (0x8<<10)
64#define OCMD_YUV_411_PACKED (0x9<<10) /* not in i965 Intel docs */
65#define OCMD_YUV_420_PLANAR (0xc<<10)
66#define OCMD_YUV_422_PLANAR (0xd<<10)
67#define OCMD_YUV_410_PLANAR (0xe<<10) /* also 411 */
68#define OCMD_TVSYNCFLIP_PARITY (0x1<<9)
69#define OCMD_TVSYNCFLIP_ENABLE (0x1<<7)
d7961364 70#define OCMD_BUF_TYPE_MASK (0x1<<5)
02e792fb
DV		 71#define OCMD_BUF_TYPE_FRAME (0x0<<5)
72#define OCMD_BUF_TYPE_FIELD (0x1<<5)
73#define OCMD_TEST_MODE (0x1<<4)
74#define OCMD_BUFFER_SELECT (0x3<<2)
75#define OCMD_BUFFER0 (0x0<<2)
76#define OCMD_BUFFER1 (0x1<<2)
77#define OCMD_FIELD_SELECT (0x1<<2)
78#define OCMD_FIELD0 (0x0<<1)
79#define OCMD_FIELD1 (0x1<<1)
80#define OCMD_ENABLE (0x1<<0)
81
82/* OCONFIG register */
83#define OCONF_PIPE_MASK (0x1<<18)
84#define OCONF_PIPE_A (0x0<<18)
85#define OCONF_PIPE_B (0x1<<18)
86#define OCONF_GAMMA2_ENABLE (0x1<<16)
87#define OCONF_CSC_MODE_BT601 (0x0<<5)
88#define OCONF_CSC_MODE_BT709 (0x1<<5)
89#define OCONF_CSC_BYPASS (0x1<<4)
90#define OCONF_CC_OUT_8BIT (0x1<<3)
91#define OCONF_TEST_MODE (0x1<<2)
92#define OCONF_THREE_LINE_BUFFER (0x1<<0)
93#define OCONF_TWO_LINE_BUFFER (0x0<<0)
94
95/* DCLRKM (dst-key) register */
96#define DST_KEY_ENABLE (0x1<<31)
97#define CLK_RGB24_MASK 0x0
98#define CLK_RGB16_MASK 0x070307
99#define CLK_RGB15_MASK 0x070707
100#define CLK_RGB8I_MASK 0xffffff
101
102#define RGB16_TO_COLORKEY(c) \
103 (((c & 0xF800) << 8) | ((c & 0x07E0) << 5) | ((c & 0x001F) << 3))
104#define RGB15_TO_COLORKEY(c) \
105 (((c & 0x7c00) << 9) | ((c & 0x03E0) << 6) | ((c & 0x001F) << 3))
106
107/* overlay flip addr flag */
108#define OFC_UPDATE 0x1
109
110/* polyphase filter coefficients */
111#define N_HORIZ_Y_TAPS 5
112#define N_VERT_Y_TAPS 3
113#define N_HORIZ_UV_TAPS 3
114#define N_VERT_UV_TAPS 3
115#define N_PHASES 17
116#define MAX_TAPS 5
117
118/* memory bufferd overlay registers */
119struct overlay_registers {
120 u32 OBUF_0Y;
121 u32 OBUF_1Y;
122 u32 OBUF_0U;
123 u32 OBUF_0V;
124 u32 OBUF_1U;
125 u32 OBUF_1V;
126 u32 OSTRIDE;
127 u32 YRGB_VPH;
128 u32 UV_VPH;
129 u32 HORZ_PH;
130 u32 INIT_PHS;
131 u32 DWINPOS;
132 u32 DWINSZ;
133 u32 SWIDTH;
134 u32 SWIDTHSW;
135 u32 SHEIGHT;
136 u32 YRGBSCALE;
137 u32 UVSCALE;
138 u32 OCLRC0;
139 u32 OCLRC1;
140 u32 DCLRKV;
141 u32 DCLRKM;
142 u32 SCLRKVH;
143 u32 SCLRKVL;
144 u32 SCLRKEN;
145 u32 OCONFIG;
146 u32 OCMD;
147 u32 RESERVED1; /* 0x6C */
148 u32 OSTART_0Y;
149 u32 OSTART_1Y;
150 u32 OSTART_0U;
151 u32 OSTART_0V;
152 u32 OSTART_1U;
153 u32 OSTART_1V;
154 u32 OTILEOFF_0Y;
155 u32 OTILEOFF_1Y;
156 u32 OTILEOFF_0U;
157 u32 OTILEOFF_0V;
158 u32 OTILEOFF_1U;
159 u32 OTILEOFF_1V;
160 u32 FASTHSCALE; /* 0xA0 */
161 u32 UVSCALEV; /* 0xA4 */
162 u32 RESERVEDC[(0x200 - 0xA8) / 4]; /* 0xA8 - 0x1FC */
163 u16 Y_VCOEFS[N_VERT_Y_TAPS * N_PHASES]; /* 0x200 */
164 u16 RESERVEDD[0x100 / 2 - N_VERT_Y_TAPS * N_PHASES];
165 u16 Y_HCOEFS[N_HORIZ_Y_TAPS * N_PHASES]; /* 0x300 */
166 u16 RESERVEDE[0x200 / 2 - N_HORIZ_Y_TAPS * N_PHASES];
167 u16 UV_VCOEFS[N_VERT_UV_TAPS * N_PHASES]; /* 0x500 */
168 u16 RESERVEDF[0x100 / 2 - N_VERT_UV_TAPS * N_PHASES];
169 u16 UV_HCOEFS[N_HORIZ_UV_TAPS * N_PHASES]; /* 0x600 */
170 u16 RESERVEDG[0x100 / 2 - N_HORIZ_UV_TAPS * N_PHASES];
171};
172
173/* overlay flip addr flag */
174#define OFC_UPDATE 0x1
175
176#define OVERLAY_NONPHYSICAL(dev) (IS_G33(dev) || IS_I965G(dev))
bad720ff 177#define OVERLAY_EXISTS(dev) (!IS_G4X(dev) && !IS_IRONLAKE(dev) && !IS_GEN6(dev))
02e792fb 178
02e792fb
DV		 179static struct overlay_registers *intel_overlay_map_regs_atomic(struct intel_overlay *overlay)
180{
181 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
182 struct overlay_registers *regs;
183
184 /* no recursive mappings */
185 BUG_ON(overlay->virt_addr);
186
187 if (OVERLAY_NONPHYSICAL(overlay->dev)) {
188 regs = io_mapping_map_atomic_wc(dev_priv->mm.gtt_mapping,
fca3ec01
CW		 189 overlay->reg_bo->gtt_offset,
190 KM_USER0);
02e792fb
DV		 191
192 if (!regs) {
193 DRM_ERROR("failed to map overlay regs in GTT\n");
194 return NULL;
195 }
196 } else
197 regs = overlay->reg_bo->phys_obj->handle->vaddr;
198
199 return overlay->virt_addr = regs;
200}
201
202static void intel_overlay_unmap_regs_atomic(struct intel_overlay *overlay)
203{
02e792fb 204 if (OVERLAY_NONPHYSICAL(overlay->dev))
fca3ec01 205 io_mapping_unmap_atomic(overlay->virt_addr, KM_USER0);
02e792fb
DV		 206
207 overlay->virt_addr = NULL;
208
02e792fb
DV		 209 return;
210}
211
212/* overlay needs to be disable in OCMD reg */
213static int intel_overlay_on(struct intel_overlay *overlay)
214{
215 struct drm_device *dev = overlay->dev;
02e792fb 216 int ret;
852835f3 217 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb
DV		 218
219 BUG_ON(overlay->active);
220
03f77ea5
DV		 221 overlay->active = 1;
222 overlay->hw_wedged = NEEDS_WAIT_FOR_FLIP;
223
4f8a567c 224 BEGIN_LP_RING(4);
02e792fb
DV		 225 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_ON);
226 OUT_RING(overlay->flip_addr | OFC_UPDATE);
227 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
228 OUT_RING(MI_NOOP);
229 ADVANCE_LP_RING();
230
852835f3 231 overlay->last_flip_req =
8a1a49f9 232 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 233 if (overlay->last_flip_req == 0)
234 return -ENOMEM;
02e792fb 235
852835f3 236 ret = i915_do_wait_request(dev,
722506f0
CW		 237 overlay->last_flip_req, true,
238 &dev_priv->render_ring);
03f77ea5
DV		 239 if (ret != 0)
240 return ret;
02e792fb 241
03f77ea5
DV		 242 overlay->hw_wedged = 0;
243 overlay->last_flip_req = 0;
02e792fb
DV		 244 return 0;
245}
246
247/* overlay needs to be enabled in OCMD reg */
248static void intel_overlay_continue(struct intel_overlay *overlay,
722506f0 249 bool load_polyphase_filter)
02e792fb
DV		 250{
251 struct drm_device *dev = overlay->dev;
252 drm_i915_private_t *dev_priv = dev->dev_private;
253 u32 flip_addr = overlay->flip_addr;
254 u32 tmp;
02e792fb
DV		 255
256 BUG_ON(!overlay->active);
257
258 if (load_polyphase_filter)
259 flip_addr |= OFC_UPDATE;
260
261 /* check for underruns */
262 tmp = I915_READ(DOVSTA);
263 if (tmp & (1 << 17))
264 DRM_DEBUG("overlay underrun, DOVSTA: %x\n", tmp);
265
4f8a567c 266 BEGIN_LP_RING(2);
02e792fb
DV		 267 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
268 OUT_RING(flip_addr);
5a5a0c64
DV		 269 ADVANCE_LP_RING();
270
852835f3 271 overlay->last_flip_req =
8a1a49f9 272 i915_add_request(dev, NULL, &dev_priv->render_ring);
5a5a0c64
DV		 273}
274
275static int intel_overlay_wait_flip(struct intel_overlay *overlay)
276{
277 struct drm_device *dev = overlay->dev;
722506f0 278 drm_i915_private_t *dev_priv = dev->dev_private;
5a5a0c64
DV		 279 int ret;
280 u32 tmp;
5a5a0c64
DV		 281
282 if (overlay->last_flip_req != 0) {
722506f0
CW		 283 ret = i915_do_wait_request(dev,
284 overlay->last_flip_req, true,
285 &dev_priv->render_ring);
5c5a4359
DV		 286 if (ret == 0) {
287 overlay->last_flip_req = 0;
5a5a0c64 288
5c5a4359 289 tmp = I915_READ(ISR);
5a5a0c64 290
5c5a4359
DV		 291 if (!(tmp & I915_OVERLAY_PLANE_FLIP_PENDING_INTERRUPT))
292 return 0;
293 }
5a5a0c64
DV		 294 }
295
296 /* synchronous slowpath */
03f77ea5
DV		 297 overlay->hw_wedged = RELEASE_OLD_VID;
298
5a5a0c64 299 BEGIN_LP_RING(2);
722506f0
CW		 300 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
301 OUT_RING(MI_NOOP);
302 ADVANCE_LP_RING();
02e792fb 303
852835f3 304 overlay->last_flip_req =
8a1a49f9 305 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 306 if (overlay->last_flip_req == 0)
307 return -ENOMEM;
02e792fb 308
722506f0
CW		 309 ret = i915_do_wait_request(dev,
310 overlay->last_flip_req, true,
311 &dev_priv->render_ring);
03f77ea5
DV		 312 if (ret != 0)
313 return ret;
314
315 overlay->hw_wedged = 0;
316 overlay->last_flip_req = 0;
317 return 0;
02e792fb
DV		 318}
319
320/* overlay needs to be disabled in OCMD reg */
321static int intel_overlay_off(struct intel_overlay *overlay)
322{
323 u32 flip_addr = overlay->flip_addr;
324 struct drm_device *dev = overlay->dev;
852835f3 325 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb 326 int ret;
02e792fb
DV		 327
328 BUG_ON(!overlay->active);
329
330 /* According to intel docs the overlay hw may hang (when switching
331 * off) without loading the filter coeffs. It is however unclear whether
332 * this applies to the disabling of the overlay or to the switching off
333 * of the hw. Do it in both cases */
334 flip_addr |= OFC_UPDATE;
335
336 /* wait for overlay to go idle */
03f77ea5
DV		 337 overlay->hw_wedged = SWITCH_OFF_STAGE_1;
338
4f8a567c 339 BEGIN_LP_RING(4);
02e792fb
DV		 340 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_CONTINUE);
341 OUT_RING(flip_addr);
722506f0
CW		 342 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
343 OUT_RING(MI_NOOP);
344 ADVANCE_LP_RING();
02e792fb 345
852835f3 346 overlay->last_flip_req =
8a1a49f9 347 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 348 if (overlay->last_flip_req == 0)
349 return -ENOMEM;
350
722506f0
CW		 351 ret = i915_do_wait_request(dev,
352 overlay->last_flip_req, true,
353 &dev_priv->render_ring);
03f77ea5 354 if (ret != 0)
02e792fb 355 return ret;
02e792fb
DV		 356
357 /* turn overlay off */
03f77ea5
DV		 358 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
359
4f8a567c 360 BEGIN_LP_RING(4);
722506f0 361 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
02e792fb 362 OUT_RING(flip_addr);
722506f0
CW		 363 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
364 OUT_RING(MI_NOOP);
02e792fb
DV		 365 ADVANCE_LP_RING();
366
852835f3 367 overlay->last_flip_req =
8a1a49f9 368 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 369 if (overlay->last_flip_req == 0)
370 return -ENOMEM;
371
722506f0
CW		 372 ret = i915_do_wait_request(dev,
373 overlay->last_flip_req, true,
374 &dev_priv->render_ring);
03f77ea5 375 if (ret != 0)
02e792fb 376 return ret;
02e792fb 377
03f77ea5
DV		 378 overlay->hw_wedged = 0;
379 overlay->last_flip_req = 0;
02e792fb
DV		 380 return ret;
381}
382
12ca45fe
DV		 383static void intel_overlay_off_tail(struct intel_overlay *overlay)
384{
385 struct drm_gem_object *obj;
386
387 /* never have the overlay hw on without showing a frame */
388 BUG_ON(!overlay->vid_bo);
a8089e84 389 obj = &overlay->vid_bo->base;
12ca45fe
DV		 390
391 i915_gem_object_unpin(obj);
392 drm_gem_object_unreference(obj);
393 overlay->vid_bo = NULL;
394
395 overlay->crtc->overlay = NULL;
396 overlay->crtc = NULL;
397 overlay->active = 0;
398}
399
03f77ea5
DV		 400/* recover from an interruption due to a signal
401 * We have to be careful not to repeat work forever an make forward progess. */
402int intel_overlay_recover_from_interrupt(struct intel_overlay *overlay,
722506f0 403 bool interruptible)
03f77ea5
DV		 404{
405 struct drm_device *dev = overlay->dev;
03f77ea5 406 struct drm_gem_object *obj;
852835f3 407 drm_i915_private_t *dev_priv = dev->dev_private;
03f77ea5
DV		 408 u32 flip_addr;
409 int ret;
03f77ea5
DV		 410
411 if (overlay->hw_wedged == HW_WEDGED)
412 return -EIO;
413
414 if (overlay->last_flip_req == 0) {
852835f3 415 overlay->last_flip_req =
8a1a49f9 416 i915_add_request(dev, NULL, &dev_priv->render_ring);
03f77ea5
DV		 417 if (overlay->last_flip_req == 0)
418 return -ENOMEM;
419 }
420
852835f3 421 ret = i915_do_wait_request(dev, overlay->last_flip_req,
722506f0 422 interruptible, &dev_priv->render_ring);
03f77ea5
DV		 423 if (ret != 0)
424 return ret;
425
426 switch (overlay->hw_wedged) {
722506f0
CW		 427 case RELEASE_OLD_VID:
428 obj = &overlay->old_vid_bo->base;
429 i915_gem_object_unpin(obj);
430 drm_gem_object_unreference(obj);
431 overlay->old_vid_bo = NULL;
432 break;
433 case SWITCH_OFF_STAGE_1:
434 flip_addr = overlay->flip_addr;
435 flip_addr |= OFC_UPDATE;
03f77ea5 436
722506f0
CW		 437 overlay->hw_wedged = SWITCH_OFF_STAGE_2;
438
439 BEGIN_LP_RING(4);
440 OUT_RING(MI_OVERLAY_FLIP | MI_OVERLAY_OFF);
441 OUT_RING(flip_addr);
442 OUT_RING(MI_WAIT_FOR_EVENT | MI_WAIT_FOR_OVERLAY_FLIP);
443 OUT_RING(MI_NOOP);
444 ADVANCE_LP_RING();
445
446 overlay->last_flip_req =
447 i915_add_request(dev, NULL,
448 &dev_priv->render_ring);
449 if (overlay->last_flip_req == 0)
450 return -ENOMEM;
451
452 ret = i915_do_wait_request(dev, overlay->last_flip_req,
453 interruptible,
454 &dev_priv->render_ring);
455 if (ret != 0)
456 return ret;
457
458 case SWITCH_OFF_STAGE_2:
459 intel_overlay_off_tail(overlay);
460 break;
461 default:
462 BUG_ON(overlay->hw_wedged != NEEDS_WAIT_FOR_FLIP);
03f77ea5
DV		 463 }
464
465 overlay->hw_wedged = 0;
466 overlay->last_flip_req = 0;
467 return 0;
468}
469
5a5a0c64
DV		 470/* Wait for pending overlay flip and release old frame.
471 * Needs to be called before the overlay register are changed
472 * via intel_overlay_(un)map_regs_atomic */
02e792fb
DV		 473static int intel_overlay_release_old_vid(struct intel_overlay *overlay)
474{
475 int ret;
476 struct drm_gem_object *obj;
477
03f77ea5
DV		 478 /* only wait if there is actually an old frame to release to
479 * guarantee forward progress */
480 if (!overlay->old_vid_bo)
481 return 0;
482
02e792fb
DV		 483 ret = intel_overlay_wait_flip(overlay);
484 if (ret != 0)
485 return ret;
486
a8089e84 487 obj = &overlay->old_vid_bo->base;
02e792fb
DV		 488 i915_gem_object_unpin(obj);
489 drm_gem_object_unreference(obj);
490 overlay->old_vid_bo = NULL;
491
492 return 0;
493}
494
495struct put_image_params {
496 int format;
497 short dst_x;
498 short dst_y;
499 short dst_w;
500 short dst_h;
501 short src_w;
502 short src_scan_h;
503 short src_scan_w;
504 short src_h;
505 short stride_Y;
506 short stride_UV;
507 int offset_Y;
508 int offset_U;
509 int offset_V;
510};
511
512static int packed_depth_bytes(u32 format)
513{
514 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 515 case I915_OVERLAY_YUV422:
516 return 4;
517 case I915_OVERLAY_YUV411:
518 /* return 6; not implemented */
519 default:
520 return -EINVAL;
02e792fb
DV		 521 }
522}
523
524static int packed_width_bytes(u32 format, short width)
525{
526 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 527 case I915_OVERLAY_YUV422:
528 return width << 1;
529 default:
530 return -EINVAL;
02e792fb
DV		 531 }
532}
533
534static int uv_hsubsampling(u32 format)
535{
536 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 537 case I915_OVERLAY_YUV422:
538 case I915_OVERLAY_YUV420:
539 return 2;
540 case I915_OVERLAY_YUV411:
541 case I915_OVERLAY_YUV410:
542 return 4;
543 default:
544 return -EINVAL;
02e792fb
DV		 545 }
546}
547
548static int uv_vsubsampling(u32 format)
549{
550 switch (format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 551 case I915_OVERLAY_YUV420:
552 case I915_OVERLAY_YUV410:
553 return 2;
554 case I915_OVERLAY_YUV422:
555 case I915_OVERLAY_YUV411:
556 return 1;
557 default:
558 return -EINVAL;
02e792fb
DV		 559 }
560}
561
562static u32 calc_swidthsw(struct drm_device *dev, u32 offset, u32 width)
563{
564 u32 mask, shift, ret;
565 if (IS_I9XX(dev)) {
566 mask = 0x3f;
567 shift = 6;
568 } else {
569 mask = 0x1f;
570 shift = 5;
571 }
572 ret = ((offset + width + mask) >> shift) - (offset >> shift);
573 if (IS_I9XX(dev))
574 ret <<= 1;
575 ret -=1;
576 return ret << 2;
577}
578
579static const u16 y_static_hcoeffs[N_HORIZ_Y_TAPS * N_PHASES] = {
580 0x3000, 0xb4a0, 0x1930, 0x1920, 0xb4a0,
581 0x3000, 0xb500, 0x19d0, 0x1880, 0xb440,
582 0x3000, 0xb540, 0x1a88, 0x2f80, 0xb3e0,
583 0x3000, 0xb580, 0x1b30, 0x2e20, 0xb380,
584 0x3000, 0xb5c0, 0x1bd8, 0x2cc0, 0xb320,
585 0x3020, 0xb5e0, 0x1c60, 0x2b80, 0xb2c0,
586 0x3020, 0xb5e0, 0x1cf8, 0x2a20, 0xb260,
587 0x3020, 0xb5e0, 0x1d80, 0x28e0, 0xb200,
588 0x3020, 0xb5c0, 0x1e08, 0x3f40, 0xb1c0,
589 0x3020, 0xb580, 0x1e78, 0x3ce0, 0xb160,
590 0x3040, 0xb520, 0x1ed8, 0x3aa0, 0xb120,
591 0x3040, 0xb4a0, 0x1f30, 0x3880, 0xb0e0,
592 0x3040, 0xb400, 0x1f78, 0x3680, 0xb0a0,
593 0x3020, 0xb340, 0x1fb8, 0x34a0, 0xb060,
594 0x3020, 0xb240, 0x1fe0, 0x32e0, 0xb040,
595 0x3020, 0xb140, 0x1ff8, 0x3160, 0xb020,
722506f0
CW		 596 0xb000, 0x3000, 0x0800, 0x3000, 0xb000
597};
598
02e792fb
DV		 599static const u16 uv_static_hcoeffs[N_HORIZ_UV_TAPS * N_PHASES] = {
600 0x3000, 0x1800, 0x1800, 0xb000, 0x18d0, 0x2e60,
601 0xb000, 0x1990, 0x2ce0, 0xb020, 0x1a68, 0x2b40,
602 0xb040, 0x1b20, 0x29e0, 0xb060, 0x1bd8, 0x2880,
603 0xb080, 0x1c88, 0x3e60, 0xb0a0, 0x1d28, 0x3c00,
604 0xb0c0, 0x1db8, 0x39e0, 0xb0e0, 0x1e40, 0x37e0,
605 0xb100, 0x1eb8, 0x3620, 0xb100, 0x1f18, 0x34a0,
606 0xb100, 0x1f68, 0x3360, 0xb0e0, 0x1fa8, 0x3240,
607 0xb0c0, 0x1fe0, 0x3140, 0xb060, 0x1ff0, 0x30a0,
722506f0
CW		 608 0x3000, 0x0800, 0x3000
609};
02e792fb
DV		 610
611static void update_polyphase_filter(struct overlay_registers *regs)
612{
613 memcpy(regs->Y_HCOEFS, y_static_hcoeffs, sizeof(y_static_hcoeffs));
614 memcpy(regs->UV_HCOEFS, uv_static_hcoeffs, sizeof(uv_static_hcoeffs));
615}
616
617static bool update_scaling_factors(struct intel_overlay *overlay,
618 struct overlay_registers *regs,
619 struct put_image_params *params)
620{
621 /* fixed point with a 12 bit shift */
622 u32 xscale, yscale, xscale_UV, yscale_UV;
623#define FP_SHIFT 12
624#define FRACT_MASK 0xfff
625 bool scale_changed = false;
626 int uv_hscale = uv_hsubsampling(params->format);
627 int uv_vscale = uv_vsubsampling(params->format);
628
629 if (params->dst_w > 1)
630 xscale = ((params->src_scan_w - 1) << FP_SHIFT)
631 /(params->dst_w);
632 else
633 xscale = 1 << FP_SHIFT;
634
635 if (params->dst_h > 1)
636 yscale = ((params->src_scan_h - 1) << FP_SHIFT)
637 /(params->dst_h);
638 else
639 yscale = 1 << FP_SHIFT;
640
641 /*if (params->format & I915_OVERLAY_YUV_PLANAR) {*/
722506f0
CW		 642 xscale_UV = xscale/uv_hscale;
643 yscale_UV = yscale/uv_vscale;
644 /* make the Y scale to UV scale ratio an exact multiply */
645 xscale = xscale_UV * uv_hscale;
646 yscale = yscale_UV * uv_vscale;
02e792fb 647 /*} else {
722506f0
CW		 648 xscale_UV = 0;
649 yscale_UV = 0;
650 }*/
02e792fb
DV		 651
652 if (xscale != overlay->old_xscale || yscale != overlay->old_yscale)
653 scale_changed = true;
654 overlay->old_xscale = xscale;
655 overlay->old_yscale = yscale;
656
722506f0
CW		 657 regs->YRGBSCALE = (((yscale & FRACT_MASK) << 20) |
658 ((xscale >> FP_SHIFT) << 16) |
659 ((xscale & FRACT_MASK) << 3));
660
661 regs->UVSCALE = (((yscale_UV & FRACT_MASK) << 20) |
662 ((xscale_UV >> FP_SHIFT) << 16) |
663 ((xscale_UV & FRACT_MASK) << 3));
664
665 regs->UVSCALEV = ((((yscale >> FP_SHIFT) << 16) |
666 ((yscale_UV >> FP_SHIFT) << 0)));
02e792fb
DV		 667
668 if (scale_changed)
669 update_polyphase_filter(regs);
670
671 return scale_changed;
672}
673
674static void update_colorkey(struct intel_overlay *overlay,
675 struct overlay_registers *regs)
676{
677 u32 key = overlay->color_key;
6ba3ddd9 678
02e792fb 679 switch (overlay->crtc->base.fb->bits_per_pixel) {
722506f0
CW		 680 case 8:
681 regs->DCLRKV = 0;
682 regs->DCLRKM = CLK_RGB8I_MASK | DST_KEY_ENABLE;
6ba3ddd9
CW		 683 break;
684
722506f0
CW		 685 case 16:
686 if (overlay->crtc->base.fb->depth == 15) {
687 regs->DCLRKV = RGB15_TO_COLORKEY(key);
688 regs->DCLRKM = CLK_RGB15_MASK | DST_KEY_ENABLE;
689 } else {
690 regs->DCLRKV = RGB16_TO_COLORKEY(key);
691 regs->DCLRKM = CLK_RGB16_MASK | DST_KEY_ENABLE;
692 }
6ba3ddd9
CW		 693 break;
694
722506f0
CW		 695 case 24:
696 case 32:
697 regs->DCLRKV = key;
698 regs->DCLRKM = CLK_RGB24_MASK | DST_KEY_ENABLE;
6ba3ddd9 699 break;
02e792fb
DV		 700 }
701}
702
703static u32 overlay_cmd_reg(struct put_image_params *params)
704{
705 u32 cmd = OCMD_ENABLE | OCMD_BUF_TYPE_FRAME | OCMD_BUFFER0;
706
707 if (params->format & I915_OVERLAY_YUV_PLANAR) {
708 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 709 case I915_OVERLAY_YUV422:
710 cmd |= OCMD_YUV_422_PLANAR;
711 break;
712 case I915_OVERLAY_YUV420:
713 cmd |= OCMD_YUV_420_PLANAR;
714 break;
715 case I915_OVERLAY_YUV411:
716 case I915_OVERLAY_YUV410:
717 cmd |= OCMD_YUV_410_PLANAR;
718 break;
02e792fb
DV		 719 }
720 } else { /* YUV packed */
721 switch (params->format & I915_OVERLAY_DEPTH_MASK) {
722506f0
CW		 722 case I915_OVERLAY_YUV422:
723 cmd |= OCMD_YUV_422_PACKED;
724 break;
725 case I915_OVERLAY_YUV411:
726 cmd |= OCMD_YUV_411_PACKED;
727 break;
02e792fb
DV		 728 }
729
730 switch (params->format & I915_OVERLAY_SWAP_MASK) {
722506f0
CW		 731 case I915_OVERLAY_NO_SWAP:
732 break;
733 case I915_OVERLAY_UV_SWAP:
734 cmd |= OCMD_UV_SWAP;
735 break;
736 case I915_OVERLAY_Y_SWAP:
737 cmd |= OCMD_Y_SWAP;
738 break;
739 case I915_OVERLAY_Y_AND_UV_SWAP:
740 cmd |= OCMD_Y_AND_UV_SWAP;
741 break;
02e792fb
DV		 742 }
743 }
744
745 return cmd;
746}
747
748int intel_overlay_do_put_image(struct intel_overlay *overlay,
749 struct drm_gem_object *new_bo,
750 struct put_image_params *params)
751{
752 int ret, tmp_width;
753 struct overlay_registers *regs;
754 bool scale_changed = false;
23010e43 755 struct drm_i915_gem_object *bo_priv = to_intel_bo(new_bo);
02e792fb
DV		 756 struct drm_device *dev = overlay->dev;
757
758 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
759 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
760 BUG_ON(!overlay);
761
02e792fb
DV		 762 ret = intel_overlay_release_old_vid(overlay);
763 if (ret != 0)
764 return ret;
765
766 ret = i915_gem_object_pin(new_bo, PAGE_SIZE);
767 if (ret != 0)
768 return ret;
769
770 ret = i915_gem_object_set_to_gtt_domain(new_bo, 0);
771 if (ret != 0)
772 goto out_unpin;
773
774 if (!overlay->active) {
775 regs = intel_overlay_map_regs_atomic(overlay);
776 if (!regs) {
777 ret = -ENOMEM;
778 goto out_unpin;
779 }
780 regs->OCONFIG = OCONF_CC_OUT_8BIT;
781 if (IS_I965GM(overlay->dev))
782 regs->OCONFIG |= OCONF_CSC_MODE_BT709;
783 regs->OCONFIG |= overlay->crtc->pipe == 0 ?
784 OCONF_PIPE_A : OCONF_PIPE_B;
785 intel_overlay_unmap_regs_atomic(overlay);
786
787 ret = intel_overlay_on(overlay);
788 if (ret != 0)
789 goto out_unpin;
790 }
791
792 regs = intel_overlay_map_regs_atomic(overlay);
793 if (!regs) {
794 ret = -ENOMEM;
795 goto out_unpin;
796 }
797
798 regs->DWINPOS = (params->dst_y << 16) | params->dst_x;
799 regs->DWINSZ = (params->dst_h << 16) | params->dst_w;
800
801 if (params->format & I915_OVERLAY_YUV_PACKED)
802 tmp_width = packed_width_bytes(params->format, params->src_w);
803 else
804 tmp_width = params->src_w;
805
806 regs->SWIDTH = params->src_w;
807 regs->SWIDTHSW = calc_swidthsw(overlay->dev,
722506f0 808 params->offset_Y, tmp_width);
02e792fb
DV		 809 regs->SHEIGHT = params->src_h;
810 regs->OBUF_0Y = bo_priv->gtt_offset + params-> offset_Y;
811 regs->OSTRIDE = params->stride_Y;
812
813 if (params->format & I915_OVERLAY_YUV_PLANAR) {
814 int uv_hscale = uv_hsubsampling(params->format);
815 int uv_vscale = uv_vsubsampling(params->format);
816 u32 tmp_U, tmp_V;
817 regs->SWIDTH |= (params->src_w/uv_hscale) << 16;
818 tmp_U = calc_swidthsw(overlay->dev, params->offset_U,
722506f0 819 params->src_w/uv_hscale);
02e792fb 820 tmp_V = calc_swidthsw(overlay->dev, params->offset_V,
722506f0 821 params->src_w/uv_hscale);
02e792fb
DV		 822 regs->SWIDTHSW |= max_t(u32, tmp_U, tmp_V) << 16;
823 regs->SHEIGHT |= (params->src_h/uv_vscale) << 16;
824 regs->OBUF_0U = bo_priv->gtt_offset + params->offset_U;
825 regs->OBUF_0V = bo_priv->gtt_offset + params->offset_V;
826 regs->OSTRIDE |= params->stride_UV << 16;
827 }
828
829 scale_changed = update_scaling_factors(overlay, regs, params);
830
831 update_colorkey(overlay, regs);
832
833 regs->OCMD = overlay_cmd_reg(params);
834
835 intel_overlay_unmap_regs_atomic(overlay);
836
837 intel_overlay_continue(overlay, scale_changed);
838
839 overlay->old_vid_bo = overlay->vid_bo;
23010e43 840 overlay->vid_bo = to_intel_bo(new_bo);
02e792fb
DV		 841
842 return 0;
843
844out_unpin:
845 i915_gem_object_unpin(new_bo);
846 return ret;
847}
848
849int intel_overlay_switch_off(struct intel_overlay *overlay)
850{
851 int ret;
852 struct overlay_registers *regs;
02e792fb
DV		 853 struct drm_device *dev = overlay->dev;
854
855 BUG_ON(!mutex_is_locked(&dev->struct_mutex));
856 BUG_ON(!mutex_is_locked(&dev->mode_config.mutex));
857
9bedb974
DV		 858 if (overlay->hw_wedged) {
859 ret = intel_overlay_recover_from_interrupt(overlay, 1);
860 if (ret != 0)
861 return ret;
862 }
863
02e792fb
DV		 864 if (!overlay->active)
865 return 0;
866
02e792fb
DV		 867 ret = intel_overlay_release_old_vid(overlay);
868 if (ret != 0)
869 return ret;
870
871 regs = intel_overlay_map_regs_atomic(overlay);
872 regs->OCMD = 0;
873 intel_overlay_unmap_regs_atomic(overlay);
874
875 ret = intel_overlay_off(overlay);
03f77ea5
DV		 876 if (ret != 0)
877 return ret;
878
12ca45fe 879 intel_overlay_off_tail(overlay);
02e792fb
DV		 880
881 return 0;
882}
883
884static int check_overlay_possible_on_crtc(struct intel_overlay *overlay,
885 struct intel_crtc *crtc)
886{
722506f0 887 drm_i915_private_t *dev_priv = overlay->dev->dev_private;
02e792fb
DV		 888 u32 pipeconf;
889 int pipeconf_reg = (crtc->pipe == 0) ? PIPEACONF : PIPEBCONF;
890
891 if (!crtc->base.enabled || crtc->dpms_mode != DRM_MODE_DPMS_ON)
892 return -EINVAL;
893
894 pipeconf = I915_READ(pipeconf_reg);
895
896 /* can't use the overlay with double wide pipe */
897 if (!IS_I965G(overlay->dev) && pipeconf & PIPEACONF_DOUBLE_WIDE)
898 return -EINVAL;
899
900 return 0;
901}
902
903static void update_pfit_vscale_ratio(struct intel_overlay *overlay)
904{
905 struct drm_device *dev = overlay->dev;
722506f0 906 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb
DV		 907 u32 ratio;
908 u32 pfit_control = I915_READ(PFIT_CONTROL);
909
910 /* XXX: This is not the same logic as in the xorg driver, but more in
911 * line with the intel documentation for the i965 */
912 if (!IS_I965G(dev) && (pfit_control & VERT_AUTO_SCALE)) {
913 ratio = I915_READ(PFIT_AUTO_RATIOS) >> PFIT_VERT_SCALE_SHIFT;
914 } else { /* on i965 use the PGM reg to read out the autoscaler values */
915 ratio = I915_READ(PFIT_PGM_RATIOS);
916 if (IS_I965G(dev))
917 ratio >>= PFIT_VERT_SCALE_SHIFT_965;
918 else
919 ratio >>= PFIT_VERT_SCALE_SHIFT;
920 }
921
922 overlay->pfit_vscale_ratio = ratio;
923}
924
925static int check_overlay_dst(struct intel_overlay *overlay,
926 struct drm_intel_overlay_put_image *rec)
927{
928 struct drm_display_mode *mode = &overlay->crtc->base.mode;
929
722506f0
CW		 930 if (rec->dst_x < mode->crtc_hdisplay &&
931 rec->dst_x + rec->dst_width <= mode->crtc_hdisplay &&
932 rec->dst_y < mode->crtc_vdisplay &&
933 rec->dst_y + rec->dst_height <= mode->crtc_vdisplay)
02e792fb
DV		 934 return 0;
935 else
936 return -EINVAL;
937}
938
939static int check_overlay_scaling(struct put_image_params *rec)
940{
941 u32 tmp;
942
943 /* downscaling limit is 8.0 */
944 tmp = ((rec->src_scan_h << 16) / rec->dst_h) >> 16;
945 if (tmp > 7)
946 return -EINVAL;
947 tmp = ((rec->src_scan_w << 16) / rec->dst_w) >> 16;
948 if (tmp > 7)
949 return -EINVAL;
950
951 return 0;
952}
953
954static int check_overlay_src(struct drm_device *dev,
955 struct drm_intel_overlay_put_image *rec,
956 struct drm_gem_object *new_bo)
957{
958 u32 stride_mask;
959 int depth;
960 int uv_hscale = uv_hsubsampling(rec->flags);
961 int uv_vscale = uv_vsubsampling(rec->flags);
962 size_t tmp;
963
964 /* check src dimensions */
965 if (IS_845G(dev) || IS_I830(dev)) {
722506f0
CW		 966 if (rec->src_height > IMAGE_MAX_HEIGHT_LEGACY ||
967 rec->src_width > IMAGE_MAX_WIDTH_LEGACY)
02e792fb
DV		 968 return -EINVAL;
969 } else {
722506f0
CW		 970 if (rec->src_height > IMAGE_MAX_HEIGHT ||
971 rec->src_width > IMAGE_MAX_WIDTH)
02e792fb
DV		 972 return -EINVAL;
973 }
974 /* better safe than sorry, use 4 as the maximal subsampling ratio */
722506f0
CW		 975 if (rec->src_height < N_VERT_Y_TAPS*4 ||
976 rec->src_width < N_HORIZ_Y_TAPS*4)
02e792fb
DV		 977 return -EINVAL;
978
a1efd14a 979 /* check alignment constraints */
02e792fb 980 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 981 case I915_OVERLAY_RGB:
982 /* not implemented */
983 return -EINVAL;
984 case I915_OVERLAY_YUV_PACKED:
985 depth = packed_depth_bytes(rec->flags);
986 if (uv_vscale != 1)
02e792fb 987 return -EINVAL;
722506f0
CW		 988 if (depth < 0)
989 return depth;
990 /* ignore UV planes */
991 rec->stride_UV = 0;
992 rec->offset_U = 0;
993 rec->offset_V = 0;
994 /* check pixel alignment */
995 if (rec->offset_Y % depth)
996 return -EINVAL;
997 break;
998 case I915_OVERLAY_YUV_PLANAR:
999 if (uv_vscale < 0 || uv_hscale < 0)
02e792fb 1000 return -EINVAL;
722506f0
CW		 1001 /* no offset restrictions for planar formats */
1002 break;
1003 default:
1004 return -EINVAL;
02e792fb
DV		 1005 }
1006
1007 if (rec->src_width % uv_hscale)
1008 return -EINVAL;
1009
1010 /* stride checking */
a1efd14a
CW		 1011 if (IS_I830(dev) || IS_845G(dev))
1012 stride_mask = 255;
1013 else
1014 stride_mask = 63;
02e792fb
DV		 1015
1016 if (rec->stride_Y & stride_mask || rec->stride_UV & stride_mask)
1017 return -EINVAL;
1018 if (IS_I965G(dev) && rec->stride_Y < 512)
1019 return -EINVAL;
1020
1021 tmp = (rec->flags & I915_OVERLAY_TYPE_MASK) == I915_OVERLAY_YUV_PLANAR ?
1022 4 : 8;
1023 if (rec->stride_Y > tmp*1024 || rec->stride_UV > 2*1024)
1024 return -EINVAL;
1025
1026 /* check buffer dimensions */
1027 switch (rec->flags & I915_OVERLAY_TYPE_MASK) {
722506f0
CW		 1028 case I915_OVERLAY_RGB:
1029 case I915_OVERLAY_YUV_PACKED:
1030 /* always 4 Y values per depth pixels */
1031 if (packed_width_bytes(rec->flags, rec->src_width) > rec->stride_Y)
1032 return -EINVAL;
1033
1034 tmp = rec->stride_Y*rec->src_height;
1035 if (rec->offset_Y + tmp > new_bo->size)
1036 return -EINVAL;
1037 break;
1038
1039 case I915_OVERLAY_YUV_PLANAR:
1040 if (rec->src_width > rec->stride_Y)
1041 return -EINVAL;
1042 if (rec->src_width/uv_hscale > rec->stride_UV)
1043 return -EINVAL;
1044
1045 tmp = rec->stride_Y*rec->src_height;
1046 if (rec->offset_Y + tmp > new_bo->size)
1047 return -EINVAL;
1048 tmp = rec->stride_UV*rec->src_height;
1049 tmp /= uv_vscale;
1050 if (rec->offset_U + tmp > new_bo->size ||
1051 rec->offset_V + tmp > new_bo->size)
1052 return -EINVAL;
1053 break;
02e792fb
DV		 1054 }
1055
1056 return 0;
1057}
1058
1059int intel_overlay_put_image(struct drm_device *dev, void *data,
1060 struct drm_file *file_priv)
1061{
1062 struct drm_intel_overlay_put_image *put_image_rec = data;
1063 drm_i915_private_t *dev_priv = dev->dev_private;
1064 struct intel_overlay *overlay;
1065 struct drm_mode_object *drmmode_obj;
1066 struct intel_crtc *crtc;
1067 struct drm_gem_object *new_bo;
1068 struct put_image_params *params;
1069 int ret;
1070
1071 if (!dev_priv) {
1072 DRM_ERROR("called with no initialization\n");
1073 return -EINVAL;
1074 }
1075
1076 overlay = dev_priv->overlay;
1077 if (!overlay) {
1078 DRM_DEBUG("userspace bug: no overlay\n");
1079 return -ENODEV;
1080 }
1081
1082 if (!(put_image_rec->flags & I915_OVERLAY_ENABLE)) {
1083 mutex_lock(&dev->mode_config.mutex);
1084 mutex_lock(&dev->struct_mutex);
1085
1086 ret = intel_overlay_switch_off(overlay);
1087
1088 mutex_unlock(&dev->struct_mutex);
1089 mutex_unlock(&dev->mode_config.mutex);
1090
1091 return ret;
1092 }
1093
1094 params = kmalloc(sizeof(struct put_image_params), GFP_KERNEL);
1095 if (!params)
1096 return -ENOMEM;
1097
1098 drmmode_obj = drm_mode_object_find(dev, put_image_rec->crtc_id,
722506f0 1099 DRM_MODE_OBJECT_CRTC);
915a428e
DC		 1100 if (!drmmode_obj) {
1101 ret = -ENOENT;
1102 goto out_free;
1103 }
02e792fb
DV		 1104 crtc = to_intel_crtc(obj_to_crtc(drmmode_obj));
1105
1106 new_bo = drm_gem_object_lookup(dev, file_priv,
722506f0 1107 put_image_rec->bo_handle);
915a428e
DC		 1108 if (!new_bo) {
1109 ret = -ENOENT;
1110 goto out_free;
1111 }
02e792fb
DV		 1112
1113 mutex_lock(&dev->mode_config.mutex);
1114 mutex_lock(&dev->struct_mutex);
1115
03f77ea5
DV		 1116 if (overlay->hw_wedged) {
1117 ret = intel_overlay_recover_from_interrupt(overlay, 1);
1118 if (ret != 0)
1119 goto out_unlock;
1120 }
1121
02e792fb
DV		 1122 if (overlay->crtc != crtc) {
1123 struct drm_display_mode *mode = &crtc->base.mode;
1124 ret = intel_overlay_switch_off(overlay);
1125 if (ret != 0)
1126 goto out_unlock;
1127
1128 ret = check_overlay_possible_on_crtc(overlay, crtc);
1129 if (ret != 0)
1130 goto out_unlock;
1131
1132 overlay->crtc = crtc;
1133 crtc->overlay = overlay;
1134
1135 if (intel_panel_fitter_pipe(dev) == crtc->pipe
1136 /* and line to wide, i.e. one-line-mode */
1137 && mode->hdisplay > 1024) {
1138 overlay->pfit_active = 1;
1139 update_pfit_vscale_ratio(overlay);
1140 } else
1141 overlay->pfit_active = 0;
1142 }
1143
1144 ret = check_overlay_dst(overlay, put_image_rec);
1145 if (ret != 0)
1146 goto out_unlock;
1147
1148 if (overlay->pfit_active) {
1149 params->dst_y = ((((u32)put_image_rec->dst_y) << 12) /
722506f0 1150 overlay->pfit_vscale_ratio);
02e792fb
DV		 1151 /* shifting right rounds downwards, so add 1 */
1152 params->dst_h = ((((u32)put_image_rec->dst_height) << 12) /
722506f0 1153 overlay->pfit_vscale_ratio) + 1;
02e792fb
DV		 1154 } else {
1155 params->dst_y = put_image_rec->dst_y;
1156 params->dst_h = put_image_rec->dst_height;
1157 }
1158 params->dst_x = put_image_rec->dst_x;
1159 params->dst_w = put_image_rec->dst_width;
1160
1161 params->src_w = put_image_rec->src_width;
1162 params->src_h = put_image_rec->src_height;
1163 params->src_scan_w = put_image_rec->src_scan_width;
1164 params->src_scan_h = put_image_rec->src_scan_height;
722506f0
CW		 1165 if (params->src_scan_h > params->src_h ||
1166 params->src_scan_w > params->src_w) {
02e792fb
DV		 1167 ret = -EINVAL;
1168 goto out_unlock;
1169 }
1170
1171 ret = check_overlay_src(dev, put_image_rec, new_bo);
1172 if (ret != 0)
1173 goto out_unlock;
1174 params->format = put_image_rec->flags & ~I915_OVERLAY_FLAGS_MASK;
1175 params->stride_Y = put_image_rec->stride_Y;
1176 params->stride_UV = put_image_rec->stride_UV;
1177 params->offset_Y = put_image_rec->offset_Y;
1178 params->offset_U = put_image_rec->offset_U;
1179 params->offset_V = put_image_rec->offset_V;
1180
1181 /* Check scaling after src size to prevent a divide-by-zero. */
1182 ret = check_overlay_scaling(params);
1183 if (ret != 0)
1184 goto out_unlock;
1185
1186 ret = intel_overlay_do_put_image(overlay, new_bo, params);
1187 if (ret != 0)
1188 goto out_unlock;
1189
1190 mutex_unlock(&dev->struct_mutex);
1191 mutex_unlock(&dev->mode_config.mutex);
1192
1193 kfree(params);
1194
1195 return 0;
1196
1197out_unlock:
1198 mutex_unlock(&dev->struct_mutex);
1199 mutex_unlock(&dev->mode_config.mutex);
bc9025bd 1200 drm_gem_object_unreference_unlocked(new_bo);
915a428e 1201out_free:
02e792fb
DV		 1202 kfree(params);
1203
1204 return ret;
1205}
1206
1207static void update_reg_attrs(struct intel_overlay *overlay,
1208 struct overlay_registers *regs)
1209{
1210 regs->OCLRC0 = (overlay->contrast << 18) | (overlay->brightness & 0xff);
1211 regs->OCLRC1 = overlay->saturation;
1212}
1213
1214static bool check_gamma_bounds(u32 gamma1, u32 gamma2)
1215{
1216 int i;
1217
1218 if (gamma1 & 0xff000000 || gamma2 & 0xff000000)
1219 return false;
1220
1221 for (i = 0; i < 3; i++) {
722506f0 1222 if (((gamma1 >> i*8) & 0xff) >= ((gamma2 >> i*8) & 0xff))
02e792fb
DV		 1223 return false;
1224 }
1225
1226 return true;
1227}
1228
1229static bool check_gamma5_errata(u32 gamma5)
1230{
1231 int i;
1232
1233 for (i = 0; i < 3; i++) {
1234 if (((gamma5 >> i*8) & 0xff) == 0x80)
1235 return false;
1236 }
1237
1238 return true;
1239}
1240
1241static int check_gamma(struct drm_intel_overlay_attrs *attrs)
1242{
722506f0
CW		 1243 if (!check_gamma_bounds(0, attrs->gamma0) ||
1244 !check_gamma_bounds(attrs->gamma0, attrs->gamma1) ||
1245 !check_gamma_bounds(attrs->gamma1, attrs->gamma2) ||
1246 !check_gamma_bounds(attrs->gamma2, attrs->gamma3) ||
1247 !check_gamma_bounds(attrs->gamma3, attrs->gamma4) ||
1248 !check_gamma_bounds(attrs->gamma4, attrs->gamma5) ||
1249 !check_gamma_bounds(attrs->gamma5, 0x00ffffff))
02e792fb 1250 return -EINVAL;
722506f0 1251
02e792fb
DV		 1252 if (!check_gamma5_errata(attrs->gamma5))
1253 return -EINVAL;
722506f0 1254
02e792fb
DV		 1255 return 0;
1256}
1257
1258int intel_overlay_attrs(struct drm_device *dev, void *data,
1259 struct drm_file *file_priv)
1260{
1261 struct drm_intel_overlay_attrs *attrs = data;
1262 drm_i915_private_t *dev_priv = dev->dev_private;
1263 struct intel_overlay *overlay;
1264 struct overlay_registers *regs;
1265 int ret;
1266
1267 if (!dev_priv) {
1268 DRM_ERROR("called with no initialization\n");
1269 return -EINVAL;
1270 }
1271
1272 overlay = dev_priv->overlay;
1273 if (!overlay) {
1274 DRM_DEBUG("userspace bug: no overlay\n");
1275 return -ENODEV;
1276 }
1277
1278 mutex_lock(&dev->mode_config.mutex);
1279 mutex_lock(&dev->struct_mutex);
1280
1281 if (!(attrs->flags & I915_OVERLAY_UPDATE_ATTRS)) {
1282 attrs->color_key = overlay->color_key;
1283 attrs->brightness = overlay->brightness;
1284 attrs->contrast = overlay->contrast;
1285 attrs->saturation = overlay->saturation;
1286
1287 if (IS_I9XX(dev)) {
1288 attrs->gamma0 = I915_READ(OGAMC0);
1289 attrs->gamma1 = I915_READ(OGAMC1);
1290 attrs->gamma2 = I915_READ(OGAMC2);
1291 attrs->gamma3 = I915_READ(OGAMC3);
1292 attrs->gamma4 = I915_READ(OGAMC4);
1293 attrs->gamma5 = I915_READ(OGAMC5);
1294 }
1295 ret = 0;
1296 } else {
1297 overlay->color_key = attrs->color_key;
1298 if (attrs->brightness >= -128 && attrs->brightness <= 127) {
1299 overlay->brightness = attrs->brightness;
1300 } else {
1301 ret = -EINVAL;
1302 goto out_unlock;
1303 }
722506f0 1304
02e792fb
DV		 1305 if (attrs->contrast <= 255) {
1306 overlay->contrast = attrs->contrast;
1307 } else {
1308 ret = -EINVAL;
1309 goto out_unlock;
1310 }
722506f0 1311
02e792fb
DV		 1312 if (attrs->saturation <= 1023) {
1313 overlay->saturation = attrs->saturation;
1314 } else {
1315 ret = -EINVAL;
1316 goto out_unlock;
1317 }
1318
1319 regs = intel_overlay_map_regs_atomic(overlay);
1320 if (!regs) {
1321 ret = -ENOMEM;
1322 goto out_unlock;
1323 }
1324
1325 update_reg_attrs(overlay, regs);
1326
1327 intel_overlay_unmap_regs_atomic(overlay);
1328
1329 if (attrs->flags & I915_OVERLAY_UPDATE_GAMMA) {
1330 if (!IS_I9XX(dev)) {
1331 ret = -EINVAL;
1332 goto out_unlock;
1333 }
1334
1335 if (overlay->active) {
1336 ret = -EBUSY;
1337 goto out_unlock;
1338 }
1339
1340 ret = check_gamma(attrs);
1341 if (ret != 0)
1342 goto out_unlock;
1343
1344 I915_WRITE(OGAMC0, attrs->gamma0);
1345 I915_WRITE(OGAMC1, attrs->gamma1);
1346 I915_WRITE(OGAMC2, attrs->gamma2);
1347 I915_WRITE(OGAMC3, attrs->gamma3);
1348 I915_WRITE(OGAMC4, attrs->gamma4);
1349 I915_WRITE(OGAMC5, attrs->gamma5);
1350 }
1351 ret = 0;
1352 }
1353
1354out_unlock:
1355 mutex_unlock(&dev->struct_mutex);
1356 mutex_unlock(&dev->mode_config.mutex);
1357
1358 return ret;
1359}
1360
1361void intel_setup_overlay(struct drm_device *dev)
1362{
1363 drm_i915_private_t *dev_priv = dev->dev_private;
1364 struct intel_overlay *overlay;
1365 struct drm_gem_object *reg_bo;
1366 struct overlay_registers *regs;
1367 int ret;
1368
1369 if (!OVERLAY_EXISTS(dev))
1370 return;
1371
1372 overlay = kzalloc(sizeof(struct intel_overlay), GFP_KERNEL);
1373 if (!overlay)
1374 return;
1375 overlay->dev = dev;
1376
ac52bc56 1377 reg_bo = i915_gem_alloc_object(dev, PAGE_SIZE);
02e792fb
DV		 1378 if (!reg_bo)
1379 goto out_free;
23010e43 1380 overlay->reg_bo = to_intel_bo(reg_bo);
02e792fb
DV		 1381
1382 if (OVERLAY_NONPHYSICAL(dev)) {
1383 ret = i915_gem_object_pin(reg_bo, PAGE_SIZE);
1384 if (ret) {
1385 DRM_ERROR("failed to pin overlay register bo\n");
1386 goto out_free_bo;
1387 }
1388 overlay->flip_addr = overlay->reg_bo->gtt_offset;
1389 } else {
1390 ret = i915_gem_attach_phys_object(dev, reg_bo,
6eeefaf3
CW		 1391 I915_GEM_PHYS_OVERLAY_REGS,
1392 0);
02e792fb
DV		 1393 if (ret) {
1394 DRM_ERROR("failed to attach phys overlay regs\n");
1395 goto out_free_bo;
1396 }
1397 overlay->flip_addr = overlay->reg_bo->phys_obj->handle->busaddr;
1398 }
1399
1400 /* init all values */
1401 overlay->color_key = 0x0101fe;
1402 overlay->brightness = -19;
1403 overlay->contrast = 75;
1404 overlay->saturation = 146;
1405
1406 regs = intel_overlay_map_regs_atomic(overlay);
1407 if (!regs)
1408 goto out_free_bo;
1409
1410 memset(regs, 0, sizeof(struct overlay_registers));
1411 update_polyphase_filter(regs);
1412
1413 update_reg_attrs(overlay, regs);
1414
1415 intel_overlay_unmap_regs_atomic(overlay);
1416
1417 dev_priv->overlay = overlay;
1418 DRM_INFO("initialized overlay support\n");
1419 return;
1420
1421out_free_bo:
1422 drm_gem_object_unreference(reg_bo);
1423out_free:
1424 kfree(overlay);
1425 return;
1426}
1427
1428void intel_cleanup_overlay(struct drm_device *dev)
1429{
722506f0 1430 drm_i915_private_t *dev_priv = dev->dev_private;
02e792fb
DV		 1431
1432 if (dev_priv->overlay) {
1433 /* The bo's should be free'd by the generic code already.
1434 * Furthermore modesetting teardown happens beforehand so the
1435 * hardware should be off already */
1436 BUG_ON(dev_priv->overlay->active);
1437
1438 kfree(dev_priv->overlay);
1439 }
1440}
6ef3d427
CW		 1441
1442struct intel_overlay_error_state {
1443 struct overlay_registers regs;
1444 unsigned long base;
1445 u32 dovsta;
1446 u32 isr;
1447};
1448
1449struct intel_overlay_error_state *
1450intel_overlay_capture_error_state(struct drm_device *dev)
1451{
1452 drm_i915_private_t *dev_priv = dev->dev_private;
1453 struct intel_overlay *overlay = dev_priv->overlay;
1454 struct intel_overlay_error_state *error;
1455 struct overlay_registers __iomem *regs;
1456
1457 if (!overlay || !overlay->active)
1458 return NULL;
1459
1460 error = kmalloc(sizeof(*error), GFP_ATOMIC);
1461 if (error == NULL)
1462 return NULL;
1463
1464 error->dovsta = I915_READ(DOVSTA);
1465 error->isr = I915_READ(ISR);
1466 if (OVERLAY_NONPHYSICAL(overlay->dev))
1467 error->base = (long) overlay->reg_bo->gtt_offset;
1468 else
1469 error->base = (long) overlay->reg_bo->phys_obj->handle->vaddr;
1470
1471 regs = intel_overlay_map_regs_atomic(overlay);
1472 if (!regs)
1473 goto err;
1474
1475 memcpy_fromio(&error->regs, regs, sizeof(struct overlay_registers));
1476 intel_overlay_unmap_regs_atomic(overlay);
1477
1478 return error;
1479
1480err:
1481 kfree(error);
1482 return NULL;
1483}
1484
1485void
1486intel_overlay_print_error_state(struct seq_file *m, struct intel_overlay_error_state *error)
1487{
1488 seq_printf(m, "Overlay, status: 0x%08x, interrupt: 0x%08x\n",
1489 error->dovsta, error->isr);
1490 seq_printf(m, " Register file at 0x%08lx:\n",
1491 error->base);
1492
1493#define P(x) seq_printf(m, " " #x ": 0x%08x\n", error->regs.x)
1494 P(OBUF_0Y);
1495 P(OBUF_1Y);
1496 P(OBUF_0U);
1497 P(OBUF_0V);
1498 P(OBUF_1U);
1499 P(OBUF_1V);
1500 P(OSTRIDE);
1501 P(YRGB_VPH);
1502 P(UV_VPH);
1503 P(HORZ_PH);
1504 P(INIT_PHS);
1505 P(DWINPOS);
1506 P(DWINSZ);
1507 P(SWIDTH);
1508 P(SWIDTHSW);
1509 P(SHEIGHT);
1510 P(YRGBSCALE);
1511 P(UVSCALE);
1512 P(OCLRC0);
1513 P(OCLRC1);
1514 P(DCLRKV);
1515 P(DCLRKM);
1516 P(SCLRKVH);
1517 P(SCLRKVL);
1518 P(SCLRKEN);
1519 P(OCONFIG);
1520 P(OCMD);
1521 P(OSTART_0Y);
1522 P(OSTART_1Y);
1523 P(OSTART_0U);
1524 P(OSTART_0V);
1525 P(OSTART_1U);
1526 P(OSTART_1V);
1527 P(OTILEOFF_0Y);
1528 P(OTILEOFF_1Y);
1529 P(OTILEOFF_0U);
1530 P(OTILEOFF_0V);
1531 P(OTILEOFF_1U);
1532 P(OTILEOFF_1V);
1533 P(FASTHSCALE);
1534 P(UVSCALEV);
1535#undef P
1536}
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