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UBUNTU: SAUCE: Revert "drm/i915/edp: Allow alternate fixed mode for eDP if available."
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW
1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
f766093e 33#include <linux/kernel.h>
7bd90909 34#include <linux/moduleparam.h>
b029e66f 35#include <linux/pwm.h>
1d8e1c75
CW
36#include "intel_drv.h"
37
b029e66f
SK
38#define CRC_PMIC_PWM_PERIOD_NS 21333
39
1d8e1c75 40void
4c6df4b4 41intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW
42 struct drm_display_mode *adjusted_mode)
43{
4c6df4b4 44 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID
45
46 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW
47}
48
525997e0
JN
49/**
50 * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID
a318b4c4 51 * @dev_priv: i915 device instance
525997e0
JN
52 * @fixed_mode : panel native mode
53 * @connector: LVDS/eDP connector
54 *
55 * Return downclock_avail
56 * Find the reduced downclock for LVDS/eDP in EDID.
57 */
58struct drm_display_mode *
a318b4c4 59intel_find_panel_downclock(struct drm_i915_private *dev_priv,
525997e0
JN
60 struct drm_display_mode *fixed_mode,
61 struct drm_connector *connector)
62{
63 struct drm_display_mode *scan, *tmp_mode;
64 int temp_downclock;
65
66 temp_downclock = fixed_mode->clock;
67 tmp_mode = NULL;
68
69 list_for_each_entry(scan, &connector->probed_modes, head) {
70 /*
71 * If one mode has the same resolution with the fixed_panel
72 * mode while they have the different refresh rate, it means
73 * that the reduced downclock is found. In such
74 * case we can set the different FPx0/1 to dynamically select
75 * between low and high frequency.
76 */
77 if (scan->hdisplay == fixed_mode->hdisplay &&
78 scan->hsync_start == fixed_mode->hsync_start &&
79 scan->hsync_end == fixed_mode->hsync_end &&
80 scan->htotal == fixed_mode->htotal &&
81 scan->vdisplay == fixed_mode->vdisplay &&
82 scan->vsync_start == fixed_mode->vsync_start &&
83 scan->vsync_end == fixed_mode->vsync_end &&
84 scan->vtotal == fixed_mode->vtotal) {
85 if (scan->clock < temp_downclock) {
86 /*
87 * The downclock is already found. But we
88 * expect to find the lower downclock.
89 */
90 temp_downclock = scan->clock;
91 tmp_mode = scan;
92 }
93 }
94 }
95
96 if (temp_downclock < fixed_mode->clock)
a318b4c4 97 return drm_mode_duplicate(&dev_priv->drm, tmp_mode);
525997e0
JN
98 else
99 return NULL;
100}
101
1d8e1c75
CW
102/* adjusted_mode has been preset to be the panel's fixed mode */
103void
b074cec8 104intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 105 struct intel_crtc_state *pipe_config,
b074cec8 106 int fitting_mode)
1d8e1c75 107{
7c5f93b0
VS
108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
109 int x = 0, y = 0, width = 0, height = 0;
1d8e1c75
CW
110
111 /* Native modes don't need fitting */
aad941d5 112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
e5c05931
SS
113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h &&
114 !pipe_config->ycbcr420)
1d8e1c75
CW
115 goto done;
116
117 switch (fitting_mode) {
118 case DRM_MODE_SCALE_CENTER:
37327abd
VS
119 width = pipe_config->pipe_src_w;
120 height = pipe_config->pipe_src_h;
aad941d5
VS
121 x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
122 y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
1d8e1c75
CW
123 break;
124
125 case DRM_MODE_SCALE_ASPECT:
126 /* Scale but preserve the aspect ratio */
127 {
aad941d5 128 u32 scaled_width = adjusted_mode->crtc_hdisplay
9084e7d2
DV
129 * pipe_config->pipe_src_h;
130 u32 scaled_height = pipe_config->pipe_src_w
aad941d5 131 * adjusted_mode->crtc_vdisplay;
1d8e1c75 132 if (scaled_width > scaled_height) { /* pillar */
37327abd 133 width = scaled_height / pipe_config->pipe_src_h;
302983e9 134 if (width & 1)
0206e353 135 width++;
aad941d5 136 x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
1d8e1c75 137 y = 0;
aad941d5 138 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 139 } else if (scaled_width < scaled_height) { /* letter */
37327abd 140 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ
141 if (height & 1)
142 height++;
aad941d5 143 y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
1d8e1c75 144 x = 0;
aad941d5 145 width = adjusted_mode->crtc_hdisplay;
1d8e1c75
CW
146 } else {
147 x = y = 0;
aad941d5
VS
148 width = adjusted_mode->crtc_hdisplay;
149 height = adjusted_mode->crtc_vdisplay;
1d8e1c75
CW
150 }
151 }
152 break;
153
1d8e1c75
CW
154 case DRM_MODE_SCALE_FULLSCREEN:
155 x = y = 0;
aad941d5
VS
156 width = adjusted_mode->crtc_hdisplay;
157 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 158 break;
ab3e67f4
JB
159
160 default:
161 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
162 return;
1d8e1c75
CW
163 }
164
165done:
b074cec8
JB
166 pipe_config->pch_pfit.pos = (x << 16) | y;
167 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 168 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 169}
a9573556 170
2dd24552 171static void
5e7234c9 172centre_horizontally(struct drm_display_mode *adjusted_mode,
2dd24552
JB
173 int width)
174{
175 u32 border, sync_pos, blank_width, sync_width;
176
177 /* keep the hsync and hblank widths constant */
5e7234c9
VS
178 sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
179 blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
2dd24552
JB
180 sync_pos = (blank_width - sync_width + 1) / 2;
181
aad941d5 182 border = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
2dd24552
JB
183 border += border & 1; /* make the border even */
184
5e7234c9
VS
185 adjusted_mode->crtc_hdisplay = width;
186 adjusted_mode->crtc_hblank_start = width + border;
187 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width;
2dd24552 188
5e7234c9
VS
189 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos;
190 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width;
2dd24552
JB
191}
192
193static void
5e7234c9 194centre_vertically(struct drm_display_mode *adjusted_mode,
2dd24552
JB
195 int height)
196{
197 u32 border, sync_pos, blank_width, sync_width;
198
199 /* keep the vsync and vblank widths constant */
5e7234c9
VS
200 sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
201 blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
2dd24552
JB
202 sync_pos = (blank_width - sync_width + 1) / 2;
203
aad941d5 204 border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
2dd24552 205
5e7234c9
VS
206 adjusted_mode->crtc_vdisplay = height;
207 adjusted_mode->crtc_vblank_start = height + border;
208 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width;
2dd24552 209
5e7234c9
VS
210 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos;
211 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width;
2dd24552
JB
212}
213
214static inline u32 panel_fitter_scaling(u32 source, u32 target)
215{
216 /*
217 * Floating point operation is not supported. So the FACTOR
218 * is defined, which can avoid the floating point computation
219 * when calculating the panel ratio.
220 */
221#define ACCURACY 12
222#define FACTOR (1 << ACCURACY)
223 u32 ratio = source * FACTOR / target;
224 return (FACTOR * ratio + FACTOR/2) / FACTOR;
225}
226
5cec258b 227static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
DV
228 u32 *pfit_control)
229{
7c5f93b0 230 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 231 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
DV
232 pipe_config->pipe_src_h;
233 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 234 adjusted_mode->crtc_vdisplay;
9084e7d2
DV
235
236 /* 965+ is easy, it does everything in hw */
237 if (scaled_width > scaled_height)
238 *pfit_control |= PFIT_ENABLE |
239 PFIT_SCALING_PILLAR;
240 else if (scaled_width < scaled_height)
241 *pfit_control |= PFIT_ENABLE |
242 PFIT_SCALING_LETTER;
aad941d5 243 else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w)
9084e7d2
DV
244 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
245}
246
5cec258b 247static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
DV
248 u32 *pfit_control, u32 *pfit_pgm_ratios,
249 u32 *border)
250{
2d112de7 251 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 252 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
DV
253 pipe_config->pipe_src_h;
254 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 255 adjusted_mode->crtc_vdisplay;
9084e7d2
DV
256 u32 bits;
257
258 /*
259 * For earlier chips we have to calculate the scaling
260 * ratio by hand and program it into the
261 * PFIT_PGM_RATIO register
262 */
263 if (scaled_width > scaled_height) { /* pillar */
264 centre_horizontally(adjusted_mode,
265 scaled_height /
266 pipe_config->pipe_src_h);
267
268 *border = LVDS_BORDER_ENABLE;
aad941d5 269 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) {
9084e7d2 270 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
aad941d5 271 adjusted_mode->crtc_vdisplay);
9084e7d2
DV
272
273 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
274 bits << PFIT_VERT_SCALE_SHIFT);
275 *pfit_control |= (PFIT_ENABLE |
276 VERT_INTERP_BILINEAR |
277 HORIZ_INTERP_BILINEAR);
278 }
279 } else if (scaled_width < scaled_height) { /* letter */
280 centre_vertically(adjusted_mode,
281 scaled_width /
282 pipe_config->pipe_src_w);
283
284 *border = LVDS_BORDER_ENABLE;
aad941d5 285 if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
9084e7d2 286 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
aad941d5 287 adjusted_mode->crtc_hdisplay);
9084e7d2
DV
288
289 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
290 bits << PFIT_VERT_SCALE_SHIFT);
291 *pfit_control |= (PFIT_ENABLE |
292 VERT_INTERP_BILINEAR |
293 HORIZ_INTERP_BILINEAR);
294 }
295 } else {
296 /* Aspects match, Let hw scale both directions */
297 *pfit_control |= (PFIT_ENABLE |
298 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
299 VERT_INTERP_BILINEAR |
300 HORIZ_INTERP_BILINEAR);
301 }
302}
303
2dd24552 304void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 305 struct intel_crtc_state *pipe_config,
2dd24552
JB
306 int fitting_mode)
307{
66478475 308 struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev);
2dd24552 309 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
7c5f93b0 310 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2dd24552
JB
311
312 /* Native modes don't need fitting */
aad941d5
VS
313 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
314 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
2dd24552
JB
315 goto out;
316
317 switch (fitting_mode) {
318 case DRM_MODE_SCALE_CENTER:
319 /*
320 * For centered modes, we have to calculate border widths &
321 * heights and modify the values programmed into the CRTC.
322 */
37327abd
VS
323 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
324 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB
325 border = LVDS_BORDER_ENABLE;
326 break;
327 case DRM_MODE_SCALE_ASPECT:
328 /* Scale but preserve the aspect ratio */
66478475 329 if (INTEL_GEN(dev_priv) >= 4)
9084e7d2
DV
330 i965_scale_aspect(pipe_config, &pfit_control);
331 else
332 i9xx_scale_aspect(pipe_config, &pfit_control,
333 &pfit_pgm_ratios, &border);
2dd24552 334 break;
2dd24552
JB
335 case DRM_MODE_SCALE_FULLSCREEN:
336 /*
337 * Full scaling, even if it changes the aspect ratio.
338 * Fortunately this is all done for us in hw.
339 */
aad941d5
VS
340 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
341 pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
2dd24552 342 pfit_control |= PFIT_ENABLE;
66478475 343 if (INTEL_GEN(dev_priv) >= 4)
2dd24552
JB
344 pfit_control |= PFIT_SCALING_AUTO;
345 else
346 pfit_control |= (VERT_AUTO_SCALE |
347 VERT_INTERP_BILINEAR |
348 HORIZ_AUTO_SCALE |
349 HORIZ_INTERP_BILINEAR);
350 }
351 break;
ab3e67f4
JB
352 default:
353 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
354 return;
2dd24552
JB
355 }
356
357 /* 965+ wants fuzzy fitting */
358 /* FIXME: handle multiple panels by failing gracefully */
66478475 359 if (INTEL_GEN(dev_priv) >= 4)
2dd24552
JB
360 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
361 PFIT_FILTER_FUZZY);
362
363out:
364 if ((pfit_control & PFIT_ENABLE) == 0) {
365 pfit_control = 0;
366 pfit_pgm_ratios = 0;
367 }
368
6b89cdde 369 /* Make sure pre-965 set dither correctly for 18bpp panels. */
66478475 370 if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18)
6b89cdde
DV
371 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
372
2deefda5
DV
373 pipe_config->gmch_pfit.control = pfit_control;
374 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 375 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB
376}
377
525997e0 378enum drm_connector_status
1650be74 379intel_panel_detect(struct drm_i915_private *dev_priv)
525997e0 380{
525997e0 381 /* Assume that the BIOS does not lie through the OpRegion... */
4f044a88 382 if (!i915_modparams.panel_ignore_lid && dev_priv->opregion.lid_state) {
115719fc 383 return *dev_priv->opregion.lid_state & 0x1 ?
525997e0
JN
384 connector_status_connected :
385 connector_status_disconnected;
386 }
387
4f044a88 388 switch (i915_modparams.panel_ignore_lid) {
525997e0
JN
389 case -2:
390 return connector_status_connected;
391 case -1:
392 return connector_status_disconnected;
393 default:
394 return connector_status_unknown;
395 }
396}
397
6dda730e
JN
398/**
399 * scale - scale values from one range to another
400 *
401 * @source_val: value in range [@source_min..@source_max]
402 *
403 * Return @source_val in range [@source_min..@source_max] scaled to range
404 * [@target_min..@target_max].
405 */
406static uint32_t scale(uint32_t source_val,
407 uint32_t source_min, uint32_t source_max,
408 uint32_t target_min, uint32_t target_max)
409{
410 uint64_t target_val;
411
412 WARN_ON(source_min > source_max);
413 WARN_ON(target_min > target_max);
414
415 /* defensive */
416 source_val = clamp(source_val, source_min, source_max);
417
418 /* avoid overflows */
673e7bbd
AE
419 target_val = DIV_ROUND_CLOSEST_ULL((uint64_t)(source_val - source_min) *
420 (target_max - target_min), source_max - source_min);
6dda730e
JN
421 target_val += target_min;
422
423 return target_val;
424}
425
426/* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */
427static inline u32 scale_user_to_hw(struct intel_connector *connector,
428 u32 user_level, u32 user_max)
429{
430 struct intel_panel *panel = &connector->panel;
431
432 return scale(user_level, 0, user_max,
433 panel->backlight.min, panel->backlight.max);
434}
435
436/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result
437 * to [hw_min..hw_max]. */
438static inline u32 clamp_user_to_hw(struct intel_connector *connector,
439 u32 user_level, u32 user_max)
440{
441 struct intel_panel *panel = &connector->panel;
442 u32 hw_level;
443
444 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max);
445 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max);
446
447 return hw_level;
448}
449
450/* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */
451static inline u32 scale_hw_to_user(struct intel_connector *connector,
452 u32 hw_level, u32 user_max)
453{
454 struct intel_panel *panel = &connector->panel;
455
456 return scale(hw_level, panel->backlight.min, panel->backlight.max,
457 0, user_max);
458}
459
7bd688cd
JN
460static u32 intel_panel_compute_brightness(struct intel_connector *connector,
461 u32 val)
7bd90909 462{
e6cb3727 463 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
f91c15e0
JN
464 struct intel_panel *panel = &connector->panel;
465
466 WARN_ON(panel->backlight.max == 0);
4dca20ef 467
4f044a88 468 if (i915_modparams.invert_brightness < 0)
4dca20ef
CE
469 return val;
470
4f044a88 471 if (i915_modparams.invert_brightness > 0 ||
d6540632 472 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
e9d7486e 473 return panel->backlight.max - val + panel->backlight.min;
d6540632 474 }
7bd90909
CE
475
476 return val;
477}
478
437b15b8 479static u32 lpt_get_backlight(struct intel_connector *connector)
0b0b053a 480{
e6cb3727 481 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0b0b053a 482
96ab4c70
DV
483 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
484}
07bf139b 485
7bd688cd 486static u32 pch_get_backlight(struct intel_connector *connector)
a9573556 487{
e6cb3727 488 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
8ba2d185 489
7bd688cd
JN
490 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
491}
a9573556 492
7bd688cd
JN
493static u32 i9xx_get_backlight(struct intel_connector *connector)
494{
e6cb3727 495 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
636baebf 496 struct intel_panel *panel = &connector->panel;
7bd688cd 497 u32 val;
07bf139b 498
7bd688cd 499 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
e6cb3727 500 if (INTEL_INFO(dev_priv)->gen < 4)
7bd688cd 501 val >>= 1;
ba3820ad 502
636baebf 503 if (panel->backlight.combination_mode) {
7bd688cd 504 u8 lbpc;
ba3820ad 505
91c8a326 506 pci_read_config_byte(dev_priv->drm.pdev, LBPC, &lbpc);
7bd688cd 507 val *= lbpc;
a9573556
CW
508 }
509
7bd688cd
JN
510 return val;
511}
512
e6cb3727 513static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe)
7bd688cd 514{
23ec0a88
VS
515 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
516 return 0;
517
7bd688cd
JN
518 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
519}
520
521static u32 vlv_get_backlight(struct intel_connector *connector)
522{
e6cb3727 523 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd
JN
524 enum pipe pipe = intel_get_pipe_from_connector(connector);
525
e6cb3727 526 return _vlv_get_backlight(dev_priv, pipe);
7bd688cd
JN
527}
528
0fb890c0
VK
529static u32 bxt_get_backlight(struct intel_connector *connector)
530{
e6cb3727 531 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52 532 struct intel_panel *panel = &connector->panel;
0fb890c0 533
022e4e52 534 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
0fb890c0
VK
535}
536
b029e66f
SK
537static u32 pwm_get_backlight(struct intel_connector *connector)
538{
539 struct intel_panel *panel = &connector->panel;
540 int duty_ns;
541
542 duty_ns = pwm_get_duty_cycle(panel->backlight.pwm);
543 return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS);
544}
545
7bd688cd
JN
546static u32 intel_panel_get_backlight(struct intel_connector *connector)
547{
e6cb3727 548 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
2d72f6c7
VS
549 struct intel_panel *panel = &connector->panel;
550 u32 val = 0;
7bd688cd 551
07f11d49 552 mutex_lock(&dev_priv->backlight_lock);
7bd688cd 553
2d72f6c7 554 if (panel->backlight.enabled) {
5507faeb 555 val = panel->backlight.get(connector);
2d72f6c7
VS
556 val = intel_panel_compute_brightness(connector, val);
557 }
8ba2d185 558
07f11d49 559 mutex_unlock(&dev_priv->backlight_lock);
8ba2d185 560
a9573556
CW
561 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
562 return val;
563}
564
7d025e08 565static void lpt_set_backlight(const struct drm_connector_state *conn_state, u32 level)
f8e10062 566{
7d025e08 567 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 568 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 569
f8e10062
BW
570 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
571 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
572}
573
7d025e08 574static void pch_set_backlight(const struct drm_connector_state *conn_state, u32 level)
a9573556 575{
7d025e08 576 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 577 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd
JN
578 u32 tmp;
579
580 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
581 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
a9573556
CW
582}
583
7d025e08 584static void i9xx_set_backlight(const struct drm_connector_state *conn_state, u32 level)
a9573556 585{
7d025e08 586 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 587 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
f91c15e0 588 struct intel_panel *panel = &connector->panel;
b329b328 589 u32 tmp, mask;
ba3820ad 590
f91c15e0
JN
591 WARN_ON(panel->backlight.max == 0);
592
636baebf 593 if (panel->backlight.combination_mode) {
ba3820ad
TI
594 u8 lbpc;
595
f91c15e0 596 lbpc = level * 0xfe / panel->backlight.max + 1;
ba3820ad 597 level /= lbpc;
91c8a326 598 pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc);
ba3820ad
TI
599 }
600
e6cb3727 601 if (IS_GEN4(dev_priv)) {
b329b328
JN
602 mask = BACKLIGHT_DUTY_CYCLE_MASK;
603 } else {
a9573556 604 level <<= 1;
b329b328
JN
605 mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
606 }
7bd688cd 607
b329b328 608 tmp = I915_READ(BLC_PWM_CTL) & ~mask;
7bd688cd
JN
609 I915_WRITE(BLC_PWM_CTL, tmp | level);
610}
611
7d025e08 612static void vlv_set_backlight(const struct drm_connector_state *conn_state, u32 level)
7bd688cd 613{
7d025e08 614 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 615 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 616 enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;
7bd688cd
JN
617 u32 tmp;
618
619 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
620 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
621}
622
7d025e08 623static void bxt_set_backlight(const struct drm_connector_state *conn_state, u32 level)
0fb890c0 624{
7d025e08 625 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 626 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52 627 struct intel_panel *panel = &connector->panel;
0fb890c0 628
022e4e52 629 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
0fb890c0
VK
630}
631
7d025e08 632static void pwm_set_backlight(const struct drm_connector_state *conn_state, u32 level)
b029e66f 633{
7d025e08 634 struct intel_panel *panel = &to_intel_connector(conn_state->connector)->panel;
b029e66f
SK
635 int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100);
636
637 pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS);
638}
639
7bd688cd 640static void
7d025e08 641intel_panel_actually_set_backlight(const struct drm_connector_state *conn_state, u32 level)
7bd688cd 642{
7d025e08 643 struct intel_connector *connector = to_intel_connector(conn_state->connector);
5507faeb 644 struct intel_panel *panel = &connector->panel;
7bd688cd
JN
645
646 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
647
648 level = intel_panel_compute_brightness(connector, level);
7d025e08 649 panel->backlight.set(conn_state, level);
a9573556 650}
47356eb6 651
6dda730e 652/* set backlight brightness to level in range [0..max], scaling wrt hw min */
7d025e08 653static void intel_panel_set_backlight(const struct drm_connector_state *conn_state,
6dda730e 654 u32 user_level, u32 user_max)
47356eb6 655{
7d025e08 656 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 657 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
58c68779 658 struct intel_panel *panel = &connector->panel;
6dda730e 659 u32 hw_level;
8ba2d185 660
260d8f98 661 if (!panel->backlight.present)
752aa88a
JB
662 return;
663
07f11d49 664 mutex_lock(&dev_priv->backlight_lock);
d6540632 665
f91c15e0 666 WARN_ON(panel->backlight.max == 0);
d6540632 667
6dda730e
JN
668 hw_level = scale_user_to_hw(connector, user_level, user_max);
669 panel->backlight.level = hw_level;
670
671 if (panel->backlight.enabled)
7d025e08 672 intel_panel_actually_set_backlight(conn_state, hw_level);
6dda730e 673
07f11d49 674 mutex_unlock(&dev_priv->backlight_lock);
6dda730e
JN
675}
676
677/* set backlight brightness to level in range [0..max], assuming hw min is
678 * respected.
679 */
90d7cd24 680void intel_panel_set_backlight_acpi(const struct drm_connector_state *conn_state,
6dda730e
JN
681 u32 user_level, u32 user_max)
682{
90d7cd24 683 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 684 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6dda730e 685 struct intel_panel *panel = &connector->panel;
6dda730e 686 u32 hw_level;
6dda730e 687
260d8f98 688 /*
90d7cd24 689 * Lack of crtc may occur during driver init because
260d8f98
VS
690 * connection_mutex isn't held across the entire backlight
691 * setup + modeset readout, and the BIOS can issue the
692 * requests at any time.
693 */
90d7cd24 694 if (!panel->backlight.present || !conn_state->crtc)
6dda730e
JN
695 return;
696
07f11d49 697 mutex_lock(&dev_priv->backlight_lock);
6dda730e
JN
698
699 WARN_ON(panel->backlight.max == 0);
700
701 hw_level = clamp_user_to_hw(connector, user_level, user_max);
702 panel->backlight.level = hw_level;
47356eb6 703
58c68779 704 if (panel->backlight.device)
6dda730e
JN
705 panel->backlight.device->props.brightness =
706 scale_hw_to_user(connector,
707 panel->backlight.level,
708 panel->backlight.device->props.max_brightness);
b6b3ba5b 709
58c68779 710 if (panel->backlight.enabled)
7d025e08 711 intel_panel_actually_set_backlight(conn_state, hw_level);
f91c15e0 712
07f11d49 713 mutex_unlock(&dev_priv->backlight_lock);
f52c619a
TI
714}
715
7d025e08 716static void lpt_disable_backlight(const struct drm_connector_state *old_conn_state)
437b15b8 717{
7d025e08 718 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 719 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
437b15b8
JN
720 u32 tmp;
721
7d025e08 722 intel_panel_actually_set_backlight(old_conn_state, 0);
437b15b8 723
6675bce2
JN
724 /*
725 * Although we don't support or enable CPU PWM with LPT/SPT based
726 * systems, it may have been enabled prior to loading the
727 * driver. Disable to avoid warnings on LCPLL disable.
728 *
729 * This needs rework if we need to add support for CPU PWM on PCH split
730 * platforms.
731 */
732 tmp = I915_READ(BLC_PWM_CPU_CTL2);
733 if (tmp & BLM_PWM_ENABLE) {
734 DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");
735 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
736 }
737
437b15b8
JN
738 tmp = I915_READ(BLC_PWM_PCH_CTL1);
739 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
740}
741
7d025e08 742static void pch_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 743{
7d025e08 744 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 745 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd
JN
746 u32 tmp;
747
7d025e08 748 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 749
7bd688cd
JN
750 tmp = I915_READ(BLC_PWM_CPU_CTL2);
751 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
752
753 tmp = I915_READ(BLC_PWM_PCH_CTL1);
754 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
755}
756
7d025e08 757static void i9xx_disable_backlight(const struct drm_connector_state *old_conn_state)
3bd712e5 758{
7d025e08 759 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5
JN
760}
761
7d025e08 762static void i965_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 763{
7d025e08 764 struct drm_i915_private *dev_priv = to_i915(old_conn_state->connector->dev);
7bd688cd
JN
765 u32 tmp;
766
7d025e08 767 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 768
7bd688cd
JN
769 tmp = I915_READ(BLC_PWM_CTL2);
770 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
771}
772
7d025e08 773static void vlv_disable_backlight(const struct drm_connector_state *old_conn_state)
7bd688cd 774{
7d025e08 775 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 776 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7d025e08 777 enum pipe pipe = to_intel_crtc(old_conn_state->crtc)->pipe;
7bd688cd
JN
778 u32 tmp;
779
7d025e08 780 intel_panel_actually_set_backlight(old_conn_state, 0);
3bd712e5 781
7bd688cd
JN
782 tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
783 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);
784}
785
7d025e08 786static void bxt_disable_backlight(const struct drm_connector_state *old_conn_state)
0fb890c0 787{
7d025e08 788 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 789 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
022e4e52
SK
790 struct intel_panel *panel = &connector->panel;
791 u32 tmp, val;
0fb890c0 792
7d025e08 793 intel_panel_actually_set_backlight(old_conn_state, 0);
0fb890c0 794
022e4e52
SK
795 tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
796 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
797 tmp & ~BXT_BLC_PWM_ENABLE);
798
799 if (panel->backlight.controller == 1) {
800 val = I915_READ(UTIL_PIN_CTL);
801 val &= ~UTIL_PIN_ENABLE;
802 I915_WRITE(UTIL_PIN_CTL, val);
803 }
0fb890c0
VK
804}
805
7d025e08 806static void cnp_disable_backlight(const struct drm_connector_state *old_conn_state)
4c9f7086 807{
7d025e08 808 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
4c9f7086
RV
809 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
810 struct intel_panel *panel = &connector->panel;
811 u32 tmp;
812
7d025e08 813 intel_panel_actually_set_backlight(old_conn_state, 0);
4c9f7086
RV
814
815 tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
816 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
817 tmp & ~BXT_BLC_PWM_ENABLE);
818}
819
7d025e08 820static void pwm_disable_backlight(const struct drm_connector_state *old_conn_state)
b029e66f 821{
7d025e08 822 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
b029e66f
SK
823 struct intel_panel *panel = &connector->panel;
824
825 /* Disable the backlight */
826 pwm_config(panel->backlight.pwm, 0, CRC_PMIC_PWM_PERIOD_NS);
827 usleep_range(2000, 3000);
828 pwm_disable(panel->backlight.pwm);
829}
830
b037d58f 831void intel_panel_disable_backlight(const struct drm_connector_state *old_conn_state)
f52c619a 832{
b037d58f 833 struct intel_connector *connector = to_intel_connector(old_conn_state->connector);
e6cb3727 834 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
58c68779 835 struct intel_panel *panel = &connector->panel;
8ba2d185 836
260d8f98 837 if (!panel->backlight.present)
752aa88a
JB
838 return;
839
3f577573 840 /*
5389e916 841 * Do not disable backlight on the vga_switcheroo path. When switching
3f577573
JN
842 * away from i915, the other client may depend on i915 to handle the
843 * backlight. This will leave the backlight on unnecessarily when
844 * another client is not activated.
845 */
91c8a326 846 if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) {
3f577573
JN
847 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
848 return;
849 }
850
07f11d49 851 mutex_lock(&dev_priv->backlight_lock);
47356eb6 852
ab656bb9
JN
853 if (panel->backlight.device)
854 panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
58c68779 855 panel->backlight.enabled = false;
7d025e08 856 panel->backlight.disable(old_conn_state);
24ded204 857
07f11d49 858 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd 859}
24ded204 860
7d025e08
ML
861static void lpt_enable_backlight(const struct intel_crtc_state *crtc_state,
862 const struct drm_connector_state *conn_state)
96ab4c70 863{
7d025e08 864 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 865 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
96ab4c70 866 struct intel_panel *panel = &connector->panel;
e29aff05 867 u32 pch_ctl1, pch_ctl2, schicken;
96ab4c70
DV
868
869 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
870 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
871 DRM_DEBUG_KMS("pch backlight already enabled\n");
872 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
873 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
874 }
24ded204 875
e29aff05
SL
876 if (HAS_PCH_LPT(dev_priv)) {
877 schicken = I915_READ(SOUTH_CHICKEN2);
878 if (panel->backlight.alternate_pwm_increment)
879 schicken |= LPT_PWM_GRANULARITY;
880 else
881 schicken &= ~LPT_PWM_GRANULARITY;
882 I915_WRITE(SOUTH_CHICKEN2, schicken);
883 } else {
884 schicken = I915_READ(SOUTH_CHICKEN1);
885 if (panel->backlight.alternate_pwm_increment)
886 schicken |= SPT_PWM_GRANULARITY;
887 else
888 schicken &= ~SPT_PWM_GRANULARITY;
889 I915_WRITE(SOUTH_CHICKEN1, schicken);
890 }
891
96ab4c70
DV
892 pch_ctl2 = panel->backlight.max << 16;
893 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
a4f32fc3 894
96ab4c70
DV
895 pch_ctl1 = 0;
896 if (panel->backlight.active_low_pwm)
897 pch_ctl1 |= BLM_PCH_POLARITY;
8ba2d185 898
e6b2627c
JN
899 /* After LPT, override is the default. */
900 if (HAS_PCH_LPT(dev_priv))
901 pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE;
96ab4c70
DV
902
903 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
904 POSTING_READ(BLC_PWM_PCH_CTL1);
905 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
906
907 /* This won't stick until the above enable. */
7d025e08 908 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
47356eb6
CW
909}
910
7d025e08
ML
911static void pch_enable_backlight(const struct intel_crtc_state *crtc_state,
912 const struct drm_connector_state *conn_state)
7bd688cd 913{
7d025e08 914 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 915 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 916 struct intel_panel *panel = &connector->panel;
7d025e08 917 enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
b35684b8 918 u32 cpu_ctl2, pch_ctl1, pch_ctl2;
7bd688cd 919
b35684b8
JN
920 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
921 if (cpu_ctl2 & BLM_PWM_ENABLE) {
813008cd 922 DRM_DEBUG_KMS("cpu backlight already enabled\n");
b35684b8
JN
923 cpu_ctl2 &= ~BLM_PWM_ENABLE;
924 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
925 }
7bd688cd 926
b35684b8
JN
927 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
928 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
929 DRM_DEBUG_KMS("pch backlight already enabled\n");
930 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
931 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
932 }
7bd688cd
JN
933
934 if (cpu_transcoder == TRANSCODER_EDP)
b35684b8 935 cpu_ctl2 = BLM_TRANSCODER_EDP;
7bd688cd 936 else
b35684b8
JN
937 cpu_ctl2 = BLM_PIPE(cpu_transcoder);
938 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
7bd688cd 939 POSTING_READ(BLC_PWM_CPU_CTL2);
b35684b8 940 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);
3bd712e5 941
b35684b8 942 /* This won't stick until the above enable. */
7d025e08 943 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
b35684b8
JN
944
945 pch_ctl2 = panel->backlight.max << 16;
946 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
947
b35684b8
JN
948 pch_ctl1 = 0;
949 if (panel->backlight.active_low_pwm)
950 pch_ctl1 |= BLM_PCH_POLARITY;
96ab4c70 951
b35684b8
JN
952 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
953 POSTING_READ(BLC_PWM_PCH_CTL1);
954 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
3bd712e5
JN
955}
956
7d025e08
ML
957static void i9xx_enable_backlight(const struct intel_crtc_state *crtc_state,
958 const struct drm_connector_state *conn_state)
3bd712e5 959{
7d025e08 960 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 961 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 962 struct intel_panel *panel = &connector->panel;
b35684b8
JN
963 u32 ctl, freq;
964
965 ctl = I915_READ(BLC_PWM_CTL);
966 if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
813008cd 967 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN
968 I915_WRITE(BLC_PWM_CTL, 0);
969 }
3bd712e5 970
b35684b8
JN
971 freq = panel->backlight.max;
972 if (panel->backlight.combination_mode)
973 freq /= 0xff;
974
975 ctl = freq << 17;
b6ab66aa 976 if (panel->backlight.combination_mode)
b35684b8 977 ctl |= BLM_LEGACY_MODE;
e6cb3727 978 if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm)
b35684b8
JN
979 ctl |= BLM_POLARITY_PNV;
980
981 I915_WRITE(BLC_PWM_CTL, ctl);
982 POSTING_READ(BLC_PWM_CTL);
983
984 /* XXX: combine this into above write? */
7d025e08 985 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
2059ac3b
JN
986
987 /*
988 * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
989 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
990 * that has backlight.
991 */
e6cb3727 992 if (IS_GEN2(dev_priv))
2059ac3b 993 I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
7bd688cd 994}
8ba2d185 995
7d025e08
ML
996static void i965_enable_backlight(const struct intel_crtc_state *crtc_state,
997 const struct drm_connector_state *conn_state)
7bd688cd 998{
7d025e08 999 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 1000 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 1001 struct intel_panel *panel = &connector->panel;
7d025e08 1002 enum pipe pipe = to_intel_crtc(conn_state->crtc)->pipe;
b35684b8 1003 u32 ctl, ctl2, freq;
7bd688cd 1004
b35684b8
JN
1005 ctl2 = I915_READ(BLC_PWM_CTL2);
1006 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 1007 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN
1008 ctl2 &= ~BLM_PWM_ENABLE;
1009 I915_WRITE(BLC_PWM_CTL2, ctl2);
1010 }
7bd688cd 1011
b35684b8
JN
1012 freq = panel->backlight.max;
1013 if (panel->backlight.combination_mode)
1014 freq /= 0xff;
7bd688cd 1015
b35684b8
JN
1016 ctl = freq << 16;
1017 I915_WRITE(BLC_PWM_CTL, ctl);
3bd712e5 1018
b35684b8
JN
1019 ctl2 = BLM_PIPE(pipe);
1020 if (panel->backlight.combination_mode)
1021 ctl2 |= BLM_COMBINATION_MODE;
1022 if (panel->backlight.active_low_pwm)
1023 ctl2 |= BLM_POLARITY_I965;
1024 I915_WRITE(BLC_PWM_CTL2, ctl2);
1025 POSTING_READ(BLC_PWM_CTL2);
1026 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
2e7eeeb5 1027
7d025e08 1028 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
7bd688cd
JN
1029}
1030
7d025e08
ML
1031static void vlv_enable_backlight(const struct intel_crtc_state *crtc_state,
1032 const struct drm_connector_state *conn_state)
7bd688cd 1033{
7d025e08 1034 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 1035 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
3bd712e5 1036 struct intel_panel *panel = &connector->panel;
7d025e08 1037 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
b35684b8 1038 u32 ctl, ctl2;
7bd688cd 1039
b35684b8
JN
1040 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
1041 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 1042 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN
1043 ctl2 &= ~BLM_PWM_ENABLE;
1044 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
1045 }
7bd688cd 1046
b35684b8
JN
1047 ctl = panel->backlight.max << 16;
1048 I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl);
7bd688cd 1049
b35684b8 1050 /* XXX: combine this into above write? */
7d025e08 1051 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
7bd688cd 1052
b35684b8
JN
1053 ctl2 = 0;
1054 if (panel->backlight.active_low_pwm)
1055 ctl2 |= BLM_POLARITY_I965;
1056 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
7bd688cd 1057 POSTING_READ(VLV_BLC_PWM_CTL2(pipe));
b35684b8 1058 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
47356eb6
CW
1059}
1060
7d025e08
ML
1061static void bxt_enable_backlight(const struct intel_crtc_state *crtc_state,
1062 const struct drm_connector_state *conn_state)
0fb890c0 1063{
7d025e08 1064 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 1065 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0fb890c0 1066 struct intel_panel *panel = &connector->panel;
7d025e08 1067 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
022e4e52
SK
1068 u32 pwm_ctl, val;
1069
add03379 1070 /* Controller 1 uses the utility pin. */
022e4e52
SK
1071 if (panel->backlight.controller == 1) {
1072 val = I915_READ(UTIL_PIN_CTL);
1073 if (val & UTIL_PIN_ENABLE) {
1074 DRM_DEBUG_KMS("util pin already enabled\n");
1075 val &= ~UTIL_PIN_ENABLE;
1076 I915_WRITE(UTIL_PIN_CTL, val);
1077 }
0fb890c0 1078
022e4e52
SK
1079 val = 0;
1080 if (panel->backlight.util_pin_active_low)
1081 val |= UTIL_PIN_POLARITY;
1082 I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
1083 UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
1084 }
1085
1086 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
0fb890c0
VK
1087 if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
1088 DRM_DEBUG_KMS("backlight already enabled\n");
1089 pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
022e4e52
SK
1090 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1091 pwm_ctl);
0fb890c0
VK
1092 }
1093
022e4e52
SK
1094 I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
1095 panel->backlight.max);
0fb890c0 1096
7d025e08 1097 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
0fb890c0
VK
1098
1099 pwm_ctl = 0;
1100 if (panel->backlight.active_low_pwm)
1101 pwm_ctl |= BXT_BLC_PWM_POLARITY;
1102
022e4e52
SK
1103 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
1104 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1105 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1106 pwm_ctl | BXT_BLC_PWM_ENABLE);
0fb890c0
VK
1107}
1108
7d025e08
ML
1109static void cnp_enable_backlight(const struct intel_crtc_state *crtc_state,
1110 const struct drm_connector_state *conn_state)
4c9f7086 1111{
7d025e08 1112 struct intel_connector *connector = to_intel_connector(conn_state->connector);
4c9f7086
RV
1113 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1114 struct intel_panel *panel = &connector->panel;
1115 u32 pwm_ctl;
1116
1117 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1118 if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
1119 DRM_DEBUG_KMS("backlight already enabled\n");
1120 pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
1121 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1122 pwm_ctl);
1123 }
1124
1125 I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
1126 panel->backlight.max);
1127
7d025e08 1128 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
4c9f7086
RV
1129
1130 pwm_ctl = 0;
1131 if (panel->backlight.active_low_pwm)
1132 pwm_ctl |= BXT_BLC_PWM_POLARITY;
1133
1134 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
1135 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1136 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1137 pwm_ctl | BXT_BLC_PWM_ENABLE);
1138}
1139
7d025e08
ML
1140static void pwm_enable_backlight(const struct intel_crtc_state *crtc_state,
1141 const struct drm_connector_state *conn_state)
b029e66f 1142{
7d025e08 1143 struct intel_connector *connector = to_intel_connector(conn_state->connector);
b029e66f
SK
1144 struct intel_panel *panel = &connector->panel;
1145
1146 pwm_enable(panel->backlight.pwm);
7d025e08 1147 intel_panel_actually_set_backlight(conn_state, panel->backlight.level);
b029e66f
SK
1148}
1149
b037d58f
ML
1150void intel_panel_enable_backlight(const struct intel_crtc_state *crtc_state,
1151 const struct drm_connector_state *conn_state)
47356eb6 1152{
b037d58f 1153 struct intel_connector *connector = to_intel_connector(conn_state->connector);
e6cb3727 1154 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
58c68779 1155 struct intel_panel *panel = &connector->panel;
b037d58f 1156 enum pipe pipe = to_intel_crtc(crtc_state->base.crtc)->pipe;
8ba2d185 1157
260d8f98 1158 if (!panel->backlight.present)
752aa88a
JB
1159 return;
1160
b037d58f 1161 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
540b5d02 1162
07f11d49 1163 mutex_lock(&dev_priv->backlight_lock);
47356eb6 1164
f91c15e0
JN
1165 WARN_ON(panel->backlight.max == 0);
1166
13f3fbe8 1167 if (panel->backlight.level <= panel->backlight.min) {
f91c15e0 1168 panel->backlight.level = panel->backlight.max;
58c68779
JN
1169 if (panel->backlight.device)
1170 panel->backlight.device->props.brightness =
6dda730e
JN
1171 scale_hw_to_user(connector,
1172 panel->backlight.level,
1173 panel->backlight.device->props.max_brightness);
b6b3ba5b 1174 }
47356eb6 1175
7d025e08 1176 panel->backlight.enable(crtc_state, conn_state);
58c68779 1177 panel->backlight.enabled = true;
ab656bb9
JN
1178 if (panel->backlight.device)
1179 panel->backlight.device->props.power = FB_BLANK_UNBLANK;
8ba2d185 1180
07f11d49 1181 mutex_unlock(&dev_priv->backlight_lock);
47356eb6
CW
1182}
1183
912e8b12 1184#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
db31af1d 1185static int intel_backlight_device_update_status(struct backlight_device *bd)
aaa6fd2a 1186{
752aa88a 1187 struct intel_connector *connector = bl_get_data(bd);
ab656bb9 1188 struct intel_panel *panel = &connector->panel;
752aa88a
JB
1189 struct drm_device *dev = connector->base.dev;
1190
51fd371b 1191 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
540b5d02
CW
1192 DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
1193 bd->props.brightness, bd->props.max_brightness);
7d025e08 1194 intel_panel_set_backlight(connector->base.state, bd->props.brightness,
d6540632 1195 bd->props.max_brightness);
ab656bb9
JN
1196
1197 /*
1198 * Allow flipping bl_power as a sub-state of enabled. Sadly the
1199 * backlight class device does not make it easy to to differentiate
1200 * between callbacks for brightness and bl_power, so our backlight_power
1201 * callback needs to take this into account.
1202 */
1203 if (panel->backlight.enabled) {
5507faeb 1204 if (panel->backlight.power) {
e6755fb7
JN
1205 bool enable = bd->props.power == FB_BLANK_UNBLANK &&
1206 bd->props.brightness != 0;
5507faeb 1207 panel->backlight.power(connector, enable);
ab656bb9
JN
1208 }
1209 } else {
1210 bd->props.power = FB_BLANK_POWERDOWN;
1211 }
1212
51fd371b 1213 drm_modeset_unlock(&dev->mode_config.connection_mutex);
aaa6fd2a
MG
1214 return 0;
1215}
1216
db31af1d 1217static int intel_backlight_device_get_brightness(struct backlight_device *bd)
aaa6fd2a 1218{
752aa88a
JB
1219 struct intel_connector *connector = bl_get_data(bd);
1220 struct drm_device *dev = connector->base.dev;
fac5e23e 1221 struct drm_i915_private *dev_priv = to_i915(dev);
6dda730e 1222 u32 hw_level;
7bd688cd 1223 int ret;
752aa88a 1224
c8c8fb33 1225 intel_runtime_pm_get(dev_priv);
51fd371b 1226 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
6dda730e
JN
1227
1228 hw_level = intel_panel_get_backlight(connector);
1229 ret = scale_hw_to_user(connector, hw_level, bd->props.max_brightness);
1230
51fd371b 1231 drm_modeset_unlock(&dev->mode_config.connection_mutex);
c8c8fb33 1232 intel_runtime_pm_put(dev_priv);
752aa88a 1233
7bd688cd 1234 return ret;
aaa6fd2a
MG
1235}
1236
db31af1d
JN
1237static const struct backlight_ops intel_backlight_device_ops = {
1238 .update_status = intel_backlight_device_update_status,
1239 .get_brightness = intel_backlight_device_get_brightness,
aaa6fd2a
MG
1240};
1241
1ebaa0b9 1242int intel_backlight_device_register(struct intel_connector *connector)
aaa6fd2a 1243{
58c68779 1244 struct intel_panel *panel = &connector->panel;
aaa6fd2a 1245 struct backlight_properties props;
aaa6fd2a 1246
58c68779 1247 if (WARN_ON(panel->backlight.device))
dc652f90
JN
1248 return -ENODEV;
1249
0962c3c9
VS
1250 if (!panel->backlight.present)
1251 return 0;
1252
6dda730e 1253 WARN_ON(panel->backlight.max == 0);
7bd688cd 1254
af437cfd 1255 memset(&props, 0, sizeof(props));
aaa6fd2a 1256 props.type = BACKLIGHT_RAW;
6dda730e
JN
1257
1258 /*
1259 * Note: Everything should work even if the backlight device max
1260 * presented to the userspace is arbitrarily chosen.
1261 */
7bd688cd 1262 props.max_brightness = panel->backlight.max;
6dda730e
JN
1263 props.brightness = scale_hw_to_user(connector,
1264 panel->backlight.level,
1265 props.max_brightness);
58c68779 1266
ab656bb9
JN
1267 if (panel->backlight.enabled)
1268 props.power = FB_BLANK_UNBLANK;
1269 else
1270 props.power = FB_BLANK_POWERDOWN;
1271
58c68779
JN
1272 /*
1273 * Note: using the same name independent of the connector prevents
1274 * registration of multiple backlight devices in the driver.
1275 */
1276 panel->backlight.device =
aaa6fd2a 1277 backlight_device_register("intel_backlight",
db31af1d
JN
1278 connector->base.kdev,
1279 connector,
1280 &intel_backlight_device_ops, &props);
aaa6fd2a 1281
58c68779 1282 if (IS_ERR(panel->backlight.device)) {
aaa6fd2a 1283 DRM_ERROR("Failed to register backlight: %ld\n",
58c68779
JN
1284 PTR_ERR(panel->backlight.device));
1285 panel->backlight.device = NULL;
aaa6fd2a
MG
1286 return -ENODEV;
1287 }
0962c3c9
VS
1288
1289 DRM_DEBUG_KMS("Connector %s backlight sysfs interface registered\n",
1290 connector->base.name);
1291
aaa6fd2a
MG
1292 return 0;
1293}
1294
e63d87c0 1295void intel_backlight_device_unregister(struct intel_connector *connector)
aaa6fd2a 1296{
58c68779
JN
1297 struct intel_panel *panel = &connector->panel;
1298
1299 if (panel->backlight.device) {
1300 backlight_device_unregister(panel->backlight.device);
1301 panel->backlight.device = NULL;
dc652f90 1302 }
aaa6fd2a 1303}
db31af1d
JN
1304#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1305
4c9f7086
RV
1306/*
1307 * CNP: PWM clock frequency is 19.2 MHz or 24 MHz.
1308 * PWM increment = 1
1309 */
1310static u32 cnp_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1311{
1312 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1313
1314 return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz);
1315}
1316
2dd6982e
JN
1317/*
1318 * BXT: PWM clock frequency = 19.2 MHz.
1319 */
1320static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1321{
37f2248e 1322 return DIV_ROUND_CLOSEST(KHz(19200), pwm_freq_hz);
2dd6982e
JN
1323}
1324
f91c15e0 1325/*
aa17cdb4
JN
1326 * SPT: This value represents the period of the PWM stream in clock periods
1327 * multiplied by 16 (default increment) or 128 (alternate increment selected in
1328 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1329 */
1330static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1331{
32b421e7 1332 struct intel_panel *panel = &connector->panel;
e7dc33f3 1333 u32 mul;
aa17cdb4 1334
32b421e7 1335 if (panel->backlight.alternate_pwm_increment)
aa17cdb4
JN
1336 mul = 128;
1337 else
1338 mul = 16;
1339
37f2248e 1340 return DIV_ROUND_CLOSEST(MHz(24), pwm_freq_hz * mul);
aa17cdb4
JN
1341}
1342
1343/*
1344 * LPT: This value represents the period of the PWM stream in clock periods
1345 * multiplied by 128 (default increment) or 16 (alternate increment, selected in
1346 * LPT SOUTH_CHICKEN2 register bit 5).
1347 */
1348static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1349{
e6cb3727 1350 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
32b421e7 1351 struct intel_panel *panel = &connector->panel;
aa17cdb4
JN
1352 u32 mul, clock;
1353
32b421e7 1354 if (panel->backlight.alternate_pwm_increment)
aa17cdb4
JN
1355 mul = 16;
1356 else
1357 mul = 128;
1358
56f5f700 1359 if (HAS_PCH_LPT_H(dev_priv))
aa17cdb4
JN
1360 clock = MHz(135); /* LPT:H */
1361 else
1362 clock = MHz(24); /* LPT:LP */
1363
37f2248e 1364 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
aa17cdb4
JN
1365}
1366
1367/*
1368 * ILK/SNB/IVB: This value represents the period of the PWM stream in PCH
1369 * display raw clocks multiplied by 128.
1370 */
1371static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1372{
e7dc33f3 1373 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
aa17cdb4 1374
37f2248e 1375 return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128);
aa17cdb4
JN
1376}
1377
1378/*
1379 * Gen2: This field determines the number of time base events (display core
1380 * clock frequency/32) in total for a complete cycle of modulated backlight
1381 * control.
f91c15e0 1382 *
aa17cdb4
JN
1383 * Gen3: A time base event equals the display core clock ([DevPNV] HRAW clock)
1384 * divided by 32.
1385 */
1386static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1387{
e7dc33f3 1388 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
aa17cdb4
JN
1389 int clock;
1390
e7dc33f3
VS
1391 if (IS_PINEVIEW(dev_priv))
1392 clock = KHz(dev_priv->rawclk_freq);
aa17cdb4 1393 else
49cd97a3 1394 clock = KHz(dev_priv->cdclk.hw.cdclk);
aa17cdb4 1395
37f2248e 1396 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32);
aa17cdb4
JN
1397}
1398
1399/*
1400 * Gen4: This value represents the period of the PWM stream in display core
83d83392
VS
1401 * clocks ([DevCTG] HRAW clocks) multiplied by 128.
1402 *
aa17cdb4
JN
1403 */
1404static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1405{
3bed7f4d 1406 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
83d83392
VS
1407 int clock;
1408
1409 if (IS_G4X(dev_priv))
e7dc33f3 1410 clock = KHz(dev_priv->rawclk_freq);
83d83392 1411 else
49cd97a3 1412 clock = KHz(dev_priv->cdclk.hw.cdclk);
aa17cdb4 1413
37f2248e 1414 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128);
aa17cdb4
JN
1415}
1416
1417/*
1418 * VLV: This value represents the period of the PWM stream in display core
1419 * clocks ([DevCTG] 200MHz HRAW clocks) multiplied by 128 or 25MHz S0IX clocks
1420 * multiplied by 16. CHV uses a 19.2MHz S0IX clock.
1421 */
1422static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1423{
e7dc33f3
VS
1424 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1425 int mul, clock;
aa17cdb4
JN
1426
1427 if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
e7dc33f3
VS
1428 if (IS_CHERRYVIEW(dev_priv))
1429 clock = KHz(19200);
aa17cdb4 1430 else
e7dc33f3
VS
1431 clock = MHz(25);
1432 mul = 16;
aa17cdb4 1433 } else {
e7dc33f3
VS
1434 clock = KHz(dev_priv->rawclk_freq);
1435 mul = 128;
aa17cdb4 1436 }
e7dc33f3 1437
37f2248e 1438 return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul);
aa17cdb4
JN
1439}
1440
1441static u32 get_backlight_max_vbt(struct intel_connector *connector)
1442{
e6cb3727 1443 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
5507faeb 1444 struct intel_panel *panel = &connector->panel;
aa17cdb4
JN
1445 u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
1446 u32 pwm;
1447
5075222b
JN
1448 if (!panel->backlight.hz_to_pwm) {
1449 DRM_DEBUG_KMS("backlight frequency conversion not supported\n");
aa17cdb4
JN
1450 return 0;
1451 }
1452
5075222b
JN
1453 if (pwm_freq_hz) {
1454 DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n",
1455 pwm_freq_hz);
1456 } else {
1457 pwm_freq_hz = 200;
1458 DRM_DEBUG_KMS("default backlight frequency %u Hz\n",
1459 pwm_freq_hz);
aa17cdb4
JN
1460 }
1461
5507faeb 1462 pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz);
aa17cdb4
JN
1463 if (!pwm) {
1464 DRM_DEBUG_KMS("backlight frequency conversion failed\n");
1465 return 0;
1466 }
1467
aa17cdb4
JN
1468 return pwm;
1469}
1470
1471/*
1472 * Note: The setup hooks can't assume pipe is set!
f91c15e0 1473 */
6dda730e
JN
1474static u32 get_backlight_min_vbt(struct intel_connector *connector)
1475{
e6cb3727 1476 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
6dda730e 1477 struct intel_panel *panel = &connector->panel;
e1c412e7 1478 int min;
6dda730e
JN
1479
1480 WARN_ON(panel->backlight.max == 0);
1481
e1c412e7
JN
1482 /*
1483 * XXX: If the vbt value is 255, it makes min equal to max, which leads
1484 * to problems. There are such machines out there. Either our
1485 * interpretation is wrong or the vbt has bogus data. Or both. Safeguard
1486 * against this by letting the minimum be at most (arbitrarily chosen)
1487 * 25% of the max.
1488 */
1489 min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
1490 if (min != dev_priv->vbt.backlight.min_brightness) {
1491 DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
1492 dev_priv->vbt.backlight.min_brightness, min);
1493 }
1494
6dda730e 1495 /* vbt value is a coefficient in range [0..255] */
e1c412e7 1496 return scale(min, 0, 255, 0, panel->backlight.max);
6dda730e
JN
1497}
1498
437b15b8 1499static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused)
aaa6fd2a 1500{
e6cb3727 1501 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
96ab4c70
DV
1502 struct intel_panel *panel = &connector->panel;
1503 u32 pch_ctl1, pch_ctl2, val;
32b421e7
JN
1504 bool alt;
1505
1506 if (HAS_PCH_LPT(dev_priv))
1507 alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY;
1508 else
1509 alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY;
1510 panel->backlight.alternate_pwm_increment = alt;
96ab4c70
DV
1511
1512 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1513 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1514
1515 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1516 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4
JN
1517
1518 if (!panel->backlight.max)
1519 panel->backlight.max = get_backlight_max_vbt(connector);
1520
96ab4c70
DV
1521 if (!panel->backlight.max)
1522 return -ENODEV;
1523
6dda730e
JN
1524 panel->backlight.min = get_backlight_min_vbt(connector);
1525
437b15b8 1526 val = lpt_get_backlight(connector);
46e69f39
JN
1527 val = intel_panel_compute_brightness(connector, val);
1528 panel->backlight.level = clamp(val, panel->backlight.min,
1529 panel->backlight.max);
96ab4c70 1530
46e69f39 1531 panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE;
96ab4c70
DV
1532
1533 return 0;
1534}
1535
6517d273 1536static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1537{
e6cb3727 1538 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1539 struct intel_panel *panel = &connector->panel;
636baebf 1540 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
7bd688cd 1541
636baebf
JN
1542 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1543 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1544
1545 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1546 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4
JN
1547
1548 if (!panel->backlight.max)
1549 panel->backlight.max = get_backlight_max_vbt(connector);
1550
7bd688cd
JN
1551 if (!panel->backlight.max)
1552 return -ENODEV;
1553
6dda730e
JN
1554 panel->backlight.min = get_backlight_min_vbt(connector);
1555
7bd688cd 1556 val = pch_get_backlight(connector);
46e69f39
JN
1557 val = intel_panel_compute_brightness(connector, val);
1558 panel->backlight.level = clamp(val, panel->backlight.min,
1559 panel->backlight.max);
7bd688cd 1560
636baebf
JN
1561 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
1562 panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) &&
46e69f39 1563 (pch_ctl1 & BLM_PCH_PWM_ENABLE);
636baebf 1564
7bd688cd
JN
1565 return 0;
1566}
1567
6517d273 1568static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1569{
e6cb3727 1570 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1571 struct intel_panel *panel = &connector->panel;
636baebf
JN
1572 u32 ctl, val;
1573
1574 ctl = I915_READ(BLC_PWM_CTL);
1575
e6cb3727 1576 if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
636baebf
JN
1577 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
1578
e6cb3727 1579 if (IS_PINEVIEW(dev_priv))
636baebf
JN
1580 panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV;
1581
1582 panel->backlight.max = ctl >> 17;
aa17cdb4
JN
1583
1584 if (!panel->backlight.max) {
1585 panel->backlight.max = get_backlight_max_vbt(connector);
1586 panel->backlight.max >>= 1;
1587 }
7bd688cd 1588
7bd688cd
JN
1589 if (!panel->backlight.max)
1590 return -ENODEV;
1591
aa17cdb4
JN
1592 if (panel->backlight.combination_mode)
1593 panel->backlight.max *= 0xff;
1594
6dda730e
JN
1595 panel->backlight.min = get_backlight_min_vbt(connector);
1596
7bd688cd 1597 val = i9xx_get_backlight(connector);
46e69f39
JN
1598 val = intel_panel_compute_brightness(connector, val);
1599 panel->backlight.level = clamp(val, panel->backlight.min,
1600 panel->backlight.max);
7bd688cd 1601
46e69f39 1602 panel->backlight.enabled = val != 0;
636baebf 1603
7bd688cd
JN
1604 return 0;
1605}
1606
6517d273 1607static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1608{
e6cb3727 1609 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1610 struct intel_panel *panel = &connector->panel;
636baebf
JN
1611 u32 ctl, ctl2, val;
1612
1613 ctl2 = I915_READ(BLC_PWM_CTL2);
1614 panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE;
1615 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1616
1617 ctl = I915_READ(BLC_PWM_CTL);
1618 panel->backlight.max = ctl >> 16;
aa17cdb4
JN
1619
1620 if (!panel->backlight.max)
1621 panel->backlight.max = get_backlight_max_vbt(connector);
7bd688cd 1622
7bd688cd
JN
1623 if (!panel->backlight.max)
1624 return -ENODEV;
1625
aa17cdb4
JN
1626 if (panel->backlight.combination_mode)
1627 panel->backlight.max *= 0xff;
1628
6dda730e
JN
1629 panel->backlight.min = get_backlight_min_vbt(connector);
1630
7bd688cd 1631 val = i9xx_get_backlight(connector);
46e69f39
JN
1632 val = intel_panel_compute_brightness(connector, val);
1633 panel->backlight.level = clamp(val, panel->backlight.min,
1634 panel->backlight.max);
7bd688cd 1635
46e69f39 1636 panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE;
636baebf 1637
7bd688cd
JN
1638 return 0;
1639}
1640
6517d273 1641static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe)
7bd688cd 1642{
e6cb3727 1643 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1644 struct intel_panel *panel = &connector->panel;
636baebf 1645 u32 ctl, ctl2, val;
7bd688cd 1646
6517d273
VS
1647 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
1648 return -ENODEV;
1649
1650 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
636baebf
JN
1651 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1652
6517d273 1653 ctl = I915_READ(VLV_BLC_PWM_CTL(pipe));
636baebf 1654 panel->backlight.max = ctl >> 16;
aa17cdb4
JN
1655
1656 if (!panel->backlight.max)
1657 panel->backlight.max = get_backlight_max_vbt(connector);
1658
7bd688cd
JN
1659 if (!panel->backlight.max)
1660 return -ENODEV;
1661
6dda730e
JN
1662 panel->backlight.min = get_backlight_min_vbt(connector);
1663
e6cb3727 1664 val = _vlv_get_backlight(dev_priv, pipe);
46e69f39
JN
1665 val = intel_panel_compute_brightness(connector, val);
1666 panel->backlight.level = clamp(val, panel->backlight.min,
1667 panel->backlight.max);
7bd688cd 1668
46e69f39 1669 panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE;
636baebf 1670
7bd688cd
JN
1671 return 0;
1672}
1673
0fb890c0
VK
1674static int
1675bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
1676{
e6cb3727 1677 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
0fb890c0
VK
1678 struct intel_panel *panel = &connector->panel;
1679 u32 pwm_ctl, val;
1680
add03379 1681 panel->backlight.controller = dev_priv->vbt.backlight.controller;
0fb890c0 1682
022e4e52
SK
1683 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1684
add03379 1685 /* Controller 1 uses the utility pin. */
022e4e52
SK
1686 if (panel->backlight.controller == 1) {
1687 val = I915_READ(UTIL_PIN_CTL);
1688 panel->backlight.util_pin_active_low =
1689 val & UTIL_PIN_POLARITY;
1690 }
1691
1692 panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
1693 panel->backlight.max =
1694 I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
aa17cdb4
JN
1695
1696 if (!panel->backlight.max)
1697 panel->backlight.max = get_backlight_max_vbt(connector);
1698
0fb890c0
VK
1699 if (!panel->backlight.max)
1700 return -ENODEV;
1701
c3881128
LS
1702 panel->backlight.min = get_backlight_min_vbt(connector);
1703
0fb890c0 1704 val = bxt_get_backlight(connector);
46e69f39
JN
1705 val = intel_panel_compute_brightness(connector, val);
1706 panel->backlight.level = clamp(val, panel->backlight.min,
1707 panel->backlight.max);
0fb890c0 1708
46e69f39 1709 panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
0fb890c0
VK
1710
1711 return 0;
1712}
1713
4c9f7086
RV
1714static int
1715cnp_setup_backlight(struct intel_connector *connector, enum pipe unused)
1716{
1717 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
1718 struct intel_panel *panel = &connector->panel;
1719 u32 pwm_ctl, val;
1720
1721 /*
1722 * CNP has the BXT implementation of backlight, but with only
1723 * one controller. Future platforms could have multiple controllers
1724 * so let's make this extensible and prepared for the future.
1725 */
1726 panel->backlight.controller = 0;
1727
1728 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1729
1730 panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
1731 panel->backlight.max =
1732 I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
1733
1734 if (!panel->backlight.max)
1735 panel->backlight.max = get_backlight_max_vbt(connector);
1736
1737 if (!panel->backlight.max)
1738 return -ENODEV;
1739
f44e354f
LS
1740 panel->backlight.min = get_backlight_min_vbt(connector);
1741
4c9f7086
RV
1742 val = bxt_get_backlight(connector);
1743 val = intel_panel_compute_brightness(connector, val);
1744 panel->backlight.level = clamp(val, panel->backlight.min,
1745 panel->backlight.max);
1746
1747 panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE;
1748
1749 return 0;
1750}
1751
b029e66f
SK
1752static int pwm_setup_backlight(struct intel_connector *connector,
1753 enum pipe pipe)
1754{
1755 struct drm_device *dev = connector->base.dev;
1756 struct intel_panel *panel = &connector->panel;
1757 int retval;
1758
1759 /* Get the PWM chip for backlight control */
1760 panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
1761 if (IS_ERR(panel->backlight.pwm)) {
1762 DRM_ERROR("Failed to own the pwm chip\n");
1763 panel->backlight.pwm = NULL;
1764 return -ENODEV;
1765 }
1766
2347aa7c
BB
1767 /*
1768 * FIXME: pwm_apply_args() should be removed when switching to
1769 * the atomic PWM API.
1770 */
1771 pwm_apply_args(panel->backlight.pwm);
1772
b029e66f
SK
1773 retval = pwm_config(panel->backlight.pwm, CRC_PMIC_PWM_PERIOD_NS,
1774 CRC_PMIC_PWM_PERIOD_NS);
1775 if (retval < 0) {
1776 DRM_ERROR("Failed to configure the pwm chip\n");
1777 pwm_put(panel->backlight.pwm);
1778 panel->backlight.pwm = NULL;
1779 return retval;
1780 }
1781
1782 panel->backlight.min = 0; /* 0% */
1783 panel->backlight.max = 100; /* 100% */
1784 panel->backlight.level = DIV_ROUND_UP(
1785 pwm_get_duty_cycle(panel->backlight.pwm) * 100,
1786 CRC_PMIC_PWM_PERIOD_NS);
1787 panel->backlight.enabled = panel->backlight.level != 0;
1788
1789 return 0;
1790}
1791
6517d273 1792int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe)
aaa6fd2a 1793{
e6cb3727 1794 struct drm_i915_private *dev_priv = to_i915(connector->dev);
db31af1d 1795 struct intel_connector *intel_connector = to_intel_connector(connector);
58c68779 1796 struct intel_panel *panel = &intel_connector->panel;
7bd688cd 1797 int ret;
db31af1d 1798
c675949e 1799 if (!dev_priv->vbt.backlight.present) {
9c72cc6f
SD
1800 if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
1801 DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
1802 } else {
1803 DRM_DEBUG_KMS("no backlight present per VBT\n");
1804 return 0;
1805 }
c675949e
JN
1806 }
1807
5507faeb
JN
1808 /* ensure intel_panel has been initialized first */
1809 if (WARN_ON(!panel->backlight.setup))
1810 return -ENODEV;
1811
7bd688cd 1812 /* set level and max in panel struct */
07f11d49 1813 mutex_lock(&dev_priv->backlight_lock);
5507faeb 1814 ret = panel->backlight.setup(intel_connector, pipe);
07f11d49 1815 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd
JN
1816
1817 if (ret) {
1818 DRM_DEBUG_KMS("failed to setup backlight for connector %s\n",
c23cc417 1819 connector->name);
7bd688cd
JN
1820 return ret;
1821 }
db31af1d 1822
c91c9f32
JN
1823 panel->backlight.present = true;
1824
0962c3c9
VS
1825 DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n",
1826 connector->name,
08c4d7fc 1827 enableddisabled(panel->backlight.enabled),
0962c3c9 1828 panel->backlight.level, panel->backlight.max);
c445b3b1 1829
aaa6fd2a
MG
1830 return 0;
1831}
1832
db31af1d 1833void intel_panel_destroy_backlight(struct drm_connector *connector)
aaa6fd2a 1834{
db31af1d 1835 struct intel_connector *intel_connector = to_intel_connector(connector);
c91c9f32 1836 struct intel_panel *panel = &intel_connector->panel;
db31af1d 1837
b029e66f
SK
1838 /* dispose of the pwm */
1839 if (panel->backlight.pwm)
1840 pwm_put(panel->backlight.pwm);
1841
c91c9f32 1842 panel->backlight.present = false;
aaa6fd2a 1843}
1d508706 1844
7bd688cd 1845/* Set up chip specific backlight functions */
5507faeb
JN
1846static void
1847intel_panel_init_backlight_funcs(struct intel_panel *panel)
7bd688cd 1848{
e6cb3727 1849 struct intel_connector *connector =
5507faeb 1850 container_of(panel, struct intel_connector, panel);
e6cb3727 1851 struct drm_i915_private *dev_priv = to_i915(connector->base.dev);
7bd688cd 1852
e7156c83
YA
1853 if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP &&
1854 intel_dp_aux_init_backlight_funcs(connector) == 0)
1855 return;
1856
90198355
JN
1857 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI &&
1858 intel_dsi_dcs_init_backlight_funcs(connector) == 0)
1859 return;
1860
cc3f90f0 1861 if (IS_GEN9_LP(dev_priv)) {
5507faeb
JN
1862 panel->backlight.setup = bxt_setup_backlight;
1863 panel->backlight.enable = bxt_enable_backlight;
1864 panel->backlight.disable = bxt_disable_backlight;
1865 panel->backlight.set = bxt_set_backlight;
1866 panel->backlight.get = bxt_get_backlight;
2dd6982e 1867 panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
4c9f7086
RV
1868 } else if (HAS_PCH_CNP(dev_priv)) {
1869 panel->backlight.setup = cnp_setup_backlight;
1870 panel->backlight.enable = cnp_enable_backlight;
1871 panel->backlight.disable = cnp_disable_backlight;
1872 panel->backlight.set = bxt_set_backlight;
1873 panel->backlight.get = bxt_get_backlight;
1874 panel->backlight.hz_to_pwm = cnp_hz_to_pwm;
22dea0be
RV
1875 } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) ||
1876 HAS_PCH_KBP(dev_priv)) {
5507faeb
JN
1877 panel->backlight.setup = lpt_setup_backlight;
1878 panel->backlight.enable = lpt_enable_backlight;
1879 panel->backlight.disable = lpt_disable_backlight;
1880 panel->backlight.set = lpt_set_backlight;
1881 panel->backlight.get = lpt_get_backlight;
e6cb3727 1882 if (HAS_PCH_LPT(dev_priv))
5507faeb 1883 panel->backlight.hz_to_pwm = lpt_hz_to_pwm;
aa17cdb4 1884 else
5507faeb 1885 panel->backlight.hz_to_pwm = spt_hz_to_pwm;
e6cb3727 1886 } else if (HAS_PCH_SPLIT(dev_priv)) {
5507faeb
JN
1887 panel->backlight.setup = pch_setup_backlight;
1888 panel->backlight.enable = pch_enable_backlight;
1889 panel->backlight.disable = pch_disable_backlight;
1890 panel->backlight.set = pch_set_backlight;
1891 panel->backlight.get = pch_get_backlight;
1892 panel->backlight.hz_to_pwm = pch_hz_to_pwm;
e6cb3727 1893 } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
92c4565e 1894 if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) {
5507faeb
JN
1895 panel->backlight.setup = pwm_setup_backlight;
1896 panel->backlight.enable = pwm_enable_backlight;
1897 panel->backlight.disable = pwm_disable_backlight;
1898 panel->backlight.set = pwm_set_backlight;
1899 panel->backlight.get = pwm_get_backlight;
b029e66f 1900 } else {
5507faeb
JN
1901 panel->backlight.setup = vlv_setup_backlight;
1902 panel->backlight.enable = vlv_enable_backlight;
1903 panel->backlight.disable = vlv_disable_backlight;
1904 panel->backlight.set = vlv_set_backlight;
1905 panel->backlight.get = vlv_get_backlight;
1906 panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
b029e66f 1907 }
e6cb3727 1908 } else if (IS_GEN4(dev_priv)) {
5507faeb
JN
1909 panel->backlight.setup = i965_setup_backlight;
1910 panel->backlight.enable = i965_enable_backlight;
1911 panel->backlight.disable = i965_disable_backlight;
1912 panel->backlight.set = i9xx_set_backlight;
1913 panel->backlight.get = i9xx_get_backlight;
1914 panel->backlight.hz_to_pwm = i965_hz_to_pwm;
7bd688cd 1915 } else {
5507faeb
JN
1916 panel->backlight.setup = i9xx_setup_backlight;
1917 panel->backlight.enable = i9xx_enable_backlight;
1918 panel->backlight.disable = i9xx_disable_backlight;
1919 panel->backlight.set = i9xx_set_backlight;
1920 panel->backlight.get = i9xx_get_backlight;
1921 panel->backlight.hz_to_pwm = i9xx_hz_to_pwm;
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1922 }
1923}
1924
dd06f90e 1925int intel_panel_init(struct intel_panel *panel,
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1926 struct drm_display_mode *fixed_mode,
1927 struct drm_display_mode *downclock_mode)
1d508706 1928{
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1929 intel_panel_init_backlight_funcs(panel);
1930
dd06f90e 1931 panel->fixed_mode = fixed_mode;
4b6ed685 1932 panel->downclock_mode = downclock_mode;
dd06f90e 1933
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1934 return 0;
1935}
1936
1937void intel_panel_fini(struct intel_panel *panel)
1938{
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1939 struct intel_connector *intel_connector =
1940 container_of(panel, struct intel_connector, panel);
1941
1942 if (panel->fixed_mode)
1943 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
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1944
1945 if (panel->downclock_mode)
1946 drm_mode_destroy(intel_connector->base.dev,
1947 panel->downclock_mode);
1d508706 1948}