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drm/i915: Add explicit pipe src size to pipe config
[mirror_ubuntu-focal-kernel.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW		 1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP		 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
7bd90909 33#include <linux/moduleparam.h>
1d8e1c75
CW		 34#include "intel_drv.h"
35
ba3820ad
TI		 36#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
37
1d8e1c75 38void
4c6df4b4 39intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW		 40 struct drm_display_mode *adjusted_mode)
41{
4c6df4b4 42 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID		 43
44 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW		 45}
46
47/* adjusted_mode has been preset to be the panel's fixed mode */
48void
b074cec8
JB		 49intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
50 struct intel_crtc_config *pipe_config,
51 int fitting_mode)
1d8e1c75 52{
37327abd 53 struct drm_display_mode *adjusted_mode;
1d8e1c75
CW		 54 int x, y, width, height;
55
b074cec8
JB		 56 adjusted_mode = &pipe_config->adjusted_mode;
57
1d8e1c75
CW		 58 x = y = width = height = 0;
59
60 /* Native modes don't need fitting */
37327abd
VS		 61 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
62 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
1d8e1c75
CW		 63 goto done;
64
65 switch (fitting_mode) {
66 case DRM_MODE_SCALE_CENTER:
37327abd
VS		 67 width = pipe_config->pipe_src_w;
68 height = pipe_config->pipe_src_h;
1d8e1c75
CW		 69 x = (adjusted_mode->hdisplay - width + 1)/2;
70 y = (adjusted_mode->vdisplay - height + 1)/2;
71 break;
72
73 case DRM_MODE_SCALE_ASPECT:
74 /* Scale but preserve the aspect ratio */
75 {
37327abd
VS		 76 u32 scaled_width = adjusted_mode->hdisplay * pipe_config->pipe_src_h;
77 u32 scaled_height = pipe_config->pipe_src_w * adjusted_mode->vdisplay;
1d8e1c75 78 if (scaled_width > scaled_height) { /* pillar */
37327abd 79 width = scaled_height / pipe_config->pipe_src_h;
302983e9 80 if (width & 1)
0206e353 81 width++;
1d8e1c75
CW		 82 x = (adjusted_mode->hdisplay - width + 1) / 2;
83 y = 0;
84 height = adjusted_mode->vdisplay;
85 } else if (scaled_width < scaled_height) { /* letter */
37327abd 86 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ		 87 if (height & 1)
88 height++;
1d8e1c75
CW		 89 y = (adjusted_mode->vdisplay - height + 1) / 2;
90 x = 0;
91 width = adjusted_mode->hdisplay;
92 } else {
93 x = y = 0;
94 width = adjusted_mode->hdisplay;
95 height = adjusted_mode->vdisplay;
96 }
97 }
98 break;
99
1d8e1c75
CW		 100 case DRM_MODE_SCALE_FULLSCREEN:
101 x = y = 0;
102 width = adjusted_mode->hdisplay;
103 height = adjusted_mode->vdisplay;
104 break;
ab3e67f4
JB		 105
106 default:
107 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
108 return;
1d8e1c75
CW		 109 }
110
111done:
b074cec8
JB		 112 pipe_config->pch_pfit.pos = (x << 16) | y;
113 pipe_config->pch_pfit.size = (width << 16) | height;
1d8e1c75 114}
a9573556 115
2dd24552
JB		 116static void
117centre_horizontally(struct drm_display_mode *mode,
118 int width)
119{
120 u32 border, sync_pos, blank_width, sync_width;
121
122 /* keep the hsync and hblank widths constant */
123 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
124 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
125 sync_pos = (blank_width - sync_width + 1) / 2;
126
127 border = (mode->hdisplay - width + 1) / 2;
128 border += border & 1; /* make the border even */
129
130 mode->crtc_hdisplay = width;
131 mode->crtc_hblank_start = width + border;
132 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
133
134 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
135 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
136}
137
138static void
139centre_vertically(struct drm_display_mode *mode,
140 int height)
141{
142 u32 border, sync_pos, blank_width, sync_width;
143
144 /* keep the vsync and vblank widths constant */
145 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
146 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
147 sync_pos = (blank_width - sync_width + 1) / 2;
148
149 border = (mode->vdisplay - height + 1) / 2;
150
151 mode->crtc_vdisplay = height;
152 mode->crtc_vblank_start = height + border;
153 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
154
155 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
156 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
157}
158
159static inline u32 panel_fitter_scaling(u32 source, u32 target)
160{
161 /*
162 * Floating point operation is not supported. So the FACTOR
163 * is defined, which can avoid the floating point computation
164 * when calculating the panel ratio.
165 */
166#define ACCURACY 12
167#define FACTOR (1 << ACCURACY)
168 u32 ratio = source * FACTOR / target;
169 return (FACTOR * ratio + FACTOR/2) / FACTOR;
170}
171
172void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
173 struct intel_crtc_config *pipe_config,
174 int fitting_mode)
175{
176 struct drm_device *dev = intel_crtc->base.dev;
2dd24552 177 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
37327abd 178 struct drm_display_mode *adjusted_mode;
2dd24552 179
2dd24552
JB		 180 adjusted_mode = &pipe_config->adjusted_mode;
181
182 /* Native modes don't need fitting */
37327abd
VS		 183 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
184 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
2dd24552
JB		 185 goto out;
186
187 switch (fitting_mode) {
188 case DRM_MODE_SCALE_CENTER:
189 /*
190 * For centered modes, we have to calculate border widths &
191 * heights and modify the values programmed into the CRTC.
192 */
37327abd
VS		 193 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
194 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB		 195 border = LVDS_BORDER_ENABLE;
196 break;
197 case DRM_MODE_SCALE_ASPECT:
198 /* Scale but preserve the aspect ratio */
199 if (INTEL_INFO(dev)->gen >= 4) {
200 u32 scaled_width = adjusted_mode->hdisplay *
37327abd
VS		 201 pipe_config->pipe_src_h;
202 u32 scaled_height = pipe_config->pipe_src_w *
2dd24552
JB		 203 adjusted_mode->vdisplay;
204
205 /* 965+ is easy, it does everything in hw */
206 if (scaled_width > scaled_height)
207 pfit_control |= PFIT_ENABLE |
208 PFIT_SCALING_PILLAR;
209 else if (scaled_width < scaled_height)
210 pfit_control |= PFIT_ENABLE |
211 PFIT_SCALING_LETTER;
37327abd 212 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
2dd24552
JB		 213 pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
214 } else {
215 u32 scaled_width = adjusted_mode->hdisplay *
37327abd
VS		 216 pipe_config->pipe_src_h;
217 u32 scaled_height = pipe_config->pipe_src_w *
2dd24552
JB		 218 adjusted_mode->vdisplay;
219 /*
220 * For earlier chips we have to calculate the scaling
221 * ratio by hand and program it into the
222 * PFIT_PGM_RATIO register
223 */
224 if (scaled_width > scaled_height) { /* pillar */
225 centre_horizontally(adjusted_mode,
226 scaled_height /
37327abd 227 pipe_config->pipe_src_h);
2dd24552
JB		 228
229 border = LVDS_BORDER_ENABLE;
37327abd
VS		 230 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
231 u32 bits = panel_fitter_scaling(pipe_config->pipe_src_h, adjusted_mode->vdisplay);
2dd24552
JB		 232 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
233 bits << PFIT_VERT_SCALE_SHIFT);
234 pfit_control |= (PFIT_ENABLE |
235 VERT_INTERP_BILINEAR |
236 HORIZ_INTERP_BILINEAR);
237 }
238 } else if (scaled_width < scaled_height) { /* letter */
239 centre_vertically(adjusted_mode,
240 scaled_width /
37327abd 241 pipe_config->pipe_src_w);
2dd24552
JB		 242
243 border = LVDS_BORDER_ENABLE;
37327abd
VS		 244 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
245 u32 bits = panel_fitter_scaling(pipe_config->pipe_src_w, adjusted_mode->hdisplay);
2dd24552
JB		 246 pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
247 bits << PFIT_VERT_SCALE_SHIFT);
248 pfit_control |= (PFIT_ENABLE |
249 VERT_INTERP_BILINEAR |
250 HORIZ_INTERP_BILINEAR);
251 }
252 } else {
253 /* Aspects match, Let hw scale both directions */
254 pfit_control |= (PFIT_ENABLE |
255 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
256 VERT_INTERP_BILINEAR |
257 HORIZ_INTERP_BILINEAR);
258 }
259 }
260 break;
2dd24552
JB		 261 case DRM_MODE_SCALE_FULLSCREEN:
262 /*
263 * Full scaling, even if it changes the aspect ratio.
264 * Fortunately this is all done for us in hw.
265 */
37327abd
VS		 266 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
267 pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
2dd24552
JB		 268 pfit_control |= PFIT_ENABLE;
269 if (INTEL_INFO(dev)->gen >= 4)
270 pfit_control |= PFIT_SCALING_AUTO;
271 else
272 pfit_control |= (VERT_AUTO_SCALE |
273 VERT_INTERP_BILINEAR |
274 HORIZ_AUTO_SCALE |
275 HORIZ_INTERP_BILINEAR);
276 }
277 break;
ab3e67f4
JB		 278 default:
279 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
280 return;
2dd24552
JB		 281 }
282
283 /* 965+ wants fuzzy fitting */
284 /* FIXME: handle multiple panels by failing gracefully */
285 if (INTEL_INFO(dev)->gen >= 4)
286 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
287 PFIT_FILTER_FUZZY);
288
289out:
290 if ((pfit_control & PFIT_ENABLE) == 0) {
291 pfit_control = 0;
292 pfit_pgm_ratios = 0;
293 }
294
295 /* Make sure pre-965 set dither correctly for 18bpp panels. */
296 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
297 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
298
2deefda5
DV		 299 pipe_config->gmch_pfit.control = pfit_control;
300 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 301 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB		 302}
303
ba3820ad
TI		 304static int is_backlight_combination_mode(struct drm_device *dev)
305{
306 struct drm_i915_private *dev_priv = dev->dev_private;
307
308 if (INTEL_INFO(dev)->gen >= 4)
309 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
310
311 if (IS_GEN2(dev))
312 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
313
314 return 0;
315}
316
d6540632
JN		 317/* XXX: query mode clock or hardware clock and program max PWM appropriately
318 * when it's 0.
319 */
bfd7590d 320static u32 i915_read_blc_pwm_ctl(struct drm_device *dev)
0b0b053a 321{
bfd7590d 322 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a
CW		 323 u32 val;
324
df0a6797 325 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
8ba2d185 326
0b0b053a
CW		 327 /* Restore the CTL value if it lost, e.g. GPU reset */
328
329 if (HAS_PCH_SPLIT(dev_priv->dev)) {
330 val = I915_READ(BLC_PWM_PCH_CTL2);
f4c956ad
DV		 331 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
332 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
0b0b053a 333 } else if (val == 0) {
f4c956ad 334 val = dev_priv->regfile.saveBLC_PWM_CTL2;
bfd7590d 335 I915_WRITE(BLC_PWM_PCH_CTL2, val);
0b0b053a
CW		 336 }
337 } else {
338 val = I915_READ(BLC_PWM_CTL);
f4c956ad
DV		 339 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
340 dev_priv->regfile.saveBLC_PWM_CTL = val;
bfd7590d
JN		 341 if (INTEL_INFO(dev)->gen >= 4)
342 dev_priv->regfile.saveBLC_PWM_CTL2 =
343 I915_READ(BLC_PWM_CTL2);
0b0b053a 344 } else if (val == 0) {
f4c956ad 345 val = dev_priv->regfile.saveBLC_PWM_CTL;
bfd7590d
JN		 346 I915_WRITE(BLC_PWM_CTL, val);
347 if (INTEL_INFO(dev)->gen >= 4)
348 I915_WRITE(BLC_PWM_CTL2,
349 dev_priv->regfile.saveBLC_PWM_CTL2);
0b0b053a
CW		 350 }
351 }
352
353 return val;
354}
355
d6540632 356static u32 intel_panel_get_max_backlight(struct drm_device *dev)
a9573556 357{
a9573556
CW		 358 u32 max;
359
bfd7590d 360 max = i915_read_blc_pwm_ctl(dev);
0b0b053a 361
a9573556 362 if (HAS_PCH_SPLIT(dev)) {
0b0b053a 363 max >>= 16;
a9573556 364 } else {
ca88479c 365 if (INTEL_INFO(dev)->gen < 4)
a9573556 366 max >>= 17;
ca88479c 367 else
a9573556 368 max >>= 16;
ba3820ad
TI		 369
370 if (is_backlight_combination_mode(dev))
371 max *= 0xff;
a9573556
CW		 372 }
373
a9573556 374 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
d6540632 375
a9573556
CW		 376 return max;
377}
378
4dca20ef
CE		 379static int i915_panel_invert_brightness;
380MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
381 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
7bd90909
CE		 382 "report PCI device ID, subsystem vendor and subsystem device ID "
383 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
384 "It will then be included in an upcoming module version.");
4dca20ef 385module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
7bd90909
CE		 386static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val)
387{
4dca20ef
CE		 388 struct drm_i915_private *dev_priv = dev->dev_private;
389
390 if (i915_panel_invert_brightness < 0)
391 return val;
392
393 if (i915_panel_invert_brightness > 0 ||
d6540632
JN		 394 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
395 u32 max = intel_panel_get_max_backlight(dev);
396 if (max)
397 return max - val;
398 }
7bd90909
CE		 399
400 return val;
401}
402
faea35dd 403static u32 intel_panel_get_backlight(struct drm_device *dev)
a9573556
CW		 404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406 u32 val;
8ba2d185
JN		 407 unsigned long flags;
408
409 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
a9573556
CW		 410
411 if (HAS_PCH_SPLIT(dev)) {
412 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
413 } else {
414 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
ca88479c 415 if (INTEL_INFO(dev)->gen < 4)
a9573556 416 val >>= 1;
ba3820ad 417
0206e353 418 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI		 419 u8 lbpc;
420
ba3820ad
TI		 421 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
422 val *= lbpc;
423 }
a9573556
CW		 424 }
425
7bd90909 426 val = intel_panel_compute_brightness(dev, val);
8ba2d185
JN		 427
428 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
429
a9573556
CW		 430 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
431 return val;
432}
433
434static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
435{
436 struct drm_i915_private *dev_priv = dev->dev_private;
437 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
438 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
439}
440
f52c619a 441static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level)
a9573556
CW		 442{
443 struct drm_i915_private *dev_priv = dev->dev_private;
444 u32 tmp;
445
446 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
7bd90909 447 level = intel_panel_compute_brightness(dev, level);
a9573556
CW		 448
449 if (HAS_PCH_SPLIT(dev))
450 return intel_pch_panel_set_backlight(dev, level);
ba3820ad 451
0206e353 452 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI		 453 u32 max = intel_panel_get_max_backlight(dev);
454 u8 lbpc;
455
d6540632
JN		 456 /* we're screwed, but keep behaviour backwards compatible */
457 if (!max)
458 max = 1;
459
ba3820ad
TI		 460 lbpc = level * 0xfe / max + 1;
461 level /= lbpc;
462 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
463 }
464
a9573556 465 tmp = I915_READ(BLC_PWM_CTL);
a726915c 466 if (INTEL_INFO(dev)->gen < 4)
a9573556 467 level <<= 1;
ca88479c 468 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
a9573556
CW		 469 I915_WRITE(BLC_PWM_CTL, tmp | level);
470}
47356eb6 471
d6540632
JN		 472/* set backlight brightness to level in range [0..max] */
473void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max)
47356eb6
CW		 474{
475 struct drm_i915_private *dev_priv = dev->dev_private;
d6540632 476 u32 freq;
8ba2d185
JN		 477 unsigned long flags;
478
479 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632
JN		 480
481 freq = intel_panel_get_max_backlight(dev);
482 if (!freq) {
483 /* we are screwed, bail out */
8ba2d185 484 goto out;
d6540632
JN		 485 }
486
22505b82
AL		 487 /* scale to hardware, but be careful to not overflow */
488 if (freq < max)
489 level = level * freq / max;
490 else
491 level = freq / max * level;
47356eb6 492
31ad8ec6
JN		 493 dev_priv->backlight.level = level;
494 if (dev_priv->backlight.device)
495 dev_priv->backlight.device->props.brightness = level;
b6b3ba5b 496
31ad8ec6 497 if (dev_priv->backlight.enabled)
f52c619a 498 intel_panel_actually_set_backlight(dev, level);
8ba2d185
JN		 499out:
500 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
f52c619a
TI		 501}
502
503void intel_panel_disable_backlight(struct drm_device *dev)
504{
505 struct drm_i915_private *dev_priv = dev->dev_private;
8ba2d185
JN		 506 unsigned long flags;
507
3f577573
JN		 508 /*
509 * Do not disable backlight on the vgaswitcheroo path. When switching
510 * away from i915, the other client may depend on i915 to handle the
511 * backlight. This will leave the backlight on unnecessarily when
512 * another client is not activated.
513 */
514 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
515 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
516 return;
517 }
518
8ba2d185 519 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 520
31ad8ec6 521 dev_priv->backlight.enabled = false;
f52c619a 522 intel_panel_actually_set_backlight(dev, 0);
24ded204
DV		 523
524 if (INTEL_INFO(dev)->gen >= 4) {
a4f32fc3 525 uint32_t reg, tmp;
24ded204
DV		 526
527 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
528
529 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
a4f32fc3
PZ		 530
531 if (HAS_PCH_SPLIT(dev)) {
532 tmp = I915_READ(BLC_PWM_PCH_CTL1);
533 tmp &= ~BLM_PCH_PWM_ENABLE;
534 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
535 }
24ded204 536 }
8ba2d185
JN		 537
538 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW		 539}
540
24ded204
DV		 541void intel_panel_enable_backlight(struct drm_device *dev,
542 enum pipe pipe)
47356eb6
CW		 543{
544 struct drm_i915_private *dev_priv = dev->dev_private;
35ffda48
JN		 545 enum transcoder cpu_transcoder =
546 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
8ba2d185
JN		 547 unsigned long flags;
548
549 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 550
31ad8ec6
JN		 551 if (dev_priv->backlight.level == 0) {
552 dev_priv->backlight.level = intel_panel_get_max_backlight(dev);
553 if (dev_priv->backlight.device)
554 dev_priv->backlight.device->props.brightness =
555 dev_priv->backlight.level;
b6b3ba5b 556 }
47356eb6 557
24ded204
DV		 558 if (INTEL_INFO(dev)->gen >= 4) {
559 uint32_t reg, tmp;
560
561 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
562
563
564 tmp = I915_READ(reg);
565
566 /* Note that this can also get called through dpms changes. And
567 * we don't track the backlight dpms state, hence check whether
568 * we have to do anything first. */
569 if (tmp & BLM_PWM_ENABLE)
770c1231 570 goto set_level;
24ded204 571
7eb552ae 572 if (INTEL_INFO(dev)->num_pipes == 3)
24ded204
DV		 573 tmp &= ~BLM_PIPE_SELECT_IVB;
574 else
575 tmp &= ~BLM_PIPE_SELECT;
576
35ffda48
JN		 577 if (cpu_transcoder == TRANSCODER_EDP)
578 tmp |= BLM_TRANSCODER_EDP;
579 else
580 tmp |= BLM_PIPE(cpu_transcoder);
24ded204
DV		 581 tmp &= ~BLM_PWM_ENABLE;
582
583 I915_WRITE(reg, tmp);
584 POSTING_READ(reg);
585 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
a4f32fc3 586
e85843be
KM		 587 if (HAS_PCH_SPLIT(dev) &&
588 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
a4f32fc3
PZ		 589 tmp = I915_READ(BLC_PWM_PCH_CTL1);
590 tmp |= BLM_PCH_PWM_ENABLE;
591 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
592 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
593 }
24ded204 594 }
770c1231
TI		 595
596set_level:
b1289371
DV		 597 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
598 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
599 * registers are set.
770c1231 600 */
ecb135a1
DV		 601 dev_priv->backlight.enabled = true;
602 intel_panel_actually_set_backlight(dev, dev_priv->backlight.level);
8ba2d185
JN		 603
604 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW		 605}
606
aaa6fd2a 607static void intel_panel_init_backlight(struct drm_device *dev)
47356eb6
CW		 608{
609 struct drm_i915_private *dev_priv = dev->dev_private;
610
31ad8ec6
JN		 611 dev_priv->backlight.level = intel_panel_get_backlight(dev);
612 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
47356eb6 613}
fe16d949
CW		 614
615enum drm_connector_status
616intel_panel_detect(struct drm_device *dev)
617{
618 struct drm_i915_private *dev_priv = dev->dev_private;
619
620 /* Assume that the BIOS does not lie through the OpRegion... */
a726915c 621 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
fe16d949
CW		 622 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
623 connector_status_connected :
624 connector_status_disconnected;
a726915c 625 }
fe16d949 626
a726915c
DV		 627 switch (i915_panel_ignore_lid) {
628 case -2:
629 return connector_status_connected;
630 case -1:
631 return connector_status_disconnected;
632 default:
633 return connector_status_unknown;
634 }
fe16d949 635}
aaa6fd2a
MG		 636
637#ifdef CONFIG_BACKLIGHT_CLASS_DEVICE
638static int intel_panel_update_status(struct backlight_device *bd)
639{
640 struct drm_device *dev = bl_get_data(bd);
d6540632
JN		 641 intel_panel_set_backlight(dev, bd->props.brightness,
642 bd->props.max_brightness);
aaa6fd2a
MG		 643 return 0;
644}
645
646static int intel_panel_get_brightness(struct backlight_device *bd)
647{
648 struct drm_device *dev = bl_get_data(bd);
7c23396b 649 return intel_panel_get_backlight(dev);
aaa6fd2a
MG		 650}
651
652static const struct backlight_ops intel_panel_bl_ops = {
653 .update_status = intel_panel_update_status,
654 .get_brightness = intel_panel_get_brightness,
655};
656
0657b6b1 657int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 658{
0657b6b1 659 struct drm_device *dev = connector->dev;
aaa6fd2a
MG		 660 struct drm_i915_private *dev_priv = dev->dev_private;
661 struct backlight_properties props;
8ba2d185 662 unsigned long flags;
aaa6fd2a
MG		 663
664 intel_panel_init_backlight(dev);
665
dc652f90
JN		 666 if (WARN_ON(dev_priv->backlight.device))
667 return -ENODEV;
668
af437cfd 669 memset(&props, 0, sizeof(props));
aaa6fd2a 670 props.type = BACKLIGHT_RAW;
31ad8ec6 671 props.brightness = dev_priv->backlight.level;
8ba2d185
JN		 672
673 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632 674 props.max_brightness = intel_panel_get_max_backlight(dev);
8ba2d185
JN		 675 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
676
28dcc2d6 677 if (props.max_brightness == 0) {
e86b6185 678 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
28dcc2d6
JN		 679 return -ENODEV;
680 }
31ad8ec6 681 dev_priv->backlight.device =
aaa6fd2a
MG		 682 backlight_device_register("intel_backlight",
683 &connector->kdev, dev,
684 &intel_panel_bl_ops, &props);
685
31ad8ec6 686 if (IS_ERR(dev_priv->backlight.device)) {
aaa6fd2a 687 DRM_ERROR("Failed to register backlight: %ld\n",
31ad8ec6
JN		 688 PTR_ERR(dev_priv->backlight.device));
689 dev_priv->backlight.device = NULL;
aaa6fd2a
MG		 690 return -ENODEV;
691 }
aaa6fd2a
MG		 692 return 0;
693}
694
695void intel_panel_destroy_backlight(struct drm_device *dev)
696{
697 struct drm_i915_private *dev_priv = dev->dev_private;
dc652f90 698 if (dev_priv->backlight.device) {
31ad8ec6 699 backlight_device_unregister(dev_priv->backlight.device);
dc652f90
JN		 700 dev_priv->backlight.device = NULL;
701 }
aaa6fd2a
MG		 702}
703#else
0657b6b1 704int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 705{
0657b6b1 706 intel_panel_init_backlight(connector->dev);
aaa6fd2a
MG		 707 return 0;
708}
709
710void intel_panel_destroy_backlight(struct drm_device *dev)
711{
712 return;
713}
714#endif
1d508706 715
dd06f90e
JN		 716int intel_panel_init(struct intel_panel *panel,
717 struct drm_display_mode *fixed_mode)
1d508706 718{
dd06f90e
JN		 719 panel->fixed_mode = fixed_mode;
720
1d508706
JN		 721 return 0;
722}
723
724void intel_panel_fini(struct intel_panel *panel)
725{
dd06f90e
JN		 726 struct intel_connector *intel_connector =
727 container_of(panel, struct intel_connector, panel);
728
729 if (panel->fixed_mode)
730 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
1d508706 731}
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