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drm/i915: make backlight functions take a connector
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW
1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP
31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
7bd90909 33#include <linux/moduleparam.h>
1d8e1c75
CW
34#include "intel_drv.h"
35
ba3820ad
TI
36#define PCI_LBPC 0xf4 /* legacy/combination backlight modes */
37
1d8e1c75 38void
4c6df4b4 39intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW
40 struct drm_display_mode *adjusted_mode)
41{
4c6df4b4 42 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID
43
44 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW
45}
46
47/* adjusted_mode has been preset to be the panel's fixed mode */
48void
b074cec8
JB
49intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
50 struct intel_crtc_config *pipe_config,
51 int fitting_mode)
1d8e1c75 52{
37327abd 53 struct drm_display_mode *adjusted_mode;
1d8e1c75
CW
54 int x, y, width, height;
55
b074cec8
JB
56 adjusted_mode = &pipe_config->adjusted_mode;
57
1d8e1c75
CW
58 x = y = width = height = 0;
59
60 /* Native modes don't need fitting */
37327abd
VS
61 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
62 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
1d8e1c75
CW
63 goto done;
64
65 switch (fitting_mode) {
66 case DRM_MODE_SCALE_CENTER:
37327abd
VS
67 width = pipe_config->pipe_src_w;
68 height = pipe_config->pipe_src_h;
1d8e1c75
CW
69 x = (adjusted_mode->hdisplay - width + 1)/2;
70 y = (adjusted_mode->vdisplay - height + 1)/2;
71 break;
72
73 case DRM_MODE_SCALE_ASPECT:
74 /* Scale but preserve the aspect ratio */
75 {
9084e7d2
DV
76 u32 scaled_width = adjusted_mode->hdisplay
77 * pipe_config->pipe_src_h;
78 u32 scaled_height = pipe_config->pipe_src_w
79 * adjusted_mode->vdisplay;
1d8e1c75 80 if (scaled_width > scaled_height) { /* pillar */
37327abd 81 width = scaled_height / pipe_config->pipe_src_h;
302983e9 82 if (width & 1)
0206e353 83 width++;
1d8e1c75
CW
84 x = (adjusted_mode->hdisplay - width + 1) / 2;
85 y = 0;
86 height = adjusted_mode->vdisplay;
87 } else if (scaled_width < scaled_height) { /* letter */
37327abd 88 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ
89 if (height & 1)
90 height++;
1d8e1c75
CW
91 y = (adjusted_mode->vdisplay - height + 1) / 2;
92 x = 0;
93 width = adjusted_mode->hdisplay;
94 } else {
95 x = y = 0;
96 width = adjusted_mode->hdisplay;
97 height = adjusted_mode->vdisplay;
98 }
99 }
100 break;
101
1d8e1c75
CW
102 case DRM_MODE_SCALE_FULLSCREEN:
103 x = y = 0;
104 width = adjusted_mode->hdisplay;
105 height = adjusted_mode->vdisplay;
106 break;
ab3e67f4
JB
107
108 default:
109 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
110 return;
1d8e1c75
CW
111 }
112
113done:
b074cec8
JB
114 pipe_config->pch_pfit.pos = (x << 16) | y;
115 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 116 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 117}
a9573556 118
2dd24552
JB
119static void
120centre_horizontally(struct drm_display_mode *mode,
121 int width)
122{
123 u32 border, sync_pos, blank_width, sync_width;
124
125 /* keep the hsync and hblank widths constant */
126 sync_width = mode->crtc_hsync_end - mode->crtc_hsync_start;
127 blank_width = mode->crtc_hblank_end - mode->crtc_hblank_start;
128 sync_pos = (blank_width - sync_width + 1) / 2;
129
130 border = (mode->hdisplay - width + 1) / 2;
131 border += border & 1; /* make the border even */
132
133 mode->crtc_hdisplay = width;
134 mode->crtc_hblank_start = width + border;
135 mode->crtc_hblank_end = mode->crtc_hblank_start + blank_width;
136
137 mode->crtc_hsync_start = mode->crtc_hblank_start + sync_pos;
138 mode->crtc_hsync_end = mode->crtc_hsync_start + sync_width;
139}
140
141static void
142centre_vertically(struct drm_display_mode *mode,
143 int height)
144{
145 u32 border, sync_pos, blank_width, sync_width;
146
147 /* keep the vsync and vblank widths constant */
148 sync_width = mode->crtc_vsync_end - mode->crtc_vsync_start;
149 blank_width = mode->crtc_vblank_end - mode->crtc_vblank_start;
150 sync_pos = (blank_width - sync_width + 1) / 2;
151
152 border = (mode->vdisplay - height + 1) / 2;
153
154 mode->crtc_vdisplay = height;
155 mode->crtc_vblank_start = height + border;
156 mode->crtc_vblank_end = mode->crtc_vblank_start + blank_width;
157
158 mode->crtc_vsync_start = mode->crtc_vblank_start + sync_pos;
159 mode->crtc_vsync_end = mode->crtc_vsync_start + sync_width;
160}
161
162static inline u32 panel_fitter_scaling(u32 source, u32 target)
163{
164 /*
165 * Floating point operation is not supported. So the FACTOR
166 * is defined, which can avoid the floating point computation
167 * when calculating the panel ratio.
168 */
169#define ACCURACY 12
170#define FACTOR (1 << ACCURACY)
171 u32 ratio = source * FACTOR / target;
172 return (FACTOR * ratio + FACTOR/2) / FACTOR;
173}
174
9084e7d2
DV
175static void i965_scale_aspect(struct intel_crtc_config *pipe_config,
176 u32 *pfit_control)
177{
178 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
179 u32 scaled_width = adjusted_mode->hdisplay *
180 pipe_config->pipe_src_h;
181 u32 scaled_height = pipe_config->pipe_src_w *
182 adjusted_mode->vdisplay;
183
184 /* 965+ is easy, it does everything in hw */
185 if (scaled_width > scaled_height)
186 *pfit_control |= PFIT_ENABLE |
187 PFIT_SCALING_PILLAR;
188 else if (scaled_width < scaled_height)
189 *pfit_control |= PFIT_ENABLE |
190 PFIT_SCALING_LETTER;
191 else if (adjusted_mode->hdisplay != pipe_config->pipe_src_w)
192 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
193}
194
195static void i9xx_scale_aspect(struct intel_crtc_config *pipe_config,
196 u32 *pfit_control, u32 *pfit_pgm_ratios,
197 u32 *border)
198{
199 struct drm_display_mode *adjusted_mode = &pipe_config->adjusted_mode;
200 u32 scaled_width = adjusted_mode->hdisplay *
201 pipe_config->pipe_src_h;
202 u32 scaled_height = pipe_config->pipe_src_w *
203 adjusted_mode->vdisplay;
204 u32 bits;
205
206 /*
207 * For earlier chips we have to calculate the scaling
208 * ratio by hand and program it into the
209 * PFIT_PGM_RATIO register
210 */
211 if (scaled_width > scaled_height) { /* pillar */
212 centre_horizontally(adjusted_mode,
213 scaled_height /
214 pipe_config->pipe_src_h);
215
216 *border = LVDS_BORDER_ENABLE;
217 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay) {
218 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
219 adjusted_mode->vdisplay);
220
221 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
222 bits << PFIT_VERT_SCALE_SHIFT);
223 *pfit_control |= (PFIT_ENABLE |
224 VERT_INTERP_BILINEAR |
225 HORIZ_INTERP_BILINEAR);
226 }
227 } else if (scaled_width < scaled_height) { /* letter */
228 centre_vertically(adjusted_mode,
229 scaled_width /
230 pipe_config->pipe_src_w);
231
232 *border = LVDS_BORDER_ENABLE;
233 if (pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
234 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
235 adjusted_mode->hdisplay);
236
237 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
238 bits << PFIT_VERT_SCALE_SHIFT);
239 *pfit_control |= (PFIT_ENABLE |
240 VERT_INTERP_BILINEAR |
241 HORIZ_INTERP_BILINEAR);
242 }
243 } else {
244 /* Aspects match, Let hw scale both directions */
245 *pfit_control |= (PFIT_ENABLE |
246 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
247 VERT_INTERP_BILINEAR |
248 HORIZ_INTERP_BILINEAR);
249 }
250}
251
2dd24552
JB
252void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
253 struct intel_crtc_config *pipe_config,
254 int fitting_mode)
255{
256 struct drm_device *dev = intel_crtc->base.dev;
2dd24552 257 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
37327abd 258 struct drm_display_mode *adjusted_mode;
2dd24552 259
2dd24552
JB
260 adjusted_mode = &pipe_config->adjusted_mode;
261
262 /* Native modes don't need fitting */
37327abd
VS
263 if (adjusted_mode->hdisplay == pipe_config->pipe_src_w &&
264 adjusted_mode->vdisplay == pipe_config->pipe_src_h)
2dd24552
JB
265 goto out;
266
267 switch (fitting_mode) {
268 case DRM_MODE_SCALE_CENTER:
269 /*
270 * For centered modes, we have to calculate border widths &
271 * heights and modify the values programmed into the CRTC.
272 */
37327abd
VS
273 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
274 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB
275 border = LVDS_BORDER_ENABLE;
276 break;
277 case DRM_MODE_SCALE_ASPECT:
278 /* Scale but preserve the aspect ratio */
9084e7d2
DV
279 if (INTEL_INFO(dev)->gen >= 4)
280 i965_scale_aspect(pipe_config, &pfit_control);
281 else
282 i9xx_scale_aspect(pipe_config, &pfit_control,
283 &pfit_pgm_ratios, &border);
2dd24552 284 break;
2dd24552
JB
285 case DRM_MODE_SCALE_FULLSCREEN:
286 /*
287 * Full scaling, even if it changes the aspect ratio.
288 * Fortunately this is all done for us in hw.
289 */
37327abd
VS
290 if (pipe_config->pipe_src_h != adjusted_mode->vdisplay ||
291 pipe_config->pipe_src_w != adjusted_mode->hdisplay) {
2dd24552
JB
292 pfit_control |= PFIT_ENABLE;
293 if (INTEL_INFO(dev)->gen >= 4)
294 pfit_control |= PFIT_SCALING_AUTO;
295 else
296 pfit_control |= (VERT_AUTO_SCALE |
297 VERT_INTERP_BILINEAR |
298 HORIZ_AUTO_SCALE |
299 HORIZ_INTERP_BILINEAR);
300 }
301 break;
ab3e67f4
JB
302 default:
303 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
304 return;
2dd24552
JB
305 }
306
307 /* 965+ wants fuzzy fitting */
308 /* FIXME: handle multiple panels by failing gracefully */
309 if (INTEL_INFO(dev)->gen >= 4)
310 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
311 PFIT_FILTER_FUZZY);
312
313out:
314 if ((pfit_control & PFIT_ENABLE) == 0) {
315 pfit_control = 0;
316 pfit_pgm_ratios = 0;
317 }
318
319 /* Make sure pre-965 set dither correctly for 18bpp panels. */
320 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
321 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
322
2deefda5
DV
323 pipe_config->gmch_pfit.control = pfit_control;
324 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 325 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB
326}
327
ba3820ad
TI
328static int is_backlight_combination_mode(struct drm_device *dev)
329{
330 struct drm_i915_private *dev_priv = dev->dev_private;
331
d9c638d5 332 if (IS_GEN4(dev))
ba3820ad
TI
333 return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE;
334
335 if (IS_GEN2(dev))
336 return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE;
337
338 return 0;
339}
340
d6540632
JN
341/* XXX: query mode clock or hardware clock and program max PWM appropriately
342 * when it's 0.
343 */
752aa88a 344static u32 i915_read_blc_pwm_ctl(struct drm_device *dev, enum pipe pipe)
0b0b053a 345{
bfd7590d 346 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a
CW
347 u32 val;
348
df0a6797 349 WARN_ON_SMP(!spin_is_locked(&dev_priv->backlight.lock));
8ba2d185 350
0b0b053a
CW
351 /* Restore the CTL value if it lost, e.g. GPU reset */
352
353 if (HAS_PCH_SPLIT(dev_priv->dev)) {
354 val = I915_READ(BLC_PWM_PCH_CTL2);
f4c956ad
DV
355 if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) {
356 dev_priv->regfile.saveBLC_PWM_CTL2 = val;
0b0b053a 357 } else if (val == 0) {
f4c956ad 358 val = dev_priv->regfile.saveBLC_PWM_CTL2;
bfd7590d 359 I915_WRITE(BLC_PWM_PCH_CTL2, val);
0b0b053a
CW
360 }
361 } else {
362 val = I915_READ(BLC_PWM_CTL);
f4c956ad
DV
363 if (dev_priv->regfile.saveBLC_PWM_CTL == 0) {
364 dev_priv->regfile.saveBLC_PWM_CTL = val;
bfd7590d
JN
365 if (INTEL_INFO(dev)->gen >= 4)
366 dev_priv->regfile.saveBLC_PWM_CTL2 =
367 I915_READ(BLC_PWM_CTL2);
0b0b053a 368 } else if (val == 0) {
f4c956ad 369 val = dev_priv->regfile.saveBLC_PWM_CTL;
bfd7590d
JN
370 I915_WRITE(BLC_PWM_CTL, val);
371 if (INTEL_INFO(dev)->gen >= 4)
372 I915_WRITE(BLC_PWM_CTL2,
373 dev_priv->regfile.saveBLC_PWM_CTL2);
0b0b053a 374 }
afc85b9d
JB
375
376 if (IS_VALLEYVIEW(dev) && !val)
377 val = 0x0f42ffff;
0b0b053a
CW
378 }
379
380 return val;
381}
382
752aa88a
JB
383static u32 intel_panel_get_max_backlight(struct drm_device *dev,
384 enum pipe pipe)
a9573556 385{
a9573556
CW
386 u32 max;
387
752aa88a 388 max = i915_read_blc_pwm_ctl(dev, pipe);
0b0b053a 389
a9573556 390 if (HAS_PCH_SPLIT(dev)) {
0b0b053a 391 max >>= 16;
a9573556 392 } else {
ca88479c 393 if (INTEL_INFO(dev)->gen < 4)
a9573556 394 max >>= 17;
ca88479c 395 else
a9573556 396 max >>= 16;
ba3820ad
TI
397
398 if (is_backlight_combination_mode(dev))
399 max *= 0xff;
a9573556
CW
400 }
401
a9573556 402 DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max);
d6540632 403
a9573556
CW
404 return max;
405}
406
4dca20ef
CE
407static int i915_panel_invert_brightness;
408MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness "
409 "(-1 force normal, 0 machine defaults, 1 force inversion), please "
7bd90909
CE
410 "report PCI device ID, subsystem vendor and subsystem device ID "
411 "to dri-devel@lists.freedesktop.org, if your machine needs it. "
412 "It will then be included in an upcoming module version.");
4dca20ef 413module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600);
752aa88a
JB
414static u32 intel_panel_compute_brightness(struct drm_device *dev,
415 enum pipe pipe, u32 val)
7bd90909 416{
4dca20ef
CE
417 struct drm_i915_private *dev_priv = dev->dev_private;
418
419 if (i915_panel_invert_brightness < 0)
420 return val;
421
422 if (i915_panel_invert_brightness > 0 ||
d6540632 423 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
752aa88a 424 u32 max = intel_panel_get_max_backlight(dev, pipe);
d6540632
JN
425 if (max)
426 return max - val;
427 }
7bd90909
CE
428
429 return val;
430}
431
752aa88a
JB
432static u32 intel_panel_get_backlight(struct drm_device *dev,
433 enum pipe pipe)
a9573556
CW
434{
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 u32 val;
8ba2d185
JN
437 unsigned long flags;
438
439 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
a9573556
CW
440
441 if (HAS_PCH_SPLIT(dev)) {
442 val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
443 } else {
444 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
ca88479c 445 if (INTEL_INFO(dev)->gen < 4)
a9573556 446 val >>= 1;
ba3820ad 447
0206e353 448 if (is_backlight_combination_mode(dev)) {
ba3820ad
TI
449 u8 lbpc;
450
ba3820ad
TI
451 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
452 val *= lbpc;
453 }
a9573556
CW
454 }
455
752aa88a 456 val = intel_panel_compute_brightness(dev, pipe, val);
8ba2d185
JN
457
458 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
459
a9573556
CW
460 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
461 return val;
462}
463
464static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level)
465{
466 struct drm_i915_private *dev_priv = dev->dev_private;
467 u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
468 I915_WRITE(BLC_PWM_CPU_CTL, val | level);
469}
470
9084e7d2 471static void intel_panel_actually_set_backlight(struct drm_device *dev,
752aa88a 472 enum pipe pipe, u32 level)
a9573556
CW
473{
474 struct drm_i915_private *dev_priv = dev->dev_private;
475 u32 tmp;
476
477 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
752aa88a 478 level = intel_panel_compute_brightness(dev, pipe, level);
a9573556
CW
479
480 if (HAS_PCH_SPLIT(dev))
481 return intel_pch_panel_set_backlight(dev, level);
ba3820ad 482
0206e353 483 if (is_backlight_combination_mode(dev)) {
752aa88a 484 u32 max = intel_panel_get_max_backlight(dev, pipe);
ba3820ad
TI
485 u8 lbpc;
486
d6540632
JN
487 /* we're screwed, but keep behaviour backwards compatible */
488 if (!max)
489 max = 1;
490
ba3820ad
TI
491 lbpc = level * 0xfe / max + 1;
492 level /= lbpc;
493 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
494 }
495
a9573556 496 tmp = I915_READ(BLC_PWM_CTL);
a726915c 497 if (INTEL_INFO(dev)->gen < 4)
a9573556 498 level <<= 1;
ca88479c 499 tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK;
a9573556
CW
500 I915_WRITE(BLC_PWM_CTL, tmp | level);
501}
47356eb6 502
d6540632 503/* set backlight brightness to level in range [0..max] */
752aa88a
JB
504void intel_panel_set_backlight(struct intel_connector *connector, u32 level,
505 u32 max)
47356eb6 506{
752aa88a 507 struct drm_device *dev = connector->base.dev;
47356eb6 508 struct drm_i915_private *dev_priv = dev->dev_private;
752aa88a 509 enum pipe pipe = intel_get_pipe_from_connector(connector);
d6540632 510 u32 freq;
8ba2d185
JN
511 unsigned long flags;
512
752aa88a
JB
513 if (pipe == INVALID_PIPE)
514 return;
515
8ba2d185 516 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
d6540632 517
752aa88a 518 freq = intel_panel_get_max_backlight(dev, pipe);
d6540632
JN
519 if (!freq) {
520 /* we are screwed, bail out */
8ba2d185 521 goto out;
d6540632
JN
522 }
523
22505b82
AL
524 /* scale to hardware, but be careful to not overflow */
525 if (freq < max)
526 level = level * freq / max;
527 else
528 level = freq / max * level;
47356eb6 529
31ad8ec6
JN
530 dev_priv->backlight.level = level;
531 if (dev_priv->backlight.device)
532 dev_priv->backlight.device->props.brightness = level;
b6b3ba5b 533
31ad8ec6 534 if (dev_priv->backlight.enabled)
752aa88a 535 intel_panel_actually_set_backlight(dev, pipe, level);
8ba2d185
JN
536out:
537 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
f52c619a
TI
538}
539
752aa88a 540void intel_panel_disable_backlight(struct intel_connector *connector)
f52c619a 541{
752aa88a 542 struct drm_device *dev = connector->base.dev;
f52c619a 543 struct drm_i915_private *dev_priv = dev->dev_private;
752aa88a 544 enum pipe pipe = intel_get_pipe_from_connector(connector);
8ba2d185
JN
545 unsigned long flags;
546
752aa88a
JB
547 if (pipe == INVALID_PIPE)
548 return;
549
3f577573
JN
550 /*
551 * Do not disable backlight on the vgaswitcheroo path. When switching
552 * away from i915, the other client may depend on i915 to handle the
553 * backlight. This will leave the backlight on unnecessarily when
554 * another client is not activated.
555 */
556 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
557 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
558 return;
559 }
560
8ba2d185 561 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 562
31ad8ec6 563 dev_priv->backlight.enabled = false;
752aa88a 564 intel_panel_actually_set_backlight(dev, pipe, 0);
24ded204
DV
565
566 if (INTEL_INFO(dev)->gen >= 4) {
a4f32fc3 567 uint32_t reg, tmp;
24ded204
DV
568
569 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
570
571 I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE);
a4f32fc3
PZ
572
573 if (HAS_PCH_SPLIT(dev)) {
574 tmp = I915_READ(BLC_PWM_PCH_CTL1);
575 tmp &= ~BLM_PCH_PWM_ENABLE;
576 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
577 }
24ded204 578 }
8ba2d185
JN
579
580 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW
581}
582
752aa88a 583void intel_panel_enable_backlight(struct intel_connector *connector)
47356eb6 584{
752aa88a 585 struct drm_device *dev = connector->base.dev;
47356eb6 586 struct drm_i915_private *dev_priv = dev->dev_private;
752aa88a 587 enum pipe pipe = intel_get_pipe_from_connector(connector);
35ffda48
JN
588 enum transcoder cpu_transcoder =
589 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
8ba2d185
JN
590 unsigned long flags;
591
752aa88a
JB
592 if (pipe == INVALID_PIPE)
593 return;
594
6f2bcceb 595 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
540b5d02 596
8ba2d185 597 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
47356eb6 598
31ad8ec6 599 if (dev_priv->backlight.level == 0) {
752aa88a
JB
600 dev_priv->backlight.level = intel_panel_get_max_backlight(dev,
601 pipe);
31ad8ec6
JN
602 if (dev_priv->backlight.device)
603 dev_priv->backlight.device->props.brightness =
604 dev_priv->backlight.level;
b6b3ba5b 605 }
47356eb6 606
24ded204
DV
607 if (INTEL_INFO(dev)->gen >= 4) {
608 uint32_t reg, tmp;
609
610 reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2;
611
612
613 tmp = I915_READ(reg);
614
615 /* Note that this can also get called through dpms changes. And
616 * we don't track the backlight dpms state, hence check whether
617 * we have to do anything first. */
618 if (tmp & BLM_PWM_ENABLE)
770c1231 619 goto set_level;
24ded204 620
7eb552ae 621 if (INTEL_INFO(dev)->num_pipes == 3)
24ded204
DV
622 tmp &= ~BLM_PIPE_SELECT_IVB;
623 else
624 tmp &= ~BLM_PIPE_SELECT;
625
35ffda48
JN
626 if (cpu_transcoder == TRANSCODER_EDP)
627 tmp |= BLM_TRANSCODER_EDP;
628 else
629 tmp |= BLM_PIPE(cpu_transcoder);
24ded204
DV
630 tmp &= ~BLM_PWM_ENABLE;
631
632 I915_WRITE(reg, tmp);
633 POSTING_READ(reg);
634 I915_WRITE(reg, tmp | BLM_PWM_ENABLE);
a4f32fc3 635
e85843be
KM
636 if (HAS_PCH_SPLIT(dev) &&
637 !(dev_priv->quirks & QUIRK_NO_PCH_PWM_ENABLE)) {
a4f32fc3
PZ
638 tmp = I915_READ(BLC_PWM_PCH_CTL1);
639 tmp |= BLM_PCH_PWM_ENABLE;
640 tmp &= ~BLM_PCH_OVERRIDE_ENABLE;
641 I915_WRITE(BLC_PWM_PCH_CTL1, tmp);
642 }
24ded204 643 }
770c1231
TI
644
645set_level:
b1289371
DV
646 /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1.
647 * BLC_PWM_CPU_CTL may be cleared to zero automatically when these
648 * registers are set.
770c1231 649 */
ecb135a1 650 dev_priv->backlight.enabled = true;
752aa88a
JB
651 intel_panel_actually_set_backlight(dev, pipe,
652 dev_priv->backlight.level);
8ba2d185
JN
653
654 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
47356eb6
CW
655}
656
afc85b9d
JB
657/* FIXME: use VBT vals to init PWM_CTL and PWM_CTL2 correctly */
658static void intel_panel_init_backlight_regs(struct drm_device *dev)
659{
660 struct drm_i915_private *dev_priv = dev->dev_private;
661
662 if (IS_VALLEYVIEW(dev)) {
663 u32 cur_val = I915_READ(BLC_PWM_CTL) &
664 BACKLIGHT_DUTY_CYCLE_MASK;
665 I915_WRITE(BLC_PWM_CTL, (0xf42 << 16) | cur_val);
666 }
667}
668
aaa6fd2a 669static void intel_panel_init_backlight(struct drm_device *dev)
47356eb6
CW
670{
671 struct drm_i915_private *dev_priv = dev->dev_private;
672
afc85b9d
JB
673 intel_panel_init_backlight_regs(dev);
674
752aa88a 675 dev_priv->backlight.level = intel_panel_get_backlight(dev, 0);
31ad8ec6 676 dev_priv->backlight.enabled = dev_priv->backlight.level != 0;
47356eb6 677}
fe16d949
CW
678
679enum drm_connector_status
680intel_panel_detect(struct drm_device *dev)
681{
682 struct drm_i915_private *dev_priv = dev->dev_private;
683
684 /* Assume that the BIOS does not lie through the OpRegion... */
a726915c 685 if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) {
fe16d949
CW
686 return ioread32(dev_priv->opregion.lid_state) & 0x1 ?
687 connector_status_connected :
688 connector_status_disconnected;
a726915c 689 }
fe16d949 690
a726915c
DV
691 switch (i915_panel_ignore_lid) {
692 case -2:
693 return connector_status_connected;
694 case -1:
695 return connector_status_disconnected;
696 default:
697 return connector_status_unknown;
698 }
fe16d949 699}
aaa6fd2a 700
912e8b12 701#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
aaa6fd2a
MG
702static int intel_panel_update_status(struct backlight_device *bd)
703{
752aa88a
JB
704 struct intel_connector *connector = bl_get_data(bd);
705 struct drm_device *dev = connector->base.dev;
706
707 mutex_lock(&dev->mode_config.mutex);
540b5d02
CW
708 DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
709 bd->props.brightness, bd->props.max_brightness);
752aa88a 710 intel_panel_set_backlight(connector, bd->props.brightness,
d6540632 711 bd->props.max_brightness);
752aa88a 712 mutex_unlock(&dev->mode_config.mutex);
aaa6fd2a
MG
713 return 0;
714}
715
716static int intel_panel_get_brightness(struct backlight_device *bd)
717{
752aa88a
JB
718 struct intel_connector *connector = bl_get_data(bd);
719 struct drm_device *dev = connector->base.dev;
720 enum pipe pipe;
721
722 mutex_lock(&dev->mode_config.mutex);
723 pipe = intel_get_pipe_from_connector(connector);
724 mutex_unlock(&dev->mode_config.mutex);
725 if (pipe == INVALID_PIPE)
726 return 0;
727
728 return intel_panel_get_backlight(connector->base.dev, pipe);
aaa6fd2a
MG
729}
730
731static const struct backlight_ops intel_panel_bl_ops = {
732 .update_status = intel_panel_update_status,
733 .get_brightness = intel_panel_get_brightness,
734};
735
0657b6b1 736int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 737{
0657b6b1 738 struct drm_device *dev = connector->dev;
aaa6fd2a
MG
739 struct drm_i915_private *dev_priv = dev->dev_private;
740 struct backlight_properties props;
8ba2d185 741 unsigned long flags;
aaa6fd2a
MG
742
743 intel_panel_init_backlight(dev);
744
dc652f90
JN
745 if (WARN_ON(dev_priv->backlight.device))
746 return -ENODEV;
747
af437cfd 748 memset(&props, 0, sizeof(props));
aaa6fd2a 749 props.type = BACKLIGHT_RAW;
31ad8ec6 750 props.brightness = dev_priv->backlight.level;
8ba2d185
JN
751
752 spin_lock_irqsave(&dev_priv->backlight.lock, flags);
752aa88a 753 props.max_brightness = intel_panel_get_max_backlight(dev, 0);
8ba2d185
JN
754 spin_unlock_irqrestore(&dev_priv->backlight.lock, flags);
755
28dcc2d6 756 if (props.max_brightness == 0) {
e86b6185 757 DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n");
28dcc2d6
JN
758 return -ENODEV;
759 }
31ad8ec6 760 dev_priv->backlight.device =
aaa6fd2a 761 backlight_device_register("intel_backlight",
752aa88a
JB
762 &connector->kdev,
763 to_intel_connector(connector),
aaa6fd2a
MG
764 &intel_panel_bl_ops, &props);
765
31ad8ec6 766 if (IS_ERR(dev_priv->backlight.device)) {
aaa6fd2a 767 DRM_ERROR("Failed to register backlight: %ld\n",
31ad8ec6
JN
768 PTR_ERR(dev_priv->backlight.device));
769 dev_priv->backlight.device = NULL;
aaa6fd2a
MG
770 return -ENODEV;
771 }
aaa6fd2a
MG
772 return 0;
773}
774
775void intel_panel_destroy_backlight(struct drm_device *dev)
776{
777 struct drm_i915_private *dev_priv = dev->dev_private;
dc652f90 778 if (dev_priv->backlight.device) {
31ad8ec6 779 backlight_device_unregister(dev_priv->backlight.device);
dc652f90
JN
780 dev_priv->backlight.device = NULL;
781 }
aaa6fd2a
MG
782}
783#else
0657b6b1 784int intel_panel_setup_backlight(struct drm_connector *connector)
aaa6fd2a 785{
0657b6b1 786 intel_panel_init_backlight(connector->dev);
aaa6fd2a
MG
787 return 0;
788}
789
790void intel_panel_destroy_backlight(struct drm_device *dev)
791{
792 return;
793}
794#endif
1d508706 795
dd06f90e
JN
796int intel_panel_init(struct intel_panel *panel,
797 struct drm_display_mode *fixed_mode)
1d508706 798{
dd06f90e
JN
799 panel->fixed_mode = fixed_mode;
800
1d508706
JN
801 return 0;
802}
803
804void intel_panel_fini(struct intel_panel *panel)
805{
dd06f90e
JN
806 struct intel_connector *intel_connector =
807 container_of(panel, struct intel_connector, panel);
808
809 if (panel->fixed_mode)
810 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
1d508706 811}