]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/intel_panel.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Fix vbt PWM max setup for CTG
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_panel.c
CommitLineData
1d8e1c75
CW		 1/*
2 * Copyright © 2006-2010 Intel Corporation
3 * Copyright (c) 2006 Dave Airlie <airlied@linux.ie>
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 *
24 * Authors:
25 * Eric Anholt <eric@anholt.net>
26 * Dave Airlie <airlied@linux.ie>
27 * Jesse Barnes <jesse.barnes@intel.com>
28 * Chris Wilson <chris@chris-wilson.co.uk>
29 */
30
a70491cc
JP		 31#define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
32
f766093e 33#include <linux/kernel.h>
7bd90909 34#include <linux/moduleparam.h>
b029e66f 35#include <linux/pwm.h>
1d8e1c75
CW		 36#include "intel_drv.h"
37
b029e66f
SK		 38#define CRC_PMIC_PWM_PERIOD_NS 21333
39
1d8e1c75 40void
4c6df4b4 41intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode,
1d8e1c75
CW		 42 struct drm_display_mode *adjusted_mode)
43{
4c6df4b4 44 drm_mode_copy(adjusted_mode, fixed_mode);
a52690e4
ID		 45
46 drm_mode_set_crtcinfo(adjusted_mode, 0);
1d8e1c75
CW		 47}
48
525997e0
JN		 49/**
50 * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID
51 * @dev: drm device
52 * @fixed_mode : panel native mode
53 * @connector: LVDS/eDP connector
54 *
55 * Return downclock_avail
56 * Find the reduced downclock for LVDS/eDP in EDID.
57 */
58struct drm_display_mode *
59intel_find_panel_downclock(struct drm_device *dev,
60 struct drm_display_mode *fixed_mode,
61 struct drm_connector *connector)
62{
63 struct drm_display_mode *scan, *tmp_mode;
64 int temp_downclock;
65
66 temp_downclock = fixed_mode->clock;
67 tmp_mode = NULL;
68
69 list_for_each_entry(scan, &connector->probed_modes, head) {
70 /*
71 * If one mode has the same resolution with the fixed_panel
72 * mode while they have the different refresh rate, it means
73 * that the reduced downclock is found. In such
74 * case we can set the different FPx0/1 to dynamically select
75 * between low and high frequency.
76 */
77 if (scan->hdisplay == fixed_mode->hdisplay &&
78 scan->hsync_start == fixed_mode->hsync_start &&
79 scan->hsync_end == fixed_mode->hsync_end &&
80 scan->htotal == fixed_mode->htotal &&
81 scan->vdisplay == fixed_mode->vdisplay &&
82 scan->vsync_start == fixed_mode->vsync_start &&
83 scan->vsync_end == fixed_mode->vsync_end &&
84 scan->vtotal == fixed_mode->vtotal) {
85 if (scan->clock < temp_downclock) {
86 /*
87 * The downclock is already found. But we
88 * expect to find the lower downclock.
89 */
90 temp_downclock = scan->clock;
91 tmp_mode = scan;
92 }
93 }
94 }
95
96 if (temp_downclock < fixed_mode->clock)
97 return drm_mode_duplicate(dev, tmp_mode);
98 else
99 return NULL;
100}
101
1d8e1c75
CW		 102/* adjusted_mode has been preset to be the panel's fixed mode */
103void
b074cec8 104intel_pch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 105 struct intel_crtc_state *pipe_config,
b074cec8 106 int fitting_mode)
1d8e1c75 107{
7c5f93b0
VS		 108 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
109 int x = 0, y = 0, width = 0, height = 0;
1d8e1c75
CW		 110
111 /* Native modes don't need fitting */
aad941d5
VS		 112 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
113 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
1d8e1c75
CW		 114 goto done;
115
116 switch (fitting_mode) {
117 case DRM_MODE_SCALE_CENTER:
37327abd
VS		 118 width = pipe_config->pipe_src_w;
119 height = pipe_config->pipe_src_h;
aad941d5
VS		 120 x = (adjusted_mode->crtc_hdisplay - width + 1)/2;
121 y = (adjusted_mode->crtc_vdisplay - height + 1)/2;
1d8e1c75
CW		 122 break;
123
124 case DRM_MODE_SCALE_ASPECT:
125 /* Scale but preserve the aspect ratio */
126 {
aad941d5 127 u32 scaled_width = adjusted_mode->crtc_hdisplay
9084e7d2
DV		 128 * pipe_config->pipe_src_h;
129 u32 scaled_height = pipe_config->pipe_src_w
aad941d5 130 * adjusted_mode->crtc_vdisplay;
1d8e1c75 131 if (scaled_width > scaled_height) { /* pillar */
37327abd 132 width = scaled_height / pipe_config->pipe_src_h;
302983e9 133 if (width & 1)
0206e353 134 width++;
aad941d5 135 x = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
1d8e1c75 136 y = 0;
aad941d5 137 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 138 } else if (scaled_width < scaled_height) { /* letter */
37327abd 139 height = scaled_width / pipe_config->pipe_src_w;
302983e9
AJ		 140 if (height & 1)
141 height++;
aad941d5 142 y = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
1d8e1c75 143 x = 0;
aad941d5 144 width = adjusted_mode->crtc_hdisplay;
1d8e1c75
CW		 145 } else {
146 x = y = 0;
aad941d5
VS		 147 width = adjusted_mode->crtc_hdisplay;
148 height = adjusted_mode->crtc_vdisplay;
1d8e1c75
CW		 149 }
150 }
151 break;
152
1d8e1c75
CW		 153 case DRM_MODE_SCALE_FULLSCREEN:
154 x = y = 0;
aad941d5
VS		 155 width = adjusted_mode->crtc_hdisplay;
156 height = adjusted_mode->crtc_vdisplay;
1d8e1c75 157 break;
ab3e67f4
JB		 158
159 default:
160 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
161 return;
1d8e1c75
CW		 162 }
163
164done:
b074cec8
JB		 165 pipe_config->pch_pfit.pos = (x << 16) | y;
166 pipe_config->pch_pfit.size = (width << 16) | height;
fd4daa9c 167 pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0;
1d8e1c75 168}
a9573556 169
2dd24552 170static void
5e7234c9 171centre_horizontally(struct drm_display_mode *adjusted_mode,
2dd24552
JB		 172 int width)
173{
174 u32 border, sync_pos, blank_width, sync_width;
175
176 /* keep the hsync and hblank widths constant */
5e7234c9
VS		 177 sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start;
178 blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start;
2dd24552
JB		 179 sync_pos = (blank_width - sync_width + 1) / 2;
180
aad941d5 181 border = (adjusted_mode->crtc_hdisplay - width + 1) / 2;
2dd24552
JB		 182 border += border & 1; /* make the border even */
183
5e7234c9
VS		 184 adjusted_mode->crtc_hdisplay = width;
185 adjusted_mode->crtc_hblank_start = width + border;
186 adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width;
2dd24552 187
5e7234c9
VS		 188 adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos;
189 adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width;
2dd24552
JB		 190}
191
192static void
5e7234c9 193centre_vertically(struct drm_display_mode *adjusted_mode,
2dd24552
JB		 194 int height)
195{
196 u32 border, sync_pos, blank_width, sync_width;
197
198 /* keep the vsync and vblank widths constant */
5e7234c9
VS		 199 sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start;
200 blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start;
2dd24552
JB		 201 sync_pos = (blank_width - sync_width + 1) / 2;
202
aad941d5 203 border = (adjusted_mode->crtc_vdisplay - height + 1) / 2;
2dd24552 204
5e7234c9
VS		 205 adjusted_mode->crtc_vdisplay = height;
206 adjusted_mode->crtc_vblank_start = height + border;
207 adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width;
2dd24552 208
5e7234c9
VS		 209 adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos;
210 adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width;
2dd24552
JB		 211}
212
213static inline u32 panel_fitter_scaling(u32 source, u32 target)
214{
215 /*
216 * Floating point operation is not supported. So the FACTOR
217 * is defined, which can avoid the floating point computation
218 * when calculating the panel ratio.
219 */
220#define ACCURACY 12
221#define FACTOR (1 << ACCURACY)
222 u32 ratio = source * FACTOR / target;
223 return (FACTOR * ratio + FACTOR/2) / FACTOR;
224}
225
5cec258b 226static void i965_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
DV		 227 u32 *pfit_control)
228{
7c5f93b0 229 const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 230 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
DV		 231 pipe_config->pipe_src_h;
232 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 233 adjusted_mode->crtc_vdisplay;
9084e7d2
DV		 234
235 /* 965+ is easy, it does everything in hw */
236 if (scaled_width > scaled_height)
237 *pfit_control |= PFIT_ENABLE |
238 PFIT_SCALING_PILLAR;
239 else if (scaled_width < scaled_height)
240 *pfit_control |= PFIT_ENABLE |
241 PFIT_SCALING_LETTER;
aad941d5 242 else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w)
9084e7d2
DV		 243 *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO;
244}
245
5cec258b 246static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config,
9084e7d2
DV		 247 u32 *pfit_control, u32 *pfit_pgm_ratios,
248 u32 *border)
249{
2d112de7 250 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
aad941d5 251 u32 scaled_width = adjusted_mode->crtc_hdisplay *
9084e7d2
DV		 252 pipe_config->pipe_src_h;
253 u32 scaled_height = pipe_config->pipe_src_w *
aad941d5 254 adjusted_mode->crtc_vdisplay;
9084e7d2
DV		 255 u32 bits;
256
257 /*
258 * For earlier chips we have to calculate the scaling
259 * ratio by hand and program it into the
260 * PFIT_PGM_RATIO register
261 */
262 if (scaled_width > scaled_height) { /* pillar */
263 centre_horizontally(adjusted_mode,
264 scaled_height /
265 pipe_config->pipe_src_h);
266
267 *border = LVDS_BORDER_ENABLE;
aad941d5 268 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) {
9084e7d2 269 bits = panel_fitter_scaling(pipe_config->pipe_src_h,
aad941d5 270 adjusted_mode->crtc_vdisplay);
9084e7d2
DV		 271
272 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
273 bits << PFIT_VERT_SCALE_SHIFT);
274 *pfit_control |= (PFIT_ENABLE |
275 VERT_INTERP_BILINEAR |
276 HORIZ_INTERP_BILINEAR);
277 }
278 } else if (scaled_width < scaled_height) { /* letter */
279 centre_vertically(adjusted_mode,
280 scaled_width /
281 pipe_config->pipe_src_w);
282
283 *border = LVDS_BORDER_ENABLE;
aad941d5 284 if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
9084e7d2 285 bits = panel_fitter_scaling(pipe_config->pipe_src_w,
aad941d5 286 adjusted_mode->crtc_hdisplay);
9084e7d2
DV		 287
288 *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT |
289 bits << PFIT_VERT_SCALE_SHIFT);
290 *pfit_control |= (PFIT_ENABLE |
291 VERT_INTERP_BILINEAR |
292 HORIZ_INTERP_BILINEAR);
293 }
294 } else {
295 /* Aspects match, Let hw scale both directions */
296 *pfit_control |= (PFIT_ENABLE |
297 VERT_AUTO_SCALE | HORIZ_AUTO_SCALE |
298 VERT_INTERP_BILINEAR |
299 HORIZ_INTERP_BILINEAR);
300 }
301}
302
2dd24552 303void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc,
5cec258b 304 struct intel_crtc_state *pipe_config,
2dd24552
JB		 305 int fitting_mode)
306{
307 struct drm_device *dev = intel_crtc->base.dev;
2dd24552 308 u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0;
7c5f93b0 309 struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode;
2dd24552
JB		 310
311 /* Native modes don't need fitting */
aad941d5
VS		 312 if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w &&
313 adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h)
2dd24552
JB		 314 goto out;
315
316 switch (fitting_mode) {
317 case DRM_MODE_SCALE_CENTER:
318 /*
319 * For centered modes, we have to calculate border widths &
320 * heights and modify the values programmed into the CRTC.
321 */
37327abd
VS		 322 centre_horizontally(adjusted_mode, pipe_config->pipe_src_w);
323 centre_vertically(adjusted_mode, pipe_config->pipe_src_h);
2dd24552
JB		 324 border = LVDS_BORDER_ENABLE;
325 break;
326 case DRM_MODE_SCALE_ASPECT:
327 /* Scale but preserve the aspect ratio */
9084e7d2
DV		 328 if (INTEL_INFO(dev)->gen >= 4)
329 i965_scale_aspect(pipe_config, &pfit_control);
330 else
331 i9xx_scale_aspect(pipe_config, &pfit_control,
332 &pfit_pgm_ratios, &border);
2dd24552 333 break;
2dd24552
JB		 334 case DRM_MODE_SCALE_FULLSCREEN:
335 /*
336 * Full scaling, even if it changes the aspect ratio.
337 * Fortunately this is all done for us in hw.
338 */
aad941d5
VS		 339 if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay ||
340 pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) {
2dd24552
JB		 341 pfit_control |= PFIT_ENABLE;
342 if (INTEL_INFO(dev)->gen >= 4)
343 pfit_control |= PFIT_SCALING_AUTO;
344 else
345 pfit_control |= (VERT_AUTO_SCALE |
346 VERT_INTERP_BILINEAR |
347 HORIZ_AUTO_SCALE |
348 HORIZ_INTERP_BILINEAR);
349 }
350 break;
ab3e67f4
JB		 351 default:
352 WARN(1, "bad panel fit mode: %d\n", fitting_mode);
353 return;
2dd24552
JB		 354 }
355
356 /* 965+ wants fuzzy fitting */
357 /* FIXME: handle multiple panels by failing gracefully */
358 if (INTEL_INFO(dev)->gen >= 4)
359 pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) |
360 PFIT_FILTER_FUZZY);
361
362out:
363 if ((pfit_control & PFIT_ENABLE) == 0) {
364 pfit_control = 0;
365 pfit_pgm_ratios = 0;
366 }
367
6b89cdde
DV		 368 /* Make sure pre-965 set dither correctly for 18bpp panels. */
369 if (INTEL_INFO(dev)->gen < 4 && pipe_config->pipe_bpp == 18)
370 pfit_control |= PANEL_8TO6_DITHER_ENABLE;
371
2deefda5
DV		 372 pipe_config->gmch_pfit.control = pfit_control;
373 pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios;
68fc8742 374 pipe_config->gmch_pfit.lvds_border_bits = border;
2dd24552
JB		 375}
376
525997e0
JN		 377enum drm_connector_status
378intel_panel_detect(struct drm_device *dev)
379{
380 struct drm_i915_private *dev_priv = dev->dev_private;
381
382 /* Assume that the BIOS does not lie through the OpRegion... */
383 if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) {
115719fc 384 return *dev_priv->opregion.lid_state & 0x1 ?
525997e0
JN		 385 connector_status_connected :
386 connector_status_disconnected;
387 }
388
389 switch (i915.panel_ignore_lid) {
390 case -2:
391 return connector_status_connected;
392 case -1:
393 return connector_status_disconnected;
394 default:
395 return connector_status_unknown;
396 }
397}
398
6dda730e
JN		 399/**
400 * scale - scale values from one range to another
401 *
402 * @source_val: value in range [@source_min..@source_max]
403 *
404 * Return @source_val in range [@source_min..@source_max] scaled to range
405 * [@target_min..@target_max].
406 */
407static uint32_t scale(uint32_t source_val,
408 uint32_t source_min, uint32_t source_max,
409 uint32_t target_min, uint32_t target_max)
410{
411 uint64_t target_val;
412
413 WARN_ON(source_min > source_max);
414 WARN_ON(target_min > target_max);
415
416 /* defensive */
417 source_val = clamp(source_val, source_min, source_max);
418
419 /* avoid overflows */
673e7bbd
AE		 420 target_val = DIV_ROUND_CLOSEST_ULL((uint64_t)(source_val - source_min) *
421 (target_max - target_min), source_max - source_min);
6dda730e
JN		 422 target_val += target_min;
423
424 return target_val;
425}
426
427/* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */
428static inline u32 scale_user_to_hw(struct intel_connector *connector,
429 u32 user_level, u32 user_max)
430{
431 struct intel_panel *panel = &connector->panel;
432
433 return scale(user_level, 0, user_max,
434 panel->backlight.min, panel->backlight.max);
435}
436
437/* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result
438 * to [hw_min..hw_max]. */
439static inline u32 clamp_user_to_hw(struct intel_connector *connector,
440 u32 user_level, u32 user_max)
441{
442 struct intel_panel *panel = &connector->panel;
443 u32 hw_level;
444
445 hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max);
446 hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max);
447
448 return hw_level;
449}
450
451/* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */
452static inline u32 scale_hw_to_user(struct intel_connector *connector,
453 u32 hw_level, u32 user_max)
454{
455 struct intel_panel *panel = &connector->panel;
456
457 return scale(hw_level, panel->backlight.min, panel->backlight.max,
458 0, user_max);
459}
460
7bd688cd
JN		 461static u32 intel_panel_compute_brightness(struct intel_connector *connector,
462 u32 val)
7bd90909 463{
7bd688cd 464 struct drm_device *dev = connector->base.dev;
4dca20ef 465 struct drm_i915_private *dev_priv = dev->dev_private;
f91c15e0
JN		 466 struct intel_panel *panel = &connector->panel;
467
468 WARN_ON(panel->backlight.max == 0);
4dca20ef 469
d330a953 470 if (i915.invert_brightness < 0)
4dca20ef
CE		 471 return val;
472
d330a953 473 if (i915.invert_brightness > 0 ||
d6540632 474 dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) {
f91c15e0 475 return panel->backlight.max - val;
d6540632 476 }
7bd90909
CE		 477
478 return val;
479}
480
437b15b8 481static u32 lpt_get_backlight(struct intel_connector *connector)
0b0b053a 482{
96ab4c70 483 struct drm_device *dev = connector->base.dev;
bfd7590d 484 struct drm_i915_private *dev_priv = dev->dev_private;
0b0b053a 485
96ab4c70
DV		 486 return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK;
487}
07bf139b 488
7bd688cd 489static u32 pch_get_backlight(struct intel_connector *connector)
a9573556 490{
7bd688cd 491 struct drm_device *dev = connector->base.dev;
a9573556 492 struct drm_i915_private *dev_priv = dev->dev_private;
8ba2d185 493
7bd688cd
JN		 494 return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
495}
a9573556 496
7bd688cd
JN		 497static u32 i9xx_get_backlight(struct intel_connector *connector)
498{
499 struct drm_device *dev = connector->base.dev;
500 struct drm_i915_private *dev_priv = dev->dev_private;
636baebf 501 struct intel_panel *panel = &connector->panel;
7bd688cd 502 u32 val;
07bf139b 503
7bd688cd
JN		 504 val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK;
505 if (INTEL_INFO(dev)->gen < 4)
506 val >>= 1;
ba3820ad 507
636baebf 508 if (panel->backlight.combination_mode) {
7bd688cd 509 u8 lbpc;
ba3820ad 510
7bd688cd
JN		 511 pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc);
512 val *= lbpc;
a9573556
CW		 513 }
514
7bd688cd
JN		 515 return val;
516}
517
518static u32 _vlv_get_backlight(struct drm_device *dev, enum pipe pipe)
519{
520 struct drm_i915_private *dev_priv = dev->dev_private;
521
23ec0a88
VS		 522 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
523 return 0;
524
7bd688cd
JN		 525 return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK;
526}
527
528static u32 vlv_get_backlight(struct intel_connector *connector)
529{
530 struct drm_device *dev = connector->base.dev;
531 enum pipe pipe = intel_get_pipe_from_connector(connector);
532
533 return _vlv_get_backlight(dev, pipe);
534}
535
0fb890c0
VK		 536static u32 bxt_get_backlight(struct intel_connector *connector)
537{
538 struct drm_device *dev = connector->base.dev;
022e4e52 539 struct intel_panel *panel = &connector->panel;
0fb890c0
VK		 540 struct drm_i915_private *dev_priv = dev->dev_private;
541
022e4e52 542 return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller));
0fb890c0
VK		 543}
544
b029e66f
SK		 545static u32 pwm_get_backlight(struct intel_connector *connector)
546{
547 struct intel_panel *panel = &connector->panel;
548 int duty_ns;
549
550 duty_ns = pwm_get_duty_cycle(panel->backlight.pwm);
551 return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS);
552}
553
7bd688cd
JN		 554static u32 intel_panel_get_backlight(struct intel_connector *connector)
555{
556 struct drm_device *dev = connector->base.dev;
557 struct drm_i915_private *dev_priv = dev->dev_private;
2d72f6c7
VS		 558 struct intel_panel *panel = &connector->panel;
559 u32 val = 0;
7bd688cd 560
07f11d49 561 mutex_lock(&dev_priv->backlight_lock);
7bd688cd 562
2d72f6c7 563 if (panel->backlight.enabled) {
5507faeb 564 val = panel->backlight.get(connector);
2d72f6c7
VS		 565 val = intel_panel_compute_brightness(connector, val);
566 }
8ba2d185 567
07f11d49 568 mutex_unlock(&dev_priv->backlight_lock);
8ba2d185 569
a9573556
CW		 570 DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val);
571 return val;
572}
573
437b15b8 574static void lpt_set_backlight(struct intel_connector *connector, u32 level)
f8e10062 575{
96ab4c70 576 struct drm_device *dev = connector->base.dev;
f8e10062
BW		 577 struct drm_i915_private *dev_priv = dev->dev_private;
578 u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK;
579 I915_WRITE(BLC_PWM_PCH_CTL2, val | level);
580}
581
7bd688cd 582static void pch_set_backlight(struct intel_connector *connector, u32 level)
a9573556 583{
7bd688cd 584 struct drm_device *dev = connector->base.dev;
a9573556 585 struct drm_i915_private *dev_priv = dev->dev_private;
7bd688cd
JN		 586 u32 tmp;
587
588 tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK;
589 I915_WRITE(BLC_PWM_CPU_CTL, tmp | level);
a9573556
CW		 590}
591
7bd688cd 592static void i9xx_set_backlight(struct intel_connector *connector, u32 level)
a9573556 593{
7bd688cd 594 struct drm_device *dev = connector->base.dev;
a9573556 595 struct drm_i915_private *dev_priv = dev->dev_private;
f91c15e0 596 struct intel_panel *panel = &connector->panel;
b329b328 597 u32 tmp, mask;
ba3820ad 598
f91c15e0
JN		 599 WARN_ON(panel->backlight.max == 0);
600
636baebf 601 if (panel->backlight.combination_mode) {
ba3820ad
TI		 602 u8 lbpc;
603
f91c15e0 604 lbpc = level * 0xfe / panel->backlight.max + 1;
ba3820ad
TI		 605 level /= lbpc;
606 pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc);
607 }
608
b329b328
JN		 609 if (IS_GEN4(dev)) {
610 mask = BACKLIGHT_DUTY_CYCLE_MASK;
611 } else {
a9573556 612 level <<= 1;
b329b328
JN		 613 mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV;
614 }
7bd688cd 615
b329b328 616 tmp = I915_READ(BLC_PWM_CTL) & ~mask;
7bd688cd
JN		 617 I915_WRITE(BLC_PWM_CTL, tmp | level);
618}
619
620static void vlv_set_backlight(struct intel_connector *connector, u32 level)
621{
622 struct drm_device *dev = connector->base.dev;
623 struct drm_i915_private *dev_priv = dev->dev_private;
624 enum pipe pipe = intel_get_pipe_from_connector(connector);
625 u32 tmp;
626
23ec0a88
VS		 627 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
628 return;
629
7bd688cd
JN		 630 tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK;
631 I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level);
632}
633
0fb890c0
VK		 634static void bxt_set_backlight(struct intel_connector *connector, u32 level)
635{
636 struct drm_device *dev = connector->base.dev;
637 struct drm_i915_private *dev_priv = dev->dev_private;
022e4e52 638 struct intel_panel *panel = &connector->panel;
0fb890c0 639
022e4e52 640 I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level);
0fb890c0
VK		 641}
642
b029e66f
SK		 643static void pwm_set_backlight(struct intel_connector *connector, u32 level)
644{
645 struct intel_panel *panel = &connector->panel;
646 int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100);
647
648 pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS);
649}
650
7bd688cd
JN		 651static void
652intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level)
653{
5507faeb 654 struct intel_panel *panel = &connector->panel;
7bd688cd
JN		 655
656 DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level);
657
658 level = intel_panel_compute_brightness(connector, level);
5507faeb 659 panel->backlight.set(connector, level);
a9573556 660}
47356eb6 661
6dda730e
JN		 662/* set backlight brightness to level in range [0..max], scaling wrt hw min */
663static void intel_panel_set_backlight(struct intel_connector *connector,
664 u32 user_level, u32 user_max)
47356eb6 665{
752aa88a 666 struct drm_device *dev = connector->base.dev;
47356eb6 667 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 668 struct intel_panel *panel = &connector->panel;
6dda730e 669 u32 hw_level;
8ba2d185 670
260d8f98 671 if (!panel->backlight.present)
752aa88a
JB		 672 return;
673
07f11d49 674 mutex_lock(&dev_priv->backlight_lock);
d6540632 675
f91c15e0 676 WARN_ON(panel->backlight.max == 0);
d6540632 677
6dda730e
JN		 678 hw_level = scale_user_to_hw(connector, user_level, user_max);
679 panel->backlight.level = hw_level;
680
681 if (panel->backlight.enabled)
682 intel_panel_actually_set_backlight(connector, hw_level);
683
07f11d49 684 mutex_unlock(&dev_priv->backlight_lock);
6dda730e
JN		 685}
686
687/* set backlight brightness to level in range [0..max], assuming hw min is
688 * respected.
689 */
690void intel_panel_set_backlight_acpi(struct intel_connector *connector,
691 u32 user_level, u32 user_max)
692{
693 struct drm_device *dev = connector->base.dev;
694 struct drm_i915_private *dev_priv = dev->dev_private;
695 struct intel_panel *panel = &connector->panel;
696 enum pipe pipe = intel_get_pipe_from_connector(connector);
697 u32 hw_level;
6dda730e 698
260d8f98
VS		 699 /*
700 * INVALID_PIPE may occur during driver init because
701 * connection_mutex isn't held across the entire backlight
702 * setup + modeset readout, and the BIOS can issue the
703 * requests at any time.
704 */
6dda730e
JN		 705 if (!panel->backlight.present || pipe == INVALID_PIPE)
706 return;
707
07f11d49 708 mutex_lock(&dev_priv->backlight_lock);
6dda730e
JN		 709
710 WARN_ON(panel->backlight.max == 0);
711
712 hw_level = clamp_user_to_hw(connector, user_level, user_max);
713 panel->backlight.level = hw_level;
47356eb6 714
58c68779 715 if (panel->backlight.device)
6dda730e
JN		 716 panel->backlight.device->props.brightness =
717 scale_hw_to_user(connector,
718 panel->backlight.level,
719 panel->backlight.device->props.max_brightness);
b6b3ba5b 720
58c68779 721 if (panel->backlight.enabled)
6dda730e 722 intel_panel_actually_set_backlight(connector, hw_level);
f91c15e0 723
07f11d49 724 mutex_unlock(&dev_priv->backlight_lock);
f52c619a
TI		 725}
726
437b15b8
JN		 727static void lpt_disable_backlight(struct intel_connector *connector)
728{
729 struct drm_device *dev = connector->base.dev;
730 struct drm_i915_private *dev_priv = dev->dev_private;
731 u32 tmp;
732
733 intel_panel_actually_set_backlight(connector, 0);
734
6675bce2
JN		 735 /*
736 * Although we don't support or enable CPU PWM with LPT/SPT based
737 * systems, it may have been enabled prior to loading the
738 * driver. Disable to avoid warnings on LCPLL disable.
739 *
740 * This needs rework if we need to add support for CPU PWM on PCH split
741 * platforms.
742 */
743 tmp = I915_READ(BLC_PWM_CPU_CTL2);
744 if (tmp & BLM_PWM_ENABLE) {
745 DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n");
746 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
747 }
748
437b15b8
JN		 749 tmp = I915_READ(BLC_PWM_PCH_CTL1);
750 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
751}
752
7bd688cd
JN		 753static void pch_disable_backlight(struct intel_connector *connector)
754{
755 struct drm_device *dev = connector->base.dev;
756 struct drm_i915_private *dev_priv = dev->dev_private;
757 u32 tmp;
758
3bd712e5
JN		 759 intel_panel_actually_set_backlight(connector, 0);
760
7bd688cd
JN		 761 tmp = I915_READ(BLC_PWM_CPU_CTL2);
762 I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE);
763
764 tmp = I915_READ(BLC_PWM_PCH_CTL1);
765 I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE);
766}
767
3bd712e5
JN		 768static void i9xx_disable_backlight(struct intel_connector *connector)
769{
770 intel_panel_actually_set_backlight(connector, 0);
771}
772
7bd688cd
JN		 773static void i965_disable_backlight(struct intel_connector *connector)
774{
775 struct drm_device *dev = connector->base.dev;
776 struct drm_i915_private *dev_priv = dev->dev_private;
777 u32 tmp;
778
3bd712e5
JN		 779 intel_panel_actually_set_backlight(connector, 0);
780
7bd688cd
JN		 781 tmp = I915_READ(BLC_PWM_CTL2);
782 I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE);
783}
784
785static void vlv_disable_backlight(struct intel_connector *connector)
786{
787 struct drm_device *dev = connector->base.dev;
788 struct drm_i915_private *dev_priv = dev->dev_private;
789 enum pipe pipe = intel_get_pipe_from_connector(connector);
790 u32 tmp;
791
23ec0a88
VS		 792 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
793 return;
794
3bd712e5
JN		 795 intel_panel_actually_set_backlight(connector, 0);
796
7bd688cd
JN		 797 tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe));
798 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE);
799}
800
0fb890c0
VK		 801static void bxt_disable_backlight(struct intel_connector *connector)
802{
803 struct drm_device *dev = connector->base.dev;
804 struct drm_i915_private *dev_priv = dev->dev_private;
022e4e52
SK		 805 struct intel_panel *panel = &connector->panel;
806 u32 tmp, val;
0fb890c0
VK		 807
808 intel_panel_actually_set_backlight(connector, 0);
809
022e4e52
SK		 810 tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
811 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
812 tmp & ~BXT_BLC_PWM_ENABLE);
813
814 if (panel->backlight.controller == 1) {
815 val = I915_READ(UTIL_PIN_CTL);
816 val &= ~UTIL_PIN_ENABLE;
817 I915_WRITE(UTIL_PIN_CTL, val);
818 }
0fb890c0
VK		 819}
820
b029e66f
SK		 821static void pwm_disable_backlight(struct intel_connector *connector)
822{
823 struct intel_panel *panel = &connector->panel;
824
825 /* Disable the backlight */
826 pwm_config(panel->backlight.pwm, 0, CRC_PMIC_PWM_PERIOD_NS);
827 usleep_range(2000, 3000);
828 pwm_disable(panel->backlight.pwm);
829}
830
752aa88a 831void intel_panel_disable_backlight(struct intel_connector *connector)
f52c619a 832{
752aa88a 833 struct drm_device *dev = connector->base.dev;
f52c619a 834 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 835 struct intel_panel *panel = &connector->panel;
8ba2d185 836
260d8f98 837 if (!panel->backlight.present)
752aa88a
JB		 838 return;
839
3f577573 840 /*
5389e916 841 * Do not disable backlight on the vga_switcheroo path. When switching
3f577573
JN		 842 * away from i915, the other client may depend on i915 to handle the
843 * backlight. This will leave the backlight on unnecessarily when
844 * another client is not activated.
845 */
846 if (dev->switch_power_state == DRM_SWITCH_POWER_CHANGING) {
847 DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n");
848 return;
849 }
850
07f11d49 851 mutex_lock(&dev_priv->backlight_lock);
47356eb6 852
ab656bb9
JN		 853 if (panel->backlight.device)
854 panel->backlight.device->props.power = FB_BLANK_POWERDOWN;
58c68779 855 panel->backlight.enabled = false;
5507faeb 856 panel->backlight.disable(connector);
24ded204 857
07f11d49 858 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd 859}
24ded204 860
437b15b8 861static void lpt_enable_backlight(struct intel_connector *connector)
96ab4c70
DV		 862{
863 struct drm_device *dev = connector->base.dev;
864 struct drm_i915_private *dev_priv = dev->dev_private;
865 struct intel_panel *panel = &connector->panel;
866 u32 pch_ctl1, pch_ctl2;
867
868 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
869 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
870 DRM_DEBUG_KMS("pch backlight already enabled\n");
871 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
872 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
873 }
24ded204 874
96ab4c70
DV		 875 pch_ctl2 = panel->backlight.max << 16;
876 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
a4f32fc3 877
96ab4c70
DV		 878 pch_ctl1 = 0;
879 if (panel->backlight.active_low_pwm)
880 pch_ctl1 |= BLM_PCH_POLARITY;
8ba2d185 881
e6b2627c
JN		 882 /* After LPT, override is the default. */
883 if (HAS_PCH_LPT(dev_priv))
884 pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE;
96ab4c70
DV		 885
886 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
887 POSTING_READ(BLC_PWM_PCH_CTL1);
888 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
889
890 /* This won't stick until the above enable. */
891 intel_panel_actually_set_backlight(connector, panel->backlight.level);
47356eb6
CW		 892}
893
7bd688cd
JN		 894static void pch_enable_backlight(struct intel_connector *connector)
895{
896 struct drm_device *dev = connector->base.dev;
897 struct drm_i915_private *dev_priv = dev->dev_private;
3bd712e5 898 struct intel_panel *panel = &connector->panel;
7bd688cd
JN		 899 enum pipe pipe = intel_get_pipe_from_connector(connector);
900 enum transcoder cpu_transcoder =
901 intel_pipe_to_cpu_transcoder(dev_priv, pipe);
b35684b8 902 u32 cpu_ctl2, pch_ctl1, pch_ctl2;
7bd688cd 903
b35684b8
JN		 904 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
905 if (cpu_ctl2 & BLM_PWM_ENABLE) {
813008cd 906 DRM_DEBUG_KMS("cpu backlight already enabled\n");
b35684b8
JN		 907 cpu_ctl2 &= ~BLM_PWM_ENABLE;
908 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
909 }
7bd688cd 910
b35684b8
JN		 911 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
912 if (pch_ctl1 & BLM_PCH_PWM_ENABLE) {
913 DRM_DEBUG_KMS("pch backlight already enabled\n");
914 pch_ctl1 &= ~BLM_PCH_PWM_ENABLE;
915 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
916 }
7bd688cd
JN		 917
918 if (cpu_transcoder == TRANSCODER_EDP)
b35684b8 919 cpu_ctl2 = BLM_TRANSCODER_EDP;
7bd688cd 920 else
b35684b8
JN		 921 cpu_ctl2 = BLM_PIPE(cpu_transcoder);
922 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2);
7bd688cd 923 POSTING_READ(BLC_PWM_CPU_CTL2);
b35684b8 924 I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE);
3bd712e5 925
b35684b8 926 /* This won't stick until the above enable. */
3bd712e5 927 intel_panel_actually_set_backlight(connector, panel->backlight.level);
b35684b8
JN		 928
929 pch_ctl2 = panel->backlight.max << 16;
930 I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2);
931
b35684b8
JN		 932 pch_ctl1 = 0;
933 if (panel->backlight.active_low_pwm)
934 pch_ctl1 |= BLM_PCH_POLARITY;
96ab4c70 935
b35684b8
JN		 936 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1);
937 POSTING_READ(BLC_PWM_PCH_CTL1);
938 I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE);
3bd712e5
JN		 939}
940
941static void i9xx_enable_backlight(struct intel_connector *connector)
942{
b35684b8
JN		 943 struct drm_device *dev = connector->base.dev;
944 struct drm_i915_private *dev_priv = dev->dev_private;
3bd712e5 945 struct intel_panel *panel = &connector->panel;
b35684b8
JN		 946 u32 ctl, freq;
947
948 ctl = I915_READ(BLC_PWM_CTL);
949 if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) {
813008cd 950 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 951 I915_WRITE(BLC_PWM_CTL, 0);
952 }
3bd712e5 953
b35684b8
JN		 954 freq = panel->backlight.max;
955 if (panel->backlight.combination_mode)
956 freq /= 0xff;
957
958 ctl = freq << 17;
b6ab66aa 959 if (panel->backlight.combination_mode)
b35684b8
JN		 960 ctl |= BLM_LEGACY_MODE;
961 if (IS_PINEVIEW(dev) && panel->backlight.active_low_pwm)
962 ctl |= BLM_POLARITY_PNV;
963
964 I915_WRITE(BLC_PWM_CTL, ctl);
965 POSTING_READ(BLC_PWM_CTL);
966
967 /* XXX: combine this into above write? */
3bd712e5 968 intel_panel_actually_set_backlight(connector, panel->backlight.level);
2059ac3b
JN		 969
970 /*
971 * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is
972 * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2
973 * that has backlight.
974 */
975 if (IS_GEN2(dev))
976 I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE);
7bd688cd 977}
8ba2d185 978
7bd688cd
JN		 979static void i965_enable_backlight(struct intel_connector *connector)
980{
981 struct drm_device *dev = connector->base.dev;
982 struct drm_i915_private *dev_priv = dev->dev_private;
3bd712e5 983 struct intel_panel *panel = &connector->panel;
7bd688cd 984 enum pipe pipe = intel_get_pipe_from_connector(connector);
b35684b8 985 u32 ctl, ctl2, freq;
7bd688cd 986
b35684b8
JN		 987 ctl2 = I915_READ(BLC_PWM_CTL2);
988 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 989 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 990 ctl2 &= ~BLM_PWM_ENABLE;
991 I915_WRITE(BLC_PWM_CTL2, ctl2);
992 }
7bd688cd 993
b35684b8
JN		 994 freq = panel->backlight.max;
995 if (panel->backlight.combination_mode)
996 freq /= 0xff;
7bd688cd 997
b35684b8
JN		 998 ctl = freq << 16;
999 I915_WRITE(BLC_PWM_CTL, ctl);
3bd712e5 1000
b35684b8
JN		 1001 ctl2 = BLM_PIPE(pipe);
1002 if (panel->backlight.combination_mode)
1003 ctl2 |= BLM_COMBINATION_MODE;
1004 if (panel->backlight.active_low_pwm)
1005 ctl2 |= BLM_POLARITY_I965;
1006 I915_WRITE(BLC_PWM_CTL2, ctl2);
1007 POSTING_READ(BLC_PWM_CTL2);
1008 I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE);
2e7eeeb5
JN		 1009
1010 intel_panel_actually_set_backlight(connector, panel->backlight.level);
7bd688cd
JN		 1011}
1012
1013static void vlv_enable_backlight(struct intel_connector *connector)
1014{
1015 struct drm_device *dev = connector->base.dev;
1016 struct drm_i915_private *dev_priv = dev->dev_private;
3bd712e5 1017 struct intel_panel *panel = &connector->panel;
7bd688cd 1018 enum pipe pipe = intel_get_pipe_from_connector(connector);
b35684b8 1019 u32 ctl, ctl2;
7bd688cd 1020
23ec0a88
VS		 1021 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
1022 return;
1023
b35684b8
JN		 1024 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
1025 if (ctl2 & BLM_PWM_ENABLE) {
813008cd 1026 DRM_DEBUG_KMS("backlight already enabled\n");
b35684b8
JN		 1027 ctl2 &= ~BLM_PWM_ENABLE;
1028 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
1029 }
7bd688cd 1030
b35684b8
JN		 1031 ctl = panel->backlight.max << 16;
1032 I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl);
7bd688cd 1033
b35684b8
JN		 1034 /* XXX: combine this into above write? */
1035 intel_panel_actually_set_backlight(connector, panel->backlight.level);
7bd688cd 1036
b35684b8
JN		 1037 ctl2 = 0;
1038 if (panel->backlight.active_low_pwm)
1039 ctl2 |= BLM_POLARITY_I965;
1040 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2);
7bd688cd 1041 POSTING_READ(VLV_BLC_PWM_CTL2(pipe));
b35684b8 1042 I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE);
47356eb6
CW		 1043}
1044
0fb890c0
VK		 1045static void bxt_enable_backlight(struct intel_connector *connector)
1046{
1047 struct drm_device *dev = connector->base.dev;
1048 struct drm_i915_private *dev_priv = dev->dev_private;
1049 struct intel_panel *panel = &connector->panel;
022e4e52
SK		 1050 enum pipe pipe = intel_get_pipe_from_connector(connector);
1051 u32 pwm_ctl, val;
1052
1053 /* To use 2nd set of backlight registers, utility pin has to be
1054 * enabled with PWM mode.
1055 * The field should only be changed when the utility pin is disabled
1056 */
1057 if (panel->backlight.controller == 1) {
1058 val = I915_READ(UTIL_PIN_CTL);
1059 if (val & UTIL_PIN_ENABLE) {
1060 DRM_DEBUG_KMS("util pin already enabled\n");
1061 val &= ~UTIL_PIN_ENABLE;
1062 I915_WRITE(UTIL_PIN_CTL, val);
1063 }
0fb890c0 1064
022e4e52
SK		 1065 val = 0;
1066 if (panel->backlight.util_pin_active_low)
1067 val |= UTIL_PIN_POLARITY;
1068 I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) |
1069 UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE);
1070 }
1071
1072 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
0fb890c0
VK		 1073 if (pwm_ctl & BXT_BLC_PWM_ENABLE) {
1074 DRM_DEBUG_KMS("backlight already enabled\n");
1075 pwm_ctl &= ~BXT_BLC_PWM_ENABLE;
022e4e52
SK		 1076 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1077 pwm_ctl);
0fb890c0
VK		 1078 }
1079
022e4e52
SK		 1080 I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller),
1081 panel->backlight.max);
0fb890c0
VK		 1082
1083 intel_panel_actually_set_backlight(connector, panel->backlight.level);
1084
1085 pwm_ctl = 0;
1086 if (panel->backlight.active_low_pwm)
1087 pwm_ctl |= BXT_BLC_PWM_POLARITY;
1088
022e4e52
SK		 1089 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl);
1090 POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1091 I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller),
1092 pwm_ctl | BXT_BLC_PWM_ENABLE);
0fb890c0
VK		 1093}
1094
b029e66f
SK		 1095static void pwm_enable_backlight(struct intel_connector *connector)
1096{
1097 struct intel_panel *panel = &connector->panel;
1098
1099 pwm_enable(panel->backlight.pwm);
1100 intel_panel_actually_set_backlight(connector, panel->backlight.level);
1101}
1102
752aa88a 1103void intel_panel_enable_backlight(struct intel_connector *connector)
47356eb6 1104{
752aa88a 1105 struct drm_device *dev = connector->base.dev;
47356eb6 1106 struct drm_i915_private *dev_priv = dev->dev_private;
58c68779 1107 struct intel_panel *panel = &connector->panel;
752aa88a 1108 enum pipe pipe = intel_get_pipe_from_connector(connector);
8ba2d185 1109
260d8f98 1110 if (!panel->backlight.present)
752aa88a
JB		 1111 return;
1112
6f2bcceb 1113 DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe));
540b5d02 1114
07f11d49 1115 mutex_lock(&dev_priv->backlight_lock);
47356eb6 1116
f91c15e0
JN		 1117 WARN_ON(panel->backlight.max == 0);
1118
13f3fbe8 1119 if (panel->backlight.level <= panel->backlight.min) {
f91c15e0 1120 panel->backlight.level = panel->backlight.max;
58c68779
JN		 1121 if (panel->backlight.device)
1122 panel->backlight.device->props.brightness =
6dda730e
JN		 1123 scale_hw_to_user(connector,
1124 panel->backlight.level,
1125 panel->backlight.device->props.max_brightness);
b6b3ba5b 1126 }
47356eb6 1127
5507faeb 1128 panel->backlight.enable(connector);
58c68779 1129 panel->backlight.enabled = true;
ab656bb9
JN		 1130 if (panel->backlight.device)
1131 panel->backlight.device->props.power = FB_BLANK_UNBLANK;
8ba2d185 1132
07f11d49 1133 mutex_unlock(&dev_priv->backlight_lock);
47356eb6
CW		 1134}
1135
912e8b12 1136#if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE)
db31af1d 1137static int intel_backlight_device_update_status(struct backlight_device *bd)
aaa6fd2a 1138{
752aa88a 1139 struct intel_connector *connector = bl_get_data(bd);
ab656bb9 1140 struct intel_panel *panel = &connector->panel;
752aa88a
JB		 1141 struct drm_device *dev = connector->base.dev;
1142
51fd371b 1143 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
540b5d02
CW		 1144 DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n",
1145 bd->props.brightness, bd->props.max_brightness);
752aa88a 1146 intel_panel_set_backlight(connector, bd->props.brightness,
d6540632 1147 bd->props.max_brightness);
ab656bb9
JN		 1148
1149 /*
1150 * Allow flipping bl_power as a sub-state of enabled. Sadly the
1151 * backlight class device does not make it easy to to differentiate
1152 * between callbacks for brightness and bl_power, so our backlight_power
1153 * callback needs to take this into account.
1154 */
1155 if (panel->backlight.enabled) {
5507faeb 1156 if (panel->backlight.power) {
e6755fb7
JN		 1157 bool enable = bd->props.power == FB_BLANK_UNBLANK &&
1158 bd->props.brightness != 0;
5507faeb 1159 panel->backlight.power(connector, enable);
ab656bb9
JN		 1160 }
1161 } else {
1162 bd->props.power = FB_BLANK_POWERDOWN;
1163 }
1164
51fd371b 1165 drm_modeset_unlock(&dev->mode_config.connection_mutex);
aaa6fd2a
MG		 1166 return 0;
1167}
1168
db31af1d 1169static int intel_backlight_device_get_brightness(struct backlight_device *bd)
aaa6fd2a 1170{
752aa88a
JB		 1171 struct intel_connector *connector = bl_get_data(bd);
1172 struct drm_device *dev = connector->base.dev;
c8c8fb33 1173 struct drm_i915_private *dev_priv = dev->dev_private;
6dda730e 1174 u32 hw_level;
7bd688cd 1175 int ret;
752aa88a 1176
c8c8fb33 1177 intel_runtime_pm_get(dev_priv);
51fd371b 1178 drm_modeset_lock(&dev->mode_config.connection_mutex, NULL);
6dda730e
JN		 1179
1180 hw_level = intel_panel_get_backlight(connector);
1181 ret = scale_hw_to_user(connector, hw_level, bd->props.max_brightness);
1182
51fd371b 1183 drm_modeset_unlock(&dev->mode_config.connection_mutex);
c8c8fb33 1184 intel_runtime_pm_put(dev_priv);
752aa88a 1185
7bd688cd 1186 return ret;
aaa6fd2a
MG		 1187}
1188
db31af1d
JN		 1189static const struct backlight_ops intel_backlight_device_ops = {
1190 .update_status = intel_backlight_device_update_status,
1191 .get_brightness = intel_backlight_device_get_brightness,
aaa6fd2a
MG		 1192};
1193
db31af1d 1194static int intel_backlight_device_register(struct intel_connector *connector)
aaa6fd2a 1195{
58c68779 1196 struct intel_panel *panel = &connector->panel;
aaa6fd2a 1197 struct backlight_properties props;
aaa6fd2a 1198
58c68779 1199 if (WARN_ON(panel->backlight.device))
dc652f90
JN		 1200 return -ENODEV;
1201
0962c3c9
VS		 1202 if (!panel->backlight.present)
1203 return 0;
1204
6dda730e 1205 WARN_ON(panel->backlight.max == 0);
7bd688cd 1206
af437cfd 1207 memset(&props, 0, sizeof(props));
aaa6fd2a 1208 props.type = BACKLIGHT_RAW;
6dda730e
JN		 1209
1210 /*
1211 * Note: Everything should work even if the backlight device max
1212 * presented to the userspace is arbitrarily chosen.
1213 */
7bd688cd 1214 props.max_brightness = panel->backlight.max;
6dda730e
JN		 1215 props.brightness = scale_hw_to_user(connector,
1216 panel->backlight.level,
1217 props.max_brightness);
58c68779 1218
ab656bb9
JN		 1219 if (panel->backlight.enabled)
1220 props.power = FB_BLANK_UNBLANK;
1221 else
1222 props.power = FB_BLANK_POWERDOWN;
1223
58c68779
JN		 1224 /*
1225 * Note: using the same name independent of the connector prevents
1226 * registration of multiple backlight devices in the driver.
1227 */
1228 panel->backlight.device =
aaa6fd2a 1229 backlight_device_register("intel_backlight",
db31af1d
JN		 1230 connector->base.kdev,
1231 connector,
1232 &intel_backlight_device_ops, &props);
aaa6fd2a 1233
58c68779 1234 if (IS_ERR(panel->backlight.device)) {
aaa6fd2a 1235 DRM_ERROR("Failed to register backlight: %ld\n",
58c68779
JN		 1236 PTR_ERR(panel->backlight.device));
1237 panel->backlight.device = NULL;
aaa6fd2a
MG		 1238 return -ENODEV;
1239 }
0962c3c9
VS		 1240
1241 DRM_DEBUG_KMS("Connector %s backlight sysfs interface registered\n",
1242 connector->base.name);
1243
aaa6fd2a
MG		 1244 return 0;
1245}
1246
db31af1d 1247static void intel_backlight_device_unregister(struct intel_connector *connector)
aaa6fd2a 1248{
58c68779
JN		 1249 struct intel_panel *panel = &connector->panel;
1250
1251 if (panel->backlight.device) {
1252 backlight_device_unregister(panel->backlight.device);
1253 panel->backlight.device = NULL;
dc652f90 1254 }
aaa6fd2a 1255}
db31af1d
JN		 1256#else /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1257static int intel_backlight_device_register(struct intel_connector *connector)
1258{
1259 return 0;
1260}
1261static void intel_backlight_device_unregister(struct intel_connector *connector)
1262{
1263}
1264#endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */
1265
2dd6982e
JN		 1266/*
1267 * BXT: PWM clock frequency = 19.2 MHz.
1268 */
1269static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1270{
1271 return KHz(19200) / pwm_freq_hz;
1272}
1273
f91c15e0 1274/*
aa17cdb4
JN		 1275 * SPT: This value represents the period of the PWM stream in clock periods
1276 * multiplied by 16 (default increment) or 128 (alternate increment selected in
1277 * SCHICKEN_1 bit 0). PWM clock is 24 MHz.
1278 */
1279static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1280{
1281 struct drm_device *dev = connector->base.dev;
1282 struct drm_i915_private *dev_priv = dev->dev_private;
1283 u32 mul, clock;
1284
1285 if (I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY)
1286 mul = 128;
1287 else
1288 mul = 16;
1289
1290 clock = MHz(24);
1291
1292 return clock / (pwm_freq_hz * mul);
1293}
1294
1295/*
1296 * LPT: This value represents the period of the PWM stream in clock periods
1297 * multiplied by 128 (default increment) or 16 (alternate increment, selected in
1298 * LPT SOUTH_CHICKEN2 register bit 5).
1299 */
1300static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1301{
1302 struct drm_device *dev = connector->base.dev;
1303 struct drm_i915_private *dev_priv = dev->dev_private;
1304 u32 mul, clock;
1305
1306 if (I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY)
1307 mul = 16;
1308 else
1309 mul = 128;
1310
1311 if (dev_priv->pch_id == INTEL_PCH_LPT_DEVICE_ID_TYPE)
1312 clock = MHz(135); /* LPT:H */
1313 else
1314 clock = MHz(24); /* LPT:LP */
1315
1316 return clock / (pwm_freq_hz * mul);
1317}
1318
1319/*
1320 * ILK/SNB/IVB: This value represents the period of the PWM stream in PCH
1321 * display raw clocks multiplied by 128.
1322 */
1323static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1324{
1325 struct drm_device *dev = connector->base.dev;
1326 int clock = MHz(intel_pch_rawclk(dev));
1327
1328 return clock / (pwm_freq_hz * 128);
1329}
1330
1331/*
1332 * Gen2: This field determines the number of time base events (display core
1333 * clock frequency/32) in total for a complete cycle of modulated backlight
1334 * control.
f91c15e0 1335 *
aa17cdb4
JN		 1336 * Gen3: A time base event equals the display core clock ([DevPNV] HRAW clock)
1337 * divided by 32.
1338 */
1339static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1340{
1341 struct drm_device *dev = connector->base.dev;
1342 struct drm_i915_private *dev_priv = dev->dev_private;
1343 int clock;
1344
1345 if (IS_PINEVIEW(dev))
245f5868 1346 clock = MHz(intel_hrawclk(dev));
aa17cdb4
JN		 1347 else
1348 clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
1349
1350 return clock / (pwm_freq_hz * 32);
1351}
1352
1353/*
1354 * Gen4: This value represents the period of the PWM stream in display core
83d83392
VS		 1355 * clocks ([DevCTG] HRAW clocks) multiplied by 128.
1356 *
aa17cdb4
JN		 1357 */
1358static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1359{
1360 struct drm_device *dev = connector->base.dev;
1361 struct drm_i915_private *dev_priv = dev->dev_private;
83d83392
VS		 1362 int clock;
1363
1364 if (IS_G4X(dev_priv))
1365 clock = MHz(intel_hrawclk(dev));
1366 else
1367 clock = 1000 * dev_priv->display.get_display_clock_speed(dev);
aa17cdb4
JN		 1368
1369 return clock / (pwm_freq_hz * 128);
1370}
1371
1372/*
1373 * VLV: This value represents the period of the PWM stream in display core
1374 * clocks ([DevCTG] 200MHz HRAW clocks) multiplied by 128 or 25MHz S0IX clocks
1375 * multiplied by 16. CHV uses a 19.2MHz S0IX clock.
1376 */
1377static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz)
1378{
1379 struct drm_device *dev = connector->base.dev;
1380 struct drm_i915_private *dev_priv = dev->dev_private;
1381 int clock;
1382
1383 if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) {
1384 if (IS_CHERRYVIEW(dev))
1385 return KHz(19200) / (pwm_freq_hz * 16);
1386 else
1387 return MHz(25) / (pwm_freq_hz * 16);
1388 } else {
1389 clock = intel_hrawclk(dev);
1390 return MHz(clock) / (pwm_freq_hz * 128);
1391 }
1392}
1393
1394static u32 get_backlight_max_vbt(struct intel_connector *connector)
1395{
1396 struct drm_device *dev = connector->base.dev;
1397 struct drm_i915_private *dev_priv = dev->dev_private;
5507faeb 1398 struct intel_panel *panel = &connector->panel;
aa17cdb4
JN		 1399 u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz;
1400 u32 pwm;
1401
5075222b
JN		 1402 if (!panel->backlight.hz_to_pwm) {
1403 DRM_DEBUG_KMS("backlight frequency conversion not supported\n");
aa17cdb4
JN		 1404 return 0;
1405 }
1406
5075222b
JN		 1407 if (pwm_freq_hz) {
1408 DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n",
1409 pwm_freq_hz);
1410 } else {
1411 pwm_freq_hz = 200;
1412 DRM_DEBUG_KMS("default backlight frequency %u Hz\n",
1413 pwm_freq_hz);
aa17cdb4
JN		 1414 }
1415
5507faeb 1416 pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz);
aa17cdb4
JN		 1417 if (!pwm) {
1418 DRM_DEBUG_KMS("backlight frequency conversion failed\n");
1419 return 0;
1420 }
1421
aa17cdb4
JN		 1422 return pwm;
1423}
1424
1425/*
1426 * Note: The setup hooks can't assume pipe is set!
f91c15e0 1427 */
6dda730e
JN		 1428static u32 get_backlight_min_vbt(struct intel_connector *connector)
1429{
1430 struct drm_device *dev = connector->base.dev;
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 struct intel_panel *panel = &connector->panel;
e1c412e7 1433 int min;
6dda730e
JN		 1434
1435 WARN_ON(panel->backlight.max == 0);
1436
e1c412e7
JN		 1437 /*
1438 * XXX: If the vbt value is 255, it makes min equal to max, which leads
1439 * to problems. There are such machines out there. Either our
1440 * interpretation is wrong or the vbt has bogus data. Or both. Safeguard
1441 * against this by letting the minimum be at most (arbitrarily chosen)
1442 * 25% of the max.
1443 */
1444 min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64);
1445 if (min != dev_priv->vbt.backlight.min_brightness) {
1446 DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n",
1447 dev_priv->vbt.backlight.min_brightness, min);
1448 }
1449
6dda730e 1450 /* vbt value is a coefficient in range [0..255] */
e1c412e7 1451 return scale(min, 0, 255, 0, panel->backlight.max);
6dda730e
JN		 1452}
1453
437b15b8 1454static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused)
aaa6fd2a 1455{
96ab4c70 1456 struct drm_device *dev = connector->base.dev;
aaa6fd2a 1457 struct drm_i915_private *dev_priv = dev->dev_private;
96ab4c70
DV		 1458 struct intel_panel *panel = &connector->panel;
1459 u32 pch_ctl1, pch_ctl2, val;
1460
1461 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1462 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1463
1464 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1465 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4
JN		 1466
1467 if (!panel->backlight.max)
1468 panel->backlight.max = get_backlight_max_vbt(connector);
1469
96ab4c70
DV		 1470 if (!panel->backlight.max)
1471 return -ENODEV;
1472
6dda730e
JN		 1473 panel->backlight.min = get_backlight_min_vbt(connector);
1474
437b15b8 1475 val = lpt_get_backlight(connector);
96ab4c70
DV		 1476 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1477
1478 panel->backlight.enabled = (pch_ctl1 & BLM_PCH_PWM_ENABLE) &&
1479 panel->backlight.level != 0;
1480
1481 return 0;
1482}
1483
6517d273 1484static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1485{
636baebf
JN		 1486 struct drm_device *dev = connector->base.dev;
1487 struct drm_i915_private *dev_priv = dev->dev_private;
7bd688cd 1488 struct intel_panel *panel = &connector->panel;
636baebf 1489 u32 cpu_ctl2, pch_ctl1, pch_ctl2, val;
7bd688cd 1490
636baebf
JN		 1491 pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1);
1492 panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY;
1493
1494 pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2);
1495 panel->backlight.max = pch_ctl2 >> 16;
aa17cdb4
JN		 1496
1497 if (!panel->backlight.max)
1498 panel->backlight.max = get_backlight_max_vbt(connector);
1499
7bd688cd
JN		 1500 if (!panel->backlight.max)
1501 return -ENODEV;
1502
6dda730e
JN		 1503 panel->backlight.min = get_backlight_min_vbt(connector);
1504
7bd688cd
JN		 1505 val = pch_get_backlight(connector);
1506 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1507
636baebf
JN		 1508 cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2);
1509 panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) &&
1510 (pch_ctl1 & BLM_PCH_PWM_ENABLE) && panel->backlight.level != 0;
1511
7bd688cd
JN		 1512 return 0;
1513}
1514
6517d273 1515static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1516{
636baebf
JN		 1517 struct drm_device *dev = connector->base.dev;
1518 struct drm_i915_private *dev_priv = dev->dev_private;
7bd688cd 1519 struct intel_panel *panel = &connector->panel;
636baebf
JN		 1520 u32 ctl, val;
1521
1522 ctl = I915_READ(BLC_PWM_CTL);
1523
b6ab66aa 1524 if (IS_GEN2(dev) || IS_I915GM(dev) || IS_I945GM(dev))
636baebf
JN		 1525 panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE;
1526
1527 if (IS_PINEVIEW(dev))
1528 panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV;
1529
1530 panel->backlight.max = ctl >> 17;
aa17cdb4
JN		 1531
1532 if (!panel->backlight.max) {
1533 panel->backlight.max = get_backlight_max_vbt(connector);
1534 panel->backlight.max >>= 1;
1535 }
7bd688cd 1536
7bd688cd
JN		 1537 if (!panel->backlight.max)
1538 return -ENODEV;
1539
aa17cdb4
JN		 1540 if (panel->backlight.combination_mode)
1541 panel->backlight.max *= 0xff;
1542
6dda730e
JN		 1543 panel->backlight.min = get_backlight_min_vbt(connector);
1544
7bd688cd
JN		 1545 val = i9xx_get_backlight(connector);
1546 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1547
636baebf
JN		 1548 panel->backlight.enabled = panel->backlight.level != 0;
1549
7bd688cd
JN		 1550 return 0;
1551}
1552
6517d273 1553static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused)
7bd688cd 1554{
636baebf
JN		 1555 struct drm_device *dev = connector->base.dev;
1556 struct drm_i915_private *dev_priv = dev->dev_private;
7bd688cd 1557 struct intel_panel *panel = &connector->panel;
636baebf
JN		 1558 u32 ctl, ctl2, val;
1559
1560 ctl2 = I915_READ(BLC_PWM_CTL2);
1561 panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE;
1562 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1563
1564 ctl = I915_READ(BLC_PWM_CTL);
1565 panel->backlight.max = ctl >> 16;
aa17cdb4
JN		 1566
1567 if (!panel->backlight.max)
1568 panel->backlight.max = get_backlight_max_vbt(connector);
7bd688cd 1569
7bd688cd
JN		 1570 if (!panel->backlight.max)
1571 return -ENODEV;
1572
aa17cdb4
JN		 1573 if (panel->backlight.combination_mode)
1574 panel->backlight.max *= 0xff;
1575
6dda730e
JN		 1576 panel->backlight.min = get_backlight_min_vbt(connector);
1577
7bd688cd
JN		 1578 val = i9xx_get_backlight(connector);
1579 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1580
636baebf
JN		 1581 panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) &&
1582 panel->backlight.level != 0;
1583
7bd688cd
JN		 1584 return 0;
1585}
1586
6517d273 1587static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe)
7bd688cd
JN		 1588{
1589 struct drm_device *dev = connector->base.dev;
1590 struct drm_i915_private *dev_priv = dev->dev_private;
1591 struct intel_panel *panel = &connector->panel;
636baebf 1592 u32 ctl, ctl2, val;
7bd688cd 1593
6517d273
VS		 1594 if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B))
1595 return -ENODEV;
1596
1597 ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe));
636baebf
JN		 1598 panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965;
1599
6517d273 1600 ctl = I915_READ(VLV_BLC_PWM_CTL(pipe));
636baebf 1601 panel->backlight.max = ctl >> 16;
aa17cdb4
JN		 1602
1603 if (!panel->backlight.max)
1604 panel->backlight.max = get_backlight_max_vbt(connector);
1605
7bd688cd
JN		 1606 if (!panel->backlight.max)
1607 return -ENODEV;
1608
6dda730e
JN		 1609 panel->backlight.min = get_backlight_min_vbt(connector);
1610
6517d273 1611 val = _vlv_get_backlight(dev, pipe);
7bd688cd
JN		 1612 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1613
636baebf
JN		 1614 panel->backlight.enabled = (ctl2 & BLM_PWM_ENABLE) &&
1615 panel->backlight.level != 0;
1616
7bd688cd
JN		 1617 return 0;
1618}
1619
0fb890c0
VK		 1620static int
1621bxt_setup_backlight(struct intel_connector *connector, enum pipe unused)
1622{
1623 struct drm_device *dev = connector->base.dev;
1624 struct drm_i915_private *dev_priv = dev->dev_private;
1625 struct intel_panel *panel = &connector->panel;
1626 u32 pwm_ctl, val;
1627
022e4e52
SK		 1628 /*
1629 * For BXT hard coding the Backlight controller to 0.
1630 * TODO : Read the controller value from VBT and generalize
1631 */
1632 panel->backlight.controller = 0;
0fb890c0 1633
022e4e52
SK		 1634 pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller));
1635
1636 /* Keeping the check if controller 1 is to be programmed.
1637 * This will come into affect once the VBT parsing
1638 * is fixed for controller selection, and controller 1 is used
1639 * for a prticular display configuration.
1640 */
1641 if (panel->backlight.controller == 1) {
1642 val = I915_READ(UTIL_PIN_CTL);
1643 panel->backlight.util_pin_active_low =
1644 val & UTIL_PIN_POLARITY;
1645 }
1646
1647 panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY;
1648 panel->backlight.max =
1649 I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller));
aa17cdb4
JN		 1650
1651 if (!panel->backlight.max)
1652 panel->backlight.max = get_backlight_max_vbt(connector);
1653
0fb890c0
VK		 1654 if (!panel->backlight.max)
1655 return -ENODEV;
1656
1657 val = bxt_get_backlight(connector);
1658 panel->backlight.level = intel_panel_compute_brightness(connector, val);
1659
1660 panel->backlight.enabled = (pwm_ctl & BXT_BLC_PWM_ENABLE) &&
1661 panel->backlight.level != 0;
1662
1663 return 0;
1664}
1665
b029e66f
SK		 1666static int pwm_setup_backlight(struct intel_connector *connector,
1667 enum pipe pipe)
1668{
1669 struct drm_device *dev = connector->base.dev;
1670 struct intel_panel *panel = &connector->panel;
1671 int retval;
1672
1673 /* Get the PWM chip for backlight control */
1674 panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight");
1675 if (IS_ERR(panel->backlight.pwm)) {
1676 DRM_ERROR("Failed to own the pwm chip\n");
1677 panel->backlight.pwm = NULL;
1678 return -ENODEV;
1679 }
1680
1681 retval = pwm_config(panel->backlight.pwm, CRC_PMIC_PWM_PERIOD_NS,
1682 CRC_PMIC_PWM_PERIOD_NS);
1683 if (retval < 0) {
1684 DRM_ERROR("Failed to configure the pwm chip\n");
1685 pwm_put(panel->backlight.pwm);
1686 panel->backlight.pwm = NULL;
1687 return retval;
1688 }
1689
1690 panel->backlight.min = 0; /* 0% */
1691 panel->backlight.max = 100; /* 100% */
1692 panel->backlight.level = DIV_ROUND_UP(
1693 pwm_get_duty_cycle(panel->backlight.pwm) * 100,
1694 CRC_PMIC_PWM_PERIOD_NS);
1695 panel->backlight.enabled = panel->backlight.level != 0;
1696
1697 return 0;
1698}
1699
6517d273 1700int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe)
aaa6fd2a 1701{
db31af1d 1702 struct drm_device *dev = connector->dev;
7bd688cd 1703 struct drm_i915_private *dev_priv = dev->dev_private;
db31af1d 1704 struct intel_connector *intel_connector = to_intel_connector(connector);
58c68779 1705 struct intel_panel *panel = &intel_connector->panel;
7bd688cd 1706 int ret;
db31af1d 1707
c675949e 1708 if (!dev_priv->vbt.backlight.present) {
9c72cc6f
SD		 1709 if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) {
1710 DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n");
1711 } else {
1712 DRM_DEBUG_KMS("no backlight present per VBT\n");
1713 return 0;
1714 }
c675949e
JN		 1715 }
1716
5507faeb
JN		 1717 /* ensure intel_panel has been initialized first */
1718 if (WARN_ON(!panel->backlight.setup))
1719 return -ENODEV;
1720
7bd688cd 1721 /* set level and max in panel struct */
07f11d49 1722 mutex_lock(&dev_priv->backlight_lock);
5507faeb 1723 ret = panel->backlight.setup(intel_connector, pipe);
07f11d49 1724 mutex_unlock(&dev_priv->backlight_lock);
7bd688cd
JN		 1725
1726 if (ret) {
1727 DRM_DEBUG_KMS("failed to setup backlight for connector %s\n",
c23cc417 1728 connector->name);
7bd688cd
JN		 1729 return ret;
1730 }
db31af1d 1731
c91c9f32
JN		 1732 panel->backlight.present = true;
1733
0962c3c9
VS		 1734 DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n",
1735 connector->name,
c445b3b1 1736 panel->backlight.enabled ? "enabled" : "disabled",
0962c3c9 1737 panel->backlight.level, panel->backlight.max);
c445b3b1 1738
aaa6fd2a
MG		 1739 return 0;
1740}
1741
db31af1d 1742void intel_panel_destroy_backlight(struct drm_connector *connector)
aaa6fd2a 1743{
db31af1d 1744 struct intel_connector *intel_connector = to_intel_connector(connector);
c91c9f32 1745 struct intel_panel *panel = &intel_connector->panel;
db31af1d 1746
b029e66f
SK		 1747 /* dispose of the pwm */
1748 if (panel->backlight.pwm)
1749 pwm_put(panel->backlight.pwm);
1750
c91c9f32 1751 panel->backlight.present = false;
aaa6fd2a 1752}
1d508706 1753
7bd688cd 1754/* Set up chip specific backlight functions */
5507faeb
JN		 1755static void
1756intel_panel_init_backlight_funcs(struct intel_panel *panel)
7bd688cd 1757{
5507faeb
JN		 1758 struct intel_connector *intel_connector =
1759 container_of(panel, struct intel_connector, panel);
1760 struct drm_device *dev = intel_connector->base.dev;
7bd688cd
JN		 1761 struct drm_i915_private *dev_priv = dev->dev_private;
1762
0fb890c0 1763 if (IS_BROXTON(dev)) {
5507faeb
JN		 1764 panel->backlight.setup = bxt_setup_backlight;
1765 panel->backlight.enable = bxt_enable_backlight;
1766 panel->backlight.disable = bxt_disable_backlight;
1767 panel->backlight.set = bxt_set_backlight;
1768 panel->backlight.get = bxt_get_backlight;
2dd6982e 1769 panel->backlight.hz_to_pwm = bxt_hz_to_pwm;
437b15b8 1770 } else if (HAS_PCH_LPT(dev) || HAS_PCH_SPT(dev)) {
5507faeb
JN		 1771 panel->backlight.setup = lpt_setup_backlight;
1772 panel->backlight.enable = lpt_enable_backlight;
1773 panel->backlight.disable = lpt_disable_backlight;
1774 panel->backlight.set = lpt_set_backlight;
1775 panel->backlight.get = lpt_get_backlight;
aa17cdb4 1776 if (HAS_PCH_LPT(dev))
5507faeb 1777 panel->backlight.hz_to_pwm = lpt_hz_to_pwm;
aa17cdb4 1778 else
5507faeb 1779 panel->backlight.hz_to_pwm = spt_hz_to_pwm;
96ab4c70 1780 } else if (HAS_PCH_SPLIT(dev)) {
5507faeb
JN		 1781 panel->backlight.setup = pch_setup_backlight;
1782 panel->backlight.enable = pch_enable_backlight;
1783 panel->backlight.disable = pch_disable_backlight;
1784 panel->backlight.set = pch_set_backlight;
1785 panel->backlight.get = pch_get_backlight;
1786 panel->backlight.hz_to_pwm = pch_hz_to_pwm;
7bd688cd 1787 } else if (IS_VALLEYVIEW(dev)) {
b029e66f 1788 if (dev_priv->vbt.has_mipi) {
5507faeb
JN		 1789 panel->backlight.setup = pwm_setup_backlight;
1790 panel->backlight.enable = pwm_enable_backlight;
1791 panel->backlight.disable = pwm_disable_backlight;
1792 panel->backlight.set = pwm_set_backlight;
1793 panel->backlight.get = pwm_get_backlight;
b029e66f 1794 } else {
5507faeb
JN		 1795 panel->backlight.setup = vlv_setup_backlight;
1796 panel->backlight.enable = vlv_enable_backlight;
1797 panel->backlight.disable = vlv_disable_backlight;
1798 panel->backlight.set = vlv_set_backlight;
1799 panel->backlight.get = vlv_get_backlight;
1800 panel->backlight.hz_to_pwm = vlv_hz_to_pwm;
b029e66f 1801 }
7bd688cd 1802 } else if (IS_GEN4(dev)) {
5507faeb
JN		 1803 panel->backlight.setup = i965_setup_backlight;
1804 panel->backlight.enable = i965_enable_backlight;
1805 panel->backlight.disable = i965_disable_backlight;
1806 panel->backlight.set = i9xx_set_backlight;
1807 panel->backlight.get = i9xx_get_backlight;
1808 panel->backlight.hz_to_pwm = i965_hz_to_pwm;
7bd688cd 1809 } else {
5507faeb
JN		 1810 panel->backlight.setup = i9xx_setup_backlight;
1811 panel->backlight.enable = i9xx_enable_backlight;
1812 panel->backlight.disable = i9xx_disable_backlight;
1813 panel->backlight.set = i9xx_set_backlight;
1814 panel->backlight.get = i9xx_get_backlight;
1815 panel->backlight.hz_to_pwm = i9xx_hz_to_pwm;
7bd688cd
JN		 1816 }
1817}
1818
dd06f90e 1819int intel_panel_init(struct intel_panel *panel,
4b6ed685
VK		 1820 struct drm_display_mode *fixed_mode,
1821 struct drm_display_mode *downclock_mode)
1d508706 1822{
5507faeb
JN		 1823 intel_panel_init_backlight_funcs(panel);
1824
dd06f90e 1825 panel->fixed_mode = fixed_mode;
4b6ed685 1826 panel->downclock_mode = downclock_mode;
dd06f90e 1827
1d508706
JN		 1828 return 0;
1829}
1830
1831void intel_panel_fini(struct intel_panel *panel)
1832{
dd06f90e
JN		 1833 struct intel_connector *intel_connector =
1834 container_of(panel, struct intel_connector, panel);
1835
1836 if (panel->fixed_mode)
1837 drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode);
ec9ed197
VK		 1838
1839 if (panel->downclock_mode)
1840 drm_mode_destroy(intel_connector->base.dev,
1841 panel->downclock_mode);
1d508706 1842}
0962c3c9
VS		 1843
1844void intel_backlight_register(struct drm_device *dev)
1845{
1846 struct intel_connector *connector;
1847
1848 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head)
1849 intel_backlight_device_register(connector);
1850}
1851
1852void intel_backlight_unregister(struct drm_device *dev)
1853{
1854 struct intel_connector *connector;
1855
1856 list_for_each_entry(connector, &dev->mode_config.connector_list, base.head)
1857 intel_backlight_device_unregister(connector);
1858}
Ubuntu Artful kernel mirror