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1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
f766093e | 33 | #include <linux/kernel.h> |
7bd90909 | 34 | #include <linux/moduleparam.h> |
b029e66f | 35 | #include <linux/pwm.h> |
1d8e1c75 CW |
36 | #include "intel_drv.h" |
37 | ||
b029e66f SK |
38 | #define CRC_PMIC_PWM_PERIOD_NS 21333 |
39 | ||
1d8e1c75 | 40 | void |
4c6df4b4 | 41 | intel_fixed_panel_mode(const struct drm_display_mode *fixed_mode, |
1d8e1c75 CW |
42 | struct drm_display_mode *adjusted_mode) |
43 | { | |
4c6df4b4 | 44 | drm_mode_copy(adjusted_mode, fixed_mode); |
a52690e4 ID |
45 | |
46 | drm_mode_set_crtcinfo(adjusted_mode, 0); | |
1d8e1c75 CW |
47 | } |
48 | ||
525997e0 JN |
49 | /** |
50 | * intel_find_panel_downclock - find the reduced downclock for LVDS in EDID | |
a318b4c4 | 51 | * @dev_priv: i915 device instance |
525997e0 JN |
52 | * @fixed_mode : panel native mode |
53 | * @connector: LVDS/eDP connector | |
54 | * | |
55 | * Return downclock_avail | |
56 | * Find the reduced downclock for LVDS/eDP in EDID. | |
57 | */ | |
58 | struct drm_display_mode * | |
a318b4c4 | 59 | intel_find_panel_downclock(struct drm_i915_private *dev_priv, |
525997e0 JN |
60 | struct drm_display_mode *fixed_mode, |
61 | struct drm_connector *connector) | |
62 | { | |
63 | struct drm_display_mode *scan, *tmp_mode; | |
64 | int temp_downclock; | |
65 | ||
66 | temp_downclock = fixed_mode->clock; | |
67 | tmp_mode = NULL; | |
68 | ||
69 | list_for_each_entry(scan, &connector->probed_modes, head) { | |
70 | /* | |
71 | * If one mode has the same resolution with the fixed_panel | |
72 | * mode while they have the different refresh rate, it means | |
73 | * that the reduced downclock is found. In such | |
74 | * case we can set the different FPx0/1 to dynamically select | |
75 | * between low and high frequency. | |
76 | */ | |
77 | if (scan->hdisplay == fixed_mode->hdisplay && | |
78 | scan->hsync_start == fixed_mode->hsync_start && | |
79 | scan->hsync_end == fixed_mode->hsync_end && | |
80 | scan->htotal == fixed_mode->htotal && | |
81 | scan->vdisplay == fixed_mode->vdisplay && | |
82 | scan->vsync_start == fixed_mode->vsync_start && | |
83 | scan->vsync_end == fixed_mode->vsync_end && | |
84 | scan->vtotal == fixed_mode->vtotal) { | |
85 | if (scan->clock < temp_downclock) { | |
86 | /* | |
87 | * The downclock is already found. But we | |
88 | * expect to find the lower downclock. | |
89 | */ | |
90 | temp_downclock = scan->clock; | |
91 | tmp_mode = scan; | |
92 | } | |
93 | } | |
94 | } | |
95 | ||
96 | if (temp_downclock < fixed_mode->clock) | |
a318b4c4 | 97 | return drm_mode_duplicate(&dev_priv->drm, tmp_mode); |
525997e0 JN |
98 | else |
99 | return NULL; | |
100 | } | |
101 | ||
1d8e1c75 CW |
102 | /* adjusted_mode has been preset to be the panel's fixed mode */ |
103 | void | |
b074cec8 | 104 | intel_pch_panel_fitting(struct intel_crtc *intel_crtc, |
5cec258b | 105 | struct intel_crtc_state *pipe_config, |
b074cec8 | 106 | int fitting_mode) |
1d8e1c75 | 107 | { |
7c5f93b0 VS |
108 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
109 | int x = 0, y = 0, width = 0, height = 0; | |
1d8e1c75 CW |
110 | |
111 | /* Native modes don't need fitting */ | |
aad941d5 VS |
112 | if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && |
113 | adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) | |
1d8e1c75 CW |
114 | goto done; |
115 | ||
116 | switch (fitting_mode) { | |
117 | case DRM_MODE_SCALE_CENTER: | |
37327abd VS |
118 | width = pipe_config->pipe_src_w; |
119 | height = pipe_config->pipe_src_h; | |
aad941d5 VS |
120 | x = (adjusted_mode->crtc_hdisplay - width + 1)/2; |
121 | y = (adjusted_mode->crtc_vdisplay - height + 1)/2; | |
1d8e1c75 CW |
122 | break; |
123 | ||
124 | case DRM_MODE_SCALE_ASPECT: | |
125 | /* Scale but preserve the aspect ratio */ | |
126 | { | |
aad941d5 | 127 | u32 scaled_width = adjusted_mode->crtc_hdisplay |
9084e7d2 DV |
128 | * pipe_config->pipe_src_h; |
129 | u32 scaled_height = pipe_config->pipe_src_w | |
aad941d5 | 130 | * adjusted_mode->crtc_vdisplay; |
1d8e1c75 | 131 | if (scaled_width > scaled_height) { /* pillar */ |
37327abd | 132 | width = scaled_height / pipe_config->pipe_src_h; |
302983e9 | 133 | if (width & 1) |
0206e353 | 134 | width++; |
aad941d5 | 135 | x = (adjusted_mode->crtc_hdisplay - width + 1) / 2; |
1d8e1c75 | 136 | y = 0; |
aad941d5 | 137 | height = adjusted_mode->crtc_vdisplay; |
1d8e1c75 | 138 | } else if (scaled_width < scaled_height) { /* letter */ |
37327abd | 139 | height = scaled_width / pipe_config->pipe_src_w; |
302983e9 AJ |
140 | if (height & 1) |
141 | height++; | |
aad941d5 | 142 | y = (adjusted_mode->crtc_vdisplay - height + 1) / 2; |
1d8e1c75 | 143 | x = 0; |
aad941d5 | 144 | width = adjusted_mode->crtc_hdisplay; |
1d8e1c75 CW |
145 | } else { |
146 | x = y = 0; | |
aad941d5 VS |
147 | width = adjusted_mode->crtc_hdisplay; |
148 | height = adjusted_mode->crtc_vdisplay; | |
1d8e1c75 CW |
149 | } |
150 | } | |
151 | break; | |
152 | ||
1d8e1c75 CW |
153 | case DRM_MODE_SCALE_FULLSCREEN: |
154 | x = y = 0; | |
aad941d5 VS |
155 | width = adjusted_mode->crtc_hdisplay; |
156 | height = adjusted_mode->crtc_vdisplay; | |
1d8e1c75 | 157 | break; |
ab3e67f4 JB |
158 | |
159 | default: | |
160 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
161 | return; | |
1d8e1c75 CW |
162 | } |
163 | ||
164 | done: | |
b074cec8 JB |
165 | pipe_config->pch_pfit.pos = (x << 16) | y; |
166 | pipe_config->pch_pfit.size = (width << 16) | height; | |
fd4daa9c | 167 | pipe_config->pch_pfit.enabled = pipe_config->pch_pfit.size != 0; |
1d8e1c75 | 168 | } |
a9573556 | 169 | |
2dd24552 | 170 | static void |
5e7234c9 | 171 | centre_horizontally(struct drm_display_mode *adjusted_mode, |
2dd24552 JB |
172 | int width) |
173 | { | |
174 | u32 border, sync_pos, blank_width, sync_width; | |
175 | ||
176 | /* keep the hsync and hblank widths constant */ | |
5e7234c9 VS |
177 | sync_width = adjusted_mode->crtc_hsync_end - adjusted_mode->crtc_hsync_start; |
178 | blank_width = adjusted_mode->crtc_hblank_end - adjusted_mode->crtc_hblank_start; | |
2dd24552 JB |
179 | sync_pos = (blank_width - sync_width + 1) / 2; |
180 | ||
aad941d5 | 181 | border = (adjusted_mode->crtc_hdisplay - width + 1) / 2; |
2dd24552 JB |
182 | border += border & 1; /* make the border even */ |
183 | ||
5e7234c9 VS |
184 | adjusted_mode->crtc_hdisplay = width; |
185 | adjusted_mode->crtc_hblank_start = width + border; | |
186 | adjusted_mode->crtc_hblank_end = adjusted_mode->crtc_hblank_start + blank_width; | |
2dd24552 | 187 | |
5e7234c9 VS |
188 | adjusted_mode->crtc_hsync_start = adjusted_mode->crtc_hblank_start + sync_pos; |
189 | adjusted_mode->crtc_hsync_end = adjusted_mode->crtc_hsync_start + sync_width; | |
2dd24552 JB |
190 | } |
191 | ||
192 | static void | |
5e7234c9 | 193 | centre_vertically(struct drm_display_mode *adjusted_mode, |
2dd24552 JB |
194 | int height) |
195 | { | |
196 | u32 border, sync_pos, blank_width, sync_width; | |
197 | ||
198 | /* keep the vsync and vblank widths constant */ | |
5e7234c9 VS |
199 | sync_width = adjusted_mode->crtc_vsync_end - adjusted_mode->crtc_vsync_start; |
200 | blank_width = adjusted_mode->crtc_vblank_end - adjusted_mode->crtc_vblank_start; | |
2dd24552 JB |
201 | sync_pos = (blank_width - sync_width + 1) / 2; |
202 | ||
aad941d5 | 203 | border = (adjusted_mode->crtc_vdisplay - height + 1) / 2; |
2dd24552 | 204 | |
5e7234c9 VS |
205 | adjusted_mode->crtc_vdisplay = height; |
206 | adjusted_mode->crtc_vblank_start = height + border; | |
207 | adjusted_mode->crtc_vblank_end = adjusted_mode->crtc_vblank_start + blank_width; | |
2dd24552 | 208 | |
5e7234c9 VS |
209 | adjusted_mode->crtc_vsync_start = adjusted_mode->crtc_vblank_start + sync_pos; |
210 | adjusted_mode->crtc_vsync_end = adjusted_mode->crtc_vsync_start + sync_width; | |
2dd24552 JB |
211 | } |
212 | ||
213 | static inline u32 panel_fitter_scaling(u32 source, u32 target) | |
214 | { | |
215 | /* | |
216 | * Floating point operation is not supported. So the FACTOR | |
217 | * is defined, which can avoid the floating point computation | |
218 | * when calculating the panel ratio. | |
219 | */ | |
220 | #define ACCURACY 12 | |
221 | #define FACTOR (1 << ACCURACY) | |
222 | u32 ratio = source * FACTOR / target; | |
223 | return (FACTOR * ratio + FACTOR/2) / FACTOR; | |
224 | } | |
225 | ||
5cec258b | 226 | static void i965_scale_aspect(struct intel_crtc_state *pipe_config, |
9084e7d2 DV |
227 | u32 *pfit_control) |
228 | { | |
7c5f93b0 | 229 | const struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
aad941d5 | 230 | u32 scaled_width = adjusted_mode->crtc_hdisplay * |
9084e7d2 DV |
231 | pipe_config->pipe_src_h; |
232 | u32 scaled_height = pipe_config->pipe_src_w * | |
aad941d5 | 233 | adjusted_mode->crtc_vdisplay; |
9084e7d2 DV |
234 | |
235 | /* 965+ is easy, it does everything in hw */ | |
236 | if (scaled_width > scaled_height) | |
237 | *pfit_control |= PFIT_ENABLE | | |
238 | PFIT_SCALING_PILLAR; | |
239 | else if (scaled_width < scaled_height) | |
240 | *pfit_control |= PFIT_ENABLE | | |
241 | PFIT_SCALING_LETTER; | |
aad941d5 | 242 | else if (adjusted_mode->crtc_hdisplay != pipe_config->pipe_src_w) |
9084e7d2 DV |
243 | *pfit_control |= PFIT_ENABLE | PFIT_SCALING_AUTO; |
244 | } | |
245 | ||
5cec258b | 246 | static void i9xx_scale_aspect(struct intel_crtc_state *pipe_config, |
9084e7d2 DV |
247 | u32 *pfit_control, u32 *pfit_pgm_ratios, |
248 | u32 *border) | |
249 | { | |
2d112de7 | 250 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
aad941d5 | 251 | u32 scaled_width = adjusted_mode->crtc_hdisplay * |
9084e7d2 DV |
252 | pipe_config->pipe_src_h; |
253 | u32 scaled_height = pipe_config->pipe_src_w * | |
aad941d5 | 254 | adjusted_mode->crtc_vdisplay; |
9084e7d2 DV |
255 | u32 bits; |
256 | ||
257 | /* | |
258 | * For earlier chips we have to calculate the scaling | |
259 | * ratio by hand and program it into the | |
260 | * PFIT_PGM_RATIO register | |
261 | */ | |
262 | if (scaled_width > scaled_height) { /* pillar */ | |
263 | centre_horizontally(adjusted_mode, | |
264 | scaled_height / | |
265 | pipe_config->pipe_src_h); | |
266 | ||
267 | *border = LVDS_BORDER_ENABLE; | |
aad941d5 | 268 | if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay) { |
9084e7d2 | 269 | bits = panel_fitter_scaling(pipe_config->pipe_src_h, |
aad941d5 | 270 | adjusted_mode->crtc_vdisplay); |
9084e7d2 DV |
271 | |
272 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
273 | bits << PFIT_VERT_SCALE_SHIFT); | |
274 | *pfit_control |= (PFIT_ENABLE | | |
275 | VERT_INTERP_BILINEAR | | |
276 | HORIZ_INTERP_BILINEAR); | |
277 | } | |
278 | } else if (scaled_width < scaled_height) { /* letter */ | |
279 | centre_vertically(adjusted_mode, | |
280 | scaled_width / | |
281 | pipe_config->pipe_src_w); | |
282 | ||
283 | *border = LVDS_BORDER_ENABLE; | |
aad941d5 | 284 | if (pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { |
9084e7d2 | 285 | bits = panel_fitter_scaling(pipe_config->pipe_src_w, |
aad941d5 | 286 | adjusted_mode->crtc_hdisplay); |
9084e7d2 DV |
287 | |
288 | *pfit_pgm_ratios |= (bits << PFIT_HORIZ_SCALE_SHIFT | | |
289 | bits << PFIT_VERT_SCALE_SHIFT); | |
290 | *pfit_control |= (PFIT_ENABLE | | |
291 | VERT_INTERP_BILINEAR | | |
292 | HORIZ_INTERP_BILINEAR); | |
293 | } | |
294 | } else { | |
295 | /* Aspects match, Let hw scale both directions */ | |
296 | *pfit_control |= (PFIT_ENABLE | | |
297 | VERT_AUTO_SCALE | HORIZ_AUTO_SCALE | | |
298 | VERT_INTERP_BILINEAR | | |
299 | HORIZ_INTERP_BILINEAR); | |
300 | } | |
301 | } | |
302 | ||
2dd24552 | 303 | void intel_gmch_panel_fitting(struct intel_crtc *intel_crtc, |
5cec258b | 304 | struct intel_crtc_state *pipe_config, |
2dd24552 JB |
305 | int fitting_mode) |
306 | { | |
66478475 | 307 | struct drm_i915_private *dev_priv = to_i915(intel_crtc->base.dev); |
2dd24552 | 308 | u32 pfit_control = 0, pfit_pgm_ratios = 0, border = 0; |
7c5f93b0 | 309 | struct drm_display_mode *adjusted_mode = &pipe_config->base.adjusted_mode; |
2dd24552 JB |
310 | |
311 | /* Native modes don't need fitting */ | |
aad941d5 VS |
312 | if (adjusted_mode->crtc_hdisplay == pipe_config->pipe_src_w && |
313 | adjusted_mode->crtc_vdisplay == pipe_config->pipe_src_h) | |
2dd24552 JB |
314 | goto out; |
315 | ||
316 | switch (fitting_mode) { | |
317 | case DRM_MODE_SCALE_CENTER: | |
318 | /* | |
319 | * For centered modes, we have to calculate border widths & | |
320 | * heights and modify the values programmed into the CRTC. | |
321 | */ | |
37327abd VS |
322 | centre_horizontally(adjusted_mode, pipe_config->pipe_src_w); |
323 | centre_vertically(adjusted_mode, pipe_config->pipe_src_h); | |
2dd24552 JB |
324 | border = LVDS_BORDER_ENABLE; |
325 | break; | |
326 | case DRM_MODE_SCALE_ASPECT: | |
327 | /* Scale but preserve the aspect ratio */ | |
66478475 | 328 | if (INTEL_GEN(dev_priv) >= 4) |
9084e7d2 DV |
329 | i965_scale_aspect(pipe_config, &pfit_control); |
330 | else | |
331 | i9xx_scale_aspect(pipe_config, &pfit_control, | |
332 | &pfit_pgm_ratios, &border); | |
2dd24552 | 333 | break; |
2dd24552 JB |
334 | case DRM_MODE_SCALE_FULLSCREEN: |
335 | /* | |
336 | * Full scaling, even if it changes the aspect ratio. | |
337 | * Fortunately this is all done for us in hw. | |
338 | */ | |
aad941d5 VS |
339 | if (pipe_config->pipe_src_h != adjusted_mode->crtc_vdisplay || |
340 | pipe_config->pipe_src_w != adjusted_mode->crtc_hdisplay) { | |
2dd24552 | 341 | pfit_control |= PFIT_ENABLE; |
66478475 | 342 | if (INTEL_GEN(dev_priv) >= 4) |
2dd24552 JB |
343 | pfit_control |= PFIT_SCALING_AUTO; |
344 | else | |
345 | pfit_control |= (VERT_AUTO_SCALE | | |
346 | VERT_INTERP_BILINEAR | | |
347 | HORIZ_AUTO_SCALE | | |
348 | HORIZ_INTERP_BILINEAR); | |
349 | } | |
350 | break; | |
ab3e67f4 JB |
351 | default: |
352 | WARN(1, "bad panel fit mode: %d\n", fitting_mode); | |
353 | return; | |
2dd24552 JB |
354 | } |
355 | ||
356 | /* 965+ wants fuzzy fitting */ | |
357 | /* FIXME: handle multiple panels by failing gracefully */ | |
66478475 | 358 | if (INTEL_GEN(dev_priv) >= 4) |
2dd24552 JB |
359 | pfit_control |= ((intel_crtc->pipe << PFIT_PIPE_SHIFT) | |
360 | PFIT_FILTER_FUZZY); | |
361 | ||
362 | out: | |
363 | if ((pfit_control & PFIT_ENABLE) == 0) { | |
364 | pfit_control = 0; | |
365 | pfit_pgm_ratios = 0; | |
366 | } | |
367 | ||
6b89cdde | 368 | /* Make sure pre-965 set dither correctly for 18bpp panels. */ |
66478475 | 369 | if (INTEL_GEN(dev_priv) < 4 && pipe_config->pipe_bpp == 18) |
6b89cdde DV |
370 | pfit_control |= PANEL_8TO6_DITHER_ENABLE; |
371 | ||
2deefda5 DV |
372 | pipe_config->gmch_pfit.control = pfit_control; |
373 | pipe_config->gmch_pfit.pgm_ratios = pfit_pgm_ratios; | |
68fc8742 | 374 | pipe_config->gmch_pfit.lvds_border_bits = border; |
2dd24552 JB |
375 | } |
376 | ||
525997e0 | 377 | enum drm_connector_status |
1650be74 | 378 | intel_panel_detect(struct drm_i915_private *dev_priv) |
525997e0 | 379 | { |
525997e0 JN |
380 | /* Assume that the BIOS does not lie through the OpRegion... */ |
381 | if (!i915.panel_ignore_lid && dev_priv->opregion.lid_state) { | |
115719fc | 382 | return *dev_priv->opregion.lid_state & 0x1 ? |
525997e0 JN |
383 | connector_status_connected : |
384 | connector_status_disconnected; | |
385 | } | |
386 | ||
387 | switch (i915.panel_ignore_lid) { | |
388 | case -2: | |
389 | return connector_status_connected; | |
390 | case -1: | |
391 | return connector_status_disconnected; | |
392 | default: | |
393 | return connector_status_unknown; | |
394 | } | |
395 | } | |
396 | ||
6dda730e JN |
397 | /** |
398 | * scale - scale values from one range to another | |
399 | * | |
400 | * @source_val: value in range [@source_min..@source_max] | |
401 | * | |
402 | * Return @source_val in range [@source_min..@source_max] scaled to range | |
403 | * [@target_min..@target_max]. | |
404 | */ | |
405 | static uint32_t scale(uint32_t source_val, | |
406 | uint32_t source_min, uint32_t source_max, | |
407 | uint32_t target_min, uint32_t target_max) | |
408 | { | |
409 | uint64_t target_val; | |
410 | ||
411 | WARN_ON(source_min > source_max); | |
412 | WARN_ON(target_min > target_max); | |
413 | ||
414 | /* defensive */ | |
415 | source_val = clamp(source_val, source_min, source_max); | |
416 | ||
417 | /* avoid overflows */ | |
673e7bbd AE |
418 | target_val = DIV_ROUND_CLOSEST_ULL((uint64_t)(source_val - source_min) * |
419 | (target_max - target_min), source_max - source_min); | |
6dda730e JN |
420 | target_val += target_min; |
421 | ||
422 | return target_val; | |
423 | } | |
424 | ||
425 | /* Scale user_level in range [0..user_max] to [hw_min..hw_max]. */ | |
426 | static inline u32 scale_user_to_hw(struct intel_connector *connector, | |
427 | u32 user_level, u32 user_max) | |
428 | { | |
429 | struct intel_panel *panel = &connector->panel; | |
430 | ||
431 | return scale(user_level, 0, user_max, | |
432 | panel->backlight.min, panel->backlight.max); | |
433 | } | |
434 | ||
435 | /* Scale user_level in range [0..user_max] to [0..hw_max], clamping the result | |
436 | * to [hw_min..hw_max]. */ | |
437 | static inline u32 clamp_user_to_hw(struct intel_connector *connector, | |
438 | u32 user_level, u32 user_max) | |
439 | { | |
440 | struct intel_panel *panel = &connector->panel; | |
441 | u32 hw_level; | |
442 | ||
443 | hw_level = scale(user_level, 0, user_max, 0, panel->backlight.max); | |
444 | hw_level = clamp(hw_level, panel->backlight.min, panel->backlight.max); | |
445 | ||
446 | return hw_level; | |
447 | } | |
448 | ||
449 | /* Scale hw_level in range [hw_min..hw_max] to [0..user_max]. */ | |
450 | static inline u32 scale_hw_to_user(struct intel_connector *connector, | |
451 | u32 hw_level, u32 user_max) | |
452 | { | |
453 | struct intel_panel *panel = &connector->panel; | |
454 | ||
455 | return scale(hw_level, panel->backlight.min, panel->backlight.max, | |
456 | 0, user_max); | |
457 | } | |
458 | ||
7bd688cd JN |
459 | static u32 intel_panel_compute_brightness(struct intel_connector *connector, |
460 | u32 val) | |
7bd90909 | 461 | { |
e6cb3727 | 462 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
f91c15e0 JN |
463 | struct intel_panel *panel = &connector->panel; |
464 | ||
465 | WARN_ON(panel->backlight.max == 0); | |
4dca20ef | 466 | |
d330a953 | 467 | if (i915.invert_brightness < 0) |
4dca20ef CE |
468 | return val; |
469 | ||
d330a953 | 470 | if (i915.invert_brightness > 0 || |
d6540632 | 471 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
f91c15e0 | 472 | return panel->backlight.max - val; |
d6540632 | 473 | } |
7bd90909 CE |
474 | |
475 | return val; | |
476 | } | |
477 | ||
437b15b8 | 478 | static u32 lpt_get_backlight(struct intel_connector *connector) |
0b0b053a | 479 | { |
e6cb3727 | 480 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
0b0b053a | 481 | |
96ab4c70 DV |
482 | return I915_READ(BLC_PWM_PCH_CTL2) & BACKLIGHT_DUTY_CYCLE_MASK; |
483 | } | |
07bf139b | 484 | |
7bd688cd | 485 | static u32 pch_get_backlight(struct intel_connector *connector) |
a9573556 | 486 | { |
e6cb3727 | 487 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
8ba2d185 | 488 | |
7bd688cd JN |
489 | return I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
490 | } | |
a9573556 | 491 | |
7bd688cd JN |
492 | static u32 i9xx_get_backlight(struct intel_connector *connector) |
493 | { | |
e6cb3727 | 494 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
636baebf | 495 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 496 | u32 val; |
07bf139b | 497 | |
7bd688cd | 498 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; |
e6cb3727 | 499 | if (INTEL_INFO(dev_priv)->gen < 4) |
7bd688cd | 500 | val >>= 1; |
ba3820ad | 501 | |
636baebf | 502 | if (panel->backlight.combination_mode) { |
7bd688cd | 503 | u8 lbpc; |
ba3820ad | 504 | |
91c8a326 | 505 | pci_read_config_byte(dev_priv->drm.pdev, LBPC, &lbpc); |
7bd688cd | 506 | val *= lbpc; |
a9573556 CW |
507 | } |
508 | ||
7bd688cd JN |
509 | return val; |
510 | } | |
511 | ||
e6cb3727 | 512 | static u32 _vlv_get_backlight(struct drm_i915_private *dev_priv, enum pipe pipe) |
7bd688cd | 513 | { |
23ec0a88 VS |
514 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
515 | return 0; | |
516 | ||
7bd688cd JN |
517 | return I915_READ(VLV_BLC_PWM_CTL(pipe)) & BACKLIGHT_DUTY_CYCLE_MASK; |
518 | } | |
519 | ||
520 | static u32 vlv_get_backlight(struct intel_connector *connector) | |
521 | { | |
e6cb3727 | 522 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
523 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
524 | ||
e6cb3727 | 525 | return _vlv_get_backlight(dev_priv, pipe); |
7bd688cd JN |
526 | } |
527 | ||
0fb890c0 VK |
528 | static u32 bxt_get_backlight(struct intel_connector *connector) |
529 | { | |
e6cb3727 | 530 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
022e4e52 | 531 | struct intel_panel *panel = &connector->panel; |
0fb890c0 | 532 | |
022e4e52 | 533 | return I915_READ(BXT_BLC_PWM_DUTY(panel->backlight.controller)); |
0fb890c0 VK |
534 | } |
535 | ||
b029e66f SK |
536 | static u32 pwm_get_backlight(struct intel_connector *connector) |
537 | { | |
538 | struct intel_panel *panel = &connector->panel; | |
539 | int duty_ns; | |
540 | ||
541 | duty_ns = pwm_get_duty_cycle(panel->backlight.pwm); | |
542 | return DIV_ROUND_UP(duty_ns * 100, CRC_PMIC_PWM_PERIOD_NS); | |
543 | } | |
544 | ||
7bd688cd JN |
545 | static u32 intel_panel_get_backlight(struct intel_connector *connector) |
546 | { | |
e6cb3727 | 547 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
2d72f6c7 VS |
548 | struct intel_panel *panel = &connector->panel; |
549 | u32 val = 0; | |
7bd688cd | 550 | |
07f11d49 | 551 | mutex_lock(&dev_priv->backlight_lock); |
7bd688cd | 552 | |
2d72f6c7 | 553 | if (panel->backlight.enabled) { |
5507faeb | 554 | val = panel->backlight.get(connector); |
2d72f6c7 VS |
555 | val = intel_panel_compute_brightness(connector, val); |
556 | } | |
8ba2d185 | 557 | |
07f11d49 | 558 | mutex_unlock(&dev_priv->backlight_lock); |
8ba2d185 | 559 | |
a9573556 CW |
560 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
561 | return val; | |
562 | } | |
563 | ||
437b15b8 | 564 | static void lpt_set_backlight(struct intel_connector *connector, u32 level) |
f8e10062 | 565 | { |
e6cb3727 | 566 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
f8e10062 BW |
567 | u32 val = I915_READ(BLC_PWM_PCH_CTL2) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
568 | I915_WRITE(BLC_PWM_PCH_CTL2, val | level); | |
569 | } | |
570 | ||
7bd688cd | 571 | static void pch_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 572 | { |
e6cb3727 | 573 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
574 | u32 tmp; |
575 | ||
576 | tmp = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
577 | I915_WRITE(BLC_PWM_CPU_CTL, tmp | level); | |
a9573556 CW |
578 | } |
579 | ||
7bd688cd | 580 | static void i9xx_set_backlight(struct intel_connector *connector, u32 level) |
a9573556 | 581 | { |
e6cb3727 | 582 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
f91c15e0 | 583 | struct intel_panel *panel = &connector->panel; |
b329b328 | 584 | u32 tmp, mask; |
ba3820ad | 585 | |
f91c15e0 JN |
586 | WARN_ON(panel->backlight.max == 0); |
587 | ||
636baebf | 588 | if (panel->backlight.combination_mode) { |
ba3820ad TI |
589 | u8 lbpc; |
590 | ||
f91c15e0 | 591 | lbpc = level * 0xfe / panel->backlight.max + 1; |
ba3820ad | 592 | level /= lbpc; |
91c8a326 | 593 | pci_write_config_byte(dev_priv->drm.pdev, LBPC, lbpc); |
ba3820ad TI |
594 | } |
595 | ||
e6cb3727 | 596 | if (IS_GEN4(dev_priv)) { |
b329b328 JN |
597 | mask = BACKLIGHT_DUTY_CYCLE_MASK; |
598 | } else { | |
a9573556 | 599 | level <<= 1; |
b329b328 JN |
600 | mask = BACKLIGHT_DUTY_CYCLE_MASK_PNV; |
601 | } | |
7bd688cd | 602 | |
b329b328 | 603 | tmp = I915_READ(BLC_PWM_CTL) & ~mask; |
7bd688cd JN |
604 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
605 | } | |
606 | ||
607 | static void vlv_set_backlight(struct intel_connector *connector, u32 level) | |
608 | { | |
e6cb3727 | 609 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
610 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
611 | u32 tmp; | |
612 | ||
23ec0a88 VS |
613 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
614 | return; | |
615 | ||
7bd688cd JN |
616 | tmp = I915_READ(VLV_BLC_PWM_CTL(pipe)) & ~BACKLIGHT_DUTY_CYCLE_MASK; |
617 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), tmp | level); | |
618 | } | |
619 | ||
0fb890c0 VK |
620 | static void bxt_set_backlight(struct intel_connector *connector, u32 level) |
621 | { | |
e6cb3727 | 622 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
022e4e52 | 623 | struct intel_panel *panel = &connector->panel; |
0fb890c0 | 624 | |
022e4e52 | 625 | I915_WRITE(BXT_BLC_PWM_DUTY(panel->backlight.controller), level); |
0fb890c0 VK |
626 | } |
627 | ||
b029e66f SK |
628 | static void pwm_set_backlight(struct intel_connector *connector, u32 level) |
629 | { | |
630 | struct intel_panel *panel = &connector->panel; | |
631 | int duty_ns = DIV_ROUND_UP(level * CRC_PMIC_PWM_PERIOD_NS, 100); | |
632 | ||
633 | pwm_config(panel->backlight.pwm, duty_ns, CRC_PMIC_PWM_PERIOD_NS); | |
634 | } | |
635 | ||
7bd688cd JN |
636 | static void |
637 | intel_panel_actually_set_backlight(struct intel_connector *connector, u32 level) | |
638 | { | |
5507faeb | 639 | struct intel_panel *panel = &connector->panel; |
7bd688cd JN |
640 | |
641 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
642 | ||
643 | level = intel_panel_compute_brightness(connector, level); | |
5507faeb | 644 | panel->backlight.set(connector, level); |
a9573556 | 645 | } |
47356eb6 | 646 | |
6dda730e JN |
647 | /* set backlight brightness to level in range [0..max], scaling wrt hw min */ |
648 | static void intel_panel_set_backlight(struct intel_connector *connector, | |
649 | u32 user_level, u32 user_max) | |
47356eb6 | 650 | { |
e6cb3727 | 651 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
58c68779 | 652 | struct intel_panel *panel = &connector->panel; |
6dda730e | 653 | u32 hw_level; |
8ba2d185 | 654 | |
260d8f98 | 655 | if (!panel->backlight.present) |
752aa88a JB |
656 | return; |
657 | ||
07f11d49 | 658 | mutex_lock(&dev_priv->backlight_lock); |
d6540632 | 659 | |
f91c15e0 | 660 | WARN_ON(panel->backlight.max == 0); |
d6540632 | 661 | |
6dda730e JN |
662 | hw_level = scale_user_to_hw(connector, user_level, user_max); |
663 | panel->backlight.level = hw_level; | |
664 | ||
665 | if (panel->backlight.enabled) | |
666 | intel_panel_actually_set_backlight(connector, hw_level); | |
667 | ||
07f11d49 | 668 | mutex_unlock(&dev_priv->backlight_lock); |
6dda730e JN |
669 | } |
670 | ||
671 | /* set backlight brightness to level in range [0..max], assuming hw min is | |
672 | * respected. | |
673 | */ | |
674 | void intel_panel_set_backlight_acpi(struct intel_connector *connector, | |
675 | u32 user_level, u32 user_max) | |
676 | { | |
e6cb3727 | 677 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
6dda730e JN |
678 | struct intel_panel *panel = &connector->panel; |
679 | enum pipe pipe = intel_get_pipe_from_connector(connector); | |
680 | u32 hw_level; | |
6dda730e | 681 | |
260d8f98 VS |
682 | /* |
683 | * INVALID_PIPE may occur during driver init because | |
684 | * connection_mutex isn't held across the entire backlight | |
685 | * setup + modeset readout, and the BIOS can issue the | |
686 | * requests at any time. | |
687 | */ | |
6dda730e JN |
688 | if (!panel->backlight.present || pipe == INVALID_PIPE) |
689 | return; | |
690 | ||
07f11d49 | 691 | mutex_lock(&dev_priv->backlight_lock); |
6dda730e JN |
692 | |
693 | WARN_ON(panel->backlight.max == 0); | |
694 | ||
695 | hw_level = clamp_user_to_hw(connector, user_level, user_max); | |
696 | panel->backlight.level = hw_level; | |
47356eb6 | 697 | |
58c68779 | 698 | if (panel->backlight.device) |
6dda730e JN |
699 | panel->backlight.device->props.brightness = |
700 | scale_hw_to_user(connector, | |
701 | panel->backlight.level, | |
702 | panel->backlight.device->props.max_brightness); | |
b6b3ba5b | 703 | |
58c68779 | 704 | if (panel->backlight.enabled) |
6dda730e | 705 | intel_panel_actually_set_backlight(connector, hw_level); |
f91c15e0 | 706 | |
07f11d49 | 707 | mutex_unlock(&dev_priv->backlight_lock); |
f52c619a TI |
708 | } |
709 | ||
437b15b8 JN |
710 | static void lpt_disable_backlight(struct intel_connector *connector) |
711 | { | |
e6cb3727 | 712 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
437b15b8 JN |
713 | u32 tmp; |
714 | ||
715 | intel_panel_actually_set_backlight(connector, 0); | |
716 | ||
6675bce2 JN |
717 | /* |
718 | * Although we don't support or enable CPU PWM with LPT/SPT based | |
719 | * systems, it may have been enabled prior to loading the | |
720 | * driver. Disable to avoid warnings on LCPLL disable. | |
721 | * | |
722 | * This needs rework if we need to add support for CPU PWM on PCH split | |
723 | * platforms. | |
724 | */ | |
725 | tmp = I915_READ(BLC_PWM_CPU_CTL2); | |
726 | if (tmp & BLM_PWM_ENABLE) { | |
727 | DRM_DEBUG_KMS("cpu backlight was enabled, disabling\n"); | |
728 | I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); | |
729 | } | |
730 | ||
437b15b8 JN |
731 | tmp = I915_READ(BLC_PWM_PCH_CTL1); |
732 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); | |
733 | } | |
734 | ||
7bd688cd JN |
735 | static void pch_disable_backlight(struct intel_connector *connector) |
736 | { | |
e6cb3727 | 737 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
738 | u32 tmp; |
739 | ||
3bd712e5 JN |
740 | intel_panel_actually_set_backlight(connector, 0); |
741 | ||
7bd688cd JN |
742 | tmp = I915_READ(BLC_PWM_CPU_CTL2); |
743 | I915_WRITE(BLC_PWM_CPU_CTL2, tmp & ~BLM_PWM_ENABLE); | |
744 | ||
745 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
746 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp & ~BLM_PCH_PWM_ENABLE); | |
747 | } | |
748 | ||
3bd712e5 JN |
749 | static void i9xx_disable_backlight(struct intel_connector *connector) |
750 | { | |
751 | intel_panel_actually_set_backlight(connector, 0); | |
752 | } | |
753 | ||
7bd688cd JN |
754 | static void i965_disable_backlight(struct intel_connector *connector) |
755 | { | |
e6cb3727 | 756 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
757 | u32 tmp; |
758 | ||
3bd712e5 JN |
759 | intel_panel_actually_set_backlight(connector, 0); |
760 | ||
7bd688cd JN |
761 | tmp = I915_READ(BLC_PWM_CTL2); |
762 | I915_WRITE(BLC_PWM_CTL2, tmp & ~BLM_PWM_ENABLE); | |
763 | } | |
764 | ||
765 | static void vlv_disable_backlight(struct intel_connector *connector) | |
766 | { | |
e6cb3727 | 767 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd JN |
768 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
769 | u32 tmp; | |
770 | ||
23ec0a88 VS |
771 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
772 | return; | |
773 | ||
3bd712e5 JN |
774 | intel_panel_actually_set_backlight(connector, 0); |
775 | ||
7bd688cd JN |
776 | tmp = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
777 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), tmp & ~BLM_PWM_ENABLE); | |
778 | } | |
779 | ||
0fb890c0 VK |
780 | static void bxt_disable_backlight(struct intel_connector *connector) |
781 | { | |
e6cb3727 | 782 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
022e4e52 SK |
783 | struct intel_panel *panel = &connector->panel; |
784 | u32 tmp, val; | |
0fb890c0 VK |
785 | |
786 | intel_panel_actually_set_backlight(connector, 0); | |
787 | ||
022e4e52 SK |
788 | tmp = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); |
789 | I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), | |
790 | tmp & ~BXT_BLC_PWM_ENABLE); | |
791 | ||
792 | if (panel->backlight.controller == 1) { | |
793 | val = I915_READ(UTIL_PIN_CTL); | |
794 | val &= ~UTIL_PIN_ENABLE; | |
795 | I915_WRITE(UTIL_PIN_CTL, val); | |
796 | } | |
0fb890c0 VK |
797 | } |
798 | ||
b029e66f SK |
799 | static void pwm_disable_backlight(struct intel_connector *connector) |
800 | { | |
801 | struct intel_panel *panel = &connector->panel; | |
802 | ||
803 | /* Disable the backlight */ | |
804 | pwm_config(panel->backlight.pwm, 0, CRC_PMIC_PWM_PERIOD_NS); | |
805 | usleep_range(2000, 3000); | |
806 | pwm_disable(panel->backlight.pwm); | |
807 | } | |
808 | ||
752aa88a | 809 | void intel_panel_disable_backlight(struct intel_connector *connector) |
f52c619a | 810 | { |
e6cb3727 | 811 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
58c68779 | 812 | struct intel_panel *panel = &connector->panel; |
8ba2d185 | 813 | |
260d8f98 | 814 | if (!panel->backlight.present) |
752aa88a JB |
815 | return; |
816 | ||
3f577573 | 817 | /* |
5389e916 | 818 | * Do not disable backlight on the vga_switcheroo path. When switching |
3f577573 JN |
819 | * away from i915, the other client may depend on i915 to handle the |
820 | * backlight. This will leave the backlight on unnecessarily when | |
821 | * another client is not activated. | |
822 | */ | |
91c8a326 | 823 | if (dev_priv->drm.switch_power_state == DRM_SWITCH_POWER_CHANGING) { |
3f577573 JN |
824 | DRM_DEBUG_DRIVER("Skipping backlight disable on vga switch\n"); |
825 | return; | |
826 | } | |
827 | ||
07f11d49 | 828 | mutex_lock(&dev_priv->backlight_lock); |
47356eb6 | 829 | |
ab656bb9 JN |
830 | if (panel->backlight.device) |
831 | panel->backlight.device->props.power = FB_BLANK_POWERDOWN; | |
58c68779 | 832 | panel->backlight.enabled = false; |
5507faeb | 833 | panel->backlight.disable(connector); |
24ded204 | 834 | |
07f11d49 | 835 | mutex_unlock(&dev_priv->backlight_lock); |
7bd688cd | 836 | } |
24ded204 | 837 | |
437b15b8 | 838 | static void lpt_enable_backlight(struct intel_connector *connector) |
96ab4c70 | 839 | { |
e6cb3727 | 840 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
96ab4c70 | 841 | struct intel_panel *panel = &connector->panel; |
e29aff05 | 842 | u32 pch_ctl1, pch_ctl2, schicken; |
96ab4c70 DV |
843 | |
844 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
845 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
846 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
847 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
848 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
849 | } | |
24ded204 | 850 | |
e29aff05 SL |
851 | if (HAS_PCH_LPT(dev_priv)) { |
852 | schicken = I915_READ(SOUTH_CHICKEN2); | |
853 | if (panel->backlight.alternate_pwm_increment) | |
854 | schicken |= LPT_PWM_GRANULARITY; | |
855 | else | |
856 | schicken &= ~LPT_PWM_GRANULARITY; | |
857 | I915_WRITE(SOUTH_CHICKEN2, schicken); | |
858 | } else { | |
859 | schicken = I915_READ(SOUTH_CHICKEN1); | |
860 | if (panel->backlight.alternate_pwm_increment) | |
861 | schicken |= SPT_PWM_GRANULARITY; | |
862 | else | |
863 | schicken &= ~SPT_PWM_GRANULARITY; | |
864 | I915_WRITE(SOUTH_CHICKEN1, schicken); | |
865 | } | |
866 | ||
96ab4c70 DV |
867 | pch_ctl2 = panel->backlight.max << 16; |
868 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
a4f32fc3 | 869 | |
96ab4c70 DV |
870 | pch_ctl1 = 0; |
871 | if (panel->backlight.active_low_pwm) | |
872 | pch_ctl1 |= BLM_PCH_POLARITY; | |
8ba2d185 | 873 | |
e6b2627c JN |
874 | /* After LPT, override is the default. */ |
875 | if (HAS_PCH_LPT(dev_priv)) | |
876 | pch_ctl1 |= BLM_PCH_OVERRIDE_ENABLE; | |
96ab4c70 DV |
877 | |
878 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
879 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
880 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
881 | ||
882 | /* This won't stick until the above enable. */ | |
883 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
47356eb6 CW |
884 | } |
885 | ||
7bd688cd JN |
886 | static void pch_enable_backlight(struct intel_connector *connector) |
887 | { | |
e6cb3727 | 888 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
3bd712e5 | 889 | struct intel_panel *panel = &connector->panel; |
7bd688cd JN |
890 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
891 | enum transcoder cpu_transcoder = | |
892 | intel_pipe_to_cpu_transcoder(dev_priv, pipe); | |
b35684b8 | 893 | u32 cpu_ctl2, pch_ctl1, pch_ctl2; |
7bd688cd | 894 | |
b35684b8 JN |
895 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
896 | if (cpu_ctl2 & BLM_PWM_ENABLE) { | |
813008cd | 897 | DRM_DEBUG_KMS("cpu backlight already enabled\n"); |
b35684b8 JN |
898 | cpu_ctl2 &= ~BLM_PWM_ENABLE; |
899 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
900 | } | |
7bd688cd | 901 | |
b35684b8 JN |
902 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
903 | if (pch_ctl1 & BLM_PCH_PWM_ENABLE) { | |
904 | DRM_DEBUG_KMS("pch backlight already enabled\n"); | |
905 | pch_ctl1 &= ~BLM_PCH_PWM_ENABLE; | |
906 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); | |
907 | } | |
7bd688cd JN |
908 | |
909 | if (cpu_transcoder == TRANSCODER_EDP) | |
b35684b8 | 910 | cpu_ctl2 = BLM_TRANSCODER_EDP; |
7bd688cd | 911 | else |
b35684b8 JN |
912 | cpu_ctl2 = BLM_PIPE(cpu_transcoder); |
913 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2); | |
7bd688cd | 914 | POSTING_READ(BLC_PWM_CPU_CTL2); |
b35684b8 | 915 | I915_WRITE(BLC_PWM_CPU_CTL2, cpu_ctl2 | BLM_PWM_ENABLE); |
3bd712e5 | 916 | |
b35684b8 | 917 | /* This won't stick until the above enable. */ |
3bd712e5 | 918 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
b35684b8 JN |
919 | |
920 | pch_ctl2 = panel->backlight.max << 16; | |
921 | I915_WRITE(BLC_PWM_PCH_CTL2, pch_ctl2); | |
922 | ||
b35684b8 JN |
923 | pch_ctl1 = 0; |
924 | if (panel->backlight.active_low_pwm) | |
925 | pch_ctl1 |= BLM_PCH_POLARITY; | |
96ab4c70 | 926 | |
b35684b8 JN |
927 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1); |
928 | POSTING_READ(BLC_PWM_PCH_CTL1); | |
929 | I915_WRITE(BLC_PWM_PCH_CTL1, pch_ctl1 | BLM_PCH_PWM_ENABLE); | |
3bd712e5 JN |
930 | } |
931 | ||
932 | static void i9xx_enable_backlight(struct intel_connector *connector) | |
933 | { | |
e6cb3727 | 934 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
3bd712e5 | 935 | struct intel_panel *panel = &connector->panel; |
b35684b8 JN |
936 | u32 ctl, freq; |
937 | ||
938 | ctl = I915_READ(BLC_PWM_CTL); | |
939 | if (ctl & BACKLIGHT_DUTY_CYCLE_MASK_PNV) { | |
813008cd | 940 | DRM_DEBUG_KMS("backlight already enabled\n"); |
b35684b8 JN |
941 | I915_WRITE(BLC_PWM_CTL, 0); |
942 | } | |
3bd712e5 | 943 | |
b35684b8 JN |
944 | freq = panel->backlight.max; |
945 | if (panel->backlight.combination_mode) | |
946 | freq /= 0xff; | |
947 | ||
948 | ctl = freq << 17; | |
b6ab66aa | 949 | if (panel->backlight.combination_mode) |
b35684b8 | 950 | ctl |= BLM_LEGACY_MODE; |
e6cb3727 | 951 | if (IS_PINEVIEW(dev_priv) && panel->backlight.active_low_pwm) |
b35684b8 JN |
952 | ctl |= BLM_POLARITY_PNV; |
953 | ||
954 | I915_WRITE(BLC_PWM_CTL, ctl); | |
955 | POSTING_READ(BLC_PWM_CTL); | |
956 | ||
957 | /* XXX: combine this into above write? */ | |
3bd712e5 | 958 | intel_panel_actually_set_backlight(connector, panel->backlight.level); |
2059ac3b JN |
959 | |
960 | /* | |
961 | * Needed to enable backlight on some 855gm models. BLC_HIST_CTL is | |
962 | * 855gm only, but checking for gen2 is safe, as 855gm is the only gen2 | |
963 | * that has backlight. | |
964 | */ | |
e6cb3727 | 965 | if (IS_GEN2(dev_priv)) |
2059ac3b | 966 | I915_WRITE(BLC_HIST_CTL, BLM_HISTOGRAM_ENABLE); |
7bd688cd | 967 | } |
8ba2d185 | 968 | |
7bd688cd JN |
969 | static void i965_enable_backlight(struct intel_connector *connector) |
970 | { | |
e6cb3727 | 971 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
3bd712e5 | 972 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 973 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 974 | u32 ctl, ctl2, freq; |
7bd688cd | 975 | |
b35684b8 JN |
976 | ctl2 = I915_READ(BLC_PWM_CTL2); |
977 | if (ctl2 & BLM_PWM_ENABLE) { | |
813008cd | 978 | DRM_DEBUG_KMS("backlight already enabled\n"); |
b35684b8 JN |
979 | ctl2 &= ~BLM_PWM_ENABLE; |
980 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
981 | } | |
7bd688cd | 982 | |
b35684b8 JN |
983 | freq = panel->backlight.max; |
984 | if (panel->backlight.combination_mode) | |
985 | freq /= 0xff; | |
7bd688cd | 986 | |
b35684b8 JN |
987 | ctl = freq << 16; |
988 | I915_WRITE(BLC_PWM_CTL, ctl); | |
3bd712e5 | 989 | |
b35684b8 JN |
990 | ctl2 = BLM_PIPE(pipe); |
991 | if (panel->backlight.combination_mode) | |
992 | ctl2 |= BLM_COMBINATION_MODE; | |
993 | if (panel->backlight.active_low_pwm) | |
994 | ctl2 |= BLM_POLARITY_I965; | |
995 | I915_WRITE(BLC_PWM_CTL2, ctl2); | |
996 | POSTING_READ(BLC_PWM_CTL2); | |
997 | I915_WRITE(BLC_PWM_CTL2, ctl2 | BLM_PWM_ENABLE); | |
2e7eeeb5 JN |
998 | |
999 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd JN |
1000 | } |
1001 | ||
1002 | static void vlv_enable_backlight(struct intel_connector *connector) | |
1003 | { | |
e6cb3727 | 1004 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
3bd712e5 | 1005 | struct intel_panel *panel = &connector->panel; |
7bd688cd | 1006 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
b35684b8 | 1007 | u32 ctl, ctl2; |
7bd688cd | 1008 | |
23ec0a88 VS |
1009 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
1010 | return; | |
1011 | ||
b35684b8 JN |
1012 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); |
1013 | if (ctl2 & BLM_PWM_ENABLE) { | |
813008cd | 1014 | DRM_DEBUG_KMS("backlight already enabled\n"); |
b35684b8 JN |
1015 | ctl2 &= ~BLM_PWM_ENABLE; |
1016 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
1017 | } | |
7bd688cd | 1018 | |
b35684b8 JN |
1019 | ctl = panel->backlight.max << 16; |
1020 | I915_WRITE(VLV_BLC_PWM_CTL(pipe), ctl); | |
7bd688cd | 1021 | |
b35684b8 JN |
1022 | /* XXX: combine this into above write? */ |
1023 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
7bd688cd | 1024 | |
b35684b8 JN |
1025 | ctl2 = 0; |
1026 | if (panel->backlight.active_low_pwm) | |
1027 | ctl2 |= BLM_POLARITY_I965; | |
1028 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2); | |
7bd688cd | 1029 | POSTING_READ(VLV_BLC_PWM_CTL2(pipe)); |
b35684b8 | 1030 | I915_WRITE(VLV_BLC_PWM_CTL2(pipe), ctl2 | BLM_PWM_ENABLE); |
47356eb6 CW |
1031 | } |
1032 | ||
0fb890c0 VK |
1033 | static void bxt_enable_backlight(struct intel_connector *connector) |
1034 | { | |
e6cb3727 | 1035 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
0fb890c0 | 1036 | struct intel_panel *panel = &connector->panel; |
022e4e52 SK |
1037 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
1038 | u32 pwm_ctl, val; | |
1039 | ||
add03379 | 1040 | /* Controller 1 uses the utility pin. */ |
022e4e52 SK |
1041 | if (panel->backlight.controller == 1) { |
1042 | val = I915_READ(UTIL_PIN_CTL); | |
1043 | if (val & UTIL_PIN_ENABLE) { | |
1044 | DRM_DEBUG_KMS("util pin already enabled\n"); | |
1045 | val &= ~UTIL_PIN_ENABLE; | |
1046 | I915_WRITE(UTIL_PIN_CTL, val); | |
1047 | } | |
0fb890c0 | 1048 | |
022e4e52 SK |
1049 | val = 0; |
1050 | if (panel->backlight.util_pin_active_low) | |
1051 | val |= UTIL_PIN_POLARITY; | |
1052 | I915_WRITE(UTIL_PIN_CTL, val | UTIL_PIN_PIPE(pipe) | | |
1053 | UTIL_PIN_MODE_PWM | UTIL_PIN_ENABLE); | |
1054 | } | |
1055 | ||
1056 | pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); | |
0fb890c0 VK |
1057 | if (pwm_ctl & BXT_BLC_PWM_ENABLE) { |
1058 | DRM_DEBUG_KMS("backlight already enabled\n"); | |
1059 | pwm_ctl &= ~BXT_BLC_PWM_ENABLE; | |
022e4e52 SK |
1060 | I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), |
1061 | pwm_ctl); | |
0fb890c0 VK |
1062 | } |
1063 | ||
022e4e52 SK |
1064 | I915_WRITE(BXT_BLC_PWM_FREQ(panel->backlight.controller), |
1065 | panel->backlight.max); | |
0fb890c0 VK |
1066 | |
1067 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
1068 | ||
1069 | pwm_ctl = 0; | |
1070 | if (panel->backlight.active_low_pwm) | |
1071 | pwm_ctl |= BXT_BLC_PWM_POLARITY; | |
1072 | ||
022e4e52 SK |
1073 | I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), pwm_ctl); |
1074 | POSTING_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); | |
1075 | I915_WRITE(BXT_BLC_PWM_CTL(panel->backlight.controller), | |
1076 | pwm_ctl | BXT_BLC_PWM_ENABLE); | |
0fb890c0 VK |
1077 | } |
1078 | ||
b029e66f SK |
1079 | static void pwm_enable_backlight(struct intel_connector *connector) |
1080 | { | |
1081 | struct intel_panel *panel = &connector->panel; | |
1082 | ||
1083 | pwm_enable(panel->backlight.pwm); | |
1084 | intel_panel_actually_set_backlight(connector, panel->backlight.level); | |
1085 | } | |
1086 | ||
752aa88a | 1087 | void intel_panel_enable_backlight(struct intel_connector *connector) |
47356eb6 | 1088 | { |
e6cb3727 | 1089 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
58c68779 | 1090 | struct intel_panel *panel = &connector->panel; |
752aa88a | 1091 | enum pipe pipe = intel_get_pipe_from_connector(connector); |
8ba2d185 | 1092 | |
260d8f98 | 1093 | if (!panel->backlight.present) |
752aa88a JB |
1094 | return; |
1095 | ||
6f2bcceb | 1096 | DRM_DEBUG_KMS("pipe %c\n", pipe_name(pipe)); |
540b5d02 | 1097 | |
07f11d49 | 1098 | mutex_lock(&dev_priv->backlight_lock); |
47356eb6 | 1099 | |
f91c15e0 JN |
1100 | WARN_ON(panel->backlight.max == 0); |
1101 | ||
13f3fbe8 | 1102 | if (panel->backlight.level <= panel->backlight.min) { |
f91c15e0 | 1103 | panel->backlight.level = panel->backlight.max; |
58c68779 JN |
1104 | if (panel->backlight.device) |
1105 | panel->backlight.device->props.brightness = | |
6dda730e JN |
1106 | scale_hw_to_user(connector, |
1107 | panel->backlight.level, | |
1108 | panel->backlight.device->props.max_brightness); | |
b6b3ba5b | 1109 | } |
47356eb6 | 1110 | |
5507faeb | 1111 | panel->backlight.enable(connector); |
58c68779 | 1112 | panel->backlight.enabled = true; |
ab656bb9 JN |
1113 | if (panel->backlight.device) |
1114 | panel->backlight.device->props.power = FB_BLANK_UNBLANK; | |
8ba2d185 | 1115 | |
07f11d49 | 1116 | mutex_unlock(&dev_priv->backlight_lock); |
47356eb6 CW |
1117 | } |
1118 | ||
912e8b12 | 1119 | #if IS_ENABLED(CONFIG_BACKLIGHT_CLASS_DEVICE) |
db31af1d | 1120 | static int intel_backlight_device_update_status(struct backlight_device *bd) |
aaa6fd2a | 1121 | { |
752aa88a | 1122 | struct intel_connector *connector = bl_get_data(bd); |
ab656bb9 | 1123 | struct intel_panel *panel = &connector->panel; |
752aa88a JB |
1124 | struct drm_device *dev = connector->base.dev; |
1125 | ||
51fd371b | 1126 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
540b5d02 CW |
1127 | DRM_DEBUG_KMS("updating intel_backlight, brightness=%d/%d\n", |
1128 | bd->props.brightness, bd->props.max_brightness); | |
752aa88a | 1129 | intel_panel_set_backlight(connector, bd->props.brightness, |
d6540632 | 1130 | bd->props.max_brightness); |
ab656bb9 JN |
1131 | |
1132 | /* | |
1133 | * Allow flipping bl_power as a sub-state of enabled. Sadly the | |
1134 | * backlight class device does not make it easy to to differentiate | |
1135 | * between callbacks for brightness and bl_power, so our backlight_power | |
1136 | * callback needs to take this into account. | |
1137 | */ | |
1138 | if (panel->backlight.enabled) { | |
5507faeb | 1139 | if (panel->backlight.power) { |
e6755fb7 JN |
1140 | bool enable = bd->props.power == FB_BLANK_UNBLANK && |
1141 | bd->props.brightness != 0; | |
5507faeb | 1142 | panel->backlight.power(connector, enable); |
ab656bb9 JN |
1143 | } |
1144 | } else { | |
1145 | bd->props.power = FB_BLANK_POWERDOWN; | |
1146 | } | |
1147 | ||
51fd371b | 1148 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
aaa6fd2a MG |
1149 | return 0; |
1150 | } | |
1151 | ||
db31af1d | 1152 | static int intel_backlight_device_get_brightness(struct backlight_device *bd) |
aaa6fd2a | 1153 | { |
752aa88a JB |
1154 | struct intel_connector *connector = bl_get_data(bd); |
1155 | struct drm_device *dev = connector->base.dev; | |
fac5e23e | 1156 | struct drm_i915_private *dev_priv = to_i915(dev); |
6dda730e | 1157 | u32 hw_level; |
7bd688cd | 1158 | int ret; |
752aa88a | 1159 | |
c8c8fb33 | 1160 | intel_runtime_pm_get(dev_priv); |
51fd371b | 1161 | drm_modeset_lock(&dev->mode_config.connection_mutex, NULL); |
6dda730e JN |
1162 | |
1163 | hw_level = intel_panel_get_backlight(connector); | |
1164 | ret = scale_hw_to_user(connector, hw_level, bd->props.max_brightness); | |
1165 | ||
51fd371b | 1166 | drm_modeset_unlock(&dev->mode_config.connection_mutex); |
c8c8fb33 | 1167 | intel_runtime_pm_put(dev_priv); |
752aa88a | 1168 | |
7bd688cd | 1169 | return ret; |
aaa6fd2a MG |
1170 | } |
1171 | ||
db31af1d JN |
1172 | static const struct backlight_ops intel_backlight_device_ops = { |
1173 | .update_status = intel_backlight_device_update_status, | |
1174 | .get_brightness = intel_backlight_device_get_brightness, | |
aaa6fd2a MG |
1175 | }; |
1176 | ||
1ebaa0b9 | 1177 | int intel_backlight_device_register(struct intel_connector *connector) |
aaa6fd2a | 1178 | { |
58c68779 | 1179 | struct intel_panel *panel = &connector->panel; |
aaa6fd2a | 1180 | struct backlight_properties props; |
aaa6fd2a | 1181 | |
58c68779 | 1182 | if (WARN_ON(panel->backlight.device)) |
dc652f90 JN |
1183 | return -ENODEV; |
1184 | ||
0962c3c9 VS |
1185 | if (!panel->backlight.present) |
1186 | return 0; | |
1187 | ||
6dda730e | 1188 | WARN_ON(panel->backlight.max == 0); |
7bd688cd | 1189 | |
af437cfd | 1190 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 1191 | props.type = BACKLIGHT_RAW; |
6dda730e JN |
1192 | |
1193 | /* | |
1194 | * Note: Everything should work even if the backlight device max | |
1195 | * presented to the userspace is arbitrarily chosen. | |
1196 | */ | |
7bd688cd | 1197 | props.max_brightness = panel->backlight.max; |
6dda730e JN |
1198 | props.brightness = scale_hw_to_user(connector, |
1199 | panel->backlight.level, | |
1200 | props.max_brightness); | |
58c68779 | 1201 | |
ab656bb9 JN |
1202 | if (panel->backlight.enabled) |
1203 | props.power = FB_BLANK_UNBLANK; | |
1204 | else | |
1205 | props.power = FB_BLANK_POWERDOWN; | |
1206 | ||
58c68779 JN |
1207 | /* |
1208 | * Note: using the same name independent of the connector prevents | |
1209 | * registration of multiple backlight devices in the driver. | |
1210 | */ | |
1211 | panel->backlight.device = | |
aaa6fd2a | 1212 | backlight_device_register("intel_backlight", |
db31af1d JN |
1213 | connector->base.kdev, |
1214 | connector, | |
1215 | &intel_backlight_device_ops, &props); | |
aaa6fd2a | 1216 | |
58c68779 | 1217 | if (IS_ERR(panel->backlight.device)) { |
aaa6fd2a | 1218 | DRM_ERROR("Failed to register backlight: %ld\n", |
58c68779 JN |
1219 | PTR_ERR(panel->backlight.device)); |
1220 | panel->backlight.device = NULL; | |
aaa6fd2a MG |
1221 | return -ENODEV; |
1222 | } | |
0962c3c9 VS |
1223 | |
1224 | DRM_DEBUG_KMS("Connector %s backlight sysfs interface registered\n", | |
1225 | connector->base.name); | |
1226 | ||
aaa6fd2a MG |
1227 | return 0; |
1228 | } | |
1229 | ||
e63d87c0 | 1230 | void intel_backlight_device_unregister(struct intel_connector *connector) |
aaa6fd2a | 1231 | { |
58c68779 JN |
1232 | struct intel_panel *panel = &connector->panel; |
1233 | ||
1234 | if (panel->backlight.device) { | |
1235 | backlight_device_unregister(panel->backlight.device); | |
1236 | panel->backlight.device = NULL; | |
dc652f90 | 1237 | } |
aaa6fd2a | 1238 | } |
db31af1d JN |
1239 | #endif /* CONFIG_BACKLIGHT_CLASS_DEVICE */ |
1240 | ||
2dd6982e JN |
1241 | /* |
1242 | * BXT: PWM clock frequency = 19.2 MHz. | |
1243 | */ | |
1244 | static u32 bxt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1245 | { | |
37f2248e | 1246 | return DIV_ROUND_CLOSEST(KHz(19200), pwm_freq_hz); |
2dd6982e JN |
1247 | } |
1248 | ||
f91c15e0 | 1249 | /* |
aa17cdb4 JN |
1250 | * SPT: This value represents the period of the PWM stream in clock periods |
1251 | * multiplied by 16 (default increment) or 128 (alternate increment selected in | |
1252 | * SCHICKEN_1 bit 0). PWM clock is 24 MHz. | |
1253 | */ | |
1254 | static u32 spt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1255 | { | |
32b421e7 | 1256 | struct intel_panel *panel = &connector->panel; |
e7dc33f3 | 1257 | u32 mul; |
aa17cdb4 | 1258 | |
32b421e7 | 1259 | if (panel->backlight.alternate_pwm_increment) |
aa17cdb4 JN |
1260 | mul = 128; |
1261 | else | |
1262 | mul = 16; | |
1263 | ||
37f2248e | 1264 | return DIV_ROUND_CLOSEST(MHz(24), pwm_freq_hz * mul); |
aa17cdb4 JN |
1265 | } |
1266 | ||
1267 | /* | |
1268 | * LPT: This value represents the period of the PWM stream in clock periods | |
1269 | * multiplied by 128 (default increment) or 16 (alternate increment, selected in | |
1270 | * LPT SOUTH_CHICKEN2 register bit 5). | |
1271 | */ | |
1272 | static u32 lpt_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1273 | { | |
e6cb3727 | 1274 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
32b421e7 | 1275 | struct intel_panel *panel = &connector->panel; |
aa17cdb4 JN |
1276 | u32 mul, clock; |
1277 | ||
32b421e7 | 1278 | if (panel->backlight.alternate_pwm_increment) |
aa17cdb4 JN |
1279 | mul = 16; |
1280 | else | |
1281 | mul = 128; | |
1282 | ||
56f5f700 | 1283 | if (HAS_PCH_LPT_H(dev_priv)) |
aa17cdb4 JN |
1284 | clock = MHz(135); /* LPT:H */ |
1285 | else | |
1286 | clock = MHz(24); /* LPT:LP */ | |
1287 | ||
37f2248e | 1288 | return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); |
aa17cdb4 JN |
1289 | } |
1290 | ||
1291 | /* | |
1292 | * ILK/SNB/IVB: This value represents the period of the PWM stream in PCH | |
1293 | * display raw clocks multiplied by 128. | |
1294 | */ | |
1295 | static u32 pch_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1296 | { | |
e7dc33f3 | 1297 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
aa17cdb4 | 1298 | |
37f2248e | 1299 | return DIV_ROUND_CLOSEST(KHz(dev_priv->rawclk_freq), pwm_freq_hz * 128); |
aa17cdb4 JN |
1300 | } |
1301 | ||
1302 | /* | |
1303 | * Gen2: This field determines the number of time base events (display core | |
1304 | * clock frequency/32) in total for a complete cycle of modulated backlight | |
1305 | * control. | |
f91c15e0 | 1306 | * |
aa17cdb4 JN |
1307 | * Gen3: A time base event equals the display core clock ([DevPNV] HRAW clock) |
1308 | * divided by 32. | |
1309 | */ | |
1310 | static u32 i9xx_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1311 | { | |
e7dc33f3 | 1312 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
aa17cdb4 JN |
1313 | int clock; |
1314 | ||
e7dc33f3 VS |
1315 | if (IS_PINEVIEW(dev_priv)) |
1316 | clock = KHz(dev_priv->rawclk_freq); | |
aa17cdb4 | 1317 | else |
e7dc33f3 | 1318 | clock = KHz(dev_priv->cdclk_freq); |
aa17cdb4 | 1319 | |
37f2248e | 1320 | return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 32); |
aa17cdb4 JN |
1321 | } |
1322 | ||
1323 | /* | |
1324 | * Gen4: This value represents the period of the PWM stream in display core | |
83d83392 VS |
1325 | * clocks ([DevCTG] HRAW clocks) multiplied by 128. |
1326 | * | |
aa17cdb4 JN |
1327 | */ |
1328 | static u32 i965_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1329 | { | |
3bed7f4d | 1330 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
83d83392 VS |
1331 | int clock; |
1332 | ||
1333 | if (IS_G4X(dev_priv)) | |
e7dc33f3 | 1334 | clock = KHz(dev_priv->rawclk_freq); |
83d83392 | 1335 | else |
e7dc33f3 | 1336 | clock = KHz(dev_priv->cdclk_freq); |
aa17cdb4 | 1337 | |
37f2248e | 1338 | return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * 128); |
aa17cdb4 JN |
1339 | } |
1340 | ||
1341 | /* | |
1342 | * VLV: This value represents the period of the PWM stream in display core | |
1343 | * clocks ([DevCTG] 200MHz HRAW clocks) multiplied by 128 or 25MHz S0IX clocks | |
1344 | * multiplied by 16. CHV uses a 19.2MHz S0IX clock. | |
1345 | */ | |
1346 | static u32 vlv_hz_to_pwm(struct intel_connector *connector, u32 pwm_freq_hz) | |
1347 | { | |
e7dc33f3 VS |
1348 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
1349 | int mul, clock; | |
aa17cdb4 JN |
1350 | |
1351 | if ((I915_READ(CBR1_VLV) & CBR_PWM_CLOCK_MUX_SELECT) == 0) { | |
e7dc33f3 VS |
1352 | if (IS_CHERRYVIEW(dev_priv)) |
1353 | clock = KHz(19200); | |
aa17cdb4 | 1354 | else |
e7dc33f3 VS |
1355 | clock = MHz(25); |
1356 | mul = 16; | |
aa17cdb4 | 1357 | } else { |
e7dc33f3 VS |
1358 | clock = KHz(dev_priv->rawclk_freq); |
1359 | mul = 128; | |
aa17cdb4 | 1360 | } |
e7dc33f3 | 1361 | |
37f2248e | 1362 | return DIV_ROUND_CLOSEST(clock, pwm_freq_hz * mul); |
aa17cdb4 JN |
1363 | } |
1364 | ||
1365 | static u32 get_backlight_max_vbt(struct intel_connector *connector) | |
1366 | { | |
e6cb3727 | 1367 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
5507faeb | 1368 | struct intel_panel *panel = &connector->panel; |
aa17cdb4 JN |
1369 | u16 pwm_freq_hz = dev_priv->vbt.backlight.pwm_freq_hz; |
1370 | u32 pwm; | |
1371 | ||
5075222b JN |
1372 | if (!panel->backlight.hz_to_pwm) { |
1373 | DRM_DEBUG_KMS("backlight frequency conversion not supported\n"); | |
aa17cdb4 JN |
1374 | return 0; |
1375 | } | |
1376 | ||
5075222b JN |
1377 | if (pwm_freq_hz) { |
1378 | DRM_DEBUG_KMS("VBT defined backlight frequency %u Hz\n", | |
1379 | pwm_freq_hz); | |
1380 | } else { | |
1381 | pwm_freq_hz = 200; | |
1382 | DRM_DEBUG_KMS("default backlight frequency %u Hz\n", | |
1383 | pwm_freq_hz); | |
aa17cdb4 JN |
1384 | } |
1385 | ||
5507faeb | 1386 | pwm = panel->backlight.hz_to_pwm(connector, pwm_freq_hz); |
aa17cdb4 JN |
1387 | if (!pwm) { |
1388 | DRM_DEBUG_KMS("backlight frequency conversion failed\n"); | |
1389 | return 0; | |
1390 | } | |
1391 | ||
aa17cdb4 JN |
1392 | return pwm; |
1393 | } | |
1394 | ||
1395 | /* | |
1396 | * Note: The setup hooks can't assume pipe is set! | |
f91c15e0 | 1397 | */ |
6dda730e JN |
1398 | static u32 get_backlight_min_vbt(struct intel_connector *connector) |
1399 | { | |
e6cb3727 | 1400 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
6dda730e | 1401 | struct intel_panel *panel = &connector->panel; |
e1c412e7 | 1402 | int min; |
6dda730e JN |
1403 | |
1404 | WARN_ON(panel->backlight.max == 0); | |
1405 | ||
e1c412e7 JN |
1406 | /* |
1407 | * XXX: If the vbt value is 255, it makes min equal to max, which leads | |
1408 | * to problems. There are such machines out there. Either our | |
1409 | * interpretation is wrong or the vbt has bogus data. Or both. Safeguard | |
1410 | * against this by letting the minimum be at most (arbitrarily chosen) | |
1411 | * 25% of the max. | |
1412 | */ | |
1413 | min = clamp_t(int, dev_priv->vbt.backlight.min_brightness, 0, 64); | |
1414 | if (min != dev_priv->vbt.backlight.min_brightness) { | |
1415 | DRM_DEBUG_KMS("clamping VBT min backlight %d/255 to %d/255\n", | |
1416 | dev_priv->vbt.backlight.min_brightness, min); | |
1417 | } | |
1418 | ||
6dda730e | 1419 | /* vbt value is a coefficient in range [0..255] */ |
e1c412e7 | 1420 | return scale(min, 0, 255, 0, panel->backlight.max); |
6dda730e JN |
1421 | } |
1422 | ||
437b15b8 | 1423 | static int lpt_setup_backlight(struct intel_connector *connector, enum pipe unused) |
aaa6fd2a | 1424 | { |
e6cb3727 | 1425 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
96ab4c70 DV |
1426 | struct intel_panel *panel = &connector->panel; |
1427 | u32 pch_ctl1, pch_ctl2, val; | |
32b421e7 JN |
1428 | bool alt; |
1429 | ||
1430 | if (HAS_PCH_LPT(dev_priv)) | |
1431 | alt = I915_READ(SOUTH_CHICKEN2) & LPT_PWM_GRANULARITY; | |
1432 | else | |
1433 | alt = I915_READ(SOUTH_CHICKEN1) & SPT_PWM_GRANULARITY; | |
1434 | panel->backlight.alternate_pwm_increment = alt; | |
96ab4c70 DV |
1435 | |
1436 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); | |
1437 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
1438 | ||
1439 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
1440 | panel->backlight.max = pch_ctl2 >> 16; | |
aa17cdb4 JN |
1441 | |
1442 | if (!panel->backlight.max) | |
1443 | panel->backlight.max = get_backlight_max_vbt(connector); | |
1444 | ||
96ab4c70 DV |
1445 | if (!panel->backlight.max) |
1446 | return -ENODEV; | |
1447 | ||
6dda730e JN |
1448 | panel->backlight.min = get_backlight_min_vbt(connector); |
1449 | ||
437b15b8 | 1450 | val = lpt_get_backlight(connector); |
46e69f39 JN |
1451 | val = intel_panel_compute_brightness(connector, val); |
1452 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1453 | panel->backlight.max); | |
96ab4c70 | 1454 | |
46e69f39 | 1455 | panel->backlight.enabled = pch_ctl1 & BLM_PCH_PWM_ENABLE; |
96ab4c70 DV |
1456 | |
1457 | return 0; | |
1458 | } | |
1459 | ||
6517d273 | 1460 | static int pch_setup_backlight(struct intel_connector *connector, enum pipe unused) |
7bd688cd | 1461 | { |
e6cb3727 | 1462 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd | 1463 | struct intel_panel *panel = &connector->panel; |
636baebf | 1464 | u32 cpu_ctl2, pch_ctl1, pch_ctl2, val; |
7bd688cd | 1465 | |
636baebf JN |
1466 | pch_ctl1 = I915_READ(BLC_PWM_PCH_CTL1); |
1467 | panel->backlight.active_low_pwm = pch_ctl1 & BLM_PCH_POLARITY; | |
1468 | ||
1469 | pch_ctl2 = I915_READ(BLC_PWM_PCH_CTL2); | |
1470 | panel->backlight.max = pch_ctl2 >> 16; | |
aa17cdb4 JN |
1471 | |
1472 | if (!panel->backlight.max) | |
1473 | panel->backlight.max = get_backlight_max_vbt(connector); | |
1474 | ||
7bd688cd JN |
1475 | if (!panel->backlight.max) |
1476 | return -ENODEV; | |
1477 | ||
6dda730e JN |
1478 | panel->backlight.min = get_backlight_min_vbt(connector); |
1479 | ||
7bd688cd | 1480 | val = pch_get_backlight(connector); |
46e69f39 JN |
1481 | val = intel_panel_compute_brightness(connector, val); |
1482 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1483 | panel->backlight.max); | |
7bd688cd | 1484 | |
636baebf JN |
1485 | cpu_ctl2 = I915_READ(BLC_PWM_CPU_CTL2); |
1486 | panel->backlight.enabled = (cpu_ctl2 & BLM_PWM_ENABLE) && | |
46e69f39 | 1487 | (pch_ctl1 & BLM_PCH_PWM_ENABLE); |
636baebf | 1488 | |
7bd688cd JN |
1489 | return 0; |
1490 | } | |
1491 | ||
6517d273 | 1492 | static int i9xx_setup_backlight(struct intel_connector *connector, enum pipe unused) |
7bd688cd | 1493 | { |
e6cb3727 | 1494 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd | 1495 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1496 | u32 ctl, val; |
1497 | ||
1498 | ctl = I915_READ(BLC_PWM_CTL); | |
1499 | ||
e6cb3727 | 1500 | if (IS_GEN2(dev_priv) || IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) |
636baebf JN |
1501 | panel->backlight.combination_mode = ctl & BLM_LEGACY_MODE; |
1502 | ||
e6cb3727 | 1503 | if (IS_PINEVIEW(dev_priv)) |
636baebf JN |
1504 | panel->backlight.active_low_pwm = ctl & BLM_POLARITY_PNV; |
1505 | ||
1506 | panel->backlight.max = ctl >> 17; | |
aa17cdb4 JN |
1507 | |
1508 | if (!panel->backlight.max) { | |
1509 | panel->backlight.max = get_backlight_max_vbt(connector); | |
1510 | panel->backlight.max >>= 1; | |
1511 | } | |
7bd688cd | 1512 | |
7bd688cd JN |
1513 | if (!panel->backlight.max) |
1514 | return -ENODEV; | |
1515 | ||
aa17cdb4 JN |
1516 | if (panel->backlight.combination_mode) |
1517 | panel->backlight.max *= 0xff; | |
1518 | ||
6dda730e JN |
1519 | panel->backlight.min = get_backlight_min_vbt(connector); |
1520 | ||
7bd688cd | 1521 | val = i9xx_get_backlight(connector); |
46e69f39 JN |
1522 | val = intel_panel_compute_brightness(connector, val); |
1523 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1524 | panel->backlight.max); | |
7bd688cd | 1525 | |
46e69f39 | 1526 | panel->backlight.enabled = val != 0; |
636baebf | 1527 | |
7bd688cd JN |
1528 | return 0; |
1529 | } | |
1530 | ||
6517d273 | 1531 | static int i965_setup_backlight(struct intel_connector *connector, enum pipe unused) |
7bd688cd | 1532 | { |
e6cb3727 | 1533 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd | 1534 | struct intel_panel *panel = &connector->panel; |
636baebf JN |
1535 | u32 ctl, ctl2, val; |
1536 | ||
1537 | ctl2 = I915_READ(BLC_PWM_CTL2); | |
1538 | panel->backlight.combination_mode = ctl2 & BLM_COMBINATION_MODE; | |
1539 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; | |
1540 | ||
1541 | ctl = I915_READ(BLC_PWM_CTL); | |
1542 | panel->backlight.max = ctl >> 16; | |
aa17cdb4 JN |
1543 | |
1544 | if (!panel->backlight.max) | |
1545 | panel->backlight.max = get_backlight_max_vbt(connector); | |
7bd688cd | 1546 | |
7bd688cd JN |
1547 | if (!panel->backlight.max) |
1548 | return -ENODEV; | |
1549 | ||
aa17cdb4 JN |
1550 | if (panel->backlight.combination_mode) |
1551 | panel->backlight.max *= 0xff; | |
1552 | ||
6dda730e JN |
1553 | panel->backlight.min = get_backlight_min_vbt(connector); |
1554 | ||
7bd688cd | 1555 | val = i9xx_get_backlight(connector); |
46e69f39 JN |
1556 | val = intel_panel_compute_brightness(connector, val); |
1557 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1558 | panel->backlight.max); | |
7bd688cd | 1559 | |
46e69f39 | 1560 | panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE; |
636baebf | 1561 | |
7bd688cd JN |
1562 | return 0; |
1563 | } | |
1564 | ||
6517d273 | 1565 | static int vlv_setup_backlight(struct intel_connector *connector, enum pipe pipe) |
7bd688cd | 1566 | { |
e6cb3727 | 1567 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd | 1568 | struct intel_panel *panel = &connector->panel; |
636baebf | 1569 | u32 ctl, ctl2, val; |
7bd688cd | 1570 | |
6517d273 VS |
1571 | if (WARN_ON(pipe != PIPE_A && pipe != PIPE_B)) |
1572 | return -ENODEV; | |
1573 | ||
1574 | ctl2 = I915_READ(VLV_BLC_PWM_CTL2(pipe)); | |
636baebf JN |
1575 | panel->backlight.active_low_pwm = ctl2 & BLM_POLARITY_I965; |
1576 | ||
6517d273 | 1577 | ctl = I915_READ(VLV_BLC_PWM_CTL(pipe)); |
636baebf | 1578 | panel->backlight.max = ctl >> 16; |
aa17cdb4 JN |
1579 | |
1580 | if (!panel->backlight.max) | |
1581 | panel->backlight.max = get_backlight_max_vbt(connector); | |
1582 | ||
7bd688cd JN |
1583 | if (!panel->backlight.max) |
1584 | return -ENODEV; | |
1585 | ||
6dda730e JN |
1586 | panel->backlight.min = get_backlight_min_vbt(connector); |
1587 | ||
e6cb3727 | 1588 | val = _vlv_get_backlight(dev_priv, pipe); |
46e69f39 JN |
1589 | val = intel_panel_compute_brightness(connector, val); |
1590 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1591 | panel->backlight.max); | |
7bd688cd | 1592 | |
46e69f39 | 1593 | panel->backlight.enabled = ctl2 & BLM_PWM_ENABLE; |
636baebf | 1594 | |
7bd688cd JN |
1595 | return 0; |
1596 | } | |
1597 | ||
0fb890c0 VK |
1598 | static int |
1599 | bxt_setup_backlight(struct intel_connector *connector, enum pipe unused) | |
1600 | { | |
e6cb3727 | 1601 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
0fb890c0 VK |
1602 | struct intel_panel *panel = &connector->panel; |
1603 | u32 pwm_ctl, val; | |
1604 | ||
add03379 | 1605 | panel->backlight.controller = dev_priv->vbt.backlight.controller; |
0fb890c0 | 1606 | |
022e4e52 SK |
1607 | pwm_ctl = I915_READ(BXT_BLC_PWM_CTL(panel->backlight.controller)); |
1608 | ||
add03379 | 1609 | /* Controller 1 uses the utility pin. */ |
022e4e52 SK |
1610 | if (panel->backlight.controller == 1) { |
1611 | val = I915_READ(UTIL_PIN_CTL); | |
1612 | panel->backlight.util_pin_active_low = | |
1613 | val & UTIL_PIN_POLARITY; | |
1614 | } | |
1615 | ||
1616 | panel->backlight.active_low_pwm = pwm_ctl & BXT_BLC_PWM_POLARITY; | |
1617 | panel->backlight.max = | |
1618 | I915_READ(BXT_BLC_PWM_FREQ(panel->backlight.controller)); | |
aa17cdb4 JN |
1619 | |
1620 | if (!panel->backlight.max) | |
1621 | panel->backlight.max = get_backlight_max_vbt(connector); | |
1622 | ||
0fb890c0 VK |
1623 | if (!panel->backlight.max) |
1624 | return -ENODEV; | |
1625 | ||
1626 | val = bxt_get_backlight(connector); | |
46e69f39 JN |
1627 | val = intel_panel_compute_brightness(connector, val); |
1628 | panel->backlight.level = clamp(val, panel->backlight.min, | |
1629 | panel->backlight.max); | |
0fb890c0 | 1630 | |
46e69f39 | 1631 | panel->backlight.enabled = pwm_ctl & BXT_BLC_PWM_ENABLE; |
0fb890c0 VK |
1632 | |
1633 | return 0; | |
1634 | } | |
1635 | ||
b029e66f SK |
1636 | static int pwm_setup_backlight(struct intel_connector *connector, |
1637 | enum pipe pipe) | |
1638 | { | |
1639 | struct drm_device *dev = connector->base.dev; | |
1640 | struct intel_panel *panel = &connector->panel; | |
1641 | int retval; | |
1642 | ||
1643 | /* Get the PWM chip for backlight control */ | |
1644 | panel->backlight.pwm = pwm_get(dev->dev, "pwm_backlight"); | |
1645 | if (IS_ERR(panel->backlight.pwm)) { | |
1646 | DRM_ERROR("Failed to own the pwm chip\n"); | |
1647 | panel->backlight.pwm = NULL; | |
1648 | return -ENODEV; | |
1649 | } | |
1650 | ||
2347aa7c BB |
1651 | /* |
1652 | * FIXME: pwm_apply_args() should be removed when switching to | |
1653 | * the atomic PWM API. | |
1654 | */ | |
1655 | pwm_apply_args(panel->backlight.pwm); | |
1656 | ||
b029e66f SK |
1657 | retval = pwm_config(panel->backlight.pwm, CRC_PMIC_PWM_PERIOD_NS, |
1658 | CRC_PMIC_PWM_PERIOD_NS); | |
1659 | if (retval < 0) { | |
1660 | DRM_ERROR("Failed to configure the pwm chip\n"); | |
1661 | pwm_put(panel->backlight.pwm); | |
1662 | panel->backlight.pwm = NULL; | |
1663 | return retval; | |
1664 | } | |
1665 | ||
1666 | panel->backlight.min = 0; /* 0% */ | |
1667 | panel->backlight.max = 100; /* 100% */ | |
1668 | panel->backlight.level = DIV_ROUND_UP( | |
1669 | pwm_get_duty_cycle(panel->backlight.pwm) * 100, | |
1670 | CRC_PMIC_PWM_PERIOD_NS); | |
1671 | panel->backlight.enabled = panel->backlight.level != 0; | |
1672 | ||
1673 | return 0; | |
1674 | } | |
1675 | ||
6517d273 | 1676 | int intel_panel_setup_backlight(struct drm_connector *connector, enum pipe pipe) |
aaa6fd2a | 1677 | { |
e6cb3727 | 1678 | struct drm_i915_private *dev_priv = to_i915(connector->dev); |
db31af1d | 1679 | struct intel_connector *intel_connector = to_intel_connector(connector); |
58c68779 | 1680 | struct intel_panel *panel = &intel_connector->panel; |
7bd688cd | 1681 | int ret; |
db31af1d | 1682 | |
c675949e | 1683 | if (!dev_priv->vbt.backlight.present) { |
9c72cc6f SD |
1684 | if (dev_priv->quirks & QUIRK_BACKLIGHT_PRESENT) { |
1685 | DRM_DEBUG_KMS("no backlight present per VBT, but present per quirk\n"); | |
1686 | } else { | |
1687 | DRM_DEBUG_KMS("no backlight present per VBT\n"); | |
1688 | return 0; | |
1689 | } | |
c675949e JN |
1690 | } |
1691 | ||
5507faeb JN |
1692 | /* ensure intel_panel has been initialized first */ |
1693 | if (WARN_ON(!panel->backlight.setup)) | |
1694 | return -ENODEV; | |
1695 | ||
7bd688cd | 1696 | /* set level and max in panel struct */ |
07f11d49 | 1697 | mutex_lock(&dev_priv->backlight_lock); |
5507faeb | 1698 | ret = panel->backlight.setup(intel_connector, pipe); |
07f11d49 | 1699 | mutex_unlock(&dev_priv->backlight_lock); |
7bd688cd JN |
1700 | |
1701 | if (ret) { | |
1702 | DRM_DEBUG_KMS("failed to setup backlight for connector %s\n", | |
c23cc417 | 1703 | connector->name); |
7bd688cd JN |
1704 | return ret; |
1705 | } | |
db31af1d | 1706 | |
c91c9f32 JN |
1707 | panel->backlight.present = true; |
1708 | ||
0962c3c9 VS |
1709 | DRM_DEBUG_KMS("Connector %s backlight initialized, %s, brightness %u/%u\n", |
1710 | connector->name, | |
08c4d7fc | 1711 | enableddisabled(panel->backlight.enabled), |
0962c3c9 | 1712 | panel->backlight.level, panel->backlight.max); |
c445b3b1 | 1713 | |
aaa6fd2a MG |
1714 | return 0; |
1715 | } | |
1716 | ||
db31af1d | 1717 | void intel_panel_destroy_backlight(struct drm_connector *connector) |
aaa6fd2a | 1718 | { |
db31af1d | 1719 | struct intel_connector *intel_connector = to_intel_connector(connector); |
c91c9f32 | 1720 | struct intel_panel *panel = &intel_connector->panel; |
db31af1d | 1721 | |
b029e66f SK |
1722 | /* dispose of the pwm */ |
1723 | if (panel->backlight.pwm) | |
1724 | pwm_put(panel->backlight.pwm); | |
1725 | ||
c91c9f32 | 1726 | panel->backlight.present = false; |
aaa6fd2a | 1727 | } |
1d508706 | 1728 | |
7bd688cd | 1729 | /* Set up chip specific backlight functions */ |
5507faeb JN |
1730 | static void |
1731 | intel_panel_init_backlight_funcs(struct intel_panel *panel) | |
7bd688cd | 1732 | { |
e6cb3727 | 1733 | struct intel_connector *connector = |
5507faeb | 1734 | container_of(panel, struct intel_connector, panel); |
e6cb3727 | 1735 | struct drm_i915_private *dev_priv = to_i915(connector->base.dev); |
7bd688cd | 1736 | |
e7156c83 YA |
1737 | if (connector->base.connector_type == DRM_MODE_CONNECTOR_eDP && |
1738 | intel_dp_aux_init_backlight_funcs(connector) == 0) | |
1739 | return; | |
1740 | ||
90198355 JN |
1741 | if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI && |
1742 | intel_dsi_dcs_init_backlight_funcs(connector) == 0) | |
1743 | return; | |
1744 | ||
cc3f90f0 | 1745 | if (IS_GEN9_LP(dev_priv)) { |
5507faeb JN |
1746 | panel->backlight.setup = bxt_setup_backlight; |
1747 | panel->backlight.enable = bxt_enable_backlight; | |
1748 | panel->backlight.disable = bxt_disable_backlight; | |
1749 | panel->backlight.set = bxt_set_backlight; | |
1750 | panel->backlight.get = bxt_get_backlight; | |
2dd6982e | 1751 | panel->backlight.hz_to_pwm = bxt_hz_to_pwm; |
22dea0be RV |
1752 | } else if (HAS_PCH_LPT(dev_priv) || HAS_PCH_SPT(dev_priv) || |
1753 | HAS_PCH_KBP(dev_priv)) { | |
5507faeb JN |
1754 | panel->backlight.setup = lpt_setup_backlight; |
1755 | panel->backlight.enable = lpt_enable_backlight; | |
1756 | panel->backlight.disable = lpt_disable_backlight; | |
1757 | panel->backlight.set = lpt_set_backlight; | |
1758 | panel->backlight.get = lpt_get_backlight; | |
e6cb3727 | 1759 | if (HAS_PCH_LPT(dev_priv)) |
5507faeb | 1760 | panel->backlight.hz_to_pwm = lpt_hz_to_pwm; |
aa17cdb4 | 1761 | else |
5507faeb | 1762 | panel->backlight.hz_to_pwm = spt_hz_to_pwm; |
e6cb3727 | 1763 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
5507faeb JN |
1764 | panel->backlight.setup = pch_setup_backlight; |
1765 | panel->backlight.enable = pch_enable_backlight; | |
1766 | panel->backlight.disable = pch_disable_backlight; | |
1767 | panel->backlight.set = pch_set_backlight; | |
1768 | panel->backlight.get = pch_get_backlight; | |
1769 | panel->backlight.hz_to_pwm = pch_hz_to_pwm; | |
e6cb3727 | 1770 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
92c4565e | 1771 | if (connector->base.connector_type == DRM_MODE_CONNECTOR_DSI) { |
5507faeb JN |
1772 | panel->backlight.setup = pwm_setup_backlight; |
1773 | panel->backlight.enable = pwm_enable_backlight; | |
1774 | panel->backlight.disable = pwm_disable_backlight; | |
1775 | panel->backlight.set = pwm_set_backlight; | |
1776 | panel->backlight.get = pwm_get_backlight; | |
b029e66f | 1777 | } else { |
5507faeb JN |
1778 | panel->backlight.setup = vlv_setup_backlight; |
1779 | panel->backlight.enable = vlv_enable_backlight; | |
1780 | panel->backlight.disable = vlv_disable_backlight; | |
1781 | panel->backlight.set = vlv_set_backlight; | |
1782 | panel->backlight.get = vlv_get_backlight; | |
1783 | panel->backlight.hz_to_pwm = vlv_hz_to_pwm; | |
b029e66f | 1784 | } |
e6cb3727 | 1785 | } else if (IS_GEN4(dev_priv)) { |
5507faeb JN |
1786 | panel->backlight.setup = i965_setup_backlight; |
1787 | panel->backlight.enable = i965_enable_backlight; | |
1788 | panel->backlight.disable = i965_disable_backlight; | |
1789 | panel->backlight.set = i9xx_set_backlight; | |
1790 | panel->backlight.get = i9xx_get_backlight; | |
1791 | panel->backlight.hz_to_pwm = i965_hz_to_pwm; | |
7bd688cd | 1792 | } else { |
5507faeb JN |
1793 | panel->backlight.setup = i9xx_setup_backlight; |
1794 | panel->backlight.enable = i9xx_enable_backlight; | |
1795 | panel->backlight.disable = i9xx_disable_backlight; | |
1796 | panel->backlight.set = i9xx_set_backlight; | |
1797 | panel->backlight.get = i9xx_get_backlight; | |
1798 | panel->backlight.hz_to_pwm = i9xx_hz_to_pwm; | |
7bd688cd JN |
1799 | } |
1800 | } | |
1801 | ||
dd06f90e | 1802 | int intel_panel_init(struct intel_panel *panel, |
4b6ed685 VK |
1803 | struct drm_display_mode *fixed_mode, |
1804 | struct drm_display_mode *downclock_mode) | |
1d508706 | 1805 | { |
5507faeb JN |
1806 | intel_panel_init_backlight_funcs(panel); |
1807 | ||
dd06f90e | 1808 | panel->fixed_mode = fixed_mode; |
4b6ed685 | 1809 | panel->downclock_mode = downclock_mode; |
dd06f90e | 1810 | |
1d508706 JN |
1811 | return 0; |
1812 | } | |
1813 | ||
1814 | void intel_panel_fini(struct intel_panel *panel) | |
1815 | { | |
dd06f90e JN |
1816 | struct intel_connector *intel_connector = |
1817 | container_of(panel, struct intel_connector, panel); | |
1818 | ||
1819 | if (panel->fixed_mode) | |
1820 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
ec9ed197 VK |
1821 | |
1822 | if (panel->downclock_mode) | |
1823 | drm_mode_destroy(intel_connector->base.dev, | |
1824 | panel->downclock_mode); | |
1d508706 | 1825 | } |