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1d8e1c75 CW |
1 | /* |
2 | * Copyright © 2006-2010 Intel Corporation | |
3 | * Copyright (c) 2006 Dave Airlie <airlied@linux.ie> | |
4 | * | |
5 | * Permission is hereby granted, free of charge, to any person obtaining a | |
6 | * copy of this software and associated documentation files (the "Software"), | |
7 | * to deal in the Software without restriction, including without limitation | |
8 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
9 | * and/or sell copies of the Software, and to permit persons to whom the | |
10 | * Software is furnished to do so, subject to the following conditions: | |
11 | * | |
12 | * The above copyright notice and this permission notice (including the next | |
13 | * paragraph) shall be included in all copies or substantial portions of the | |
14 | * Software. | |
15 | * | |
16 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
17 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
18 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
19 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
20 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
21 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER | |
22 | * DEALINGS IN THE SOFTWARE. | |
23 | * | |
24 | * Authors: | |
25 | * Eric Anholt <eric@anholt.net> | |
26 | * Dave Airlie <airlied@linux.ie> | |
27 | * Jesse Barnes <jesse.barnes@intel.com> | |
28 | * Chris Wilson <chris@chris-wilson.co.uk> | |
29 | */ | |
30 | ||
a70491cc JP |
31 | #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt |
32 | ||
7bd90909 | 33 | #include <linux/moduleparam.h> |
1d8e1c75 CW |
34 | #include "intel_drv.h" |
35 | ||
ba3820ad TI |
36 | #define PCI_LBPC 0xf4 /* legacy/combination backlight modes */ |
37 | ||
1d8e1c75 CW |
38 | void |
39 | intel_fixed_panel_mode(struct drm_display_mode *fixed_mode, | |
40 | struct drm_display_mode *adjusted_mode) | |
41 | { | |
42 | adjusted_mode->hdisplay = fixed_mode->hdisplay; | |
43 | adjusted_mode->hsync_start = fixed_mode->hsync_start; | |
44 | adjusted_mode->hsync_end = fixed_mode->hsync_end; | |
45 | adjusted_mode->htotal = fixed_mode->htotal; | |
46 | ||
47 | adjusted_mode->vdisplay = fixed_mode->vdisplay; | |
48 | adjusted_mode->vsync_start = fixed_mode->vsync_start; | |
49 | adjusted_mode->vsync_end = fixed_mode->vsync_end; | |
50 | adjusted_mode->vtotal = fixed_mode->vtotal; | |
51 | ||
52 | adjusted_mode->clock = fixed_mode->clock; | |
1d8e1c75 CW |
53 | } |
54 | ||
55 | /* adjusted_mode has been preset to be the panel's fixed mode */ | |
56 | void | |
57 | intel_pch_panel_fitting(struct drm_device *dev, | |
58 | int fitting_mode, | |
cb1793ce | 59 | const struct drm_display_mode *mode, |
1d8e1c75 CW |
60 | struct drm_display_mode *adjusted_mode) |
61 | { | |
62 | struct drm_i915_private *dev_priv = dev->dev_private; | |
63 | int x, y, width, height; | |
64 | ||
65 | x = y = width = height = 0; | |
66 | ||
67 | /* Native modes don't need fitting */ | |
68 | if (adjusted_mode->hdisplay == mode->hdisplay && | |
69 | adjusted_mode->vdisplay == mode->vdisplay) | |
70 | goto done; | |
71 | ||
72 | switch (fitting_mode) { | |
73 | case DRM_MODE_SCALE_CENTER: | |
74 | width = mode->hdisplay; | |
75 | height = mode->vdisplay; | |
76 | x = (adjusted_mode->hdisplay - width + 1)/2; | |
77 | y = (adjusted_mode->vdisplay - height + 1)/2; | |
78 | break; | |
79 | ||
80 | case DRM_MODE_SCALE_ASPECT: | |
81 | /* Scale but preserve the aspect ratio */ | |
82 | { | |
83 | u32 scaled_width = adjusted_mode->hdisplay * mode->vdisplay; | |
84 | u32 scaled_height = mode->hdisplay * adjusted_mode->vdisplay; | |
85 | if (scaled_width > scaled_height) { /* pillar */ | |
86 | width = scaled_height / mode->vdisplay; | |
302983e9 | 87 | if (width & 1) |
0206e353 | 88 | width++; |
1d8e1c75 CW |
89 | x = (adjusted_mode->hdisplay - width + 1) / 2; |
90 | y = 0; | |
91 | height = adjusted_mode->vdisplay; | |
92 | } else if (scaled_width < scaled_height) { /* letter */ | |
93 | height = scaled_width / mode->hdisplay; | |
302983e9 AJ |
94 | if (height & 1) |
95 | height++; | |
1d8e1c75 CW |
96 | y = (adjusted_mode->vdisplay - height + 1) / 2; |
97 | x = 0; | |
98 | width = adjusted_mode->hdisplay; | |
99 | } else { | |
100 | x = y = 0; | |
101 | width = adjusted_mode->hdisplay; | |
102 | height = adjusted_mode->vdisplay; | |
103 | } | |
104 | } | |
105 | break; | |
106 | ||
107 | default: | |
108 | case DRM_MODE_SCALE_FULLSCREEN: | |
109 | x = y = 0; | |
110 | width = adjusted_mode->hdisplay; | |
111 | height = adjusted_mode->vdisplay; | |
112 | break; | |
113 | } | |
114 | ||
115 | done: | |
116 | dev_priv->pch_pf_pos = (x << 16) | y; | |
117 | dev_priv->pch_pf_size = (width << 16) | height; | |
118 | } | |
a9573556 | 119 | |
ba3820ad TI |
120 | static int is_backlight_combination_mode(struct drm_device *dev) |
121 | { | |
122 | struct drm_i915_private *dev_priv = dev->dev_private; | |
123 | ||
124 | if (INTEL_INFO(dev)->gen >= 4) | |
125 | return I915_READ(BLC_PWM_CTL2) & BLM_COMBINATION_MODE; | |
126 | ||
127 | if (IS_GEN2(dev)) | |
128 | return I915_READ(BLC_PWM_CTL) & BLM_LEGACY_MODE; | |
129 | ||
130 | return 0; | |
131 | } | |
132 | ||
d6540632 JN |
133 | /* XXX: query mode clock or hardware clock and program max PWM appropriately |
134 | * when it's 0. | |
135 | */ | |
bfd7590d | 136 | static u32 i915_read_blc_pwm_ctl(struct drm_device *dev) |
0b0b053a | 137 | { |
bfd7590d | 138 | struct drm_i915_private *dev_priv = dev->dev_private; |
0b0b053a CW |
139 | u32 val; |
140 | ||
141 | /* Restore the CTL value if it lost, e.g. GPU reset */ | |
142 | ||
143 | if (HAS_PCH_SPLIT(dev_priv->dev)) { | |
144 | val = I915_READ(BLC_PWM_PCH_CTL2); | |
f4c956ad DV |
145 | if (dev_priv->regfile.saveBLC_PWM_CTL2 == 0) { |
146 | dev_priv->regfile.saveBLC_PWM_CTL2 = val; | |
0b0b053a | 147 | } else if (val == 0) { |
f4c956ad | 148 | val = dev_priv->regfile.saveBLC_PWM_CTL2; |
bfd7590d | 149 | I915_WRITE(BLC_PWM_PCH_CTL2, val); |
0b0b053a CW |
150 | } |
151 | } else { | |
152 | val = I915_READ(BLC_PWM_CTL); | |
f4c956ad DV |
153 | if (dev_priv->regfile.saveBLC_PWM_CTL == 0) { |
154 | dev_priv->regfile.saveBLC_PWM_CTL = val; | |
bfd7590d JN |
155 | if (INTEL_INFO(dev)->gen >= 4) |
156 | dev_priv->regfile.saveBLC_PWM_CTL2 = | |
157 | I915_READ(BLC_PWM_CTL2); | |
0b0b053a | 158 | } else if (val == 0) { |
f4c956ad | 159 | val = dev_priv->regfile.saveBLC_PWM_CTL; |
bfd7590d JN |
160 | I915_WRITE(BLC_PWM_CTL, val); |
161 | if (INTEL_INFO(dev)->gen >= 4) | |
162 | I915_WRITE(BLC_PWM_CTL2, | |
163 | dev_priv->regfile.saveBLC_PWM_CTL2); | |
0b0b053a CW |
164 | } |
165 | } | |
166 | ||
167 | return val; | |
168 | } | |
169 | ||
d6540632 | 170 | static u32 intel_panel_get_max_backlight(struct drm_device *dev) |
a9573556 | 171 | { |
a9573556 CW |
172 | u32 max; |
173 | ||
bfd7590d | 174 | max = i915_read_blc_pwm_ctl(dev); |
0b0b053a | 175 | |
a9573556 | 176 | if (HAS_PCH_SPLIT(dev)) { |
0b0b053a | 177 | max >>= 16; |
a9573556 | 178 | } else { |
ca88479c | 179 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 180 | max >>= 17; |
ca88479c | 181 | else |
a9573556 | 182 | max >>= 16; |
ba3820ad TI |
183 | |
184 | if (is_backlight_combination_mode(dev)) | |
185 | max *= 0xff; | |
a9573556 CW |
186 | } |
187 | ||
a9573556 | 188 | DRM_DEBUG_DRIVER("max backlight PWM = %d\n", max); |
d6540632 | 189 | |
a9573556 CW |
190 | return max; |
191 | } | |
192 | ||
4dca20ef CE |
193 | static int i915_panel_invert_brightness; |
194 | MODULE_PARM_DESC(invert_brightness, "Invert backlight brightness " | |
195 | "(-1 force normal, 0 machine defaults, 1 force inversion), please " | |
7bd90909 CE |
196 | "report PCI device ID, subsystem vendor and subsystem device ID " |
197 | "to dri-devel@lists.freedesktop.org, if your machine needs it. " | |
198 | "It will then be included in an upcoming module version."); | |
4dca20ef | 199 | module_param_named(invert_brightness, i915_panel_invert_brightness, int, 0600); |
7bd90909 CE |
200 | static u32 intel_panel_compute_brightness(struct drm_device *dev, u32 val) |
201 | { | |
4dca20ef CE |
202 | struct drm_i915_private *dev_priv = dev->dev_private; |
203 | ||
204 | if (i915_panel_invert_brightness < 0) | |
205 | return val; | |
206 | ||
207 | if (i915_panel_invert_brightness > 0 || | |
d6540632 JN |
208 | dev_priv->quirks & QUIRK_INVERT_BRIGHTNESS) { |
209 | u32 max = intel_panel_get_max_backlight(dev); | |
210 | if (max) | |
211 | return max - val; | |
212 | } | |
7bd90909 CE |
213 | |
214 | return val; | |
215 | } | |
216 | ||
faea35dd | 217 | static u32 intel_panel_get_backlight(struct drm_device *dev) |
a9573556 CW |
218 | { |
219 | struct drm_i915_private *dev_priv = dev->dev_private; | |
220 | u32 val; | |
221 | ||
222 | if (HAS_PCH_SPLIT(dev)) { | |
223 | val = I915_READ(BLC_PWM_CPU_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; | |
224 | } else { | |
225 | val = I915_READ(BLC_PWM_CTL) & BACKLIGHT_DUTY_CYCLE_MASK; | |
ca88479c | 226 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 227 | val >>= 1; |
ba3820ad | 228 | |
0206e353 | 229 | if (is_backlight_combination_mode(dev)) { |
ba3820ad TI |
230 | u8 lbpc; |
231 | ||
ba3820ad TI |
232 | pci_read_config_byte(dev->pdev, PCI_LBPC, &lbpc); |
233 | val *= lbpc; | |
234 | } | |
a9573556 CW |
235 | } |
236 | ||
7bd90909 | 237 | val = intel_panel_compute_brightness(dev, val); |
a9573556 CW |
238 | DRM_DEBUG_DRIVER("get backlight PWM = %d\n", val); |
239 | return val; | |
240 | } | |
241 | ||
242 | static void intel_pch_panel_set_backlight(struct drm_device *dev, u32 level) | |
243 | { | |
244 | struct drm_i915_private *dev_priv = dev->dev_private; | |
245 | u32 val = I915_READ(BLC_PWM_CPU_CTL) & ~BACKLIGHT_DUTY_CYCLE_MASK; | |
246 | I915_WRITE(BLC_PWM_CPU_CTL, val | level); | |
247 | } | |
248 | ||
f52c619a | 249 | static void intel_panel_actually_set_backlight(struct drm_device *dev, u32 level) |
a9573556 CW |
250 | { |
251 | struct drm_i915_private *dev_priv = dev->dev_private; | |
252 | u32 tmp; | |
253 | ||
254 | DRM_DEBUG_DRIVER("set backlight PWM = %d\n", level); | |
7bd90909 | 255 | level = intel_panel_compute_brightness(dev, level); |
a9573556 CW |
256 | |
257 | if (HAS_PCH_SPLIT(dev)) | |
258 | return intel_pch_panel_set_backlight(dev, level); | |
ba3820ad | 259 | |
0206e353 | 260 | if (is_backlight_combination_mode(dev)) { |
ba3820ad TI |
261 | u32 max = intel_panel_get_max_backlight(dev); |
262 | u8 lbpc; | |
263 | ||
d6540632 JN |
264 | /* we're screwed, but keep behaviour backwards compatible */ |
265 | if (!max) | |
266 | max = 1; | |
267 | ||
ba3820ad TI |
268 | lbpc = level * 0xfe / max + 1; |
269 | level /= lbpc; | |
270 | pci_write_config_byte(dev->pdev, PCI_LBPC, lbpc); | |
271 | } | |
272 | ||
a9573556 | 273 | tmp = I915_READ(BLC_PWM_CTL); |
a726915c | 274 | if (INTEL_INFO(dev)->gen < 4) |
a9573556 | 275 | level <<= 1; |
ca88479c | 276 | tmp &= ~BACKLIGHT_DUTY_CYCLE_MASK; |
a9573556 CW |
277 | I915_WRITE(BLC_PWM_CTL, tmp | level); |
278 | } | |
47356eb6 | 279 | |
d6540632 JN |
280 | /* set backlight brightness to level in range [0..max] */ |
281 | void intel_panel_set_backlight(struct drm_device *dev, u32 level, u32 max) | |
47356eb6 CW |
282 | { |
283 | struct drm_i915_private *dev_priv = dev->dev_private; | |
d6540632 JN |
284 | u32 freq; |
285 | ||
286 | freq = intel_panel_get_max_backlight(dev); | |
287 | if (!freq) { | |
288 | /* we are screwed, bail out */ | |
289 | return; | |
290 | } | |
291 | ||
292 | /* scale to hardware */ | |
293 | level = level * freq / max; | |
47356eb6 | 294 | |
31ad8ec6 JN |
295 | dev_priv->backlight.level = level; |
296 | if (dev_priv->backlight.device) | |
297 | dev_priv->backlight.device->props.brightness = level; | |
b6b3ba5b | 298 | |
31ad8ec6 | 299 | if (dev_priv->backlight.enabled) |
f52c619a TI |
300 | intel_panel_actually_set_backlight(dev, level); |
301 | } | |
302 | ||
303 | void intel_panel_disable_backlight(struct drm_device *dev) | |
304 | { | |
305 | struct drm_i915_private *dev_priv = dev->dev_private; | |
47356eb6 | 306 | |
31ad8ec6 | 307 | dev_priv->backlight.enabled = false; |
f52c619a | 308 | intel_panel_actually_set_backlight(dev, 0); |
24ded204 DV |
309 | |
310 | if (INTEL_INFO(dev)->gen >= 4) { | |
a4f32fc3 | 311 | uint32_t reg, tmp; |
24ded204 DV |
312 | |
313 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; | |
314 | ||
315 | I915_WRITE(reg, I915_READ(reg) & ~BLM_PWM_ENABLE); | |
a4f32fc3 PZ |
316 | |
317 | if (HAS_PCH_SPLIT(dev)) { | |
318 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
319 | tmp &= ~BLM_PCH_PWM_ENABLE; | |
320 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); | |
321 | } | |
24ded204 | 322 | } |
47356eb6 CW |
323 | } |
324 | ||
24ded204 DV |
325 | void intel_panel_enable_backlight(struct drm_device *dev, |
326 | enum pipe pipe) | |
47356eb6 CW |
327 | { |
328 | struct drm_i915_private *dev_priv = dev->dev_private; | |
329 | ||
31ad8ec6 JN |
330 | if (dev_priv->backlight.level == 0) { |
331 | dev_priv->backlight.level = intel_panel_get_max_backlight(dev); | |
332 | if (dev_priv->backlight.device) | |
333 | dev_priv->backlight.device->props.brightness = | |
334 | dev_priv->backlight.level; | |
b6b3ba5b | 335 | } |
47356eb6 | 336 | |
24ded204 DV |
337 | if (INTEL_INFO(dev)->gen >= 4) { |
338 | uint32_t reg, tmp; | |
339 | ||
340 | reg = HAS_PCH_SPLIT(dev) ? BLC_PWM_CPU_CTL2 : BLC_PWM_CTL2; | |
341 | ||
342 | ||
343 | tmp = I915_READ(reg); | |
344 | ||
345 | /* Note that this can also get called through dpms changes. And | |
346 | * we don't track the backlight dpms state, hence check whether | |
347 | * we have to do anything first. */ | |
348 | if (tmp & BLM_PWM_ENABLE) | |
770c1231 | 349 | goto set_level; |
24ded204 | 350 | |
7eb552ae | 351 | if (INTEL_INFO(dev)->num_pipes == 3) |
24ded204 DV |
352 | tmp &= ~BLM_PIPE_SELECT_IVB; |
353 | else | |
354 | tmp &= ~BLM_PIPE_SELECT; | |
355 | ||
356 | tmp |= BLM_PIPE(pipe); | |
357 | tmp &= ~BLM_PWM_ENABLE; | |
358 | ||
359 | I915_WRITE(reg, tmp); | |
360 | POSTING_READ(reg); | |
361 | I915_WRITE(reg, tmp | BLM_PWM_ENABLE); | |
a4f32fc3 PZ |
362 | |
363 | if (HAS_PCH_SPLIT(dev)) { | |
364 | tmp = I915_READ(BLC_PWM_PCH_CTL1); | |
365 | tmp |= BLM_PCH_PWM_ENABLE; | |
366 | tmp &= ~BLM_PCH_OVERRIDE_ENABLE; | |
367 | I915_WRITE(BLC_PWM_PCH_CTL1, tmp); | |
368 | } | |
24ded204 | 369 | } |
770c1231 TI |
370 | |
371 | set_level: | |
b1289371 DV |
372 | /* Call below after setting BLC_PWM_CPU_CTL2 and BLC_PWM_PCH_CTL1. |
373 | * BLC_PWM_CPU_CTL may be cleared to zero automatically when these | |
374 | * registers are set. | |
770c1231 | 375 | */ |
ecb135a1 DV |
376 | dev_priv->backlight.enabled = true; |
377 | intel_panel_actually_set_backlight(dev, dev_priv->backlight.level); | |
47356eb6 CW |
378 | } |
379 | ||
aaa6fd2a | 380 | static void intel_panel_init_backlight(struct drm_device *dev) |
47356eb6 CW |
381 | { |
382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
383 | ||
31ad8ec6 JN |
384 | dev_priv->backlight.level = intel_panel_get_backlight(dev); |
385 | dev_priv->backlight.enabled = dev_priv->backlight.level != 0; | |
47356eb6 | 386 | } |
fe16d949 CW |
387 | |
388 | enum drm_connector_status | |
389 | intel_panel_detect(struct drm_device *dev) | |
390 | { | |
391 | struct drm_i915_private *dev_priv = dev->dev_private; | |
392 | ||
393 | /* Assume that the BIOS does not lie through the OpRegion... */ | |
a726915c | 394 | if (!i915_panel_ignore_lid && dev_priv->opregion.lid_state) { |
fe16d949 CW |
395 | return ioread32(dev_priv->opregion.lid_state) & 0x1 ? |
396 | connector_status_connected : | |
397 | connector_status_disconnected; | |
a726915c | 398 | } |
fe16d949 | 399 | |
a726915c DV |
400 | switch (i915_panel_ignore_lid) { |
401 | case -2: | |
402 | return connector_status_connected; | |
403 | case -1: | |
404 | return connector_status_disconnected; | |
405 | default: | |
406 | return connector_status_unknown; | |
407 | } | |
fe16d949 | 408 | } |
aaa6fd2a MG |
409 | |
410 | #ifdef CONFIG_BACKLIGHT_CLASS_DEVICE | |
411 | static int intel_panel_update_status(struct backlight_device *bd) | |
412 | { | |
413 | struct drm_device *dev = bl_get_data(bd); | |
d6540632 JN |
414 | intel_panel_set_backlight(dev, bd->props.brightness, |
415 | bd->props.max_brightness); | |
aaa6fd2a MG |
416 | return 0; |
417 | } | |
418 | ||
419 | static int intel_panel_get_brightness(struct backlight_device *bd) | |
420 | { | |
421 | struct drm_device *dev = bl_get_data(bd); | |
7c23396b | 422 | return intel_panel_get_backlight(dev); |
aaa6fd2a MG |
423 | } |
424 | ||
425 | static const struct backlight_ops intel_panel_bl_ops = { | |
426 | .update_status = intel_panel_update_status, | |
427 | .get_brightness = intel_panel_get_brightness, | |
428 | }; | |
429 | ||
0657b6b1 | 430 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 431 | { |
0657b6b1 | 432 | struct drm_device *dev = connector->dev; |
aaa6fd2a MG |
433 | struct drm_i915_private *dev_priv = dev->dev_private; |
434 | struct backlight_properties props; | |
aaa6fd2a MG |
435 | |
436 | intel_panel_init_backlight(dev); | |
437 | ||
dc652f90 JN |
438 | if (WARN_ON(dev_priv->backlight.device)) |
439 | return -ENODEV; | |
440 | ||
af437cfd | 441 | memset(&props, 0, sizeof(props)); |
aaa6fd2a | 442 | props.type = BACKLIGHT_RAW; |
31ad8ec6 | 443 | props.brightness = dev_priv->backlight.level; |
d6540632 | 444 | props.max_brightness = intel_panel_get_max_backlight(dev); |
28dcc2d6 | 445 | if (props.max_brightness == 0) { |
e86b6185 | 446 | DRM_DEBUG_DRIVER("Failed to get maximum backlight value\n"); |
28dcc2d6 JN |
447 | return -ENODEV; |
448 | } | |
31ad8ec6 | 449 | dev_priv->backlight.device = |
aaa6fd2a MG |
450 | backlight_device_register("intel_backlight", |
451 | &connector->kdev, dev, | |
452 | &intel_panel_bl_ops, &props); | |
453 | ||
31ad8ec6 | 454 | if (IS_ERR(dev_priv->backlight.device)) { |
aaa6fd2a | 455 | DRM_ERROR("Failed to register backlight: %ld\n", |
31ad8ec6 JN |
456 | PTR_ERR(dev_priv->backlight.device)); |
457 | dev_priv->backlight.device = NULL; | |
aaa6fd2a MG |
458 | return -ENODEV; |
459 | } | |
aaa6fd2a MG |
460 | return 0; |
461 | } | |
462 | ||
463 | void intel_panel_destroy_backlight(struct drm_device *dev) | |
464 | { | |
465 | struct drm_i915_private *dev_priv = dev->dev_private; | |
dc652f90 | 466 | if (dev_priv->backlight.device) { |
31ad8ec6 | 467 | backlight_device_unregister(dev_priv->backlight.device); |
dc652f90 JN |
468 | dev_priv->backlight.device = NULL; |
469 | } | |
aaa6fd2a MG |
470 | } |
471 | #else | |
0657b6b1 | 472 | int intel_panel_setup_backlight(struct drm_connector *connector) |
aaa6fd2a | 473 | { |
0657b6b1 | 474 | intel_panel_init_backlight(connector->dev); |
aaa6fd2a MG |
475 | return 0; |
476 | } | |
477 | ||
478 | void intel_panel_destroy_backlight(struct drm_device *dev) | |
479 | { | |
480 | return; | |
481 | } | |
482 | #endif | |
1d508706 | 483 | |
dd06f90e JN |
484 | int intel_panel_init(struct intel_panel *panel, |
485 | struct drm_display_mode *fixed_mode) | |
1d508706 | 486 | { |
dd06f90e JN |
487 | panel->fixed_mode = fixed_mode; |
488 | ||
1d508706 JN |
489 | return 0; |
490 | } | |
491 | ||
492 | void intel_panel_fini(struct intel_panel *panel) | |
493 | { | |
dd06f90e JN |
494 | struct intel_connector *intel_connector = |
495 | container_of(panel, struct intel_connector, panel); | |
496 | ||
497 | if (panel->fixed_mode) | |
498 | drm_mode_destroy(intel_connector->base.dev, panel->fixed_mode); | |
1d508706 | 499 | } |