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731035fe TV |
1 | /* |
2 | * Copyright © 2013 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Author: Damien Lespiau <damien.lespiau@intel.com> | |
24 | * | |
25 | */ | |
26 | ||
27 | #include <linux/seq_file.h> | |
28 | #include <linux/circ_buf.h> | |
29 | #include <linux/ctype.h> | |
30 | #include <linux/debugfs.h> | |
31 | #include "intel_drv.h" | |
32 | ||
33 | struct pipe_crc_info { | |
34 | const char *name; | |
35 | struct drm_i915_private *dev_priv; | |
36 | enum pipe pipe; | |
37 | }; | |
38 | ||
731035fe TV |
39 | static int i915_pipe_crc_open(struct inode *inode, struct file *filep) |
40 | { | |
41 | struct pipe_crc_info *info = inode->i_private; | |
42 | struct drm_i915_private *dev_priv = info->dev_priv; | |
43 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
44 | ||
45 | if (info->pipe >= INTEL_INFO(dev_priv)->num_pipes) | |
46 | return -ENODEV; | |
47 | ||
48 | spin_lock_irq(&pipe_crc->lock); | |
49 | ||
50 | if (pipe_crc->opened) { | |
51 | spin_unlock_irq(&pipe_crc->lock); | |
52 | return -EBUSY; /* already open */ | |
53 | } | |
54 | ||
55 | pipe_crc->opened = true; | |
56 | filep->private_data = inode->i_private; | |
57 | ||
58 | spin_unlock_irq(&pipe_crc->lock); | |
59 | ||
60 | return 0; | |
61 | } | |
62 | ||
63 | static int i915_pipe_crc_release(struct inode *inode, struct file *filep) | |
64 | { | |
65 | struct pipe_crc_info *info = inode->i_private; | |
66 | struct drm_i915_private *dev_priv = info->dev_priv; | |
67 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
68 | ||
69 | spin_lock_irq(&pipe_crc->lock); | |
70 | pipe_crc->opened = false; | |
71 | spin_unlock_irq(&pipe_crc->lock); | |
72 | ||
73 | return 0; | |
74 | } | |
75 | ||
76 | /* (6 fields, 8 chars each, space separated (5) + '\n') */ | |
77 | #define PIPE_CRC_LINE_LEN (6 * 8 + 5 + 1) | |
78 | /* account for \'0' */ | |
79 | #define PIPE_CRC_BUFFER_LEN (PIPE_CRC_LINE_LEN + 1) | |
80 | ||
81 | static int pipe_crc_data_count(struct intel_pipe_crc *pipe_crc) | |
82 | { | |
67520415 | 83 | lockdep_assert_held(&pipe_crc->lock); |
731035fe TV |
84 | return CIRC_CNT(pipe_crc->head, pipe_crc->tail, |
85 | INTEL_PIPE_CRC_ENTRIES_NR); | |
86 | } | |
87 | ||
88 | static ssize_t | |
89 | i915_pipe_crc_read(struct file *filep, char __user *user_buf, size_t count, | |
90 | loff_t *pos) | |
91 | { | |
92 | struct pipe_crc_info *info = filep->private_data; | |
93 | struct drm_i915_private *dev_priv = info->dev_priv; | |
94 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[info->pipe]; | |
95 | char buf[PIPE_CRC_BUFFER_LEN]; | |
96 | int n_entries; | |
97 | ssize_t bytes_read; | |
98 | ||
99 | /* | |
100 | * Don't allow user space to provide buffers not big enough to hold | |
101 | * a line of data. | |
102 | */ | |
103 | if (count < PIPE_CRC_LINE_LEN) | |
104 | return -EINVAL; | |
105 | ||
106 | if (pipe_crc->source == INTEL_PIPE_CRC_SOURCE_NONE) | |
107 | return 0; | |
108 | ||
109 | /* nothing to read */ | |
110 | spin_lock_irq(&pipe_crc->lock); | |
111 | while (pipe_crc_data_count(pipe_crc) == 0) { | |
112 | int ret; | |
113 | ||
114 | if (filep->f_flags & O_NONBLOCK) { | |
115 | spin_unlock_irq(&pipe_crc->lock); | |
116 | return -EAGAIN; | |
117 | } | |
118 | ||
119 | ret = wait_event_interruptible_lock_irq(pipe_crc->wq, | |
120 | pipe_crc_data_count(pipe_crc), pipe_crc->lock); | |
121 | if (ret) { | |
122 | spin_unlock_irq(&pipe_crc->lock); | |
123 | return ret; | |
124 | } | |
125 | } | |
126 | ||
127 | /* We now have one or more entries to read */ | |
128 | n_entries = count / PIPE_CRC_LINE_LEN; | |
129 | ||
130 | bytes_read = 0; | |
131 | while (n_entries > 0) { | |
132 | struct intel_pipe_crc_entry *entry = | |
133 | &pipe_crc->entries[pipe_crc->tail]; | |
134 | ||
135 | if (CIRC_CNT(pipe_crc->head, pipe_crc->tail, | |
136 | INTEL_PIPE_CRC_ENTRIES_NR) < 1) | |
137 | break; | |
138 | ||
139 | BUILD_BUG_ON_NOT_POWER_OF_2(INTEL_PIPE_CRC_ENTRIES_NR); | |
140 | pipe_crc->tail = (pipe_crc->tail + 1) & | |
141 | (INTEL_PIPE_CRC_ENTRIES_NR - 1); | |
142 | ||
143 | bytes_read += snprintf(buf, PIPE_CRC_BUFFER_LEN, | |
144 | "%8u %8x %8x %8x %8x %8x\n", | |
145 | entry->frame, entry->crc[0], | |
146 | entry->crc[1], entry->crc[2], | |
147 | entry->crc[3], entry->crc[4]); | |
148 | ||
149 | spin_unlock_irq(&pipe_crc->lock); | |
150 | ||
151 | if (copy_to_user(user_buf, buf, PIPE_CRC_LINE_LEN)) | |
152 | return -EFAULT; | |
153 | ||
154 | user_buf += PIPE_CRC_LINE_LEN; | |
155 | n_entries--; | |
156 | ||
157 | spin_lock_irq(&pipe_crc->lock); | |
158 | } | |
159 | ||
160 | spin_unlock_irq(&pipe_crc->lock); | |
161 | ||
162 | return bytes_read; | |
163 | } | |
164 | ||
165 | static const struct file_operations i915_pipe_crc_fops = { | |
166 | .owner = THIS_MODULE, | |
167 | .open = i915_pipe_crc_open, | |
168 | .read = i915_pipe_crc_read, | |
169 | .release = i915_pipe_crc_release, | |
170 | }; | |
171 | ||
172 | static struct pipe_crc_info i915_pipe_crc_data[I915_MAX_PIPES] = { | |
173 | { | |
174 | .name = "i915_pipe_A_crc", | |
175 | .pipe = PIPE_A, | |
176 | }, | |
177 | { | |
178 | .name = "i915_pipe_B_crc", | |
179 | .pipe = PIPE_B, | |
180 | }, | |
181 | { | |
182 | .name = "i915_pipe_C_crc", | |
183 | .pipe = PIPE_C, | |
184 | }, | |
185 | }; | |
186 | ||
731035fe TV |
187 | static const char * const pipe_crc_sources[] = { |
188 | "none", | |
189 | "plane1", | |
190 | "plane2", | |
191 | "pf", | |
192 | "pipe", | |
193 | "TV", | |
194 | "DP-B", | |
195 | "DP-C", | |
196 | "DP-D", | |
197 | "auto", | |
198 | }; | |
199 | ||
200 | static const char *pipe_crc_source_name(enum intel_pipe_crc_source source) | |
201 | { | |
202 | BUILD_BUG_ON(ARRAY_SIZE(pipe_crc_sources) != INTEL_PIPE_CRC_SOURCE_MAX); | |
203 | return pipe_crc_sources[source]; | |
204 | } | |
205 | ||
206 | static int display_crc_ctl_show(struct seq_file *m, void *data) | |
207 | { | |
208 | struct drm_i915_private *dev_priv = m->private; | |
209 | int i; | |
210 | ||
211 | for (i = 0; i < I915_MAX_PIPES; i++) | |
212 | seq_printf(m, "%c %s\n", pipe_name(i), | |
213 | pipe_crc_source_name(dev_priv->pipe_crc[i].source)); | |
214 | ||
215 | return 0; | |
216 | } | |
217 | ||
218 | static int display_crc_ctl_open(struct inode *inode, struct file *file) | |
219 | { | |
220 | return single_open(file, display_crc_ctl_show, inode->i_private); | |
221 | } | |
222 | ||
223 | static int i8xx_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, | |
224 | uint32_t *val) | |
225 | { | |
226 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) | |
227 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
228 | ||
229 | switch (*source) { | |
230 | case INTEL_PIPE_CRC_SOURCE_PIPE: | |
231 | *val = PIPE_CRC_ENABLE | PIPE_CRC_INCLUDE_BORDER_I8XX; | |
232 | break; | |
233 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
234 | *val = 0; | |
235 | break; | |
236 | default: | |
237 | return -EINVAL; | |
238 | } | |
239 | ||
240 | return 0; | |
241 | } | |
242 | ||
243 | static int i9xx_pipe_crc_auto_source(struct drm_i915_private *dev_priv, | |
244 | enum pipe pipe, | |
245 | enum intel_pipe_crc_source *source) | |
246 | { | |
247 | struct drm_device *dev = &dev_priv->drm; | |
248 | struct intel_encoder *encoder; | |
249 | struct intel_crtc *crtc; | |
250 | struct intel_digital_port *dig_port; | |
251 | int ret = 0; | |
252 | ||
253 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
254 | ||
255 | drm_modeset_lock_all(dev); | |
256 | for_each_intel_encoder(dev, encoder) { | |
257 | if (!encoder->base.crtc) | |
258 | continue; | |
259 | ||
260 | crtc = to_intel_crtc(encoder->base.crtc); | |
261 | ||
262 | if (crtc->pipe != pipe) | |
263 | continue; | |
264 | ||
265 | switch (encoder->type) { | |
266 | case INTEL_OUTPUT_TVOUT: | |
267 | *source = INTEL_PIPE_CRC_SOURCE_TV; | |
268 | break; | |
269 | case INTEL_OUTPUT_DP: | |
270 | case INTEL_OUTPUT_EDP: | |
271 | dig_port = enc_to_dig_port(&encoder->base); | |
272 | switch (dig_port->port) { | |
273 | case PORT_B: | |
274 | *source = INTEL_PIPE_CRC_SOURCE_DP_B; | |
275 | break; | |
276 | case PORT_C: | |
277 | *source = INTEL_PIPE_CRC_SOURCE_DP_C; | |
278 | break; | |
279 | case PORT_D: | |
280 | *source = INTEL_PIPE_CRC_SOURCE_DP_D; | |
281 | break; | |
282 | default: | |
283 | WARN(1, "nonexisting DP port %c\n", | |
284 | port_name(dig_port->port)); | |
285 | break; | |
286 | } | |
287 | break; | |
288 | default: | |
289 | break; | |
290 | } | |
291 | } | |
292 | drm_modeset_unlock_all(dev); | |
293 | ||
294 | return ret; | |
295 | } | |
296 | ||
297 | static int vlv_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, | |
298 | enum pipe pipe, | |
299 | enum intel_pipe_crc_source *source, | |
300 | uint32_t *val) | |
301 | { | |
302 | bool need_stable_symbols = false; | |
303 | ||
304 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { | |
305 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); | |
306 | if (ret) | |
307 | return ret; | |
308 | } | |
309 | ||
310 | switch (*source) { | |
311 | case INTEL_PIPE_CRC_SOURCE_PIPE: | |
312 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_VLV; | |
313 | break; | |
314 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
315 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_VLV; | |
316 | need_stable_symbols = true; | |
317 | break; | |
318 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
319 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_VLV; | |
320 | need_stable_symbols = true; | |
321 | break; | |
322 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
323 | if (!IS_CHERRYVIEW(dev_priv)) | |
324 | return -EINVAL; | |
325 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_VLV; | |
326 | need_stable_symbols = true; | |
327 | break; | |
328 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
329 | *val = 0; | |
330 | break; | |
331 | default: | |
332 | return -EINVAL; | |
333 | } | |
334 | ||
335 | /* | |
336 | * When the pipe CRC tap point is after the transcoders we need | |
337 | * to tweak symbol-level features to produce a deterministic series of | |
338 | * symbols for a given frame. We need to reset those features only once | |
339 | * a frame (instead of every nth symbol): | |
340 | * - DC-balance: used to ensure a better clock recovery from the data | |
341 | * link (SDVO) | |
342 | * - DisplayPort scrambling: used for EMI reduction | |
343 | */ | |
344 | if (need_stable_symbols) { | |
345 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
346 | ||
347 | tmp |= DC_BALANCE_RESET_VLV; | |
348 | switch (pipe) { | |
349 | case PIPE_A: | |
350 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
351 | break; | |
352 | case PIPE_B: | |
353 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
354 | break; | |
355 | case PIPE_C: | |
356 | tmp |= PIPE_C_SCRAMBLE_RESET; | |
357 | break; | |
358 | default: | |
359 | return -EINVAL; | |
360 | } | |
361 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
362 | } | |
363 | ||
364 | return 0; | |
365 | } | |
366 | ||
367 | static int i9xx_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, | |
368 | enum pipe pipe, | |
369 | enum intel_pipe_crc_source *source, | |
370 | uint32_t *val) | |
371 | { | |
372 | bool need_stable_symbols = false; | |
373 | ||
374 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) { | |
375 | int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); | |
376 | if (ret) | |
377 | return ret; | |
378 | } | |
379 | ||
380 | switch (*source) { | |
381 | case INTEL_PIPE_CRC_SOURCE_PIPE: | |
382 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_I9XX; | |
383 | break; | |
384 | case INTEL_PIPE_CRC_SOURCE_TV: | |
385 | if (!SUPPORTS_TV(dev_priv)) | |
386 | return -EINVAL; | |
387 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_TV_PRE; | |
388 | break; | |
389 | case INTEL_PIPE_CRC_SOURCE_DP_B: | |
390 | if (!IS_G4X(dev_priv)) | |
391 | return -EINVAL; | |
392 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_B_G4X; | |
393 | need_stable_symbols = true; | |
394 | break; | |
395 | case INTEL_PIPE_CRC_SOURCE_DP_C: | |
396 | if (!IS_G4X(dev_priv)) | |
397 | return -EINVAL; | |
398 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_C_G4X; | |
399 | need_stable_symbols = true; | |
400 | break; | |
401 | case INTEL_PIPE_CRC_SOURCE_DP_D: | |
402 | if (!IS_G4X(dev_priv)) | |
403 | return -EINVAL; | |
404 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_DP_D_G4X; | |
405 | need_stable_symbols = true; | |
406 | break; | |
407 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
408 | *val = 0; | |
409 | break; | |
410 | default: | |
411 | return -EINVAL; | |
412 | } | |
413 | ||
414 | /* | |
415 | * When the pipe CRC tap point is after the transcoders we need | |
416 | * to tweak symbol-level features to produce a deterministic series of | |
417 | * symbols for a given frame. We need to reset those features only once | |
418 | * a frame (instead of every nth symbol): | |
419 | * - DC-balance: used to ensure a better clock recovery from the data | |
420 | * link (SDVO) | |
421 | * - DisplayPort scrambling: used for EMI reduction | |
422 | */ | |
423 | if (need_stable_symbols) { | |
424 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
425 | ||
426 | WARN_ON(!IS_G4X(dev_priv)); | |
427 | ||
428 | I915_WRITE(PORT_DFT_I9XX, | |
429 | I915_READ(PORT_DFT_I9XX) | DC_BALANCE_RESET); | |
430 | ||
431 | if (pipe == PIPE_A) | |
432 | tmp |= PIPE_A_SCRAMBLE_RESET; | |
433 | else | |
434 | tmp |= PIPE_B_SCRAMBLE_RESET; | |
435 | ||
436 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
437 | } | |
438 | ||
439 | return 0; | |
440 | } | |
441 | ||
442 | static void vlv_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, | |
443 | enum pipe pipe) | |
444 | { | |
445 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
446 | ||
447 | switch (pipe) { | |
448 | case PIPE_A: | |
449 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
450 | break; | |
451 | case PIPE_B: | |
452 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
453 | break; | |
454 | case PIPE_C: | |
455 | tmp &= ~PIPE_C_SCRAMBLE_RESET; | |
456 | break; | |
457 | default: | |
458 | return; | |
459 | } | |
460 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) | |
461 | tmp &= ~DC_BALANCE_RESET_VLV; | |
462 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
463 | ||
464 | } | |
465 | ||
466 | static void g4x_undo_pipe_scramble_reset(struct drm_i915_private *dev_priv, | |
467 | enum pipe pipe) | |
468 | { | |
469 | uint32_t tmp = I915_READ(PORT_DFT2_G4X); | |
470 | ||
471 | if (pipe == PIPE_A) | |
472 | tmp &= ~PIPE_A_SCRAMBLE_RESET; | |
473 | else | |
474 | tmp &= ~PIPE_B_SCRAMBLE_RESET; | |
475 | I915_WRITE(PORT_DFT2_G4X, tmp); | |
476 | ||
477 | if (!(tmp & PIPE_SCRAMBLE_RESET_MASK)) { | |
478 | I915_WRITE(PORT_DFT_I9XX, | |
479 | I915_READ(PORT_DFT_I9XX) & ~DC_BALANCE_RESET); | |
480 | } | |
481 | } | |
482 | ||
483 | static int ilk_pipe_crc_ctl_reg(enum intel_pipe_crc_source *source, | |
484 | uint32_t *val) | |
485 | { | |
486 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) | |
487 | *source = INTEL_PIPE_CRC_SOURCE_PIPE; | |
488 | ||
489 | switch (*source) { | |
490 | case INTEL_PIPE_CRC_SOURCE_PLANE1: | |
491 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_ILK; | |
492 | break; | |
493 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
494 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_ILK; | |
495 | break; | |
496 | case INTEL_PIPE_CRC_SOURCE_PIPE: | |
497 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PIPE_ILK; | |
498 | break; | |
499 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
500 | *val = 0; | |
501 | break; | |
502 | default: | |
503 | return -EINVAL; | |
504 | } | |
505 | ||
506 | return 0; | |
507 | } | |
508 | ||
509 | static void hsw_trans_edp_pipe_A_crc_wa(struct drm_i915_private *dev_priv, | |
510 | bool enable) | |
511 | { | |
512 | struct drm_device *dev = &dev_priv->drm; | |
513 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, PIPE_A); | |
514 | struct intel_crtc_state *pipe_config; | |
515 | struct drm_atomic_state *state; | |
aab9094b | 516 | struct drm_modeset_acquire_ctx ctx; |
731035fe TV |
517 | int ret = 0; |
518 | ||
aab9094b ML |
519 | drm_modeset_acquire_init(&ctx, 0); |
520 | ||
731035fe TV |
521 | state = drm_atomic_state_alloc(dev); |
522 | if (!state) { | |
523 | ret = -ENOMEM; | |
1e5a15d6 | 524 | goto unlock; |
731035fe TV |
525 | } |
526 | ||
aab9094b ML |
527 | state->acquire_ctx = &ctx; |
528 | ||
529 | retry: | |
731035fe TV |
530 | pipe_config = intel_atomic_get_crtc_state(state, crtc); |
531 | if (IS_ERR(pipe_config)) { | |
532 | ret = PTR_ERR(pipe_config); | |
1e5a15d6 | 533 | goto put_state; |
731035fe TV |
534 | } |
535 | ||
536 | pipe_config->pch_pfit.force_thru = enable; | |
537 | if (pipe_config->cpu_transcoder == TRANSCODER_EDP && | |
538 | pipe_config->pch_pfit.enabled != enable) | |
539 | pipe_config->base.connectors_changed = true; | |
540 | ||
541 | ret = drm_atomic_commit(state); | |
1e5a15d6 ACO |
542 | |
543 | put_state: | |
aab9094b ML |
544 | if (ret == -EDEADLK) { |
545 | drm_atomic_state_clear(state); | |
546 | drm_modeset_backoff(&ctx); | |
547 | goto retry; | |
548 | } | |
549 | ||
1e5a15d6 ACO |
550 | drm_atomic_state_put(state); |
551 | unlock: | |
731035fe | 552 | WARN(ret, "Toggling workaround to %i returns %i\n", enable, ret); |
aab9094b ML |
553 | drm_modeset_drop_locks(&ctx); |
554 | drm_modeset_acquire_fini(&ctx); | |
731035fe TV |
555 | } |
556 | ||
557 | static int ivb_pipe_crc_ctl_reg(struct drm_i915_private *dev_priv, | |
558 | enum pipe pipe, | |
559 | enum intel_pipe_crc_source *source, | |
560 | uint32_t *val) | |
561 | { | |
562 | if (*source == INTEL_PIPE_CRC_SOURCE_AUTO) | |
563 | *source = INTEL_PIPE_CRC_SOURCE_PF; | |
564 | ||
565 | switch (*source) { | |
566 | case INTEL_PIPE_CRC_SOURCE_PLANE1: | |
567 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PRIMARY_IVB; | |
568 | break; | |
569 | case INTEL_PIPE_CRC_SOURCE_PLANE2: | |
570 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_SPRITE_IVB; | |
571 | break; | |
572 | case INTEL_PIPE_CRC_SOURCE_PF: | |
573 | if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
574 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, true); | |
575 | ||
576 | *val = PIPE_CRC_ENABLE | PIPE_CRC_SOURCE_PF_IVB; | |
577 | break; | |
578 | case INTEL_PIPE_CRC_SOURCE_NONE: | |
579 | *val = 0; | |
580 | break; | |
581 | default: | |
582 | return -EINVAL; | |
583 | } | |
584 | ||
585 | return 0; | |
586 | } | |
587 | ||
8c6b709d TV |
588 | static int get_new_crc_ctl_reg(struct drm_i915_private *dev_priv, |
589 | enum pipe pipe, | |
590 | enum intel_pipe_crc_source *source, u32 *val) | |
591 | { | |
592 | if (IS_GEN2(dev_priv)) | |
593 | return i8xx_pipe_crc_ctl_reg(source, val); | |
594 | else if (INTEL_GEN(dev_priv) < 5) | |
595 | return i9xx_pipe_crc_ctl_reg(dev_priv, pipe, source, val); | |
596 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
597 | return vlv_pipe_crc_ctl_reg(dev_priv, pipe, source, val); | |
598 | else if (IS_GEN5(dev_priv) || IS_GEN6(dev_priv)) | |
599 | return ilk_pipe_crc_ctl_reg(source, val); | |
600 | else | |
601 | return ivb_pipe_crc_ctl_reg(dev_priv, pipe, source, val); | |
602 | } | |
603 | ||
731035fe TV |
604 | static int pipe_crc_set_source(struct drm_i915_private *dev_priv, |
605 | enum pipe pipe, | |
606 | enum intel_pipe_crc_source source) | |
607 | { | |
608 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
609 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, pipe); | |
610 | enum intel_display_power_domain power_domain; | |
611 | u32 val = 0; /* shut up gcc */ | |
612 | int ret; | |
613 | ||
614 | if (pipe_crc->source == source) | |
615 | return 0; | |
616 | ||
617 | /* forbid changing the source without going back to 'none' */ | |
618 | if (pipe_crc->source && source) | |
619 | return -EINVAL; | |
620 | ||
621 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
622 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
623 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
624 | return -EIO; | |
625 | } | |
626 | ||
8c6b709d | 627 | ret = get_new_crc_ctl_reg(dev_priv, pipe, &source, &val); |
731035fe TV |
628 | if (ret != 0) |
629 | goto out; | |
630 | ||
631 | /* none -> real source transition */ | |
632 | if (source) { | |
633 | struct intel_pipe_crc_entry *entries; | |
634 | ||
635 | DRM_DEBUG_DRIVER("collecting CRCs for pipe %c, %s\n", | |
636 | pipe_name(pipe), pipe_crc_source_name(source)); | |
637 | ||
638 | entries = kcalloc(INTEL_PIPE_CRC_ENTRIES_NR, | |
639 | sizeof(pipe_crc->entries[0]), | |
640 | GFP_KERNEL); | |
641 | if (!entries) { | |
642 | ret = -ENOMEM; | |
643 | goto out; | |
644 | } | |
645 | ||
646 | /* | |
647 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
648 | * enabled and disabled dynamically based on package C states, | |
649 | * user space can't make reliable use of the CRCs, so let's just | |
650 | * completely disable it. | |
651 | */ | |
652 | hsw_disable_ips(crtc); | |
653 | ||
654 | spin_lock_irq(&pipe_crc->lock); | |
655 | kfree(pipe_crc->entries); | |
656 | pipe_crc->entries = entries; | |
657 | pipe_crc->head = 0; | |
658 | pipe_crc->tail = 0; | |
659 | spin_unlock_irq(&pipe_crc->lock); | |
660 | } | |
661 | ||
662 | pipe_crc->source = source; | |
663 | ||
664 | I915_WRITE(PIPE_CRC_CTL(pipe), val); | |
665 | POSTING_READ(PIPE_CRC_CTL(pipe)); | |
666 | ||
667 | /* real source -> none transition */ | |
8c6b709d | 668 | if (!source) { |
731035fe TV |
669 | struct intel_pipe_crc_entry *entries; |
670 | struct intel_crtc *crtc = intel_get_crtc_for_pipe(dev_priv, | |
671 | pipe); | |
672 | ||
673 | DRM_DEBUG_DRIVER("stopping CRCs for pipe %c\n", | |
674 | pipe_name(pipe)); | |
675 | ||
676 | drm_modeset_lock(&crtc->base.mutex, NULL); | |
677 | if (crtc->base.state->active) | |
678 | intel_wait_for_vblank(dev_priv, pipe); | |
679 | drm_modeset_unlock(&crtc->base.mutex); | |
680 | ||
681 | spin_lock_irq(&pipe_crc->lock); | |
682 | entries = pipe_crc->entries; | |
683 | pipe_crc->entries = NULL; | |
684 | pipe_crc->head = 0; | |
685 | pipe_crc->tail = 0; | |
686 | spin_unlock_irq(&pipe_crc->lock); | |
687 | ||
688 | kfree(entries); | |
689 | ||
690 | if (IS_G4X(dev_priv)) | |
691 | g4x_undo_pipe_scramble_reset(dev_priv, pipe); | |
692 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
693 | vlv_undo_pipe_scramble_reset(dev_priv, pipe); | |
694 | else if (IS_HASWELL(dev_priv) && pipe == PIPE_A) | |
695 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
696 | ||
697 | hsw_enable_ips(crtc); | |
698 | } | |
699 | ||
700 | ret = 0; | |
701 | ||
702 | out: | |
703 | intel_display_power_put(dev_priv, power_domain); | |
704 | ||
705 | return ret; | |
706 | } | |
707 | ||
708 | /* | |
709 | * Parse pipe CRC command strings: | |
710 | * command: wsp* object wsp+ name wsp+ source wsp* | |
711 | * object: 'pipe' | |
712 | * name: (A | B | C) | |
713 | * source: (none | plane1 | plane2 | pf) | |
714 | * wsp: (#0x20 | #0x9 | #0xA)+ | |
715 | * | |
716 | * eg.: | |
717 | * "pipe A plane1" -> Start CRC computations on plane1 of pipe A | |
718 | * "pipe A none" -> Stop CRC | |
719 | */ | |
720 | static int display_crc_ctl_tokenize(char *buf, char *words[], int max_words) | |
721 | { | |
722 | int n_words = 0; | |
723 | ||
724 | while (*buf) { | |
725 | char *end; | |
726 | ||
727 | /* skip leading white space */ | |
728 | buf = skip_spaces(buf); | |
729 | if (!*buf) | |
730 | break; /* end of buffer */ | |
731 | ||
732 | /* find end of word */ | |
733 | for (end = buf; *end && !isspace(*end); end++) | |
734 | ; | |
735 | ||
736 | if (n_words == max_words) { | |
737 | DRM_DEBUG_DRIVER("too many words, allowed <= %d\n", | |
738 | max_words); | |
739 | return -EINVAL; /* ran out of words[] before bytes */ | |
740 | } | |
741 | ||
742 | if (*end) | |
743 | *end++ = '\0'; | |
744 | words[n_words++] = buf; | |
745 | buf = end; | |
746 | } | |
747 | ||
748 | return n_words; | |
749 | } | |
750 | ||
751 | enum intel_pipe_crc_object { | |
752 | PIPE_CRC_OBJECT_PIPE, | |
753 | }; | |
754 | ||
755 | static const char * const pipe_crc_objects[] = { | |
756 | "pipe", | |
757 | }; | |
758 | ||
759 | static int | |
760 | display_crc_ctl_parse_object(const char *buf, enum intel_pipe_crc_object *o) | |
761 | { | |
762 | int i; | |
763 | ||
764 | for (i = 0; i < ARRAY_SIZE(pipe_crc_objects); i++) | |
765 | if (!strcmp(buf, pipe_crc_objects[i])) { | |
766 | *o = i; | |
767 | return 0; | |
768 | } | |
769 | ||
770 | return -EINVAL; | |
771 | } | |
772 | ||
773 | static int display_crc_ctl_parse_pipe(const char *buf, enum pipe *pipe) | |
774 | { | |
775 | const char name = buf[0]; | |
776 | ||
777 | if (name < 'A' || name >= pipe_name(I915_MAX_PIPES)) | |
778 | return -EINVAL; | |
779 | ||
780 | *pipe = name - 'A'; | |
781 | ||
782 | return 0; | |
783 | } | |
784 | ||
785 | static int | |
786 | display_crc_ctl_parse_source(const char *buf, enum intel_pipe_crc_source *s) | |
787 | { | |
788 | int i; | |
789 | ||
8c6b709d TV |
790 | if (!buf) { |
791 | *s = INTEL_PIPE_CRC_SOURCE_NONE; | |
792 | return 0; | |
793 | } | |
794 | ||
731035fe TV |
795 | for (i = 0; i < ARRAY_SIZE(pipe_crc_sources); i++) |
796 | if (!strcmp(buf, pipe_crc_sources[i])) { | |
797 | *s = i; | |
798 | return 0; | |
799 | } | |
800 | ||
801 | return -EINVAL; | |
802 | } | |
803 | ||
804 | static int display_crc_ctl_parse(struct drm_i915_private *dev_priv, | |
805 | char *buf, size_t len) | |
806 | { | |
807 | #define N_WORDS 3 | |
808 | int n_words; | |
809 | char *words[N_WORDS]; | |
810 | enum pipe pipe; | |
811 | enum intel_pipe_crc_object object; | |
812 | enum intel_pipe_crc_source source; | |
813 | ||
814 | n_words = display_crc_ctl_tokenize(buf, words, N_WORDS); | |
815 | if (n_words != N_WORDS) { | |
816 | DRM_DEBUG_DRIVER("tokenize failed, a command is %d words\n", | |
817 | N_WORDS); | |
818 | return -EINVAL; | |
819 | } | |
820 | ||
821 | if (display_crc_ctl_parse_object(words[0], &object) < 0) { | |
822 | DRM_DEBUG_DRIVER("unknown object %s\n", words[0]); | |
823 | return -EINVAL; | |
824 | } | |
825 | ||
826 | if (display_crc_ctl_parse_pipe(words[1], &pipe) < 0) { | |
827 | DRM_DEBUG_DRIVER("unknown pipe %s\n", words[1]); | |
828 | return -EINVAL; | |
829 | } | |
830 | ||
831 | if (display_crc_ctl_parse_source(words[2], &source) < 0) { | |
832 | DRM_DEBUG_DRIVER("unknown source %s\n", words[2]); | |
833 | return -EINVAL; | |
834 | } | |
835 | ||
836 | return pipe_crc_set_source(dev_priv, pipe, source); | |
837 | } | |
838 | ||
839 | static ssize_t display_crc_ctl_write(struct file *file, const char __user *ubuf, | |
840 | size_t len, loff_t *offp) | |
841 | { | |
842 | struct seq_file *m = file->private_data; | |
843 | struct drm_i915_private *dev_priv = m->private; | |
844 | char *tmpbuf; | |
845 | int ret; | |
846 | ||
847 | if (len == 0) | |
848 | return 0; | |
849 | ||
850 | if (len > PAGE_SIZE - 1) { | |
851 | DRM_DEBUG_DRIVER("expected <%lu bytes into pipe crc control\n", | |
852 | PAGE_SIZE); | |
853 | return -E2BIG; | |
854 | } | |
855 | ||
261aeba8 GT |
856 | tmpbuf = memdup_user_nul(ubuf, len); |
857 | if (IS_ERR(tmpbuf)) | |
858 | return PTR_ERR(tmpbuf); | |
731035fe TV |
859 | |
860 | ret = display_crc_ctl_parse(dev_priv, tmpbuf, len); | |
861 | ||
731035fe TV |
862 | kfree(tmpbuf); |
863 | if (ret < 0) | |
864 | return ret; | |
865 | ||
866 | *offp += len; | |
867 | return len; | |
868 | } | |
869 | ||
870 | const struct file_operations i915_display_crc_ctl_fops = { | |
871 | .owner = THIS_MODULE, | |
872 | .open = display_crc_ctl_open, | |
873 | .read = seq_read, | |
874 | .llseek = seq_lseek, | |
875 | .release = single_release, | |
876 | .write = display_crc_ctl_write | |
877 | }; | |
878 | ||
879 | void intel_display_crc_init(struct drm_i915_private *dev_priv) | |
880 | { | |
881 | enum pipe pipe; | |
882 | ||
883 | for_each_pipe(dev_priv, pipe) { | |
884 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[pipe]; | |
885 | ||
886 | pipe_crc->opened = false; | |
887 | spin_lock_init(&pipe_crc->lock); | |
888 | init_waitqueue_head(&pipe_crc->wq); | |
889 | } | |
890 | } | |
891 | ||
892 | int intel_pipe_crc_create(struct drm_minor *minor) | |
893 | { | |
b05eeb0f NT |
894 | struct drm_i915_private *dev_priv = to_i915(minor->dev); |
895 | struct dentry *ent; | |
731035fe TV |
896 | int i; |
897 | ||
898 | for (i = 0; i < ARRAY_SIZE(i915_pipe_crc_data); i++) { | |
b05eeb0f | 899 | struct pipe_crc_info *info = &i915_pipe_crc_data[i]; |
731035fe | 900 | |
b05eeb0f NT |
901 | info->dev_priv = dev_priv; |
902 | ent = debugfs_create_file(info->name, S_IRUGO, | |
903 | minor->debugfs_root, info, | |
904 | &i915_pipe_crc_fops); | |
905 | if (!ent) | |
906 | return -ENOMEM; | |
731035fe | 907 | } |
b05eeb0f NT |
908 | |
909 | return 0; | |
731035fe | 910 | } |
8c6b709d TV |
911 | |
912 | int intel_crtc_set_crc_source(struct drm_crtc *crtc, const char *source_name, | |
913 | size_t *values_cnt) | |
914 | { | |
915 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; | |
916 | struct intel_pipe_crc *pipe_crc = &dev_priv->pipe_crc[crtc->index]; | |
917 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
918 | enum intel_display_power_domain power_domain; | |
919 | enum intel_pipe_crc_source source; | |
920 | u32 val = 0; /* shut up gcc */ | |
921 | int ret = 0; | |
922 | ||
923 | if (display_crc_ctl_parse_source(source_name, &source) < 0) { | |
924 | DRM_DEBUG_DRIVER("unknown source %s\n", source_name); | |
925 | return -EINVAL; | |
926 | } | |
927 | ||
928 | power_domain = POWER_DOMAIN_PIPE(crtc->index); | |
929 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) { | |
930 | DRM_DEBUG_KMS("Trying to capture CRC while pipe is off\n"); | |
931 | return -EIO; | |
932 | } | |
933 | ||
934 | ret = get_new_crc_ctl_reg(dev_priv, crtc->index, &source, &val); | |
935 | if (ret != 0) | |
936 | goto out; | |
937 | ||
938 | if (source) { | |
939 | /* | |
940 | * When IPS gets enabled, the pipe CRC changes. Since IPS gets | |
941 | * enabled and disabled dynamically based on package C states, | |
942 | * user space can't make reliable use of the CRCs, so let's just | |
943 | * completely disable it. | |
944 | */ | |
945 | hsw_disable_ips(intel_crtc); | |
946 | } | |
947 | ||
948 | I915_WRITE(PIPE_CRC_CTL(crtc->index), val); | |
949 | POSTING_READ(PIPE_CRC_CTL(crtc->index)); | |
950 | ||
951 | if (!source) { | |
952 | if (IS_G4X(dev_priv)) | |
953 | g4x_undo_pipe_scramble_reset(dev_priv, crtc->index); | |
954 | else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) | |
955 | vlv_undo_pipe_scramble_reset(dev_priv, crtc->index); | |
956 | else if (IS_HASWELL(dev_priv) && crtc->index == PIPE_A) | |
957 | hsw_trans_edp_pipe_A_crc_wa(dev_priv, false); | |
958 | ||
959 | hsw_enable_ips(intel_crtc); | |
960 | } | |
961 | ||
962 | pipe_crc->skipped = 0; | |
963 | *values_cnt = 5; | |
964 | ||
965 | out: | |
966 | intel_display_power_put(dev_priv, power_domain); | |
967 | ||
968 | return ret; | |
969 | } |