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[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
1fa61106 46static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 47{
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 u32 fbc_ctl;
50
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
54 return;
55
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
58
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
62 return;
63 }
64
65 DRM_DEBUG_KMS("disabled FBC\n");
66}
67
1fa61106 68static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 69{
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
76 int cfb_pitch;
77 int plane, i;
78 u32 fbc_ctl, fbc_ctl2;
79
5c3fe8b0 80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
83
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
87
88 /* Clear old tags */
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
91
92 /* Set it up... */
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
94 fbc_ctl2 |= plane;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
97
98 /* enable it... */
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
100 if (IS_I945GM(dev))
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
106
84f44ce7
VS		 107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 109}
110
1fa61106 111static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 112{
113 struct drm_i915_private *dev_priv = dev->dev_private;
114
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
116}
117
1fa61106 118static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 119{
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
128 u32 dpfc_ctl;
129
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
133
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
138
139 /* enable it... */
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
141
84f44ce7 142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 143}
144
1fa61106 145static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 146{
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u32 dpfc_ctl;
149
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
155
156 DRM_DEBUG_KMS("disabled FBC\n");
157 }
158}
159
1fa61106 160static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 161{
162 struct drm_i915_private *dev_priv = dev->dev_private;
163
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
165}
166
167static void sandybridge_blit_fbc_update(struct drm_device *dev)
168{
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 blt_ecoskpd;
171
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
185}
186
1fa61106 187static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 188{
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
197 u32 dpfc_ctl;
198
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
206
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 212 /* enable it... */
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
214
215 if (IS_GEN6(dev)) {
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
220 }
221
84f44ce7 222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 223}
224
1fa61106 225static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 226{
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 dpfc_ctl;
229
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
235
b74ea102 236 if (IS_IVYBRIDGE(dev))
7dd23ba0 237 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
241
d89f2071 242 if (IS_HASWELL(dev))
7dd23ba0 243 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
247
85208be0
ED		 248 DRM_DEBUG_KMS("disabled FBC\n");
249 }
250}
251
1fa61106 252static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
257}
258
abe959c7
RV		 259static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
260{
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
267
f343c5f6 268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 269
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
273
891348b2 274 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 277 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 281 } else {
7dd23ba0 282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
891348b2 289 }
b74ea102 290
abe959c7
RV		 291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
294
295 sandybridge_blit_fbc_update(dev);
296
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
298}
299
85208be0
ED		 300bool intel_fbc_enabled(struct drm_device *dev)
301{
302 struct drm_i915_private *dev_priv = dev->dev_private;
303
304 if (!dev_priv->display.fbc_enabled)
305 return false;
306
307 return dev_priv->display.fbc_enabled(dev);
308}
309
310static void intel_fbc_work_fn(struct work_struct *__work)
311{
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317
318 mutex_lock(&dev->struct_mutex);
5c3fe8b0 319 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 320 /* Double check that we haven't switched fb without cancelling
321 * the prior work.
322 */
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
325 work->interval);
326
5c3fe8b0
BW		 327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 330 }
331
5c3fe8b0 332 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 333 }
334 mutex_unlock(&dev->struct_mutex);
335
336 kfree(work);
337}
338
339static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
340{
5c3fe8b0 341 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 342 return;
343
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
345
346 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 348 * entirely asynchronously.
349 */
5c3fe8b0 350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 351 /* tasklet was killed before being run, clean up */
5c3fe8b0 352 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 353
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
357 * necessary to run.
358 */
5c3fe8b0 359 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 360}
361
b63fb44c 362static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 363{
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367
368 if (!dev_priv->display.enable_fbc)
369 return;
370
371 intel_cancel_fbc_work(dev_priv);
372
b14c5679 373 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 374 if (work == NULL) {
6cdcb5e7 375 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 376 dev_priv->display.enable_fbc(crtc, interval);
377 return;
378 }
379
380 work->crtc = crtc;
381 work->fb = crtc->fb;
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
384
5c3fe8b0 385 dev_priv->fbc.fbc_work = work;
85208be0 386
85208be0
ED		 387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
392 *
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
7457d617
DL		 397 *
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 399 */
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
401}
402
403void intel_disable_fbc(struct drm_device *dev)
404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406
407 intel_cancel_fbc_work(dev_priv);
408
409 if (!dev_priv->display.disable_fbc)
410 return;
411
412 dev_priv->display.disable_fbc(dev);
5c3fe8b0 413 dev_priv->fbc.plane = -1;
85208be0
ED		 414}
415
29ebf90f
CW		 416static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
418{
419 if (dev_priv->fbc.no_fbc_reason == reason)
420 return false;
421
422 dev_priv->fbc.no_fbc_reason = reason;
423 return true;
424}
425
85208be0
ED		 426/**
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
429 *
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
435 * - no dual wide
f85da868 436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 437 *
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
441 * stolen memory.
442 *
443 * We need to enable/disable FBC on a global basis.
444 */
445void intel_update_fbc(struct drm_device *dev)
446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
ef644fda 453 const struct drm_display_mode *adjusted_mode;
37327abd 454 unsigned int max_width, max_height;
85208be0 455
29ebf90f
CW		 456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 458 return;
29ebf90f 459 }
85208be0 460
29ebf90f
CW		 461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 464 return;
29ebf90f 465 }
85208be0
ED		 466
467 /*
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
475 */
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 477 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 478 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 479 if (crtc) {
29ebf90f
CW		 480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 482 goto out_disable;
483 }
484 crtc = tmp_crtc;
485 }
486 }
487
488 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 491 goto out_disable;
492 }
493
494 intel_crtc = to_intel_crtc(crtc);
495 fb = crtc->fb;
496 intel_fb = to_intel_framebuffer(fb);
497 obj = intel_fb->obj;
ef644fda 498 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 499
8a5729a3
DL		 500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 504 goto out_disable;
85208be0 505 }
8a5729a3 506 if (!i915_enable_fbc) {
29ebf90f
CW		 507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 509 goto out_disable;
510 }
ef644fda
VS		 511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
515 "disabling\n");
85208be0
ED		 516 goto out_disable;
517 }
f85da868
PZ		 518
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 520 max_width = 4096;
521 max_height = 2048;
f85da868 522 } else {
37327abd
VS		 523 max_width = 2048;
524 max_height = 1536;
f85da868 525 }
37327abd
VS		 526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
891348b2
RV		 532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 536 goto out_disable;
537 }
538
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
541 */
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 546 goto out_disable;
547 }
548
549 /* If the kernel debugger is active, always disable compression */
550 if (in_dbg_master())
551 goto out_disable;
552
11be49eb 553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 556 goto out_disable;
557 }
558
85208be0
ED		 559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
563 */
5c3fe8b0
BW		 564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
85208be0
ED		 567 return;
568
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
575 *
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
584 * callback.
585 *
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
592 */
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
595 }
596
597 intel_enable_fbc(crtc, 500);
29ebf90f 598 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 599 return;
600
601out_disable:
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
606 }
11be49eb 607 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 608}
609
c921aba8
DV		 610static void i915_pineview_get_mem_freq(struct drm_device *dev)
611{
612 drm_i915_private_t *dev_priv = dev->dev_private;
613 u32 tmp;
614
615 tmp = I915_READ(CLKCFG);
616
617 switch (tmp & CLKCFG_FSB_MASK) {
618 case CLKCFG_FSB_533:
619 dev_priv->fsb_freq = 533; /* 133*4 */
620 break;
621 case CLKCFG_FSB_800:
622 dev_priv->fsb_freq = 800; /* 200*4 */
623 break;
624 case CLKCFG_FSB_667:
625 dev_priv->fsb_freq = 667; /* 167*4 */
626 break;
627 case CLKCFG_FSB_400:
628 dev_priv->fsb_freq = 400; /* 100*4 */
629 break;
630 }
631
632 switch (tmp & CLKCFG_MEM_MASK) {
633 case CLKCFG_MEM_533:
634 dev_priv->mem_freq = 533;
635 break;
636 case CLKCFG_MEM_667:
637 dev_priv->mem_freq = 667;
638 break;
639 case CLKCFG_MEM_800:
640 dev_priv->mem_freq = 800;
641 break;
642 }
643
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
647}
648
649static void i915_ironlake_get_mem_freq(struct drm_device *dev)
650{
651 drm_i915_private_t *dev_priv = dev->dev_private;
652 u16 ddrpll, csipll;
653
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
656
657 switch (ddrpll & 0xff) {
658 case 0xc:
659 dev_priv->mem_freq = 800;
660 break;
661 case 0x10:
662 dev_priv->mem_freq = 1066;
663 break;
664 case 0x14:
665 dev_priv->mem_freq = 1333;
666 break;
667 case 0x18:
668 dev_priv->mem_freq = 1600;
669 break;
670 default:
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
672 ddrpll & 0xff);
673 dev_priv->mem_freq = 0;
674 break;
675 }
676
20e4d407 677 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 678
679 switch (csipll & 0x3ff) {
680 case 0x00c:
681 dev_priv->fsb_freq = 3200;
682 break;
683 case 0x00e:
684 dev_priv->fsb_freq = 3733;
685 break;
686 case 0x010:
687 dev_priv->fsb_freq = 4266;
688 break;
689 case 0x012:
690 dev_priv->fsb_freq = 4800;
691 break;
692 case 0x014:
693 dev_priv->fsb_freq = 5333;
694 break;
695 case 0x016:
696 dev_priv->fsb_freq = 5866;
697 break;
698 case 0x018:
699 dev_priv->fsb_freq = 6400;
700 break;
701 default:
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
703 csipll & 0x3ff);
704 dev_priv->fsb_freq = 0;
705 break;
706 }
707
708 if (dev_priv->fsb_freq == 3200) {
20e4d407 709 dev_priv->ips.c_m = 0;
c921aba8 710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 711 dev_priv->ips.c_m = 1;
c921aba8 712 } else {
20e4d407 713 dev_priv->ips.c_m = 2;
c921aba8
DV		 714 }
715}
716
b445e3b0
ED		 717static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
723
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
729
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
735
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
741
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
747
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
753};
754
63c62275 755static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 756 int is_ddr3,
757 int fsb,
758 int mem)
759{
760 const struct cxsr_latency *latency;
761 int i;
762
763 if (fsb == 0 || mem == 0)
764 return NULL;
765
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
771 return latency;
772 }
773
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
775
776 return NULL;
777}
778
1fa61106 779static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 780{
781 struct drm_i915_private *dev_priv = dev->dev_private;
782
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
785}
786
787/*
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
790 * - chipset
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
797 *
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
800 */
801static const int latency_ns = 5000;
802
1fa61106 803static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
807 int size;
808
809 size = dsparb & 0x7f;
810 if (plane)
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817}
818
1fa61106 819static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x1ff;
826 if (plane)
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834}
835
1fa61106 836static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 837{
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
844
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
846 plane ? "B" : "A",
847 size);
848
849 return size;
850}
851
1fa61106 852static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 853{
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
856 int size;
857
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
860
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
863
864 return size;
865}
866
867/* Pineview has different values for various configs */
868static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874};
875static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
877 PINEVIEW_MAX_WM,
878 PINEVIEW_DFT_HPLLOFF_WM,
879 PINEVIEW_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE
881};
882static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
888};
889static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
895};
896static const struct intel_watermark_params g4x_wm_info = {
897 G4X_FIFO_SIZE,
898 G4X_MAX_WM,
899 G4X_MAX_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902};
903static const struct intel_watermark_params g4x_cursor_wm_info = {
904 I965_CURSOR_FIFO,
905 I965_CURSOR_MAX_WM,
906 I965_CURSOR_DFT_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909};
910static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
912 VALLEYVIEW_MAX_WM,
913 VALLEYVIEW_MAX_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916};
917static const struct intel_watermark_params valleyview_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 VALLEYVIEW_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 G4X_FIFO_LINE_SIZE,
923};
924static const struct intel_watermark_params i965_cursor_wm_info = {
925 I965_CURSOR_FIFO,
926 I965_CURSOR_MAX_WM,
927 I965_CURSOR_DFT_WM,
928 2,
929 I915_FIFO_LINE_SIZE,
930};
931static const struct intel_watermark_params i945_wm_info = {
932 I945_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937};
938static const struct intel_watermark_params i915_wm_info = {
939 I915_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I915_FIFO_LINE_SIZE
944};
945static const struct intel_watermark_params i855_wm_info = {
946 I855GM_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951};
952static const struct intel_watermark_params i830_wm_info = {
953 I830_FIFO_SIZE,
954 I915_MAX_WM,
955 1,
956 2,
957 I830_FIFO_LINE_SIZE
958};
959
960static const struct intel_watermark_params ironlake_display_wm_info = {
961 ILK_DISPLAY_FIFO,
962 ILK_DISPLAY_MAXWM,
963 ILK_DISPLAY_DFTWM,
964 2,
965 ILK_FIFO_LINE_SIZE
966};
967static const struct intel_watermark_params ironlake_cursor_wm_info = {
968 ILK_CURSOR_FIFO,
969 ILK_CURSOR_MAXWM,
970 ILK_CURSOR_DFTWM,
971 2,
972 ILK_FIFO_LINE_SIZE
973};
974static const struct intel_watermark_params ironlake_display_srwm_info = {
975 ILK_DISPLAY_SR_FIFO,
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
978 2,
979 ILK_FIFO_LINE_SIZE
980};
981static const struct intel_watermark_params ironlake_cursor_srwm_info = {
982 ILK_CURSOR_SR_FIFO,
983 ILK_CURSOR_MAX_SRWM,
984 ILK_CURSOR_DFT_SRWM,
985 2,
986 ILK_FIFO_LINE_SIZE
987};
988
989static const struct intel_watermark_params sandybridge_display_wm_info = {
990 SNB_DISPLAY_FIFO,
991 SNB_DISPLAY_MAXWM,
992 SNB_DISPLAY_DFTWM,
993 2,
994 SNB_FIFO_LINE_SIZE
995};
996static const struct intel_watermark_params sandybridge_cursor_wm_info = {
997 SNB_CURSOR_FIFO,
998 SNB_CURSOR_MAXWM,
999 SNB_CURSOR_DFTWM,
1000 2,
1001 SNB_FIFO_LINE_SIZE
1002};
1003static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1007 2,
1008 SNB_FIFO_LINE_SIZE
1009};
1010static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011 SNB_CURSOR_SR_FIFO,
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1014 2,
1015 SNB_FIFO_LINE_SIZE
1016};
1017
1018
1019/**
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1025 *
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1030 *
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1036 */
1037static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1039 int fifo_size,
1040 int pixel_size,
1041 unsigned long latency_ns)
1042{
1043 long entries_required, wm_size;
1044
1045 /*
1046 * Note: we need to make sure we don't overflow for various clock &
1047 * latency values.
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1050 */
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052 1000;
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1064 if (wm_size <= 0)
1065 wm_size = wm->default_wm;
1066 return wm_size;
1067}
1068
1069static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070{
1071 struct drm_crtc *crtc, *enabled = NULL;
1072
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1074 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1075 if (enabled)
1076 return NULL;
1077 enabled = crtc;
1078 }
1079 }
1080
1081 return enabled;
1082}
1083
46ba614c 1084static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1085{
46ba614c 1086 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1090 u32 reg;
1091 unsigned long wm;
1092
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1095 if (!latency) {
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1098 return;
1099 }
1100
1101 crtc = single_enabled_crtc(dev);
1102 if (crtc) {
241bfc38 1103 const struct drm_display_mode *adjusted_mode;
b445e3b0 1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1105 int clock;
1106
1107 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1108 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1109
1110 /* Display SR */
1111 wm = intel_calculate_wm(clock, &pineview_display_wm,
1112 pineview_display_wm.fifo_size,
1113 pixel_size, latency->display_sr);
1114 reg = I915_READ(DSPFW1);
1115 reg &= ~DSPFW_SR_MASK;
1116 reg |= wm << DSPFW_SR_SHIFT;
1117 I915_WRITE(DSPFW1, reg);
1118 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1119
1120 /* cursor SR */
1121 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1122 pineview_display_wm.fifo_size,
1123 pixel_size, latency->cursor_sr);
1124 reg = I915_READ(DSPFW3);
1125 reg &= ~DSPFW_CURSOR_SR_MASK;
1126 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1127 I915_WRITE(DSPFW3, reg);
1128
1129 /* Display HPLL off SR */
1130 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1131 pineview_display_hplloff_wm.fifo_size,
1132 pixel_size, latency->display_hpll_disable);
1133 reg = I915_READ(DSPFW3);
1134 reg &= ~DSPFW_HPLL_SR_MASK;
1135 reg |= wm & DSPFW_HPLL_SR_MASK;
1136 I915_WRITE(DSPFW3, reg);
1137
1138 /* cursor HPLL off SR */
1139 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1140 pineview_display_hplloff_wm.fifo_size,
1141 pixel_size, latency->cursor_hpll_disable);
1142 reg = I915_READ(DSPFW3);
1143 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1144 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1145 I915_WRITE(DSPFW3, reg);
1146 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1147
1148 /* activate cxsr */
1149 I915_WRITE(DSPFW3,
1150 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1151 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1152 } else {
1153 pineview_disable_cxsr(dev);
1154 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1155 }
1156}
1157
1158static bool g4x_compute_wm0(struct drm_device *dev,
1159 int plane,
1160 const struct intel_watermark_params *display,
1161 int display_latency_ns,
1162 const struct intel_watermark_params *cursor,
1163 int cursor_latency_ns,
1164 int *plane_wm,
1165 int *cursor_wm)
1166{
1167 struct drm_crtc *crtc;
4fe8590a 1168 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
4fe8590a 1180 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1181 clock = adjusted_mode->crtc_clock;
4fe8590a 1182 htotal = adjusted_mode->htotal;
37327abd 1183 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1184 pixel_size = crtc->fb->bits_per_pixel / 8;
1185
1186 /* Use the small buffer method to calculate plane watermark */
1187 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1188 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1189 if (tlb_miss > 0)
1190 entries += tlb_miss;
1191 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1192 *plane_wm = entries + display->guard_size;
1193 if (*plane_wm > (int)display->max_wm)
1194 *plane_wm = display->max_wm;
1195
1196 /* Use the large buffer method to calculate cursor watermark */
1197 line_time_us = ((htotal * 1000) / clock);
1198 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1199 entries = line_count * 64 * pixel_size;
1200 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1201 if (tlb_miss > 0)
1202 entries += tlb_miss;
1203 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1204 *cursor_wm = entries + cursor->guard_size;
1205 if (*cursor_wm > (int)cursor->max_wm)
1206 *cursor_wm = (int)cursor->max_wm;
1207
1208 return true;
1209}
1210
1211/*
1212 * Check the wm result.
1213 *
1214 * If any calculated watermark values is larger than the maximum value that
1215 * can be programmed into the associated watermark register, that watermark
1216 * must be disabled.
1217 */
1218static bool g4x_check_srwm(struct drm_device *dev,
1219 int display_wm, int cursor_wm,
1220 const struct intel_watermark_params *display,
1221 const struct intel_watermark_params *cursor)
1222{
1223 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1224 display_wm, cursor_wm);
1225
1226 if (display_wm > display->max_wm) {
1227 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1228 display_wm, display->max_wm);
1229 return false;
1230 }
1231
1232 if (cursor_wm > cursor->max_wm) {
1233 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1234 cursor_wm, cursor->max_wm);
1235 return false;
1236 }
1237
1238 if (!(display_wm || cursor_wm)) {
1239 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1240 return false;
1241 }
1242
1243 return true;
1244}
1245
1246static bool g4x_compute_srwm(struct drm_device *dev,
1247 int plane,
1248 int latency_ns,
1249 const struct intel_watermark_params *display,
1250 const struct intel_watermark_params *cursor,
1251 int *display_wm, int *cursor_wm)
1252{
1253 struct drm_crtc *crtc;
4fe8590a 1254 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1255 int hdisplay, htotal, pixel_size, clock;
1256 unsigned long line_time_us;
1257 int line_count, line_size;
1258 int small, large;
1259 int entries;
1260
1261 if (!latency_ns) {
1262 *display_wm = *cursor_wm = 0;
1263 return false;
1264 }
1265
1266 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1267 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1268 clock = adjusted_mode->crtc_clock;
4fe8590a 1269 htotal = adjusted_mode->htotal;
37327abd 1270 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1271 pixel_size = crtc->fb->bits_per_pixel / 8;
1272
1273 line_time_us = (htotal * 1000) / clock;
1274 line_count = (latency_ns / line_time_us + 1000) / 1000;
1275 line_size = hdisplay * pixel_size;
1276
1277 /* Use the minimum of the small and large buffer method for primary */
1278 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1279 large = line_count * line_size;
1280
1281 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1282 *display_wm = entries + display->guard_size;
1283
1284 /* calculate the self-refresh watermark for display cursor */
1285 entries = line_count * pixel_size * 64;
1286 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1287 *cursor_wm = entries + cursor->guard_size;
1288
1289 return g4x_check_srwm(dev,
1290 *display_wm, *cursor_wm,
1291 display, cursor);
1292}
1293
1294static bool vlv_compute_drain_latency(struct drm_device *dev,
1295 int plane,
1296 int *plane_prec_mult,
1297 int *plane_dl,
1298 int *cursor_prec_mult,
1299 int *cursor_dl)
1300{
1301 struct drm_crtc *crtc;
1302 int clock, pixel_size;
1303 int entries;
1304
1305 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1306 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1307 return false;
1308
241bfc38 1309 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1310 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1311
1312 entries = (clock / 1000) * pixel_size;
1313 *plane_prec_mult = (entries > 256) ?
1314 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1315 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1316 pixel_size);
1317
1318 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1319 *cursor_prec_mult = (entries > 256) ?
1320 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1321 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1322
1323 return true;
1324}
1325
1326/*
1327 * Update drain latency registers of memory arbiter
1328 *
1329 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1330 * to be programmed. Each plane has a drain latency multiplier and a drain
1331 * latency value.
1332 */
1333
1334static void vlv_update_drain_latency(struct drm_device *dev)
1335{
1336 struct drm_i915_private *dev_priv = dev->dev_private;
1337 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1338 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1339 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1340 either 16 or 32 */
1341
1342 /* For plane A, Cursor A */
1343 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1344 &cursor_prec_mult, &cursora_dl)) {
1345 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1346 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1347 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1348 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1349
1350 I915_WRITE(VLV_DDL1, cursora_prec |
1351 (cursora_dl << DDL_CURSORA_SHIFT) |
1352 planea_prec | planea_dl);
1353 }
1354
1355 /* For plane B, Cursor B */
1356 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1357 &cursor_prec_mult, &cursorb_dl)) {
1358 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1359 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1360 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1361 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1362
1363 I915_WRITE(VLV_DDL2, cursorb_prec |
1364 (cursorb_dl << DDL_CURSORB_SHIFT) |
1365 planeb_prec | planeb_dl);
1366 }
1367}
1368
1369#define single_plane_enabled(mask) is_power_of_2(mask)
1370
46ba614c 1371static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1372{
46ba614c 1373 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1374 static const int sr_latency_ns = 12000;
1375 struct drm_i915_private *dev_priv = dev->dev_private;
1376 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1377 int plane_sr, cursor_sr;
af6c4575 1378 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1379 unsigned int enabled = 0;
1380
1381 vlv_update_drain_latency(dev);
1382
51cea1f4 1383 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1384 &valleyview_wm_info, latency_ns,
1385 &valleyview_cursor_wm_info, latency_ns,
1386 &planea_wm, &cursora_wm))
51cea1f4 1387 enabled |= 1 << PIPE_A;
b445e3b0 1388
51cea1f4 1389 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1390 &valleyview_wm_info, latency_ns,
1391 &valleyview_cursor_wm_info, latency_ns,
1392 &planeb_wm, &cursorb_wm))
51cea1f4 1393 enabled |= 1 << PIPE_B;
b445e3b0 1394
b445e3b0
ED		 1395 if (single_plane_enabled(enabled) &&
1396 g4x_compute_srwm(dev, ffs(enabled) - 1,
1397 sr_latency_ns,
1398 &valleyview_wm_info,
1399 &valleyview_cursor_wm_info,
af6c4575
CW		 1400 &plane_sr, &ignore_cursor_sr) &&
1401 g4x_compute_srwm(dev, ffs(enabled) - 1,
1402 2*sr_latency_ns,
1403 &valleyview_wm_info,
1404 &valleyview_cursor_wm_info,
52bd02d8 1405 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1406 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1407 } else {
b445e3b0
ED		 1408 I915_WRITE(FW_BLC_SELF_VLV,
1409 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1410 plane_sr = cursor_sr = 0;
1411 }
b445e3b0
ED		 1412
1413 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1414 planea_wm, cursora_wm,
1415 planeb_wm, cursorb_wm,
1416 plane_sr, cursor_sr);
1417
1418 I915_WRITE(DSPFW1,
1419 (plane_sr << DSPFW_SR_SHIFT) |
1420 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1421 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1422 planea_wm);
1423 I915_WRITE(DSPFW2,
8c919b28 1424 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1425 (cursora_wm << DSPFW_CURSORA_SHIFT));
1426 I915_WRITE(DSPFW3,
8c919b28
CW		 1427 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1428 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1429}
1430
46ba614c 1431static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1432{
46ba614c 1433 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1434 static const int sr_latency_ns = 12000;
1435 struct drm_i915_private *dev_priv = dev->dev_private;
1436 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1437 int plane_sr, cursor_sr;
1438 unsigned int enabled = 0;
1439
51cea1f4 1440 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1441 &g4x_wm_info, latency_ns,
1442 &g4x_cursor_wm_info, latency_ns,
1443 &planea_wm, &cursora_wm))
51cea1f4 1444 enabled |= 1 << PIPE_A;
b445e3b0 1445
51cea1f4 1446 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1447 &g4x_wm_info, latency_ns,
1448 &g4x_cursor_wm_info, latency_ns,
1449 &planeb_wm, &cursorb_wm))
51cea1f4 1450 enabled |= 1 << PIPE_B;
b445e3b0 1451
b445e3b0
ED		 1452 if (single_plane_enabled(enabled) &&
1453 g4x_compute_srwm(dev, ffs(enabled) - 1,
1454 sr_latency_ns,
1455 &g4x_wm_info,
1456 &g4x_cursor_wm_info,
52bd02d8 1457 &plane_sr, &cursor_sr)) {
b445e3b0 1458 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1459 } else {
b445e3b0
ED		 1460 I915_WRITE(FW_BLC_SELF,
1461 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1462 plane_sr = cursor_sr = 0;
1463 }
b445e3b0
ED		 1464
1465 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1466 planea_wm, cursora_wm,
1467 planeb_wm, cursorb_wm,
1468 plane_sr, cursor_sr);
1469
1470 I915_WRITE(DSPFW1,
1471 (plane_sr << DSPFW_SR_SHIFT) |
1472 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1473 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1474 planea_wm);
1475 I915_WRITE(DSPFW2,
8c919b28 1476 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1477 (cursora_wm << DSPFW_CURSORA_SHIFT));
1478 /* HPLL off in SR has some issues on G4x... disable it */
1479 I915_WRITE(DSPFW3,
8c919b28 1480 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1481 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1482}
1483
46ba614c 1484static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1485{
46ba614c 1486 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1487 struct drm_i915_private *dev_priv = dev->dev_private;
1488 struct drm_crtc *crtc;
1489 int srwm = 1;
1490 int cursor_sr = 16;
1491
1492 /* Calc sr entries for one plane configs */
1493 crtc = single_enabled_crtc(dev);
1494 if (crtc) {
1495 /* self-refresh has much higher latency */
1496 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1497 const struct drm_display_mode *adjusted_mode =
1498 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1499 int clock = adjusted_mode->crtc_clock;
4fe8590a 1500 int htotal = adjusted_mode->htotal;
37327abd 1501 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1502 int pixel_size = crtc->fb->bits_per_pixel / 8;
1503 unsigned long line_time_us;
1504 int entries;
1505
1506 line_time_us = ((htotal * 1000) / clock);
1507
1508 /* Use ns/us then divide to preserve precision */
1509 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1510 pixel_size * hdisplay;
1511 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1512 srwm = I965_FIFO_SIZE - entries;
1513 if (srwm < 0)
1514 srwm = 1;
1515 srwm &= 0x1ff;
1516 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1517 entries, srwm);
1518
1519 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1520 pixel_size * 64;
1521 entries = DIV_ROUND_UP(entries,
1522 i965_cursor_wm_info.cacheline_size);
1523 cursor_sr = i965_cursor_wm_info.fifo_size -
1524 (entries + i965_cursor_wm_info.guard_size);
1525
1526 if (cursor_sr > i965_cursor_wm_info.max_wm)
1527 cursor_sr = i965_cursor_wm_info.max_wm;
1528
1529 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1530 "cursor %d\n", srwm, cursor_sr);
1531
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1534 } else {
1535 /* Turn off self refresh if both pipes are enabled */
1536 if (IS_CRESTLINE(dev))
1537 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1538 & ~FW_BLC_SELF_EN);
1539 }
1540
1541 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1542 srwm);
1543
1544 /* 965 has limitations... */
1545 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1546 (8 << 16) | (8 << 8) | (8 << 0));
1547 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1548 /* update cursor SR watermark */
1549 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1550}
1551
46ba614c 1552static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1553{
46ba614c 1554 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1557 uint32_t fwater_lo;
1558 uint32_t fwater_hi;
1559 int cwm, srwm = 1;
1560 int fifo_size;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1563
1564 if (IS_I945GM(dev))
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1568 else
1569 wm_info = &i855_wm_info;
1570
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1573 if (intel_crtc_active(crtc)) {
241bfc38 1574 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1575 int cpp = crtc->fb->bits_per_pixel / 8;
1576 if (IS_GEN2(dev))
1577 cpp = 4;
1578
241bfc38
DL		 1579 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1581 wm_info, fifo_size, cpp,
b445e3b0
ED		 1582 latency_ns);
1583 enabled = crtc;
1584 } else
1585 planea_wm = fifo_size - wm_info->guard_size;
1586
1587 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1588 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1589 if (intel_crtc_active(crtc)) {
241bfc38 1590 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1591 int cpp = crtc->fb->bits_per_pixel / 8;
1592 if (IS_GEN2(dev))
1593 cpp = 4;
1594
241bfc38
DL		 1595 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1596 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1597 wm_info, fifo_size, cpp,
b445e3b0
ED		 1598 latency_ns);
1599 if (enabled == NULL)
1600 enabled = crtc;
1601 else
1602 enabled = NULL;
1603 } else
1604 planeb_wm = fifo_size - wm_info->guard_size;
1605
1606 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1607
1608 /*
1609 * Overlay gets an aggressive default since video jitter is bad.
1610 */
1611 cwm = 2;
1612
1613 /* Play safe and disable self-refresh before adjusting watermarks. */
1614 if (IS_I945G(dev) || IS_I945GM(dev))
1615 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1618
1619 /* Calc sr entries for one plane configs */
1620 if (HAS_FW_BLC(dev) && enabled) {
1621 /* self-refresh has much higher latency */
1622 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1623 const struct drm_display_mode *adjusted_mode =
1624 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1625 int clock = adjusted_mode->crtc_clock;
4fe8590a 1626 int htotal = adjusted_mode->htotal;
37327abd 1627 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1628 int pixel_size = enabled->fb->bits_per_pixel / 8;
1629 unsigned long line_time_us;
1630 int entries;
1631
1632 line_time_us = (htotal * 1000) / clock;
1633
1634 /* Use ns/us then divide to preserve precision */
1635 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1636 pixel_size * hdisplay;
1637 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1638 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1639 srwm = wm_info->fifo_size - entries;
1640 if (srwm < 0)
1641 srwm = 1;
1642
1643 if (IS_I945G(dev) || IS_I945GM(dev))
1644 I915_WRITE(FW_BLC_SELF,
1645 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1646 else if (IS_I915GM(dev))
1647 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1648 }
1649
1650 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1651 planea_wm, planeb_wm, cwm, srwm);
1652
1653 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1654 fwater_hi = (cwm & 0x1f);
1655
1656 /* Set request length to 8 cachelines per fetch */
1657 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1658 fwater_hi = fwater_hi | (1 << 8);
1659
1660 I915_WRITE(FW_BLC, fwater_lo);
1661 I915_WRITE(FW_BLC2, fwater_hi);
1662
1663 if (HAS_FW_BLC(dev)) {
1664 if (enabled) {
1665 if (IS_I945G(dev) || IS_I945GM(dev))
1666 I915_WRITE(FW_BLC_SELF,
1667 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1668 else if (IS_I915GM(dev))
1669 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1670 DRM_DEBUG_KMS("memory self refresh enabled\n");
1671 } else
1672 DRM_DEBUG_KMS("memory self refresh disabled\n");
1673 }
1674}
1675
46ba614c 1676static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1677{
46ba614c 1678 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1679 struct drm_i915_private *dev_priv = dev->dev_private;
1680 struct drm_crtc *crtc;
241bfc38 1681 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1682 uint32_t fwater_lo;
1683 int planea_wm;
1684
1685 crtc = single_enabled_crtc(dev);
1686 if (crtc == NULL)
1687 return;
1688
241bfc38
DL		 1689 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1690 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1691 &i830_wm_info,
b445e3b0 1692 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1693 4, latency_ns);
b445e3b0
ED		 1694 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1695 fwater_lo |= (3<<8) | planea_wm;
1696
1697 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1698
1699 I915_WRITE(FW_BLC, fwater_lo);
1700}
1701
b445e3b0
ED		 1702/*
1703 * Check the wm result.
1704 *
1705 * If any calculated watermark values is larger than the maximum value that
1706 * can be programmed into the associated watermark register, that watermark
1707 * must be disabled.
1708 */
1709static bool ironlake_check_srwm(struct drm_device *dev, int level,
1710 int fbc_wm, int display_wm, int cursor_wm,
1711 const struct intel_watermark_params *display,
1712 const struct intel_watermark_params *cursor)
1713{
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715
1716 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1717 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1718
1719 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1720 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1721 fbc_wm, SNB_FBC_MAX_SRWM, level);
1722
1723 /* fbc has it's own way to disable FBC WM */
1724 I915_WRITE(DISP_ARB_CTL,
1725 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1726 return false;
615aaa5f
VS		 1727 } else if (INTEL_INFO(dev)->gen >= 6) {
1728 /* enable FBC WM (except on ILK, where it must remain off) */
1729 I915_WRITE(DISP_ARB_CTL,
1730 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1731 }
1732
1733 if (display_wm > display->max_wm) {
1734 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1735 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1736 return false;
1737 }
1738
1739 if (cursor_wm > cursor->max_wm) {
1740 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1741 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1742 return false;
1743 }
1744
1745 if (!(fbc_wm || display_wm || cursor_wm)) {
1746 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1747 return false;
1748 }
1749
1750 return true;
1751}
1752
1753/*
1754 * Compute watermark values of WM[1-3],
1755 */
1756static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1757 int latency_ns,
1758 const struct intel_watermark_params *display,
1759 const struct intel_watermark_params *cursor,
1760 int *fbc_wm, int *display_wm, int *cursor_wm)
1761{
1762 struct drm_crtc *crtc;
4fe8590a 1763 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1764 unsigned long line_time_us;
1765 int hdisplay, htotal, pixel_size, clock;
1766 int line_count, line_size;
1767 int small, large;
1768 int entries;
1769
1770 if (!latency_ns) {
1771 *fbc_wm = *display_wm = *cursor_wm = 0;
1772 return false;
1773 }
1774
1775 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1776 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1777 clock = adjusted_mode->crtc_clock;
4fe8590a 1778 htotal = adjusted_mode->htotal;
37327abd 1779 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1780 pixel_size = crtc->fb->bits_per_pixel / 8;
1781
1782 line_time_us = (htotal * 1000) / clock;
1783 line_count = (latency_ns / line_time_us + 1000) / 1000;
1784 line_size = hdisplay * pixel_size;
1785
1786 /* Use the minimum of the small and large buffer method for primary */
1787 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1788 large = line_count * line_size;
1789
1790 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1791 *display_wm = entries + display->guard_size;
1792
1793 /*
1794 * Spec says:
1795 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1796 */
1797 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1798
1799 /* calculate the self-refresh watermark for display cursor */
1800 entries = line_count * pixel_size * 64;
1801 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1802 *cursor_wm = entries + cursor->guard_size;
1803
1804 return ironlake_check_srwm(dev, level,
1805 *fbc_wm, *display_wm, *cursor_wm,
1806 display, cursor);
1807}
1808
46ba614c 1809static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1810{
46ba614c 1811 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1812 struct drm_i915_private *dev_priv = dev->dev_private;
1813 int fbc_wm, plane_wm, cursor_wm;
1814 unsigned int enabled;
1815
1816 enabled = 0;
51cea1f4 1817 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1818 &ironlake_display_wm_info,
b0aea5dc 1819 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1820 &ironlake_cursor_wm_info,
b0aea5dc 1821 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1822 &plane_wm, &cursor_wm)) {
1823 I915_WRITE(WM0_PIPEA_ILK,
1824 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1825 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1826 " plane %d, " "cursor: %d\n",
1827 plane_wm, cursor_wm);
51cea1f4 1828 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1829 }
1830
51cea1f4 1831 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1832 &ironlake_display_wm_info,
b0aea5dc 1833 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1834 &ironlake_cursor_wm_info,
b0aea5dc 1835 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1836 &plane_wm, &cursor_wm)) {
1837 I915_WRITE(WM0_PIPEB_ILK,
1838 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1839 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1840 " plane %d, cursor: %d\n",
1841 plane_wm, cursor_wm);
51cea1f4 1842 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1843 }
1844
1845 /*
1846 * Calculate and update the self-refresh watermark only when one
1847 * display plane is used.
1848 */
1849 I915_WRITE(WM3_LP_ILK, 0);
1850 I915_WRITE(WM2_LP_ILK, 0);
1851 I915_WRITE(WM1_LP_ILK, 0);
1852
1853 if (!single_plane_enabled(enabled))
1854 return;
1855 enabled = ffs(enabled) - 1;
1856
1857 /* WM1 */
1858 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1859 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1860 &ironlake_display_srwm_info,
1861 &ironlake_cursor_srwm_info,
1862 &fbc_wm, &plane_wm, &cursor_wm))
1863 return;
1864
1865 I915_WRITE(WM1_LP_ILK,
1866 WM1_LP_SR_EN |
b0aea5dc 1867 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1868 (fbc_wm << WM1_LP_FBC_SHIFT) |
1869 (plane_wm << WM1_LP_SR_SHIFT) |
1870 cursor_wm);
1871
1872 /* WM2 */
1873 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1874 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1875 &ironlake_display_srwm_info,
1876 &ironlake_cursor_srwm_info,
1877 &fbc_wm, &plane_wm, &cursor_wm))
1878 return;
1879
1880 I915_WRITE(WM2_LP_ILK,
1881 WM2_LP_EN |
b0aea5dc 1882 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1883 (fbc_wm << WM1_LP_FBC_SHIFT) |
1884 (plane_wm << WM1_LP_SR_SHIFT) |
1885 cursor_wm);
1886
1887 /*
1888 * WM3 is unsupported on ILK, probably because we don't have latency
1889 * data for that power state
1890 */
1891}
1892
46ba614c 1893static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1894{
46ba614c 1895 struct drm_device *dev = crtc->dev;
b445e3b0 1896 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1897 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1898 u32 val;
1899 int fbc_wm, plane_wm, cursor_wm;
1900 unsigned int enabled;
1901
1902 enabled = 0;
51cea1f4 1903 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1904 &sandybridge_display_wm_info, latency,
1905 &sandybridge_cursor_wm_info, latency,
1906 &plane_wm, &cursor_wm)) {
1907 val = I915_READ(WM0_PIPEA_ILK);
1908 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1909 I915_WRITE(WM0_PIPEA_ILK, val |
1910 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1911 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1912 " plane %d, " "cursor: %d\n",
1913 plane_wm, cursor_wm);
51cea1f4 1914 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1915 }
1916
51cea1f4 1917 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1918 &sandybridge_display_wm_info, latency,
1919 &sandybridge_cursor_wm_info, latency,
1920 &plane_wm, &cursor_wm)) {
1921 val = I915_READ(WM0_PIPEB_ILK);
1922 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1923 I915_WRITE(WM0_PIPEB_ILK, val |
1924 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1925 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1926 " plane %d, cursor: %d\n",
1927 plane_wm, cursor_wm);
51cea1f4 1928 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1929 }
1930
c43d0188
CW		 1931 /*
1932 * Calculate and update the self-refresh watermark only when one
1933 * display plane is used.
1934 *
1935 * SNB support 3 levels of watermark.
1936 *
1937 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1938 * and disabled in the descending order
1939 *
1940 */
1941 I915_WRITE(WM3_LP_ILK, 0);
1942 I915_WRITE(WM2_LP_ILK, 0);
1943 I915_WRITE(WM1_LP_ILK, 0);
1944
1945 if (!single_plane_enabled(enabled) ||
1946 dev_priv->sprite_scaling_enabled)
1947 return;
1948 enabled = ffs(enabled) - 1;
1949
1950 /* WM1 */
1951 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1952 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1953 &sandybridge_display_srwm_info,
1954 &sandybridge_cursor_srwm_info,
1955 &fbc_wm, &plane_wm, &cursor_wm))
1956 return;
1957
1958 I915_WRITE(WM1_LP_ILK,
1959 WM1_LP_SR_EN |
b0aea5dc 1960 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1961 (fbc_wm << WM1_LP_FBC_SHIFT) |
1962 (plane_wm << WM1_LP_SR_SHIFT) |
1963 cursor_wm);
1964
1965 /* WM2 */
1966 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1967 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1968 &sandybridge_display_srwm_info,
1969 &sandybridge_cursor_srwm_info,
1970 &fbc_wm, &plane_wm, &cursor_wm))
1971 return;
1972
1973 I915_WRITE(WM2_LP_ILK,
1974 WM2_LP_EN |
b0aea5dc 1975 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1976 (fbc_wm << WM1_LP_FBC_SHIFT) |
1977 (plane_wm << WM1_LP_SR_SHIFT) |
1978 cursor_wm);
1979
1980 /* WM3 */
1981 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1982 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1983 &sandybridge_display_srwm_info,
1984 &sandybridge_cursor_srwm_info,
1985 &fbc_wm, &plane_wm, &cursor_wm))
1986 return;
1987
1988 I915_WRITE(WM3_LP_ILK,
1989 WM3_LP_EN |
b0aea5dc 1990 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1991 (fbc_wm << WM1_LP_FBC_SHIFT) |
1992 (plane_wm << WM1_LP_SR_SHIFT) |
1993 cursor_wm);
1994}
1995
46ba614c 1996static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1997{
46ba614c 1998 struct drm_device *dev = crtc->dev;
c43d0188 1999 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2000 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2001 u32 val;
2002 int fbc_wm, plane_wm, cursor_wm;
2003 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2004 unsigned int enabled;
2005
2006 enabled = 0;
51cea1f4 2007 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2008 &sandybridge_display_wm_info, latency,
2009 &sandybridge_cursor_wm_info, latency,
2010 &plane_wm, &cursor_wm)) {
2011 val = I915_READ(WM0_PIPEA_ILK);
2012 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2013 I915_WRITE(WM0_PIPEA_ILK, val |
2014 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2015 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2016 " plane %d, " "cursor: %d\n",
2017 plane_wm, cursor_wm);
51cea1f4 2018 enabled |= 1 << PIPE_A;
c43d0188
CW		 2019 }
2020
51cea1f4 2021 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2022 &sandybridge_display_wm_info, latency,
2023 &sandybridge_cursor_wm_info, latency,
2024 &plane_wm, &cursor_wm)) {
2025 val = I915_READ(WM0_PIPEB_ILK);
2026 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2027 I915_WRITE(WM0_PIPEB_ILK, val |
2028 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2029 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2030 " plane %d, cursor: %d\n",
2031 plane_wm, cursor_wm);
51cea1f4 2032 enabled |= 1 << PIPE_B;
c43d0188
CW		 2033 }
2034
51cea1f4 2035 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2036 &sandybridge_display_wm_info, latency,
2037 &sandybridge_cursor_wm_info, latency,
2038 &plane_wm, &cursor_wm)) {
2039 val = I915_READ(WM0_PIPEC_IVB);
2040 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2041 I915_WRITE(WM0_PIPEC_IVB, val |
2042 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2043 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2044 " plane %d, cursor: %d\n",
2045 plane_wm, cursor_wm);
51cea1f4 2046 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2047 }
2048
2049 /*
2050 * Calculate and update the self-refresh watermark only when one
2051 * display plane is used.
2052 *
2053 * SNB support 3 levels of watermark.
2054 *
2055 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2056 * and disabled in the descending order
2057 *
2058 */
2059 I915_WRITE(WM3_LP_ILK, 0);
2060 I915_WRITE(WM2_LP_ILK, 0);
2061 I915_WRITE(WM1_LP_ILK, 0);
2062
2063 if (!single_plane_enabled(enabled) ||
2064 dev_priv->sprite_scaling_enabled)
2065 return;
2066 enabled = ffs(enabled) - 1;
2067
2068 /* WM1 */
2069 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2070 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2071 &sandybridge_display_srwm_info,
2072 &sandybridge_cursor_srwm_info,
2073 &fbc_wm, &plane_wm, &cursor_wm))
2074 return;
2075
2076 I915_WRITE(WM1_LP_ILK,
2077 WM1_LP_SR_EN |
b0aea5dc 2078 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2079 (fbc_wm << WM1_LP_FBC_SHIFT) |
2080 (plane_wm << WM1_LP_SR_SHIFT) |
2081 cursor_wm);
2082
2083 /* WM2 */
2084 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2085 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2086 &sandybridge_display_srwm_info,
2087 &sandybridge_cursor_srwm_info,
2088 &fbc_wm, &plane_wm, &cursor_wm))
2089 return;
2090
2091 I915_WRITE(WM2_LP_ILK,
2092 WM2_LP_EN |
b0aea5dc 2093 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2094 (fbc_wm << WM1_LP_FBC_SHIFT) |
2095 (plane_wm << WM1_LP_SR_SHIFT) |
2096 cursor_wm);
2097
c43d0188 2098 /* WM3, note we have to correct the cursor latency */
b445e3b0 2099 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2100 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2101 &sandybridge_display_srwm_info,
2102 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2103 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2104 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2105 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2106 &sandybridge_display_srwm_info,
2107 &sandybridge_cursor_srwm_info,
2108 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2109 return;
2110
2111 I915_WRITE(WM3_LP_ILK,
2112 WM3_LP_EN |
b0aea5dc 2113 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2114 (fbc_wm << WM1_LP_FBC_SHIFT) |
2115 (plane_wm << WM1_LP_SR_SHIFT) |
2116 cursor_wm);
2117}
2118
3658729a
VS		 2119static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2120 struct drm_crtc *crtc)
801bcfff
PZ		 2121{
2122 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2123 uint32_t pixel_rate;
801bcfff 2124
241bfc38 2125 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2126
2127 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2128 * adjust the pixel_rate here. */
2129
fd4daa9c 2130 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2131 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2132 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2133
37327abd
VS		 2134 pipe_w = intel_crtc->config.pipe_src_w;
2135 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2136 pfit_w = (pfit_size >> 16) & 0xFFFF;
2137 pfit_h = pfit_size & 0xFFFF;
2138 if (pipe_w < pfit_w)
2139 pipe_w = pfit_w;
2140 if (pipe_h < pfit_h)
2141 pipe_h = pfit_h;
2142
2143 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2144 pfit_w * pfit_h);
2145 }
2146
2147 return pixel_rate;
2148}
2149
37126462 2150/* latency must be in 0.1us units. */
23297044 2151static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2152 uint32_t latency)
2153{
2154 uint64_t ret;
2155
3312ba65
VS		 2156 if (WARN(latency == 0, "Latency value missing\n"))
2157 return UINT_MAX;
2158
801bcfff
PZ		 2159 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2160 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2161
2162 return ret;
2163}
2164
37126462 2165/* latency must be in 0.1us units. */
23297044 2166static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2167 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2168 uint32_t latency)
2169{
2170 uint32_t ret;
2171
3312ba65
VS		 2172 if (WARN(latency == 0, "Latency value missing\n"))
2173 return UINT_MAX;
2174
801bcfff
PZ		 2175 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2176 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2177 ret = DIV_ROUND_UP(ret, 64) + 2;
2178 return ret;
2179}
2180
23297044 2181static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2182 uint8_t bytes_per_pixel)
2183{
2184 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2185}
2186
801bcfff
PZ		 2187struct hsw_pipe_wm_parameters {
2188 bool active;
801bcfff
PZ		 2189 uint32_t pipe_htotal;
2190 uint32_t pixel_rate;
c35426d2
VS		 2191 struct intel_plane_wm_parameters pri;
2192 struct intel_plane_wm_parameters spr;
2193 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2194};
2195
cca32e9a
PZ		 2196struct hsw_wm_maximums {
2197 uint16_t pri;
2198 uint16_t spr;
2199 uint16_t cur;
2200 uint16_t fbc;
2201};
2202
801bcfff
PZ		 2203struct hsw_wm_values {
2204 uint32_t wm_pipe[3];
2205 uint32_t wm_lp[3];
2206 uint32_t wm_lp_spr[3];
2207 uint32_t wm_linetime[3];
cca32e9a 2208 bool enable_fbc_wm;
801bcfff
PZ		 2209};
2210
240264f4
VS		 2211/* used in computing the new watermarks state */
2212struct intel_wm_config {
2213 unsigned int num_pipes_active;
2214 bool sprites_enabled;
2215 bool sprites_scaled;
2216 bool fbc_wm_enabled;
2217};
2218
37126462
VS		 2219/*
2220 * For both WM_PIPE and WM_LP.
2221 * mem_value must be in 0.1us units.
2222 */
ac830fe1 2223static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2224 uint32_t mem_value,
2225 bool is_lp)
801bcfff 2226{
cca32e9a
PZ		 2227 uint32_t method1, method2;
2228
c35426d2 2229 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2230 return 0;
2231
23297044 2232 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2233 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2234 mem_value);
2235
2236 if (!is_lp)
2237 return method1;
2238
23297044 2239 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2240 params->pipe_htotal,
c35426d2
VS		 2241 params->pri.horiz_pixels,
2242 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2243 mem_value);
2244
2245 return min(method1, method2);
801bcfff
PZ		 2246}
2247
37126462
VS		 2248/*
2249 * For both WM_PIPE and WM_LP.
2250 * mem_value must be in 0.1us units.
2251 */
ac830fe1 2252static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2253 uint32_t mem_value)
2254{
2255 uint32_t method1, method2;
2256
c35426d2 2257 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2258 return 0;
2259
23297044 2260 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2261 params->spr.bytes_per_pixel,
801bcfff 2262 mem_value);
23297044 2263 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2264 params->pipe_htotal,
c35426d2
VS		 2265 params->spr.horiz_pixels,
2266 params->spr.bytes_per_pixel,
801bcfff
PZ		 2267 mem_value);
2268 return min(method1, method2);
2269}
2270
37126462
VS		 2271/*
2272 * For both WM_PIPE and WM_LP.
2273 * mem_value must be in 0.1us units.
2274 */
ac830fe1 2275static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2276 uint32_t mem_value)
2277{
c35426d2 2278 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2279 return 0;
2280
23297044 2281 return ilk_wm_method2(params->pixel_rate,
801bcfff 2282 params->pipe_htotal,
c35426d2
VS		 2283 params->cur.horiz_pixels,
2284 params->cur.bytes_per_pixel,
801bcfff
PZ		 2285 mem_value);
2286}
2287
cca32e9a 2288/* Only for WM_LP. */
ac830fe1 2289static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2290 uint32_t pri_val)
cca32e9a 2291{
c35426d2 2292 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2293 return 0;
2294
23297044 2295 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2296 params->pri.horiz_pixels,
2297 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2298}
2299
158ae64f
VS		 2300static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2301{
2302 if (INTEL_INFO(dev)->gen >= 7)
2303 return 768;
2304 else
2305 return 512;
2306}
2307
2308/* Calculate the maximum primary/sprite plane watermark */
2309static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2310 int level,
240264f4 2311 const struct intel_wm_config *config,
158ae64f
VS		 2312 enum intel_ddb_partitioning ddb_partitioning,
2313 bool is_sprite)
2314{
2315 unsigned int fifo_size = ilk_display_fifo_size(dev);
2316 unsigned int max;
2317
2318 /* if sprites aren't enabled, sprites get nothing */
240264f4 2319 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2320 return 0;
2321
2322 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2323 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2324 fifo_size /= INTEL_INFO(dev)->num_pipes;
2325
2326 /*
2327 * For some reason the non self refresh
2328 * FIFO size is only half of the self
2329 * refresh FIFO size on ILK/SNB.
2330 */
2331 if (INTEL_INFO(dev)->gen <= 6)
2332 fifo_size /= 2;
2333 }
2334
240264f4 2335 if (config->sprites_enabled) {
158ae64f
VS		 2336 /* level 0 is always calculated with 1:1 split */
2337 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2338 if (is_sprite)
2339 fifo_size *= 5;
2340 fifo_size /= 6;
2341 } else {
2342 fifo_size /= 2;
2343 }
2344 }
2345
2346 /* clamp to max that the registers can hold */
2347 if (INTEL_INFO(dev)->gen >= 7)
2348 /* IVB/HSW primary/sprite plane watermarks */
2349 max = level == 0 ? 127 : 1023;
2350 else if (!is_sprite)
2351 /* ILK/SNB primary plane watermarks */
2352 max = level == 0 ? 127 : 511;
2353 else
2354 /* ILK/SNB sprite plane watermarks */
2355 max = level == 0 ? 63 : 255;
2356
2357 return min(fifo_size, max);
2358}
2359
2360/* Calculate the maximum cursor plane watermark */
2361static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2362 int level,
2363 const struct intel_wm_config *config)
158ae64f
VS		 2364{
2365 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2366 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2367 return 64;
2368
2369 /* otherwise just report max that registers can hold */
2370 if (INTEL_INFO(dev)->gen >= 7)
2371 return level == 0 ? 63 : 255;
2372 else
2373 return level == 0 ? 31 : 63;
2374}
2375
2376/* Calculate the maximum FBC watermark */
2377static unsigned int ilk_fbc_wm_max(void)
2378{
2379 /* max that registers can hold */
2380 return 15;
2381}
2382
2383static void ilk_wm_max(struct drm_device *dev,
2384 int level,
240264f4 2385 const struct intel_wm_config *config,
158ae64f
VS		 2386 enum intel_ddb_partitioning ddb_partitioning,
2387 struct hsw_wm_maximums *max)
2388{
240264f4
VS		 2389 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2390 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2391 max->cur = ilk_cursor_wm_max(dev, level, config);
158ae64f
VS		 2392 max->fbc = ilk_fbc_wm_max();
2393}
2394
a9786a11
VS		 2395static bool ilk_check_wm(int level,
2396 const struct hsw_wm_maximums *max,
1fd527cc 2397 struct intel_wm_level *result)
a9786a11
VS		 2398{
2399 bool ret;
2400
2401 /* already determined to be invalid? */
2402 if (!result->enable)
2403 return false;
2404
2405 result->enable = result->pri_val <= max->pri &&
2406 result->spr_val <= max->spr &&
2407 result->cur_val <= max->cur;
2408
2409 ret = result->enable;
2410
2411 /*
2412 * HACK until we can pre-compute everything,
2413 * and thus fail gracefully if LP0 watermarks
2414 * are exceeded...
2415 */
2416 if (level == 0 && !result->enable) {
2417 if (result->pri_val > max->pri)
2418 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2419 level, result->pri_val, max->pri);
2420 if (result->spr_val > max->spr)
2421 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2422 level, result->spr_val, max->spr);
2423 if (result->cur_val > max->cur)
2424 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2425 level, result->cur_val, max->cur);
2426
2427 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2428 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2429 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2430 result->enable = true;
2431 }
2432
2433 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2434
2435 return ret;
2436}
2437
6f5ddd17
VS		 2438static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2439 int level,
ac830fe1 2440 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2441 struct intel_wm_level *result)
6f5ddd17
VS		 2442{
2443 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2444 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2445 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2446
2447 /* WM1+ latency values stored in 0.5us units */
2448 if (level > 0) {
2449 pri_latency *= 5;
2450 spr_latency *= 5;
2451 cur_latency *= 5;
2452 }
2453
2454 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2455 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2456 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2457 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2458 result->enable = true;
2459}
2460
5b77da33 2461static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
ac830fe1
VS		 2462 int level, const struct hsw_wm_maximums *max,
2463 const struct hsw_pipe_wm_parameters *params,
1fd527cc 2464 struct intel_wm_level *result)
cca32e9a
PZ		 2465{
2466 enum pipe pipe;
1fd527cc 2467 struct intel_wm_level res[3];
6f5ddd17
VS		 2468
2469 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2470 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
cca32e9a 2471
6f5ddd17
VS		 2472 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2473 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2474 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2475 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2476 result->enable = true;
cca32e9a 2477
a9786a11 2478 return ilk_check_wm(level, max, result);
cca32e9a
PZ		 2479}
2480
8de123a5
VS		 2481
2482static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
ac830fe1 2483 const struct hsw_pipe_wm_parameters *params)
801bcfff 2484{
8de123a5
VS		 2485 struct drm_i915_private *dev_priv = dev->dev_private;
2486 struct intel_wm_config config = {
2487 .num_pipes_active = 1,
2488 .sprites_enabled = params->spr.enabled,
2489 .sprites_scaled = params->spr.scaled,
2490 };
2491 struct hsw_wm_maximums max;
2492 struct intel_wm_level res;
2493
2494 if (!params->active)
2495 return 0;
2496
2497 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
801bcfff 2498
8de123a5 2499 ilk_compute_wm_level(dev_priv, 0, params, &res);
801bcfff 2500
8de123a5 2501 ilk_check_wm(0, &max, &res);
801bcfff 2502
8de123a5
VS		 2503 return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
2504 (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
2505 res.cur_val;
801bcfff
PZ		 2506}
2507
2508static uint32_t
2509hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2510{
2511 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2512 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2513 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2514 u32 linetime, ips_linetime;
1f8eeabf 2515
801bcfff
PZ		 2516 if (!intel_crtc_active(crtc))
2517 return 0;
1011d8c4 2518
1f8eeabf
ED		 2519 /* The WM are computed with base on how long it takes to fill a single
2520 * row at the given clock rate, multiplied by 8.
2521 * */
85a02deb
PZ		 2522 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2523 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2524 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2525
801bcfff
PZ		 2526 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2527 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2528}
2529
12b134df
VS		 2530static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2531{
2532 struct drm_i915_private *dev_priv = dev->dev_private;
2533
2534 if (IS_HASWELL(dev)) {
2535 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2536
2537 wm[0] = (sskpd >> 56) & 0xFF;
2538 if (wm[0] == 0)
2539 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2540 wm[1] = (sskpd >> 4) & 0xFF;
2541 wm[2] = (sskpd >> 12) & 0xFF;
2542 wm[3] = (sskpd >> 20) & 0x1FF;
2543 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2544 } else if (INTEL_INFO(dev)->gen >= 6) {
2545 uint32_t sskpd = I915_READ(MCH_SSKPD);
2546
2547 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2548 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2549 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2550 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2551 } else if (INTEL_INFO(dev)->gen >= 5) {
2552 uint32_t mltr = I915_READ(MLTR_ILK);
2553
2554 /* ILK primary LP0 latency is 700 ns */
2555 wm[0] = 7;
2556 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2557 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2558 }
2559}
2560
53615a5e
VS		 2561static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2562{
2563 /* ILK sprite LP0 latency is 1300 ns */
2564 if (INTEL_INFO(dev)->gen == 5)
2565 wm[0] = 13;
2566}
2567
2568static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2569{
2570 /* ILK cursor LP0 latency is 1300 ns */
2571 if (INTEL_INFO(dev)->gen == 5)
2572 wm[0] = 13;
2573
2574 /* WaDoubleCursorLP3Latency:ivb */
2575 if (IS_IVYBRIDGE(dev))
2576 wm[3] *= 2;
2577}
2578
ad0d6dc4 2579static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2580{
26ec971e
VS		 2581 /* how many WM levels are we expecting */
2582 if (IS_HASWELL(dev))
ad0d6dc4 2583 return 4;
26ec971e 2584 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2585 return 3;
26ec971e 2586 else
ad0d6dc4
VS		 2587 return 2;
2588}
2589
2590static void intel_print_wm_latency(struct drm_device *dev,
2591 const char *name,
2592 const uint16_t wm[5])
2593{
2594 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2595
2596 for (level = 0; level <= max_level; level++) {
2597 unsigned int latency = wm[level];
2598
2599 if (latency == 0) {
2600 DRM_ERROR("%s WM%d latency not provided\n",
2601 name, level);
2602 continue;
2603 }
2604
2605 /* WM1+ latency values in 0.5us units */
2606 if (level > 0)
2607 latency *= 5;
2608
2609 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2610 name, level, wm[level],
2611 latency / 10, latency % 10);
2612 }
2613}
2614
53615a5e
VS		 2615static void intel_setup_wm_latency(struct drm_device *dev)
2616{
2617 struct drm_i915_private *dev_priv = dev->dev_private;
2618
2619 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2620
2621 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2622 sizeof(dev_priv->wm.pri_latency));
2623 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2624 sizeof(dev_priv->wm.pri_latency));
2625
2626 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2627 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2628
2629 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2630 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2631 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2632}
2633
801bcfff
PZ		 2634static void hsw_compute_wm_parameters(struct drm_device *dev,
2635 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2636 struct hsw_wm_maximums *lp_max_1_2,
2637 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2638{
1011d8c4 2639 struct drm_crtc *crtc;
801bcfff 2640 struct drm_plane *plane;
1011d8c4 2641 enum pipe pipe;
240264f4 2642 struct intel_wm_config config = {};
1011d8c4 2643
801bcfff
PZ		 2644 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2646 struct hsw_pipe_wm_parameters *p;
2647
2648 pipe = intel_crtc->pipe;
2649 p = &params[pipe];
2650
2651 p->active = intel_crtc_active(crtc);
2652 if (!p->active)
2653 continue;
2654
240264f4 2655 config.num_pipes_active++;
cca32e9a 2656
801bcfff 2657 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2658 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2659 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2660 p->cur.bytes_per_pixel = 4;
37327abd 2661 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2662 p->cur.horiz_pixels = 64;
2663 /* TODO: for now, assume primary and cursor planes are always enabled. */
2664 p->pri.enabled = true;
2665 p->cur.enabled = true;
801bcfff
PZ		 2666 }
2667
2668 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2669 struct intel_plane *intel_plane = to_intel_plane(plane);
2670 struct hsw_pipe_wm_parameters *p;
2671
2672 pipe = intel_plane->pipe;
2673 p = &params[pipe];
2674
c35426d2 2675 p->spr = intel_plane->wm;
cca32e9a 2676
c35426d2
VS		 2677 config.sprites_enabled |= p->spr.enabled;
2678 config.sprites_scaled |= p->spr.scaled;
cca32e9a
PZ		 2679 }
2680
240264f4 2681 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
158ae64f
VS		 2682
2683 /* 5/6 split only in single pipe config on IVB+ */
240264f4
VS		 2684 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2685 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
158ae64f
VS		 2686 else
2687 *lp_max_5_6 = *lp_max_1_2;
801bcfff
PZ		 2688}
2689
2690static void hsw_compute_wm_results(struct drm_device *dev,
ac830fe1
VS		 2691 const struct hsw_pipe_wm_parameters *params,
2692 const struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2693 struct hsw_wm_values *results)
2694{
2695 struct drm_i915_private *dev_priv = dev->dev_private;
2696 struct drm_crtc *crtc;
1fd527cc 2697 struct intel_wm_level lp_results[4] = {};
801bcfff 2698 enum pipe pipe;
cca32e9a
PZ		 2699 int level, max_level, wm_lp;
2700
2701 for (level = 1; level <= 4; level++)
5b77da33
VS		 2702 if (!hsw_compute_lp_wm(dev_priv, level,
2703 lp_maximums, params,
cca32e9a
PZ		 2704 &lp_results[level - 1]))
2705 break;
2706 max_level = level - 1;
2707
5c536613
VS		 2708 memset(results, 0, sizeof(*results));
2709
cca32e9a
PZ		 2710 /* The spec says it is preferred to disable FBC WMs instead of disabling
2711 * a WM level. */
2712 results->enable_fbc_wm = true;
2713 for (level = 1; level <= max_level; level++) {
16e54061 2714 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
cca32e9a 2715 results->enable_fbc_wm = false;
71fff20f 2716 lp_results[level - 1].fbc_val = 0;
cca32e9a
PZ		 2717 }
2718 }
2719
cca32e9a 2720 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2721 const struct intel_wm_level *r;
801bcfff 2722
cca32e9a
PZ		 2723 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2724 if (level > max_level)
2725 break;
2726
2727 r = &lp_results[level - 1];
2728 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2729 r->fbc_val,
2730 r->pri_val,
2731 r->cur_val);
2732 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2733 }
801bcfff
PZ		 2734
2735 for_each_pipe(pipe)
8de123a5 2736 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
801bcfff 2737 &params[pipe]);
1011d8c4
PZ		 2738
2739 for_each_pipe(pipe) {
2740 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2741 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2742 }
2743}
2744
861f3389
PZ		 2745/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2746 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2747static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2748 struct hsw_wm_values *r2)
861f3389
PZ		 2749{
2750 int i, val_r1 = 0, val_r2 = 0;
2751
2752 for (i = 0; i < 3; i++) {
2753 if (r1->wm_lp[i] & WM3_LP_EN)
2754 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2755 if (r2->wm_lp[i] & WM3_LP_EN)
2756 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2757 }
2758
2759 if (val_r1 == val_r2) {
2760 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2761 return r2;
2762 else
2763 return r1;
2764 } else if (val_r1 > val_r2) {
2765 return r1;
2766 } else {
2767 return r2;
2768 }
2769}
2770
801bcfff
PZ		 2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
2775static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct hsw_wm_values *results,
77c122bc 2777 enum intel_ddb_partitioning partitioning)
801bcfff
PZ		 2778{
2779 struct hsw_wm_values previous;
2780 uint32_t val;
77c122bc 2781 enum intel_ddb_partitioning prev_partitioning;
cca32e9a 2782 bool prev_enable_fbc_wm;
801bcfff
PZ		 2783
2784 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2785 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2786 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2787 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2788 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2789 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2790 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2791 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2792 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2793 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2794 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2795 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2796
2797 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
77c122bc 2798 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
801bcfff 2799
cca32e9a
PZ		 2800 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2801
801bcfff
PZ		 2802 if (memcmp(results->wm_pipe, previous.wm_pipe,
2803 sizeof(results->wm_pipe)) == 0 &&
2804 memcmp(results->wm_lp, previous.wm_lp,
2805 sizeof(results->wm_lp)) == 0 &&
2806 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2807 sizeof(results->wm_lp_spr)) == 0 &&
2808 memcmp(results->wm_linetime, previous.wm_linetime,
2809 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2810 partitioning == prev_partitioning &&
2811 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2812 return;
2813
2814 if (previous.wm_lp[2] != 0)
2815 I915_WRITE(WM3_LP_ILK, 0);
2816 if (previous.wm_lp[1] != 0)
2817 I915_WRITE(WM2_LP_ILK, 0);
2818 if (previous.wm_lp[0] != 0)
2819 I915_WRITE(WM1_LP_ILK, 0);
2820
2821 if (previous.wm_pipe[0] != results->wm_pipe[0])
2822 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2823 if (previous.wm_pipe[1] != results->wm_pipe[1])
2824 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2825 if (previous.wm_pipe[2] != results->wm_pipe[2])
2826 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2827
2828 if (previous.wm_linetime[0] != results->wm_linetime[0])
2829 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2830 if (previous.wm_linetime[1] != results->wm_linetime[1])
2831 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2832 if (previous.wm_linetime[2] != results->wm_linetime[2])
2833 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2834
2835 if (prev_partitioning != partitioning) {
2836 val = I915_READ(WM_MISC);
77c122bc 2837 if (partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2838 val &= ~WM_MISC_DATA_PARTITION_5_6;
2839 else
2840 val |= WM_MISC_DATA_PARTITION_5_6;
2841 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2842 }
2843
cca32e9a
PZ		 2844 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2845 val = I915_READ(DISP_ARB_CTL);
2846 if (results->enable_fbc_wm)
2847 val &= ~DISP_FBC_WM_DIS;
2848 else
2849 val |= DISP_FBC_WM_DIS;
2850 I915_WRITE(DISP_ARB_CTL, val);
2851 }
2852
801bcfff
PZ		 2853 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2854 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2855 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2856 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2857 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2858 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2859
2860 if (results->wm_lp[0] != 0)
2861 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2862 if (results->wm_lp[1] != 0)
2863 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2864 if (results->wm_lp[2] != 0)
2865 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2866}
2867
46ba614c 2868static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2869{
46ba614c 2870 struct drm_device *dev = crtc->dev;
801bcfff 2871 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2872 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2873 struct hsw_pipe_wm_parameters params[3];
861f3389 2874 struct hsw_wm_values results_1_2, results_5_6, *best_results;
77c122bc 2875 enum intel_ddb_partitioning partitioning;
861f3389 2876
12b134df 2877 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2878
53615a5e 2879 hsw_compute_wm_results(dev, params,
53615a5e 2880 &lp_max_1_2, &results_1_2);
861f3389 2881 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2882 hsw_compute_wm_results(dev, params,
53615a5e 2883 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2884 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2885 } else {
2886 best_results = &results_1_2;
2887 }
2888
2889 partitioning = (best_results == &results_1_2) ?
77c122bc 2890 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2891
861f3389 2892 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2893}
2894
adf3d35e
VS		 2895static void haswell_update_sprite_wm(struct drm_plane *plane,
2896 struct drm_crtc *crtc,
526682e9 2897 uint32_t sprite_width, int pixel_size,
bdd57d03 2898 bool enabled, bool scaled)
526682e9 2899{
adf3d35e 2900 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2901
adf3d35e
VS		 2902 intel_plane->wm.enabled = enabled;
2903 intel_plane->wm.scaled = scaled;
2904 intel_plane->wm.horiz_pixels = sprite_width;
2905 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2906
46ba614c 2907 haswell_update_wm(crtc);
526682e9
PZ		 2908}
2909
b445e3b0
ED		 2910static bool
2911sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2912 uint32_t sprite_width, int pixel_size,
2913 const struct intel_watermark_params *display,
2914 int display_latency_ns, int *sprite_wm)
2915{
2916 struct drm_crtc *crtc;
2917 int clock;
2918 int entries, tlb_miss;
2919
2920 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2921 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2922 *sprite_wm = display->guard_size;
2923 return false;
2924 }
2925
241bfc38 2926 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 2927
2928 /* Use the small buffer method to calculate the sprite watermark */
2929 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2930 tlb_miss = display->fifo_size*display->cacheline_size -
2931 sprite_width * 8;
2932 if (tlb_miss > 0)
2933 entries += tlb_miss;
2934 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2935 *sprite_wm = entries + display->guard_size;
2936 if (*sprite_wm > (int)display->max_wm)
2937 *sprite_wm = display->max_wm;
2938
2939 return true;
2940}
2941
2942static bool
2943sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2944 uint32_t sprite_width, int pixel_size,
2945 const struct intel_watermark_params *display,
2946 int latency_ns, int *sprite_wm)
2947{
2948 struct drm_crtc *crtc;
2949 unsigned long line_time_us;
2950 int clock;
2951 int line_count, line_size;
2952 int small, large;
2953 int entries;
2954
2955 if (!latency_ns) {
2956 *sprite_wm = 0;
2957 return false;
2958 }
2959
2960 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 2961 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 2962 if (!clock) {
2963 *sprite_wm = 0;
2964 return false;
2965 }
2966
2967 line_time_us = (sprite_width * 1000) / clock;
2968 if (!line_time_us) {
2969 *sprite_wm = 0;
2970 return false;
2971 }
2972
2973 line_count = (latency_ns / line_time_us + 1000) / 1000;
2974 line_size = sprite_width * pixel_size;
2975
2976 /* Use the minimum of the small and large buffer method for primary */
2977 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2978 large = line_count * line_size;
2979
2980 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2981 *sprite_wm = entries + display->guard_size;
2982
2983 return *sprite_wm > 0x3ff ? false : true;
2984}
2985
adf3d35e
VS		 2986static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2987 struct drm_crtc *crtc,
4c4ff43a 2988 uint32_t sprite_width, int pixel_size,
39db4a4d 2989 bool enabled, bool scaled)
b445e3b0 2990{
adf3d35e 2991 struct drm_device *dev = plane->dev;
b445e3b0 2992 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 2993 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 2994 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2995 u32 val;
2996 int sprite_wm, reg;
2997 int ret;
2998
39db4a4d 2999 if (!enabled)
4c4ff43a
PZ		 3000 return;
3001
b445e3b0
ED		 3002 switch (pipe) {
3003 case 0:
3004 reg = WM0_PIPEA_ILK;
3005 break;
3006 case 1:
3007 reg = WM0_PIPEB_ILK;
3008 break;
3009 case 2:
3010 reg = WM0_PIPEC_IVB;
3011 break;
3012 default:
3013 return; /* bad pipe */
3014 }
3015
3016 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3017 &sandybridge_display_wm_info,
3018 latency, &sprite_wm);
3019 if (!ret) {
84f44ce7
VS		 3020 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3021 pipe_name(pipe));
b445e3b0
ED		 3022 return;
3023 }
3024
3025 val = I915_READ(reg);
3026 val &= ~WM0_PIPE_SPRITE_MASK;
3027 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3028 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3029
3030
3031 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3032 pixel_size,
3033 &sandybridge_display_srwm_info,
b0aea5dc 3034 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3035 &sprite_wm);
3036 if (!ret) {
84f44ce7
VS		 3037 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3038 pipe_name(pipe));
b445e3b0
ED		 3039 return;
3040 }
3041 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3042
3043 /* Only IVB has two more LP watermarks for sprite */
3044 if (!IS_IVYBRIDGE(dev))
3045 return;
3046
3047 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3048 pixel_size,
3049 &sandybridge_display_srwm_info,
b0aea5dc 3050 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3051 &sprite_wm);
3052 if (!ret) {
84f44ce7
VS		 3053 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3054 pipe_name(pipe));
b445e3b0
ED		 3055 return;
3056 }
3057 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3058
3059 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3060 pixel_size,
3061 &sandybridge_display_srwm_info,
b0aea5dc 3062 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3063 &sprite_wm);
3064 if (!ret) {
84f44ce7
VS		 3065 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3066 pipe_name(pipe));
b445e3b0
ED		 3067 return;
3068 }
3069 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3070}
3071
3072/**
3073 * intel_update_watermarks - update FIFO watermark values based on current modes
3074 *
3075 * Calculate watermark values for the various WM regs based on current mode
3076 * and plane configuration.
3077 *
3078 * There are several cases to deal with here:
3079 * - normal (i.e. non-self-refresh)
3080 * - self-refresh (SR) mode
3081 * - lines are large relative to FIFO size (buffer can hold up to 2)
3082 * - lines are small relative to FIFO size (buffer can hold more than 2
3083 * lines), so need to account for TLB latency
3084 *
3085 * The normal calculation is:
3086 * watermark = dotclock * bytes per pixel * latency
3087 * where latency is platform & configuration dependent (we assume pessimal
3088 * values here).
3089 *
3090 * The SR calculation is:
3091 * watermark = (trunc(latency/line time)+1) * surface width *
3092 * bytes per pixel
3093 * where
3094 * line time = htotal / dotclock
3095 * surface width = hdisplay for normal plane and 64 for cursor
3096 * and latency is assumed to be high, as above.
3097 *
3098 * The final value programmed to the register should always be rounded up,
3099 * and include an extra 2 entries to account for clock crossings.
3100 *
3101 * We don't use the sprite, so we can ignore that. And on Crestline we have
3102 * to set the non-SR watermarks to 8.
3103 */
46ba614c 3104void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3105{
46ba614c 3106 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3107
3108 if (dev_priv->display.update_wm)
46ba614c 3109 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3110}
3111
adf3d35e
VS		 3112void intel_update_sprite_watermarks(struct drm_plane *plane,
3113 struct drm_crtc *crtc,
4c4ff43a 3114 uint32_t sprite_width, int pixel_size,
39db4a4d 3115 bool enabled, bool scaled)
b445e3b0 3116{
adf3d35e 3117 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3118
3119 if (dev_priv->display.update_sprite_wm)
adf3d35e 3120 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3121 pixel_size, enabled, scaled);
b445e3b0
ED		 3122}
3123
2b4e57bd
ED		 3124static struct drm_i915_gem_object *
3125intel_alloc_context_page(struct drm_device *dev)
3126{
3127 struct drm_i915_gem_object *ctx;
3128 int ret;
3129
3130 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3131
3132 ctx = i915_gem_alloc_object(dev, 4096);
3133 if (!ctx) {
3134 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3135 return NULL;
3136 }
3137
c37e2204 3138 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3139 if (ret) {
3140 DRM_ERROR("failed to pin power context: %d\n", ret);
3141 goto err_unref;
3142 }
3143
3144 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3145 if (ret) {
3146 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3147 goto err_unpin;
3148 }
3149
3150 return ctx;
3151
3152err_unpin:
3153 i915_gem_object_unpin(ctx);
3154err_unref:
3155 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3156 return NULL;
3157}
3158
9270388e
DV		 3159/**
3160 * Lock protecting IPS related data structures
9270388e
DV		 3161 */
3162DEFINE_SPINLOCK(mchdev_lock);
3163
3164/* Global for IPS driver to get at the current i915 device. Protected by
3165 * mchdev_lock. */
3166static struct drm_i915_private *i915_mch_dev;
3167
2b4e57bd
ED		 3168bool ironlake_set_drps(struct drm_device *dev, u8 val)
3169{
3170 struct drm_i915_private *dev_priv = dev->dev_private;
3171 u16 rgvswctl;
3172
9270388e
DV		 3173 assert_spin_locked(&mchdev_lock);
3174
2b4e57bd
ED		 3175 rgvswctl = I915_READ16(MEMSWCTL);
3176 if (rgvswctl & MEMCTL_CMD_STS) {
3177 DRM_DEBUG("gpu busy, RCS change rejected\n");
3178 return false; /* still busy with another command */
3179 }
3180
3181 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3182 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3183 I915_WRITE16(MEMSWCTL, rgvswctl);
3184 POSTING_READ16(MEMSWCTL);
3185
3186 rgvswctl |= MEMCTL_CMD_STS;
3187 I915_WRITE16(MEMSWCTL, rgvswctl);
3188
3189 return true;
3190}
3191
8090c6b9 3192static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3193{
3194 struct drm_i915_private *dev_priv = dev->dev_private;
3195 u32 rgvmodectl = I915_READ(MEMMODECTL);
3196 u8 fmax, fmin, fstart, vstart;
3197
9270388e
DV		 3198 spin_lock_irq(&mchdev_lock);
3199
2b4e57bd
ED		 3200 /* Enable temp reporting */
3201 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3202 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3203
3204 /* 100ms RC evaluation intervals */
3205 I915_WRITE(RCUPEI, 100000);
3206 I915_WRITE(RCDNEI, 100000);
3207
3208 /* Set max/min thresholds to 90ms and 80ms respectively */
3209 I915_WRITE(RCBMAXAVG, 90000);
3210 I915_WRITE(RCBMINAVG, 80000);
3211
3212 I915_WRITE(MEMIHYST, 1);
3213
3214 /* Set up min, max, and cur for interrupt handling */
3215 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3216 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3217 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3218 MEMMODE_FSTART_SHIFT;
3219
3220 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3221 PXVFREQ_PX_SHIFT;
3222
20e4d407
DV		 3223 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3224 dev_priv->ips.fstart = fstart;
2b4e57bd 3225
20e4d407
DV		 3226 dev_priv->ips.max_delay = fstart;
3227 dev_priv->ips.min_delay = fmin;
3228 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3229
3230 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3231 fmax, fmin, fstart);
3232
3233 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3234
3235 /*
3236 * Interrupts will be enabled in ironlake_irq_postinstall
3237 */
3238
3239 I915_WRITE(VIDSTART, vstart);
3240 POSTING_READ(VIDSTART);
3241
3242 rgvmodectl |= MEMMODE_SWMODE_EN;
3243 I915_WRITE(MEMMODECTL, rgvmodectl);
3244
9270388e 3245 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3246 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3247 mdelay(1);
2b4e57bd
ED		 3248
3249 ironlake_set_drps(dev, fstart);
3250
20e4d407 3251 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3252 I915_READ(0x112e0);
20e4d407
DV		 3253 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3254 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3255 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3256
3257 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3258}
3259
8090c6b9 3260static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3261{
3262 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3263 u16 rgvswctl;
3264
3265 spin_lock_irq(&mchdev_lock);
3266
3267 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3268
3269 /* Ack interrupts, disable EFC interrupt */
3270 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3271 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3272 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3273 I915_WRITE(DEIIR, DE_PCU_EVENT);
3274 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3275
3276 /* Go back to the starting frequency */
20e4d407 3277 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3278 mdelay(1);
2b4e57bd
ED		 3279 rgvswctl |= MEMCTL_CMD_STS;
3280 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3281 mdelay(1);
2b4e57bd 3282
9270388e 3283 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3284}
3285
acbe9475
DV		 3286/* There's a funny hw issue where the hw returns all 0 when reading from
3287 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3288 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3289 * all limits and the gpu stuck at whatever frequency it is at atm).
3290 */
65bccb5c 3291static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3292{
7b9e0ae6 3293 u32 limits;
2b4e57bd 3294
7b9e0ae6 3295 limits = 0;
c6a828d3
DV		 3296
3297 if (*val >= dev_priv->rps.max_delay)
3298 *val = dev_priv->rps.max_delay;
3299 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3300
3301 /* Only set the down limit when we've reached the lowest level to avoid
3302 * getting more interrupts, otherwise leave this clear. This prevents a
3303 * race in the hw when coming out of rc6: There's a tiny window where
3304 * the hw runs at the minimal clock before selecting the desired
3305 * frequency, if the down threshold expires in that window we will not
3306 * receive a down interrupt. */
c6a828d3
DV		 3307 if (*val <= dev_priv->rps.min_delay) {
3308 *val = dev_priv->rps.min_delay;
3309 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3310 }
3311
3312 return limits;
3313}
3314
dd75fdc8
CW		 3315static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3316{
3317 int new_power;
3318
3319 new_power = dev_priv->rps.power;
3320 switch (dev_priv->rps.power) {
3321 case LOW_POWER:
3322 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3323 new_power = BETWEEN;
3324 break;
3325
3326 case BETWEEN:
3327 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3328 new_power = LOW_POWER;
3329 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3330 new_power = HIGH_POWER;
3331 break;
3332
3333 case HIGH_POWER:
3334 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3335 new_power = BETWEEN;
3336 break;
3337 }
3338 /* Max/min bins are special */
3339 if (val == dev_priv->rps.min_delay)
3340 new_power = LOW_POWER;
3341 if (val == dev_priv->rps.max_delay)
3342 new_power = HIGH_POWER;
3343 if (new_power == dev_priv->rps.power)
3344 return;
3345
3346 /* Note the units here are not exactly 1us, but 1280ns. */
3347 switch (new_power) {
3348 case LOW_POWER:
3349 /* Upclock if more than 95% busy over 16ms */
3350 I915_WRITE(GEN6_RP_UP_EI, 12500);
3351 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3352
3353 /* Downclock if less than 85% busy over 32ms */
3354 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3355 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3356
3357 I915_WRITE(GEN6_RP_CONTROL,
3358 GEN6_RP_MEDIA_TURBO |
3359 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3360 GEN6_RP_MEDIA_IS_GFX |
3361 GEN6_RP_ENABLE |
3362 GEN6_RP_UP_BUSY_AVG |
3363 GEN6_RP_DOWN_IDLE_AVG);
3364 break;
3365
3366 case BETWEEN:
3367 /* Upclock if more than 90% busy over 13ms */
3368 I915_WRITE(GEN6_RP_UP_EI, 10250);
3369 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3370
3371 /* Downclock if less than 75% busy over 32ms */
3372 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3373 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3374
3375 I915_WRITE(GEN6_RP_CONTROL,
3376 GEN6_RP_MEDIA_TURBO |
3377 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3378 GEN6_RP_MEDIA_IS_GFX |
3379 GEN6_RP_ENABLE |
3380 GEN6_RP_UP_BUSY_AVG |
3381 GEN6_RP_DOWN_IDLE_AVG);
3382 break;
3383
3384 case HIGH_POWER:
3385 /* Upclock if more than 85% busy over 10ms */
3386 I915_WRITE(GEN6_RP_UP_EI, 8000);
3387 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3388
3389 /* Downclock if less than 60% busy over 32ms */
3390 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3391 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3392
3393 I915_WRITE(GEN6_RP_CONTROL,
3394 GEN6_RP_MEDIA_TURBO |
3395 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3396 GEN6_RP_MEDIA_IS_GFX |
3397 GEN6_RP_ENABLE |
3398 GEN6_RP_UP_BUSY_AVG |
3399 GEN6_RP_DOWN_IDLE_AVG);
3400 break;
3401 }
3402
3403 dev_priv->rps.power = new_power;
3404 dev_priv->rps.last_adj = 0;
3405}
3406
20b46e59
DV		 3407void gen6_set_rps(struct drm_device *dev, u8 val)
3408{
3409 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3410 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3411
4fc688ce 3412 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3413 WARN_ON(val > dev_priv->rps.max_delay);
3414 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3415
c6a828d3 3416 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3417 return;
3418
dd75fdc8
CW		 3419 gen6_set_rps_thresholds(dev_priv, val);
3420
92bd1bf0
RV		 3421 if (IS_HASWELL(dev))
3422 I915_WRITE(GEN6_RPNSWREQ,
3423 HSW_FREQUENCY(val));
3424 else
3425 I915_WRITE(GEN6_RPNSWREQ,
3426 GEN6_FREQUENCY(val) |
3427 GEN6_OFFSET(0) |
3428 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3429
3430 /* Make sure we continue to get interrupts
3431 * until we hit the minimum or maximum frequencies.
3432 */
3433 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3434
d5570a72
BW		 3435 POSTING_READ(GEN6_RPNSWREQ);
3436
c6a828d3 3437 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3438
3439 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3440}
3441
b29c19b6
CW		 3442void gen6_rps_idle(struct drm_i915_private *dev_priv)
3443{
3444 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3445 if (dev_priv->rps.enabled) {
3446 if (dev_priv->info->is_valleyview)
3447 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3448 else
3449 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3450 dev_priv->rps.last_adj = 0;
3451 }
b29c19b6
CW		 3452 mutex_unlock(&dev_priv->rps.hw_lock);
3453}
3454
3455void gen6_rps_boost(struct drm_i915_private *dev_priv)
3456{
3457 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3458 if (dev_priv->rps.enabled) {
3459 if (dev_priv->info->is_valleyview)
3460 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3461 else
3462 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3463 dev_priv->rps.last_adj = 0;
3464 }
b29c19b6
CW		 3465 mutex_unlock(&dev_priv->rps.hw_lock);
3466}
3467
80814ae4
VS		 3468/*
3469 * Wait until the previous freq change has completed,
3470 * or the timeout elapsed, and then update our notion
3471 * of the current GPU frequency.
3472 */
3473static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3474{
80814ae4
VS		 3475 u32 pval;
3476
3477 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3478
e8474409
VS		 3479 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3480 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3481
3482 pval >>= 8;
3483
3484 if (pval != dev_priv->rps.cur_delay)
3485 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3486 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3487 dev_priv->rps.cur_delay,
3488 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3489
3490 dev_priv->rps.cur_delay = pval;
3491}
3492
0a073b84
JB		 3493void valleyview_set_rps(struct drm_device *dev, u8 val)
3494{
3495 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3496
3497 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3498
3499 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3500 WARN_ON(val > dev_priv->rps.max_delay);
3501 WARN_ON(val < dev_priv->rps.min_delay);
3502
80814ae4
VS		 3503 vlv_update_rps_cur_delay(dev_priv);
3504
73008b98 3505 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3506 vlv_gpu_freq(dev_priv->mem_freq,
3507 dev_priv->rps.cur_delay),
73008b98
VS		 3508 dev_priv->rps.cur_delay,
3509 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3510
3511 if (val == dev_priv->rps.cur_delay)
3512 return;
3513
ae99258f 3514 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3515
80814ae4 3516 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3517
3518 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3519}
3520
44fc7d5c 3521static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3522{
3523 struct drm_i915_private *dev_priv = dev->dev_private;
3524
2b4e57bd 3525 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3526 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3527 /* Complete PM interrupt masking here doesn't race with the rps work
3528 * item again unmasking PM interrupts because that is using a different
3529 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3530 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3531
59cdb63d 3532 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3533 dev_priv->rps.pm_iir = 0;
59cdb63d 3534 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3535
4848405c 3536 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3537}
3538
44fc7d5c 3539static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3540{
3541 struct drm_i915_private *dev_priv = dev->dev_private;
3542
3543 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3544 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3545
44fc7d5c
DV		 3546 gen6_disable_rps_interrupts(dev);
3547}
3548
3549static void valleyview_disable_rps(struct drm_device *dev)
3550{
3551 struct drm_i915_private *dev_priv = dev->dev_private;
3552
3553 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3554
44fc7d5c 3555 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3556
3557 if (dev_priv->vlv_pctx) {
3558 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3559 dev_priv->vlv_pctx = NULL;
3560 }
d20d4f0c
JB		 3561}
3562
2b4e57bd
ED		 3563int intel_enable_rc6(const struct drm_device *dev)
3564{
eb4926e4
DL		 3565 /* No RC6 before Ironlake */
3566 if (INTEL_INFO(dev)->gen < 5)
3567 return 0;
3568
456470eb 3569 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3570 if (i915_enable_rc6 >= 0)
3571 return i915_enable_rc6;
3572
6567d748
CW		 3573 /* Disable RC6 on Ironlake */
3574 if (INTEL_INFO(dev)->gen == 5)
3575 return 0;
2b4e57bd 3576
456470eb
DV		 3577 if (IS_HASWELL(dev)) {
3578 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3579 return INTEL_RC6_ENABLE;
456470eb 3580 }
2b4e57bd 3581
456470eb 3582 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3583 if (INTEL_INFO(dev)->gen == 6) {
3584 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3585 return INTEL_RC6_ENABLE;
3586 }
456470eb 3587
2b4e57bd
ED		 3588 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3589 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3590}
3591
44fc7d5c
DV		 3592static void gen6_enable_rps_interrupts(struct drm_device *dev)
3593{
3594 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3595 u32 enabled_intrs;
44fc7d5c
DV		 3596
3597 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3598 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3599 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3600 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3601 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3602
fd547d25 3603 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3604 enabled_intrs = GEN6_PM_RPS_EVENTS;
3605
3606 /* IVB and SNB hard hangs on looping batchbuffer
3607 * if GEN6_PM_UP_EI_EXPIRED is masked.
3608 */
3609 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3610 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3611
3612 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3613}
3614
79f5b2c7 3615static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3616{
79f5b2c7 3617 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3618 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3619 u32 rp_state_cap;
3620 u32 gt_perf_status;
31643d54 3621 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3622 u32 gtfifodbg;
2b4e57bd 3623 int rc6_mode;
42c0526c 3624 int i, ret;
2b4e57bd 3625
4fc688ce 3626 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3627
2b4e57bd
ED		 3628 /* Here begins a magic sequence of register writes to enable
3629 * auto-downclocking.
3630 *
3631 * Perhaps there might be some value in exposing these to
3632 * userspace...
3633 */
3634 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3635
3636 /* Clear the DBG now so we don't confuse earlier errors */
3637 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3638 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3639 I915_WRITE(GTFIFODBG, gtfifodbg);
3640 }
3641
3642 gen6_gt_force_wake_get(dev_priv);
3643
7b9e0ae6
CW		 3644 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3645 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3646
31c77388
BW		 3647 /* In units of 50MHz */
3648 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3649 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3650 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3651 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3652 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3653 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3654
2b4e57bd
ED		 3655 /* disable the counters and set deterministic thresholds */
3656 I915_WRITE(GEN6_RC_CONTROL, 0);
3657
3658 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3659 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3660 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3661 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3662 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3663
b4519513
CW		 3664 for_each_ring(ring, dev_priv, i)
3665 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3666
3667 I915_WRITE(GEN6_RC_SLEEP, 0);
3668 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3669 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3670 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3671 else
3672 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3673 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3674 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3675
5a7dc92a 3676 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3677 rc6_mode = intel_enable_rc6(dev_priv->dev);
3678 if (rc6_mode & INTEL_RC6_ENABLE)
3679 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3680
5a7dc92a
ED		 3681 /* We don't use those on Haswell */
3682 if (!IS_HASWELL(dev)) {
3683 if (rc6_mode & INTEL_RC6p_ENABLE)
3684 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3685
5a7dc92a
ED		 3686 if (rc6_mode & INTEL_RC6pp_ENABLE)
3687 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3688 }
2b4e57bd
ED		 3689
3690 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3691 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3692 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3693 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3694
3695 I915_WRITE(GEN6_RC_CONTROL,
3696 rc6_mask |
3697 GEN6_RC_CTL_EI_MODE(1) |
3698 GEN6_RC_CTL_HW_ENABLE);
3699
dd75fdc8
CW		 3700 /* Power down if completely idle for over 50ms */
3701 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3702 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3703
42c0526c 3704 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3705 if (!ret) {
42c0526c
BW		 3706 pcu_mbox = 0;
3707 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3708 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3709 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3710 (dev_priv->rps.max_delay & 0xff) * 50,
3711 (pcu_mbox & 0xff) * 50);
31c77388 3712 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3713 }
3714 } else {
3715 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3716 }
3717
dd75fdc8
CW		 3718 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3719 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3720
44fc7d5c 3721 gen6_enable_rps_interrupts(dev);
2b4e57bd 3722
31643d54
BW		 3723 rc6vids = 0;
3724 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3725 if (IS_GEN6(dev) && ret) {
3726 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3727 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3728 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3729 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3730 rc6vids &= 0xffff00;
3731 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3732 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3733 if (ret)
3734 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3735 }
3736
2b4e57bd 3737 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3738}
3739
c67a470b 3740void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3741{
79f5b2c7 3742 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3743 int min_freq = 15;
3ebecd07
CW		 3744 unsigned int gpu_freq;
3745 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3746 int scaling_factor = 180;
eda79642 3747 struct cpufreq_policy *policy;
2b4e57bd 3748
4fc688ce 3749 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3750
eda79642
BW		 3751 policy = cpufreq_cpu_get(0);
3752 if (policy) {
3753 max_ia_freq = policy->cpuinfo.max_freq;
3754 cpufreq_cpu_put(policy);
3755 } else {
3756 /*
3757 * Default to measured freq if none found, PCU will ensure we
3758 * don't go over
3759 */
2b4e57bd 3760 max_ia_freq = tsc_khz;
eda79642 3761 }
2b4e57bd
ED		 3762
3763 /* Convert from kHz to MHz */
3764 max_ia_freq /= 1000;
3765
f6aca45c
BW		 3766 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK) & 0xf;
3767 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3768 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3769
2b4e57bd
ED		 3770 /*
3771 * For each potential GPU frequency, load a ring frequency we'd like
3772 * to use for memory access. We do this by specifying the IA frequency
3773 * the PCU should use as a reference to determine the ring frequency.
3774 */
c6a828d3 3775 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3776 gpu_freq--) {
c6a828d3 3777 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3778 unsigned int ia_freq = 0, ring_freq = 0;
3779
3780 if (IS_HASWELL(dev)) {
f6aca45c 3781 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3782 ring_freq = max(min_ring_freq, ring_freq);
3783 /* leave ia_freq as the default, chosen by cpufreq */
3784 } else {
3785 /* On older processors, there is no separate ring
3786 * clock domain, so in order to boost the bandwidth
3787 * of the ring, we need to upclock the CPU (ia_freq).
3788 *
3789 * For GPU frequencies less than 750MHz,
3790 * just use the lowest ring freq.
3791 */
3792 if (gpu_freq < min_freq)
3793 ia_freq = 800;
3794 else
3795 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3796 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3797 }
2b4e57bd 3798
42c0526c
BW		 3799 sandybridge_pcode_write(dev_priv,
3800 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3801 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3802 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3803 gpu_freq);
2b4e57bd 3804 }
2b4e57bd
ED		 3805}
3806
0a073b84
JB		 3807int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3808{
3809 u32 val, rp0;
3810
64936258 3811 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3812
3813 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3814 /* Clamp to max */
3815 rp0 = min_t(u32, rp0, 0xea);
3816
3817 return rp0;
3818}
3819
3820static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3821{
3822 u32 val, rpe;
3823
64936258 3824 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3825 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3826 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3827 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3828
3829 return rpe;
3830}
3831
3832int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3833{
64936258 3834 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3835}
3836
c9cddffc
JB		 3837static void valleyview_setup_pctx(struct drm_device *dev)
3838{
3839 struct drm_i915_private *dev_priv = dev->dev_private;
3840 struct drm_i915_gem_object *pctx;
3841 unsigned long pctx_paddr;
3842 u32 pcbr;
3843 int pctx_size = 24*1024;
3844
3845 pcbr = I915_READ(VLV_PCBR);
3846 if (pcbr) {
3847 /* BIOS set it up already, grab the pre-alloc'd space */
3848 int pcbr_offset;
3849
3850 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3851 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3852 pcbr_offset,
190d6cd5 3853 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3854 pctx_size);
3855 goto out;
3856 }
3857
3858 /*
3859 * From the Gunit register HAS:
3860 * The Gfx driver is expected to program this register and ensure
3861 * proper allocation within Gfx stolen memory. For example, this
3862 * register should be programmed such than the PCBR range does not
3863 * overlap with other ranges, such as the frame buffer, protected
3864 * memory, or any other relevant ranges.
3865 */
3866 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3867 if (!pctx) {
3868 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3869 return;
3870 }
3871
3872 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3873 I915_WRITE(VLV_PCBR, pctx_paddr);
3874
3875out:
3876 dev_priv->vlv_pctx = pctx;
3877}
3878
0a073b84
JB		 3879static void valleyview_enable_rps(struct drm_device *dev)
3880{
3881 struct drm_i915_private *dev_priv = dev->dev_private;
3882 struct intel_ring_buffer *ring;
a2b23fe0 3883 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3884 int i;
3885
3886 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3887
3888 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 3889 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
3890 gtfifodbg);
0a073b84
JB		 3891 I915_WRITE(GTFIFODBG, gtfifodbg);
3892 }
3893
c9cddffc
JB		 3894 valleyview_setup_pctx(dev);
3895
0a073b84
JB		 3896 gen6_gt_force_wake_get(dev_priv);
3897
3898 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3899 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3900 I915_WRITE(GEN6_RP_UP_EI, 66000);
3901 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3902
3903 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3904
3905 I915_WRITE(GEN6_RP_CONTROL,
3906 GEN6_RP_MEDIA_TURBO |
3907 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3908 GEN6_RP_MEDIA_IS_GFX |
3909 GEN6_RP_ENABLE |
3910 GEN6_RP_UP_BUSY_AVG |
3911 GEN6_RP_DOWN_IDLE_CONT);
3912
3913 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3914 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3915 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3916
3917 for_each_ring(ring, dev_priv, i)
3918 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3919
3920 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3921
3922 /* allows RC6 residency counter to work */
49798eb2
JB		 3923 I915_WRITE(VLV_COUNTER_CONTROL,
3924 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
3925 VLV_MEDIA_RC6_COUNT_EN |
3926 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0
JB		 3927 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3928 rc6_mode = GEN7_RC_CTL_TO_MODE;
3929 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3930
64936258 3931 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3932 switch ((val >> 6) & 3) {
3933 case 0:
3934 case 1:
3935 dev_priv->mem_freq = 800;
3936 break;
3937 case 2:
3938 dev_priv->mem_freq = 1066;
3939 break;
3940 case 3:
3941 dev_priv->mem_freq = 1333;
3942 break;
3943 }
0a073b84
JB		 3944 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3945
3946 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3947 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3948
0a073b84 3949 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3950 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3951 vlv_gpu_freq(dev_priv->mem_freq,
3952 dev_priv->rps.cur_delay),
3953 dev_priv->rps.cur_delay);
0a073b84
JB		 3954
3955 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3956 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3957 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3958 vlv_gpu_freq(dev_priv->mem_freq,
3959 dev_priv->rps.max_delay),
3960 dev_priv->rps.max_delay);
0a073b84 3961
73008b98
VS		 3962 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3963 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3964 vlv_gpu_freq(dev_priv->mem_freq,
3965 dev_priv->rps.rpe_delay),
3966 dev_priv->rps.rpe_delay);
0a073b84 3967
73008b98
VS		 3968 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3969 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3970 vlv_gpu_freq(dev_priv->mem_freq,
3971 dev_priv->rps.min_delay),
3972 dev_priv->rps.min_delay);
0a073b84 3973
73008b98
VS		 3974 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3975 vlv_gpu_freq(dev_priv->mem_freq,
3976 dev_priv->rps.rpe_delay),
3977 dev_priv->rps.rpe_delay);
0a073b84 3978
73008b98 3979 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3980
44fc7d5c 3981 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3982
3983 gen6_gt_force_wake_put(dev_priv);
3984}
3985
930ebb46 3986void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3987{
3988 struct drm_i915_private *dev_priv = dev->dev_private;
3989
3e373948
DV		 3990 if (dev_priv->ips.renderctx) {
3991 i915_gem_object_unpin(dev_priv->ips.renderctx);
3992 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3993 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3994 }
3995
3e373948
DV		 3996 if (dev_priv->ips.pwrctx) {
3997 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3998 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3999 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4000 }
4001}
4002
930ebb46 4003static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4004{
4005 struct drm_i915_private *dev_priv = dev->dev_private;
4006
4007 if (I915_READ(PWRCTXA)) {
4008 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4009 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4010 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4011 50);
4012
4013 I915_WRITE(PWRCTXA, 0);
4014 POSTING_READ(PWRCTXA);
4015
4016 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4017 POSTING_READ(RSTDBYCTL);
4018 }
2b4e57bd
ED		 4019}
4020
4021static int ironlake_setup_rc6(struct drm_device *dev)
4022{
4023 struct drm_i915_private *dev_priv = dev->dev_private;
4024
3e373948
DV		 4025 if (dev_priv->ips.renderctx == NULL)
4026 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4027 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4028 return -ENOMEM;
4029
3e373948
DV		 4030 if (dev_priv->ips.pwrctx == NULL)
4031 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4032 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4033 ironlake_teardown_rc6(dev);
4034 return -ENOMEM;
4035 }
4036
4037 return 0;
4038}
4039
930ebb46 4040static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4041{
4042 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4043 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4044 bool was_interruptible;
2b4e57bd
ED		 4045 int ret;
4046
4047 /* rc6 disabled by default due to repeated reports of hanging during
4048 * boot and resume.
4049 */
4050 if (!intel_enable_rc6(dev))
4051 return;
4052
79f5b2c7
DV		 4053 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4054
2b4e57bd 4055 ret = ironlake_setup_rc6(dev);
79f5b2c7 4056 if (ret)
2b4e57bd 4057 return;
2b4e57bd 4058
3e960501
CW		 4059 was_interruptible = dev_priv->mm.interruptible;
4060 dev_priv->mm.interruptible = false;
4061
2b4e57bd
ED		 4062 /*
4063 * GPU can automatically power down the render unit if given a page
4064 * to save state.
4065 */
6d90c952 4066 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4067 if (ret) {
4068 ironlake_teardown_rc6(dev);
3e960501 4069 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4070 return;
4071 }
4072
6d90c952
DV		 4073 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4074 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4075 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4076 MI_MM_SPACE_GTT |
4077 MI_SAVE_EXT_STATE_EN |
4078 MI_RESTORE_EXT_STATE_EN |
4079 MI_RESTORE_INHIBIT);
4080 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4081 intel_ring_emit(ring, MI_NOOP);
4082 intel_ring_emit(ring, MI_FLUSH);
4083 intel_ring_advance(ring);
2b4e57bd
ED		 4084
4085 /*
4086 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4087 * does an implicit flush, combined with MI_FLUSH above, it should be
4088 * safe to assume that renderctx is valid
4089 */
3e960501
CW		 4090 ret = intel_ring_idle(ring);
4091 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4092 if (ret) {
def27a58 4093 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4094 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4095 return;
4096 }
4097
f343c5f6 4098 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4099 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 4100}
4101
dde18883
ED		 4102static unsigned long intel_pxfreq(u32 vidfreq)
4103{
4104 unsigned long freq;
4105 int div = (vidfreq & 0x3f0000) >> 16;
4106 int post = (vidfreq & 0x3000) >> 12;
4107 int pre = (vidfreq & 0x7);
4108
4109 if (!pre)
4110 return 0;
4111
4112 freq = ((div * 133333) / ((1<<post) * pre));
4113
4114 return freq;
4115}
4116
eb48eb00
DV		 4117static const struct cparams {
4118 u16 i;
4119 u16 t;
4120 u16 m;
4121 u16 c;
4122} cparams[] = {
4123 { 1, 1333, 301, 28664 },
4124 { 1, 1066, 294, 24460 },
4125 { 1, 800, 294, 25192 },
4126 { 0, 1333, 276, 27605 },
4127 { 0, 1066, 276, 27605 },
4128 { 0, 800, 231, 23784 },
4129};
4130
f531dcb2 4131static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4132{
4133 u64 total_count, diff, ret;
4134 u32 count1, count2, count3, m = 0, c = 0;
4135 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4136 int i;
4137
02d71956
DV		 4138 assert_spin_locked(&mchdev_lock);
4139
20e4d407 4140 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4141
4142 /* Prevent division-by-zero if we are asking too fast.
4143 * Also, we don't get interesting results if we are polling
4144 * faster than once in 10ms, so just return the saved value
4145 * in such cases.
4146 */
4147 if (diff1 <= 10)
20e4d407 4148 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4149
4150 count1 = I915_READ(DMIEC);
4151 count2 = I915_READ(DDREC);
4152 count3 = I915_READ(CSIEC);
4153
4154 total_count = count1 + count2 + count3;
4155
4156 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4157 if (total_count < dev_priv->ips.last_count1) {
4158 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4159 diff += total_count;
4160 } else {
20e4d407 4161 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4162 }
4163
4164 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4165 if (cparams[i].i == dev_priv->ips.c_m &&
4166 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4167 m = cparams[i].m;
4168 c = cparams[i].c;
4169 break;
4170 }
4171 }
4172
4173 diff = div_u64(diff, diff1);
4174 ret = ((m * diff) + c);
4175 ret = div_u64(ret, 10);
4176
20e4d407
DV		 4177 dev_priv->ips.last_count1 = total_count;
4178 dev_priv->ips.last_time1 = now;
eb48eb00 4179
20e4d407 4180 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4181
4182 return ret;
4183}
4184
f531dcb2
CW		 4185unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4186{
4187 unsigned long val;
4188
4189 if (dev_priv->info->gen != 5)
4190 return 0;
4191
4192 spin_lock_irq(&mchdev_lock);
4193
4194 val = __i915_chipset_val(dev_priv);
4195
4196 spin_unlock_irq(&mchdev_lock);
4197
4198 return val;
4199}
4200
eb48eb00
DV		 4201unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4202{
4203 unsigned long m, x, b;
4204 u32 tsfs;
4205
4206 tsfs = I915_READ(TSFS);
4207
4208 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4209 x = I915_READ8(TR1);
4210
4211 b = tsfs & TSFS_INTR_MASK;
4212
4213 return ((m * x) / 127) - b;
4214}
4215
4216static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4217{
4218 static const struct v_table {
4219 u16 vd; /* in .1 mil */
4220 u16 vm; /* in .1 mil */
4221 } v_table[] = {
4222 { 0, 0, },
4223 { 375, 0, },
4224 { 500, 0, },
4225 { 625, 0, },
4226 { 750, 0, },
4227 { 875, 0, },
4228 { 1000, 0, },
4229 { 1125, 0, },
4230 { 4125, 3000, },
4231 { 4125, 3000, },
4232 { 4125, 3000, },
4233 { 4125, 3000, },
4234 { 4125, 3000, },
4235 { 4125, 3000, },
4236 { 4125, 3000, },
4237 { 4125, 3000, },
4238 { 4125, 3000, },
4239 { 4125, 3000, },
4240 { 4125, 3000, },
4241 { 4125, 3000, },
4242 { 4125, 3000, },
4243 { 4125, 3000, },
4244 { 4125, 3000, },
4245 { 4125, 3000, },
4246 { 4125, 3000, },
4247 { 4125, 3000, },
4248 { 4125, 3000, },
4249 { 4125, 3000, },
4250 { 4125, 3000, },
4251 { 4125, 3000, },
4252 { 4125, 3000, },
4253 { 4125, 3000, },
4254 { 4250, 3125, },
4255 { 4375, 3250, },
4256 { 4500, 3375, },
4257 { 4625, 3500, },
4258 { 4750, 3625, },
4259 { 4875, 3750, },
4260 { 5000, 3875, },
4261 { 5125, 4000, },
4262 { 5250, 4125, },
4263 { 5375, 4250, },
4264 { 5500, 4375, },
4265 { 5625, 4500, },
4266 { 5750, 4625, },
4267 { 5875, 4750, },
4268 { 6000, 4875, },
4269 { 6125, 5000, },
4270 { 6250, 5125, },
4271 { 6375, 5250, },
4272 { 6500, 5375, },
4273 { 6625, 5500, },
4274 { 6750, 5625, },
4275 { 6875, 5750, },
4276 { 7000, 5875, },
4277 { 7125, 6000, },
4278 { 7250, 6125, },
4279 { 7375, 6250, },
4280 { 7500, 6375, },
4281 { 7625, 6500, },
4282 { 7750, 6625, },
4283 { 7875, 6750, },
4284 { 8000, 6875, },
4285 { 8125, 7000, },
4286 { 8250, 7125, },
4287 { 8375, 7250, },
4288 { 8500, 7375, },
4289 { 8625, 7500, },
4290 { 8750, 7625, },
4291 { 8875, 7750, },
4292 { 9000, 7875, },
4293 { 9125, 8000, },
4294 { 9250, 8125, },
4295 { 9375, 8250, },
4296 { 9500, 8375, },
4297 { 9625, 8500, },
4298 { 9750, 8625, },
4299 { 9875, 8750, },
4300 { 10000, 8875, },
4301 { 10125, 9000, },
4302 { 10250, 9125, },
4303 { 10375, 9250, },
4304 { 10500, 9375, },
4305 { 10625, 9500, },
4306 { 10750, 9625, },
4307 { 10875, 9750, },
4308 { 11000, 9875, },
4309 { 11125, 10000, },
4310 { 11250, 10125, },
4311 { 11375, 10250, },
4312 { 11500, 10375, },
4313 { 11625, 10500, },
4314 { 11750, 10625, },
4315 { 11875, 10750, },
4316 { 12000, 10875, },
4317 { 12125, 11000, },
4318 { 12250, 11125, },
4319 { 12375, 11250, },
4320 { 12500, 11375, },
4321 { 12625, 11500, },
4322 { 12750, 11625, },
4323 { 12875, 11750, },
4324 { 13000, 11875, },
4325 { 13125, 12000, },
4326 { 13250, 12125, },
4327 { 13375, 12250, },
4328 { 13500, 12375, },
4329 { 13625, 12500, },
4330 { 13750, 12625, },
4331 { 13875, 12750, },
4332 { 14000, 12875, },
4333 { 14125, 13000, },
4334 { 14250, 13125, },
4335 { 14375, 13250, },
4336 { 14500, 13375, },
4337 { 14625, 13500, },
4338 { 14750, 13625, },
4339 { 14875, 13750, },
4340 { 15000, 13875, },
4341 { 15125, 14000, },
4342 { 15250, 14125, },
4343 { 15375, 14250, },
4344 { 15500, 14375, },
4345 { 15625, 14500, },
4346 { 15750, 14625, },
4347 { 15875, 14750, },
4348 { 16000, 14875, },
4349 { 16125, 15000, },
4350 };
4351 if (dev_priv->info->is_mobile)
4352 return v_table[pxvid].vm;
4353 else
4354 return v_table[pxvid].vd;
4355}
4356
02d71956 4357static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4358{
4359 struct timespec now, diff1;
4360 u64 diff;
4361 unsigned long diffms;
4362 u32 count;
4363
02d71956 4364 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4365
4366 getrawmonotonic(&now);
20e4d407 4367 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4368
4369 /* Don't divide by 0 */
4370 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4371 if (!diffms)
4372 return;
4373
4374 count = I915_READ(GFXEC);
4375
20e4d407
DV		 4376 if (count < dev_priv->ips.last_count2) {
4377 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4378 diff += count;
4379 } else {
20e4d407 4380 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4381 }
4382
20e4d407
DV		 4383 dev_priv->ips.last_count2 = count;
4384 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4385
4386 /* More magic constants... */
4387 diff = diff * 1181;
4388 diff = div_u64(diff, diffms * 10);
20e4d407 4389 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4390}
4391
02d71956
DV		 4392void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4393{
4394 if (dev_priv->info->gen != 5)
4395 return;
4396
9270388e 4397 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4398
4399 __i915_update_gfx_val(dev_priv);
4400
9270388e 4401 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4402}
4403
f531dcb2 4404static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4405{
4406 unsigned long t, corr, state1, corr2, state2;
4407 u32 pxvid, ext_v;
4408
02d71956
DV		 4409 assert_spin_locked(&mchdev_lock);
4410
c6a828d3 4411 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4412 pxvid = (pxvid >> 24) & 0x7f;
4413 ext_v = pvid_to_extvid(dev_priv, pxvid);
4414
4415 state1 = ext_v;
4416
4417 t = i915_mch_val(dev_priv);
4418
4419 /* Revel in the empirically derived constants */
4420
4421 /* Correction factor in 1/100000 units */
4422 if (t > 80)
4423 corr = ((t * 2349) + 135940);
4424 else if (t >= 50)
4425 corr = ((t * 964) + 29317);
4426 else /* < 50 */
4427 corr = ((t * 301) + 1004);
4428
4429 corr = corr * ((150142 * state1) / 10000 - 78642);
4430 corr /= 100000;
20e4d407 4431 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4432
4433 state2 = (corr2 * state1) / 10000;
4434 state2 /= 100; /* convert to mW */
4435
02d71956 4436 __i915_update_gfx_val(dev_priv);
eb48eb00 4437
20e4d407 4438 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4439}
4440
f531dcb2
CW		 4441unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4442{
4443 unsigned long val;
4444
4445 if (dev_priv->info->gen != 5)
4446 return 0;
4447
4448 spin_lock_irq(&mchdev_lock);
4449
4450 val = __i915_gfx_val(dev_priv);
4451
4452 spin_unlock_irq(&mchdev_lock);
4453
4454 return val;
4455}
4456
eb48eb00
DV		 4457/**
4458 * i915_read_mch_val - return value for IPS use
4459 *
4460 * Calculate and return a value for the IPS driver to use when deciding whether
4461 * we have thermal and power headroom to increase CPU or GPU power budget.
4462 */
4463unsigned long i915_read_mch_val(void)
4464{
4465 struct drm_i915_private *dev_priv;
4466 unsigned long chipset_val, graphics_val, ret = 0;
4467
9270388e 4468 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4469 if (!i915_mch_dev)
4470 goto out_unlock;
4471 dev_priv = i915_mch_dev;
4472
f531dcb2
CW		 4473 chipset_val = __i915_chipset_val(dev_priv);
4474 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4475
4476 ret = chipset_val + graphics_val;
4477
4478out_unlock:
9270388e 4479 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4480
4481 return ret;
4482}
4483EXPORT_SYMBOL_GPL(i915_read_mch_val);
4484
4485/**
4486 * i915_gpu_raise - raise GPU frequency limit
4487 *
4488 * Raise the limit; IPS indicates we have thermal headroom.
4489 */
4490bool i915_gpu_raise(void)
4491{
4492 struct drm_i915_private *dev_priv;
4493 bool ret = true;
4494
9270388e 4495 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4496 if (!i915_mch_dev) {
4497 ret = false;
4498 goto out_unlock;
4499 }
4500 dev_priv = i915_mch_dev;
4501
20e4d407
DV		 4502 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4503 dev_priv->ips.max_delay--;
eb48eb00
DV		 4504
4505out_unlock:
9270388e 4506 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4507
4508 return ret;
4509}
4510EXPORT_SYMBOL_GPL(i915_gpu_raise);
4511
4512/**
4513 * i915_gpu_lower - lower GPU frequency limit
4514 *
4515 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4516 * frequency maximum.
4517 */
4518bool i915_gpu_lower(void)
4519{
4520 struct drm_i915_private *dev_priv;
4521 bool ret = true;
4522
9270388e 4523 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4524 if (!i915_mch_dev) {
4525 ret = false;
4526 goto out_unlock;
4527 }
4528 dev_priv = i915_mch_dev;
4529
20e4d407
DV		 4530 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4531 dev_priv->ips.max_delay++;
eb48eb00
DV		 4532
4533out_unlock:
9270388e 4534 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4535
4536 return ret;
4537}
4538EXPORT_SYMBOL_GPL(i915_gpu_lower);
4539
4540/**
4541 * i915_gpu_busy - indicate GPU business to IPS
4542 *
4543 * Tell the IPS driver whether or not the GPU is busy.
4544 */
4545bool i915_gpu_busy(void)
4546{
4547 struct drm_i915_private *dev_priv;
f047e395 4548 struct intel_ring_buffer *ring;
eb48eb00 4549 bool ret = false;
f047e395 4550 int i;
eb48eb00 4551
9270388e 4552 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4553 if (!i915_mch_dev)
4554 goto out_unlock;
4555 dev_priv = i915_mch_dev;
4556
f047e395
CW		 4557 for_each_ring(ring, dev_priv, i)
4558 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4559
4560out_unlock:
9270388e 4561 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4562
4563 return ret;
4564}
4565EXPORT_SYMBOL_GPL(i915_gpu_busy);
4566
4567/**
4568 * i915_gpu_turbo_disable - disable graphics turbo
4569 *
4570 * Disable graphics turbo by resetting the max frequency and setting the
4571 * current frequency to the default.
4572 */
4573bool i915_gpu_turbo_disable(void)
4574{
4575 struct drm_i915_private *dev_priv;
4576 bool ret = true;
4577
9270388e 4578 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4579 if (!i915_mch_dev) {
4580 ret = false;
4581 goto out_unlock;
4582 }
4583 dev_priv = i915_mch_dev;
4584
20e4d407 4585 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4586
20e4d407 4587 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4588 ret = false;
4589
4590out_unlock:
9270388e 4591 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4592
4593 return ret;
4594}
4595EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4596
4597/**
4598 * Tells the intel_ips driver that the i915 driver is now loaded, if
4599 * IPS got loaded first.
4600 *
4601 * This awkward dance is so that neither module has to depend on the
4602 * other in order for IPS to do the appropriate communication of
4603 * GPU turbo limits to i915.
4604 */
4605static void
4606ips_ping_for_i915_load(void)
4607{
4608 void (*link)(void);
4609
4610 link = symbol_get(ips_link_to_i915_driver);
4611 if (link) {
4612 link();
4613 symbol_put(ips_link_to_i915_driver);
4614 }
4615}
4616
4617void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4618{
02d71956
DV		 4619 /* We only register the i915 ips part with intel-ips once everything is
4620 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4621 spin_lock_irq(&mchdev_lock);
eb48eb00 4622 i915_mch_dev = dev_priv;
9270388e 4623 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4624
4625 ips_ping_for_i915_load();
4626}
4627
4628void intel_gpu_ips_teardown(void)
4629{
9270388e 4630 spin_lock_irq(&mchdev_lock);
eb48eb00 4631 i915_mch_dev = NULL;
9270388e 4632 spin_unlock_irq(&mchdev_lock);
eb48eb00 4633}
8090c6b9 4634static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4635{
4636 struct drm_i915_private *dev_priv = dev->dev_private;
4637 u32 lcfuse;
4638 u8 pxw[16];
4639 int i;
4640
4641 /* Disable to program */
4642 I915_WRITE(ECR, 0);
4643 POSTING_READ(ECR);
4644
4645 /* Program energy weights for various events */
4646 I915_WRITE(SDEW, 0x15040d00);
4647 I915_WRITE(CSIEW0, 0x007f0000);
4648 I915_WRITE(CSIEW1, 0x1e220004);
4649 I915_WRITE(CSIEW2, 0x04000004);
4650
4651 for (i = 0; i < 5; i++)
4652 I915_WRITE(PEW + (i * 4), 0);
4653 for (i = 0; i < 3; i++)
4654 I915_WRITE(DEW + (i * 4), 0);
4655
4656 /* Program P-state weights to account for frequency power adjustment */
4657 for (i = 0; i < 16; i++) {
4658 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4659 unsigned long freq = intel_pxfreq(pxvidfreq);
4660 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4661 PXVFREQ_PX_SHIFT;
4662 unsigned long val;
4663
4664 val = vid * vid;
4665 val *= (freq / 1000);
4666 val *= 255;
4667 val /= (127*127*900);
4668 if (val > 0xff)
4669 DRM_ERROR("bad pxval: %ld\n", val);
4670 pxw[i] = val;
4671 }
4672 /* Render standby states get 0 weight */
4673 pxw[14] = 0;
4674 pxw[15] = 0;
4675
4676 for (i = 0; i < 4; i++) {
4677 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4678 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4679 I915_WRITE(PXW + (i * 4), val);
4680 }
4681
4682 /* Adjust magic regs to magic values (more experimental results) */
4683 I915_WRITE(OGW0, 0);
4684 I915_WRITE(OGW1, 0);
4685 I915_WRITE(EG0, 0x00007f00);
4686 I915_WRITE(EG1, 0x0000000e);
4687 I915_WRITE(EG2, 0x000e0000);
4688 I915_WRITE(EG3, 0x68000300);
4689 I915_WRITE(EG4, 0x42000000);
4690 I915_WRITE(EG5, 0x00140031);
4691 I915_WRITE(EG6, 0);
4692 I915_WRITE(EG7, 0);
4693
4694 for (i = 0; i < 8; i++)
4695 I915_WRITE(PXWL + (i * 4), 0);
4696
4697 /* Enable PMON + select events */
4698 I915_WRITE(ECR, 0x80000019);
4699
4700 lcfuse = I915_READ(LCFUSE02);
4701
20e4d407 4702 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4703}
4704
8090c6b9
DV		 4705void intel_disable_gt_powersave(struct drm_device *dev)
4706{
1a01ab3b
JB		 4707 struct drm_i915_private *dev_priv = dev->dev_private;
4708
fd0c0642
DV		 4709 /* Interrupts should be disabled already to avoid re-arming. */
4710 WARN_ON(dev->irq_enabled);
4711
930ebb46 4712 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4713 ironlake_disable_drps(dev);
930ebb46 4714 ironlake_disable_rc6(dev);
0a073b84 4715 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4716 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4717 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4718 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4719 if (IS_VALLEYVIEW(dev))
4720 valleyview_disable_rps(dev);
4721 else
4722 gen6_disable_rps(dev);
c0951f0c 4723 dev_priv->rps.enabled = false;
4fc688ce 4724 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4725 }
8090c6b9
DV		 4726}
4727
1a01ab3b
JB		 4728static void intel_gen6_powersave_work(struct work_struct *work)
4729{
4730 struct drm_i915_private *dev_priv =
4731 container_of(work, struct drm_i915_private,
4732 rps.delayed_resume_work.work);
4733 struct drm_device *dev = dev_priv->dev;
4734
4fc688ce 4735 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4736
4737 if (IS_VALLEYVIEW(dev)) {
4738 valleyview_enable_rps(dev);
4739 } else {
4740 gen6_enable_rps(dev);
4741 gen6_update_ring_freq(dev);
4742 }
c0951f0c 4743 dev_priv->rps.enabled = true;
4fc688ce 4744 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4745}
4746
8090c6b9
DV		 4747void intel_enable_gt_powersave(struct drm_device *dev)
4748{
1a01ab3b
JB		 4749 struct drm_i915_private *dev_priv = dev->dev_private;
4750
8090c6b9
DV		 4751 if (IS_IRONLAKE_M(dev)) {
4752 ironlake_enable_drps(dev);
4753 ironlake_enable_rc6(dev);
4754 intel_init_emon(dev);
0a073b84 4755 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4756 /*
4757 * PCU communication is slow and this doesn't need to be
4758 * done at any specific time, so do this out of our fast path
4759 * to make resume and init faster.
4760 */
4761 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4762 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4763 }
4764}
4765
3107bd48
DV		 4766static void ibx_init_clock_gating(struct drm_device *dev)
4767{
4768 struct drm_i915_private *dev_priv = dev->dev_private;
4769
4770 /*
4771 * On Ibex Peak and Cougar Point, we need to disable clock
4772 * gating for the panel power sequencer or it will fail to
4773 * start up when no ports are active.
4774 */
4775 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4776}
4777
0e088b8f
VS		 4778static void g4x_disable_trickle_feed(struct drm_device *dev)
4779{
4780 struct drm_i915_private *dev_priv = dev->dev_private;
4781 int pipe;
4782
4783 for_each_pipe(pipe) {
4784 I915_WRITE(DSPCNTR(pipe),
4785 I915_READ(DSPCNTR(pipe)) |
4786 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4787 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4788 }
4789}
4790
1fa61106 4791static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4792{
4793 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4794 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4795
f1e8fa56
DL		 4796 /*
4797 * Required for FBC
4798 * WaFbcDisableDpfcClockGating:ilk
4799 */
4d47e4f5
DL		 4800 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4801 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4802 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4803
4804 I915_WRITE(PCH_3DCGDIS0,
4805 MARIUNIT_CLOCK_GATE_DISABLE |
4806 SVSMUNIT_CLOCK_GATE_DISABLE);
4807 I915_WRITE(PCH_3DCGDIS1,
4808 VFMUNIT_CLOCK_GATE_DISABLE);
4809
6f1d69b0
ED		 4810 /*
4811 * According to the spec the following bits should be set in
4812 * order to enable memory self-refresh
4813 * The bit 22/21 of 0x42004
4814 * The bit 5 of 0x42020
4815 * The bit 15 of 0x45000
4816 */
4817 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4818 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4819 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4820 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4821 I915_WRITE(DISP_ARB_CTL,
4822 (I915_READ(DISP_ARB_CTL) |
4823 DISP_FBC_WM_DIS));
4824 I915_WRITE(WM3_LP_ILK, 0);
4825 I915_WRITE(WM2_LP_ILK, 0);
4826 I915_WRITE(WM1_LP_ILK, 0);
4827
4828 /*
4829 * Based on the document from hardware guys the following bits
4830 * should be set unconditionally in order to enable FBC.
4831 * The bit 22 of 0x42000
4832 * The bit 22 of 0x42004
4833 * The bit 7,8,9 of 0x42020.
4834 */
4835 if (IS_IRONLAKE_M(dev)) {
4bb35334 4836 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4837 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4838 I915_READ(ILK_DISPLAY_CHICKEN1) |
4839 ILK_FBCQ_DIS);
4840 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4841 I915_READ(ILK_DISPLAY_CHICKEN2) |
4842 ILK_DPARB_GATE);
6f1d69b0
ED		 4843 }
4844
4d47e4f5
DL		 4845 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4846
6f1d69b0
ED		 4847 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4848 I915_READ(ILK_DISPLAY_CHICKEN2) |
4849 ILK_ELPIN_409_SELECT);
4850 I915_WRITE(_3D_CHICKEN2,
4851 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4852 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4853
ecdb4eb7 4854 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4855 I915_WRITE(CACHE_MODE_0,
4856 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4857
0e088b8f 4858 g4x_disable_trickle_feed(dev);
bdad2b2f 4859
3107bd48
DV		 4860 ibx_init_clock_gating(dev);
4861}
4862
4863static void cpt_init_clock_gating(struct drm_device *dev)
4864{
4865 struct drm_i915_private *dev_priv = dev->dev_private;
4866 int pipe;
3f704fa2 4867 uint32_t val;
3107bd48
DV		 4868
4869 /*
4870 * On Ibex Peak and Cougar Point, we need to disable clock
4871 * gating for the panel power sequencer or it will fail to
4872 * start up when no ports are active.
4873 */
4874 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4875 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4876 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4877 /* The below fixes the weird display corruption, a few pixels shifted
4878 * downward, on (only) LVDS of some HP laptops with IVY.
4879 */
3f704fa2 4880 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4881 val = I915_READ(TRANS_CHICKEN2(pipe));
4882 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4883 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4884 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4885 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4886 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4887 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4888 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4889 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4890 }
3107bd48
DV		 4891 /* WADP0ClockGatingDisable */
4892 for_each_pipe(pipe) {
4893 I915_WRITE(TRANS_CHICKEN1(pipe),
4894 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4895 }
6f1d69b0
ED		 4896}
4897
1d7aaa0c
DV		 4898static void gen6_check_mch_setup(struct drm_device *dev)
4899{
4900 struct drm_i915_private *dev_priv = dev->dev_private;
4901 uint32_t tmp;
4902
4903 tmp = I915_READ(MCH_SSKPD);
4904 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4905 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4906 DRM_INFO("This can cause pipe underruns and display issues.\n");
4907 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4908 }
4909}
4910
1fa61106 4911static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4912{
4913 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4914 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4915
231e54f6 4916 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4917
4918 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4919 I915_READ(ILK_DISPLAY_CHICKEN2) |
4920 ILK_ELPIN_409_SELECT);
4921
ecdb4eb7 4922 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4923 I915_WRITE(_3D_CHICKEN,
4924 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4925
ecdb4eb7 4926 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4927 if (IS_SNB_GT1(dev))
4928 I915_WRITE(GEN6_GT_MODE,
4929 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4930
6f1d69b0
ED		 4931 I915_WRITE(WM3_LP_ILK, 0);
4932 I915_WRITE(WM2_LP_ILK, 0);
4933 I915_WRITE(WM1_LP_ILK, 0);
4934
6f1d69b0 4935 I915_WRITE(CACHE_MODE_0,
50743298 4936 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4937
4938 I915_WRITE(GEN6_UCGCTL1,
4939 I915_READ(GEN6_UCGCTL1) |
4940 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4941 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4942
4943 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4944 * gating disable must be set. Failure to set it results in
4945 * flickering pixels due to Z write ordering failures after
4946 * some amount of runtime in the Mesa "fire" demo, and Unigine
4947 * Sanctuary and Tropics, and apparently anything else with
4948 * alpha test or pixel discard.
4949 *
4950 * According to the spec, bit 11 (RCCUNIT) must also be set,
4951 * but we didn't debug actual testcases to find it out.
0f846f81 4952 *
ecdb4eb7
DL		 4953 * Also apply WaDisableVDSUnitClockGating:snb and
4954 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4955 */
4956 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4957 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4958 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4959 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4960
4961 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4962 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4963 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4964
4965 /*
4966 * According to the spec the following bits should be
4967 * set in order to enable memory self-refresh and fbc:
4968 * The bit21 and bit22 of 0x42000
4969 * The bit21 and bit22 of 0x42004
4970 * The bit5 and bit7 of 0x42020
4971 * The bit14 of 0x70180
4972 * The bit14 of 0x71180
4bb35334
DL		 4973 *
4974 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4975 */
4976 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4977 I915_READ(ILK_DISPLAY_CHICKEN1) |
4978 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4979 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4980 I915_READ(ILK_DISPLAY_CHICKEN2) |
4981 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4982 I915_WRITE(ILK_DSPCLK_GATE_D,
4983 I915_READ(ILK_DSPCLK_GATE_D) |
4984 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4985 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4986
0e088b8f 4987 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4988
4989 /* The default value should be 0x200 according to docs, but the two
4990 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4991 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4992 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4993
4994 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4995
4996 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4997}
4998
4999static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5000{
5001 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5002
5003 reg &= ~GEN7_FF_SCHED_MASK;
5004 reg |= GEN7_FF_TS_SCHED_HW;
5005 reg |= GEN7_FF_VS_SCHED_HW;
5006 reg |= GEN7_FF_DS_SCHED_HW;
5007
41c0b3a8
BW		 5008 if (IS_HASWELL(dev_priv->dev))
5009 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5010
6f1d69b0
ED		 5011 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5012}
5013
17a303ec
PZ		 5014static void lpt_init_clock_gating(struct drm_device *dev)
5015{
5016 struct drm_i915_private *dev_priv = dev->dev_private;
5017
5018 /*
5019 * TODO: this bit should only be enabled when really needed, then
5020 * disabled when not needed anymore in order to save power.
5021 */
5022 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5023 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5024 I915_READ(SOUTH_DSPCLK_GATE_D) |
5025 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5026
5027 /* WADPOClockGatingDisable:hsw */
5028 I915_WRITE(_TRANSA_CHICKEN1,
5029 I915_READ(_TRANSA_CHICKEN1) |
5030 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5031}
5032
7d708ee4
ID		 5033static void lpt_suspend_hw(struct drm_device *dev)
5034{
5035 struct drm_i915_private *dev_priv = dev->dev_private;
5036
5037 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5038 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5039
5040 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5041 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5042 }
5043}
5044
cad2a2d7
ED		 5045static void haswell_init_clock_gating(struct drm_device *dev)
5046{
5047 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5048
5049 I915_WRITE(WM3_LP_ILK, 0);
5050 I915_WRITE(WM2_LP_ILK, 0);
5051 I915_WRITE(WM1_LP_ILK, 0);
5052
5053 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5054 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5055 */
5056 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5057
ecdb4eb7 5058 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5059 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5060 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5061
ecdb4eb7 5062 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5063 I915_WRITE(GEN7_L3CNTLREG1,
5064 GEN7_WA_FOR_GEN7_L3_CONTROL);
5065 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5066 GEN7_WA_L3_CHICKEN_MODE);
5067
ecdb4eb7 5068 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5069 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5070 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5071 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5072
ecdb4eb7 5073 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5074 gen7_setup_fixed_func_scheduler(dev_priv);
5075
ecdb4eb7 5076 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5077 I915_WRITE(CACHE_MODE_1,
5078 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5079
ecdb4eb7 5080 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5081 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5082
90a88643
PZ		 5083 /* WaRsPkgCStateDisplayPMReq:hsw */
5084 I915_WRITE(CHICKEN_PAR1_1,
5085 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5086
17a303ec 5087 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5088}
5089
1fa61106 5090static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5091{
5092 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5093 uint32_t snpcr;
6f1d69b0 5094
6f1d69b0
ED		 5095 I915_WRITE(WM3_LP_ILK, 0);
5096 I915_WRITE(WM2_LP_ILK, 0);
5097 I915_WRITE(WM1_LP_ILK, 0);
5098
231e54f6 5099 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5100
ecdb4eb7 5101 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5102 I915_WRITE(_3D_CHICKEN3,
5103 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5104
ecdb4eb7 5105 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5106 I915_WRITE(IVB_CHICKEN3,
5107 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5108 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5109
ecdb4eb7 5110 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5111 if (IS_IVB_GT1(dev))
5112 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5113 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5114 else
5115 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5116 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5117
ecdb4eb7 5118 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5119 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5120 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5121
ecdb4eb7 5122 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5123 I915_WRITE(GEN7_L3CNTLREG1,
5124 GEN7_WA_FOR_GEN7_L3_CONTROL);
5125 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5126 GEN7_WA_L3_CHICKEN_MODE);
5127 if (IS_IVB_GT1(dev))
5128 I915_WRITE(GEN7_ROW_CHICKEN2,
5129 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5130 else
5131 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5132 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5133
6f1d69b0 5134
ecdb4eb7 5135 /* WaForceL3Serialization:ivb */
61939d97
JB		 5136 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5137 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5138
0f846f81
JB		 5139 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5140 * gating disable must be set. Failure to set it results in
5141 * flickering pixels due to Z write ordering failures after
5142 * some amount of runtime in the Mesa "fire" demo, and Unigine
5143 * Sanctuary and Tropics, and apparently anything else with
5144 * alpha test or pixel discard.
5145 *
5146 * According to the spec, bit 11 (RCCUNIT) must also be set,
5147 * but we didn't debug actual testcases to find it out.
5148 *
5149 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5150 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5151 */
5152 I915_WRITE(GEN6_UCGCTL2,
5153 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5154 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5155
ecdb4eb7 5156 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5157 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5158 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5159 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5160
0e088b8f 5161 g4x_disable_trickle_feed(dev);
6f1d69b0 5162
ecdb4eb7 5163 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5164 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5165
ecdb4eb7 5166 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5167 I915_WRITE(CACHE_MODE_1,
5168 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5169
5170 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5171 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5172 snpcr |= GEN6_MBC_SNPCR_MED;
5173 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5174
ab5c608b
BW		 5175 if (!HAS_PCH_NOP(dev))
5176 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5177
5178 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5179}
5180
1fa61106 5181static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5182{
5183 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5184
d7fe0cc0 5185 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5186
ecdb4eb7 5187 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5188 I915_WRITE(_3D_CHICKEN3,
5189 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5190
ecdb4eb7 5191 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5192 I915_WRITE(IVB_CHICKEN3,
5193 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5194 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5195
ecdb4eb7 5196 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5197 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5198 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5199 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5200
ecdb4eb7 5201 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5202 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5203 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5204
ecdb4eb7 5205 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5206 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5207 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5208
ecdb4eb7 5209 /* WaForceL3Serialization:vlv */
61939d97
JB		 5210 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5211 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5212
ecdb4eb7 5213 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5214 I915_WRITE(GEN7_ROW_CHICKEN2,
5215 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5216
ecdb4eb7 5217 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5218 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5219 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5220 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5221
0f846f81
JB		 5222 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5223 * gating disable must be set. Failure to set it results in
5224 * flickering pixels due to Z write ordering failures after
5225 * some amount of runtime in the Mesa "fire" demo, and Unigine
5226 * Sanctuary and Tropics, and apparently anything else with
5227 * alpha test or pixel discard.
5228 *
5229 * According to the spec, bit 11 (RCCUNIT) must also be set,
5230 * but we didn't debug actual testcases to find it out.
5231 *
5232 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5233 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5234 *
ecdb4eb7
DL		 5235 * Also apply WaDisableVDSUnitClockGating:vlv and
5236 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5237 */
5238 I915_WRITE(GEN6_UCGCTL2,
5239 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5240 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5241 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5242 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5243 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5244
e3f33d46
JB		 5245 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5246
e0d8d59b 5247 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5248
6b26c86d
DV		 5249 I915_WRITE(CACHE_MODE_1,
5250 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5251
2d809570 5252 /*
ecdb4eb7 5253 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5254 * Disable clock gating on th GCFG unit to prevent a delay
5255 * in the reporting of vblank events.
5256 */
4e8c84a5
JB		 5257 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5258
5259 /* Conservative clock gating settings for now */
5260 I915_WRITE(0x9400, 0xffffffff);
5261 I915_WRITE(0x9404, 0xffffffff);
5262 I915_WRITE(0x9408, 0xffffffff);
5263 I915_WRITE(0x940c, 0xffffffff);
5264 I915_WRITE(0x9410, 0xffffffff);
5265 I915_WRITE(0x9414, 0xffffffff);
5266 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5267}
5268
1fa61106 5269static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5270{
5271 struct drm_i915_private *dev_priv = dev->dev_private;
5272 uint32_t dspclk_gate;
5273
5274 I915_WRITE(RENCLK_GATE_D1, 0);
5275 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5276 GS_UNIT_CLOCK_GATE_DISABLE |
5277 CL_UNIT_CLOCK_GATE_DISABLE);
5278 I915_WRITE(RAMCLK_GATE_D, 0);
5279 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5280 OVRUNIT_CLOCK_GATE_DISABLE |
5281 OVCUNIT_CLOCK_GATE_DISABLE;
5282 if (IS_GM45(dev))
5283 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5284 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5285
5286 /* WaDisableRenderCachePipelinedFlush */
5287 I915_WRITE(CACHE_MODE_0,
5288 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5289
0e088b8f 5290 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5291}
5292
1fa61106 5293static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5294{
5295 struct drm_i915_private *dev_priv = dev->dev_private;
5296
5297 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5298 I915_WRITE(RENCLK_GATE_D2, 0);
5299 I915_WRITE(DSPCLK_GATE_D, 0);
5300 I915_WRITE(RAMCLK_GATE_D, 0);
5301 I915_WRITE16(DEUC, 0);
20f94967
VS		 5302 I915_WRITE(MI_ARB_STATE,
5303 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5304}
5305
1fa61106 5306static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5307{
5308 struct drm_i915_private *dev_priv = dev->dev_private;
5309
5310 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5311 I965_RCC_CLOCK_GATE_DISABLE |
5312 I965_RCPB_CLOCK_GATE_DISABLE |
5313 I965_ISC_CLOCK_GATE_DISABLE |
5314 I965_FBC_CLOCK_GATE_DISABLE);
5315 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5316 I915_WRITE(MI_ARB_STATE,
5317 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5318}
5319
1fa61106 5320static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5321{
5322 struct drm_i915_private *dev_priv = dev->dev_private;
5323 u32 dstate = I915_READ(D_STATE);
5324
5325 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5326 DSTATE_DOT_CLOCK_GATING;
5327 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5328
5329 if (IS_PINEVIEW(dev))
5330 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5331
5332 /* IIR "flip pending" means done if this bit is set */
5333 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5334}
5335
1fa61106 5336static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5337{
5338 struct drm_i915_private *dev_priv = dev->dev_private;
5339
5340 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5341}
5342
1fa61106 5343static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5344{
5345 struct drm_i915_private *dev_priv = dev->dev_private;
5346
5347 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5348}
5349
6f1d69b0
ED		 5350void intel_init_clock_gating(struct drm_device *dev)
5351{
5352 struct drm_i915_private *dev_priv = dev->dev_private;
5353
5354 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5355}
5356
7d708ee4
ID		 5357void intel_suspend_hw(struct drm_device *dev)
5358{
5359 if (HAS_PCH_LPT(dev))
5360 lpt_suspend_hw(dev);
5361}
5362
15d199ea
PZ		 5363/**
5364 * We should only use the power well if we explicitly asked the hardware to
5365 * enable it, so check if it's enabled and also check if we've requested it to
5366 * be enabled.
5367 */
b97186f0
PZ		 5368bool intel_display_power_enabled(struct drm_device *dev,
5369 enum intel_display_power_domain domain)
15d199ea
PZ		 5370{
5371 struct drm_i915_private *dev_priv = dev->dev_private;
5372
b97186f0
PZ		 5373 if (!HAS_POWER_WELL(dev))
5374 return true;
5375
5376 switch (domain) {
5377 case POWER_DOMAIN_PIPE_A:
5378 case POWER_DOMAIN_TRANSCODER_EDP:
5379 return true;
cdf8dd7f 5380 case POWER_DOMAIN_VGA:
b97186f0
PZ		 5381 case POWER_DOMAIN_PIPE_B:
5382 case POWER_DOMAIN_PIPE_C:
5383 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5384 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5385 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5386 case POWER_DOMAIN_TRANSCODER_A:
5387 case POWER_DOMAIN_TRANSCODER_B:
5388 case POWER_DOMAIN_TRANSCODER_C:
15d199ea 5389 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5390 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
b97186f0
PZ		 5391 default:
5392 BUG();
5393 }
15d199ea
PZ		 5394}
5395
a38911a3 5396static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5397{
5398 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5399 bool is_enabled, enable_requested;
5400 uint32_t tmp;
d0d3e513 5401
fa42e23c 5402 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5403 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5404 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5405
fa42e23c
PZ		 5406 if (enable) {
5407 if (!enable_requested)
6aedd1f5
PZ		 5408 I915_WRITE(HSW_PWR_WELL_DRIVER,
5409 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5410
fa42e23c
PZ		 5411 if (!is_enabled) {
5412 DRM_DEBUG_KMS("Enabling power well\n");
5413 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5414 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5415 DRM_ERROR("Timeout enabling power well\n");
5416 }
5417 } else {
5418 if (enable_requested) {
9dbd8feb
PZ		 5419 unsigned long irqflags;
5420 enum pipe p;
5421
fa42e23c 5422 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5423 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5424 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5425
5426 /*
5427 * After this, the registers on the pipes that are part
5428 * of the power well will become zero, so we have to
5429 * adjust our counters according to that.
5430 *
5431 * FIXME: Should we do this in general in
5432 * drm_vblank_post_modeset?
5433 */
5434 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5435 for_each_pipe(p)
5436 if (p != PIPE_A)
5380e929 5437 dev->vblank[p].last = 0;
9dbd8feb 5438 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5439 }
5440 }
fa42e23c 5441}
d0d3e513 5442
2d66aef5
VS		 5443static void __intel_power_well_get(struct i915_power_well *power_well)
5444{
5445 if (!power_well->count++)
5446 __intel_set_power_well(power_well->device, true);
5447}
5448
5449static void __intel_power_well_put(struct i915_power_well *power_well)
5450{
5451 WARN_ON(!power_well->count);
5452 if (!--power_well->count)
5453 __intel_set_power_well(power_well->device, false);
5454}
5455
6765625e
VS		 5456void intel_display_power_get(struct drm_device *dev,
5457 enum intel_display_power_domain domain)
5458{
5459 struct drm_i915_private *dev_priv = dev->dev_private;
5460 struct i915_power_well *power_well = &dev_priv->power_well;
5461
5462 if (!HAS_POWER_WELL(dev))
5463 return;
5464
5465 switch (domain) {
5466 case POWER_DOMAIN_PIPE_A:
5467 case POWER_DOMAIN_TRANSCODER_EDP:
5468 return;
cdf8dd7f 5469 case POWER_DOMAIN_VGA:
6765625e
VS		 5470 case POWER_DOMAIN_PIPE_B:
5471 case POWER_DOMAIN_PIPE_C:
5472 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5473 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5474 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5475 case POWER_DOMAIN_TRANSCODER_A:
5476 case POWER_DOMAIN_TRANSCODER_B:
5477 case POWER_DOMAIN_TRANSCODER_C:
5478 spin_lock_irq(&power_well->lock);
2d66aef5 5479 __intel_power_well_get(power_well);
6765625e
VS		 5480 spin_unlock_irq(&power_well->lock);
5481 return;
5482 default:
5483 BUG();
5484 }
5485}
5486
5487void intel_display_power_put(struct drm_device *dev,
5488 enum intel_display_power_domain domain)
5489{
5490 struct drm_i915_private *dev_priv = dev->dev_private;
5491 struct i915_power_well *power_well = &dev_priv->power_well;
5492
5493 if (!HAS_POWER_WELL(dev))
5494 return;
5495
5496 switch (domain) {
5497 case POWER_DOMAIN_PIPE_A:
5498 case POWER_DOMAIN_TRANSCODER_EDP:
5499 return;
cdf8dd7f 5500 case POWER_DOMAIN_VGA:
6765625e
VS		 5501 case POWER_DOMAIN_PIPE_B:
5502 case POWER_DOMAIN_PIPE_C:
5503 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5504 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5505 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5506 case POWER_DOMAIN_TRANSCODER_A:
5507 case POWER_DOMAIN_TRANSCODER_B:
5508 case POWER_DOMAIN_TRANSCODER_C:
5509 spin_lock_irq(&power_well->lock);
2d66aef5 5510 __intel_power_well_put(power_well);
6765625e
VS		 5511 spin_unlock_irq(&power_well->lock);
5512 return;
5513 default:
5514 BUG();
5515 }
5516}
5517
a38911a3
WX		 5518static struct i915_power_well *hsw_pwr;
5519
5520/* Display audio driver power well request */
5521void i915_request_power_well(void)
5522{
5523 if (WARN_ON(!hsw_pwr))
5524 return;
5525
5526 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5527 __intel_power_well_get(hsw_pwr);
a38911a3
WX		 5528 spin_unlock_irq(&hsw_pwr->lock);
5529}
5530EXPORT_SYMBOL_GPL(i915_request_power_well);
5531
5532/* Display audio driver power well release */
5533void i915_release_power_well(void)
5534{
5535 if (WARN_ON(!hsw_pwr))
5536 return;
5537
5538 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5539 __intel_power_well_put(hsw_pwr);
a38911a3
WX		 5540 spin_unlock_irq(&hsw_pwr->lock);
5541}
5542EXPORT_SYMBOL_GPL(i915_release_power_well);
5543
5544int i915_init_power_well(struct drm_device *dev)
5545{
5546 struct drm_i915_private *dev_priv = dev->dev_private;
5547
5548 hsw_pwr = &dev_priv->power_well;
5549
5550 hsw_pwr->device = dev;
5551 spin_lock_init(&hsw_pwr->lock);
5552 hsw_pwr->count = 0;
5553
5554 return 0;
5555}
5556
5557void i915_remove_power_well(struct drm_device *dev)
5558{
5559 hsw_pwr = NULL;
5560}
5561
5562void intel_set_power_well(struct drm_device *dev, bool enable)
5563{
5564 struct drm_i915_private *dev_priv = dev->dev_private;
5565 struct i915_power_well *power_well = &dev_priv->power_well;
5566
5567 if (!HAS_POWER_WELL(dev))
5568 return;
5569
5570 if (!i915_disable_power_well && !enable)
5571 return;
5572
5573 spin_lock_irq(&power_well->lock);
9cdb826c
VS		 5574
5575 /*
5576 * This function will only ever contribute one
5577 * to the power well reference count. i915_request
5578 * is what tracks whether we have or have not
5579 * added the one to the reference count.
5580 */
5581 if (power_well->i915_request == enable)
5582 goto out;
5583
a38911a3
WX		 5584 power_well->i915_request = enable;
5585
2d66aef5
VS		 5586 if (enable)
5587 __intel_power_well_get(power_well);
5588 else
5589 __intel_power_well_put(power_well);
a38911a3 5590
9cdb826c
VS		 5591 out:
5592 spin_unlock_irq(&power_well->lock);
5593}
5594
51340990 5595static void intel_resume_power_well(struct drm_device *dev)
9cdb826c
VS		 5596{
5597 struct drm_i915_private *dev_priv = dev->dev_private;
5598 struct i915_power_well *power_well = &dev_priv->power_well;
5599
5600 if (!HAS_POWER_WELL(dev))
5601 return;
5602
5603 spin_lock_irq(&power_well->lock);
5604 __intel_set_power_well(dev, power_well->count > 0);
a38911a3
WX		 5605 spin_unlock_irq(&power_well->lock);
5606}
5607
fa42e23c
PZ		 5608/*
5609 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5610 * when not needed anymore. We have 4 registers that can request the power well
5611 * to be enabled, and it will only be disabled if none of the registers is
5612 * requesting it to be enabled.
d0d3e513 5613 */
fa42e23c 5614void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5615{
5616 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5617
86d52df6 5618 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5619 return;
5620
fa42e23c
PZ		 5621 /* For now, we need the power well to be always enabled. */
5622 intel_set_power_well(dev, true);
9cdb826c 5623 intel_resume_power_well(dev);
d0d3e513 5624
fa42e23c
PZ		 5625 /* We're taking over the BIOS, so clear any requests made by it since
5626 * the driver is in charge now. */
6aedd1f5 5627 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5628 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5629}
5630
c67a470b
PZ		 5631/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5632void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5633{
5634 hsw_disable_package_c8(dev_priv);
5635}
5636
5637void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5638{
5639 hsw_enable_package_c8(dev_priv);
5640}
5641
1fa61106
ED		 5642/* Set up chip specific power management-related functions */
5643void intel_init_pm(struct drm_device *dev)
5644{
5645 struct drm_i915_private *dev_priv = dev->dev_private;
5646
5647 if (I915_HAS_FBC(dev)) {
5648 if (HAS_PCH_SPLIT(dev)) {
5649 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5650 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5651 dev_priv->display.enable_fbc =
5652 gen7_enable_fbc;
5653 else
5654 dev_priv->display.enable_fbc =
5655 ironlake_enable_fbc;
1fa61106
ED		 5656 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5657 } else if (IS_GM45(dev)) {
5658 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5659 dev_priv->display.enable_fbc = g4x_enable_fbc;
5660 dev_priv->display.disable_fbc = g4x_disable_fbc;
5661 } else if (IS_CRESTLINE(dev)) {
5662 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5663 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5664 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5665 }
5666 /* 855GM needs testing */
5667 }
5668
c921aba8
DV		 5669 /* For cxsr */
5670 if (IS_PINEVIEW(dev))
5671 i915_pineview_get_mem_freq(dev);
5672 else if (IS_GEN5(dev))
5673 i915_ironlake_get_mem_freq(dev);
5674
1fa61106
ED		 5675 /* For FIFO watermark updates */
5676 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5677 intel_setup_wm_latency(dev);
5678
1fa61106 5679 if (IS_GEN5(dev)) {
53615a5e
VS		 5680 if (dev_priv->wm.pri_latency[1] &&
5681 dev_priv->wm.spr_latency[1] &&
5682 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5683 dev_priv->display.update_wm = ironlake_update_wm;
5684 else {
5685 DRM_DEBUG_KMS("Failed to get proper latency. "
5686 "Disable CxSR\n");
5687 dev_priv->display.update_wm = NULL;
5688 }
5689 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5690 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5691 if (dev_priv->wm.pri_latency[0] &&
5692 dev_priv->wm.spr_latency[0] &&
5693 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5694 dev_priv->display.update_wm = sandybridge_update_wm;
5695 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5696 } else {
5697 DRM_DEBUG_KMS("Failed to read display plane latency. "
5698 "Disable CxSR\n");
5699 dev_priv->display.update_wm = NULL;
5700 }
5701 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5702 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5703 if (dev_priv->wm.pri_latency[0] &&
5704 dev_priv->wm.spr_latency[0] &&
5705 dev_priv->wm.cur_latency[0]) {
c43d0188 5706 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5707 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5708 } else {
5709 DRM_DEBUG_KMS("Failed to read display plane latency. "
5710 "Disable CxSR\n");
5711 dev_priv->display.update_wm = NULL;
5712 }
5713 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5714 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5715 if (dev_priv->wm.pri_latency[0] &&
5716 dev_priv->wm.spr_latency[0] &&
5717 dev_priv->wm.cur_latency[0]) {
1011d8c4 5718 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5719 dev_priv->display.update_sprite_wm =
5720 haswell_update_sprite_wm;
6b8a5eeb
ED		 5721 } else {
5722 DRM_DEBUG_KMS("Failed to read display plane latency. "
5723 "Disable CxSR\n");
5724 dev_priv->display.update_wm = NULL;
5725 }
cad2a2d7 5726 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5727 } else
5728 dev_priv->display.update_wm = NULL;
5729 } else if (IS_VALLEYVIEW(dev)) {
5730 dev_priv->display.update_wm = valleyview_update_wm;
5731 dev_priv->display.init_clock_gating =
5732 valleyview_init_clock_gating;
1fa61106
ED		 5733 } else if (IS_PINEVIEW(dev)) {
5734 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5735 dev_priv->is_ddr3,
5736 dev_priv->fsb_freq,
5737 dev_priv->mem_freq)) {
5738 DRM_INFO("failed to find known CxSR latency "
5739 "(found ddr%s fsb freq %d, mem freq %d), "
5740 "disabling CxSR\n",
5741 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5742 dev_priv->fsb_freq, dev_priv->mem_freq);
5743 /* Disable CxSR and never update its watermark again */
5744 pineview_disable_cxsr(dev);
5745 dev_priv->display.update_wm = NULL;
5746 } else
5747 dev_priv->display.update_wm = pineview_update_wm;
5748 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5749 } else if (IS_G4X(dev)) {
5750 dev_priv->display.update_wm = g4x_update_wm;
5751 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5752 } else if (IS_GEN4(dev)) {
5753 dev_priv->display.update_wm = i965_update_wm;
5754 if (IS_CRESTLINE(dev))
5755 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5756 else if (IS_BROADWATER(dev))
5757 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5758 } else if (IS_GEN3(dev)) {
5759 dev_priv->display.update_wm = i9xx_update_wm;
5760 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5761 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5762 } else if (IS_I865G(dev)) {
5763 dev_priv->display.update_wm = i830_update_wm;
5764 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5765 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5766 } else if (IS_I85X(dev)) {
5767 dev_priv->display.update_wm = i9xx_update_wm;
5768 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5769 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5770 } else {
5771 dev_priv->display.update_wm = i830_update_wm;
5772 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5773 if (IS_845G(dev))
5774 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5775 else
5776 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5777 }
5778}
5779
42c0526c
BW		 5780int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5781{
4fc688ce 5782 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5783
5784 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5785 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5786 return -EAGAIN;
5787 }
5788
5789 I915_WRITE(GEN6_PCODE_DATA, *val);
5790 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5791
5792 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5793 500)) {
5794 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5795 return -ETIMEDOUT;
5796 }
5797
5798 *val = I915_READ(GEN6_PCODE_DATA);
5799 I915_WRITE(GEN6_PCODE_DATA, 0);
5800
5801 return 0;
5802}
5803
5804int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5805{
4fc688ce 5806 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5807
5808 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5809 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5810 return -EAGAIN;
5811 }
5812
5813 I915_WRITE(GEN6_PCODE_DATA, val);
5814 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5815
5816 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5817 500)) {
5818 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5819 return -ETIMEDOUT;
5820 }
5821
5822 I915_WRITE(GEN6_PCODE_DATA, 0);
5823
5824 return 0;
5825}
a0e4e199 5826
855ba3be
JB		 5827int vlv_gpu_freq(int ddr_freq, int val)
5828{
5829 int mult, base;
5830
5831 switch (ddr_freq) {
5832 case 800:
5833 mult = 20;
5834 base = 120;
5835 break;
5836 case 1066:
5837 mult = 22;
5838 base = 133;
5839 break;
5840 case 1333:
5841 mult = 21;
5842 base = 125;
5843 break;
5844 default:
5845 return -1;
5846 }
5847
5848 return ((val - 0xbd) * mult) + base;
5849}
5850
5851int vlv_freq_opcode(int ddr_freq, int val)
5852{
5853 int mult, base;
5854
5855 switch (ddr_freq) {
5856 case 800:
5857 mult = 20;
5858 base = 120;
5859 break;
5860 case 1066:
5861 mult = 22;
5862 base = 133;
5863 break;
5864 case 1333:
5865 mult = 21;
5866 base = 125;
5867 break;
5868 default:
5869 return -1;
5870 }
5871
5872 val /= mult;
5873 val -= base / mult;
5874 val += 0xbd;
5875
5876 if (val > 0xea)
5877 val = 0xea;
5878
5879 return val;
5880}
5881
907b28c5
CW		 5882void intel_pm_init(struct drm_device *dev)
5883{
5884 struct drm_i915_private *dev_priv = dev->dev_private;
5885
5886 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5887 intel_gen6_powersave_work);
5888}
5889
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