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drm/i915: Improve vlv_gpu_freq() and vlv_freq_opcode()
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
dc39fff7
BW		 35/**
36 * RC6 is a special power stage which allows the GPU to enter an very
37 * low-voltage mode when idle, using down to 0V while at this stage. This
38 * stage is entered automatically when the GPU is idle when RC6 support is
39 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
40 *
41 * There are different RC6 modes available in Intel GPU, which differentiate
42 * among each other with the latency required to enter and leave RC6 and
43 * voltage consumed by the GPU in different states.
44 *
45 * The combination of the following flags define which states GPU is allowed
46 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
47 * RC6pp is deepest RC6. Their support by hardware varies according to the
48 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
49 * which brings the most power savings; deeper states save more power, but
50 * require higher latency to switch to and wake up.
51 */
52#define INTEL_RC6_ENABLE (1<<0)
53#define INTEL_RC6p_ENABLE (1<<1)
54#define INTEL_RC6pp_ENABLE (1<<2)
55
f6750b3c
ED		 56/* FBC, or Frame Buffer Compression, is a technique employed to compress the
57 * framebuffer contents in-memory, aiming at reducing the required bandwidth
58 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 59 *
f6750b3c
ED		 60 * The benefits of FBC are mostly visible with solid backgrounds and
61 * variation-less patterns.
85208be0 62 *
f6750b3c
ED		 63 * FBC-related functionality can be enabled by the means of the
64 * i915.i915_enable_fbc parameter
85208be0
ED		 65 */
66
1fa61106 67static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 68{
69 struct drm_i915_private *dev_priv = dev->dev_private;
70 u32 fbc_ctl;
71
72 /* Disable compression */
73 fbc_ctl = I915_READ(FBC_CONTROL);
74 if ((fbc_ctl & FBC_CTL_EN) == 0)
75 return;
76
77 fbc_ctl &= ~FBC_CTL_EN;
78 I915_WRITE(FBC_CONTROL, fbc_ctl);
79
80 /* Wait for compressing bit to clear */
81 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
82 DRM_DEBUG_KMS("FBC idle timed out\n");
83 return;
84 }
85
86 DRM_DEBUG_KMS("disabled FBC\n");
87}
88
1fa61106 89static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 90{
91 struct drm_device *dev = crtc->dev;
92 struct drm_i915_private *dev_priv = dev->dev_private;
93 struct drm_framebuffer *fb = crtc->fb;
94 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
95 struct drm_i915_gem_object *obj = intel_fb->obj;
96 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
97 int cfb_pitch;
98 int plane, i;
99 u32 fbc_ctl, fbc_ctl2;
100
5c3fe8b0 101 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 102 if (fb->pitches[0] < cfb_pitch)
103 cfb_pitch = fb->pitches[0];
104
105 /* FBC_CTL wants 64B units */
106 cfb_pitch = (cfb_pitch / 64) - 1;
107 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
108
109 /* Clear old tags */
110 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
111 I915_WRITE(FBC_TAG + (i * 4), 0);
112
113 /* Set it up... */
114 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
115 fbc_ctl2 |= plane;
116 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
117 I915_WRITE(FBC_FENCE_OFF, crtc->y);
118
119 /* enable it... */
120 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
121 if (IS_I945GM(dev))
122 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
123 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
124 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
125 fbc_ctl |= obj->fence_reg;
126 I915_WRITE(FBC_CONTROL, fbc_ctl);
127
84f44ce7
VS		 128 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
129 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 130}
131
1fa61106 132static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 133{
134 struct drm_i915_private *dev_priv = dev->dev_private;
135
136 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
137}
138
1fa61106 139static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 140{
141 struct drm_device *dev = crtc->dev;
142 struct drm_i915_private *dev_priv = dev->dev_private;
143 struct drm_framebuffer *fb = crtc->fb;
144 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
145 struct drm_i915_gem_object *obj = intel_fb->obj;
146 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
147 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
148 unsigned long stall_watermark = 200;
149 u32 dpfc_ctl;
150
151 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
152 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
153 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
154
155 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
156 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
157 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
158 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
159
160 /* enable it... */
161 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
162
84f44ce7 163 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 164}
165
1fa61106 166static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 167{
168 struct drm_i915_private *dev_priv = dev->dev_private;
169 u32 dpfc_ctl;
170
171 /* Disable compression */
172 dpfc_ctl = I915_READ(DPFC_CONTROL);
173 if (dpfc_ctl & DPFC_CTL_EN) {
174 dpfc_ctl &= ~DPFC_CTL_EN;
175 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
176
177 DRM_DEBUG_KMS("disabled FBC\n");
178 }
179}
180
1fa61106 181static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 182{
183 struct drm_i915_private *dev_priv = dev->dev_private;
184
185 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
186}
187
188static void sandybridge_blit_fbc_update(struct drm_device *dev)
189{
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 u32 blt_ecoskpd;
192
193 /* Make sure blitter notifies FBC of writes */
194 gen6_gt_force_wake_get(dev_priv);
195 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
196 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
197 GEN6_BLITTER_LOCK_SHIFT;
198 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
199 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
200 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
201 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
202 GEN6_BLITTER_LOCK_SHIFT);
203 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
204 POSTING_READ(GEN6_BLITTER_ECOSKPD);
205 gen6_gt_force_wake_put(dev_priv);
206}
207
1fa61106 208static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 209{
210 struct drm_device *dev = crtc->dev;
211 struct drm_i915_private *dev_priv = dev->dev_private;
212 struct drm_framebuffer *fb = crtc->fb;
213 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
214 struct drm_i915_gem_object *obj = intel_fb->obj;
215 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
216 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
217 unsigned long stall_watermark = 200;
218 u32 dpfc_ctl;
219
220 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
221 dpfc_ctl &= DPFC_RESERVED;
222 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
223 /* Set persistent mode for front-buffer rendering, ala X. */
224 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
225 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
226 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
227
228 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
229 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
230 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
231 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 232 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 233 /* enable it... */
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
235
236 if (IS_GEN6(dev)) {
237 I915_WRITE(SNB_DPFC_CTL_SA,
238 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
239 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
240 sandybridge_blit_fbc_update(dev);
241 }
242
84f44ce7 243 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 244}
245
1fa61106 246static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 247{
248 struct drm_i915_private *dev_priv = dev->dev_private;
249 u32 dpfc_ctl;
250
251 /* Disable compression */
252 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
253 if (dpfc_ctl & DPFC_CTL_EN) {
254 dpfc_ctl &= ~DPFC_CTL_EN;
255 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
256
257 DRM_DEBUG_KMS("disabled FBC\n");
258 }
259}
260
1fa61106 261static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 262{
263 struct drm_i915_private *dev_priv = dev->dev_private;
264
265 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
266}
267
abe959c7
RV		 268static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
269{
270 struct drm_device *dev = crtc->dev;
271 struct drm_i915_private *dev_priv = dev->dev_private;
272 struct drm_framebuffer *fb = crtc->fb;
273 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
274 struct drm_i915_gem_object *obj = intel_fb->obj;
275 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
276
f343c5f6 277 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 278
279 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
280 IVB_DPFC_CTL_FENCE_EN |
281 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
282
891348b2 283 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 284 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 285 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
28554164 286 } else {
7dd23ba0 287 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 288 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
289 HSW_BYPASS_FBC_QUEUE);
891348b2 290 }
b74ea102 291
abe959c7
RV		 292 I915_WRITE(SNB_DPFC_CTL_SA,
293 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
294 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
295
296 sandybridge_blit_fbc_update(dev);
297
298 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
299}
300
85208be0
ED		 301bool intel_fbc_enabled(struct drm_device *dev)
302{
303 struct drm_i915_private *dev_priv = dev->dev_private;
304
305 if (!dev_priv->display.fbc_enabled)
306 return false;
307
308 return dev_priv->display.fbc_enabled(dev);
309}
310
311static void intel_fbc_work_fn(struct work_struct *__work)
312{
313 struct intel_fbc_work *work =
314 container_of(to_delayed_work(__work),
315 struct intel_fbc_work, work);
316 struct drm_device *dev = work->crtc->dev;
317 struct drm_i915_private *dev_priv = dev->dev_private;
318
319 mutex_lock(&dev->struct_mutex);
5c3fe8b0 320 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 321 /* Double check that we haven't switched fb without cancelling
322 * the prior work.
323 */
324 if (work->crtc->fb == work->fb) {
325 dev_priv->display.enable_fbc(work->crtc,
326 work->interval);
327
5c3fe8b0
BW		 328 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
329 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
330 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 331 }
332
5c3fe8b0 333 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 334 }
335 mutex_unlock(&dev->struct_mutex);
336
337 kfree(work);
338}
339
340static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
341{
5c3fe8b0 342 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 343 return;
344
345 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
346
347 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 348 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 349 * entirely asynchronously.
350 */
5c3fe8b0 351 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 352 /* tasklet was killed before being run, clean up */
5c3fe8b0 353 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 354
355 /* Mark the work as no longer wanted so that if it does
356 * wake-up (because the work was already running and waiting
357 * for our mutex), it will discover that is no longer
358 * necessary to run.
359 */
5c3fe8b0 360 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 361}
362
b63fb44c 363static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 364{
365 struct intel_fbc_work *work;
366 struct drm_device *dev = crtc->dev;
367 struct drm_i915_private *dev_priv = dev->dev_private;
368
369 if (!dev_priv->display.enable_fbc)
370 return;
371
372 intel_cancel_fbc_work(dev_priv);
373
b14c5679 374 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 375 if (work == NULL) {
6cdcb5e7 376 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 377 dev_priv->display.enable_fbc(crtc, interval);
378 return;
379 }
380
381 work->crtc = crtc;
382 work->fb = crtc->fb;
383 work->interval = interval;
384 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
385
5c3fe8b0 386 dev_priv->fbc.fbc_work = work;
85208be0 387
85208be0
ED		 388 /* Delay the actual enabling to let pageflipping cease and the
389 * display to settle before starting the compression. Note that
390 * this delay also serves a second purpose: it allows for a
391 * vblank to pass after disabling the FBC before we attempt
392 * to modify the control registers.
393 *
394 * A more complicated solution would involve tracking vblanks
395 * following the termination of the page-flipping sequence
396 * and indeed performing the enable as a co-routine and not
397 * waiting synchronously upon the vblank.
7457d617
DL		 398 *
399 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 400 */
401 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
402}
403
404void intel_disable_fbc(struct drm_device *dev)
405{
406 struct drm_i915_private *dev_priv = dev->dev_private;
407
408 intel_cancel_fbc_work(dev_priv);
409
410 if (!dev_priv->display.disable_fbc)
411 return;
412
413 dev_priv->display.disable_fbc(dev);
5c3fe8b0 414 dev_priv->fbc.plane = -1;
85208be0
ED		 415}
416
29ebf90f
CW		 417static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
418 enum no_fbc_reason reason)
419{
420 if (dev_priv->fbc.no_fbc_reason == reason)
421 return false;
422
423 dev_priv->fbc.no_fbc_reason = reason;
424 return true;
425}
426
85208be0
ED		 427/**
428 * intel_update_fbc - enable/disable FBC as needed
429 * @dev: the drm_device
430 *
431 * Set up the framebuffer compression hardware at mode set time. We
432 * enable it if possible:
433 * - plane A only (on pre-965)
434 * - no pixel mulitply/line duplication
435 * - no alpha buffer discard
436 * - no dual wide
f85da868 437 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 438 *
439 * We can't assume that any compression will take place (worst case),
440 * so the compressed buffer has to be the same size as the uncompressed
441 * one. It also must reside (along with the line length buffer) in
442 * stolen memory.
443 *
444 * We need to enable/disable FBC on a global basis.
445 */
446void intel_update_fbc(struct drm_device *dev)
447{
448 struct drm_i915_private *dev_priv = dev->dev_private;
449 struct drm_crtc *crtc = NULL, *tmp_crtc;
450 struct intel_crtc *intel_crtc;
451 struct drm_framebuffer *fb;
452 struct intel_framebuffer *intel_fb;
453 struct drm_i915_gem_object *obj;
ef644fda 454 const struct drm_display_mode *adjusted_mode;
37327abd 455 unsigned int max_width, max_height;
85208be0 456
29ebf90f
CW		 457 if (!I915_HAS_FBC(dev)) {
458 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 459 return;
29ebf90f 460 }
85208be0 461
29ebf90f
CW		 462 if (!i915_powersave) {
463 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
464 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 465 return;
29ebf90f 466 }
85208be0
ED		 467
468 /*
469 * If FBC is already on, we just have to verify that we can
470 * keep it that way...
471 * Need to disable if:
472 * - more than one pipe is active
473 * - changing FBC params (stride, fence, mode)
474 * - new fb is too large to fit in compressed buffer
475 * - going to an unsupported config (interlace, pixel multiply, etc.)
476 */
477 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 478 if (intel_crtc_active(tmp_crtc) &&
4c445e0e 479 to_intel_crtc(tmp_crtc)->primary_enabled) {
85208be0 480 if (crtc) {
29ebf90f
CW		 481 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
482 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 483 goto out_disable;
484 }
485 crtc = tmp_crtc;
486 }
487 }
488
489 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 490 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
491 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 492 goto out_disable;
493 }
494
495 intel_crtc = to_intel_crtc(crtc);
496 fb = crtc->fb;
497 intel_fb = to_intel_framebuffer(fb);
498 obj = intel_fb->obj;
ef644fda 499 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 500
8a5729a3
DL		 501 if (i915_enable_fbc < 0 &&
502 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 503 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
504 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 505 goto out_disable;
85208be0 506 }
8a5729a3 507 if (!i915_enable_fbc) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
509 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 510 goto out_disable;
511 }
ef644fda
VS		 512 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
513 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 514 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
515 DRM_DEBUG_KMS("mode incompatible with compression, "
516 "disabling\n");
85208be0
ED		 517 goto out_disable;
518 }
f85da868
PZ		 519
520 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 521 max_width = 4096;
522 max_height = 2048;
f85da868 523 } else {
37327abd
VS		 524 max_width = 2048;
525 max_height = 1536;
f85da868 526 }
37327abd
VS		 527 if (intel_crtc->config.pipe_src_w > max_width ||
528 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 529 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
530 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 531 goto out_disable;
532 }
891348b2
RV		 533 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
534 intel_crtc->plane != 0) {
29ebf90f
CW		 535 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
536 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 537 goto out_disable;
538 }
539
540 /* The use of a CPU fence is mandatory in order to detect writes
541 * by the CPU to the scanout and trigger updates to the FBC.
542 */
543 if (obj->tiling_mode != I915_TILING_X ||
544 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 545 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
546 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 547 goto out_disable;
548 }
549
550 /* If the kernel debugger is active, always disable compression */
551 if (in_dbg_master())
552 goto out_disable;
553
11be49eb 554 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 555 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
556 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 557 goto out_disable;
558 }
559
85208be0
ED		 560 /* If the scanout has not changed, don't modify the FBC settings.
561 * Note that we make the fundamental assumption that the fb->obj
562 * cannot be unpinned (and have its GTT offset and fence revoked)
563 * without first being decoupled from the scanout and FBC disabled.
564 */
5c3fe8b0
BW		 565 if (dev_priv->fbc.plane == intel_crtc->plane &&
566 dev_priv->fbc.fb_id == fb->base.id &&
567 dev_priv->fbc.y == crtc->y)
85208be0
ED		 568 return;
569
570 if (intel_fbc_enabled(dev)) {
571 /* We update FBC along two paths, after changing fb/crtc
572 * configuration (modeswitching) and after page-flipping
573 * finishes. For the latter, we know that not only did
574 * we disable the FBC at the start of the page-flip
575 * sequence, but also more than one vblank has passed.
576 *
577 * For the former case of modeswitching, it is possible
578 * to switch between two FBC valid configurations
579 * instantaneously so we do need to disable the FBC
580 * before we can modify its control registers. We also
581 * have to wait for the next vblank for that to take
582 * effect. However, since we delay enabling FBC we can
583 * assume that a vblank has passed since disabling and
584 * that we can safely alter the registers in the deferred
585 * callback.
586 *
587 * In the scenario that we go from a valid to invalid
588 * and then back to valid FBC configuration we have
589 * no strict enforcement that a vblank occurred since
590 * disabling the FBC. However, along all current pipe
591 * disabling paths we do need to wait for a vblank at
592 * some point. And we wait before enabling FBC anyway.
593 */
594 DRM_DEBUG_KMS("disabling active FBC for update\n");
595 intel_disable_fbc(dev);
596 }
597
598 intel_enable_fbc(crtc, 500);
29ebf90f 599 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 600 return;
601
602out_disable:
603 /* Multiple disables should be harmless */
604 if (intel_fbc_enabled(dev)) {
605 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
606 intel_disable_fbc(dev);
607 }
11be49eb 608 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 609}
610
c921aba8
DV		 611static void i915_pineview_get_mem_freq(struct drm_device *dev)
612{
613 drm_i915_private_t *dev_priv = dev->dev_private;
614 u32 tmp;
615
616 tmp = I915_READ(CLKCFG);
617
618 switch (tmp & CLKCFG_FSB_MASK) {
619 case CLKCFG_FSB_533:
620 dev_priv->fsb_freq = 533; /* 133*4 */
621 break;
622 case CLKCFG_FSB_800:
623 dev_priv->fsb_freq = 800; /* 200*4 */
624 break;
625 case CLKCFG_FSB_667:
626 dev_priv->fsb_freq = 667; /* 167*4 */
627 break;
628 case CLKCFG_FSB_400:
629 dev_priv->fsb_freq = 400; /* 100*4 */
630 break;
631 }
632
633 switch (tmp & CLKCFG_MEM_MASK) {
634 case CLKCFG_MEM_533:
635 dev_priv->mem_freq = 533;
636 break;
637 case CLKCFG_MEM_667:
638 dev_priv->mem_freq = 667;
639 break;
640 case CLKCFG_MEM_800:
641 dev_priv->mem_freq = 800;
642 break;
643 }
644
645 /* detect pineview DDR3 setting */
646 tmp = I915_READ(CSHRDDR3CTL);
647 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
648}
649
650static void i915_ironlake_get_mem_freq(struct drm_device *dev)
651{
652 drm_i915_private_t *dev_priv = dev->dev_private;
653 u16 ddrpll, csipll;
654
655 ddrpll = I915_READ16(DDRMPLL1);
656 csipll = I915_READ16(CSIPLL0);
657
658 switch (ddrpll & 0xff) {
659 case 0xc:
660 dev_priv->mem_freq = 800;
661 break;
662 case 0x10:
663 dev_priv->mem_freq = 1066;
664 break;
665 case 0x14:
666 dev_priv->mem_freq = 1333;
667 break;
668 case 0x18:
669 dev_priv->mem_freq = 1600;
670 break;
671 default:
672 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
673 ddrpll & 0xff);
674 dev_priv->mem_freq = 0;
675 break;
676 }
677
20e4d407 678 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 679
680 switch (csipll & 0x3ff) {
681 case 0x00c:
682 dev_priv->fsb_freq = 3200;
683 break;
684 case 0x00e:
685 dev_priv->fsb_freq = 3733;
686 break;
687 case 0x010:
688 dev_priv->fsb_freq = 4266;
689 break;
690 case 0x012:
691 dev_priv->fsb_freq = 4800;
692 break;
693 case 0x014:
694 dev_priv->fsb_freq = 5333;
695 break;
696 case 0x016:
697 dev_priv->fsb_freq = 5866;
698 break;
699 case 0x018:
700 dev_priv->fsb_freq = 6400;
701 break;
702 default:
703 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
704 csipll & 0x3ff);
705 dev_priv->fsb_freq = 0;
706 break;
707 }
708
709 if (dev_priv->fsb_freq == 3200) {
20e4d407 710 dev_priv->ips.c_m = 0;
c921aba8 711 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 712 dev_priv->ips.c_m = 1;
c921aba8 713 } else {
20e4d407 714 dev_priv->ips.c_m = 2;
c921aba8
DV		 715 }
716}
717
b445e3b0
ED		 718static const struct cxsr_latency cxsr_latency_table[] = {
719 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
720 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
721 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
722 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
723 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
724
725 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
726 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
727 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
728 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
729 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
730
731 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
732 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
733 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
734 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
735 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
736
737 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
738 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
739 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
740 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
741 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
742
743 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
744 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
745 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
746 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
747 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
748
749 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
750 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
751 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
752 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
753 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
754};
755
63c62275 756static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 757 int is_ddr3,
758 int fsb,
759 int mem)
760{
761 const struct cxsr_latency *latency;
762 int i;
763
764 if (fsb == 0 || mem == 0)
765 return NULL;
766
767 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
768 latency = &cxsr_latency_table[i];
769 if (is_desktop == latency->is_desktop &&
770 is_ddr3 == latency->is_ddr3 &&
771 fsb == latency->fsb_freq && mem == latency->mem_freq)
772 return latency;
773 }
774
775 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
776
777 return NULL;
778}
779
1fa61106 780static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 781{
782 struct drm_i915_private *dev_priv = dev->dev_private;
783
784 /* deactivate cxsr */
785 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
786}
787
788/*
789 * Latency for FIFO fetches is dependent on several factors:
790 * - memory configuration (speed, channels)
791 * - chipset
792 * - current MCH state
793 * It can be fairly high in some situations, so here we assume a fairly
794 * pessimal value. It's a tradeoff between extra memory fetches (if we
795 * set this value too high, the FIFO will fetch frequently to stay full)
796 * and power consumption (set it too low to save power and we might see
797 * FIFO underruns and display "flicker").
798 *
799 * A value of 5us seems to be a good balance; safe for very low end
800 * platforms but not overly aggressive on lower latency configs.
801 */
802static const int latency_ns = 5000;
803
1fa61106 804static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 805{
806 struct drm_i915_private *dev_priv = dev->dev_private;
807 uint32_t dsparb = I915_READ(DSPARB);
808 int size;
809
810 size = dsparb & 0x7f;
811 if (plane)
812 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
813
814 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
815 plane ? "B" : "A", size);
816
817 return size;
818}
819
1fa61106 820static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 821{
822 struct drm_i915_private *dev_priv = dev->dev_private;
823 uint32_t dsparb = I915_READ(DSPARB);
824 int size;
825
826 size = dsparb & 0x1ff;
827 if (plane)
828 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
829 size >>= 1; /* Convert to cachelines */
830
831 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
832 plane ? "B" : "A", size);
833
834 return size;
835}
836
1fa61106 837static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 838{
839 struct drm_i915_private *dev_priv = dev->dev_private;
840 uint32_t dsparb = I915_READ(DSPARB);
841 int size;
842
843 size = dsparb & 0x7f;
844 size >>= 2; /* Convert to cachelines */
845
846 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
847 plane ? "B" : "A",
848 size);
849
850 return size;
851}
852
1fa61106 853static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 854{
855 struct drm_i915_private *dev_priv = dev->dev_private;
856 uint32_t dsparb = I915_READ(DSPARB);
857 int size;
858
859 size = dsparb & 0x7f;
860 size >>= 1; /* Convert to cachelines */
861
862 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
863 plane ? "B" : "A", size);
864
865 return size;
866}
867
868/* Pineview has different values for various configs */
869static const struct intel_watermark_params pineview_display_wm = {
870 PINEVIEW_DISPLAY_FIFO,
871 PINEVIEW_MAX_WM,
872 PINEVIEW_DFT_WM,
873 PINEVIEW_GUARD_WM,
874 PINEVIEW_FIFO_LINE_SIZE
875};
876static const struct intel_watermark_params pineview_display_hplloff_wm = {
877 PINEVIEW_DISPLAY_FIFO,
878 PINEVIEW_MAX_WM,
879 PINEVIEW_DFT_HPLLOFF_WM,
880 PINEVIEW_GUARD_WM,
881 PINEVIEW_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params pineview_cursor_wm = {
884 PINEVIEW_CURSOR_FIFO,
885 PINEVIEW_CURSOR_MAX_WM,
886 PINEVIEW_CURSOR_DFT_WM,
887 PINEVIEW_CURSOR_GUARD_WM,
888 PINEVIEW_FIFO_LINE_SIZE,
889};
890static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
891 PINEVIEW_CURSOR_FIFO,
892 PINEVIEW_CURSOR_MAX_WM,
893 PINEVIEW_CURSOR_DFT_WM,
894 PINEVIEW_CURSOR_GUARD_WM,
895 PINEVIEW_FIFO_LINE_SIZE
896};
897static const struct intel_watermark_params g4x_wm_info = {
898 G4X_FIFO_SIZE,
899 G4X_MAX_WM,
900 G4X_MAX_WM,
901 2,
902 G4X_FIFO_LINE_SIZE,
903};
904static const struct intel_watermark_params g4x_cursor_wm_info = {
905 I965_CURSOR_FIFO,
906 I965_CURSOR_MAX_WM,
907 I965_CURSOR_DFT_WM,
908 2,
909 G4X_FIFO_LINE_SIZE,
910};
911static const struct intel_watermark_params valleyview_wm_info = {
912 VALLEYVIEW_FIFO_SIZE,
913 VALLEYVIEW_MAX_WM,
914 VALLEYVIEW_MAX_WM,
915 2,
916 G4X_FIFO_LINE_SIZE,
917};
918static const struct intel_watermark_params valleyview_cursor_wm_info = {
919 I965_CURSOR_FIFO,
920 VALLEYVIEW_CURSOR_MAX_WM,
921 I965_CURSOR_DFT_WM,
922 2,
923 G4X_FIFO_LINE_SIZE,
924};
925static const struct intel_watermark_params i965_cursor_wm_info = {
926 I965_CURSOR_FIFO,
927 I965_CURSOR_MAX_WM,
928 I965_CURSOR_DFT_WM,
929 2,
930 I915_FIFO_LINE_SIZE,
931};
932static const struct intel_watermark_params i945_wm_info = {
933 I945_FIFO_SIZE,
934 I915_MAX_WM,
935 1,
936 2,
937 I915_FIFO_LINE_SIZE
938};
939static const struct intel_watermark_params i915_wm_info = {
940 I915_FIFO_SIZE,
941 I915_MAX_WM,
942 1,
943 2,
944 I915_FIFO_LINE_SIZE
945};
946static const struct intel_watermark_params i855_wm_info = {
947 I855GM_FIFO_SIZE,
948 I915_MAX_WM,
949 1,
950 2,
951 I830_FIFO_LINE_SIZE
952};
953static const struct intel_watermark_params i830_wm_info = {
954 I830_FIFO_SIZE,
955 I915_MAX_WM,
956 1,
957 2,
958 I830_FIFO_LINE_SIZE
959};
960
961static const struct intel_watermark_params ironlake_display_wm_info = {
962 ILK_DISPLAY_FIFO,
963 ILK_DISPLAY_MAXWM,
964 ILK_DISPLAY_DFTWM,
965 2,
966 ILK_FIFO_LINE_SIZE
967};
968static const struct intel_watermark_params ironlake_cursor_wm_info = {
969 ILK_CURSOR_FIFO,
970 ILK_CURSOR_MAXWM,
971 ILK_CURSOR_DFTWM,
972 2,
973 ILK_FIFO_LINE_SIZE
974};
975static const struct intel_watermark_params ironlake_display_srwm_info = {
976 ILK_DISPLAY_SR_FIFO,
977 ILK_DISPLAY_MAX_SRWM,
978 ILK_DISPLAY_DFT_SRWM,
979 2,
980 ILK_FIFO_LINE_SIZE
981};
982static const struct intel_watermark_params ironlake_cursor_srwm_info = {
983 ILK_CURSOR_SR_FIFO,
984 ILK_CURSOR_MAX_SRWM,
985 ILK_CURSOR_DFT_SRWM,
986 2,
987 ILK_FIFO_LINE_SIZE
988};
989
990static const struct intel_watermark_params sandybridge_display_wm_info = {
991 SNB_DISPLAY_FIFO,
992 SNB_DISPLAY_MAXWM,
993 SNB_DISPLAY_DFTWM,
994 2,
995 SNB_FIFO_LINE_SIZE
996};
997static const struct intel_watermark_params sandybridge_cursor_wm_info = {
998 SNB_CURSOR_FIFO,
999 SNB_CURSOR_MAXWM,
1000 SNB_CURSOR_DFTWM,
1001 2,
1002 SNB_FIFO_LINE_SIZE
1003};
1004static const struct intel_watermark_params sandybridge_display_srwm_info = {
1005 SNB_DISPLAY_SR_FIFO,
1006 SNB_DISPLAY_MAX_SRWM,
1007 SNB_DISPLAY_DFT_SRWM,
1008 2,
1009 SNB_FIFO_LINE_SIZE
1010};
1011static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1012 SNB_CURSOR_SR_FIFO,
1013 SNB_CURSOR_MAX_SRWM,
1014 SNB_CURSOR_DFT_SRWM,
1015 2,
1016 SNB_FIFO_LINE_SIZE
1017};
1018
1019
1020/**
1021 * intel_calculate_wm - calculate watermark level
1022 * @clock_in_khz: pixel clock
1023 * @wm: chip FIFO params
1024 * @pixel_size: display pixel size
1025 * @latency_ns: memory latency for the platform
1026 *
1027 * Calculate the watermark level (the level at which the display plane will
1028 * start fetching from memory again). Each chip has a different display
1029 * FIFO size and allocation, so the caller needs to figure that out and pass
1030 * in the correct intel_watermark_params structure.
1031 *
1032 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1033 * on the pixel size. When it reaches the watermark level, it'll start
1034 * fetching FIFO line sized based chunks from memory until the FIFO fills
1035 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1036 * will occur, and a display engine hang could result.
1037 */
1038static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1039 const struct intel_watermark_params *wm,
1040 int fifo_size,
1041 int pixel_size,
1042 unsigned long latency_ns)
1043{
1044 long entries_required, wm_size;
1045
1046 /*
1047 * Note: we need to make sure we don't overflow for various clock &
1048 * latency values.
1049 * clocks go from a few thousand to several hundred thousand.
1050 * latency is usually a few thousand
1051 */
1052 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1053 1000;
1054 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1055
1056 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1057
1058 wm_size = fifo_size - (entries_required + wm->guard_size);
1059
1060 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1061
1062 /* Don't promote wm_size to unsigned... */
1063 if (wm_size > (long)wm->max_wm)
1064 wm_size = wm->max_wm;
1065 if (wm_size <= 0)
1066 wm_size = wm->default_wm;
1067 return wm_size;
1068}
1069
1070static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1071{
1072 struct drm_crtc *crtc, *enabled = NULL;
1073
1074 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1075 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1076 if (enabled)
1077 return NULL;
1078 enabled = crtc;
1079 }
1080 }
1081
1082 return enabled;
1083}
1084
46ba614c 1085static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1086{
46ba614c 1087 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1088 struct drm_i915_private *dev_priv = dev->dev_private;
1089 struct drm_crtc *crtc;
1090 const struct cxsr_latency *latency;
1091 u32 reg;
1092 unsigned long wm;
1093
1094 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1095 dev_priv->fsb_freq, dev_priv->mem_freq);
1096 if (!latency) {
1097 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1098 pineview_disable_cxsr(dev);
1099 return;
1100 }
1101
1102 crtc = single_enabled_crtc(dev);
1103 if (crtc) {
241bfc38 1104 const struct drm_display_mode *adjusted_mode;
b445e3b0 1105 int pixel_size = crtc->fb->bits_per_pixel / 8;
241bfc38
DL		 1106 int clock;
1107
1108 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1109 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
4fe8590a 1169 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1170 int htotal, hdisplay, clock, pixel_size;
1171 int line_time_us, line_count;
1172 int entries, tlb_miss;
1173
1174 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1175 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1176 *cursor_wm = cursor->guard_size;
1177 *plane_wm = display->guard_size;
1178 return false;
1179 }
1180
4fe8590a 1181 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1182 clock = adjusted_mode->crtc_clock;
4fe8590a 1183 htotal = adjusted_mode->htotal;
37327abd 1184 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1185 pixel_size = crtc->fb->bits_per_pixel / 8;
1186
1187 /* Use the small buffer method to calculate plane watermark */
1188 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1189 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1190 if (tlb_miss > 0)
1191 entries += tlb_miss;
1192 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1193 *plane_wm = entries + display->guard_size;
1194 if (*plane_wm > (int)display->max_wm)
1195 *plane_wm = display->max_wm;
1196
1197 /* Use the large buffer method to calculate cursor watermark */
1198 line_time_us = ((htotal * 1000) / clock);
1199 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1200 entries = line_count * 64 * pixel_size;
1201 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1202 if (tlb_miss > 0)
1203 entries += tlb_miss;
1204 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1205 *cursor_wm = entries + cursor->guard_size;
1206 if (*cursor_wm > (int)cursor->max_wm)
1207 *cursor_wm = (int)cursor->max_wm;
1208
1209 return true;
1210}
1211
1212/*
1213 * Check the wm result.
1214 *
1215 * If any calculated watermark values is larger than the maximum value that
1216 * can be programmed into the associated watermark register, that watermark
1217 * must be disabled.
1218 */
1219static bool g4x_check_srwm(struct drm_device *dev,
1220 int display_wm, int cursor_wm,
1221 const struct intel_watermark_params *display,
1222 const struct intel_watermark_params *cursor)
1223{
1224 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1225 display_wm, cursor_wm);
1226
1227 if (display_wm > display->max_wm) {
1228 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1229 display_wm, display->max_wm);
1230 return false;
1231 }
1232
1233 if (cursor_wm > cursor->max_wm) {
1234 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1235 cursor_wm, cursor->max_wm);
1236 return false;
1237 }
1238
1239 if (!(display_wm || cursor_wm)) {
1240 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1241 return false;
1242 }
1243
1244 return true;
1245}
1246
1247static bool g4x_compute_srwm(struct drm_device *dev,
1248 int plane,
1249 int latency_ns,
1250 const struct intel_watermark_params *display,
1251 const struct intel_watermark_params *cursor,
1252 int *display_wm, int *cursor_wm)
1253{
1254 struct drm_crtc *crtc;
4fe8590a 1255 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1256 int hdisplay, htotal, pixel_size, clock;
1257 unsigned long line_time_us;
1258 int line_count, line_size;
1259 int small, large;
1260 int entries;
1261
1262 if (!latency_ns) {
1263 *display_wm = *cursor_wm = 0;
1264 return false;
1265 }
1266
1267 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1268 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1269 clock = adjusted_mode->crtc_clock;
4fe8590a 1270 htotal = adjusted_mode->htotal;
37327abd 1271 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1272 pixel_size = crtc->fb->bits_per_pixel / 8;
1273
1274 line_time_us = (htotal * 1000) / clock;
1275 line_count = (latency_ns / line_time_us + 1000) / 1000;
1276 line_size = hdisplay * pixel_size;
1277
1278 /* Use the minimum of the small and large buffer method for primary */
1279 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1280 large = line_count * line_size;
1281
1282 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1283 *display_wm = entries + display->guard_size;
1284
1285 /* calculate the self-refresh watermark for display cursor */
1286 entries = line_count * pixel_size * 64;
1287 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1288 *cursor_wm = entries + cursor->guard_size;
1289
1290 return g4x_check_srwm(dev,
1291 *display_wm, *cursor_wm,
1292 display, cursor);
1293}
1294
1295static bool vlv_compute_drain_latency(struct drm_device *dev,
1296 int plane,
1297 int *plane_prec_mult,
1298 int *plane_dl,
1299 int *cursor_prec_mult,
1300 int *cursor_dl)
1301{
1302 struct drm_crtc *crtc;
1303 int clock, pixel_size;
1304 int entries;
1305
1306 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1307 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1308 return false;
1309
241bfc38 1310 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 1311 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1312
1313 entries = (clock / 1000) * pixel_size;
1314 *plane_prec_mult = (entries > 256) ?
1315 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1316 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1317 pixel_size);
1318
1319 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1320 *cursor_prec_mult = (entries > 256) ?
1321 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1322 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1323
1324 return true;
1325}
1326
1327/*
1328 * Update drain latency registers of memory arbiter
1329 *
1330 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1331 * to be programmed. Each plane has a drain latency multiplier and a drain
1332 * latency value.
1333 */
1334
1335static void vlv_update_drain_latency(struct drm_device *dev)
1336{
1337 struct drm_i915_private *dev_priv = dev->dev_private;
1338 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1339 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1340 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1341 either 16 or 32 */
1342
1343 /* For plane A, Cursor A */
1344 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1345 &cursor_prec_mult, &cursora_dl)) {
1346 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1347 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1348 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1349 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1350
1351 I915_WRITE(VLV_DDL1, cursora_prec |
1352 (cursora_dl << DDL_CURSORA_SHIFT) |
1353 planea_prec | planea_dl);
1354 }
1355
1356 /* For plane B, Cursor B */
1357 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1358 &cursor_prec_mult, &cursorb_dl)) {
1359 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1360 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1361 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1362 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1363
1364 I915_WRITE(VLV_DDL2, cursorb_prec |
1365 (cursorb_dl << DDL_CURSORB_SHIFT) |
1366 planeb_prec | planeb_dl);
1367 }
1368}
1369
1370#define single_plane_enabled(mask) is_power_of_2(mask)
1371
46ba614c 1372static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1373{
46ba614c 1374 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1375 static const int sr_latency_ns = 12000;
1376 struct drm_i915_private *dev_priv = dev->dev_private;
1377 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1378 int plane_sr, cursor_sr;
af6c4575 1379 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1380 unsigned int enabled = 0;
1381
1382 vlv_update_drain_latency(dev);
1383
51cea1f4 1384 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1385 &valleyview_wm_info, latency_ns,
1386 &valleyview_cursor_wm_info, latency_ns,
1387 &planea_wm, &cursora_wm))
51cea1f4 1388 enabled |= 1 << PIPE_A;
b445e3b0 1389
51cea1f4 1390 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1391 &valleyview_wm_info, latency_ns,
1392 &valleyview_cursor_wm_info, latency_ns,
1393 &planeb_wm, &cursorb_wm))
51cea1f4 1394 enabled |= 1 << PIPE_B;
b445e3b0 1395
b445e3b0
ED		 1396 if (single_plane_enabled(enabled) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
af6c4575
CW		 1401 &plane_sr, &ignore_cursor_sr) &&
1402 g4x_compute_srwm(dev, ffs(enabled) - 1,
1403 2*sr_latency_ns,
1404 &valleyview_wm_info,
1405 &valleyview_cursor_wm_info,
52bd02d8 1406 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1407 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1408 } else {
b445e3b0
ED		 1409 I915_WRITE(FW_BLC_SELF_VLV,
1410 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1411 plane_sr = cursor_sr = 0;
1412 }
b445e3b0
ED		 1413
1414 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1415 planea_wm, cursora_wm,
1416 planeb_wm, cursorb_wm,
1417 plane_sr, cursor_sr);
1418
1419 I915_WRITE(DSPFW1,
1420 (plane_sr << DSPFW_SR_SHIFT) |
1421 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1422 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1423 planea_wm);
1424 I915_WRITE(DSPFW2,
8c919b28 1425 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1426 (cursora_wm << DSPFW_CURSORA_SHIFT));
1427 I915_WRITE(DSPFW3,
8c919b28
CW		 1428 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1429 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1430}
1431
46ba614c 1432static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1433{
46ba614c 1434 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1435 static const int sr_latency_ns = 12000;
1436 struct drm_i915_private *dev_priv = dev->dev_private;
1437 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1438 int plane_sr, cursor_sr;
1439 unsigned int enabled = 0;
1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planea_wm, &cursora_wm))
51cea1f4 1445 enabled |= 1 << PIPE_A;
b445e3b0 1446
51cea1f4 1447 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1448 &g4x_wm_info, latency_ns,
1449 &g4x_cursor_wm_info, latency_ns,
1450 &planeb_wm, &cursorb_wm))
51cea1f4 1451 enabled |= 1 << PIPE_B;
b445e3b0 1452
b445e3b0
ED		 1453 if (single_plane_enabled(enabled) &&
1454 g4x_compute_srwm(dev, ffs(enabled) - 1,
1455 sr_latency_ns,
1456 &g4x_wm_info,
1457 &g4x_cursor_wm_info,
52bd02d8 1458 &plane_sr, &cursor_sr)) {
b445e3b0 1459 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1460 } else {
b445e3b0
ED		 1461 I915_WRITE(FW_BLC_SELF,
1462 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1463 plane_sr = cursor_sr = 0;
1464 }
b445e3b0
ED		 1465
1466 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1467 planea_wm, cursora_wm,
1468 planeb_wm, cursorb_wm,
1469 plane_sr, cursor_sr);
1470
1471 I915_WRITE(DSPFW1,
1472 (plane_sr << DSPFW_SR_SHIFT) |
1473 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1474 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1475 planea_wm);
1476 I915_WRITE(DSPFW2,
8c919b28 1477 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1478 (cursora_wm << DSPFW_CURSORA_SHIFT));
1479 /* HPLL off in SR has some issues on G4x... disable it */
1480 I915_WRITE(DSPFW3,
8c919b28 1481 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1482 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1483}
1484
46ba614c 1485static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1486{
46ba614c 1487 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1488 struct drm_i915_private *dev_priv = dev->dev_private;
1489 struct drm_crtc *crtc;
1490 int srwm = 1;
1491 int cursor_sr = 16;
1492
1493 /* Calc sr entries for one plane configs */
1494 crtc = single_enabled_crtc(dev);
1495 if (crtc) {
1496 /* self-refresh has much higher latency */
1497 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1498 const struct drm_display_mode *adjusted_mode =
1499 &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1500 int clock = adjusted_mode->crtc_clock;
4fe8590a 1501 int htotal = adjusted_mode->htotal;
37327abd 1502 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1503 int pixel_size = crtc->fb->bits_per_pixel / 8;
1504 unsigned long line_time_us;
1505 int entries;
1506
1507 line_time_us = ((htotal * 1000) / clock);
1508
1509 /* Use ns/us then divide to preserve precision */
1510 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1511 pixel_size * hdisplay;
1512 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1513 srwm = I965_FIFO_SIZE - entries;
1514 if (srwm < 0)
1515 srwm = 1;
1516 srwm &= 0x1ff;
1517 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1518 entries, srwm);
1519
1520 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1521 pixel_size * 64;
1522 entries = DIV_ROUND_UP(entries,
1523 i965_cursor_wm_info.cacheline_size);
1524 cursor_sr = i965_cursor_wm_info.fifo_size -
1525 (entries + i965_cursor_wm_info.guard_size);
1526
1527 if (cursor_sr > i965_cursor_wm_info.max_wm)
1528 cursor_sr = i965_cursor_wm_info.max_wm;
1529
1530 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1531 "cursor %d\n", srwm, cursor_sr);
1532
1533 if (IS_CRESTLINE(dev))
1534 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1535 } else {
1536 /* Turn off self refresh if both pipes are enabled */
1537 if (IS_CRESTLINE(dev))
1538 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1539 & ~FW_BLC_SELF_EN);
1540 }
1541
1542 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1543 srwm);
1544
1545 /* 965 has limitations... */
1546 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1547 (8 << 16) | (8 << 8) | (8 << 0));
1548 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1549 /* update cursor SR watermark */
1550 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1551}
1552
46ba614c 1553static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1554{
46ba614c 1555 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1556 struct drm_i915_private *dev_priv = dev->dev_private;
1557 const struct intel_watermark_params *wm_info;
1558 uint32_t fwater_lo;
1559 uint32_t fwater_hi;
1560 int cwm, srwm = 1;
1561 int fifo_size;
1562 int planea_wm, planeb_wm;
1563 struct drm_crtc *crtc, *enabled = NULL;
1564
1565 if (IS_I945GM(dev))
1566 wm_info = &i945_wm_info;
1567 else if (!IS_GEN2(dev))
1568 wm_info = &i915_wm_info;
1569 else
1570 wm_info = &i855_wm_info;
1571
1572 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1573 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1574 if (intel_crtc_active(crtc)) {
241bfc38 1575 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1576 int cpp = crtc->fb->bits_per_pixel / 8;
1577 if (IS_GEN2(dev))
1578 cpp = 4;
1579
241bfc38
DL		 1580 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1581 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1582 wm_info, fifo_size, cpp,
b445e3b0
ED		 1583 latency_ns);
1584 enabled = crtc;
1585 } else
1586 planea_wm = fifo_size - wm_info->guard_size;
1587
1588 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1589 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1590 if (intel_crtc_active(crtc)) {
241bfc38 1591 const struct drm_display_mode *adjusted_mode;
b9e0bda3
CW		 1592 int cpp = crtc->fb->bits_per_pixel / 8;
1593 if (IS_GEN2(dev))
1594 cpp = 4;
1595
241bfc38
DL		 1596 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1597 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1598 wm_info, fifo_size, cpp,
b445e3b0
ED		 1599 latency_ns);
1600 if (enabled == NULL)
1601 enabled = crtc;
1602 else
1603 enabled = NULL;
1604 } else
1605 planeb_wm = fifo_size - wm_info->guard_size;
1606
1607 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1608
1609 /*
1610 * Overlay gets an aggressive default since video jitter is bad.
1611 */
1612 cwm = 2;
1613
1614 /* Play safe and disable self-refresh before adjusting watermarks. */
1615 if (IS_I945G(dev) || IS_I945GM(dev))
1616 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1617 else if (IS_I915GM(dev))
1618 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1619
1620 /* Calc sr entries for one plane configs */
1621 if (HAS_FW_BLC(dev) && enabled) {
1622 /* self-refresh has much higher latency */
1623 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1624 const struct drm_display_mode *adjusted_mode =
1625 &to_intel_crtc(enabled)->config.adjusted_mode;
241bfc38 1626 int clock = adjusted_mode->crtc_clock;
4fe8590a 1627 int htotal = adjusted_mode->htotal;
37327abd 1628 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1629 int pixel_size = enabled->fb->bits_per_pixel / 8;
1630 unsigned long line_time_us;
1631 int entries;
1632
1633 line_time_us = (htotal * 1000) / clock;
1634
1635 /* Use ns/us then divide to preserve precision */
1636 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1637 pixel_size * hdisplay;
1638 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1639 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1640 srwm = wm_info->fifo_size - entries;
1641 if (srwm < 0)
1642 srwm = 1;
1643
1644 if (IS_I945G(dev) || IS_I945GM(dev))
1645 I915_WRITE(FW_BLC_SELF,
1646 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1647 else if (IS_I915GM(dev))
1648 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1649 }
1650
1651 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1652 planea_wm, planeb_wm, cwm, srwm);
1653
1654 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1655 fwater_hi = (cwm & 0x1f);
1656
1657 /* Set request length to 8 cachelines per fetch */
1658 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1659 fwater_hi = fwater_hi | (1 << 8);
1660
1661 I915_WRITE(FW_BLC, fwater_lo);
1662 I915_WRITE(FW_BLC2, fwater_hi);
1663
1664 if (HAS_FW_BLC(dev)) {
1665 if (enabled) {
1666 if (IS_I945G(dev) || IS_I945GM(dev))
1667 I915_WRITE(FW_BLC_SELF,
1668 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1669 else if (IS_I915GM(dev))
1670 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1671 DRM_DEBUG_KMS("memory self refresh enabled\n");
1672 } else
1673 DRM_DEBUG_KMS("memory self refresh disabled\n");
1674 }
1675}
1676
46ba614c 1677static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1678{
46ba614c 1679 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1680 struct drm_i915_private *dev_priv = dev->dev_private;
1681 struct drm_crtc *crtc;
241bfc38 1682 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1683 uint32_t fwater_lo;
1684 int planea_wm;
1685
1686 crtc = single_enabled_crtc(dev);
1687 if (crtc == NULL)
1688 return;
1689
241bfc38
DL		 1690 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1691 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
4fe8590a 1692 &i830_wm_info,
b445e3b0 1693 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1694 4, latency_ns);
b445e3b0
ED		 1695 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1696 fwater_lo |= (3<<8) | planea_wm;
1697
1698 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1699
1700 I915_WRITE(FW_BLC, fwater_lo);
1701}
1702
b445e3b0
ED		 1703/*
1704 * Check the wm result.
1705 *
1706 * If any calculated watermark values is larger than the maximum value that
1707 * can be programmed into the associated watermark register, that watermark
1708 * must be disabled.
1709 */
1710static bool ironlake_check_srwm(struct drm_device *dev, int level,
1711 int fbc_wm, int display_wm, int cursor_wm,
1712 const struct intel_watermark_params *display,
1713 const struct intel_watermark_params *cursor)
1714{
1715 struct drm_i915_private *dev_priv = dev->dev_private;
1716
1717 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1718 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1719
1720 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1721 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1722 fbc_wm, SNB_FBC_MAX_SRWM, level);
1723
1724 /* fbc has it's own way to disable FBC WM */
1725 I915_WRITE(DISP_ARB_CTL,
1726 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1727 return false;
615aaa5f
VS		 1728 } else if (INTEL_INFO(dev)->gen >= 6) {
1729 /* enable FBC WM (except on ILK, where it must remain off) */
1730 I915_WRITE(DISP_ARB_CTL,
1731 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1732 }
1733
1734 if (display_wm > display->max_wm) {
1735 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1736 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1737 return false;
1738 }
1739
1740 if (cursor_wm > cursor->max_wm) {
1741 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1742 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1743 return false;
1744 }
1745
1746 if (!(fbc_wm || display_wm || cursor_wm)) {
1747 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1748 return false;
1749 }
1750
1751 return true;
1752}
1753
1754/*
1755 * Compute watermark values of WM[1-3],
1756 */
1757static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1758 int latency_ns,
1759 const struct intel_watermark_params *display,
1760 const struct intel_watermark_params *cursor,
1761 int *fbc_wm, int *display_wm, int *cursor_wm)
1762{
1763 struct drm_crtc *crtc;
4fe8590a 1764 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1765 unsigned long line_time_us;
1766 int hdisplay, htotal, pixel_size, clock;
1767 int line_count, line_size;
1768 int small, large;
1769 int entries;
1770
1771 if (!latency_ns) {
1772 *fbc_wm = *display_wm = *cursor_wm = 0;
1773 return false;
1774 }
1775
1776 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 1777 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
241bfc38 1778 clock = adjusted_mode->crtc_clock;
4fe8590a 1779 htotal = adjusted_mode->htotal;
37327abd 1780 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1781 pixel_size = crtc->fb->bits_per_pixel / 8;
1782
1783 line_time_us = (htotal * 1000) / clock;
1784 line_count = (latency_ns / line_time_us + 1000) / 1000;
1785 line_size = hdisplay * pixel_size;
1786
1787 /* Use the minimum of the small and large buffer method for primary */
1788 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1789 large = line_count * line_size;
1790
1791 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1792 *display_wm = entries + display->guard_size;
1793
1794 /*
1795 * Spec says:
1796 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1797 */
1798 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1799
1800 /* calculate the self-refresh watermark for display cursor */
1801 entries = line_count * pixel_size * 64;
1802 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1803 *cursor_wm = entries + cursor->guard_size;
1804
1805 return ironlake_check_srwm(dev, level,
1806 *fbc_wm, *display_wm, *cursor_wm,
1807 display, cursor);
1808}
1809
46ba614c 1810static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1811{
46ba614c 1812 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1813 struct drm_i915_private *dev_priv = dev->dev_private;
1814 int fbc_wm, plane_wm, cursor_wm;
1815 unsigned int enabled;
1816
1817 enabled = 0;
51cea1f4 1818 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1819 &ironlake_display_wm_info,
b0aea5dc 1820 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1821 &ironlake_cursor_wm_info,
b0aea5dc 1822 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1823 &plane_wm, &cursor_wm)) {
1824 I915_WRITE(WM0_PIPEA_ILK,
1825 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1827 " plane %d, " "cursor: %d\n",
1828 plane_wm, cursor_wm);
51cea1f4 1829 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1830 }
1831
51cea1f4 1832 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1833 &ironlake_display_wm_info,
b0aea5dc 1834 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1835 &ironlake_cursor_wm_info,
b0aea5dc 1836 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1837 &plane_wm, &cursor_wm)) {
1838 I915_WRITE(WM0_PIPEB_ILK,
1839 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1840 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1841 " plane %d, cursor: %d\n",
1842 plane_wm, cursor_wm);
51cea1f4 1843 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1844 }
1845
1846 /*
1847 * Calculate and update the self-refresh watermark only when one
1848 * display plane is used.
1849 */
1850 I915_WRITE(WM3_LP_ILK, 0);
1851 I915_WRITE(WM2_LP_ILK, 0);
1852 I915_WRITE(WM1_LP_ILK, 0);
1853
1854 if (!single_plane_enabled(enabled))
1855 return;
1856 enabled = ffs(enabled) - 1;
1857
1858 /* WM1 */
1859 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1860 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1861 &ironlake_display_srwm_info,
1862 &ironlake_cursor_srwm_info,
1863 &fbc_wm, &plane_wm, &cursor_wm))
1864 return;
1865
1866 I915_WRITE(WM1_LP_ILK,
1867 WM1_LP_SR_EN |
b0aea5dc 1868 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1869 (fbc_wm << WM1_LP_FBC_SHIFT) |
1870 (plane_wm << WM1_LP_SR_SHIFT) |
1871 cursor_wm);
1872
1873 /* WM2 */
1874 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1875 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1876 &ironlake_display_srwm_info,
1877 &ironlake_cursor_srwm_info,
1878 &fbc_wm, &plane_wm, &cursor_wm))
1879 return;
1880
1881 I915_WRITE(WM2_LP_ILK,
1882 WM2_LP_EN |
b0aea5dc 1883 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1884 (fbc_wm << WM1_LP_FBC_SHIFT) |
1885 (plane_wm << WM1_LP_SR_SHIFT) |
1886 cursor_wm);
1887
1888 /*
1889 * WM3 is unsupported on ILK, probably because we don't have latency
1890 * data for that power state
1891 */
1892}
1893
46ba614c 1894static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1895{
46ba614c 1896 struct drm_device *dev = crtc->dev;
b445e3b0 1897 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1898 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1899 u32 val;
1900 int fbc_wm, plane_wm, cursor_wm;
1901 unsigned int enabled;
1902
1903 enabled = 0;
51cea1f4 1904 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1905 &sandybridge_display_wm_info, latency,
1906 &sandybridge_cursor_wm_info, latency,
1907 &plane_wm, &cursor_wm)) {
1908 val = I915_READ(WM0_PIPEA_ILK);
1909 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1910 I915_WRITE(WM0_PIPEA_ILK, val |
1911 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1912 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1913 " plane %d, " "cursor: %d\n",
1914 plane_wm, cursor_wm);
51cea1f4 1915 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1916 }
1917
51cea1f4 1918 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1919 &sandybridge_display_wm_info, latency,
1920 &sandybridge_cursor_wm_info, latency,
1921 &plane_wm, &cursor_wm)) {
1922 val = I915_READ(WM0_PIPEB_ILK);
1923 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1924 I915_WRITE(WM0_PIPEB_ILK, val |
1925 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1926 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1927 " plane %d, cursor: %d\n",
1928 plane_wm, cursor_wm);
51cea1f4 1929 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1930 }
1931
c43d0188
CW		 1932 /*
1933 * Calculate and update the self-refresh watermark only when one
1934 * display plane is used.
1935 *
1936 * SNB support 3 levels of watermark.
1937 *
1938 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1939 * and disabled in the descending order
1940 *
1941 */
1942 I915_WRITE(WM3_LP_ILK, 0);
1943 I915_WRITE(WM2_LP_ILK, 0);
1944 I915_WRITE(WM1_LP_ILK, 0);
1945
1946 if (!single_plane_enabled(enabled) ||
1947 dev_priv->sprite_scaling_enabled)
1948 return;
1949 enabled = ffs(enabled) - 1;
1950
1951 /* WM1 */
1952 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1953 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1954 &sandybridge_display_srwm_info,
1955 &sandybridge_cursor_srwm_info,
1956 &fbc_wm, &plane_wm, &cursor_wm))
1957 return;
1958
1959 I915_WRITE(WM1_LP_ILK,
1960 WM1_LP_SR_EN |
b0aea5dc 1961 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1962 (fbc_wm << WM1_LP_FBC_SHIFT) |
1963 (plane_wm << WM1_LP_SR_SHIFT) |
1964 cursor_wm);
1965
1966 /* WM2 */
1967 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1968 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1969 &sandybridge_display_srwm_info,
1970 &sandybridge_cursor_srwm_info,
1971 &fbc_wm, &plane_wm, &cursor_wm))
1972 return;
1973
1974 I915_WRITE(WM2_LP_ILK,
1975 WM2_LP_EN |
b0aea5dc 1976 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1977 (fbc_wm << WM1_LP_FBC_SHIFT) |
1978 (plane_wm << WM1_LP_SR_SHIFT) |
1979 cursor_wm);
1980
1981 /* WM3 */
1982 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1983 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1984 &sandybridge_display_srwm_info,
1985 &sandybridge_cursor_srwm_info,
1986 &fbc_wm, &plane_wm, &cursor_wm))
1987 return;
1988
1989 I915_WRITE(WM3_LP_ILK,
1990 WM3_LP_EN |
b0aea5dc 1991 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1992 (fbc_wm << WM1_LP_FBC_SHIFT) |
1993 (plane_wm << WM1_LP_SR_SHIFT) |
1994 cursor_wm);
1995}
1996
46ba614c 1997static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1998{
46ba614c 1999 struct drm_device *dev = crtc->dev;
c43d0188 2000 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2001 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 2002 u32 val;
2003 int fbc_wm, plane_wm, cursor_wm;
2004 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
2005 unsigned int enabled;
2006
2007 enabled = 0;
51cea1f4 2008 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 2009 &sandybridge_display_wm_info, latency,
2010 &sandybridge_cursor_wm_info, latency,
2011 &plane_wm, &cursor_wm)) {
2012 val = I915_READ(WM0_PIPEA_ILK);
2013 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2014 I915_WRITE(WM0_PIPEA_ILK, val |
2015 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2016 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2017 " plane %d, " "cursor: %d\n",
2018 plane_wm, cursor_wm);
51cea1f4 2019 enabled |= 1 << PIPE_A;
c43d0188
CW		 2020 }
2021
51cea1f4 2022 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2023 &sandybridge_display_wm_info, latency,
2024 &sandybridge_cursor_wm_info, latency,
2025 &plane_wm, &cursor_wm)) {
2026 val = I915_READ(WM0_PIPEB_ILK);
2027 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2028 I915_WRITE(WM0_PIPEB_ILK, val |
2029 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2030 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2031 " plane %d, cursor: %d\n",
2032 plane_wm, cursor_wm);
51cea1f4 2033 enabled |= 1 << PIPE_B;
c43d0188
CW		 2034 }
2035
51cea1f4 2036 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2037 &sandybridge_display_wm_info, latency,
2038 &sandybridge_cursor_wm_info, latency,
2039 &plane_wm, &cursor_wm)) {
2040 val = I915_READ(WM0_PIPEC_IVB);
2041 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2042 I915_WRITE(WM0_PIPEC_IVB, val |
2043 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2044 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2045 " plane %d, cursor: %d\n",
2046 plane_wm, cursor_wm);
51cea1f4 2047 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2048 }
2049
2050 /*
2051 * Calculate and update the self-refresh watermark only when one
2052 * display plane is used.
2053 *
2054 * SNB support 3 levels of watermark.
2055 *
2056 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2057 * and disabled in the descending order
2058 *
2059 */
2060 I915_WRITE(WM3_LP_ILK, 0);
2061 I915_WRITE(WM2_LP_ILK, 0);
2062 I915_WRITE(WM1_LP_ILK, 0);
2063
2064 if (!single_plane_enabled(enabled) ||
2065 dev_priv->sprite_scaling_enabled)
2066 return;
2067 enabled = ffs(enabled) - 1;
2068
2069 /* WM1 */
2070 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2071 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2072 &sandybridge_display_srwm_info,
2073 &sandybridge_cursor_srwm_info,
2074 &fbc_wm, &plane_wm, &cursor_wm))
2075 return;
2076
2077 I915_WRITE(WM1_LP_ILK,
2078 WM1_LP_SR_EN |
b0aea5dc 2079 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2080 (fbc_wm << WM1_LP_FBC_SHIFT) |
2081 (plane_wm << WM1_LP_SR_SHIFT) |
2082 cursor_wm);
2083
2084 /* WM2 */
2085 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2086 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2087 &sandybridge_display_srwm_info,
2088 &sandybridge_cursor_srwm_info,
2089 &fbc_wm, &plane_wm, &cursor_wm))
2090 return;
2091
2092 I915_WRITE(WM2_LP_ILK,
2093 WM2_LP_EN |
b0aea5dc 2094 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2095 (fbc_wm << WM1_LP_FBC_SHIFT) |
2096 (plane_wm << WM1_LP_SR_SHIFT) |
2097 cursor_wm);
2098
c43d0188 2099 /* WM3, note we have to correct the cursor latency */
b445e3b0 2100 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2101 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2102 &sandybridge_display_srwm_info,
2103 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2104 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2105 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2106 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2107 &sandybridge_display_srwm_info,
2108 &sandybridge_cursor_srwm_info,
2109 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2110 return;
2111
2112 I915_WRITE(WM3_LP_ILK,
2113 WM3_LP_EN |
b0aea5dc 2114 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2115 (fbc_wm << WM1_LP_FBC_SHIFT) |
2116 (plane_wm << WM1_LP_SR_SHIFT) |
2117 cursor_wm);
2118}
2119
3658729a
VS		 2120static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2121 struct drm_crtc *crtc)
801bcfff
PZ		 2122{
2123 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2124 uint32_t pixel_rate;
801bcfff 2125
241bfc38 2126 pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock;
801bcfff
PZ		 2127
2128 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2129 * adjust the pixel_rate here. */
2130
fd4daa9c 2131 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2132 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2133 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2134
37327abd
VS		 2135 pipe_w = intel_crtc->config.pipe_src_w;
2136 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2137 pfit_w = (pfit_size >> 16) & 0xFFFF;
2138 pfit_h = pfit_size & 0xFFFF;
2139 if (pipe_w < pfit_w)
2140 pipe_w = pfit_w;
2141 if (pipe_h < pfit_h)
2142 pipe_h = pfit_h;
2143
2144 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2145 pfit_w * pfit_h);
2146 }
2147
2148 return pixel_rate;
2149}
2150
37126462 2151/* latency must be in 0.1us units. */
23297044 2152static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2153 uint32_t latency)
2154{
2155 uint64_t ret;
2156
3312ba65
VS		 2157 if (WARN(latency == 0, "Latency value missing\n"))
2158 return UINT_MAX;
2159
801bcfff
PZ		 2160 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2161 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2162
2163 return ret;
2164}
2165
37126462 2166/* latency must be in 0.1us units. */
23297044 2167static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2168 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2169 uint32_t latency)
2170{
2171 uint32_t ret;
2172
3312ba65
VS		 2173 if (WARN(latency == 0, "Latency value missing\n"))
2174 return UINT_MAX;
2175
801bcfff
PZ		 2176 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2177 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2178 ret = DIV_ROUND_UP(ret, 64) + 2;
2179 return ret;
2180}
2181
23297044 2182static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2183 uint8_t bytes_per_pixel)
2184{
2185 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2186}
2187
801bcfff
PZ		 2188struct hsw_pipe_wm_parameters {
2189 bool active;
801bcfff
PZ		 2190 uint32_t pipe_htotal;
2191 uint32_t pixel_rate;
c35426d2
VS		 2192 struct intel_plane_wm_parameters pri;
2193 struct intel_plane_wm_parameters spr;
2194 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2195};
2196
cca32e9a
PZ		 2197struct hsw_wm_maximums {
2198 uint16_t pri;
2199 uint16_t spr;
2200 uint16_t cur;
2201 uint16_t fbc;
2202};
2203
240264f4
VS		 2204/* used in computing the new watermarks state */
2205struct intel_wm_config {
2206 unsigned int num_pipes_active;
2207 bool sprites_enabled;
2208 bool sprites_scaled;
240264f4
VS		 2209};
2210
37126462
VS		 2211/*
2212 * For both WM_PIPE and WM_LP.
2213 * mem_value must be in 0.1us units.
2214 */
ac830fe1 2215static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2216 uint32_t mem_value,
2217 bool is_lp)
801bcfff 2218{
cca32e9a
PZ		 2219 uint32_t method1, method2;
2220
c35426d2 2221 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2222 return 0;
2223
23297044 2224 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2225 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2226 mem_value);
2227
2228 if (!is_lp)
2229 return method1;
2230
23297044 2231 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2232 params->pipe_htotal,
c35426d2
VS		 2233 params->pri.horiz_pixels,
2234 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2235 mem_value);
2236
2237 return min(method1, method2);
801bcfff
PZ		 2238}
2239
37126462
VS		 2240/*
2241 * For both WM_PIPE and WM_LP.
2242 * mem_value must be in 0.1us units.
2243 */
ac830fe1 2244static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2245 uint32_t mem_value)
2246{
2247 uint32_t method1, method2;
2248
c35426d2 2249 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2250 return 0;
2251
23297044 2252 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2253 params->spr.bytes_per_pixel,
801bcfff 2254 mem_value);
23297044 2255 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2256 params->pipe_htotal,
c35426d2
VS		 2257 params->spr.horiz_pixels,
2258 params->spr.bytes_per_pixel,
801bcfff
PZ		 2259 mem_value);
2260 return min(method1, method2);
2261}
2262
37126462
VS		 2263/*
2264 * For both WM_PIPE and WM_LP.
2265 * mem_value must be in 0.1us units.
2266 */
ac830fe1 2267static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2268 uint32_t mem_value)
2269{
c35426d2 2270 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2271 return 0;
2272
23297044 2273 return ilk_wm_method2(params->pixel_rate,
801bcfff 2274 params->pipe_htotal,
c35426d2
VS		 2275 params->cur.horiz_pixels,
2276 params->cur.bytes_per_pixel,
801bcfff
PZ		 2277 mem_value);
2278}
2279
cca32e9a 2280/* Only for WM_LP. */
ac830fe1 2281static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2282 uint32_t pri_val)
cca32e9a 2283{
c35426d2 2284 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2285 return 0;
2286
23297044 2287 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2288 params->pri.horiz_pixels,
2289 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2290}
2291
158ae64f
VS		 2292static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2293{
2294 if (INTEL_INFO(dev)->gen >= 7)
2295 return 768;
2296 else
2297 return 512;
2298}
2299
2300/* Calculate the maximum primary/sprite plane watermark */
2301static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2302 int level,
240264f4 2303 const struct intel_wm_config *config,
158ae64f
VS		 2304 enum intel_ddb_partitioning ddb_partitioning,
2305 bool is_sprite)
2306{
2307 unsigned int fifo_size = ilk_display_fifo_size(dev);
2308 unsigned int max;
2309
2310 /* if sprites aren't enabled, sprites get nothing */
240264f4 2311 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2312 return 0;
2313
2314 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2315 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2316 fifo_size /= INTEL_INFO(dev)->num_pipes;
2317
2318 /*
2319 * For some reason the non self refresh
2320 * FIFO size is only half of the self
2321 * refresh FIFO size on ILK/SNB.
2322 */
2323 if (INTEL_INFO(dev)->gen <= 6)
2324 fifo_size /= 2;
2325 }
2326
240264f4 2327 if (config->sprites_enabled) {
158ae64f
VS		 2328 /* level 0 is always calculated with 1:1 split */
2329 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2330 if (is_sprite)
2331 fifo_size *= 5;
2332 fifo_size /= 6;
2333 } else {
2334 fifo_size /= 2;
2335 }
2336 }
2337
2338 /* clamp to max that the registers can hold */
2339 if (INTEL_INFO(dev)->gen >= 7)
2340 /* IVB/HSW primary/sprite plane watermarks */
2341 max = level == 0 ? 127 : 1023;
2342 else if (!is_sprite)
2343 /* ILK/SNB primary plane watermarks */
2344 max = level == 0 ? 127 : 511;
2345 else
2346 /* ILK/SNB sprite plane watermarks */
2347 max = level == 0 ? 63 : 255;
2348
2349 return min(fifo_size, max);
2350}
2351
2352/* Calculate the maximum cursor plane watermark */
2353static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2354 int level,
2355 const struct intel_wm_config *config)
158ae64f
VS		 2356{
2357 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2358 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2359 return 64;
2360
2361 /* otherwise just report max that registers can hold */
2362 if (INTEL_INFO(dev)->gen >= 7)
2363 return level == 0 ? 63 : 255;
2364 else
2365 return level == 0 ? 31 : 63;
2366}
2367
2368/* Calculate the maximum FBC watermark */
2369static unsigned int ilk_fbc_wm_max(void)
2370{
2371 /* max that registers can hold */
2372 return 15;
2373}
2374
34982fe1
VS		 2375static void ilk_compute_wm_maximums(struct drm_device *dev,
2376 int level,
2377 const struct intel_wm_config *config,
2378 enum intel_ddb_partitioning ddb_partitioning,
2379 struct hsw_wm_maximums *max)
158ae64f 2380{
240264f4
VS		 2381 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2382 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2383 max->cur = ilk_cursor_wm_max(dev, level, config);
158ae64f
VS		 2384 max->fbc = ilk_fbc_wm_max();
2385}
2386
d9395655
VS		 2387static bool ilk_validate_wm_level(int level,
2388 const struct hsw_wm_maximums *max,
2389 struct intel_wm_level *result)
a9786a11
VS		 2390{
2391 bool ret;
2392
2393 /* already determined to be invalid? */
2394 if (!result->enable)
2395 return false;
2396
2397 result->enable = result->pri_val <= max->pri &&
2398 result->spr_val <= max->spr &&
2399 result->cur_val <= max->cur;
2400
2401 ret = result->enable;
2402
2403 /*
2404 * HACK until we can pre-compute everything,
2405 * and thus fail gracefully if LP0 watermarks
2406 * are exceeded...
2407 */
2408 if (level == 0 && !result->enable) {
2409 if (result->pri_val > max->pri)
2410 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2411 level, result->pri_val, max->pri);
2412 if (result->spr_val > max->spr)
2413 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2414 level, result->spr_val, max->spr);
2415 if (result->cur_val > max->cur)
2416 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2417 level, result->cur_val, max->cur);
2418
2419 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2420 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2421 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2422 result->enable = true;
2423 }
2424
a9786a11
VS		 2425 return ret;
2426}
2427
6f5ddd17
VS		 2428static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2429 int level,
ac830fe1 2430 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2431 struct intel_wm_level *result)
6f5ddd17
VS		 2432{
2433 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2434 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2435 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2436
2437 /* WM1+ latency values stored in 0.5us units */
2438 if (level > 0) {
2439 pri_latency *= 5;
2440 spr_latency *= 5;
2441 cur_latency *= 5;
2442 }
2443
2444 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2445 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2446 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2447 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2448 result->enable = true;
2449}
2450
801bcfff
PZ		 2451static uint32_t
2452hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2453{
2454 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2455 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2456 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2457 u32 linetime, ips_linetime;
1f8eeabf 2458
801bcfff
PZ		 2459 if (!intel_crtc_active(crtc))
2460 return 0;
1011d8c4 2461
1f8eeabf
ED		 2462 /* The WM are computed with base on how long it takes to fill a single
2463 * row at the given clock rate, multiplied by 8.
2464 * */
85a02deb
PZ		 2465 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2466 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2467 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2468
801bcfff
PZ		 2469 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2470 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2471}
2472
12b134df
VS		 2473static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2474{
2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476
2477 if (IS_HASWELL(dev)) {
2478 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2479
2480 wm[0] = (sskpd >> 56) & 0xFF;
2481 if (wm[0] == 0)
2482 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2483 wm[1] = (sskpd >> 4) & 0xFF;
2484 wm[2] = (sskpd >> 12) & 0xFF;
2485 wm[3] = (sskpd >> 20) & 0x1FF;
2486 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2487 } else if (INTEL_INFO(dev)->gen >= 6) {
2488 uint32_t sskpd = I915_READ(MCH_SSKPD);
2489
2490 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2491 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2492 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2493 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2494 } else if (INTEL_INFO(dev)->gen >= 5) {
2495 uint32_t mltr = I915_READ(MLTR_ILK);
2496
2497 /* ILK primary LP0 latency is 700 ns */
2498 wm[0] = 7;
2499 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2500 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2501 }
2502}
2503
53615a5e
VS		 2504static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2505{
2506 /* ILK sprite LP0 latency is 1300 ns */
2507 if (INTEL_INFO(dev)->gen == 5)
2508 wm[0] = 13;
2509}
2510
2511static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2512{
2513 /* ILK cursor LP0 latency is 1300 ns */
2514 if (INTEL_INFO(dev)->gen == 5)
2515 wm[0] = 13;
2516
2517 /* WaDoubleCursorLP3Latency:ivb */
2518 if (IS_IVYBRIDGE(dev))
2519 wm[3] *= 2;
2520}
2521
ad0d6dc4 2522static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2523{
26ec971e
VS		 2524 /* how many WM levels are we expecting */
2525 if (IS_HASWELL(dev))
ad0d6dc4 2526 return 4;
26ec971e 2527 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2528 return 3;
26ec971e 2529 else
ad0d6dc4
VS		 2530 return 2;
2531}
2532
2533static void intel_print_wm_latency(struct drm_device *dev,
2534 const char *name,
2535 const uint16_t wm[5])
2536{
2537 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2538
2539 for (level = 0; level <= max_level; level++) {
2540 unsigned int latency = wm[level];
2541
2542 if (latency == 0) {
2543 DRM_ERROR("%s WM%d latency not provided\n",
2544 name, level);
2545 continue;
2546 }
2547
2548 /* WM1+ latency values in 0.5us units */
2549 if (level > 0)
2550 latency *= 5;
2551
2552 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2553 name, level, wm[level],
2554 latency / 10, latency % 10);
2555 }
2556}
2557
53615a5e
VS		 2558static void intel_setup_wm_latency(struct drm_device *dev)
2559{
2560 struct drm_i915_private *dev_priv = dev->dev_private;
2561
2562 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2563
2564 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2565 sizeof(dev_priv->wm.pri_latency));
2566 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2567 sizeof(dev_priv->wm.pri_latency));
2568
2569 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2570 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2571
2572 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2573 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2574 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2575}
2576
7c4a395f
VS		 2577static void hsw_compute_wm_parameters(struct drm_crtc *crtc,
2578 struct hsw_pipe_wm_parameters *p,
a485bfb8 2579 struct intel_wm_config *config)
1011d8c4 2580{
7c4a395f
VS		 2581 struct drm_device *dev = crtc->dev;
2582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2583 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2584 struct drm_plane *plane;
1011d8c4 2585
7c4a395f
VS		 2586 p->active = intel_crtc_active(crtc);
2587 if (p->active) {
801bcfff 2588 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2589 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2590 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2591 p->cur.bytes_per_pixel = 4;
37327abd 2592 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2593 p->cur.horiz_pixels = 64;
2594 /* TODO: for now, assume primary and cursor planes are always enabled. */
2595 p->pri.enabled = true;
2596 p->cur.enabled = true;
801bcfff
PZ		 2597 }
2598
7c4a395f 2599 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
a485bfb8 2600 config->num_pipes_active += intel_crtc_active(crtc);
7c4a395f 2601
801bcfff
PZ		 2602 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2603 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2604
7c4a395f
VS		 2605 if (intel_plane->pipe == pipe)
2606 p->spr = intel_plane->wm;
cca32e9a 2607
a485bfb8
VS		 2608 config->sprites_enabled |= intel_plane->wm.enabled;
2609 config->sprites_scaled |= intel_plane->wm.scaled;
cca32e9a 2610 }
801bcfff
PZ		 2611}
2612
0b2ae6d7
VS		 2613/* Compute new watermarks for the pipe */
2614static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
2615 const struct hsw_pipe_wm_parameters *params,
2616 struct intel_pipe_wm *pipe_wm)
2617{
2618 struct drm_device *dev = crtc->dev;
2619 struct drm_i915_private *dev_priv = dev->dev_private;
2620 int level, max_level = ilk_wm_max_level(dev);
2621 /* LP0 watermark maximums depend on this pipe alone */
2622 struct intel_wm_config config = {
2623 .num_pipes_active = 1,
2624 .sprites_enabled = params->spr.enabled,
2625 .sprites_scaled = params->spr.scaled,
2626 };
2627 struct hsw_wm_maximums max;
2628
0b2ae6d7 2629 /* LP0 watermarks always use 1/2 DDB partitioning */
34982fe1 2630 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
0b2ae6d7
VS		 2631
2632 for (level = 0; level <= max_level; level++)
2633 ilk_compute_wm_level(dev_priv, level, params,
2634 &pipe_wm->wm[level]);
2635
2636 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
2637
2638 /* At least LP0 must be valid */
d9395655 2639 return ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]);
0b2ae6d7
VS		 2640}
2641
2642/*
2643 * Merge the watermarks from all active pipes for a specific level.
2644 */
2645static void ilk_merge_wm_level(struct drm_device *dev,
2646 int level,
2647 struct intel_wm_level *ret_wm)
2648{
2649 const struct intel_crtc *intel_crtc;
2650
2651 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2652 const struct intel_wm_level *wm =
2653 &intel_crtc->wm.active.wm[level];
2654
2655 if (!wm->enable)
2656 return;
2657
2658 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2659 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2660 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2661 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2662 }
2663
2664 ret_wm->enable = true;
2665}
2666
2667/*
2668 * Merge all low power watermarks for all active pipes.
2669 */
2670static void ilk_wm_merge(struct drm_device *dev,
2671 const struct hsw_wm_maximums *max,
2672 struct intel_pipe_wm *merged)
2673{
2674 int level, max_level = ilk_wm_max_level(dev);
2675
2676 merged->fbc_wm_enabled = true;
2677
2678 /* merge each WM1+ level */
2679 for (level = 1; level <= max_level; level++) {
2680 struct intel_wm_level *wm = &merged->wm[level];
2681
2682 ilk_merge_wm_level(dev, level, wm);
2683
d9395655 2684 if (!ilk_validate_wm_level(level, max, wm))
0b2ae6d7
VS		 2685 break;
2686
2687 /*
2688 * The spec says it is preferred to disable
2689 * FBC WMs instead of disabling a WM level.
2690 */
2691 if (wm->fbc_val > max->fbc) {
2692 merged->fbc_wm_enabled = false;
2693 wm->fbc_val = 0;
2694 }
2695 }
2696}
2697
b380ca3c
VS		 2698static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2699{
2700 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2701 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2702}
2703
801bcfff 2704static void hsw_compute_wm_results(struct drm_device *dev,
0362c781 2705 const struct intel_pipe_wm *merged,
609cedef 2706 enum intel_ddb_partitioning partitioning,
801bcfff
PZ		 2707 struct hsw_wm_values *results)
2708{
0b2ae6d7
VS		 2709 struct intel_crtc *intel_crtc;
2710 int level, wm_lp;
cca32e9a 2711
0362c781 2712 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2713 results->partitioning = partitioning;
cca32e9a 2714
0b2ae6d7 2715 /* LP1+ register values */
cca32e9a 2716 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2717 const struct intel_wm_level *r;
801bcfff 2718
b380ca3c 2719 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2720
0362c781 2721 r = &merged->wm[level];
0b2ae6d7 2722 if (!r->enable)
cca32e9a
PZ		 2723 break;
2724
cca32e9a
PZ		 2725 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2726 r->fbc_val,
2727 r->pri_val,
2728 r->cur_val);
2729 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2730 }
801bcfff 2731
0b2ae6d7
VS		 2732 /* LP0 register values */
2733 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, base.head) {
2734 enum pipe pipe = intel_crtc->pipe;
2735 const struct intel_wm_level *r =
2736 &intel_crtc->wm.active.wm[0];
2737
2738 if (WARN_ON(!r->enable))
2739 continue;
2740
2741 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2742
0b2ae6d7
VS		 2743 results->wm_pipe[pipe] =
2744 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2745 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2746 r->cur_val;
801bcfff
PZ		 2747 }
2748}
2749
861f3389
PZ		 2750/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2751 * case both are at the same level. Prefer r1 in case they're the same. */
198a1e9b
VS		 2752static struct intel_pipe_wm *hsw_find_best_result(struct drm_device *dev,
2753 struct intel_pipe_wm *r1,
2754 struct intel_pipe_wm *r2)
861f3389 2755{
198a1e9b
VS		 2756 int level, max_level = ilk_wm_max_level(dev);
2757 int level1 = 0, level2 = 0;
861f3389 2758
198a1e9b
VS		 2759 for (level = 1; level <= max_level; level++) {
2760 if (r1->wm[level].enable)
2761 level1 = level;
2762 if (r2->wm[level].enable)
2763 level2 = level;
861f3389
PZ		 2764 }
2765
198a1e9b
VS		 2766 if (level1 == level2) {
2767 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2768 return r2;
2769 else
2770 return r1;
198a1e9b 2771 } else if (level1 > level2) {
861f3389
PZ		 2772 return r1;
2773 } else {
2774 return r2;
2775 }
2776}
2777
49a687c4
VS		 2778/* dirty bits used to track which watermarks need changes */
2779#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2780#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2781#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2782#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2783#define WM_DIRTY_FBC (1 << 24)
2784#define WM_DIRTY_DDB (1 << 25)
2785
2786static unsigned int ilk_compute_wm_dirty(struct drm_device *dev,
2787 const struct hsw_wm_values *old,
2788 const struct hsw_wm_values *new)
2789{
2790 unsigned int dirty = 0;
2791 enum pipe pipe;
2792 int wm_lp;
2793
2794 for_each_pipe(pipe) {
2795 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2796 dirty |= WM_DIRTY_LINETIME(pipe);
2797 /* Must disable LP1+ watermarks too */
2798 dirty |= WM_DIRTY_LP_ALL;
2799 }
2800
2801 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2802 dirty |= WM_DIRTY_PIPE(pipe);
2803 /* Must disable LP1+ watermarks too */
2804 dirty |= WM_DIRTY_LP_ALL;
2805 }
2806 }
2807
2808 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2809 dirty |= WM_DIRTY_FBC;
2810 /* Must disable LP1+ watermarks too */
2811 dirty |= WM_DIRTY_LP_ALL;
2812 }
2813
2814 if (old->partitioning != new->partitioning) {
2815 dirty |= WM_DIRTY_DDB;
2816 /* Must disable LP1+ watermarks too */
2817 dirty |= WM_DIRTY_LP_ALL;
2818 }
2819
2820 /* LP1+ watermarks already deemed dirty, no need to continue */
2821 if (dirty & WM_DIRTY_LP_ALL)
2822 return dirty;
2823
2824 /* Find the lowest numbered LP1+ watermark in need of an update... */
2825 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2826 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2827 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2828 break;
2829 }
2830
2831 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2832 for (; wm_lp <= 3; wm_lp++)
2833 dirty |= WM_DIRTY_LP(wm_lp);
2834
2835 return dirty;
2836}
2837
801bcfff
PZ		 2838/*
2839 * The spec says we shouldn't write when we don't need, because every write
2840 * causes WMs to be re-evaluated, expending some power.
2841 */
2842static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
609cedef 2843 struct hsw_wm_values *results)
801bcfff 2844{
243e6a44 2845 struct hsw_wm_values *previous = &dev_priv->wm.hw;
49a687c4 2846 unsigned int dirty;
801bcfff 2847 uint32_t val;
801bcfff 2848
243e6a44 2849 dirty = ilk_compute_wm_dirty(dev_priv->dev, previous, results);
49a687c4 2850 if (!dirty)
801bcfff
PZ		 2851 return;
2852
243e6a44 2853 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != 0)
801bcfff 2854 I915_WRITE(WM3_LP_ILK, 0);
243e6a44 2855 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != 0)
801bcfff 2856 I915_WRITE(WM2_LP_ILK, 0);
243e6a44 2857 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != 0)
801bcfff
PZ		 2858 I915_WRITE(WM1_LP_ILK, 0);
2859
49a687c4 2860 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2861 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2862 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2863 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2864 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2865 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2866
49a687c4 2867 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2868 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2869 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2870 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2871 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2872 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2873
49a687c4 2874 if (dirty & WM_DIRTY_DDB) {
801bcfff 2875 val = I915_READ(WM_MISC);
609cedef 2876 if (results->partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2877 val &= ~WM_MISC_DATA_PARTITION_5_6;
2878 else
2879 val |= WM_MISC_DATA_PARTITION_5_6;
2880 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2881 }
2882
49a687c4 2883 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2884 val = I915_READ(DISP_ARB_CTL);
2885 if (results->enable_fbc_wm)
2886 val &= ~DISP_FBC_WM_DIS;
2887 else
2888 val |= DISP_FBC_WM_DIS;
2889 I915_WRITE(DISP_ARB_CTL, val);
2890 }
2891
243e6a44 2892 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp_spr[0] != results->wm_lp_spr[0])
801bcfff 2893 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
243e6a44 2894 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
801bcfff 2895 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
243e6a44 2896 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
801bcfff
PZ		 2897 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2898
49a687c4 2899 if (dirty & WM_DIRTY_LP(1) && results->wm_lp[0] != 0)
801bcfff 2900 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
49a687c4 2901 if (dirty & WM_DIRTY_LP(2) && results->wm_lp[1] != 0)
801bcfff 2902 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
49a687c4 2903 if (dirty & WM_DIRTY_LP(3) && results->wm_lp[2] != 0)
801bcfff 2904 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2905
2906 dev_priv->wm.hw = *results;
801bcfff
PZ		 2907}
2908
46ba614c 2909static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2910{
7c4a395f 2911 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 2912 struct drm_device *dev = crtc->dev;
801bcfff 2913 struct drm_i915_private *dev_priv = dev->dev_private;
a485bfb8 2914 struct hsw_wm_maximums max;
7c4a395f 2915 struct hsw_pipe_wm_parameters params = {};
198a1e9b 2916 struct hsw_wm_values results = {};
77c122bc 2917 enum intel_ddb_partitioning partitioning;
7c4a395f 2918 struct intel_pipe_wm pipe_wm = {};
198a1e9b 2919 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 2920 struct intel_wm_config config = {};
7c4a395f 2921
a485bfb8 2922 hsw_compute_wm_parameters(crtc, &params, &config);
7c4a395f
VS		 2923
2924 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
2925
2926 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
2927 return;
861f3389 2928
7c4a395f 2929 intel_crtc->wm.active = pipe_wm;
861f3389 2930
34982fe1 2931 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
a485bfb8
VS		 2932 ilk_wm_merge(dev, &max, &lp_wm_1_2);
2933
2934 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 2935 if (INTEL_INFO(dev)->gen >= 7 &&
2936 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 2937 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
a485bfb8 2938 ilk_wm_merge(dev, &max, &lp_wm_5_6);
0362c781 2939
198a1e9b 2940 best_lp_wm = hsw_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 2941 } else {
198a1e9b 2942 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 2943 }
2944
198a1e9b 2945 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 2946 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2947
609cedef
VS		 2948 hsw_compute_wm_results(dev, best_lp_wm, partitioning, &results);
2949
2950 hsw_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 2951}
2952
adf3d35e
VS		 2953static void haswell_update_sprite_wm(struct drm_plane *plane,
2954 struct drm_crtc *crtc,
526682e9 2955 uint32_t sprite_width, int pixel_size,
bdd57d03 2956 bool enabled, bool scaled)
526682e9 2957{
adf3d35e 2958 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2959
adf3d35e
VS		 2960 intel_plane->wm.enabled = enabled;
2961 intel_plane->wm.scaled = scaled;
2962 intel_plane->wm.horiz_pixels = sprite_width;
2963 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2964
46ba614c 2965 haswell_update_wm(crtc);
526682e9
PZ		 2966}
2967
b445e3b0
ED		 2968static bool
2969sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2970 uint32_t sprite_width, int pixel_size,
2971 const struct intel_watermark_params *display,
2972 int display_latency_ns, int *sprite_wm)
2973{
2974 struct drm_crtc *crtc;
2975 int clock;
2976 int entries, tlb_miss;
2977
2978 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2979 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2980 *sprite_wm = display->guard_size;
2981 return false;
2982 }
2983
241bfc38 2984 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 2985
2986 /* Use the small buffer method to calculate the sprite watermark */
2987 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2988 tlb_miss = display->fifo_size*display->cacheline_size -
2989 sprite_width * 8;
2990 if (tlb_miss > 0)
2991 entries += tlb_miss;
2992 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2993 *sprite_wm = entries + display->guard_size;
2994 if (*sprite_wm > (int)display->max_wm)
2995 *sprite_wm = display->max_wm;
2996
2997 return true;
2998}
2999
3000static bool
3001sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
3002 uint32_t sprite_width, int pixel_size,
3003 const struct intel_watermark_params *display,
3004 int latency_ns, int *sprite_wm)
3005{
3006 struct drm_crtc *crtc;
3007 unsigned long line_time_us;
3008 int clock;
3009 int line_count, line_size;
3010 int small, large;
3011 int entries;
3012
3013 if (!latency_ns) {
3014 *sprite_wm = 0;
3015 return false;
3016 }
3017
3018 crtc = intel_get_crtc_for_plane(dev, plane);
241bfc38 3019 clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock;
b445e3b0
ED		 3020 if (!clock) {
3021 *sprite_wm = 0;
3022 return false;
3023 }
3024
3025 line_time_us = (sprite_width * 1000) / clock;
3026 if (!line_time_us) {
3027 *sprite_wm = 0;
3028 return false;
3029 }
3030
3031 line_count = (latency_ns / line_time_us + 1000) / 1000;
3032 line_size = sprite_width * pixel_size;
3033
3034 /* Use the minimum of the small and large buffer method for primary */
3035 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
3036 large = line_count * line_size;
3037
3038 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
3039 *sprite_wm = entries + display->guard_size;
3040
3041 return *sprite_wm > 0x3ff ? false : true;
3042}
3043
adf3d35e
VS		 3044static void sandybridge_update_sprite_wm(struct drm_plane *plane,
3045 struct drm_crtc *crtc,
4c4ff43a 3046 uint32_t sprite_width, int pixel_size,
39db4a4d 3047 bool enabled, bool scaled)
b445e3b0 3048{
adf3d35e 3049 struct drm_device *dev = plane->dev;
b445e3b0 3050 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 3051 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 3052 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 3053 u32 val;
3054 int sprite_wm, reg;
3055 int ret;
3056
39db4a4d 3057 if (!enabled)
4c4ff43a
PZ		 3058 return;
3059
b445e3b0
ED		 3060 switch (pipe) {
3061 case 0:
3062 reg = WM0_PIPEA_ILK;
3063 break;
3064 case 1:
3065 reg = WM0_PIPEB_ILK;
3066 break;
3067 case 2:
3068 reg = WM0_PIPEC_IVB;
3069 break;
3070 default:
3071 return; /* bad pipe */
3072 }
3073
3074 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3075 &sandybridge_display_wm_info,
3076 latency, &sprite_wm);
3077 if (!ret) {
84f44ce7
VS		 3078 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3079 pipe_name(pipe));
b445e3b0
ED		 3080 return;
3081 }
3082
3083 val = I915_READ(reg);
3084 val &= ~WM0_PIPE_SPRITE_MASK;
3085 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3086 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3087
3088
3089 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3090 pixel_size,
3091 &sandybridge_display_srwm_info,
b0aea5dc 3092 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3093 &sprite_wm);
3094 if (!ret) {
84f44ce7
VS		 3095 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3096 pipe_name(pipe));
b445e3b0
ED		 3097 return;
3098 }
3099 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3100
3101 /* Only IVB has two more LP watermarks for sprite */
3102 if (!IS_IVYBRIDGE(dev))
3103 return;
3104
3105 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3106 pixel_size,
3107 &sandybridge_display_srwm_info,
b0aea5dc 3108 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3109 &sprite_wm);
3110 if (!ret) {
84f44ce7
VS		 3111 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3112 pipe_name(pipe));
b445e3b0
ED		 3113 return;
3114 }
3115 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3116
3117 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3118 pixel_size,
3119 &sandybridge_display_srwm_info,
b0aea5dc 3120 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3121 &sprite_wm);
3122 if (!ret) {
84f44ce7
VS		 3123 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3124 pipe_name(pipe));
b445e3b0
ED		 3125 return;
3126 }
3127 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3128}
3129
243e6a44
VS		 3130static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3131{
3132 struct drm_device *dev = crtc->dev;
3133 struct drm_i915_private *dev_priv = dev->dev_private;
3134 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3135 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3136 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3137 enum pipe pipe = intel_crtc->pipe;
3138 static const unsigned int wm0_pipe_reg[] = {
3139 [PIPE_A] = WM0_PIPEA_ILK,
3140 [PIPE_B] = WM0_PIPEB_ILK,
3141 [PIPE_C] = WM0_PIPEC_IVB,
3142 };
3143
3144 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
3145 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3146
3147 if (intel_crtc_active(crtc)) {
3148 u32 tmp = hw->wm_pipe[pipe];
3149
3150 /*
3151 * For active pipes LP0 watermark is marked as
3152 * enabled, and LP1+ watermaks as disabled since
3153 * we can't really reverse compute them in case
3154 * multiple pipes are active.
3155 */
3156 active->wm[0].enable = true;
3157 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3158 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3159 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3160 active->linetime = hw->wm_linetime[pipe];
3161 } else {
3162 int level, max_level = ilk_wm_max_level(dev);
3163
3164 /*
3165 * For inactive pipes, all watermark levels
3166 * should be marked as enabled but zeroed,
3167 * which is what we'd compute them to.
3168 */
3169 for (level = 0; level <= max_level; level++)
3170 active->wm[level].enable = true;
3171 }
3172}
3173
3174void ilk_wm_get_hw_state(struct drm_device *dev)
3175{
3176 struct drm_i915_private *dev_priv = dev->dev_private;
3177 struct hsw_wm_values *hw = &dev_priv->wm.hw;
3178 struct drm_crtc *crtc;
3179
3180 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3181 ilk_pipe_wm_get_hw_state(crtc);
3182
3183 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3184 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3185 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3186
3187 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
3188 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3189 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3190
3191 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3192 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3193
3194 hw->enable_fbc_wm =
3195 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3196}
3197
b445e3b0
ED		 3198/**
3199 * intel_update_watermarks - update FIFO watermark values based on current modes
3200 *
3201 * Calculate watermark values for the various WM regs based on current mode
3202 * and plane configuration.
3203 *
3204 * There are several cases to deal with here:
3205 * - normal (i.e. non-self-refresh)
3206 * - self-refresh (SR) mode
3207 * - lines are large relative to FIFO size (buffer can hold up to 2)
3208 * - lines are small relative to FIFO size (buffer can hold more than 2
3209 * lines), so need to account for TLB latency
3210 *
3211 * The normal calculation is:
3212 * watermark = dotclock * bytes per pixel * latency
3213 * where latency is platform & configuration dependent (we assume pessimal
3214 * values here).
3215 *
3216 * The SR calculation is:
3217 * watermark = (trunc(latency/line time)+1) * surface width *
3218 * bytes per pixel
3219 * where
3220 * line time = htotal / dotclock
3221 * surface width = hdisplay for normal plane and 64 for cursor
3222 * and latency is assumed to be high, as above.
3223 *
3224 * The final value programmed to the register should always be rounded up,
3225 * and include an extra 2 entries to account for clock crossings.
3226 *
3227 * We don't use the sprite, so we can ignore that. And on Crestline we have
3228 * to set the non-SR watermarks to 8.
3229 */
46ba614c 3230void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3231{
46ba614c 3232 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3233
3234 if (dev_priv->display.update_wm)
46ba614c 3235 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3236}
3237
adf3d35e
VS		 3238void intel_update_sprite_watermarks(struct drm_plane *plane,
3239 struct drm_crtc *crtc,
4c4ff43a 3240 uint32_t sprite_width, int pixel_size,
39db4a4d 3241 bool enabled, bool scaled)
b445e3b0 3242{
adf3d35e 3243 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3244
3245 if (dev_priv->display.update_sprite_wm)
adf3d35e 3246 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3247 pixel_size, enabled, scaled);
b445e3b0
ED		 3248}
3249
2b4e57bd
ED		 3250static struct drm_i915_gem_object *
3251intel_alloc_context_page(struct drm_device *dev)
3252{
3253 struct drm_i915_gem_object *ctx;
3254 int ret;
3255
3256 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3257
3258 ctx = i915_gem_alloc_object(dev, 4096);
3259 if (!ctx) {
3260 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3261 return NULL;
3262 }
3263
c37e2204 3264 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3265 if (ret) {
3266 DRM_ERROR("failed to pin power context: %d\n", ret);
3267 goto err_unref;
3268 }
3269
3270 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3271 if (ret) {
3272 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3273 goto err_unpin;
3274 }
3275
3276 return ctx;
3277
3278err_unpin:
3279 i915_gem_object_unpin(ctx);
3280err_unref:
3281 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3282 return NULL;
3283}
3284
9270388e
DV		 3285/**
3286 * Lock protecting IPS related data structures
9270388e
DV		 3287 */
3288DEFINE_SPINLOCK(mchdev_lock);
3289
3290/* Global for IPS driver to get at the current i915 device. Protected by
3291 * mchdev_lock. */
3292static struct drm_i915_private *i915_mch_dev;
3293
2b4e57bd
ED		 3294bool ironlake_set_drps(struct drm_device *dev, u8 val)
3295{
3296 struct drm_i915_private *dev_priv = dev->dev_private;
3297 u16 rgvswctl;
3298
9270388e
DV		 3299 assert_spin_locked(&mchdev_lock);
3300
2b4e57bd
ED		 3301 rgvswctl = I915_READ16(MEMSWCTL);
3302 if (rgvswctl & MEMCTL_CMD_STS) {
3303 DRM_DEBUG("gpu busy, RCS change rejected\n");
3304 return false; /* still busy with another command */
3305 }
3306
3307 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3308 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3309 I915_WRITE16(MEMSWCTL, rgvswctl);
3310 POSTING_READ16(MEMSWCTL);
3311
3312 rgvswctl |= MEMCTL_CMD_STS;
3313 I915_WRITE16(MEMSWCTL, rgvswctl);
3314
3315 return true;
3316}
3317
8090c6b9 3318static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3319{
3320 struct drm_i915_private *dev_priv = dev->dev_private;
3321 u32 rgvmodectl = I915_READ(MEMMODECTL);
3322 u8 fmax, fmin, fstart, vstart;
3323
9270388e
DV		 3324 spin_lock_irq(&mchdev_lock);
3325
2b4e57bd
ED		 3326 /* Enable temp reporting */
3327 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3328 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3329
3330 /* 100ms RC evaluation intervals */
3331 I915_WRITE(RCUPEI, 100000);
3332 I915_WRITE(RCDNEI, 100000);
3333
3334 /* Set max/min thresholds to 90ms and 80ms respectively */
3335 I915_WRITE(RCBMAXAVG, 90000);
3336 I915_WRITE(RCBMINAVG, 80000);
3337
3338 I915_WRITE(MEMIHYST, 1);
3339
3340 /* Set up min, max, and cur for interrupt handling */
3341 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3342 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3343 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3344 MEMMODE_FSTART_SHIFT;
3345
3346 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3347 PXVFREQ_PX_SHIFT;
3348
20e4d407
DV		 3349 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3350 dev_priv->ips.fstart = fstart;
2b4e57bd 3351
20e4d407
DV		 3352 dev_priv->ips.max_delay = fstart;
3353 dev_priv->ips.min_delay = fmin;
3354 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3355
3356 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3357 fmax, fmin, fstart);
3358
3359 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3360
3361 /*
3362 * Interrupts will be enabled in ironlake_irq_postinstall
3363 */
3364
3365 I915_WRITE(VIDSTART, vstart);
3366 POSTING_READ(VIDSTART);
3367
3368 rgvmodectl |= MEMMODE_SWMODE_EN;
3369 I915_WRITE(MEMMODECTL, rgvmodectl);
3370
9270388e 3371 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3372 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3373 mdelay(1);
2b4e57bd
ED		 3374
3375 ironlake_set_drps(dev, fstart);
3376
20e4d407 3377 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3378 I915_READ(0x112e0);
20e4d407
DV		 3379 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3380 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3381 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3382
3383 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3384}
3385
8090c6b9 3386static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3387{
3388 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3389 u16 rgvswctl;
3390
3391 spin_lock_irq(&mchdev_lock);
3392
3393 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3394
3395 /* Ack interrupts, disable EFC interrupt */
3396 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3397 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3398 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3399 I915_WRITE(DEIIR, DE_PCU_EVENT);
3400 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3401
3402 /* Go back to the starting frequency */
20e4d407 3403 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3404 mdelay(1);
2b4e57bd
ED		 3405 rgvswctl |= MEMCTL_CMD_STS;
3406 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3407 mdelay(1);
2b4e57bd 3408
9270388e 3409 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3410}
3411
acbe9475
DV		 3412/* There's a funny hw issue where the hw returns all 0 when reading from
3413 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3414 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3415 * all limits and the gpu stuck at whatever frequency it is at atm).
3416 */
65bccb5c 3417static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3418{
7b9e0ae6 3419 u32 limits;
2b4e57bd 3420
7b9e0ae6 3421 limits = 0;
c6a828d3
DV		 3422
3423 if (*val >= dev_priv->rps.max_delay)
3424 *val = dev_priv->rps.max_delay;
3425 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3426
3427 /* Only set the down limit when we've reached the lowest level to avoid
3428 * getting more interrupts, otherwise leave this clear. This prevents a
3429 * race in the hw when coming out of rc6: There's a tiny window where
3430 * the hw runs at the minimal clock before selecting the desired
3431 * frequency, if the down threshold expires in that window we will not
3432 * receive a down interrupt. */
c6a828d3
DV		 3433 if (*val <= dev_priv->rps.min_delay) {
3434 *val = dev_priv->rps.min_delay;
3435 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3436 }
3437
3438 return limits;
3439}
3440
dd75fdc8
CW		 3441static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3442{
3443 int new_power;
3444
3445 new_power = dev_priv->rps.power;
3446 switch (dev_priv->rps.power) {
3447 case LOW_POWER:
3448 if (val > dev_priv->rps.rpe_delay + 1 && val > dev_priv->rps.cur_delay)
3449 new_power = BETWEEN;
3450 break;
3451
3452 case BETWEEN:
3453 if (val <= dev_priv->rps.rpe_delay && val < dev_priv->rps.cur_delay)
3454 new_power = LOW_POWER;
3455 else if (val >= dev_priv->rps.rp0_delay && val > dev_priv->rps.cur_delay)
3456 new_power = HIGH_POWER;
3457 break;
3458
3459 case HIGH_POWER:
3460 if (val < (dev_priv->rps.rp1_delay + dev_priv->rps.rp0_delay) >> 1 && val < dev_priv->rps.cur_delay)
3461 new_power = BETWEEN;
3462 break;
3463 }
3464 /* Max/min bins are special */
3465 if (val == dev_priv->rps.min_delay)
3466 new_power = LOW_POWER;
3467 if (val == dev_priv->rps.max_delay)
3468 new_power = HIGH_POWER;
3469 if (new_power == dev_priv->rps.power)
3470 return;
3471
3472 /* Note the units here are not exactly 1us, but 1280ns. */
3473 switch (new_power) {
3474 case LOW_POWER:
3475 /* Upclock if more than 95% busy over 16ms */
3476 I915_WRITE(GEN6_RP_UP_EI, 12500);
3477 I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800);
3478
3479 /* Downclock if less than 85% busy over 32ms */
3480 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3481 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250);
3482
3483 I915_WRITE(GEN6_RP_CONTROL,
3484 GEN6_RP_MEDIA_TURBO |
3485 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3486 GEN6_RP_MEDIA_IS_GFX |
3487 GEN6_RP_ENABLE |
3488 GEN6_RP_UP_BUSY_AVG |
3489 GEN6_RP_DOWN_IDLE_AVG);
3490 break;
3491
3492 case BETWEEN:
3493 /* Upclock if more than 90% busy over 13ms */
3494 I915_WRITE(GEN6_RP_UP_EI, 10250);
3495 I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225);
3496
3497 /* Downclock if less than 75% busy over 32ms */
3498 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3499 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750);
3500
3501 I915_WRITE(GEN6_RP_CONTROL,
3502 GEN6_RP_MEDIA_TURBO |
3503 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3504 GEN6_RP_MEDIA_IS_GFX |
3505 GEN6_RP_ENABLE |
3506 GEN6_RP_UP_BUSY_AVG |
3507 GEN6_RP_DOWN_IDLE_AVG);
3508 break;
3509
3510 case HIGH_POWER:
3511 /* Upclock if more than 85% busy over 10ms */
3512 I915_WRITE(GEN6_RP_UP_EI, 8000);
3513 I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800);
3514
3515 /* Downclock if less than 60% busy over 32ms */
3516 I915_WRITE(GEN6_RP_DOWN_EI, 25000);
3517 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000);
3518
3519 I915_WRITE(GEN6_RP_CONTROL,
3520 GEN6_RP_MEDIA_TURBO |
3521 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3522 GEN6_RP_MEDIA_IS_GFX |
3523 GEN6_RP_ENABLE |
3524 GEN6_RP_UP_BUSY_AVG |
3525 GEN6_RP_DOWN_IDLE_AVG);
3526 break;
3527 }
3528
3529 dev_priv->rps.power = new_power;
3530 dev_priv->rps.last_adj = 0;
3531}
3532
20b46e59
DV		 3533void gen6_set_rps(struct drm_device *dev, u8 val)
3534{
3535 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3536 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3537
4fc688ce 3538 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3539 WARN_ON(val > dev_priv->rps.max_delay);
3540 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3541
c6a828d3 3542 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3543 return;
3544
dd75fdc8
CW		 3545 gen6_set_rps_thresholds(dev_priv, val);
3546
92bd1bf0
RV		 3547 if (IS_HASWELL(dev))
3548 I915_WRITE(GEN6_RPNSWREQ,
3549 HSW_FREQUENCY(val));
3550 else
3551 I915_WRITE(GEN6_RPNSWREQ,
3552 GEN6_FREQUENCY(val) |
3553 GEN6_OFFSET(0) |
3554 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3555
3556 /* Make sure we continue to get interrupts
3557 * until we hit the minimum or maximum frequencies.
3558 */
3559 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3560
d5570a72
BW		 3561 POSTING_READ(GEN6_RPNSWREQ);
3562
c6a828d3 3563 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3564
3565 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3566}
3567
b29c19b6
CW		 3568void gen6_rps_idle(struct drm_i915_private *dev_priv)
3569{
3570 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3571 if (dev_priv->rps.enabled) {
3572 if (dev_priv->info->is_valleyview)
3573 valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3574 else
3575 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
3576 dev_priv->rps.last_adj = 0;
3577 }
b29c19b6
CW		 3578 mutex_unlock(&dev_priv->rps.hw_lock);
3579}
3580
3581void gen6_rps_boost(struct drm_i915_private *dev_priv)
3582{
3583 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c
CW		 3584 if (dev_priv->rps.enabled) {
3585 if (dev_priv->info->is_valleyview)
3586 valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3587 else
3588 gen6_set_rps(dev_priv->dev, dev_priv->rps.max_delay);
3589 dev_priv->rps.last_adj = 0;
3590 }
b29c19b6
CW		 3591 mutex_unlock(&dev_priv->rps.hw_lock);
3592}
3593
80814ae4
VS		 3594/*
3595 * Wait until the previous freq change has completed,
3596 * or the timeout elapsed, and then update our notion
3597 * of the current GPU frequency.
3598 */
3599static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3600{
80814ae4
VS		 3601 u32 pval;
3602
3603 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3604
e8474409
VS		 3605 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3606 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3607
3608 pval >>= 8;
3609
3610 if (pval != dev_priv->rps.cur_delay)
3611 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3612 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3613 dev_priv->rps.cur_delay,
3614 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3615
3616 dev_priv->rps.cur_delay = pval;
3617}
3618
0a073b84
JB		 3619void valleyview_set_rps(struct drm_device *dev, u8 val)
3620{
3621 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3622
3623 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3624
3625 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3626 WARN_ON(val > dev_priv->rps.max_delay);
3627 WARN_ON(val < dev_priv->rps.min_delay);
3628
80814ae4
VS		 3629 vlv_update_rps_cur_delay(dev_priv);
3630
73008b98 3631 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3632 vlv_gpu_freq(dev_priv->mem_freq,
3633 dev_priv->rps.cur_delay),
73008b98
VS		 3634 dev_priv->rps.cur_delay,
3635 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3636
3637 if (val == dev_priv->rps.cur_delay)
3638 return;
3639
ae99258f 3640 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3641
80814ae4 3642 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3643
3644 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3645}
3646
44fc7d5c 3647static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3648{
3649 struct drm_i915_private *dev_priv = dev->dev_private;
3650
2b4e57bd 3651 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3652 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3653 /* Complete PM interrupt masking here doesn't race with the rps work
3654 * item again unmasking PM interrupts because that is using a different
3655 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3656 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3657
59cdb63d 3658 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3659 dev_priv->rps.pm_iir = 0;
59cdb63d 3660 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3661
4848405c 3662 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3663}
3664
44fc7d5c 3665static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3666{
3667 struct drm_i915_private *dev_priv = dev->dev_private;
3668
3669 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3670 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3671
44fc7d5c
DV		 3672 gen6_disable_rps_interrupts(dev);
3673}
3674
3675static void valleyview_disable_rps(struct drm_device *dev)
3676{
3677 struct drm_i915_private *dev_priv = dev->dev_private;
3678
3679 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3680
44fc7d5c 3681 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3682
3683 if (dev_priv->vlv_pctx) {
3684 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3685 dev_priv->vlv_pctx = NULL;
3686 }
d20d4f0c
JB		 3687}
3688
dc39fff7
BW		 3689static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
3690{
3691 if (IS_GEN6(dev))
3692 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3693
3694 if (IS_HASWELL(dev))
3695 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
3696
3697 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
3698 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3699 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3700 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
3701}
3702
2b4e57bd
ED		 3703int intel_enable_rc6(const struct drm_device *dev)
3704{
eb4926e4
DL		 3705 /* No RC6 before Ironlake */
3706 if (INTEL_INFO(dev)->gen < 5)
3707 return 0;
3708
456470eb 3709 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3710 if (i915_enable_rc6 >= 0)
3711 return i915_enable_rc6;
3712
6567d748
CW		 3713 /* Disable RC6 on Ironlake */
3714 if (INTEL_INFO(dev)->gen == 5)
3715 return 0;
2b4e57bd 3716
dc39fff7 3717 if (IS_HASWELL(dev))
4a637c2c 3718 return INTEL_RC6_ENABLE;
2b4e57bd 3719
456470eb 3720 /* snb/ivb have more than one rc6 state. */
dc39fff7 3721 if (INTEL_INFO(dev)->gen == 6)
2b4e57bd 3722 return INTEL_RC6_ENABLE;
456470eb 3723
2b4e57bd
ED		 3724 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3725}
3726
44fc7d5c
DV		 3727static void gen6_enable_rps_interrupts(struct drm_device *dev)
3728{
3729 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3730 u32 enabled_intrs;
44fc7d5c
DV		 3731
3732 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3733 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3734 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3735 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3736 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3737
fd547d25 3738 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3739 enabled_intrs = GEN6_PM_RPS_EVENTS;
3740
3741 /* IVB and SNB hard hangs on looping batchbuffer
3742 * if GEN6_PM_UP_EI_EXPIRED is masked.
3743 */
3744 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3745 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3746
3747 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3748}
3749
79f5b2c7 3750static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3751{
79f5b2c7 3752 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3753 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3754 u32 rp_state_cap;
3755 u32 gt_perf_status;
31643d54 3756 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3757 u32 gtfifodbg;
2b4e57bd 3758 int rc6_mode;
42c0526c 3759 int i, ret;
2b4e57bd 3760
4fc688ce 3761 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3762
2b4e57bd
ED		 3763 /* Here begins a magic sequence of register writes to enable
3764 * auto-downclocking.
3765 *
3766 * Perhaps there might be some value in exposing these to
3767 * userspace...
3768 */
3769 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3770
3771 /* Clear the DBG now so we don't confuse earlier errors */
3772 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3773 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3774 I915_WRITE(GTFIFODBG, gtfifodbg);
3775 }
3776
3777 gen6_gt_force_wake_get(dev_priv);
3778
7b9e0ae6
CW		 3779 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3780 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3781
31c77388
BW		 3782 /* In units of 50MHz */
3783 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
dd75fdc8
CW		 3784 dev_priv->rps.min_delay = (rp_state_cap >> 16) & 0xff;
3785 dev_priv->rps.rp1_delay = (rp_state_cap >> 8) & 0xff;
3786 dev_priv->rps.rp0_delay = (rp_state_cap >> 0) & 0xff;
3787 dev_priv->rps.rpe_delay = dev_priv->rps.rp1_delay;
c6a828d3 3788 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3789
2b4e57bd
ED		 3790 /* disable the counters and set deterministic thresholds */
3791 I915_WRITE(GEN6_RC_CONTROL, 0);
3792
3793 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3794 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3795 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3796 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3797 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3798
b4519513
CW		 3799 for_each_ring(ring, dev_priv, i)
3800 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3801
3802 I915_WRITE(GEN6_RC_SLEEP, 0);
3803 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3804 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3805 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3806 else
3807 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3808 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3809 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3810
5a7dc92a 3811 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3812 rc6_mode = intel_enable_rc6(dev_priv->dev);
3813 if (rc6_mode & INTEL_RC6_ENABLE)
3814 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3815
5a7dc92a
ED		 3816 /* We don't use those on Haswell */
3817 if (!IS_HASWELL(dev)) {
3818 if (rc6_mode & INTEL_RC6p_ENABLE)
3819 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3820
5a7dc92a
ED		 3821 if (rc6_mode & INTEL_RC6pp_ENABLE)
3822 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3823 }
2b4e57bd 3824
dc39fff7 3825 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 3826
3827 I915_WRITE(GEN6_RC_CONTROL,
3828 rc6_mask |
3829 GEN6_RC_CTL_EI_MODE(1) |
3830 GEN6_RC_CTL_HW_ENABLE);
3831
dd75fdc8
CW		 3832 /* Power down if completely idle for over 50ms */
3833 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 3834 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 3835
42c0526c 3836 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3837 if (!ret) {
42c0526c
BW		 3838 pcu_mbox = 0;
3839 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3840 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3841 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3842 (dev_priv->rps.max_delay & 0xff) * 50,
3843 (pcu_mbox & 0xff) * 50);
31c77388 3844 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3845 }
3846 } else {
3847 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3848 }
3849
dd75fdc8
CW		 3850 dev_priv->rps.power = HIGH_POWER; /* force a reset */
3851 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_delay);
2b4e57bd 3852
44fc7d5c 3853 gen6_enable_rps_interrupts(dev);
2b4e57bd 3854
31643d54
BW		 3855 rc6vids = 0;
3856 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3857 if (IS_GEN6(dev) && ret) {
3858 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3859 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3860 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3861 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3862 rc6vids &= 0xffff00;
3863 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3864 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3865 if (ret)
3866 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3867 }
3868
2b4e57bd 3869 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3870}
3871
c67a470b 3872void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3873{
79f5b2c7 3874 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3875 int min_freq = 15;
3ebecd07
CW		 3876 unsigned int gpu_freq;
3877 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 3878 int scaling_factor = 180;
eda79642 3879 struct cpufreq_policy *policy;
2b4e57bd 3880
4fc688ce 3881 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3882
eda79642
BW		 3883 policy = cpufreq_cpu_get(0);
3884 if (policy) {
3885 max_ia_freq = policy->cpuinfo.max_freq;
3886 cpufreq_cpu_put(policy);
3887 } else {
3888 /*
3889 * Default to measured freq if none found, PCU will ensure we
3890 * don't go over
3891 */
2b4e57bd 3892 max_ia_freq = tsc_khz;
eda79642 3893 }
2b4e57bd
ED		 3894
3895 /* Convert from kHz to MHz */
3896 max_ia_freq /= 1000;
3897
153b4b95 3898 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 3899 /* convert DDR frequency from units of 266.6MHz to bandwidth */
3900 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 3901
2b4e57bd
ED		 3902 /*
3903 * For each potential GPU frequency, load a ring frequency we'd like
3904 * to use for memory access. We do this by specifying the IA frequency
3905 * the PCU should use as a reference to determine the ring frequency.
3906 */
c6a828d3 3907 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3908 gpu_freq--) {
c6a828d3 3909 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3910 unsigned int ia_freq = 0, ring_freq = 0;
3911
3912 if (IS_HASWELL(dev)) {
f6aca45c 3913 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 3914 ring_freq = max(min_ring_freq, ring_freq);
3915 /* leave ia_freq as the default, chosen by cpufreq */
3916 } else {
3917 /* On older processors, there is no separate ring
3918 * clock domain, so in order to boost the bandwidth
3919 * of the ring, we need to upclock the CPU (ia_freq).
3920 *
3921 * For GPU frequencies less than 750MHz,
3922 * just use the lowest ring freq.
3923 */
3924 if (gpu_freq < min_freq)
3925 ia_freq = 800;
3926 else
3927 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3928 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3929 }
2b4e57bd 3930
42c0526c
BW		 3931 sandybridge_pcode_write(dev_priv,
3932 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3933 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3934 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3935 gpu_freq);
2b4e57bd 3936 }
2b4e57bd
ED		 3937}
3938
0a073b84
JB		 3939int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3940{
3941 u32 val, rp0;
3942
64936258 3943 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3944
3945 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3946 /* Clamp to max */
3947 rp0 = min_t(u32, rp0, 0xea);
3948
3949 return rp0;
3950}
3951
3952static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3953{
3954 u32 val, rpe;
3955
64936258 3956 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3957 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3958 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3959 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3960
3961 return rpe;
3962}
3963
3964int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3965{
64936258 3966 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3967}
3968
c9cddffc
JB		 3969static void valleyview_setup_pctx(struct drm_device *dev)
3970{
3971 struct drm_i915_private *dev_priv = dev->dev_private;
3972 struct drm_i915_gem_object *pctx;
3973 unsigned long pctx_paddr;
3974 u32 pcbr;
3975 int pctx_size = 24*1024;
3976
3977 pcbr = I915_READ(VLV_PCBR);
3978 if (pcbr) {
3979 /* BIOS set it up already, grab the pre-alloc'd space */
3980 int pcbr_offset;
3981
3982 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3983 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3984 pcbr_offset,
190d6cd5 3985 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3986 pctx_size);
3987 goto out;
3988 }
3989
3990 /*
3991 * From the Gunit register HAS:
3992 * The Gfx driver is expected to program this register and ensure
3993 * proper allocation within Gfx stolen memory. For example, this
3994 * register should be programmed such than the PCBR range does not
3995 * overlap with other ranges, such as the frame buffer, protected
3996 * memory, or any other relevant ranges.
3997 */
3998 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3999 if (!pctx) {
4000 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4001 return;
4002 }
4003
4004 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4005 I915_WRITE(VLV_PCBR, pctx_paddr);
4006
4007out:
4008 dev_priv->vlv_pctx = pctx;
4009}
4010
0a073b84
JB		 4011static void valleyview_enable_rps(struct drm_device *dev)
4012{
4013 struct drm_i915_private *dev_priv = dev->dev_private;
4014 struct intel_ring_buffer *ring;
a2b23fe0 4015 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 4016 int i;
4017
4018 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4019
4020 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 4021 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
4022 gtfifodbg);
0a073b84
JB		 4023 I915_WRITE(GTFIFODBG, gtfifodbg);
4024 }
4025
c9cddffc
JB		 4026 valleyview_setup_pctx(dev);
4027
0a073b84
JB		 4028 gen6_gt_force_wake_get(dev_priv);
4029
4030 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
4031 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
4032 I915_WRITE(GEN6_RP_UP_EI, 66000);
4033 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
4034
4035 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
4036
4037 I915_WRITE(GEN6_RP_CONTROL,
4038 GEN6_RP_MEDIA_TURBO |
4039 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4040 GEN6_RP_MEDIA_IS_GFX |
4041 GEN6_RP_ENABLE |
4042 GEN6_RP_UP_BUSY_AVG |
4043 GEN6_RP_DOWN_IDLE_CONT);
4044
4045 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
4046 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4047 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4048
4049 for_each_ring(ring, dev_priv, i)
4050 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4051
4052 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
4053
4054 /* allows RC6 residency counter to work */
49798eb2
JB		 4055 I915_WRITE(VLV_COUNTER_CONTROL,
4056 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
4057 VLV_MEDIA_RC6_COUNT_EN |
4058 VLV_RENDER_RC6_COUNT_EN));
a2b23fe0
JB		 4059 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4060 rc6_mode = GEN7_RC_CTL_TO_MODE;
dc39fff7
BW		 4061
4062 intel_print_rc6_info(dev, rc6_mode);
4063
a2b23fe0 4064 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 4065
64936258 4066 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84
JB		 4067
4068 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
4069 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
4070
0a073b84 4071 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 4072 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
4073 vlv_gpu_freq(dev_priv->mem_freq,
4074 dev_priv->rps.cur_delay),
4075 dev_priv->rps.cur_delay);
0a073b84
JB		 4076
4077 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
4078 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 4079 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
4080 vlv_gpu_freq(dev_priv->mem_freq,
4081 dev_priv->rps.max_delay),
4082 dev_priv->rps.max_delay);
0a073b84 4083
73008b98
VS		 4084 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
4085 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
4086 vlv_gpu_freq(dev_priv->mem_freq,
4087 dev_priv->rps.rpe_delay),
4088 dev_priv->rps.rpe_delay);
0a073b84 4089
73008b98
VS		 4090 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
4091 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
4092 vlv_gpu_freq(dev_priv->mem_freq,
4093 dev_priv->rps.min_delay),
4094 dev_priv->rps.min_delay);
0a073b84 4095
73008b98
VS		 4096 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
4097 vlv_gpu_freq(dev_priv->mem_freq,
4098 dev_priv->rps.rpe_delay),
4099 dev_priv->rps.rpe_delay);
0a073b84 4100
73008b98 4101 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 4102
44fc7d5c 4103 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 4104
4105 gen6_gt_force_wake_put(dev_priv);
4106}
4107
930ebb46 4108void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 4109{
4110 struct drm_i915_private *dev_priv = dev->dev_private;
4111
3e373948
DV		 4112 if (dev_priv->ips.renderctx) {
4113 i915_gem_object_unpin(dev_priv->ips.renderctx);
4114 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
4115 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 4116 }
4117
3e373948
DV		 4118 if (dev_priv->ips.pwrctx) {
4119 i915_gem_object_unpin(dev_priv->ips.pwrctx);
4120 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
4121 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 4122 }
4123}
4124
930ebb46 4125static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4126{
4127 struct drm_i915_private *dev_priv = dev->dev_private;
4128
4129 if (I915_READ(PWRCTXA)) {
4130 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
4131 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
4132 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
4133 50);
4134
4135 I915_WRITE(PWRCTXA, 0);
4136 POSTING_READ(PWRCTXA);
4137
4138 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
4139 POSTING_READ(RSTDBYCTL);
4140 }
2b4e57bd
ED		 4141}
4142
4143static int ironlake_setup_rc6(struct drm_device *dev)
4144{
4145 struct drm_i915_private *dev_priv = dev->dev_private;
4146
3e373948
DV		 4147 if (dev_priv->ips.renderctx == NULL)
4148 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
4149 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 4150 return -ENOMEM;
4151
3e373948
DV		 4152 if (dev_priv->ips.pwrctx == NULL)
4153 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
4154 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 4155 ironlake_teardown_rc6(dev);
4156 return -ENOMEM;
4157 }
4158
4159 return 0;
4160}
4161
930ebb46 4162static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 4163{
4164 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 4165 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 4166 bool was_interruptible;
2b4e57bd
ED		 4167 int ret;
4168
4169 /* rc6 disabled by default due to repeated reports of hanging during
4170 * boot and resume.
4171 */
4172 if (!intel_enable_rc6(dev))
4173 return;
4174
79f5b2c7
DV		 4175 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4176
2b4e57bd 4177 ret = ironlake_setup_rc6(dev);
79f5b2c7 4178 if (ret)
2b4e57bd 4179 return;
2b4e57bd 4180
3e960501
CW		 4181 was_interruptible = dev_priv->mm.interruptible;
4182 dev_priv->mm.interruptible = false;
4183
2b4e57bd
ED		 4184 /*
4185 * GPU can automatically power down the render unit if given a page
4186 * to save state.
4187 */
6d90c952 4188 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 4189 if (ret) {
4190 ironlake_teardown_rc6(dev);
3e960501 4191 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 4192 return;
4193 }
4194
6d90c952
DV		 4195 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
4196 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 4197 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 4198 MI_MM_SPACE_GTT |
4199 MI_SAVE_EXT_STATE_EN |
4200 MI_RESTORE_EXT_STATE_EN |
4201 MI_RESTORE_INHIBIT);
4202 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
4203 intel_ring_emit(ring, MI_NOOP);
4204 intel_ring_emit(ring, MI_FLUSH);
4205 intel_ring_advance(ring);
2b4e57bd
ED		 4206
4207 /*
4208 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
4209 * does an implicit flush, combined with MI_FLUSH above, it should be
4210 * safe to assume that renderctx is valid
4211 */
3e960501
CW		 4212 ret = intel_ring_idle(ring);
4213 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 4214 if (ret) {
def27a58 4215 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4216 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4217 return;
4218 }
4219
f343c5f6 4220 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4221 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
dc39fff7
BW		 4222
4223 intel_print_rc6_info(dev, INTEL_RC6_ENABLE);
2b4e57bd
ED		 4224}
4225
dde18883
ED		 4226static unsigned long intel_pxfreq(u32 vidfreq)
4227{
4228 unsigned long freq;
4229 int div = (vidfreq & 0x3f0000) >> 16;
4230 int post = (vidfreq & 0x3000) >> 12;
4231 int pre = (vidfreq & 0x7);
4232
4233 if (!pre)
4234 return 0;
4235
4236 freq = ((div * 133333) / ((1<<post) * pre));
4237
4238 return freq;
4239}
4240
eb48eb00
DV		 4241static const struct cparams {
4242 u16 i;
4243 u16 t;
4244 u16 m;
4245 u16 c;
4246} cparams[] = {
4247 { 1, 1333, 301, 28664 },
4248 { 1, 1066, 294, 24460 },
4249 { 1, 800, 294, 25192 },
4250 { 0, 1333, 276, 27605 },
4251 { 0, 1066, 276, 27605 },
4252 { 0, 800, 231, 23784 },
4253};
4254
f531dcb2 4255static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4256{
4257 u64 total_count, diff, ret;
4258 u32 count1, count2, count3, m = 0, c = 0;
4259 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4260 int i;
4261
02d71956
DV		 4262 assert_spin_locked(&mchdev_lock);
4263
20e4d407 4264 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4265
4266 /* Prevent division-by-zero if we are asking too fast.
4267 * Also, we don't get interesting results if we are polling
4268 * faster than once in 10ms, so just return the saved value
4269 * in such cases.
4270 */
4271 if (diff1 <= 10)
20e4d407 4272 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4273
4274 count1 = I915_READ(DMIEC);
4275 count2 = I915_READ(DDREC);
4276 count3 = I915_READ(CSIEC);
4277
4278 total_count = count1 + count2 + count3;
4279
4280 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4281 if (total_count < dev_priv->ips.last_count1) {
4282 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4283 diff += total_count;
4284 } else {
20e4d407 4285 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4286 }
4287
4288 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4289 if (cparams[i].i == dev_priv->ips.c_m &&
4290 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4291 m = cparams[i].m;
4292 c = cparams[i].c;
4293 break;
4294 }
4295 }
4296
4297 diff = div_u64(diff, diff1);
4298 ret = ((m * diff) + c);
4299 ret = div_u64(ret, 10);
4300
20e4d407
DV		 4301 dev_priv->ips.last_count1 = total_count;
4302 dev_priv->ips.last_time1 = now;
eb48eb00 4303
20e4d407 4304 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4305
4306 return ret;
4307}
4308
f531dcb2
CW		 4309unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4310{
4311 unsigned long val;
4312
4313 if (dev_priv->info->gen != 5)
4314 return 0;
4315
4316 spin_lock_irq(&mchdev_lock);
4317
4318 val = __i915_chipset_val(dev_priv);
4319
4320 spin_unlock_irq(&mchdev_lock);
4321
4322 return val;
4323}
4324
eb48eb00
DV		 4325unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4326{
4327 unsigned long m, x, b;
4328 u32 tsfs;
4329
4330 tsfs = I915_READ(TSFS);
4331
4332 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4333 x = I915_READ8(TR1);
4334
4335 b = tsfs & TSFS_INTR_MASK;
4336
4337 return ((m * x) / 127) - b;
4338}
4339
4340static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4341{
4342 static const struct v_table {
4343 u16 vd; /* in .1 mil */
4344 u16 vm; /* in .1 mil */
4345 } v_table[] = {
4346 { 0, 0, },
4347 { 375, 0, },
4348 { 500, 0, },
4349 { 625, 0, },
4350 { 750, 0, },
4351 { 875, 0, },
4352 { 1000, 0, },
4353 { 1125, 0, },
4354 { 4125, 3000, },
4355 { 4125, 3000, },
4356 { 4125, 3000, },
4357 { 4125, 3000, },
4358 { 4125, 3000, },
4359 { 4125, 3000, },
4360 { 4125, 3000, },
4361 { 4125, 3000, },
4362 { 4125, 3000, },
4363 { 4125, 3000, },
4364 { 4125, 3000, },
4365 { 4125, 3000, },
4366 { 4125, 3000, },
4367 { 4125, 3000, },
4368 { 4125, 3000, },
4369 { 4125, 3000, },
4370 { 4125, 3000, },
4371 { 4125, 3000, },
4372 { 4125, 3000, },
4373 { 4125, 3000, },
4374 { 4125, 3000, },
4375 { 4125, 3000, },
4376 { 4125, 3000, },
4377 { 4125, 3000, },
4378 { 4250, 3125, },
4379 { 4375, 3250, },
4380 { 4500, 3375, },
4381 { 4625, 3500, },
4382 { 4750, 3625, },
4383 { 4875, 3750, },
4384 { 5000, 3875, },
4385 { 5125, 4000, },
4386 { 5250, 4125, },
4387 { 5375, 4250, },
4388 { 5500, 4375, },
4389 { 5625, 4500, },
4390 { 5750, 4625, },
4391 { 5875, 4750, },
4392 { 6000, 4875, },
4393 { 6125, 5000, },
4394 { 6250, 5125, },
4395 { 6375, 5250, },
4396 { 6500, 5375, },
4397 { 6625, 5500, },
4398 { 6750, 5625, },
4399 { 6875, 5750, },
4400 { 7000, 5875, },
4401 { 7125, 6000, },
4402 { 7250, 6125, },
4403 { 7375, 6250, },
4404 { 7500, 6375, },
4405 { 7625, 6500, },
4406 { 7750, 6625, },
4407 { 7875, 6750, },
4408 { 8000, 6875, },
4409 { 8125, 7000, },
4410 { 8250, 7125, },
4411 { 8375, 7250, },
4412 { 8500, 7375, },
4413 { 8625, 7500, },
4414 { 8750, 7625, },
4415 { 8875, 7750, },
4416 { 9000, 7875, },
4417 { 9125, 8000, },
4418 { 9250, 8125, },
4419 { 9375, 8250, },
4420 { 9500, 8375, },
4421 { 9625, 8500, },
4422 { 9750, 8625, },
4423 { 9875, 8750, },
4424 { 10000, 8875, },
4425 { 10125, 9000, },
4426 { 10250, 9125, },
4427 { 10375, 9250, },
4428 { 10500, 9375, },
4429 { 10625, 9500, },
4430 { 10750, 9625, },
4431 { 10875, 9750, },
4432 { 11000, 9875, },
4433 { 11125, 10000, },
4434 { 11250, 10125, },
4435 { 11375, 10250, },
4436 { 11500, 10375, },
4437 { 11625, 10500, },
4438 { 11750, 10625, },
4439 { 11875, 10750, },
4440 { 12000, 10875, },
4441 { 12125, 11000, },
4442 { 12250, 11125, },
4443 { 12375, 11250, },
4444 { 12500, 11375, },
4445 { 12625, 11500, },
4446 { 12750, 11625, },
4447 { 12875, 11750, },
4448 { 13000, 11875, },
4449 { 13125, 12000, },
4450 { 13250, 12125, },
4451 { 13375, 12250, },
4452 { 13500, 12375, },
4453 { 13625, 12500, },
4454 { 13750, 12625, },
4455 { 13875, 12750, },
4456 { 14000, 12875, },
4457 { 14125, 13000, },
4458 { 14250, 13125, },
4459 { 14375, 13250, },
4460 { 14500, 13375, },
4461 { 14625, 13500, },
4462 { 14750, 13625, },
4463 { 14875, 13750, },
4464 { 15000, 13875, },
4465 { 15125, 14000, },
4466 { 15250, 14125, },
4467 { 15375, 14250, },
4468 { 15500, 14375, },
4469 { 15625, 14500, },
4470 { 15750, 14625, },
4471 { 15875, 14750, },
4472 { 16000, 14875, },
4473 { 16125, 15000, },
4474 };
4475 if (dev_priv->info->is_mobile)
4476 return v_table[pxvid].vm;
4477 else
4478 return v_table[pxvid].vd;
4479}
4480
02d71956 4481static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4482{
4483 struct timespec now, diff1;
4484 u64 diff;
4485 unsigned long diffms;
4486 u32 count;
4487
02d71956 4488 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4489
4490 getrawmonotonic(&now);
20e4d407 4491 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4492
4493 /* Don't divide by 0 */
4494 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4495 if (!diffms)
4496 return;
4497
4498 count = I915_READ(GFXEC);
4499
20e4d407
DV		 4500 if (count < dev_priv->ips.last_count2) {
4501 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4502 diff += count;
4503 } else {
20e4d407 4504 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4505 }
4506
20e4d407
DV		 4507 dev_priv->ips.last_count2 = count;
4508 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4509
4510 /* More magic constants... */
4511 diff = diff * 1181;
4512 diff = div_u64(diff, diffms * 10);
20e4d407 4513 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4514}
4515
02d71956
DV		 4516void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4517{
4518 if (dev_priv->info->gen != 5)
4519 return;
4520
9270388e 4521 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4522
4523 __i915_update_gfx_val(dev_priv);
4524
9270388e 4525 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4526}
4527
f531dcb2 4528static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4529{
4530 unsigned long t, corr, state1, corr2, state2;
4531 u32 pxvid, ext_v;
4532
02d71956
DV		 4533 assert_spin_locked(&mchdev_lock);
4534
c6a828d3 4535 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4536 pxvid = (pxvid >> 24) & 0x7f;
4537 ext_v = pvid_to_extvid(dev_priv, pxvid);
4538
4539 state1 = ext_v;
4540
4541 t = i915_mch_val(dev_priv);
4542
4543 /* Revel in the empirically derived constants */
4544
4545 /* Correction factor in 1/100000 units */
4546 if (t > 80)
4547 corr = ((t * 2349) + 135940);
4548 else if (t >= 50)
4549 corr = ((t * 964) + 29317);
4550 else /* < 50 */
4551 corr = ((t * 301) + 1004);
4552
4553 corr = corr * ((150142 * state1) / 10000 - 78642);
4554 corr /= 100000;
20e4d407 4555 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4556
4557 state2 = (corr2 * state1) / 10000;
4558 state2 /= 100; /* convert to mW */
4559
02d71956 4560 __i915_update_gfx_val(dev_priv);
eb48eb00 4561
20e4d407 4562 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4563}
4564
f531dcb2
CW		 4565unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4566{
4567 unsigned long val;
4568
4569 if (dev_priv->info->gen != 5)
4570 return 0;
4571
4572 spin_lock_irq(&mchdev_lock);
4573
4574 val = __i915_gfx_val(dev_priv);
4575
4576 spin_unlock_irq(&mchdev_lock);
4577
4578 return val;
4579}
4580
eb48eb00
DV		 4581/**
4582 * i915_read_mch_val - return value for IPS use
4583 *
4584 * Calculate and return a value for the IPS driver to use when deciding whether
4585 * we have thermal and power headroom to increase CPU or GPU power budget.
4586 */
4587unsigned long i915_read_mch_val(void)
4588{
4589 struct drm_i915_private *dev_priv;
4590 unsigned long chipset_val, graphics_val, ret = 0;
4591
9270388e 4592 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4593 if (!i915_mch_dev)
4594 goto out_unlock;
4595 dev_priv = i915_mch_dev;
4596
f531dcb2
CW		 4597 chipset_val = __i915_chipset_val(dev_priv);
4598 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4599
4600 ret = chipset_val + graphics_val;
4601
4602out_unlock:
9270388e 4603 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4604
4605 return ret;
4606}
4607EXPORT_SYMBOL_GPL(i915_read_mch_val);
4608
4609/**
4610 * i915_gpu_raise - raise GPU frequency limit
4611 *
4612 * Raise the limit; IPS indicates we have thermal headroom.
4613 */
4614bool i915_gpu_raise(void)
4615{
4616 struct drm_i915_private *dev_priv;
4617 bool ret = true;
4618
9270388e 4619 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4620 if (!i915_mch_dev) {
4621 ret = false;
4622 goto out_unlock;
4623 }
4624 dev_priv = i915_mch_dev;
4625
20e4d407
DV		 4626 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4627 dev_priv->ips.max_delay--;
eb48eb00
DV		 4628
4629out_unlock:
9270388e 4630 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4631
4632 return ret;
4633}
4634EXPORT_SYMBOL_GPL(i915_gpu_raise);
4635
4636/**
4637 * i915_gpu_lower - lower GPU frequency limit
4638 *
4639 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4640 * frequency maximum.
4641 */
4642bool i915_gpu_lower(void)
4643{
4644 struct drm_i915_private *dev_priv;
4645 bool ret = true;
4646
9270388e 4647 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4648 if (!i915_mch_dev) {
4649 ret = false;
4650 goto out_unlock;
4651 }
4652 dev_priv = i915_mch_dev;
4653
20e4d407
DV		 4654 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4655 dev_priv->ips.max_delay++;
eb48eb00
DV		 4656
4657out_unlock:
9270388e 4658 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4659
4660 return ret;
4661}
4662EXPORT_SYMBOL_GPL(i915_gpu_lower);
4663
4664/**
4665 * i915_gpu_busy - indicate GPU business to IPS
4666 *
4667 * Tell the IPS driver whether or not the GPU is busy.
4668 */
4669bool i915_gpu_busy(void)
4670{
4671 struct drm_i915_private *dev_priv;
f047e395 4672 struct intel_ring_buffer *ring;
eb48eb00 4673 bool ret = false;
f047e395 4674 int i;
eb48eb00 4675
9270388e 4676 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4677 if (!i915_mch_dev)
4678 goto out_unlock;
4679 dev_priv = i915_mch_dev;
4680
f047e395
CW		 4681 for_each_ring(ring, dev_priv, i)
4682 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4683
4684out_unlock:
9270388e 4685 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4686
4687 return ret;
4688}
4689EXPORT_SYMBOL_GPL(i915_gpu_busy);
4690
4691/**
4692 * i915_gpu_turbo_disable - disable graphics turbo
4693 *
4694 * Disable graphics turbo by resetting the max frequency and setting the
4695 * current frequency to the default.
4696 */
4697bool i915_gpu_turbo_disable(void)
4698{
4699 struct drm_i915_private *dev_priv;
4700 bool ret = true;
4701
9270388e 4702 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4703 if (!i915_mch_dev) {
4704 ret = false;
4705 goto out_unlock;
4706 }
4707 dev_priv = i915_mch_dev;
4708
20e4d407 4709 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4710
20e4d407 4711 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4712 ret = false;
4713
4714out_unlock:
9270388e 4715 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4716
4717 return ret;
4718}
4719EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4720
4721/**
4722 * Tells the intel_ips driver that the i915 driver is now loaded, if
4723 * IPS got loaded first.
4724 *
4725 * This awkward dance is so that neither module has to depend on the
4726 * other in order for IPS to do the appropriate communication of
4727 * GPU turbo limits to i915.
4728 */
4729static void
4730ips_ping_for_i915_load(void)
4731{
4732 void (*link)(void);
4733
4734 link = symbol_get(ips_link_to_i915_driver);
4735 if (link) {
4736 link();
4737 symbol_put(ips_link_to_i915_driver);
4738 }
4739}
4740
4741void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4742{
02d71956
DV		 4743 /* We only register the i915 ips part with intel-ips once everything is
4744 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4745 spin_lock_irq(&mchdev_lock);
eb48eb00 4746 i915_mch_dev = dev_priv;
9270388e 4747 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4748
4749 ips_ping_for_i915_load();
4750}
4751
4752void intel_gpu_ips_teardown(void)
4753{
9270388e 4754 spin_lock_irq(&mchdev_lock);
eb48eb00 4755 i915_mch_dev = NULL;
9270388e 4756 spin_unlock_irq(&mchdev_lock);
eb48eb00 4757}
8090c6b9 4758static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4759{
4760 struct drm_i915_private *dev_priv = dev->dev_private;
4761 u32 lcfuse;
4762 u8 pxw[16];
4763 int i;
4764
4765 /* Disable to program */
4766 I915_WRITE(ECR, 0);
4767 POSTING_READ(ECR);
4768
4769 /* Program energy weights for various events */
4770 I915_WRITE(SDEW, 0x15040d00);
4771 I915_WRITE(CSIEW0, 0x007f0000);
4772 I915_WRITE(CSIEW1, 0x1e220004);
4773 I915_WRITE(CSIEW2, 0x04000004);
4774
4775 for (i = 0; i < 5; i++)
4776 I915_WRITE(PEW + (i * 4), 0);
4777 for (i = 0; i < 3; i++)
4778 I915_WRITE(DEW + (i * 4), 0);
4779
4780 /* Program P-state weights to account for frequency power adjustment */
4781 for (i = 0; i < 16; i++) {
4782 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4783 unsigned long freq = intel_pxfreq(pxvidfreq);
4784 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4785 PXVFREQ_PX_SHIFT;
4786 unsigned long val;
4787
4788 val = vid * vid;
4789 val *= (freq / 1000);
4790 val *= 255;
4791 val /= (127*127*900);
4792 if (val > 0xff)
4793 DRM_ERROR("bad pxval: %ld\n", val);
4794 pxw[i] = val;
4795 }
4796 /* Render standby states get 0 weight */
4797 pxw[14] = 0;
4798 pxw[15] = 0;
4799
4800 for (i = 0; i < 4; i++) {
4801 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4802 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4803 I915_WRITE(PXW + (i * 4), val);
4804 }
4805
4806 /* Adjust magic regs to magic values (more experimental results) */
4807 I915_WRITE(OGW0, 0);
4808 I915_WRITE(OGW1, 0);
4809 I915_WRITE(EG0, 0x00007f00);
4810 I915_WRITE(EG1, 0x0000000e);
4811 I915_WRITE(EG2, 0x000e0000);
4812 I915_WRITE(EG3, 0x68000300);
4813 I915_WRITE(EG4, 0x42000000);
4814 I915_WRITE(EG5, 0x00140031);
4815 I915_WRITE(EG6, 0);
4816 I915_WRITE(EG7, 0);
4817
4818 for (i = 0; i < 8; i++)
4819 I915_WRITE(PXWL + (i * 4), 0);
4820
4821 /* Enable PMON + select events */
4822 I915_WRITE(ECR, 0x80000019);
4823
4824 lcfuse = I915_READ(LCFUSE02);
4825
20e4d407 4826 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4827}
4828
8090c6b9
DV		 4829void intel_disable_gt_powersave(struct drm_device *dev)
4830{
1a01ab3b
JB		 4831 struct drm_i915_private *dev_priv = dev->dev_private;
4832
fd0c0642
DV		 4833 /* Interrupts should be disabled already to avoid re-arming. */
4834 WARN_ON(dev->irq_enabled);
4835
930ebb46 4836 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4837 ironlake_disable_drps(dev);
930ebb46 4838 ironlake_disable_rc6(dev);
0a073b84 4839 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4840 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4841 cancel_work_sync(&dev_priv->rps.work);
4fc688ce 4842 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4843 if (IS_VALLEYVIEW(dev))
4844 valleyview_disable_rps(dev);
4845 else
4846 gen6_disable_rps(dev);
c0951f0c 4847 dev_priv->rps.enabled = false;
4fc688ce 4848 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4849 }
8090c6b9
DV		 4850}
4851
1a01ab3b
JB		 4852static void intel_gen6_powersave_work(struct work_struct *work)
4853{
4854 struct drm_i915_private *dev_priv =
4855 container_of(work, struct drm_i915_private,
4856 rps.delayed_resume_work.work);
4857 struct drm_device *dev = dev_priv->dev;
4858
4fc688ce 4859 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4860
4861 if (IS_VALLEYVIEW(dev)) {
4862 valleyview_enable_rps(dev);
4863 } else {
4864 gen6_enable_rps(dev);
4865 gen6_update_ring_freq(dev);
4866 }
c0951f0c 4867 dev_priv->rps.enabled = true;
4fc688ce 4868 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4869}
4870
8090c6b9
DV		 4871void intel_enable_gt_powersave(struct drm_device *dev)
4872{
1a01ab3b
JB		 4873 struct drm_i915_private *dev_priv = dev->dev_private;
4874
8090c6b9
DV		 4875 if (IS_IRONLAKE_M(dev)) {
4876 ironlake_enable_drps(dev);
4877 ironlake_enable_rc6(dev);
4878 intel_init_emon(dev);
0a073b84 4879 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4880 /*
4881 * PCU communication is slow and this doesn't need to be
4882 * done at any specific time, so do this out of our fast path
4883 * to make resume and init faster.
4884 */
4885 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4886 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4887 }
4888}
4889
3107bd48
DV		 4890static void ibx_init_clock_gating(struct drm_device *dev)
4891{
4892 struct drm_i915_private *dev_priv = dev->dev_private;
4893
4894 /*
4895 * On Ibex Peak and Cougar Point, we need to disable clock
4896 * gating for the panel power sequencer or it will fail to
4897 * start up when no ports are active.
4898 */
4899 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4900}
4901
0e088b8f
VS		 4902static void g4x_disable_trickle_feed(struct drm_device *dev)
4903{
4904 struct drm_i915_private *dev_priv = dev->dev_private;
4905 int pipe;
4906
4907 for_each_pipe(pipe) {
4908 I915_WRITE(DSPCNTR(pipe),
4909 I915_READ(DSPCNTR(pipe)) |
4910 DISPPLANE_TRICKLE_FEED_DISABLE);
1dba99f4 4911 intel_flush_primary_plane(dev_priv, pipe);
0e088b8f
VS		 4912 }
4913}
4914
1fa61106 4915static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4916{
4917 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4918 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4919
f1e8fa56
DL		 4920 /*
4921 * Required for FBC
4922 * WaFbcDisableDpfcClockGating:ilk
4923 */
4d47e4f5
DL		 4924 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4925 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4926 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4927
4928 I915_WRITE(PCH_3DCGDIS0,
4929 MARIUNIT_CLOCK_GATE_DISABLE |
4930 SVSMUNIT_CLOCK_GATE_DISABLE);
4931 I915_WRITE(PCH_3DCGDIS1,
4932 VFMUNIT_CLOCK_GATE_DISABLE);
4933
6f1d69b0
ED		 4934 /*
4935 * According to the spec the following bits should be set in
4936 * order to enable memory self-refresh
4937 * The bit 22/21 of 0x42004
4938 * The bit 5 of 0x42020
4939 * The bit 15 of 0x45000
4940 */
4941 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4942 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4943 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4944 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4945 I915_WRITE(DISP_ARB_CTL,
4946 (I915_READ(DISP_ARB_CTL) |
4947 DISP_FBC_WM_DIS));
4948 I915_WRITE(WM3_LP_ILK, 0);
4949 I915_WRITE(WM2_LP_ILK, 0);
4950 I915_WRITE(WM1_LP_ILK, 0);
4951
4952 /*
4953 * Based on the document from hardware guys the following bits
4954 * should be set unconditionally in order to enable FBC.
4955 * The bit 22 of 0x42000
4956 * The bit 22 of 0x42004
4957 * The bit 7,8,9 of 0x42020.
4958 */
4959 if (IS_IRONLAKE_M(dev)) {
4bb35334 4960 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4961 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4962 I915_READ(ILK_DISPLAY_CHICKEN1) |
4963 ILK_FBCQ_DIS);
4964 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4965 I915_READ(ILK_DISPLAY_CHICKEN2) |
4966 ILK_DPARB_GATE);
6f1d69b0
ED		 4967 }
4968
4d47e4f5
DL		 4969 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4970
6f1d69b0
ED		 4971 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4972 I915_READ(ILK_DISPLAY_CHICKEN2) |
4973 ILK_ELPIN_409_SELECT);
4974 I915_WRITE(_3D_CHICKEN2,
4975 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4976 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4977
ecdb4eb7 4978 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4979 I915_WRITE(CACHE_MODE_0,
4980 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4981
0e088b8f 4982 g4x_disable_trickle_feed(dev);
bdad2b2f 4983
3107bd48
DV		 4984 ibx_init_clock_gating(dev);
4985}
4986
4987static void cpt_init_clock_gating(struct drm_device *dev)
4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990 int pipe;
3f704fa2 4991 uint32_t val;
3107bd48
DV		 4992
4993 /*
4994 * On Ibex Peak and Cougar Point, we need to disable clock
4995 * gating for the panel power sequencer or it will fail to
4996 * start up when no ports are active.
4997 */
cd664078
JB		 4998 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
4999 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5000 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 5001 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
5002 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 5003 /* The below fixes the weird display corruption, a few pixels shifted
5004 * downward, on (only) LVDS of some HP laptops with IVY.
5005 */
3f704fa2 5006 for_each_pipe(pipe) {
dc4bd2d1
PZ		 5007 val = I915_READ(TRANS_CHICKEN2(pipe));
5008 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
5009 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 5010 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 5011 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 5012 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
5013 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
5014 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 5015 I915_WRITE(TRANS_CHICKEN2(pipe), val);
5016 }
3107bd48
DV		 5017 /* WADP0ClockGatingDisable */
5018 for_each_pipe(pipe) {
5019 I915_WRITE(TRANS_CHICKEN1(pipe),
5020 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
5021 }
6f1d69b0
ED		 5022}
5023
1d7aaa0c
DV		 5024static void gen6_check_mch_setup(struct drm_device *dev)
5025{
5026 struct drm_i915_private *dev_priv = dev->dev_private;
5027 uint32_t tmp;
5028
5029 tmp = I915_READ(MCH_SSKPD);
5030 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
5031 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
5032 DRM_INFO("This can cause pipe underruns and display issues.\n");
5033 DRM_INFO("Please upgrade your BIOS to fix this.\n");
5034 }
5035}
5036
1fa61106 5037static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5038{
5039 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5040 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5041
231e54f6 5042 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 5043
5044 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5045 I915_READ(ILK_DISPLAY_CHICKEN2) |
5046 ILK_ELPIN_409_SELECT);
5047
ecdb4eb7 5048 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 5049 I915_WRITE(_3D_CHICKEN,
5050 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
5051
ecdb4eb7 5052 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 5053 if (IS_SNB_GT1(dev))
5054 I915_WRITE(GEN6_GT_MODE,
5055 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
5056
6f1d69b0
ED		 5057 I915_WRITE(WM3_LP_ILK, 0);
5058 I915_WRITE(WM2_LP_ILK, 0);
5059 I915_WRITE(WM1_LP_ILK, 0);
5060
6f1d69b0 5061 I915_WRITE(CACHE_MODE_0,
50743298 5062 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 5063
5064 I915_WRITE(GEN6_UCGCTL1,
5065 I915_READ(GEN6_UCGCTL1) |
5066 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
5067 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
5068
5069 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5070 * gating disable must be set. Failure to set it results in
5071 * flickering pixels due to Z write ordering failures after
5072 * some amount of runtime in the Mesa "fire" demo, and Unigine
5073 * Sanctuary and Tropics, and apparently anything else with
5074 * alpha test or pixel discard.
5075 *
5076 * According to the spec, bit 11 (RCCUNIT) must also be set,
5077 * but we didn't debug actual testcases to find it out.
0f846f81 5078 *
ecdb4eb7
DL		 5079 * Also apply WaDisableVDSUnitClockGating:snb and
5080 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 5081 */
5082 I915_WRITE(GEN6_UCGCTL2,
0f846f81 5083 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 5084 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5085 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5086
5087 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 5088 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
5089 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 5090
5091 /*
5092 * According to the spec the following bits should be
5093 * set in order to enable memory self-refresh and fbc:
5094 * The bit21 and bit22 of 0x42000
5095 * The bit21 and bit22 of 0x42004
5096 * The bit5 and bit7 of 0x42020
5097 * The bit14 of 0x70180
5098 * The bit14 of 0x71180
4bb35334
DL		 5099 *
5100 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 5101 */
5102 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5103 I915_READ(ILK_DISPLAY_CHICKEN1) |
5104 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
5105 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5106 I915_READ(ILK_DISPLAY_CHICKEN2) |
5107 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 5108 I915_WRITE(ILK_DSPCLK_GATE_D,
5109 I915_READ(ILK_DSPCLK_GATE_D) |
5110 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
5111 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 5112
0e088b8f 5113 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 5114
5115 /* The default value should be 0x200 according to docs, but the two
5116 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
5117 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
5118 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 5119
5120 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5121
5122 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5123}
5124
5125static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
5126{
5127 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
5128
5129 reg &= ~GEN7_FF_SCHED_MASK;
5130 reg |= GEN7_FF_TS_SCHED_HW;
5131 reg |= GEN7_FF_VS_SCHED_HW;
5132 reg |= GEN7_FF_DS_SCHED_HW;
5133
41c0b3a8
BW		 5134 if (IS_HASWELL(dev_priv->dev))
5135 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
5136
6f1d69b0
ED		 5137 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
5138}
5139
17a303ec
PZ		 5140static void lpt_init_clock_gating(struct drm_device *dev)
5141{
5142 struct drm_i915_private *dev_priv = dev->dev_private;
5143
5144 /*
5145 * TODO: this bit should only be enabled when really needed, then
5146 * disabled when not needed anymore in order to save power.
5147 */
5148 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
5149 I915_WRITE(SOUTH_DSPCLK_GATE_D,
5150 I915_READ(SOUTH_DSPCLK_GATE_D) |
5151 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 5152
5153 /* WADPOClockGatingDisable:hsw */
5154 I915_WRITE(_TRANSA_CHICKEN1,
5155 I915_READ(_TRANSA_CHICKEN1) |
5156 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 5157}
5158
7d708ee4
ID		 5159static void lpt_suspend_hw(struct drm_device *dev)
5160{
5161 struct drm_i915_private *dev_priv = dev->dev_private;
5162
5163 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
5164 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
5165
5166 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
5167 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
5168 }
5169}
5170
cad2a2d7
ED		 5171static void haswell_init_clock_gating(struct drm_device *dev)
5172{
5173 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 5174
5175 I915_WRITE(WM3_LP_ILK, 0);
5176 I915_WRITE(WM2_LP_ILK, 0);
5177 I915_WRITE(WM1_LP_ILK, 0);
5178
5179 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5180 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 5181 */
5182 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
5183
ecdb4eb7 5184 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 5185 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5186 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5187
ecdb4eb7 5188 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 5189 I915_WRITE(GEN7_L3CNTLREG1,
5190 GEN7_WA_FOR_GEN7_L3_CONTROL);
5191 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
5192 GEN7_WA_L3_CHICKEN_MODE);
5193
f3fc4884
FJ		 5194 /* L3 caching of data atomics doesn't work -- disable it. */
5195 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
5196 I915_WRITE(HSW_ROW_CHICKEN3,
5197 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
5198
ecdb4eb7 5199 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 5200 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5201 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5202 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5203
ecdb4eb7 5204 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 5205 gen7_setup_fixed_func_scheduler(dev_priv);
5206
ecdb4eb7 5207 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 5208 I915_WRITE(CACHE_MODE_1,
5209 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 5210
ecdb4eb7 5211 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 5212 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
5213
90a88643
PZ		 5214 /* WaRsPkgCStateDisplayPMReq:hsw */
5215 I915_WRITE(CHICKEN_PAR1_1,
5216 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 5217
17a303ec 5218 lpt_init_clock_gating(dev);
cad2a2d7
ED		 5219}
5220
1fa61106 5221static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5222{
5223 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 5224 uint32_t snpcr;
6f1d69b0 5225
6f1d69b0
ED		 5226 I915_WRITE(WM3_LP_ILK, 0);
5227 I915_WRITE(WM2_LP_ILK, 0);
5228 I915_WRITE(WM1_LP_ILK, 0);
5229
231e54f6 5230 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5231
ecdb4eb7 5232 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5233 I915_WRITE(_3D_CHICKEN3,
5234 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5235
ecdb4eb7 5236 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5237 I915_WRITE(IVB_CHICKEN3,
5238 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5239 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5240
ecdb4eb7 5241 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5242 if (IS_IVB_GT1(dev))
5243 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5244 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5245 else
5246 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5247 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5248
ecdb4eb7 5249 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5250 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5251 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5252
ecdb4eb7 5253 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5254 I915_WRITE(GEN7_L3CNTLREG1,
5255 GEN7_WA_FOR_GEN7_L3_CONTROL);
5256 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5257 GEN7_WA_L3_CHICKEN_MODE);
5258 if (IS_IVB_GT1(dev))
5259 I915_WRITE(GEN7_ROW_CHICKEN2,
5260 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5261 else
5262 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5263 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5264
6f1d69b0 5265
ecdb4eb7 5266 /* WaForceL3Serialization:ivb */
61939d97
JB		 5267 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5268 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5269
0f846f81
JB		 5270 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5271 * gating disable must be set. Failure to set it results in
5272 * flickering pixels due to Z write ordering failures after
5273 * some amount of runtime in the Mesa "fire" demo, and Unigine
5274 * Sanctuary and Tropics, and apparently anything else with
5275 * alpha test or pixel discard.
5276 *
5277 * According to the spec, bit 11 (RCCUNIT) must also be set,
5278 * but we didn't debug actual testcases to find it out.
5279 *
5280 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5281 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5282 */
5283 I915_WRITE(GEN6_UCGCTL2,
5284 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5285 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5286
ecdb4eb7 5287 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5288 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5289 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5290 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5291
0e088b8f 5292 g4x_disable_trickle_feed(dev);
6f1d69b0 5293
ecdb4eb7 5294 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5295 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5296
ecdb4eb7 5297 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5298 I915_WRITE(CACHE_MODE_1,
5299 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5300
5301 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5302 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5303 snpcr |= GEN6_MBC_SNPCR_MED;
5304 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5305
ab5c608b
BW		 5306 if (!HAS_PCH_NOP(dev))
5307 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5308
5309 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5310}
5311
1fa61106 5312static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5313{
5314 struct drm_i915_private *dev_priv = dev->dev_private;
85b1d7b3
JB		 5315 u32 val;
5316
5317 mutex_lock(&dev_priv->rps.hw_lock);
5318 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5319 mutex_unlock(&dev_priv->rps.hw_lock);
5320 switch ((val >> 6) & 3) {
5321 case 0:
85b1d7b3
JB		 5322 dev_priv->mem_freq = 800;
5323 break;
f64a28a7 5324 case 1:
85b1d7b3
JB		 5325 dev_priv->mem_freq = 1066;
5326 break;
f64a28a7 5327 case 2:
85b1d7b3
JB		 5328 dev_priv->mem_freq = 1333;
5329 break;
f64a28a7
JB		 5330 case 3:
5331 /*
5332 * Probably a BIOS/Punit bug, or a new platform we don't
5333 * support yet.
5334 */
5335 WARN(1, "invalid DDR freq detected, assuming 800MHz\n");
5336 dev_priv->mem_freq = 800;
5337 break;
85b1d7b3
JB		 5338 }
5339 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
6f1d69b0 5340
d7fe0cc0 5341 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5342
ecdb4eb7 5343 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5344 I915_WRITE(_3D_CHICKEN3,
5345 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5346
ecdb4eb7 5347 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5348 I915_WRITE(IVB_CHICKEN3,
5349 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5350 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5351
ecdb4eb7 5352 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5353 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5354 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5355 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5356
ecdb4eb7 5357 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5358 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5359 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5360
ecdb4eb7 5361 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5362 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5363 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5364
ecdb4eb7 5365 /* WaForceL3Serialization:vlv */
61939d97
JB		 5366 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5367 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5368
ecdb4eb7 5369 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5370 I915_WRITE(GEN7_ROW_CHICKEN2,
5371 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5372
ecdb4eb7 5373 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5374 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5375 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5376 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5377
0f846f81
JB		 5378 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5379 * gating disable must be set. Failure to set it results in
5380 * flickering pixels due to Z write ordering failures after
5381 * some amount of runtime in the Mesa "fire" demo, and Unigine
5382 * Sanctuary and Tropics, and apparently anything else with
5383 * alpha test or pixel discard.
5384 *
5385 * According to the spec, bit 11 (RCCUNIT) must also be set,
5386 * but we didn't debug actual testcases to find it out.
5387 *
5388 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5389 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5390 *
ecdb4eb7
DL		 5391 * Also apply WaDisableVDSUnitClockGating:vlv and
5392 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5393 */
5394 I915_WRITE(GEN6_UCGCTL2,
5395 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5396 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5397 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5398 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5399 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5400
e3f33d46
JB		 5401 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5402
e0d8d59b 5403 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5404
6b26c86d
DV		 5405 I915_WRITE(CACHE_MODE_1,
5406 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5407
2d809570 5408 /*
ecdb4eb7 5409 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5410 * Disable clock gating on th GCFG unit to prevent a delay
5411 * in the reporting of vblank events.
5412 */
4e8c84a5
JB		 5413 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5414
5415 /* Conservative clock gating settings for now */
5416 I915_WRITE(0x9400, 0xffffffff);
5417 I915_WRITE(0x9404, 0xffffffff);
5418 I915_WRITE(0x9408, 0xffffffff);
5419 I915_WRITE(0x940c, 0xffffffff);
5420 I915_WRITE(0x9410, 0xffffffff);
5421 I915_WRITE(0x9414, 0xffffffff);
5422 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5423}
5424
1fa61106 5425static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5426{
5427 struct drm_i915_private *dev_priv = dev->dev_private;
5428 uint32_t dspclk_gate;
5429
5430 I915_WRITE(RENCLK_GATE_D1, 0);
5431 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5432 GS_UNIT_CLOCK_GATE_DISABLE |
5433 CL_UNIT_CLOCK_GATE_DISABLE);
5434 I915_WRITE(RAMCLK_GATE_D, 0);
5435 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5436 OVRUNIT_CLOCK_GATE_DISABLE |
5437 OVCUNIT_CLOCK_GATE_DISABLE;
5438 if (IS_GM45(dev))
5439 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5440 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5441
5442 /* WaDisableRenderCachePipelinedFlush */
5443 I915_WRITE(CACHE_MODE_0,
5444 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5445
0e088b8f 5446 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5447}
5448
1fa61106 5449static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5450{
5451 struct drm_i915_private *dev_priv = dev->dev_private;
5452
5453 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5454 I915_WRITE(RENCLK_GATE_D2, 0);
5455 I915_WRITE(DSPCLK_GATE_D, 0);
5456 I915_WRITE(RAMCLK_GATE_D, 0);
5457 I915_WRITE16(DEUC, 0);
20f94967
VS		 5458 I915_WRITE(MI_ARB_STATE,
5459 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5460}
5461
1fa61106 5462static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5463{
5464 struct drm_i915_private *dev_priv = dev->dev_private;
5465
5466 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5467 I965_RCC_CLOCK_GATE_DISABLE |
5468 I965_RCPB_CLOCK_GATE_DISABLE |
5469 I965_ISC_CLOCK_GATE_DISABLE |
5470 I965_FBC_CLOCK_GATE_DISABLE);
5471 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5472 I915_WRITE(MI_ARB_STATE,
5473 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5474}
5475
1fa61106 5476static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5477{
5478 struct drm_i915_private *dev_priv = dev->dev_private;
5479 u32 dstate = I915_READ(D_STATE);
5480
5481 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5482 DSTATE_DOT_CLOCK_GATING;
5483 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5484
5485 if (IS_PINEVIEW(dev))
5486 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5487
5488 /* IIR "flip pending" means done if this bit is set */
5489 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5490}
5491
1fa61106 5492static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5493{
5494 struct drm_i915_private *dev_priv = dev->dev_private;
5495
5496 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5497}
5498
1fa61106 5499static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5500{
5501 struct drm_i915_private *dev_priv = dev->dev_private;
5502
5503 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5504}
5505
6f1d69b0
ED		 5506void intel_init_clock_gating(struct drm_device *dev)
5507{
5508 struct drm_i915_private *dev_priv = dev->dev_private;
5509
5510 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5511}
5512
7d708ee4
ID		 5513void intel_suspend_hw(struct drm_device *dev)
5514{
5515 if (HAS_PCH_LPT(dev))
5516 lpt_suspend_hw(dev);
5517}
5518
bddc7645
ID		 5519static bool is_always_on_power_domain(struct drm_device *dev,
5520 enum intel_display_power_domain domain)
5521{
5522 unsigned long always_on_domains;
5523
5524 BUG_ON(BIT(domain) & ~POWER_DOMAIN_MASK);
5525
5526 if (IS_HASWELL(dev)) {
5527 always_on_domains = HSW_ALWAYS_ON_POWER_DOMAINS;
5528 } else {
5529 WARN_ON(1);
5530 return true;
5531 }
5532
5533 return BIT(domain) & always_on_domains;
5534}
5535
15d199ea
PZ		 5536/**
5537 * We should only use the power well if we explicitly asked the hardware to
5538 * enable it, so check if it's enabled and also check if we've requested it to
5539 * be enabled.
5540 */
b97186f0
PZ		 5541bool intel_display_power_enabled(struct drm_device *dev,
5542 enum intel_display_power_domain domain)
15d199ea
PZ		 5543{
5544 struct drm_i915_private *dev_priv = dev->dev_private;
5545
b97186f0
PZ		 5546 if (!HAS_POWER_WELL(dev))
5547 return true;
5548
bddc7645 5549 if (is_always_on_power_domain(dev, domain))
b97186f0 5550 return true;
bddc7645
ID		 5551
5552 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5553 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
15d199ea
PZ		 5554}
5555
a38911a3 5556static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5557{
5558 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5559 bool is_enabled, enable_requested;
5560 uint32_t tmp;
d0d3e513 5561
fa42e23c 5562 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5563 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5564 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5565
fa42e23c
PZ		 5566 if (enable) {
5567 if (!enable_requested)
6aedd1f5
PZ		 5568 I915_WRITE(HSW_PWR_WELL_DRIVER,
5569 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5570
fa42e23c
PZ		 5571 if (!is_enabled) {
5572 DRM_DEBUG_KMS("Enabling power well\n");
5573 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5574 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5575 DRM_ERROR("Timeout enabling power well\n");
5576 }
5577 } else {
5578 if (enable_requested) {
9dbd8feb
PZ		 5579 unsigned long irqflags;
5580 enum pipe p;
5581
fa42e23c 5582 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5583 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5584 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5585
5586 /*
5587 * After this, the registers on the pipes that are part
5588 * of the power well will become zero, so we have to
5589 * adjust our counters according to that.
5590 *
5591 * FIXME: Should we do this in general in
5592 * drm_vblank_post_modeset?
5593 */
5594 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5595 for_each_pipe(p)
5596 if (p != PIPE_A)
5380e929 5597 dev->vblank[p].last = 0;
9dbd8feb 5598 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5599 }
5600 }
fa42e23c 5601}
d0d3e513 5602
b4ed4484
ID		 5603static void __intel_power_well_get(struct drm_device *dev,
5604 struct i915_power_well *power_well)
2d66aef5
VS		 5605{
5606 if (!power_well->count++)
b4ed4484 5607 __intel_set_power_well(dev, true);
2d66aef5
VS		 5608}
5609
b4ed4484
ID		 5610static void __intel_power_well_put(struct drm_device *dev,
5611 struct i915_power_well *power_well)
2d66aef5
VS		 5612{
5613 WARN_ON(!power_well->count);
1ad577ac 5614 if (!--power_well->count && i915_disable_power_well)
b4ed4484 5615 __intel_set_power_well(dev, false);
2d66aef5
VS		 5616}
5617
6765625e
VS		 5618void intel_display_power_get(struct drm_device *dev,
5619 enum intel_display_power_domain domain)
5620{
5621 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5622 struct i915_power_domains *power_domains;
6765625e
VS		 5623
5624 if (!HAS_POWER_WELL(dev))
5625 return;
5626
bddc7645 5627 if (is_always_on_power_domain(dev, domain))
6765625e 5628 return;
bddc7645 5629
83c00f55
ID		 5630 power_domains = &dev_priv->power_domains;
5631
5632 mutex_lock(&power_domains->lock);
b4ed4484 5633 __intel_power_well_get(dev, &power_domains->power_wells[0]);
83c00f55 5634 mutex_unlock(&power_domains->lock);
6765625e
VS		 5635}
5636
5637void intel_display_power_put(struct drm_device *dev,
5638 enum intel_display_power_domain domain)
5639{
5640 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55 5641 struct i915_power_domains *power_domains;
6765625e
VS		 5642
5643 if (!HAS_POWER_WELL(dev))
5644 return;
5645
bddc7645 5646 if (is_always_on_power_domain(dev, domain))
6765625e 5647 return;
bddc7645 5648
83c00f55
ID		 5649 power_domains = &dev_priv->power_domains;
5650
5651 mutex_lock(&power_domains->lock);
b4ed4484 5652 __intel_power_well_put(dev, &power_domains->power_wells[0]);
83c00f55 5653 mutex_unlock(&power_domains->lock);
6765625e
VS		 5654}
5655
83c00f55 5656static struct i915_power_domains *hsw_pwr;
a38911a3
WX		 5657
5658/* Display audio driver power well request */
5659void i915_request_power_well(void)
5660{
b4ed4484
ID		 5661 struct drm_i915_private *dev_priv;
5662
a38911a3
WX		 5663 if (WARN_ON(!hsw_pwr))
5664 return;
5665
b4ed4484
ID		 5666 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5667 power_domains);
5668
959cbc1b 5669 mutex_lock(&hsw_pwr->lock);
b4ed4484 5670 __intel_power_well_get(dev_priv->dev, &hsw_pwr->power_wells[0]);
959cbc1b 5671 mutex_unlock(&hsw_pwr->lock);
a38911a3
WX		 5672}
5673EXPORT_SYMBOL_GPL(i915_request_power_well);
5674
5675/* Display audio driver power well release */
5676void i915_release_power_well(void)
5677{
b4ed4484
ID		 5678 struct drm_i915_private *dev_priv;
5679
a38911a3
WX		 5680 if (WARN_ON(!hsw_pwr))
5681 return;
5682
b4ed4484
ID		 5683 dev_priv = container_of(hsw_pwr, struct drm_i915_private,
5684 power_domains);
5685
959cbc1b 5686 mutex_lock(&hsw_pwr->lock);
b4ed4484 5687 __intel_power_well_put(dev_priv->dev, &hsw_pwr->power_wells[0]);
959cbc1b 5688 mutex_unlock(&hsw_pwr->lock);
a38911a3
WX		 5689}
5690EXPORT_SYMBOL_GPL(i915_release_power_well);
5691
ddb642fb 5692int intel_power_domains_init(struct drm_device *dev)
a38911a3
WX		 5693{
5694 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5695 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5696 struct i915_power_well *power_well;
a38911a3 5697
83c00f55
ID		 5698 mutex_init(&power_domains->lock);
5699 hsw_pwr = power_domains;
a38911a3 5700
83c00f55 5701 power_well = &power_domains->power_wells[0];
83c00f55 5702 power_well->count = 0;
a38911a3
WX		 5703
5704 return 0;
5705}
5706
ddb642fb 5707void intel_power_domains_remove(struct drm_device *dev)
a38911a3
WX		 5708{
5709 hsw_pwr = NULL;
5710}
5711
ddb642fb 5712static void intel_power_domains_resume(struct drm_device *dev)
9cdb826c
VS		 5713{
5714 struct drm_i915_private *dev_priv = dev->dev_private;
83c00f55
ID		 5715 struct i915_power_domains *power_domains = &dev_priv->power_domains;
5716 struct i915_power_well *power_well;
9cdb826c
VS		 5717
5718 if (!HAS_POWER_WELL(dev))
5719 return;
5720
83c00f55
ID		 5721 mutex_lock(&power_domains->lock);
5722
5723 power_well = &power_domains->power_wells[0];
9cdb826c 5724 __intel_set_power_well(dev, power_well->count > 0);
83c00f55
ID		 5725
5726 mutex_unlock(&power_domains->lock);
a38911a3
WX		 5727}
5728
fa42e23c
PZ		 5729/*
5730 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5731 * when not needed anymore. We have 4 registers that can request the power well
5732 * to be enabled, and it will only be disabled if none of the registers is
5733 * requesting it to be enabled.
d0d3e513 5734 */
ddb642fb 5735void intel_power_domains_init_hw(struct drm_device *dev)
d0d3e513
ED		 5736{
5737 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5738
86d52df6 5739 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5740 return;
5741
fa42e23c 5742 /* For now, we need the power well to be always enabled. */
baa70707 5743 intel_display_set_init_power(dev, true);
ddb642fb 5744 intel_power_domains_resume(dev);
d0d3e513 5745
fa42e23c
PZ		 5746 /* We're taking over the BIOS, so clear any requests made by it since
5747 * the driver is in charge now. */
6aedd1f5 5748 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5749 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5750}
5751
c67a470b
PZ		 5752/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5753void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5754{
5755 hsw_disable_package_c8(dev_priv);
5756}
5757
5758void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5759{
5760 hsw_enable_package_c8(dev_priv);
5761}
5762
1fa61106
ED		 5763/* Set up chip specific power management-related functions */
5764void intel_init_pm(struct drm_device *dev)
5765{
5766 struct drm_i915_private *dev_priv = dev->dev_private;
5767
5768 if (I915_HAS_FBC(dev)) {
5769 if (HAS_PCH_SPLIT(dev)) {
5770 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5771 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5772 dev_priv->display.enable_fbc =
5773 gen7_enable_fbc;
5774 else
5775 dev_priv->display.enable_fbc =
5776 ironlake_enable_fbc;
1fa61106
ED		 5777 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5778 } else if (IS_GM45(dev)) {
5779 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5780 dev_priv->display.enable_fbc = g4x_enable_fbc;
5781 dev_priv->display.disable_fbc = g4x_disable_fbc;
5782 } else if (IS_CRESTLINE(dev)) {
5783 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5784 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5785 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5786 }
5787 /* 855GM needs testing */
5788 }
5789
c921aba8
DV		 5790 /* For cxsr */
5791 if (IS_PINEVIEW(dev))
5792 i915_pineview_get_mem_freq(dev);
5793 else if (IS_GEN5(dev))
5794 i915_ironlake_get_mem_freq(dev);
5795
1fa61106
ED		 5796 /* For FIFO watermark updates */
5797 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5798 intel_setup_wm_latency(dev);
5799
1fa61106 5800 if (IS_GEN5(dev)) {
53615a5e
VS		 5801 if (dev_priv->wm.pri_latency[1] &&
5802 dev_priv->wm.spr_latency[1] &&
5803 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5804 dev_priv->display.update_wm = ironlake_update_wm;
5805 else {
5806 DRM_DEBUG_KMS("Failed to get proper latency. "
5807 "Disable CxSR\n");
5808 dev_priv->display.update_wm = NULL;
5809 }
5810 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5811 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5812 if (dev_priv->wm.pri_latency[0] &&
5813 dev_priv->wm.spr_latency[0] &&
5814 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5815 dev_priv->display.update_wm = sandybridge_update_wm;
5816 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5817 } else {
5818 DRM_DEBUG_KMS("Failed to read display plane latency. "
5819 "Disable CxSR\n");
5820 dev_priv->display.update_wm = NULL;
5821 }
5822 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5823 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5824 if (dev_priv->wm.pri_latency[0] &&
5825 dev_priv->wm.spr_latency[0] &&
5826 dev_priv->wm.cur_latency[0]) {
c43d0188 5827 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5828 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5829 } else {
5830 DRM_DEBUG_KMS("Failed to read display plane latency. "
5831 "Disable CxSR\n");
5832 dev_priv->display.update_wm = NULL;
5833 }
5834 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5835 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5836 if (dev_priv->wm.pri_latency[0] &&
5837 dev_priv->wm.spr_latency[0] &&
5838 dev_priv->wm.cur_latency[0]) {
1011d8c4 5839 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5840 dev_priv->display.update_sprite_wm =
5841 haswell_update_sprite_wm;
6b8a5eeb
ED		 5842 } else {
5843 DRM_DEBUG_KMS("Failed to read display plane latency. "
5844 "Disable CxSR\n");
5845 dev_priv->display.update_wm = NULL;
5846 }
cad2a2d7 5847 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5848 } else
5849 dev_priv->display.update_wm = NULL;
5850 } else if (IS_VALLEYVIEW(dev)) {
5851 dev_priv->display.update_wm = valleyview_update_wm;
5852 dev_priv->display.init_clock_gating =
5853 valleyview_init_clock_gating;
1fa61106
ED		 5854 } else if (IS_PINEVIEW(dev)) {
5855 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5856 dev_priv->is_ddr3,
5857 dev_priv->fsb_freq,
5858 dev_priv->mem_freq)) {
5859 DRM_INFO("failed to find known CxSR latency "
5860 "(found ddr%s fsb freq %d, mem freq %d), "
5861 "disabling CxSR\n",
5862 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5863 dev_priv->fsb_freq, dev_priv->mem_freq);
5864 /* Disable CxSR and never update its watermark again */
5865 pineview_disable_cxsr(dev);
5866 dev_priv->display.update_wm = NULL;
5867 } else
5868 dev_priv->display.update_wm = pineview_update_wm;
5869 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5870 } else if (IS_G4X(dev)) {
5871 dev_priv->display.update_wm = g4x_update_wm;
5872 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5873 } else if (IS_GEN4(dev)) {
5874 dev_priv->display.update_wm = i965_update_wm;
5875 if (IS_CRESTLINE(dev))
5876 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5877 else if (IS_BROADWATER(dev))
5878 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5879 } else if (IS_GEN3(dev)) {
5880 dev_priv->display.update_wm = i9xx_update_wm;
5881 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5882 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5883 } else if (IS_I865G(dev)) {
5884 dev_priv->display.update_wm = i830_update_wm;
5885 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5886 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5887 } else if (IS_I85X(dev)) {
5888 dev_priv->display.update_wm = i9xx_update_wm;
5889 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5890 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5891 } else {
5892 dev_priv->display.update_wm = i830_update_wm;
5893 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5894 if (IS_845G(dev))
5895 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5896 else
5897 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5898 }
5899}
5900
42c0526c
BW		 5901int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5902{
4fc688ce 5903 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5904
5905 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5906 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5907 return -EAGAIN;
5908 }
5909
5910 I915_WRITE(GEN6_PCODE_DATA, *val);
5911 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5912
5913 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5914 500)) {
5915 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5916 return -ETIMEDOUT;
5917 }
5918
5919 *val = I915_READ(GEN6_PCODE_DATA);
5920 I915_WRITE(GEN6_PCODE_DATA, 0);
5921
5922 return 0;
5923}
5924
5925int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5926{
4fc688ce 5927 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5928
5929 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5930 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5931 return -EAGAIN;
5932 }
5933
5934 I915_WRITE(GEN6_PCODE_DATA, val);
5935 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5936
5937 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5938 500)) {
5939 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5940 return -ETIMEDOUT;
5941 }
5942
5943 I915_WRITE(GEN6_PCODE_DATA, 0);
5944
5945 return 0;
5946}
a0e4e199 5947
855ba3be
JB		 5948int vlv_gpu_freq(int ddr_freq, int val)
5949{
07ab118b 5950 int div;
855ba3be 5951
07ab118b 5952 /* 4 x czclk */
855ba3be
JB		 5953 switch (ddr_freq) {
5954 case 800:
07ab118b 5955 div = 10;
855ba3be
JB		 5956 break;
5957 case 1066:
07ab118b 5958 div = 12;
855ba3be
JB		 5959 break;
5960 case 1333:
07ab118b 5961 div = 16;
855ba3be
JB		 5962 break;
5963 default:
5964 return -1;
5965 }
5966
07ab118b 5967 return DIV_ROUND_CLOSEST(ddr_freq * (val + 6 - 0xbd), 4 * div);
855ba3be
JB		 5968}
5969
5970int vlv_freq_opcode(int ddr_freq, int val)
5971{
07ab118b 5972 int mul;
855ba3be 5973
07ab118b 5974 /* 4 x czclk */
855ba3be
JB		 5975 switch (ddr_freq) {
5976 case 800:
07ab118b 5977 mul = 10;
855ba3be
JB		 5978 break;
5979 case 1066:
07ab118b 5980 mul = 12;
855ba3be
JB		 5981 break;
5982 case 1333:
07ab118b 5983 mul = 16;
855ba3be
JB		 5984 break;
5985 default:
5986 return -1;
5987 }
5988
07ab118b 5989 return DIV_ROUND_CLOSEST(4 * mul * val, ddr_freq) + 0xbd - 6;
855ba3be
JB		 5990}
5991
907b28c5
CW		 5992void intel_pm_init(struct drm_device *dev)
5993{
5994 struct drm_i915_private *dev_priv = dev->dev_private;
5995
5996 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5997 intel_gen6_powersave_work);
5998}
5999
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