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drm/i915: Limit CHV max cdclk
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
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85208be0
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1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED
29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV
31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW
34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL
55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL
57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL
59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
62}
91e41d16 63
45db2194 64static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 65{
acd5c346 66 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 67
77719d28
DL
68 gen9_init_clock_gating(dev);
69
669506e7 70 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN
71 /*
72 * WaDisableSDEUnitClockGating:skl
9253c2e5 73 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN
74 */
75 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 76 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 77 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL
78
79 /* WaDisableVFUnitClockGating:skl */
80 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
81 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 82 }
8bc0ccf6 83
2caa3b26 84 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL
85 /* WaDisableHDCInvalidation:skl */
86 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
87 BDW_DISABLE_HDC_INVALIDATION);
88
2caa3b26
DL
89 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
90 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 91 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 92 }
81e231af 93
8bc0ccf6
DL
94 if (INTEL_REVID(dev) <= SKL_REVID_E0)
95 /* WaDisableLSQCROPERFforOCL:skl */
96 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
97 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL
98}
99
a82abe43
ID
100static void bxt_init_clock_gating(struct drm_device *dev)
101{
32608ca2
ID
102 struct drm_i915_private *dev_priv = dev->dev_private;
103
a82abe43 104 gen9_init_clock_gating(dev);
32608ca2
ID
105
106 /*
107 * FIXME:
108 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 109 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID
110 */
111 /* WaDisableSDEUnitClockGating:bxt */
112 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW
113 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
114 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 115
e3a29055
RB
116 /* FIXME: apply on A0 only */
117 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID
118}
119
c921aba8
DV
120static void i915_pineview_get_mem_freq(struct drm_device *dev)
121{
50227e1c 122 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV
123 u32 tmp;
124
125 tmp = I915_READ(CLKCFG);
126
127 switch (tmp & CLKCFG_FSB_MASK) {
128 case CLKCFG_FSB_533:
129 dev_priv->fsb_freq = 533; /* 133*4 */
130 break;
131 case CLKCFG_FSB_800:
132 dev_priv->fsb_freq = 800; /* 200*4 */
133 break;
134 case CLKCFG_FSB_667:
135 dev_priv->fsb_freq = 667; /* 167*4 */
136 break;
137 case CLKCFG_FSB_400:
138 dev_priv->fsb_freq = 400; /* 100*4 */
139 break;
140 }
141
142 switch (tmp & CLKCFG_MEM_MASK) {
143 case CLKCFG_MEM_533:
144 dev_priv->mem_freq = 533;
145 break;
146 case CLKCFG_MEM_667:
147 dev_priv->mem_freq = 667;
148 break;
149 case CLKCFG_MEM_800:
150 dev_priv->mem_freq = 800;
151 break;
152 }
153
154 /* detect pineview DDR3 setting */
155 tmp = I915_READ(CSHRDDR3CTL);
156 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
157}
158
159static void i915_ironlake_get_mem_freq(struct drm_device *dev)
160{
50227e1c 161 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV
162 u16 ddrpll, csipll;
163
164 ddrpll = I915_READ16(DDRMPLL1);
165 csipll = I915_READ16(CSIPLL0);
166
167 switch (ddrpll & 0xff) {
168 case 0xc:
169 dev_priv->mem_freq = 800;
170 break;
171 case 0x10:
172 dev_priv->mem_freq = 1066;
173 break;
174 case 0x14:
175 dev_priv->mem_freq = 1333;
176 break;
177 case 0x18:
178 dev_priv->mem_freq = 1600;
179 break;
180 default:
181 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
182 ddrpll & 0xff);
183 dev_priv->mem_freq = 0;
184 break;
185 }
186
20e4d407 187 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV
188
189 switch (csipll & 0x3ff) {
190 case 0x00c:
191 dev_priv->fsb_freq = 3200;
192 break;
193 case 0x00e:
194 dev_priv->fsb_freq = 3733;
195 break;
196 case 0x010:
197 dev_priv->fsb_freq = 4266;
198 break;
199 case 0x012:
200 dev_priv->fsb_freq = 4800;
201 break;
202 case 0x014:
203 dev_priv->fsb_freq = 5333;
204 break;
205 case 0x016:
206 dev_priv->fsb_freq = 5866;
207 break;
208 case 0x018:
209 dev_priv->fsb_freq = 6400;
210 break;
211 default:
212 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
213 csipll & 0x3ff);
214 dev_priv->fsb_freq = 0;
215 break;
216 }
217
218 if (dev_priv->fsb_freq == 3200) {
20e4d407 219 dev_priv->ips.c_m = 0;
c921aba8 220 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 221 dev_priv->ips.c_m = 1;
c921aba8 222 } else {
20e4d407 223 dev_priv->ips.c_m = 2;
c921aba8
DV
224 }
225}
226
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ED
227static const struct cxsr_latency cxsr_latency_table[] = {
228 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
229 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
230 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
231 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
232 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
233
234 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
235 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
236 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
237 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
238 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
239
240 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
241 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
242 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
243 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
244 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
245
246 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
247 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
248 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
249 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
250 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
251
252 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
253 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
254 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
255 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
256 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
257
258 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
259 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
260 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
261 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
262 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
263};
264
63c62275 265static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED
266 int is_ddr3,
267 int fsb,
268 int mem)
269{
270 const struct cxsr_latency *latency;
271 int i;
272
273 if (fsb == 0 || mem == 0)
274 return NULL;
275
276 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
277 latency = &cxsr_latency_table[i];
278 if (is_desktop == latency->is_desktop &&
279 is_ddr3 == latency->is_ddr3 &&
280 fsb == latency->fsb_freq && mem == latency->mem_freq)
281 return latency;
282 }
283
284 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
285
286 return NULL;
287}
288
fc1ac8de
VS
289static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
290{
291 u32 val;
292
293 mutex_lock(&dev_priv->rps.hw_lock);
294
295 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
296 if (enable)
297 val &= ~FORCE_DDR_HIGH_FREQ;
298 else
299 val |= FORCE_DDR_HIGH_FREQ;
300 val &= ~FORCE_DDR_LOW_FREQ;
301 val |= FORCE_DDR_FREQ_REQ_ACK;
302 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
303
304 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
305 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
306 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
307
308 mutex_unlock(&dev_priv->rps.hw_lock);
309}
310
cfb41411
VS
311static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
312{
313 u32 val;
314
315 mutex_lock(&dev_priv->rps.hw_lock);
316
317 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
318 if (enable)
319 val |= DSP_MAXFIFO_PM5_ENABLE;
320 else
321 val &= ~DSP_MAXFIFO_PM5_ENABLE;
322 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
323
324 mutex_unlock(&dev_priv->rps.hw_lock);
325}
326
f4998963
VS
327#define FW_WM(value, plane) \
328 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
329
5209b1f4 330void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 331{
5209b1f4
ID
332 struct drm_device *dev = dev_priv->dev;
333 u32 val;
b445e3b0 334
5209b1f4
ID
335 if (IS_VALLEYVIEW(dev)) {
336 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
cfb41411
VS
337 if (IS_CHERRYVIEW(dev))
338 chv_set_memory_pm5(dev_priv, enable);
5209b1f4
ID
339 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
340 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
341 } else if (IS_PINEVIEW(dev)) {
342 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
343 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
344 I915_WRITE(DSPFW3, val);
345 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
346 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
347 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
348 I915_WRITE(FW_BLC_SELF, val);
349 } else if (IS_I915GM(dev)) {
350 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
351 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
352 I915_WRITE(INSTPM, val);
353 } else {
354 return;
355 }
b445e3b0 356
5209b1f4
ID
357 DRM_DEBUG_KMS("memory self-refresh is %s\n",
358 enable ? "enabled" : "disabled");
b445e3b0
ED
359}
360
fc1ac8de 361
b445e3b0
ED
362/*
363 * Latency for FIFO fetches is dependent on several factors:
364 * - memory configuration (speed, channels)
365 * - chipset
366 * - current MCH state
367 * It can be fairly high in some situations, so here we assume a fairly
368 * pessimal value. It's a tradeoff between extra memory fetches (if we
369 * set this value too high, the FIFO will fetch frequently to stay full)
370 * and power consumption (set it too low to save power and we might see
371 * FIFO underruns and display "flicker").
372 *
373 * A value of 5us seems to be a good balance; safe for very low end
374 * platforms but not overly aggressive on lower latency configs.
375 */
5aef6003 376static const int pessimal_latency_ns = 5000;
b445e3b0 377
b5004720
VS
378#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
379 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
380
381static int vlv_get_fifo_size(struct drm_device *dev,
382 enum pipe pipe, int plane)
383{
384 struct drm_i915_private *dev_priv = dev->dev_private;
385 int sprite0_start, sprite1_start, size;
386
387 switch (pipe) {
388 uint32_t dsparb, dsparb2, dsparb3;
389 case PIPE_A:
390 dsparb = I915_READ(DSPARB);
391 dsparb2 = I915_READ(DSPARB2);
392 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
393 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
394 break;
395 case PIPE_B:
396 dsparb = I915_READ(DSPARB);
397 dsparb2 = I915_READ(DSPARB2);
398 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
399 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
400 break;
401 case PIPE_C:
402 dsparb2 = I915_READ(DSPARB2);
403 dsparb3 = I915_READ(DSPARB3);
404 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
405 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
406 break;
407 default:
408 return 0;
409 }
410
411 switch (plane) {
412 case 0:
413 size = sprite0_start;
414 break;
415 case 1:
416 size = sprite1_start - sprite0_start;
417 break;
418 case 2:
419 size = 512 - 1 - sprite1_start;
420 break;
421 default:
422 return 0;
423 }
424
425 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
426 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
427 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
428 size);
429
430 return size;
431}
432
1fa61106 433static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED
434{
435 struct drm_i915_private *dev_priv = dev->dev_private;
436 uint32_t dsparb = I915_READ(DSPARB);
437 int size;
438
439 size = dsparb & 0x7f;
440 if (plane)
441 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
442
443 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
444 plane ? "B" : "A", size);
445
446 return size;
447}
448
feb56b93 449static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED
450{
451 struct drm_i915_private *dev_priv = dev->dev_private;
452 uint32_t dsparb = I915_READ(DSPARB);
453 int size;
454
455 size = dsparb & 0x1ff;
456 if (plane)
457 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
458 size >>= 1; /* Convert to cachelines */
459
460 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
461 plane ? "B" : "A", size);
462
463 return size;
464}
465
1fa61106 466static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED
467{
468 struct drm_i915_private *dev_priv = dev->dev_private;
469 uint32_t dsparb = I915_READ(DSPARB);
470 int size;
471
472 size = dsparb & 0x7f;
473 size >>= 2; /* Convert to cachelines */
474
475 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
476 plane ? "B" : "A",
477 size);
478
479 return size;
480}
481
b445e3b0
ED
482/* Pineview has different values for various configs */
483static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS
484 .fifo_size = PINEVIEW_DISPLAY_FIFO,
485 .max_wm = PINEVIEW_MAX_WM,
486 .default_wm = PINEVIEW_DFT_WM,
487 .guard_size = PINEVIEW_GUARD_WM,
488 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
489};
490static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS
491 .fifo_size = PINEVIEW_DISPLAY_FIFO,
492 .max_wm = PINEVIEW_MAX_WM,
493 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
494 .guard_size = PINEVIEW_GUARD_WM,
495 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
496};
497static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS
498 .fifo_size = PINEVIEW_CURSOR_FIFO,
499 .max_wm = PINEVIEW_CURSOR_MAX_WM,
500 .default_wm = PINEVIEW_CURSOR_DFT_WM,
501 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
502 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
503};
504static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS
505 .fifo_size = PINEVIEW_CURSOR_FIFO,
506 .max_wm = PINEVIEW_CURSOR_MAX_WM,
507 .default_wm = PINEVIEW_CURSOR_DFT_WM,
508 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
509 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED
510};
511static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS
512 .fifo_size = G4X_FIFO_SIZE,
513 .max_wm = G4X_MAX_WM,
514 .default_wm = G4X_MAX_WM,
515 .guard_size = 2,
516 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED
517};
518static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS
519 .fifo_size = I965_CURSOR_FIFO,
520 .max_wm = I965_CURSOR_MAX_WM,
521 .default_wm = I965_CURSOR_DFT_WM,
522 .guard_size = 2,
523 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED
524};
525static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS
526 .fifo_size = VALLEYVIEW_FIFO_SIZE,
527 .max_wm = VALLEYVIEW_MAX_WM,
528 .default_wm = VALLEYVIEW_MAX_WM,
529 .guard_size = 2,
530 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED
531};
532static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS
533 .fifo_size = I965_CURSOR_FIFO,
534 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
535 .default_wm = I965_CURSOR_DFT_WM,
536 .guard_size = 2,
537 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED
538};
539static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS
540 .fifo_size = I965_CURSOR_FIFO,
541 .max_wm = I965_CURSOR_MAX_WM,
542 .default_wm = I965_CURSOR_DFT_WM,
543 .guard_size = 2,
544 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED
545};
546static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS
547 .fifo_size = I945_FIFO_SIZE,
548 .max_wm = I915_MAX_WM,
549 .default_wm = 1,
550 .guard_size = 2,
551 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED
552};
553static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS
554 .fifo_size = I915_FIFO_SIZE,
555 .max_wm = I915_MAX_WM,
556 .default_wm = 1,
557 .guard_size = 2,
558 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 559};
9d539105 560static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS
561 .fifo_size = I855GM_FIFO_SIZE,
562 .max_wm = I915_MAX_WM,
563 .default_wm = 1,
564 .guard_size = 2,
565 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 566};
9d539105
VS
567static const struct intel_watermark_params i830_bc_wm_info = {
568 .fifo_size = I855GM_FIFO_SIZE,
569 .max_wm = I915_MAX_WM/2,
570 .default_wm = 1,
571 .guard_size = 2,
572 .cacheline_size = I830_FIFO_LINE_SIZE,
573};
feb56b93 574static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS
575 .fifo_size = I830_FIFO_SIZE,
576 .max_wm = I915_MAX_WM,
577 .default_wm = 1,
578 .guard_size = 2,
579 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED
580};
581
b445e3b0
ED
582/**
583 * intel_calculate_wm - calculate watermark level
584 * @clock_in_khz: pixel clock
585 * @wm: chip FIFO params
586 * @pixel_size: display pixel size
587 * @latency_ns: memory latency for the platform
588 *
589 * Calculate the watermark level (the level at which the display plane will
590 * start fetching from memory again). Each chip has a different display
591 * FIFO size and allocation, so the caller needs to figure that out and pass
592 * in the correct intel_watermark_params structure.
593 *
594 * As the pixel clock runs, the FIFO will be drained at a rate that depends
595 * on the pixel size. When it reaches the watermark level, it'll start
596 * fetching FIFO line sized based chunks from memory until the FIFO fills
597 * past the watermark point. If the FIFO drains completely, a FIFO underrun
598 * will occur, and a display engine hang could result.
599 */
600static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
601 const struct intel_watermark_params *wm,
602 int fifo_size,
603 int pixel_size,
604 unsigned long latency_ns)
605{
606 long entries_required, wm_size;
607
608 /*
609 * Note: we need to make sure we don't overflow for various clock &
610 * latency values.
611 * clocks go from a few thousand to several hundred thousand.
612 * latency is usually a few thousand
613 */
614 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
615 1000;
616 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
617
618 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
619
620 wm_size = fifo_size - (entries_required + wm->guard_size);
621
622 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
623
624 /* Don't promote wm_size to unsigned... */
625 if (wm_size > (long)wm->max_wm)
626 wm_size = wm->max_wm;
627 if (wm_size <= 0)
628 wm_size = wm->default_wm;
d6feb196
VS
629
630 /*
631 * Bspec seems to indicate that the value shouldn't be lower than
632 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
633 * Lets go for 8 which is the burst size since certain platforms
634 * already use a hardcoded 8 (which is what the spec says should be
635 * done).
636 */
637 if (wm_size <= 8)
638 wm_size = 8;
639
b445e3b0
ED
640 return wm_size;
641}
642
643static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
644{
645 struct drm_crtc *crtc, *enabled = NULL;
646
70e1e0ec 647 for_each_crtc(dev, crtc) {
3490ea5d 648 if (intel_crtc_active(crtc)) {
b445e3b0
ED
649 if (enabled)
650 return NULL;
651 enabled = crtc;
652 }
653 }
654
655 return enabled;
656}
657
46ba614c 658static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 659{
46ba614c 660 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
661 struct drm_i915_private *dev_priv = dev->dev_private;
662 struct drm_crtc *crtc;
663 const struct cxsr_latency *latency;
664 u32 reg;
665 unsigned long wm;
666
667 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
668 dev_priv->fsb_freq, dev_priv->mem_freq);
669 if (!latency) {
670 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 671 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
672 return;
673 }
674
675 crtc = single_enabled_crtc(dev);
676 if (crtc) {
241bfc38 677 const struct drm_display_mode *adjusted_mode;
59bea882 678 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL
679 int clock;
680
6e3c9717 681 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 682 clock = adjusted_mode->crtc_clock;
b445e3b0
ED
683
684 /* Display SR */
685 wm = intel_calculate_wm(clock, &pineview_display_wm,
686 pineview_display_wm.fifo_size,
687 pixel_size, latency->display_sr);
688 reg = I915_READ(DSPFW1);
689 reg &= ~DSPFW_SR_MASK;
f4998963 690 reg |= FW_WM(wm, SR);
b445e3b0
ED
691 I915_WRITE(DSPFW1, reg);
692 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
693
694 /* cursor SR */
695 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
696 pineview_display_wm.fifo_size,
697 pixel_size, latency->cursor_sr);
698 reg = I915_READ(DSPFW3);
699 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 700 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED
701 I915_WRITE(DSPFW3, reg);
702
703 /* Display HPLL off SR */
704 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
705 pineview_display_hplloff_wm.fifo_size,
706 pixel_size, latency->display_hpll_disable);
707 reg = I915_READ(DSPFW3);
708 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 709 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED
710 I915_WRITE(DSPFW3, reg);
711
712 /* cursor HPLL off SR */
713 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
714 pineview_display_hplloff_wm.fifo_size,
715 pixel_size, latency->cursor_hpll_disable);
716 reg = I915_READ(DSPFW3);
717 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 718 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED
719 I915_WRITE(DSPFW3, reg);
720 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
721
5209b1f4 722 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 723 } else {
5209b1f4 724 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
725 }
726}
727
728static bool g4x_compute_wm0(struct drm_device *dev,
729 int plane,
730 const struct intel_watermark_params *display,
731 int display_latency_ns,
732 const struct intel_watermark_params *cursor,
733 int cursor_latency_ns,
734 int *plane_wm,
735 int *cursor_wm)
736{
737 struct drm_crtc *crtc;
4fe8590a 738 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
739 int htotal, hdisplay, clock, pixel_size;
740 int line_time_us, line_count;
741 int entries, tlb_miss;
742
743 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 744 if (!intel_crtc_active(crtc)) {
b445e3b0
ED
745 *cursor_wm = cursor->guard_size;
746 *plane_wm = display->guard_size;
747 return false;
748 }
749
6e3c9717 750 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 751 clock = adjusted_mode->crtc_clock;
fec8cba3 752 htotal = adjusted_mode->crtc_htotal;
6e3c9717 753 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 754 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED
755
756 /* Use the small buffer method to calculate plane watermark */
757 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
758 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
759 if (tlb_miss > 0)
760 entries += tlb_miss;
761 entries = DIV_ROUND_UP(entries, display->cacheline_size);
762 *plane_wm = entries + display->guard_size;
763 if (*plane_wm > (int)display->max_wm)
764 *plane_wm = display->max_wm;
765
766 /* Use the large buffer method to calculate cursor watermark */
922044c9 767 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 768 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 769 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED
770 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
771 if (tlb_miss > 0)
772 entries += tlb_miss;
773 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
774 *cursor_wm = entries + cursor->guard_size;
775 if (*cursor_wm > (int)cursor->max_wm)
776 *cursor_wm = (int)cursor->max_wm;
777
778 return true;
779}
780
781/*
782 * Check the wm result.
783 *
784 * If any calculated watermark values is larger than the maximum value that
785 * can be programmed into the associated watermark register, that watermark
786 * must be disabled.
787 */
788static bool g4x_check_srwm(struct drm_device *dev,
789 int display_wm, int cursor_wm,
790 const struct intel_watermark_params *display,
791 const struct intel_watermark_params *cursor)
792{
793 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
794 display_wm, cursor_wm);
795
796 if (display_wm > display->max_wm) {
797 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
798 display_wm, display->max_wm);
799 return false;
800 }
801
802 if (cursor_wm > cursor->max_wm) {
803 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
804 cursor_wm, cursor->max_wm);
805 return false;
806 }
807
808 if (!(display_wm || cursor_wm)) {
809 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
810 return false;
811 }
812
813 return true;
814}
815
816static bool g4x_compute_srwm(struct drm_device *dev,
817 int plane,
818 int latency_ns,
819 const struct intel_watermark_params *display,
820 const struct intel_watermark_params *cursor,
821 int *display_wm, int *cursor_wm)
822{
823 struct drm_crtc *crtc;
4fe8590a 824 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
825 int hdisplay, htotal, pixel_size, clock;
826 unsigned long line_time_us;
827 int line_count, line_size;
828 int small, large;
829 int entries;
830
831 if (!latency_ns) {
832 *display_wm = *cursor_wm = 0;
833 return false;
834 }
835
836 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 837 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 838 clock = adjusted_mode->crtc_clock;
fec8cba3 839 htotal = adjusted_mode->crtc_htotal;
6e3c9717 840 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 841 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 842
922044c9 843 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
844 line_count = (latency_ns / line_time_us + 1000) / 1000;
845 line_size = hdisplay * pixel_size;
846
847 /* Use the minimum of the small and large buffer method for primary */
848 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
849 large = line_count * line_size;
850
851 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
852 *display_wm = entries + display->guard_size;
853
854 /* calculate the self-refresh watermark for display cursor */
3dd512fb 855 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED
856 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
857 *cursor_wm = entries + cursor->guard_size;
858
859 return g4x_check_srwm(dev,
860 *display_wm, *cursor_wm,
861 display, cursor);
862}
863
15665979
VS
864#define FW_WM_VLV(value, plane) \
865 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
866
0018fda1
VS
867static void vlv_write_wm_values(struct intel_crtc *crtc,
868 const struct vlv_wm_values *wm)
869{
870 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
871 enum pipe pipe = crtc->pipe;
872
873 I915_WRITE(VLV_DDL(pipe),
874 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
875 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
876 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
877 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
878
ae80152d 879 I915_WRITE(DSPFW1,
15665979
VS
880 FW_WM(wm->sr.plane, SR) |
881 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
882 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
883 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 884 I915_WRITE(DSPFW2,
15665979
VS
885 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
886 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
887 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 888 I915_WRITE(DSPFW3,
15665979 889 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS
890
891 if (IS_CHERRYVIEW(dev_priv)) {
892 I915_WRITE(DSPFW7_CHV,
15665979
VS
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
894 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 895 I915_WRITE(DSPFW8_CHV,
15665979
VS
896 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
897 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 898 I915_WRITE(DSPFW9_CHV,
15665979
VS
899 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
900 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 901 I915_WRITE(DSPHOWM,
15665979
VS
902 FW_WM(wm->sr.plane >> 9, SR_HI) |
903 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
904 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
905 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
906 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
907 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
908 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
909 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
910 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
911 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS
912 } else {
913 I915_WRITE(DSPFW7,
15665979
VS
914 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
915 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 916 I915_WRITE(DSPHOWM,
15665979
VS
917 FW_WM(wm->sr.plane >> 9, SR_HI) |
918 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
919 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
920 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
921 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
922 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
923 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS
924 }
925
926 POSTING_READ(DSPFW1);
927
0018fda1
VS
928 dev_priv->wm.vlv = *wm;
929}
930
15665979
VS
931#undef FW_WM_VLV
932
341c526f 933static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc,
883a3d2f 934 struct drm_plane *plane)
b445e3b0 935{
5e56ba45 936 struct drm_device *dev = crtc->dev;
883a3d2f
VS
937 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
938 int entries, prec_mult, drain_latency, pixel_size;
939 int clock = intel_crtc->config->base.adjusted_mode.crtc_clock;
341c526f 940 const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64;
b445e3b0 941
883a3d2f
VS
942 /*
943 * FIXME the plane might have an fb
944 * but be invisible (eg. due to clipping)
945 */
946 if (!intel_crtc->active || !plane->state->fb)
947 return 0;
948
0948c265 949 if (WARN(clock == 0, "Pixel clock is zero!\n"))
341c526f 950 return 0;
b445e3b0 951
883a3d2f
VS
952 pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0);
953
0948c265 954 if (WARN(pixel_size == 0, "Pixel size is zero!\n"))
341c526f 955 return 0;
b445e3b0 956
a398e9c7 957 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
abfc00b5 958
341c526f
VS
959 prec_mult = high_precision;
960 drain_latency = 64 * prec_mult * 4 / entries;
b445e3b0 961
341c526f
VS
962 if (drain_latency > DRAIN_LATENCY_MASK) {
963 prec_mult /= 2;
964 drain_latency = 64 * prec_mult * 4 / entries;
abfc00b5
VS
965 }
966
341c526f
VS
967 if (drain_latency > DRAIN_LATENCY_MASK)
968 drain_latency = DRAIN_LATENCY_MASK;
b445e3b0 969
341c526f
VS
970 return drain_latency | (prec_mult == high_precision ?
971 DDL_PRECISION_HIGH : DDL_PRECISION_LOW);
b445e3b0
ED
972}
973
ae80152d
VS
974static int vlv_compute_wm(struct intel_crtc *crtc,
975 struct intel_plane *plane,
976 int fifo_size)
b445e3b0 977{
ae80152d 978 int clock, entries, pixel_size;
b445e3b0 979
ae80152d
VS
980 /*
981 * FIXME the plane might have an fb
982 * but be invisible (eg. due to clipping)
983 */
984 if (!crtc->active || !plane->base.state->fb)
985 return 0;
0948c265 986
ae80152d
VS
987 pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0);
988 clock = crtc->config->base.adjusted_mode.crtc_clock;
b445e3b0 989
ae80152d 990 entries = DIV_ROUND_UP(clock, 1000) * pixel_size;
b445e3b0 991
ae80152d
VS
992 /*
993 * Set up the watermark such that we don't start issuing memory
994 * requests until we are within PND's max deadline value (256us).
995 * Idea being to be idle as long as possible while still taking
996 * advatange of PND's deadline scheduling. The limit of 8
997 * cachelines (used when the FIFO will anyway drain in less time
998 * than 256us) should match what we would be done if trickle
999 * feed were enabled.
1000 */
1001 return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8);
1002}
1003
1004static bool vlv_compute_sr_wm(struct drm_device *dev,
1005 struct vlv_wm_values *wm)
b445e3b0 1006{
ae80152d
VS
1007 struct drm_i915_private *dev_priv = to_i915(dev);
1008 struct drm_crtc *crtc;
1009 enum pipe pipe = INVALID_PIPE;
1010 int num_planes = 0;
1011 int fifo_size = 0;
1012 struct intel_plane *plane;
b445e3b0 1013
ae80152d 1014 wm->sr.cursor = wm->sr.plane = 0;
b445e3b0 1015
ae80152d
VS
1016 crtc = single_enabled_crtc(dev);
1017 /* maxfifo not supported on pipe C */
1018 if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) {
1019 pipe = to_intel_crtc(crtc)->pipe;
1020 num_planes = !!wm->pipe[pipe].primary +
1021 !!wm->pipe[pipe].sprite[0] +
1022 !!wm->pipe[pipe].sprite[1];
1023 fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
1024 }
b445e3b0 1025
ae80152d
VS
1026 if (fifo_size == 0 || num_planes > 1)
1027 return false;
b445e3b0 1028
ae80152d
VS
1029 wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc),
1030 to_intel_plane(crtc->cursor), 0x3f);
b445e3b0 1031
ae80152d
VS
1032 list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) {
1033 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1034 continue;
b445e3b0 1035
ae80152d
VS
1036 if (plane->pipe != pipe)
1037 continue;
9858425c 1038
ae80152d
VS
1039 wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc),
1040 plane, fifo_size);
1041 if (wm->sr.plane != 0)
1042 break;
1043 }
1044
1045 return true;
b445e3b0
ED
1046}
1047
ae80152d 1048static void valleyview_update_wm(struct drm_crtc *crtc)
3c2777fd
VS
1049{
1050 struct drm_device *dev = crtc->dev;
3c2777fd 1051 struct drm_i915_private *dev_priv = dev->dev_private;
ae80152d
VS
1052 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1053 enum pipe pipe = intel_crtc->pipe;
3c2777fd 1054 bool cxsr_enabled;
ae80152d 1055 struct vlv_wm_values wm = dev_priv->wm.vlv;
3c2777fd 1056
ae80152d
VS
1057 wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary);
1058 wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc,
1059 to_intel_plane(crtc->primary),
1060 vlv_get_fifo_size(dev, pipe, 0));
3c2777fd 1061
ae80152d
VS
1062 wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor);
1063 wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc,
1064 to_intel_plane(crtc->cursor),
1065 0x3f);
3c2777fd 1066
ae80152d 1067 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
3c2777fd 1068
ae80152d
VS
1069 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1070 return;
3c2777fd 1071
ae80152d
VS
1072 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1073 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1074 wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1075 wm.sr.plane, wm.sr.cursor);
3c2777fd 1076
fc1ac8de
VS
1077 /*
1078 * FIXME DDR DVFS introduces massive memory latencies which
1079 * are not known to system agent so any deadline specified
1080 * by the display may not be respected. To support DDR DVFS
1081 * the watermark code needs to be rewritten to essentially
1082 * bypass deadline mechanism and rely solely on the
1083 * watermarks. For now disable DDR DVFS.
1084 */
1085 if (IS_CHERRYVIEW(dev_priv))
1086 chv_set_memory_dvfs(dev_priv, false);
1087
ae80152d
VS
1088 if (!cxsr_enabled)
1089 intel_set_memory_cxsr(dev_priv, false);
3c2777fd 1090
ae80152d 1091 vlv_write_wm_values(intel_crtc, &wm);
3c2777fd
VS
1092
1093 if (cxsr_enabled)
1094 intel_set_memory_cxsr(dev_priv, true);
1095}
1096
01e184cc
GB
1097static void valleyview_update_sprite_wm(struct drm_plane *plane,
1098 struct drm_crtc *crtc,
1099 uint32_t sprite_width,
1100 uint32_t sprite_height,
1101 int pixel_size,
1102 bool enabled, bool scaled)
1103{
1104 struct drm_device *dev = crtc->dev;
1105 struct drm_i915_private *dev_priv = dev->dev_private;
0018fda1
VS
1106 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1107 enum pipe pipe = intel_crtc->pipe;
01e184cc 1108 int sprite = to_intel_plane(plane)->plane;
ae80152d 1109 bool cxsr_enabled;
0018fda1 1110 struct vlv_wm_values wm = dev_priv->wm.vlv;
01e184cc 1111
ae80152d 1112 if (enabled) {
0018fda1 1113 wm.ddl[pipe].sprite[sprite] =
883a3d2f 1114 vlv_compute_drain_latency(crtc, plane);
ae80152d
VS
1115
1116 wm.pipe[pipe].sprite[sprite] =
1117 vlv_compute_wm(intel_crtc,
1118 to_intel_plane(plane),
1119 vlv_get_fifo_size(dev, pipe, sprite+1));
1120 } else {
0018fda1 1121 wm.ddl[pipe].sprite[sprite] = 0;
ae80152d
VS
1122 wm.pipe[pipe].sprite[sprite] = 0;
1123 }
1124
1125 cxsr_enabled = vlv_compute_sr_wm(dev, &wm);
1126
1127 if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0)
1128 return;
1129
1130 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, "
1131 "SR: plane=%d, cursor=%d\n", pipe_name(pipe),
1132 sprite_name(pipe, sprite),
1133 wm.pipe[pipe].sprite[sprite],
1134 wm.sr.plane, wm.sr.cursor);
1135
1136 if (!cxsr_enabled)
1137 intel_set_memory_cxsr(dev_priv, false);
01e184cc 1138
0018fda1 1139 vlv_write_wm_values(intel_crtc, &wm);
ae80152d
VS
1140
1141 if (cxsr_enabled)
1142 intel_set_memory_cxsr(dev_priv, true);
01e184cc
GB
1143}
1144
ae80152d
VS
1145#define single_plane_enabled(mask) is_power_of_2(mask)
1146
46ba614c 1147static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1148{
46ba614c 1149 struct drm_device *dev = crtc->dev;
b445e3b0
ED
1150 static const int sr_latency_ns = 12000;
1151 struct drm_i915_private *dev_priv = dev->dev_private;
1152 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1153 int plane_sr, cursor_sr;
1154 unsigned int enabled = 0;
9858425c 1155 bool cxsr_enabled;
b445e3b0 1156
51cea1f4 1157 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW
1158 &g4x_wm_info, pessimal_latency_ns,
1159 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1160 &planea_wm, &cursora_wm))
51cea1f4 1161 enabled |= 1 << PIPE_A;
b445e3b0 1162
51cea1f4 1163 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW
1164 &g4x_wm_info, pessimal_latency_ns,
1165 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1166 &planeb_wm, &cursorb_wm))
51cea1f4 1167 enabled |= 1 << PIPE_B;
b445e3b0 1168
b445e3b0
ED
1169 if (single_plane_enabled(enabled) &&
1170 g4x_compute_srwm(dev, ffs(enabled) - 1,
1171 sr_latency_ns,
1172 &g4x_wm_info,
1173 &g4x_cursor_wm_info,
52bd02d8 1174 &plane_sr, &cursor_sr)) {
9858425c 1175 cxsr_enabled = true;
52bd02d8 1176 } else {
9858425c 1177 cxsr_enabled = false;
5209b1f4 1178 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW
1179 plane_sr = cursor_sr = 0;
1180 }
b445e3b0 1181
a5043453
VS
1182 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1183 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED
1184 planea_wm, cursora_wm,
1185 planeb_wm, cursorb_wm,
1186 plane_sr, cursor_sr);
1187
1188 I915_WRITE(DSPFW1,
f4998963
VS
1189 FW_WM(plane_sr, SR) |
1190 FW_WM(cursorb_wm, CURSORB) |
1191 FW_WM(planeb_wm, PLANEB) |
1192 FW_WM(planea_wm, PLANEA));
b445e3b0 1193 I915_WRITE(DSPFW2,
8c919b28 1194 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1195 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED
1196 /* HPLL off in SR has some issues on G4x... disable it */
1197 I915_WRITE(DSPFW3,
8c919b28 1198 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1199 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID
1200
1201 if (cxsr_enabled)
1202 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1203}
1204
46ba614c 1205static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1206{
46ba614c 1207 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1208 struct drm_i915_private *dev_priv = dev->dev_private;
1209 struct drm_crtc *crtc;
1210 int srwm = 1;
1211 int cursor_sr = 16;
9858425c 1212 bool cxsr_enabled;
b445e3b0
ED
1213
1214 /* Calc sr entries for one plane configs */
1215 crtc = single_enabled_crtc(dev);
1216 if (crtc) {
1217 /* self-refresh has much higher latency */
1218 static const int sr_latency_ns = 12000;
4fe8590a 1219 const struct drm_display_mode *adjusted_mode =
6e3c9717 1220 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1221 int clock = adjusted_mode->crtc_clock;
fec8cba3 1222 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1223 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1224 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED
1225 unsigned long line_time_us;
1226 int entries;
1227
922044c9 1228 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
1229
1230 /* Use ns/us then divide to preserve precision */
1231 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1232 pixel_size * hdisplay;
1233 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1234 srwm = I965_FIFO_SIZE - entries;
1235 if (srwm < 0)
1236 srwm = 1;
1237 srwm &= 0x1ff;
1238 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1239 entries, srwm);
1240
1241 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1242 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED
1243 entries = DIV_ROUND_UP(entries,
1244 i965_cursor_wm_info.cacheline_size);
1245 cursor_sr = i965_cursor_wm_info.fifo_size -
1246 (entries + i965_cursor_wm_info.guard_size);
1247
1248 if (cursor_sr > i965_cursor_wm_info.max_wm)
1249 cursor_sr = i965_cursor_wm_info.max_wm;
1250
1251 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1252 "cursor %d\n", srwm, cursor_sr);
1253
9858425c 1254 cxsr_enabled = true;
b445e3b0 1255 } else {
9858425c 1256 cxsr_enabled = false;
b445e3b0 1257 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1258 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
1259 }
1260
1261 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1262 srwm);
1263
1264 /* 965 has limitations... */
f4998963
VS
1265 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1266 FW_WM(8, CURSORB) |
1267 FW_WM(8, PLANEB) |
1268 FW_WM(8, PLANEA));
1269 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1270 FW_WM(8, PLANEC_OLD));
b445e3b0 1271 /* update cursor SR watermark */
f4998963 1272 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID
1273
1274 if (cxsr_enabled)
1275 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1276}
1277
f4998963
VS
1278#undef FW_WM
1279
46ba614c 1280static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1281{
46ba614c 1282 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1283 struct drm_i915_private *dev_priv = dev->dev_private;
1284 const struct intel_watermark_params *wm_info;
1285 uint32_t fwater_lo;
1286 uint32_t fwater_hi;
1287 int cwm, srwm = 1;
1288 int fifo_size;
1289 int planea_wm, planeb_wm;
1290 struct drm_crtc *crtc, *enabled = NULL;
1291
1292 if (IS_I945GM(dev))
1293 wm_info = &i945_wm_info;
1294 else if (!IS_GEN2(dev))
1295 wm_info = &i915_wm_info;
1296 else
9d539105 1297 wm_info = &i830_a_wm_info;
b445e3b0
ED
1298
1299 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1300 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1301 if (intel_crtc_active(crtc)) {
241bfc38 1302 const struct drm_display_mode *adjusted_mode;
59bea882 1303 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW
1304 if (IS_GEN2(dev))
1305 cpp = 4;
1306
6e3c9717 1307 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1308 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1309 wm_info, fifo_size, cpp,
5aef6003 1310 pessimal_latency_ns);
b445e3b0 1311 enabled = crtc;
9d539105 1312 } else {
b445e3b0 1313 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS
1314 if (planea_wm > (long)wm_info->max_wm)
1315 planea_wm = wm_info->max_wm;
1316 }
1317
1318 if (IS_GEN2(dev))
1319 wm_info = &i830_bc_wm_info;
b445e3b0
ED
1320
1321 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1322 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1323 if (intel_crtc_active(crtc)) {
241bfc38 1324 const struct drm_display_mode *adjusted_mode;
59bea882 1325 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW
1326 if (IS_GEN2(dev))
1327 cpp = 4;
1328
6e3c9717 1329 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1330 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1331 wm_info, fifo_size, cpp,
5aef6003 1332 pessimal_latency_ns);
b445e3b0
ED
1333 if (enabled == NULL)
1334 enabled = crtc;
1335 else
1336 enabled = NULL;
9d539105 1337 } else {
b445e3b0 1338 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS
1339 if (planeb_wm > (long)wm_info->max_wm)
1340 planeb_wm = wm_info->max_wm;
1341 }
b445e3b0
ED
1342
1343 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1344
2ab1bc9d 1345 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1346 struct drm_i915_gem_object *obj;
2ab1bc9d 1347
59bea882 1348 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV
1349
1350 /* self-refresh seems busted with untiled */
2ff8fde1 1351 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV
1352 enabled = NULL;
1353 }
1354
b445e3b0
ED
1355 /*
1356 * Overlay gets an aggressive default since video jitter is bad.
1357 */
1358 cwm = 2;
1359
1360 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1361 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED
1362
1363 /* Calc sr entries for one plane configs */
1364 if (HAS_FW_BLC(dev) && enabled) {
1365 /* self-refresh has much higher latency */
1366 static const int sr_latency_ns = 6000;
4fe8590a 1367 const struct drm_display_mode *adjusted_mode =
6e3c9717 1368 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1369 int clock = adjusted_mode->crtc_clock;
fec8cba3 1370 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1371 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1372 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED
1373 unsigned long line_time_us;
1374 int entries;
1375
922044c9 1376 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED
1377
1378 /* Use ns/us then divide to preserve precision */
1379 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1380 pixel_size * hdisplay;
1381 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1382 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1383 srwm = wm_info->fifo_size - entries;
1384 if (srwm < 0)
1385 srwm = 1;
1386
1387 if (IS_I945G(dev) || IS_I945GM(dev))
1388 I915_WRITE(FW_BLC_SELF,
1389 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1390 else if (IS_I915GM(dev))
1391 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1392 }
1393
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1395 planea_wm, planeb_wm, cwm, srwm);
1396
1397 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1398 fwater_hi = (cwm & 0x1f);
1399
1400 /* Set request length to 8 cachelines per fetch */
1401 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1402 fwater_hi = fwater_hi | (1 << 8);
1403
1404 I915_WRITE(FW_BLC, fwater_lo);
1405 I915_WRITE(FW_BLC2, fwater_hi);
1406
5209b1f4
ID
1407 if (enabled)
1408 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED
1409}
1410
feb56b93 1411static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1412{
46ba614c 1413 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED
1414 struct drm_i915_private *dev_priv = dev->dev_private;
1415 struct drm_crtc *crtc;
241bfc38 1416 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED
1417 uint32_t fwater_lo;
1418 int planea_wm;
1419
1420 crtc = single_enabled_crtc(dev);
1421 if (crtc == NULL)
1422 return;
1423
6e3c9717 1424 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1425 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1426 &i845_wm_info,
b445e3b0 1427 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1428 4, pessimal_latency_ns);
b445e3b0
ED
1429 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1430 fwater_lo |= (3<<8) | planea_wm;
1431
1432 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1433
1434 I915_WRITE(FW_BLC, fwater_lo);
1435}
1436
8cfb3407 1437uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1438{
fd4daa9c 1439 uint32_t pixel_rate;
801bcfff 1440
8cfb3407 1441 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ
1442
1443 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1444 * adjust the pixel_rate here. */
1445
8cfb3407 1446 if (pipe_config->pch_pfit.enabled) {
801bcfff 1447 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS
1448 uint32_t pfit_size = pipe_config->pch_pfit.size;
1449
1450 pipe_w = pipe_config->pipe_src_w;
1451 pipe_h = pipe_config->pipe_src_h;
801bcfff 1452
801bcfff
PZ
1453 pfit_w = (pfit_size >> 16) & 0xFFFF;
1454 pfit_h = pfit_size & 0xFFFF;
1455 if (pipe_w < pfit_w)
1456 pipe_w = pfit_w;
1457 if (pipe_h < pfit_h)
1458 pipe_h = pfit_h;
1459
1460 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1461 pfit_w * pfit_h);
1462 }
1463
1464 return pixel_rate;
1465}
1466
37126462 1467/* latency must be in 0.1us units. */
23297044 1468static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ
1469 uint32_t latency)
1470{
1471 uint64_t ret;
1472
3312ba65
VS
1473 if (WARN(latency == 0, "Latency value missing\n"))
1474 return UINT_MAX;
1475
801bcfff
PZ
1476 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1477 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1478
1479 return ret;
1480}
1481
37126462 1482/* latency must be in 0.1us units. */
23297044 1483static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ
1484 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1485 uint32_t latency)
1486{
1487 uint32_t ret;
1488
3312ba65
VS
1489 if (WARN(latency == 0, "Latency value missing\n"))
1490 return UINT_MAX;
1491
801bcfff
PZ
1492 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1493 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1494 ret = DIV_ROUND_UP(ret, 64) + 2;
1495 return ret;
1496}
1497
23297044 1498static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ
1499 uint8_t bytes_per_pixel)
1500{
1501 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1502}
1503
2ac96d2a
PB
1504struct skl_pipe_wm_parameters {
1505 bool active;
1506 uint32_t pipe_htotal;
1507 uint32_t pixel_rate; /* in KHz */
1508 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1509 struct intel_plane_wm_parameters cursor;
1510};
1511
820c1980 1512struct ilk_pipe_wm_parameters {
801bcfff 1513 bool active;
801bcfff
PZ
1514 uint32_t pipe_htotal;
1515 uint32_t pixel_rate;
c35426d2
VS
1516 struct intel_plane_wm_parameters pri;
1517 struct intel_plane_wm_parameters spr;
1518 struct intel_plane_wm_parameters cur;
801bcfff
PZ
1519};
1520
820c1980 1521struct ilk_wm_maximums {
cca32e9a
PZ
1522 uint16_t pri;
1523 uint16_t spr;
1524 uint16_t cur;
1525 uint16_t fbc;
1526};
1527
240264f4
VS
1528/* used in computing the new watermarks state */
1529struct intel_wm_config {
1530 unsigned int num_pipes_active;
1531 bool sprites_enabled;
1532 bool sprites_scaled;
240264f4
VS
1533};
1534
37126462
VS
1535/*
1536 * For both WM_PIPE and WM_LP.
1537 * mem_value must be in 0.1us units.
1538 */
820c1980 1539static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ
1540 uint32_t mem_value,
1541 bool is_lp)
801bcfff 1542{
cca32e9a
PZ
1543 uint32_t method1, method2;
1544
c35426d2 1545 if (!params->active || !params->pri.enabled)
801bcfff
PZ
1546 return 0;
1547
23297044 1548 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1549 params->pri.bytes_per_pixel,
cca32e9a
PZ
1550 mem_value);
1551
1552 if (!is_lp)
1553 return method1;
1554
23297044 1555 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1556 params->pipe_htotal,
c35426d2
VS
1557 params->pri.horiz_pixels,
1558 params->pri.bytes_per_pixel,
cca32e9a
PZ
1559 mem_value);
1560
1561 return min(method1, method2);
801bcfff
PZ
1562}
1563
37126462
VS
1564/*
1565 * For both WM_PIPE and WM_LP.
1566 * mem_value must be in 0.1us units.
1567 */
820c1980 1568static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ
1569 uint32_t mem_value)
1570{
1571 uint32_t method1, method2;
1572
c35426d2 1573 if (!params->active || !params->spr.enabled)
801bcfff
PZ
1574 return 0;
1575
23297044 1576 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1577 params->spr.bytes_per_pixel,
801bcfff 1578 mem_value);
23297044 1579 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1580 params->pipe_htotal,
c35426d2
VS
1581 params->spr.horiz_pixels,
1582 params->spr.bytes_per_pixel,
801bcfff
PZ
1583 mem_value);
1584 return min(method1, method2);
1585}
1586
37126462
VS
1587/*
1588 * For both WM_PIPE and WM_LP.
1589 * mem_value must be in 0.1us units.
1590 */
820c1980 1591static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ
1592 uint32_t mem_value)
1593{
c35426d2 1594 if (!params->active || !params->cur.enabled)
801bcfff
PZ
1595 return 0;
1596
23297044 1597 return ilk_wm_method2(params->pixel_rate,
801bcfff 1598 params->pipe_htotal,
c35426d2
VS
1599 params->cur.horiz_pixels,
1600 params->cur.bytes_per_pixel,
801bcfff
PZ
1601 mem_value);
1602}
1603
cca32e9a 1604/* Only for WM_LP. */
820c1980 1605static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1606 uint32_t pri_val)
cca32e9a 1607{
c35426d2 1608 if (!params->active || !params->pri.enabled)
cca32e9a
PZ
1609 return 0;
1610
23297044 1611 return ilk_wm_fbc(pri_val,
c35426d2
VS
1612 params->pri.horiz_pixels,
1613 params->pri.bytes_per_pixel);
cca32e9a
PZ
1614}
1615
158ae64f
VS
1616static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1617{
416f4727
VS
1618 if (INTEL_INFO(dev)->gen >= 8)
1619 return 3072;
1620 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS
1621 return 768;
1622 else
1623 return 512;
1624}
1625
4e975081
VS
1626static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1627 int level, bool is_sprite)
1628{
1629 if (INTEL_INFO(dev)->gen >= 8)
1630 /* BDW primary/sprite plane watermarks */
1631 return level == 0 ? 255 : 2047;
1632 else if (INTEL_INFO(dev)->gen >= 7)
1633 /* IVB/HSW primary/sprite plane watermarks */
1634 return level == 0 ? 127 : 1023;
1635 else if (!is_sprite)
1636 /* ILK/SNB primary plane watermarks */
1637 return level == 0 ? 127 : 511;
1638 else
1639 /* ILK/SNB sprite plane watermarks */
1640 return level == 0 ? 63 : 255;
1641}
1642
1643static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1644 int level)
1645{
1646 if (INTEL_INFO(dev)->gen >= 7)
1647 return level == 0 ? 63 : 255;
1648 else
1649 return level == 0 ? 31 : 63;
1650}
1651
1652static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1653{
1654 if (INTEL_INFO(dev)->gen >= 8)
1655 return 31;
1656 else
1657 return 15;
1658}
1659
158ae64f
VS
1660/* Calculate the maximum primary/sprite plane watermark */
1661static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1662 int level,
240264f4 1663 const struct intel_wm_config *config,
158ae64f
VS
1664 enum intel_ddb_partitioning ddb_partitioning,
1665 bool is_sprite)
1666{
1667 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS
1668
1669 /* if sprites aren't enabled, sprites get nothing */
240264f4 1670 if (is_sprite && !config->sprites_enabled)
158ae64f
VS
1671 return 0;
1672
1673 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1674 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS
1675 fifo_size /= INTEL_INFO(dev)->num_pipes;
1676
1677 /*
1678 * For some reason the non self refresh
1679 * FIFO size is only half of the self
1680 * refresh FIFO size on ILK/SNB.
1681 */
1682 if (INTEL_INFO(dev)->gen <= 6)
1683 fifo_size /= 2;
1684 }
1685
240264f4 1686 if (config->sprites_enabled) {
158ae64f
VS
1687 /* level 0 is always calculated with 1:1 split */
1688 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1689 if (is_sprite)
1690 fifo_size *= 5;
1691 fifo_size /= 6;
1692 } else {
1693 fifo_size /= 2;
1694 }
1695 }
1696
1697 /* clamp to max that the registers can hold */
4e975081 1698 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS
1699}
1700
1701/* Calculate the maximum cursor plane watermark */
1702static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS
1703 int level,
1704 const struct intel_wm_config *config)
158ae64f
VS
1705{
1706 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1707 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS
1708 return 64;
1709
1710 /* otherwise just report max that registers can hold */
4e975081 1711 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS
1712}
1713
d34ff9c6 1714static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS
1715 int level,
1716 const struct intel_wm_config *config,
1717 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1718 struct ilk_wm_maximums *max)
158ae64f 1719{
240264f4
VS
1720 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1721 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1722 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1723 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS
1724}
1725
a3cb4048
VS
1726static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1727 int level,
1728 struct ilk_wm_maximums *max)
1729{
1730 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1731 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1732 max->cur = ilk_cursor_wm_reg_max(dev, level);
1733 max->fbc = ilk_fbc_wm_reg_max(dev);
1734}
1735
d9395655 1736static bool ilk_validate_wm_level(int level,
820c1980 1737 const struct ilk_wm_maximums *max,
d9395655 1738 struct intel_wm_level *result)
a9786a11
VS
1739{
1740 bool ret;
1741
1742 /* already determined to be invalid? */
1743 if (!result->enable)
1744 return false;
1745
1746 result->enable = result->pri_val <= max->pri &&
1747 result->spr_val <= max->spr &&
1748 result->cur_val <= max->cur;
1749
1750 ret = result->enable;
1751
1752 /*
1753 * HACK until we can pre-compute everything,
1754 * and thus fail gracefully if LP0 watermarks
1755 * are exceeded...
1756 */
1757 if (level == 0 && !result->enable) {
1758 if (result->pri_val > max->pri)
1759 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1760 level, result->pri_val, max->pri);
1761 if (result->spr_val > max->spr)
1762 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1763 level, result->spr_val, max->spr);
1764 if (result->cur_val > max->cur)
1765 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1766 level, result->cur_val, max->cur);
1767
1768 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1769 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1770 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1771 result->enable = true;
1772 }
1773
a9786a11
VS
1774 return ret;
1775}
1776
d34ff9c6 1777static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 1778 int level,
820c1980 1779 const struct ilk_pipe_wm_parameters *p,
1fd527cc 1780 struct intel_wm_level *result)
6f5ddd17
VS
1781{
1782 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1783 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1784 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1785
1786 /* WM1+ latency values stored in 0.5us units */
1787 if (level > 0) {
1788 pri_latency *= 5;
1789 spr_latency *= 5;
1790 cur_latency *= 5;
1791 }
1792
1793 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
1794 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
1795 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
1796 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
1797 result->enable = true;
1798}
1799
801bcfff
PZ
1800static uint32_t
1801hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED
1802{
1803 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 1804 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 1805 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 1806 u32 linetime, ips_linetime;
1f8eeabf 1807
3ef00284 1808 if (!intel_crtc->active)
801bcfff 1809 return 0;
1011d8c4 1810
1f8eeabf
ED
1811 /* The WM are computed with base on how long it takes to fill a single
1812 * row at the given clock rate, multiplied by 8.
1813 * */
fec8cba3
JB
1814 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
1815 mode->crtc_clock);
1816 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 1817 dev_priv->cdclk_freq);
1f8eeabf 1818
801bcfff
PZ
1819 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
1820 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED
1821}
1822
2af30a5c 1823static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS
1824{
1825 struct drm_i915_private *dev_priv = dev->dev_private;
1826
2af30a5c
PB
1827 if (IS_GEN9(dev)) {
1828 uint32_t val;
4f947386 1829 int ret, i;
367294be 1830 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB
1831
1832 /* read the first set of memory latencies[0:3] */
1833 val = 0; /* data0 to be programmed to 0 for first set */
1834 mutex_lock(&dev_priv->rps.hw_lock);
1835 ret = sandybridge_pcode_read(dev_priv,
1836 GEN9_PCODE_READ_MEM_LATENCY,
1837 &val);
1838 mutex_unlock(&dev_priv->rps.hw_lock);
1839
1840 if (ret) {
1841 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1842 return;
1843 }
1844
1845 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1846 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1847 GEN9_MEM_LATENCY_LEVEL_MASK;
1848 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1849 GEN9_MEM_LATENCY_LEVEL_MASK;
1850 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1851 GEN9_MEM_LATENCY_LEVEL_MASK;
1852
1853 /* read the second set of memory latencies[4:7] */
1854 val = 1; /* data0 to be programmed to 1 for second set */
1855 mutex_lock(&dev_priv->rps.hw_lock);
1856 ret = sandybridge_pcode_read(dev_priv,
1857 GEN9_PCODE_READ_MEM_LATENCY,
1858 &val);
1859 mutex_unlock(&dev_priv->rps.hw_lock);
1860 if (ret) {
1861 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
1862 return;
1863 }
1864
1865 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
1866 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
1867 GEN9_MEM_LATENCY_LEVEL_MASK;
1868 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
1869 GEN9_MEM_LATENCY_LEVEL_MASK;
1870 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
1871 GEN9_MEM_LATENCY_LEVEL_MASK;
1872
367294be 1873 /*
6f97235b
DL
1874 * WaWmMemoryReadLatency:skl
1875 *
367294be
VK
1876 * punit doesn't take into account the read latency so we need
1877 * to add 2us to the various latency levels we retrieve from
1878 * the punit.
1879 * - W0 is a bit special in that it's the only level that
1880 * can't be disabled if we want to have display working, so
1881 * we always add 2us there.
1882 * - For levels >=1, punit returns 0us latency when they are
1883 * disabled, so we respect that and don't add 2us then
4f947386
VK
1884 *
1885 * Additionally, if a level n (n > 1) has a 0us latency, all
1886 * levels m (m >= n) need to be disabled. We make sure to
1887 * sanitize the values out of the punit to satisfy this
1888 * requirement.
367294be
VK
1889 */
1890 wm[0] += 2;
1891 for (level = 1; level <= max_level; level++)
1892 if (wm[level] != 0)
1893 wm[level] += 2;
4f947386
VK
1894 else {
1895 for (i = level + 1; i <= max_level; i++)
1896 wm[i] = 0;
367294be 1897
4f947386
VK
1898 break;
1899 }
2af30a5c 1900 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS
1901 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1902
1903 wm[0] = (sskpd >> 56) & 0xFF;
1904 if (wm[0] == 0)
1905 wm[0] = sskpd & 0xF;
e5d5019e
VS
1906 wm[1] = (sskpd >> 4) & 0xFF;
1907 wm[2] = (sskpd >> 12) & 0xFF;
1908 wm[3] = (sskpd >> 20) & 0x1FF;
1909 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS
1910 } else if (INTEL_INFO(dev)->gen >= 6) {
1911 uint32_t sskpd = I915_READ(MCH_SSKPD);
1912
1913 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
1914 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
1915 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
1916 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS
1917 } else if (INTEL_INFO(dev)->gen >= 5) {
1918 uint32_t mltr = I915_READ(MLTR_ILK);
1919
1920 /* ILK primary LP0 latency is 700 ns */
1921 wm[0] = 7;
1922 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
1923 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS
1924 }
1925}
1926
53615a5e
VS
1927static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
1928{
1929 /* ILK sprite LP0 latency is 1300 ns */
1930 if (INTEL_INFO(dev)->gen == 5)
1931 wm[0] = 13;
1932}
1933
1934static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
1935{
1936 /* ILK cursor LP0 latency is 1300 ns */
1937 if (INTEL_INFO(dev)->gen == 5)
1938 wm[0] = 13;
1939
1940 /* WaDoubleCursorLP3Latency:ivb */
1941 if (IS_IVYBRIDGE(dev))
1942 wm[3] *= 2;
1943}
1944
546c81fd 1945int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 1946{
26ec971e 1947 /* how many WM levels are we expecting */
b6e742f6 1948 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB
1949 return 7;
1950 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 1951 return 4;
26ec971e 1952 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 1953 return 3;
26ec971e 1954 else
ad0d6dc4
VS
1955 return 2;
1956}
7526ed79 1957
ad0d6dc4
VS
1958static void intel_print_wm_latency(struct drm_device *dev,
1959 const char *name,
2af30a5c 1960 const uint16_t wm[8])
ad0d6dc4
VS
1961{
1962 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS
1963
1964 for (level = 0; level <= max_level; level++) {
1965 unsigned int latency = wm[level];
1966
1967 if (latency == 0) {
1968 DRM_ERROR("%s WM%d latency not provided\n",
1969 name, level);
1970 continue;
1971 }
1972
2af30a5c
PB
1973 /*
1974 * - latencies are in us on gen9.
1975 * - before then, WM1+ latency values are in 0.5us units
1976 */
1977 if (IS_GEN9(dev))
1978 latency *= 10;
1979 else if (level > 0)
26ec971e
VS
1980 latency *= 5;
1981
1982 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
1983 name, level, wm[level],
1984 latency / 10, latency % 10);
1985 }
1986}
1987
e95a2f75
VS
1988static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
1989 uint16_t wm[5], uint16_t min)
1990{
1991 int level, max_level = ilk_wm_max_level(dev_priv->dev);
1992
1993 if (wm[0] >= min)
1994 return false;
1995
1996 wm[0] = max(wm[0], min);
1997 for (level = 1; level <= max_level; level++)
1998 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
1999
2000 return true;
2001}
2002
2003static void snb_wm_latency_quirk(struct drm_device *dev)
2004{
2005 struct drm_i915_private *dev_priv = dev->dev_private;
2006 bool changed;
2007
2008 /*
2009 * The BIOS provided WM memory latency values are often
2010 * inadequate for high resolution displays. Adjust them.
2011 */
2012 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2013 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2014 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2015
2016 if (!changed)
2017 return;
2018
2019 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2020 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2021 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2022 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2023}
2024
fa50ad61 2025static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS
2026{
2027 struct drm_i915_private *dev_priv = dev->dev_private;
2028
2029 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2030
2031 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2032 sizeof(dev_priv->wm.pri_latency));
2033 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2034 sizeof(dev_priv->wm.pri_latency));
2035
2036 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2037 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS
2038
2039 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2040 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2041 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS
2042
2043 if (IS_GEN6(dev))
2044 snb_wm_latency_quirk(dev);
53615a5e
VS
2045}
2046
2af30a5c
PB
2047static void skl_setup_wm_latency(struct drm_device *dev)
2048{
2049 struct drm_i915_private *dev_priv = dev->dev_private;
2050
2051 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2052 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2053}
2054
820c1980 2055static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2056 struct ilk_pipe_wm_parameters *p)
1011d8c4 2057{
7c4a395f
VS
2058 struct drm_device *dev = crtc->dev;
2059 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2060 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2061 struct drm_plane *plane;
1011d8c4 2062
3ef00284 2063 if (!intel_crtc->active)
2a44b76b 2064 return;
801bcfff 2065
2a44b76b 2066 p->active = true;
6e3c9717 2067 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2068 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2069
54da691d 2070 if (crtc->primary->state->fb)
c9f038a1
MR
2071 p->pri.bytes_per_pixel =
2072 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG
2073 else
2074 p->pri.bytes_per_pixel = 4;
2075
2076 p->cur.bytes_per_pixel = 4;
2077 /*
2078 * TODO: for now, assume primary and cursor planes are always enabled.
2079 * Setting them to false makes the screen flicker.
2080 */
2081 p->pri.enabled = true;
2082 p->cur.enabled = true;
c9f038a1 2083
6e3c9717 2084 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2085 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2086
af2b653b 2087 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2088 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2089
2a44b76b 2090 if (intel_plane->pipe == pipe) {
7c4a395f 2091 p->spr = intel_plane->wm;
2a44b76b
VS
2092 break;
2093 }
2094 }
2095}
2096
2097static void ilk_compute_wm_config(struct drm_device *dev,
2098 struct intel_wm_config *config)
2099{
2100 struct intel_crtc *intel_crtc;
2101
2102 /* Compute the currently _active_ config */
d3fcc808 2103 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2104 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2105
2a44b76b
VS
2106 if (!wm->pipe_enabled)
2107 continue;
cca32e9a 2108
2a44b76b
VS
2109 config->sprites_enabled |= wm->sprites_enabled;
2110 config->sprites_scaled |= wm->sprites_scaled;
2111 config->num_pipes_active++;
cca32e9a 2112 }
801bcfff
PZ
2113}
2114
0b2ae6d7
VS
2115/* Compute new watermarks for the pipe */
2116static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2117 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS
2118 struct intel_pipe_wm *pipe_wm)
2119{
2120 struct drm_device *dev = crtc->dev;
d34ff9c6 2121 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS
2122 int level, max_level = ilk_wm_max_level(dev);
2123 /* LP0 watermark maximums depend on this pipe alone */
2124 struct intel_wm_config config = {
2125 .num_pipes_active = 1,
2126 .sprites_enabled = params->spr.enabled,
2127 .sprites_scaled = params->spr.scaled,
2128 };
820c1980 2129 struct ilk_wm_maximums max;
0b2ae6d7 2130
2a44b76b
VS
2131 pipe_wm->pipe_enabled = params->active;
2132 pipe_wm->sprites_enabled = params->spr.enabled;
2133 pipe_wm->sprites_scaled = params->spr.scaled;
2134
7b39a0b7
VS
2135 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2136 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2137 max_level = 1;
2138
2139 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2140 if (params->spr.scaled)
2141 max_level = 0;
2142
a3cb4048 2143 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2144
a42a5719 2145 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2146 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2147
a3cb4048
VS
2148 /* LP0 watermarks always use 1/2 DDB partitioning */
2149 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2150
0b2ae6d7 2151 /* At least LP0 must be valid */
a3cb4048
VS
2152 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2153 return false;
2154
2155 ilk_compute_wm_reg_maximums(dev, 1, &max);
2156
2157 for (level = 1; level <= max_level; level++) {
2158 struct intel_wm_level wm = {};
2159
2160 ilk_compute_wm_level(dev_priv, level, params, &wm);
2161
2162 /*
2163 * Disable any watermark level that exceeds the
2164 * register maximums since such watermarks are
2165 * always invalid.
2166 */
2167 if (!ilk_validate_wm_level(level, &max, &wm))
2168 break;
2169
2170 pipe_wm->wm[level] = wm;
2171 }
2172
2173 return true;
0b2ae6d7
VS
2174}
2175
2176/*
2177 * Merge the watermarks from all active pipes for a specific level.
2178 */
2179static void ilk_merge_wm_level(struct drm_device *dev,
2180 int level,
2181 struct intel_wm_level *ret_wm)
2182{
2183 const struct intel_crtc *intel_crtc;
2184
d52fea5b
VS
2185 ret_wm->enable = true;
2186
d3fcc808 2187 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS
2188 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2189 const struct intel_wm_level *wm = &active->wm[level];
2190
2191 if (!active->pipe_enabled)
2192 continue;
0b2ae6d7 2193
d52fea5b
VS
2194 /*
2195 * The watermark values may have been used in the past,
2196 * so we must maintain them in the registers for some
2197 * time even if the level is now disabled.
2198 */
0b2ae6d7 2199 if (!wm->enable)
d52fea5b 2200 ret_wm->enable = false;
0b2ae6d7
VS
2201
2202 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2203 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2204 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2205 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2206 }
0b2ae6d7
VS
2207}
2208
2209/*
2210 * Merge all low power watermarks for all active pipes.
2211 */
2212static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2213 const struct intel_wm_config *config,
820c1980 2214 const struct ilk_wm_maximums *max,
0b2ae6d7
VS
2215 struct intel_pipe_wm *merged)
2216{
2217 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2218 int last_enabled_level = max_level;
0b2ae6d7 2219
0ba22e26
VS
2220 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2221 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2222 config->num_pipes_active > 1)
2223 return;
2224
6c8b6c28
VS
2225 /* ILK: FBC WM must be disabled always */
2226 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS
2227
2228 /* merge each WM1+ level */
2229 for (level = 1; level <= max_level; level++) {
2230 struct intel_wm_level *wm = &merged->wm[level];
2231
2232 ilk_merge_wm_level(dev, level, wm);
2233
d52fea5b
VS
2234 if (level > last_enabled_level)
2235 wm->enable = false;
2236 else if (!ilk_validate_wm_level(level, max, wm))
2237 /* make sure all following levels get disabled */
2238 last_enabled_level = level - 1;
0b2ae6d7
VS
2239
2240 /*
2241 * The spec says it is preferred to disable
2242 * FBC WMs instead of disabling a WM level.
2243 */
2244 if (wm->fbc_val > max->fbc) {
d52fea5b
VS
2245 if (wm->enable)
2246 merged->fbc_wm_enabled = false;
0b2ae6d7
VS
2247 wm->fbc_val = 0;
2248 }
2249 }
6c8b6c28
VS
2250
2251 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2252 /*
2253 * FIXME this is racy. FBC might get enabled later.
2254 * What we should check here is whether FBC can be
2255 * enabled sometime later.
2256 */
2257 if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) {
2258 for (level = 2; level <= max_level; level++) {
2259 struct intel_wm_level *wm = &merged->wm[level];
2260
2261 wm->enable = false;
2262 }
2263 }
0b2ae6d7
VS
2264}
2265
b380ca3c
VS
2266static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2267{
2268 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2269 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2270}
2271
a68d68ee
VS
2272/* The value we need to program into the WM_LPx latency field */
2273static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2274{
2275 struct drm_i915_private *dev_priv = dev->dev_private;
2276
a42a5719 2277 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS
2278 return 2 * level;
2279 else
2280 return dev_priv->wm.pri_latency[level];
2281}
2282
820c1980 2283static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2284 const struct intel_pipe_wm *merged,
609cedef 2285 enum intel_ddb_partitioning partitioning,
820c1980 2286 struct ilk_wm_values *results)
801bcfff 2287{
0b2ae6d7
VS
2288 struct intel_crtc *intel_crtc;
2289 int level, wm_lp;
cca32e9a 2290
0362c781 2291 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2292 results->partitioning = partitioning;
cca32e9a 2293
0b2ae6d7 2294 /* LP1+ register values */
cca32e9a 2295 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2296 const struct intel_wm_level *r;
801bcfff 2297
b380ca3c 2298 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2299
0362c781 2300 r = &merged->wm[level];
cca32e9a 2301
d52fea5b
VS
2302 /*
2303 * Maintain the watermark values even if the level is
2304 * disabled. Doing otherwise could cause underruns.
2305 */
2306 results->wm_lp[wm_lp - 1] =
a68d68ee 2307 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS
2308 (r->pri_val << WM1_LP_SR_SHIFT) |
2309 r->cur_val;
2310
d52fea5b
VS
2311 if (r->enable)
2312 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2313
416f4727
VS
2314 if (INTEL_INFO(dev)->gen >= 8)
2315 results->wm_lp[wm_lp - 1] |=
2316 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2317 else
2318 results->wm_lp[wm_lp - 1] |=
2319 r->fbc_val << WM1_LP_FBC_SHIFT;
2320
d52fea5b
VS
2321 /*
2322 * Always set WM1S_LP_EN when spr_val != 0, even if the
2323 * level is disabled. Doing otherwise could cause underruns.
2324 */
6cef2b8a
VS
2325 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2326 WARN_ON(wm_lp != 1);
2327 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2328 } else
2329 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2330 }
801bcfff 2331
0b2ae6d7 2332 /* LP0 register values */
d3fcc808 2333 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS
2334 enum pipe pipe = intel_crtc->pipe;
2335 const struct intel_wm_level *r =
2336 &intel_crtc->wm.active.wm[0];
2337
2338 if (WARN_ON(!r->enable))
2339 continue;
2340
2341 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2342
0b2ae6d7
VS
2343 results->wm_pipe[pipe] =
2344 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2345 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2346 r->cur_val;
801bcfff
PZ
2347 }
2348}
2349
861f3389
PZ
2350/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2351 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2352static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS
2353 struct intel_pipe_wm *r1,
2354 struct intel_pipe_wm *r2)
861f3389 2355{
198a1e9b
VS
2356 int level, max_level = ilk_wm_max_level(dev);
2357 int level1 = 0, level2 = 0;
861f3389 2358
198a1e9b
VS
2359 for (level = 1; level <= max_level; level++) {
2360 if (r1->wm[level].enable)
2361 level1 = level;
2362 if (r2->wm[level].enable)
2363 level2 = level;
861f3389
PZ
2364 }
2365
198a1e9b
VS
2366 if (level1 == level2) {
2367 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ
2368 return r2;
2369 else
2370 return r1;
198a1e9b 2371 } else if (level1 > level2) {
861f3389
PZ
2372 return r1;
2373 } else {
2374 return r2;
2375 }
2376}
2377
49a687c4
VS
2378/* dirty bits used to track which watermarks need changes */
2379#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2380#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2381#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2382#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2383#define WM_DIRTY_FBC (1 << 24)
2384#define WM_DIRTY_DDB (1 << 25)
2385
055e393f 2386static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID
2387 const struct ilk_wm_values *old,
2388 const struct ilk_wm_values *new)
49a687c4
VS
2389{
2390 unsigned int dirty = 0;
2391 enum pipe pipe;
2392 int wm_lp;
2393
055e393f 2394 for_each_pipe(dev_priv, pipe) {
49a687c4
VS
2395 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2396 dirty |= WM_DIRTY_LINETIME(pipe);
2397 /* Must disable LP1+ watermarks too */
2398 dirty |= WM_DIRTY_LP_ALL;
2399 }
2400
2401 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2402 dirty |= WM_DIRTY_PIPE(pipe);
2403 /* Must disable LP1+ watermarks too */
2404 dirty |= WM_DIRTY_LP_ALL;
2405 }
2406 }
2407
2408 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2409 dirty |= WM_DIRTY_FBC;
2410 /* Must disable LP1+ watermarks too */
2411 dirty |= WM_DIRTY_LP_ALL;
2412 }
2413
2414 if (old->partitioning != new->partitioning) {
2415 dirty |= WM_DIRTY_DDB;
2416 /* Must disable LP1+ watermarks too */
2417 dirty |= WM_DIRTY_LP_ALL;
2418 }
2419
2420 /* LP1+ watermarks already deemed dirty, no need to continue */
2421 if (dirty & WM_DIRTY_LP_ALL)
2422 return dirty;
2423
2424 /* Find the lowest numbered LP1+ watermark in need of an update... */
2425 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2426 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2427 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2428 break;
2429 }
2430
2431 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2432 for (; wm_lp <= 3; wm_lp++)
2433 dirty |= WM_DIRTY_LP(wm_lp);
2434
2435 return dirty;
2436}
2437
8553c18e
VS
2438static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2439 unsigned int dirty)
801bcfff 2440{
820c1980 2441 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2442 bool changed = false;
801bcfff 2443
facd619b
VS
2444 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2445 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2446 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2447 changed = true;
facd619b
VS
2448 }
2449 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2450 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2451 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2452 changed = true;
facd619b
VS
2453 }
2454 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2455 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2456 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2457 changed = true;
facd619b 2458 }
801bcfff 2459
facd619b
VS
2460 /*
2461 * Don't touch WM1S_LP_EN here.
2462 * Doing so could cause underruns.
2463 */
6cef2b8a 2464
8553c18e
VS
2465 return changed;
2466}
2467
2468/*
2469 * The spec says we shouldn't write when we don't need, because every write
2470 * causes WMs to be re-evaluated, expending some power.
2471 */
820c1980
ID
2472static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2473 struct ilk_wm_values *results)
8553c18e
VS
2474{
2475 struct drm_device *dev = dev_priv->dev;
820c1980 2476 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS
2477 unsigned int dirty;
2478 uint32_t val;
2479
055e393f 2480 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS
2481 if (!dirty)
2482 return;
2483
2484 _ilk_disable_lp_wm(dev_priv, dirty);
2485
49a687c4 2486 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2487 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2488 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2489 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2490 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ
2491 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2492
49a687c4 2493 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2494 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2495 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2496 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2497 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ
2498 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2499
49a687c4 2500 if (dirty & WM_DIRTY_DDB) {
a42a5719 2501 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS
2502 val = I915_READ(WM_MISC);
2503 if (results->partitioning == INTEL_DDB_PART_1_2)
2504 val &= ~WM_MISC_DATA_PARTITION_5_6;
2505 else
2506 val |= WM_MISC_DATA_PARTITION_5_6;
2507 I915_WRITE(WM_MISC, val);
2508 } else {
2509 val = I915_READ(DISP_ARB_CTL2);
2510 if (results->partitioning == INTEL_DDB_PART_1_2)
2511 val &= ~DISP_DATA_PARTITION_5_6;
2512 else
2513 val |= DISP_DATA_PARTITION_5_6;
2514 I915_WRITE(DISP_ARB_CTL2, val);
2515 }
1011d8c4
PZ
2516 }
2517
49a687c4 2518 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ
2519 val = I915_READ(DISP_ARB_CTL);
2520 if (results->enable_fbc_wm)
2521 val &= ~DISP_FBC_WM_DIS;
2522 else
2523 val |= DISP_FBC_WM_DIS;
2524 I915_WRITE(DISP_ARB_CTL, val);
2525 }
2526
954911eb
ID
2527 if (dirty & WM_DIRTY_LP(1) &&
2528 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2529 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2530
2531 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS
2532 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2533 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2534 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2535 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2536 }
801bcfff 2537
facd619b 2538 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2539 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2540 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2541 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2542 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2543 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS
2544
2545 dev_priv->wm.hw = *results;
801bcfff
PZ
2546}
2547
8553c18e
VS
2548static bool ilk_disable_lp_wm(struct drm_device *dev)
2549{
2550 struct drm_i915_private *dev_priv = dev->dev_private;
2551
2552 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2553}
2554
b9cec075
DL
2555/*
2556 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2557 * different active planes.
2558 */
2559
2560#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2561#define BXT_DDB_SIZE 512
b9cec075
DL
2562
2563static void
2564skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2565 struct drm_crtc *for_crtc,
2566 const struct intel_wm_config *config,
2567 const struct skl_pipe_wm_parameters *params,
2568 struct skl_ddb_entry *alloc /* out */)
2569{
2570 struct drm_crtc *crtc;
2571 unsigned int pipe_size, ddb_size;
2572 int nth_active_pipe;
2573
2574 if (!params->active) {
2575 alloc->start = 0;
2576 alloc->end = 0;
2577 return;
2578 }
2579
43d735a6
DL
2580 if (IS_BROXTON(dev))
2581 ddb_size = BXT_DDB_SIZE;
2582 else
2583 ddb_size = SKL_DDB_SIZE;
b9cec075
DL
2584
2585 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2586
2587 nth_active_pipe = 0;
2588 for_each_crtc(dev, crtc) {
3ef00284 2589 if (!to_intel_crtc(crtc)->active)
b9cec075
DL
2590 continue;
2591
2592 if (crtc == for_crtc)
2593 break;
2594
2595 nth_active_pipe++;
2596 }
2597
2598 pipe_size = ddb_size / config->num_pipes_active;
2599 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2600 alloc->end = alloc->start + pipe_size;
b9cec075
DL
2601}
2602
2603static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2604{
2605 if (config->num_pipes_active == 1)
2606 return 32;
2607
2608 return 8;
2609}
2610
a269c583
DL
2611static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2612{
2613 entry->start = reg & 0x3ff;
2614 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL
2615 if (entry->end)
2616 entry->end += 1;
a269c583
DL
2617}
2618
08db6652
DL
2619void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2620 struct skl_ddb_allocation *ddb /* out */)
a269c583 2621{
a269c583
DL
2622 enum pipe pipe;
2623 int plane;
2624 u32 val;
2625
2626 for_each_pipe(dev_priv, pipe) {
dd740780 2627 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL
2628 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2629 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2630 val);
2631 }
2632
2633 val = I915_READ(CUR_BUF_CFG(pipe));
2634 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2635 }
2636}
2637
b9cec075 2638static unsigned int
2cd601c6 2639skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2640{
2cd601c6
CK
2641
2642 /* for planar format */
2643 if (p->y_bytes_per_pixel) {
2644 if (y) /* y-plane data rate */
2645 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2646 else /* uv-plane data rate */
2647 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2648 }
2649
2650 /* for packed formats */
b9cec075
DL
2651 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2652}
2653
2654/*
2655 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2656 * a 8192x4096@32bpp framebuffer:
2657 * 3 * 4096 * 8192 * 4 < 2^32
2658 */
2659static unsigned int
2660skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2661 const struct skl_pipe_wm_parameters *params)
2662{
2663 unsigned int total_data_rate = 0;
2664 int plane;
2665
2666 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2667 const struct intel_plane_wm_parameters *p;
2668
2669 p = &params->plane[plane];
2670 if (!p->enabled)
2671 continue;
2672
2cd601c6
CK
2673 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2674 if (p->y_bytes_per_pixel) {
2675 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2676 }
b9cec075
DL
2677 }
2678
2679 return total_data_rate;
2680}
2681
2682static void
2683skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2684 const struct intel_wm_config *config,
2685 const struct skl_pipe_wm_parameters *params,
2686 struct skl_ddb_allocation *ddb /* out */)
2687{
2688 struct drm_device *dev = crtc->dev;
dd740780 2689 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL
2690 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2691 enum pipe pipe = intel_crtc->pipe;
34bb56af 2692 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2693 uint16_t alloc_size, start, cursor_blocks;
80958155 2694 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2695 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL
2696 unsigned int total_data_rate;
2697 int plane;
2698
34bb56af
DL
2699 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2700 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL
2701 if (alloc_size == 0) {
2702 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2703 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2704 return;
2705 }
2706
2707 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL
2708 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2709 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL
2710
2711 alloc_size -= cursor_blocks;
34bb56af 2712 alloc->end -= cursor_blocks;
b9cec075 2713
80958155 2714 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2715 for_each_plane(dev_priv, pipe, plane) {
80958155
DL
2716 const struct intel_plane_wm_parameters *p;
2717
2718 p = &params->plane[plane];
2719 if (!p->enabled)
2720 continue;
2721
2722 minimum[plane] = 8;
2723 alloc_size -= minimum[plane];
2cd601c6
CK
2724 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2725 alloc_size -= y_minimum[plane];
80958155
DL
2726 }
2727
b9cec075 2728 /*
80958155
DL
2729 * 2. Distribute the remaining space in proportion to the amount of
2730 * data each plane needs to fetch from memory.
b9cec075
DL
2731 *
2732 * FIXME: we may not allocate every single block here.
2733 */
2734 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
2735
34bb56af 2736 start = alloc->start;
b9cec075
DL
2737 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2738 const struct intel_plane_wm_parameters *p;
2cd601c6
CK
2739 unsigned int data_rate, y_data_rate;
2740 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL
2741
2742 p = &params->plane[plane];
2743 if (!p->enabled)
2744 continue;
2745
2cd601c6 2746 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL
2747
2748 /*
2cd601c6 2749 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL
2750 * promote the expression to 64 bits to avoid overflowing, the
2751 * result is < available as data_rate / total_data_rate < 1
2752 */
80958155
DL
2753 plane_blocks = minimum[plane];
2754 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2755 total_data_rate);
b9cec075
DL
2756
2757 ddb->plane[pipe][plane].start = start;
16160e3d 2758 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL
2759
2760 start += plane_blocks;
2cd601c6
CK
2761
2762 /*
2763 * allocation for y_plane part of planar format:
2764 */
2765 if (p->y_bytes_per_pixel) {
2766 y_data_rate = skl_plane_relative_data_rate(p, 1);
2767 y_plane_blocks = y_minimum[plane];
2768 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
2769 total_data_rate);
2770
2771 ddb->y_plane[pipe][plane].start = start;
2772 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
2773
2774 start += y_plane_blocks;
2775 }
2776
b9cec075
DL
2777 }
2778
2779}
2780
5cec258b 2781static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB
2782{
2783 /* TODO: Take into account the scalers once we support them */
2d112de7 2784 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB
2785}
2786
2787/*
2788 * The max latency should be 257 (max the punit can code is 255 and we add 2us
2789 * for the read latency) and bytes_per_pixel should always be <= 8, so that
2790 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
2791 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
2792*/
2793static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2794 uint32_t latency)
2795{
2796 uint32_t wm_intermediate_val, ret;
2797
2798 if (latency == 0)
2799 return UINT_MAX;
2800
d4c2aa60 2801 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB
2802 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
2803
2804 return ret;
2805}
2806
2807static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2808 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 2809 uint64_t tiling, uint32_t latency)
2d41c0b5 2810{
d4c2aa60
TU
2811 uint32_t ret;
2812 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2813 uint32_t wm_intermediate_val;
2d41c0b5
PB
2814
2815 if (latency == 0)
2816 return UINT_MAX;
2817
2818 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU
2819
2820 if (tiling == I915_FORMAT_MOD_Y_TILED ||
2821 tiling == I915_FORMAT_MOD_Yf_TILED) {
2822 plane_bytes_per_line *= 4;
2823 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2824 plane_blocks_per_line /= 4;
2825 } else {
2826 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2827 }
2828
2d41c0b5
PB
2829 wm_intermediate_val = latency * pixel_rate;
2830 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 2831 plane_blocks_per_line;
2d41c0b5
PB
2832
2833 return ret;
2834}
2835
2d41c0b5
PB
2836static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
2837 const struct intel_crtc *intel_crtc)
2838{
2839 struct drm_device *dev = intel_crtc->base.dev;
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2842 enum pipe pipe = intel_crtc->pipe;
2843
2844 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
2845 sizeof(new_ddb->plane[pipe])))
2846 return true;
2847
2848 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
2849 sizeof(new_ddb->cursor[pipe])))
2850 return true;
2851
2852 return false;
2853}
2854
2855static void skl_compute_wm_global_parameters(struct drm_device *dev,
2856 struct intel_wm_config *config)
2857{
2858 struct drm_crtc *crtc;
2859 struct drm_plane *plane;
2860
2861 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 2862 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB
2863
2864 /* FIXME: I don't think we need those two global parameters on SKL */
2865 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2866 struct intel_plane *intel_plane = to_intel_plane(plane);
2867
2868 config->sprites_enabled |= intel_plane->wm.enabled;
2869 config->sprites_scaled |= intel_plane->wm.scaled;
2870 }
2871}
2872
2873static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
2874 struct skl_pipe_wm_parameters *p)
2875{
2876 struct drm_device *dev = crtc->dev;
2877 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2878 enum pipe pipe = intel_crtc->pipe;
2879 struct drm_plane *plane;
0fda6568 2880 struct drm_framebuffer *fb;
2d41c0b5
PB
2881 int i = 1; /* Index for sprite planes start */
2882
3ef00284 2883 p->active = intel_crtc->active;
2d41c0b5 2884 if (p->active) {
6e3c9717
ACO
2885 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
2886 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 2887
0fda6568 2888 fb = crtc->primary->state->fb;
2cd601c6 2889 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR
2890 if (fb) {
2891 p->plane[0].enabled = true;
2cd601c6
CK
2892 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2893 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
2894 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
2895 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 2896 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR
2897 } else {
2898 p->plane[0].enabled = false;
2899 p->plane[0].bytes_per_pixel = 0;
2cd601c6 2900 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR
2901 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
2902 }
2903 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
2904 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 2905 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 2906
c9f038a1 2907 fb = crtc->cursor->state->fb;
2cd601c6 2908 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR
2909 if (fb) {
2910 p->cursor.enabled = true;
2911 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
2912 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
2913 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
2914 } else {
2915 p->cursor.enabled = false;
2916 p->cursor.bytes_per_pixel = 0;
2917 p->cursor.horiz_pixels = 64;
2918 p->cursor.vert_pixels = 64;
2919 }
2d41c0b5
PB
2920 }
2921
2922 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2923 struct intel_plane *intel_plane = to_intel_plane(plane);
2924
a712f8eb
SJ
2925 if (intel_plane->pipe == pipe &&
2926 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB
2927 p->plane[i++] = intel_plane->wm;
2928 }
2929}
2930
d4c2aa60
TU
2931static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
2932 struct skl_pipe_wm_parameters *p,
afb024aa
DL
2933 struct intel_plane_wm_parameters *p_params,
2934 uint16_t ddb_allocation,
d4c2aa60 2935 int level,
afb024aa
DL
2936 uint16_t *out_blocks, /* out */
2937 uint8_t *out_lines /* out */)
2d41c0b5 2938{
d4c2aa60
TU
2939 uint32_t latency = dev_priv->wm.skl_latency[level];
2940 uint32_t method1, method2;
2941 uint32_t plane_bytes_per_line, plane_blocks_per_line;
2942 uint32_t res_blocks, res_lines;
2943 uint32_t selected_result;
2cd601c6 2944 uint8_t bytes_per_pixel;
2d41c0b5 2945
d4c2aa60 2946 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB
2947 return false;
2948
2cd601c6
CK
2949 bytes_per_pixel = p_params->y_bytes_per_pixel ?
2950 p_params->y_bytes_per_pixel :
2951 p_params->bytes_per_pixel;
2d41c0b5 2952 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 2953 bytes_per_pixel,
d4c2aa60 2954 latency);
2d41c0b5
PB
2955 method2 = skl_wm_method2(p->pixel_rate,
2956 p->pipe_htotal,
2957 p_params->horiz_pixels,
2cd601c6 2958 bytes_per_pixel,
0fda6568 2959 p_params->tiling,
d4c2aa60 2960 latency);
2d41c0b5 2961
2cd601c6 2962 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 2963 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 2964
0fda6568
TU
2965 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2966 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU
2967 uint32_t min_scanlines = 4;
2968 uint32_t y_tile_minimum;
2969 if (intel_rotation_90_or_270(p_params->rotation)) {
2970 switch (p_params->bytes_per_pixel) {
2971 case 1:
2972 min_scanlines = 16;
2973 break;
2974 case 2:
2975 min_scanlines = 8;
2976 break;
2977 case 8:
2978 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 2979 }
1fc0a8f7
TU
2980 }
2981 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU
2982 selected_result = max(method2, y_tile_minimum);
2983 } else {
2984 if ((ddb_allocation / plane_blocks_per_line) >= 1)
2985 selected_result = min(method1, method2);
2986 else
2987 selected_result = method1;
2988 }
2d41c0b5 2989
d4c2aa60
TU
2990 res_blocks = selected_result + 1;
2991 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 2992
0fda6568
TU
2993 if (level >= 1 && level <= 7) {
2994 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
2995 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
2996 res_lines += 4;
2997 else
2998 res_blocks++;
2999 }
e6d66171 3000
d4c2aa60 3001 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL
3002 return false;
3003
3004 *out_blocks = res_blocks;
3005 *out_lines = res_lines;
2d41c0b5
PB
3006
3007 return true;
3008}
3009
3010static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3011 struct skl_ddb_allocation *ddb,
3012 struct skl_pipe_wm_parameters *p,
3013 enum pipe pipe,
3014 int level,
3015 int num_planes,
3016 struct skl_wm_level *result)
3017{
2d41c0b5
PB
3018 uint16_t ddb_blocks;
3019 int i;
3020
3021 for (i = 0; i < num_planes; i++) {
3022 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3023
d4c2aa60
TU
3024 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3025 p, &p->plane[i],
2d41c0b5 3026 ddb_blocks,
d4c2aa60 3027 level,
2d41c0b5
PB
3028 &result->plane_res_b[i],
3029 &result->plane_res_l[i]);
3030 }
3031
3032 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU
3033 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3034 ddb_blocks, level,
3035 &result->cursor_res_b,
2d41c0b5
PB
3036 &result->cursor_res_l);
3037}
3038
407b50f3
DL
3039static uint32_t
3040skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3041{
3ef00284 3042 if (!to_intel_crtc(crtc)->active)
407b50f3
DL
3043 return 0;
3044
3045 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3046
3047}
3048
3049static void skl_compute_transition_wm(struct drm_crtc *crtc,
3050 struct skl_pipe_wm_parameters *params,
9414f563 3051 struct skl_wm_level *trans_wm /* out */)
407b50f3 3052{
9414f563
DL
3053 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3054 int i;
3055
407b50f3
DL
3056 if (!params->active)
3057 return;
9414f563
DL
3058
3059 /* Until we know more, just disable transition WMs */
3060 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3061 trans_wm->plane_en[i] = false;
3062 trans_wm->cursor_en = false;
407b50f3
DL
3063}
3064
2d41c0b5
PB
3065static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3066 struct skl_ddb_allocation *ddb,
3067 struct skl_pipe_wm_parameters *params,
3068 struct skl_pipe_wm *pipe_wm)
3069{
3070 struct drm_device *dev = crtc->dev;
3071 const struct drm_i915_private *dev_priv = dev->dev_private;
3072 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3073 int level, max_level = ilk_wm_max_level(dev);
3074
3075 for (level = 0; level <= max_level; level++) {
3076 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3077 level, intel_num_planes(intel_crtc),
3078 &pipe_wm->wm[level]);
3079 }
3080 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3081
9414f563 3082 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB
3083}
3084
3085static void skl_compute_wm_results(struct drm_device *dev,
3086 struct skl_pipe_wm_parameters *p,
3087 struct skl_pipe_wm *p_wm,
3088 struct skl_wm_values *r,
3089 struct intel_crtc *intel_crtc)
3090{
3091 int level, max_level = ilk_wm_max_level(dev);
3092 enum pipe pipe = intel_crtc->pipe;
9414f563
DL
3093 uint32_t temp;
3094 int i;
2d41c0b5
PB
3095
3096 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB
3097 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3098 temp = 0;
2d41c0b5
PB
3099
3100 temp |= p_wm->wm[level].plane_res_l[i] <<
3101 PLANE_WM_LINES_SHIFT;
3102 temp |= p_wm->wm[level].plane_res_b[i];
3103 if (p_wm->wm[level].plane_en[i])
3104 temp |= PLANE_WM_EN;
3105
3106 r->plane[pipe][i][level] = temp;
2d41c0b5
PB
3107 }
3108
3109 temp = 0;
2d41c0b5
PB
3110
3111 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3112 temp |= p_wm->wm[level].cursor_res_b;
3113
3114 if (p_wm->wm[level].cursor_en)
3115 temp |= PLANE_WM_EN;
3116
3117 r->cursor[pipe][level] = temp;
2d41c0b5
PB
3118
3119 }
3120
9414f563
DL
3121 /* transition WMs */
3122 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3123 temp = 0;
3124 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3125 temp |= p_wm->trans_wm.plane_res_b[i];
3126 if (p_wm->trans_wm.plane_en[i])
3127 temp |= PLANE_WM_EN;
3128
3129 r->plane_trans[pipe][i] = temp;
3130 }
3131
3132 temp = 0;
3133 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3134 temp |= p_wm->trans_wm.cursor_res_b;
3135 if (p_wm->trans_wm.cursor_en)
3136 temp |= PLANE_WM_EN;
3137
3138 r->cursor_trans[pipe] = temp;
3139
2d41c0b5
PB
3140 r->wm_linetime[pipe] = p_wm->linetime;
3141}
3142
16160e3d
DL
3143static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3144 const struct skl_ddb_entry *entry)
3145{
3146 if (entry->end)
3147 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3148 else
3149 I915_WRITE(reg, 0);
3150}
3151
2d41c0b5
PB
3152static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3153 const struct skl_wm_values *new)
3154{
3155 struct drm_device *dev = dev_priv->dev;
3156 struct intel_crtc *crtc;
3157
3158 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3159 int i, level, max_level = ilk_wm_max_level(dev);
3160 enum pipe pipe = crtc->pipe;
3161
5d374d96
DL
3162 if (!new->dirty[pipe])
3163 continue;
8211bd5b 3164
5d374d96 3165 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3166
5d374d96
DL
3167 for (level = 0; level <= max_level; level++) {
3168 for (i = 0; i < intel_num_planes(crtc); i++)
3169 I915_WRITE(PLANE_WM(pipe, i, level),
3170 new->plane[pipe][i][level]);
3171 I915_WRITE(CUR_WM(pipe, level),
3172 new->cursor[pipe][level]);
2d41c0b5 3173 }
5d374d96
DL
3174 for (i = 0; i < intel_num_planes(crtc); i++)
3175 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3176 new->plane_trans[pipe][i]);
3177 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3178
2cd601c6 3179 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL
3180 skl_ddb_entry_write(dev_priv,
3181 PLANE_BUF_CFG(pipe, i),
3182 &new->ddb.plane[pipe][i]);
2cd601c6
CK
3183 skl_ddb_entry_write(dev_priv,
3184 PLANE_NV12_BUF_CFG(pipe, i),
3185 &new->ddb.y_plane[pipe][i]);
3186 }
5d374d96
DL
3187
3188 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3189 &new->ddb.cursor[pipe]);
2d41c0b5 3190 }
2d41c0b5
PB
3191}
3192
0e8fb7ba
DL
3193/*
3194 * When setting up a new DDB allocation arrangement, we need to correctly
3195 * sequence the times at which the new allocations for the pipes are taken into
3196 * account or we'll have pipes fetching from space previously allocated to
3197 * another pipe.
3198 *
3199 * Roughly the sequence looks like:
3200 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3201 * overlapping with a previous light-up pipe (another way to put it is:
3202 * pipes with their new allocation strickly included into their old ones).
3203 * 2. re-allocate the other pipes that get their allocation reduced
3204 * 3. allocate the pipes having their allocation increased
3205 *
3206 * Steps 1. and 2. are here to take care of the following case:
3207 * - Initially DDB looks like this:
3208 * | B | C |
3209 * - enable pipe A.
3210 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3211 * allocation
3212 * | A | B | C |
3213 *
3214 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3215 */
3216
d21b795c
DL
3217static void
3218skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3219{
0e8fb7ba
DL
3220 int plane;
3221
d21b795c
DL
3222 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3223
dd740780 3224 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL
3225 I915_WRITE(PLANE_SURF(pipe, plane),
3226 I915_READ(PLANE_SURF(pipe, plane)));
3227 }
3228 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3229}
3230
3231static bool
3232skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3233 const struct skl_ddb_allocation *new,
3234 enum pipe pipe)
3235{
3236 uint16_t old_size, new_size;
3237
3238 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3239 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3240
3241 return old_size != new_size &&
3242 new->pipe[pipe].start >= old->pipe[pipe].start &&
3243 new->pipe[pipe].end <= old->pipe[pipe].end;
3244}
3245
3246static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3247 struct skl_wm_values *new_values)
3248{
3249 struct drm_device *dev = dev_priv->dev;
3250 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3251 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL
3252 struct intel_crtc *crtc;
3253 enum pipe pipe;
3254
3255 new_ddb = &new_values->ddb;
3256 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3257
3258 /*
3259 * First pass: flush the pipes with the new allocation contained into
3260 * the old space.
3261 *
3262 * We'll wait for the vblank on those pipes to ensure we can safely
3263 * re-allocate the freed space without this pipe fetching from it.
3264 */
3265 for_each_intel_crtc(dev, crtc) {
3266 if (!crtc->active)
3267 continue;
3268
3269 pipe = crtc->pipe;
3270
3271 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3272 continue;
3273
d21b795c 3274 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL
3275 intel_wait_for_vblank(dev, pipe);
3276
3277 reallocated[pipe] = true;
3278 }
3279
3280
3281 /*
3282 * Second pass: flush the pipes that are having their allocation
3283 * reduced, but overlapping with a previous allocation.
3284 *
3285 * Here as well we need to wait for the vblank to make sure the freed
3286 * space is not used anymore.
3287 */
3288 for_each_intel_crtc(dev, crtc) {
3289 if (!crtc->active)
3290 continue;
3291
3292 pipe = crtc->pipe;
3293
3294 if (reallocated[pipe])
3295 continue;
3296
3297 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3298 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3299 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3300 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3301 reallocated[pipe] = true;
0e8fb7ba 3302 }
0e8fb7ba
DL
3303 }
3304
3305 /*
3306 * Third pass: flush the pipes that got more space allocated.
3307 *
3308 * We don't need to actively wait for the update here, next vblank
3309 * will just get more DDB space with the correct WM values.
3310 */
3311 for_each_intel_crtc(dev, crtc) {
3312 if (!crtc->active)
3313 continue;
3314
3315 pipe = crtc->pipe;
3316
3317 /*
3318 * At this point, only the pipes more space than before are
3319 * left to re-allocate.
3320 */
3321 if (reallocated[pipe])
3322 continue;
3323
d21b795c 3324 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL
3325 }
3326}
3327
2d41c0b5
PB
3328static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3329 struct skl_pipe_wm_parameters *params,
3330 struct intel_wm_config *config,
3331 struct skl_ddb_allocation *ddb, /* out */
3332 struct skl_pipe_wm *pipe_wm /* out */)
3333{
3334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3335
3336 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3337 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB
3338 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3339
3340 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3341 return false;
3342
3343 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3344
2d41c0b5
PB
3345 return true;
3346}
3347
3348static void skl_update_other_pipe_wm(struct drm_device *dev,
3349 struct drm_crtc *crtc,
3350 struct intel_wm_config *config,
3351 struct skl_wm_values *r)
3352{
3353 struct intel_crtc *intel_crtc;
3354 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3355
3356 /*
3357 * If the WM update hasn't changed the allocation for this_crtc (the
3358 * crtc we are currently computing the new WM values for), other
3359 * enabled crtcs will keep the same allocation and we don't need to
3360 * recompute anything for them.
3361 */
3362 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3363 return;
3364
3365 /*
3366 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3367 * other active pipes need new DDB allocation and WM values.
3368 */
3369 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3370 base.head) {
3371 struct skl_pipe_wm_parameters params = {};
3372 struct skl_pipe_wm pipe_wm = {};
3373 bool wm_changed;
3374
3375 if (this_crtc->pipe == intel_crtc->pipe)
3376 continue;
3377
3378 if (!intel_crtc->active)
3379 continue;
3380
3381 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3382 &params, config,
3383 &r->ddb, &pipe_wm);
3384
3385 /*
3386 * If we end up re-computing the other pipe WM values, it's
3387 * because it was really needed, so we expect the WM values to
3388 * be different.
3389 */
3390 WARN_ON(!wm_changed);
3391
3392 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3393 r->dirty[intel_crtc->pipe] = true;
3394 }
3395}
3396
3397static void skl_update_wm(struct drm_crtc *crtc)
3398{
3399 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3400 struct drm_device *dev = crtc->dev;
3401 struct drm_i915_private *dev_priv = dev->dev_private;
3402 struct skl_pipe_wm_parameters params = {};
3403 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3404 struct skl_pipe_wm pipe_wm = {};
3405 struct intel_wm_config config = {};
3406
3407 memset(results, 0, sizeof(*results));
3408
3409 skl_compute_wm_global_parameters(dev, &config);
3410
3411 if (!skl_update_pipe_wm(crtc, &params, &config,
3412 &results->ddb, &pipe_wm))
3413 return;
3414
3415 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3416 results->dirty[intel_crtc->pipe] = true;
3417
3418 skl_update_other_pipe_wm(dev, crtc, &config, results);
3419 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3420 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL
3421
3422 /* store the new configuration */
3423 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB
3424}
3425
3426static void
3427skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3428 uint32_t sprite_width, uint32_t sprite_height,
3429 int pixel_size, bool enabled, bool scaled)
3430{
3431 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3432 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB
3433
3434 intel_plane->wm.enabled = enabled;
3435 intel_plane->wm.scaled = scaled;
3436 intel_plane->wm.horiz_pixels = sprite_width;
3437 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3438 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK
3439
3440 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3441 intel_plane->wm.bytes_per_pixel =
3442 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3443 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3444 intel_plane->wm.y_bytes_per_pixel =
3445 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3446 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3447
0fda6568
TU
3448 /*
3449 * Framebuffer can be NULL on plane disable, but it does not
3450 * matter for watermarks if we assume no tiling in that case.
3451 */
3452 if (fb)
3453 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3454 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB
3455
3456 skl_update_wm(crtc);
3457}
3458
820c1980 3459static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3460{
7c4a395f 3461 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3462 struct drm_device *dev = crtc->dev;
801bcfff 3463 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID
3464 struct ilk_wm_maximums max;
3465 struct ilk_pipe_wm_parameters params = {};
3466 struct ilk_wm_values results = {};
77c122bc 3467 enum intel_ddb_partitioning partitioning;
7c4a395f 3468 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3469 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3470 struct intel_wm_config config = {};
7c4a395f 3471
2a44b76b 3472 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS
3473
3474 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3475
3476 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3477 return;
861f3389 3478
7c4a395f 3479 intel_crtc->wm.active = pipe_wm;
861f3389 3480
2a44b76b
VS
3481 ilk_compute_wm_config(dev, &config);
3482
34982fe1 3483 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3484 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS
3485
3486 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS
3487 if (INTEL_INFO(dev)->gen >= 7 &&
3488 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3489 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3490 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3491
820c1980 3492 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3493 } else {
198a1e9b 3494 best_lp_wm = &lp_wm_1_2;
861f3389
PZ
3495 }
3496
198a1e9b 3497 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3498 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3499
820c1980 3500 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3501
820c1980 3502 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ
3503}
3504
ed57cb8a
DL
3505static void
3506ilk_update_sprite_wm(struct drm_plane *plane,
3507 struct drm_crtc *crtc,
3508 uint32_t sprite_width, uint32_t sprite_height,
3509 int pixel_size, bool enabled, bool scaled)
526682e9 3510{
8553c18e 3511 struct drm_device *dev = plane->dev;
adf3d35e 3512 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3513
adf3d35e
VS
3514 intel_plane->wm.enabled = enabled;
3515 intel_plane->wm.scaled = scaled;
3516 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3517 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3518 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3519
8553c18e
VS
3520 /*
3521 * IVB workaround: must disable low power watermarks for at least
3522 * one frame before enabling scaling. LP watermarks can be re-enabled
3523 * when scaling is disabled.
3524 *
3525 * WaCxSRDisabledForSpriteScaling:ivb
3526 */
3527 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3528 intel_wait_for_vblank(dev, intel_plane->pipe);
3529
820c1980 3530 ilk_update_wm(crtc);
526682e9
PZ
3531}
3532
3078999f
PB
3533static void skl_pipe_wm_active_state(uint32_t val,
3534 struct skl_pipe_wm *active,
3535 bool is_transwm,
3536 bool is_cursor,
3537 int i,
3538 int level)
3539{
3540 bool is_enabled = (val & PLANE_WM_EN) != 0;
3541
3542 if (!is_transwm) {
3543 if (!is_cursor) {
3544 active->wm[level].plane_en[i] = is_enabled;
3545 active->wm[level].plane_res_b[i] =
3546 val & PLANE_WM_BLOCKS_MASK;
3547 active->wm[level].plane_res_l[i] =
3548 (val >> PLANE_WM_LINES_SHIFT) &
3549 PLANE_WM_LINES_MASK;
3550 } else {
3551 active->wm[level].cursor_en = is_enabled;
3552 active->wm[level].cursor_res_b =
3553 val & PLANE_WM_BLOCKS_MASK;
3554 active->wm[level].cursor_res_l =
3555 (val >> PLANE_WM_LINES_SHIFT) &
3556 PLANE_WM_LINES_MASK;
3557 }
3558 } else {
3559 if (!is_cursor) {
3560 active->trans_wm.plane_en[i] = is_enabled;
3561 active->trans_wm.plane_res_b[i] =
3562 val & PLANE_WM_BLOCKS_MASK;
3563 active->trans_wm.plane_res_l[i] =
3564 (val >> PLANE_WM_LINES_SHIFT) &
3565 PLANE_WM_LINES_MASK;
3566 } else {
3567 active->trans_wm.cursor_en = is_enabled;
3568 active->trans_wm.cursor_res_b =
3569 val & PLANE_WM_BLOCKS_MASK;
3570 active->trans_wm.cursor_res_l =
3571 (val >> PLANE_WM_LINES_SHIFT) &
3572 PLANE_WM_LINES_MASK;
3573 }
3574 }
3575}
3576
3577static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3578{
3579 struct drm_device *dev = crtc->dev;
3580 struct drm_i915_private *dev_priv = dev->dev_private;
3581 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3582 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3583 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3584 enum pipe pipe = intel_crtc->pipe;
3585 int level, i, max_level;
3586 uint32_t temp;
3587
3588 max_level = ilk_wm_max_level(dev);
3589
3590 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3591
3592 for (level = 0; level <= max_level; level++) {
3593 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3594 hw->plane[pipe][i][level] =
3595 I915_READ(PLANE_WM(pipe, i, level));
3596 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3597 }
3598
3599 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3600 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3601 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3602
3ef00284 3603 if (!intel_crtc->active)
3078999f
PB
3604 return;
3605
3606 hw->dirty[pipe] = true;
3607
3608 active->linetime = hw->wm_linetime[pipe];
3609
3610 for (level = 0; level <= max_level; level++) {
3611 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3612 temp = hw->plane[pipe][i][level];
3613 skl_pipe_wm_active_state(temp, active, false,
3614 false, i, level);
3615 }
3616 temp = hw->cursor[pipe][level];
3617 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3618 }
3619
3620 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3621 temp = hw->plane_trans[pipe][i];
3622 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3623 }
3624
3625 temp = hw->cursor_trans[pipe];
3626 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3627}
3628
3629void skl_wm_get_hw_state(struct drm_device *dev)
3630{
a269c583
DL
3631 struct drm_i915_private *dev_priv = dev->dev_private;
3632 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB
3633 struct drm_crtc *crtc;
3634
a269c583 3635 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB
3636 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3637 skl_pipe_wm_get_hw_state(crtc);
3638}
3639
243e6a44
VS
3640static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3641{
3642 struct drm_device *dev = crtc->dev;
3643 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3644 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS
3645 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3646 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3647 enum pipe pipe = intel_crtc->pipe;
3648 static const unsigned int wm0_pipe_reg[] = {
3649 [PIPE_A] = WM0_PIPEA_ILK,
3650 [PIPE_B] = WM0_PIPEB_ILK,
3651 [PIPE_C] = WM0_PIPEC_IVB,
3652 };
3653
3654 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3655 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3656 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3657
3ef00284 3658 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS
3659
3660 if (active->pipe_enabled) {
243e6a44
VS
3661 u32 tmp = hw->wm_pipe[pipe];
3662
3663 /*
3664 * For active pipes LP0 watermark is marked as
3665 * enabled, and LP1+ watermaks as disabled since
3666 * we can't really reverse compute them in case
3667 * multiple pipes are active.
3668 */
3669 active->wm[0].enable = true;
3670 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3671 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3672 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3673 active->linetime = hw->wm_linetime[pipe];
3674 } else {
3675 int level, max_level = ilk_wm_max_level(dev);
3676
3677 /*
3678 * For inactive pipes, all watermark levels
3679 * should be marked as enabled but zeroed,
3680 * which is what we'd compute them to.
3681 */
3682 for (level = 0; level <= max_level; level++)
3683 active->wm[level].enable = true;
3684 }
3685}
3686
3687void ilk_wm_get_hw_state(struct drm_device *dev)
3688{
3689 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3690 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS
3691 struct drm_crtc *crtc;
3692
70e1e0ec 3693 for_each_crtc(dev, crtc)
243e6a44
VS
3694 ilk_pipe_wm_get_hw_state(crtc);
3695
3696 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3697 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3698 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3699
3700 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS
3701 if (INTEL_INFO(dev)->gen >= 7) {
3702 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3703 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3704 }
243e6a44 3705
a42a5719 3706 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS
3707 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3708 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3709 else if (IS_IVYBRIDGE(dev))
3710 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3711 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS
3712
3713 hw->enable_fbc_wm =
3714 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3715}
3716
b445e3b0
ED
3717/**
3718 * intel_update_watermarks - update FIFO watermark values based on current modes
3719 *
3720 * Calculate watermark values for the various WM regs based on current mode
3721 * and plane configuration.
3722 *
3723 * There are several cases to deal with here:
3724 * - normal (i.e. non-self-refresh)
3725 * - self-refresh (SR) mode
3726 * - lines are large relative to FIFO size (buffer can hold up to 2)
3727 * - lines are small relative to FIFO size (buffer can hold more than 2
3728 * lines), so need to account for TLB latency
3729 *
3730 * The normal calculation is:
3731 * watermark = dotclock * bytes per pixel * latency
3732 * where latency is platform & configuration dependent (we assume pessimal
3733 * values here).
3734 *
3735 * The SR calculation is:
3736 * watermark = (trunc(latency/line time)+1) * surface width *
3737 * bytes per pixel
3738 * where
3739 * line time = htotal / dotclock
3740 * surface width = hdisplay for normal plane and 64 for cursor
3741 * and latency is assumed to be high, as above.
3742 *
3743 * The final value programmed to the register should always be rounded up,
3744 * and include an extra 2 entries to account for clock crossings.
3745 *
3746 * We don't use the sprite, so we can ignore that. And on Crestline we have
3747 * to set the non-SR watermarks to 8.
3748 */
46ba614c 3749void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3750{
46ba614c 3751 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED
3752
3753 if (dev_priv->display.update_wm)
46ba614c 3754 dev_priv->display.update_wm(crtc);
b445e3b0
ED
3755}
3756
adf3d35e
VS
3757void intel_update_sprite_watermarks(struct drm_plane *plane,
3758 struct drm_crtc *crtc,
ed57cb8a
DL
3759 uint32_t sprite_width,
3760 uint32_t sprite_height,
3761 int pixel_size,
39db4a4d 3762 bool enabled, bool scaled)
b445e3b0 3763{
adf3d35e 3764 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED
3765
3766 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL
3767 dev_priv->display.update_sprite_wm(plane, crtc,
3768 sprite_width, sprite_height,
39db4a4d 3769 pixel_size, enabled, scaled);
b445e3b0
ED
3770}
3771
9270388e
DV
3772/**
3773 * Lock protecting IPS related data structures
9270388e
DV
3774 */
3775DEFINE_SPINLOCK(mchdev_lock);
3776
3777/* Global for IPS driver to get at the current i915 device. Protected by
3778 * mchdev_lock. */
3779static struct drm_i915_private *i915_mch_dev;
3780
2b4e57bd
ED
3781bool ironlake_set_drps(struct drm_device *dev, u8 val)
3782{
3783 struct drm_i915_private *dev_priv = dev->dev_private;
3784 u16 rgvswctl;
3785
9270388e
DV
3786 assert_spin_locked(&mchdev_lock);
3787
2b4e57bd
ED
3788 rgvswctl = I915_READ16(MEMSWCTL);
3789 if (rgvswctl & MEMCTL_CMD_STS) {
3790 DRM_DEBUG("gpu busy, RCS change rejected\n");
3791 return false; /* still busy with another command */
3792 }
3793
3794 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3795 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3796 I915_WRITE16(MEMSWCTL, rgvswctl);
3797 POSTING_READ16(MEMSWCTL);
3798
3799 rgvswctl |= MEMCTL_CMD_STS;
3800 I915_WRITE16(MEMSWCTL, rgvswctl);
3801
3802 return true;
3803}
3804
8090c6b9 3805static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED
3806{
3807 struct drm_i915_private *dev_priv = dev->dev_private;
3808 u32 rgvmodectl = I915_READ(MEMMODECTL);
3809 u8 fmax, fmin, fstart, vstart;
3810
9270388e
DV
3811 spin_lock_irq(&mchdev_lock);
3812
2b4e57bd
ED
3813 /* Enable temp reporting */
3814 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3815 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3816
3817 /* 100ms RC evaluation intervals */
3818 I915_WRITE(RCUPEI, 100000);
3819 I915_WRITE(RCDNEI, 100000);
3820
3821 /* Set max/min thresholds to 90ms and 80ms respectively */
3822 I915_WRITE(RCBMAXAVG, 90000);
3823 I915_WRITE(RCBMINAVG, 80000);
3824
3825 I915_WRITE(MEMIHYST, 1);
3826
3827 /* Set up min, max, and cur for interrupt handling */
3828 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3829 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3830 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3831 MEMMODE_FSTART_SHIFT;
3832
3833 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3834 PXVFREQ_PX_SHIFT;
3835
20e4d407
DV
3836 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3837 dev_priv->ips.fstart = fstart;
2b4e57bd 3838
20e4d407
DV
3839 dev_priv->ips.max_delay = fstart;
3840 dev_priv->ips.min_delay = fmin;
3841 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED
3842
3843 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3844 fmax, fmin, fstart);
3845
3846 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3847
3848 /*
3849 * Interrupts will be enabled in ironlake_irq_postinstall
3850 */
3851
3852 I915_WRITE(VIDSTART, vstart);
3853 POSTING_READ(VIDSTART);
3854
3855 rgvmodectl |= MEMMODE_SWMODE_EN;
3856 I915_WRITE(MEMMODECTL, rgvmodectl);
3857
9270388e 3858 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3859 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3860 mdelay(1);
2b4e57bd
ED
3861
3862 ironlake_set_drps(dev, fstart);
3863
20e4d407 3864 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3865 I915_READ(0x112e0);
20e4d407
DV
3866 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3867 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 3868 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV
3869
3870 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED
3871}
3872
8090c6b9 3873static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED
3874{
3875 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV
3876 u16 rgvswctl;
3877
3878 spin_lock_irq(&mchdev_lock);
3879
3880 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED
3881
3882 /* Ack interrupts, disable EFC interrupt */
3883 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3884 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3885 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3886 I915_WRITE(DEIIR, DE_PCU_EVENT);
3887 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3888
3889 /* Go back to the starting frequency */
20e4d407 3890 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3891 mdelay(1);
2b4e57bd
ED
3892 rgvswctl |= MEMCTL_CMD_STS;
3893 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3894 mdelay(1);
2b4e57bd 3895
9270388e 3896 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED
3897}
3898
acbe9475
DV
3899/* There's a funny hw issue where the hw returns all 0 when reading from
3900 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3901 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3902 * all limits and the gpu stuck at whatever frequency it is at atm).
3903 */
74ef1173 3904static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 3905{
7b9e0ae6 3906 u32 limits;
2b4e57bd 3907
20b46e59
DV
3908 /* Only set the down limit when we've reached the lowest level to avoid
3909 * getting more interrupts, otherwise leave this clear. This prevents a
3910 * race in the hw when coming out of rc6: There's a tiny window where
3911 * the hw runs at the minimal clock before selecting the desired
3912 * frequency, if the down threshold expires in that window we will not
3913 * receive a down interrupt. */
74ef1173
AG
3914 if (IS_GEN9(dev_priv->dev)) {
3915 limits = (dev_priv->rps.max_freq_softlimit) << 23;
3916 if (val <= dev_priv->rps.min_freq_softlimit)
3917 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
3918 } else {
3919 limits = dev_priv->rps.max_freq_softlimit << 24;
3920 if (val <= dev_priv->rps.min_freq_softlimit)
3921 limits |= dev_priv->rps.min_freq_softlimit << 16;
3922 }
20b46e59
DV
3923
3924 return limits;
3925}
3926
dd75fdc8
CW
3927static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
3928{
3929 int new_power;
8a586437
AG
3930 u32 threshold_up = 0, threshold_down = 0; /* in % */
3931 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW
3932
3933 new_power = dev_priv->rps.power;
3934 switch (dev_priv->rps.power) {
3935 case LOW_POWER:
b39fb297 3936 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW
3937 new_power = BETWEEN;
3938 break;
3939
3940 case BETWEEN:
b39fb297 3941 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 3942 new_power = LOW_POWER;
b39fb297 3943 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW
3944 new_power = HIGH_POWER;
3945 break;
3946
3947 case HIGH_POWER:
b39fb297 3948 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW
3949 new_power = BETWEEN;
3950 break;
3951 }
3952 /* Max/min bins are special */
aed242ff 3953 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 3954 new_power = LOW_POWER;
aed242ff 3955 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW
3956 new_power = HIGH_POWER;
3957 if (new_power == dev_priv->rps.power)
3958 return;
3959
3960 /* Note the units here are not exactly 1us, but 1280ns. */
3961 switch (new_power) {
3962 case LOW_POWER:
3963 /* Upclock if more than 95% busy over 16ms */
8a586437
AG
3964 ei_up = 16000;
3965 threshold_up = 95;
dd75fdc8
CW
3966
3967 /* Downclock if less than 85% busy over 32ms */
8a586437
AG
3968 ei_down = 32000;
3969 threshold_down = 85;
dd75fdc8
CW
3970 break;
3971
3972 case BETWEEN:
3973 /* Upclock if more than 90% busy over 13ms */
8a586437
AG
3974 ei_up = 13000;
3975 threshold_up = 90;
dd75fdc8
CW
3976
3977 /* Downclock if less than 75% busy over 32ms */
8a586437
AG
3978 ei_down = 32000;
3979 threshold_down = 75;
dd75fdc8
CW
3980 break;
3981
3982 case HIGH_POWER:
3983 /* Upclock if more than 85% busy over 10ms */
8a586437
AG
3984 ei_up = 10000;
3985 threshold_up = 85;
dd75fdc8
CW
3986
3987 /* Downclock if less than 60% busy over 32ms */
8a586437
AG
3988 ei_down = 32000;
3989 threshold_down = 60;
dd75fdc8
CW
3990 break;
3991 }
3992
8a586437
AG
3993 I915_WRITE(GEN6_RP_UP_EI,
3994 GT_INTERVAL_FROM_US(dev_priv, ei_up));
3995 I915_WRITE(GEN6_RP_UP_THRESHOLD,
3996 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
3997
3998 I915_WRITE(GEN6_RP_DOWN_EI,
3999 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4000 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4001 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4002
4003 I915_WRITE(GEN6_RP_CONTROL,
4004 GEN6_RP_MEDIA_TURBO |
4005 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4006 GEN6_RP_MEDIA_IS_GFX |
4007 GEN6_RP_ENABLE |
4008 GEN6_RP_UP_BUSY_AVG |
4009 GEN6_RP_DOWN_IDLE_AVG);
4010
dd75fdc8 4011 dev_priv->rps.power = new_power;
8fb55197
CW
4012 dev_priv->rps.up_threshold = threshold_up;
4013 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW
4014 dev_priv->rps.last_adj = 0;
4015}
4016
2876ce73
CW
4017static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4018{
4019 u32 mask = 0;
4020
4021 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4022 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4023 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4024 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4025
7b3c29f6
CW
4026 mask &= dev_priv->pm_rps_events;
4027
59d02a1f 4028 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW
4029}
4030
b8a5ff8d
JM
4031/* gen6_set_rps is called to update the frequency request, but should also be
4032 * called when the range (min_delay and max_delay) is modified so that we can
4033 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4034static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV
4035{
4036 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4037
4fc688ce 4038 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW
4039 WARN_ON(val > dev_priv->rps.max_freq);
4040 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4041
eb64cad1
CW
4042 /* min/max delay may still have been modified so be sure to
4043 * write the limits value.
4044 */
4045 if (val != dev_priv->rps.cur_freq) {
4046 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4047
5704195c
AG
4048 if (IS_GEN9(dev))
4049 I915_WRITE(GEN6_RPNSWREQ,
4050 GEN9_FREQUENCY(val));
4051 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW
4052 I915_WRITE(GEN6_RPNSWREQ,
4053 HSW_FREQUENCY(val));
4054 else
4055 I915_WRITE(GEN6_RPNSWREQ,
4056 GEN6_FREQUENCY(val) |
4057 GEN6_OFFSET(0) |
4058 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4059 }
7b9e0ae6 4060
7b9e0ae6
CW
4061 /* Make sure we continue to get interrupts
4062 * until we hit the minimum or maximum frequencies.
4063 */
74ef1173 4064 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4065 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4066
d5570a72
BW
4067 POSTING_READ(GEN6_RPNSWREQ);
4068
b39fb297 4069 dev_priv->rps.cur_freq = val;
be2cde9a 4070 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED
4071}
4072
ffe02b40
VS
4073static void valleyview_set_rps(struct drm_device *dev, u8 val)
4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076
4077 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW
4078 WARN_ON(val > dev_priv->rps.max_freq);
4079 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS
4080
4081 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4082 "Odd GPU freq value\n"))
4083 val &= ~1;
4084
8fb55197 4085 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4086 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW
4087 if (!IS_CHERRYVIEW(dev_priv))
4088 gen6_set_rps_thresholds(dev_priv, val);
4089 }
ffe02b40
VS
4090
4091 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4092
4093 dev_priv->rps.cur_freq = val;
4094 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4095}
4096
a7f6e231 4097/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D
4098 *
4099 * * If Gfx is Idle, then
a7f6e231
D
4100 * 1. Forcewake Media well.
4101 * 2. Request idle freq.
4102 * 3. Release Forcewake of Media well.
76c3552f
D
4103*/
4104static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4105{
aed242ff 4106 u32 val = dev_priv->rps.idle_freq;
5549d25f 4107
aed242ff 4108 if (dev_priv->rps.cur_freq <= val)
76c3552f
D
4109 return;
4110
a7f6e231
D
4111 /* Wake up the media well, as that takes a lot less
4112 * power than the Render well. */
4113 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4114 valleyview_set_rps(dev_priv->dev, val);
4115 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D
4116}
4117
43cf3bf0
CW
4118void gen6_rps_busy(struct drm_i915_private *dev_priv)
4119{
4120 mutex_lock(&dev_priv->rps.hw_lock);
4121 if (dev_priv->rps.enabled) {
4122 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4123 gen6_rps_reset_ei(dev_priv);
4124 I915_WRITE(GEN6_PMINTRMSK,
4125 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4126 }
4127 mutex_unlock(&dev_priv->rps.hw_lock);
4128}
4129
b29c19b6
CW
4130void gen6_rps_idle(struct drm_i915_private *dev_priv)
4131{
691bb717
DL
4132 struct drm_device *dev = dev_priv->dev;
4133
b29c19b6 4134 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4135 if (dev_priv->rps.enabled) {
21a11fff 4136 if (IS_VALLEYVIEW(dev))
76c3552f 4137 vlv_set_rps_idle(dev_priv);
7526ed79 4138 else
aed242ff 4139 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4140 dev_priv->rps.last_adj = 0;
43cf3bf0 4141 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4142 }
8d3afd7d 4143 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4144
8d3afd7d 4145 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW
4146 while (!list_empty(&dev_priv->rps.clients))
4147 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4148 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW
4149}
4150
1854d5ca 4151void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW
4152 struct intel_rps_client *rps,
4153 unsigned long submitted)
b29c19b6 4154{
8d3afd7d
CW
4155 /* This is intentionally racy! We peek at the state here, then
4156 * validate inside the RPS worker.
4157 */
4158 if (!(dev_priv->mm.busy &&
4159 dev_priv->rps.enabled &&
4160 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4161 return;
43cf3bf0 4162
e61b9958
CW
4163 /* Force a RPS boost (and don't count it against the client) if
4164 * the GPU is severely congested.
4165 */
d0bc54f2 4166 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW
4167 rps = NULL;
4168
8d3afd7d
CW
4169 spin_lock(&dev_priv->rps.client_lock);
4170 if (rps == NULL || list_empty(&rps->link)) {
4171 spin_lock_irq(&dev_priv->irq_lock);
4172 if (dev_priv->rps.interrupts_enabled) {
4173 dev_priv->rps.client_boost = true;
4174 queue_work(dev_priv->wq, &dev_priv->rps.work);
4175 }
4176 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4177
2e1b8730
CW
4178 if (rps != NULL) {
4179 list_add(&rps->link, &dev_priv->rps.clients);
4180 rps->boosts++;
1854d5ca
CW
4181 } else
4182 dev_priv->rps.boosts++;
c0951f0c 4183 }
8d3afd7d 4184 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW
4185}
4186
ffe02b40 4187void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4188{
ffe02b40
VS
4189 if (IS_VALLEYVIEW(dev))
4190 valleyview_set_rps(dev, val);
4191 else
4192 gen6_set_rps(dev, val);
0a073b84
JB
4193}
4194
20e49366
ZW
4195static void gen9_disable_rps(struct drm_device *dev)
4196{
4197 struct drm_i915_private *dev_priv = dev->dev_private;
4198
4199 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4200 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW
4201}
4202
44fc7d5c 4203static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB
4204{
4205 struct drm_i915_private *dev_priv = dev->dev_private;
4206
4207 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4208 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV
4209}
4210
38807746
D
4211static void cherryview_disable_rps(struct drm_device *dev)
4212{
4213 struct drm_i915_private *dev_priv = dev->dev_private;
4214
4215 I915_WRITE(GEN6_RC_CONTROL, 0);
4216}
4217
44fc7d5c
DV
4218static void valleyview_disable_rps(struct drm_device *dev)
4219{
4220 struct drm_i915_private *dev_priv = dev->dev_private;
4221
98a2e5f9
D
4222 /* we're doing forcewake before Disabling RC6,
4223 * This what the BIOS expects when going into suspend */
59bad947 4224 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4225
44fc7d5c 4226 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4227
59bad947 4228 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB
4229}
4230
dc39fff7
BW
4231static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4232{
91ca689a
ID
4233 if (IS_VALLEYVIEW(dev)) {
4234 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4235 mode = GEN6_RC_CTL_RC6_ENABLE;
4236 else
4237 mode = 0;
4238 }
58abf1da
RV
4239 if (HAS_RC6p(dev))
4240 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4241 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4242 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4243 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4244
4245 else
4246 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4247 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW
4248}
4249
e6069ca8 4250static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4251{
eb4926e4
DL
4252 /* No RC6 before Ironlake */
4253 if (INTEL_INFO(dev)->gen < 5)
4254 return 0;
4255
e6069ca8
ID
4256 /* RC6 is only on Ironlake mobile not on desktop */
4257 if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev))
4258 return 0;
4259
456470eb 4260 /* Respect the kernel parameter if it is set */
e6069ca8
ID
4261 if (enable_rc6 >= 0) {
4262 int mask;
4263
58abf1da 4264 if (HAS_RC6p(dev))
e6069ca8
ID
4265 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4266 INTEL_RC6pp_ENABLE;
4267 else
4268 mask = INTEL_RC6_ENABLE;
4269
4270 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV
4271 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4272 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID
4273
4274 return enable_rc6 & mask;
4275 }
2b4e57bd 4276
6567d748
CW
4277 /* Disable RC6 on Ironlake */
4278 if (INTEL_INFO(dev)->gen == 5)
4279 return 0;
2b4e57bd 4280
8bade1ad 4281 if (IS_IVYBRIDGE(dev))
cca84a1f 4282 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW
4283
4284 return INTEL_RC6_ENABLE;
2b4e57bd
ED
4285}
4286
e6069ca8
ID
4287int intel_enable_rc6(const struct drm_device *dev)
4288{
4289 return i915.enable_rc6;
4290}
4291
93ee2920 4292static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4293{
93ee2920
TR
4294 struct drm_i915_private *dev_priv = dev->dev_private;
4295 uint32_t rp_state_cap;
4296 u32 ddcc_status = 0;
4297 int ret;
4298
4299 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3280e8b0
BW
4300 /* All of these values are in units of 50MHz */
4301 dev_priv->rps.cur_freq = 0;
93ee2920 4302 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
3280e8b0 4303 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
93ee2920 4304 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
3280e8b0 4305 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
cee991cb
AG
4306 if (IS_SKYLAKE(dev)) {
4307 /* Store the frequency values in 16.66 MHZ units, which is
4308 the natural hardware unit for SKL */
4309 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4310 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4311 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4312 }
3280e8b0
BW
4313 /* hw_max = RP0 until we check for overclocking */
4314 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4315
93ee2920
TR
4316 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
4317 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
4318 ret = sandybridge_pcode_read(dev_priv,
4319 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4320 &ddcc_status);
4321 if (0 == ret)
4322 dev_priv->rps.efficient_freq =
46efa4ab
TR
4323 clamp_t(u8,
4324 ((ddcc_status >> 8) & 0xff),
4325 dev_priv->rps.min_freq,
4326 dev_priv->rps.max_freq);
93ee2920
TR
4327 }
4328
aed242ff
CW
4329 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4330
3280e8b0
BW
4331 /* Preserve min/max settings in case of re-init */
4332 if (dev_priv->rps.max_freq_softlimit == 0)
4333 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4334
93ee2920
TR
4335 if (dev_priv->rps.min_freq_softlimit == 0) {
4336 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4337 dev_priv->rps.min_freq_softlimit =
813b5e69
VS
4338 max_t(int, dev_priv->rps.efficient_freq,
4339 intel_freq_opcode(dev_priv, 450));
93ee2920
TR
4340 else
4341 dev_priv->rps.min_freq_softlimit =
4342 dev_priv->rps.min_freq;
4343 }
3280e8b0
BW
4344}
4345
b6fef0ef 4346/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4347static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB
4348{
4349 struct drm_i915_private *dev_priv = dev->dev_private;
4350
4351 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4352
ba1c554c
DL
4353 gen6_init_rps_frequencies(dev);
4354
0beb059a
AG
4355 /* Program defaults and thresholds for RPS*/
4356 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4357 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4358
4359 /* 1 second timeout*/
4360 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4361 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4362
b6fef0ef 4363 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4364
0beb059a
AG
4365 /* Leaning on the below call to gen6_set_rps to program/setup the
4366 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4367 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4368 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4369 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB
4370
4371 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4372}
4373
4374static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW
4375{
4376 struct drm_i915_private *dev_priv = dev->dev_private;
4377 struct intel_engine_cs *ring;
4378 uint32_t rc6_mask = 0;
4379 int unused;
4380
4381 /* 1a: Software RC state - RC0 */
4382 I915_WRITE(GEN6_RC_STATE, 0);
4383
4384 /* 1b: Get forcewake during program sequence. Although the driver
4385 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4386 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW
4387
4388 /* 2a: Disable RC states. */
4389 I915_WRITE(GEN6_RC_CONTROL, 0);
4390
4391 /* 2b: Program RC6 thresholds.*/
4392 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4393 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4394 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4395 for_each_ring(ring, dev_priv, unused)
4396 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4397 I915_WRITE(GEN6_RC_SLEEP, 0);
4398 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4399
38c23527
ZW
4400 /* 2c: Program Coarse Power Gating Policies. */
4401 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4402 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4403
20e49366
ZW
4404 /* 3a: Enable RC6 */
4405 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4406 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4407 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4408 "on" : "off");
4409 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4410 GEN6_RC_CTL_EI_MODE(1) |
4411 rc6_mask);
4412
cb07bae0
SK
4413 /*
4414 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4415 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4416 */
a4104c55 4417 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4418 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4419
38c23527 4420
59bad947 4421 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW
4422
4423}
4424
6edee7f3
BW
4425static void gen8_enable_rps(struct drm_device *dev)
4426{
4427 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4428 struct intel_engine_cs *ring;
93ee2920 4429 uint32_t rc6_mask = 0;
6edee7f3
BW
4430 int unused;
4431
4432 /* 1a: Software RC state - RC0 */
4433 I915_WRITE(GEN6_RC_STATE, 0);
4434
4435 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4436 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4437 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW
4438
4439 /* 2a: Disable RC states. */
4440 I915_WRITE(GEN6_RC_CONTROL, 0);
4441
93ee2920
TR
4442 /* Initialize rps frequencies */
4443 gen6_init_rps_frequencies(dev);
6edee7f3
BW
4444
4445 /* 2b: Program RC6 thresholds.*/
4446 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4447 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4448 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4449 for_each_ring(ring, dev_priv, unused)
4450 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4451 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR
4452 if (IS_BROADWELL(dev))
4453 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4454 else
4455 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW
4456
4457 /* 3: Enable RC6 */
4458 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4459 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4460 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR
4461 if (IS_BROADWELL(dev))
4462 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4463 GEN7_RC_CTL_TO_MODE |
4464 rc6_mask);
4465 else
4466 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4467 GEN6_RC_CTL_EI_MODE(1) |
4468 rc6_mask);
6edee7f3
BW
4469
4470 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW
4471 I915_WRITE(GEN6_RPNSWREQ,
4472 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4473 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4474 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV
4475 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4476 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4477
4478 /* Docs recommend 900MHz, and 300 MHz respectively */
4479 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4480 dev_priv->rps.max_freq_softlimit << 24 |
4481 dev_priv->rps.min_freq_softlimit << 16);
4482
4483 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4484 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4485 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4486 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4487
4488 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW
4489
4490 /* 5: Enable RPS */
7526ed79
DV
4491 I915_WRITE(GEN6_RP_CONTROL,
4492 GEN6_RP_MEDIA_TURBO |
4493 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4494 GEN6_RP_MEDIA_IS_GFX |
4495 GEN6_RP_ENABLE |
4496 GEN6_RP_UP_BUSY_AVG |
4497 GEN6_RP_DOWN_IDLE_AVG);
4498
4499 /* 6: Ring frequency + overclocking (our driver does this later */
4500
c7f3153a 4501 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4502 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4503
59bad947 4504 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW
4505}
4506
79f5b2c7 4507static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4508{
79f5b2c7 4509 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4510 struct intel_engine_cs *ring;
d060c169 4511 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4512 u32 gtfifodbg;
2b4e57bd 4513 int rc6_mode;
42c0526c 4514 int i, ret;
2b4e57bd 4515
4fc688ce 4516 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4517
2b4e57bd
ED
4518 /* Here begins a magic sequence of register writes to enable
4519 * auto-downclocking.
4520 *
4521 * Perhaps there might be some value in exposing these to
4522 * userspace...
4523 */
4524 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED
4525
4526 /* Clear the DBG now so we don't confuse earlier errors */
4527 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4528 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4529 I915_WRITE(GTFIFODBG, gtfifodbg);
4530 }
4531
59bad947 4532 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4533
93ee2920
TR
4534 /* Initialize rps frequencies */
4535 gen6_init_rps_frequencies(dev);
dd0a1aa1 4536
2b4e57bd
ED
4537 /* disable the counters and set deterministic thresholds */
4538 I915_WRITE(GEN6_RC_CONTROL, 0);
4539
4540 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4541 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4542 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4543 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4544 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4545
b4519513
CW
4546 for_each_ring(ring, dev_priv, i)
4547 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED
4548
4549 I915_WRITE(GEN6_RC_SLEEP, 0);
4550 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4551 if (IS_IVYBRIDGE(dev))
351aa566
SM
4552 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4553 else
4554 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4555 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED
4556 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4557
5a7dc92a 4558 /* Check if we are enabling RC6 */
2b4e57bd
ED
4559 rc6_mode = intel_enable_rc6(dev_priv->dev);
4560 if (rc6_mode & INTEL_RC6_ENABLE)
4561 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4562
5a7dc92a
ED
4563 /* We don't use those on Haswell */
4564 if (!IS_HASWELL(dev)) {
4565 if (rc6_mode & INTEL_RC6p_ENABLE)
4566 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4567
5a7dc92a
ED
4568 if (rc6_mode & INTEL_RC6pp_ENABLE)
4569 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4570 }
2b4e57bd 4571
dc39fff7 4572 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED
4573
4574 I915_WRITE(GEN6_RC_CONTROL,
4575 rc6_mask |
4576 GEN6_RC_CTL_EI_MODE(1) |
4577 GEN6_RC_CTL_HW_ENABLE);
4578
dd75fdc8
CW
4579 /* Power down if completely idle for over 50ms */
4580 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4581 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4582
42c0526c 4583 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4584 if (ret)
42c0526c 4585 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW
4586
4587 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4588 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4589 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4590 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4591 (pcu_mbox & 0xff) * 50);
b39fb297 4592 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED
4593 }
4594
dd75fdc8 4595 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4596 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4597
31643d54
BW
4598 rc6vids = 0;
4599 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4600 if (IS_GEN6(dev) && ret) {
4601 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4602 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4603 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4604 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4605 rc6vids &= 0xffff00;
4606 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4607 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4608 if (ret)
4609 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4610 }
4611
59bad947 4612 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED
4613}
4614
c2bc2fc5 4615static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4616{
79f5b2c7 4617 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4618 int min_freq = 15;
3ebecd07
CW
4619 unsigned int gpu_freq;
4620 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd 4621 int scaling_factor = 180;
eda79642 4622 struct cpufreq_policy *policy;
2b4e57bd 4623
4fc688ce 4624 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4625
eda79642
BW
4626 policy = cpufreq_cpu_get(0);
4627 if (policy) {
4628 max_ia_freq = policy->cpuinfo.max_freq;
4629 cpufreq_cpu_put(policy);
4630 } else {
4631 /*
4632 * Default to measured freq if none found, PCU will ensure we
4633 * don't go over
4634 */
2b4e57bd 4635 max_ia_freq = tsc_khz;
eda79642 4636 }
2b4e57bd
ED
4637
4638 /* Convert from kHz to MHz */
4639 max_ia_freq /= 1000;
4640
153b4b95 4641 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW
4642 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4643 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4644
2b4e57bd
ED
4645 /*
4646 * For each potential GPU frequency, load a ring frequency we'd like
4647 * to use for memory access. We do this by specifying the IA frequency
4648 * the PCU should use as a reference to determine the ring frequency.
4649 */
6985b352 4650 for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq;
2b4e57bd 4651 gpu_freq--) {
6985b352 4652 int diff = dev_priv->rps.max_freq - gpu_freq;
3ebecd07
CW
4653 unsigned int ia_freq = 0, ring_freq = 0;
4654
46c764d4
BW
4655 if (INTEL_INFO(dev)->gen >= 8) {
4656 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4657 ring_freq = max(min_ring_freq, gpu_freq);
4658 } else if (IS_HASWELL(dev)) {
f6aca45c 4659 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW
4660 ring_freq = max(min_ring_freq, ring_freq);
4661 /* leave ia_freq as the default, chosen by cpufreq */
4662 } else {
4663 /* On older processors, there is no separate ring
4664 * clock domain, so in order to boost the bandwidth
4665 * of the ring, we need to upclock the CPU (ia_freq).
4666 *
4667 * For GPU frequencies less than 750MHz,
4668 * just use the lowest ring freq.
4669 */
4670 if (gpu_freq < min_freq)
4671 ia_freq = 800;
4672 else
4673 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4674 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4675 }
2b4e57bd 4676
42c0526c
BW
4677 sandybridge_pcode_write(dev_priv,
4678 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW
4679 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4680 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4681 gpu_freq);
2b4e57bd 4682 }
2b4e57bd
ED
4683}
4684
c2bc2fc5
ID
4685void gen6_update_ring_freq(struct drm_device *dev)
4686{
4687 struct drm_i915_private *dev_priv = dev->dev_private;
4688
4689 if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev))
4690 return;
4691
4692 mutex_lock(&dev_priv->rps.hw_lock);
4693 __gen6_update_ring_freq(dev);
4694 mutex_unlock(&dev_priv->rps.hw_lock);
4695}
4696
03af2045 4697static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 4698{
095acd5f 4699 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D
4700 u32 val, rp0;
4701
095acd5f
D
4702 if (dev->pdev->revision >= 0x20) {
4703 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 4704
095acd5f
D
4705 switch (INTEL_INFO(dev)->eu_total) {
4706 case 8:
4707 /* (2 * 4) config */
4708 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
4709 break;
4710 case 12:
4711 /* (2 * 6) config */
4712 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
4713 break;
4714 case 16:
4715 /* (2 * 8) config */
4716 default:
4717 /* Setting (2 * 8) Min RP0 for any other combination */
4718 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
4719 break;
4720 }
4721 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
4722 } else {
4723 /* For pre-production hardware */
4724 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
4725 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4726 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
4727 }
2b6b3a09
D
4728 return rp0;
4729}
4730
4731static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4732{
4733 u32 val, rpe;
4734
4735 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
4736 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
4737
4738 return rpe;
4739}
4740
7707df4a
D
4741static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
4742{
095acd5f 4743 struct drm_device *dev = dev_priv->dev;
7707df4a
D
4744 u32 val, rp1;
4745
095acd5f
D
4746 if (dev->pdev->revision >= 0x20) {
4747 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
4748 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
4749 } else {
4750 /* For pre-production hardware */
4751 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4752 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
4753 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
4754 }
7707df4a
D
4755 return rp1;
4756}
4757
f8f2b001
D
4758static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
4759{
4760 u32 val, rp1;
4761
4762 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
4763
4764 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
4765
4766 return rp1;
4767}
4768
03af2045 4769static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB
4770{
4771 u32 val, rp0;
4772
64936258 4773 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB
4774
4775 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
4776 /* Clamp to max */
4777 rp0 = min_t(u32, rp0, 0xea);
4778
4779 return rp0;
4780}
4781
4782static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
4783{
4784 u32 val, rpe;
4785
64936258 4786 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 4787 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 4788 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB
4789 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
4790
4791 return rpe;
4792}
4793
03af2045 4794static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 4795{
64936258 4796 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB
4797}
4798
ae48434c
ID
4799/* Check that the pctx buffer wasn't move under us. */
4800static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
4801{
4802 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4803
4804 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
4805 dev_priv->vlv_pctx->stolen->start);
4806}
4807
38807746
D
4808
4809/* Check that the pcbr address is not empty. */
4810static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
4811{
4812 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
4813
4814 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
4815}
4816
4817static void cherryview_setup_pctx(struct drm_device *dev)
4818{
4819 struct drm_i915_private *dev_priv = dev->dev_private;
4820 unsigned long pctx_paddr, paddr;
4821 struct i915_gtt *gtt = &dev_priv->gtt;
4822 u32 pcbr;
4823 int pctx_size = 32*1024;
4824
4825 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4826
4827 pcbr = I915_READ(VLV_PCBR);
4828 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 4829 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D
4830 paddr = (dev_priv->mm.stolen_base +
4831 (gtt->stolen_size - pctx_size));
4832
4833 pctx_paddr = (paddr & (~4095));
4834 I915_WRITE(VLV_PCBR, pctx_paddr);
4835 }
ce611ef8
VS
4836
4837 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D
4838}
4839
c9cddffc
JB
4840static void valleyview_setup_pctx(struct drm_device *dev)
4841{
4842 struct drm_i915_private *dev_priv = dev->dev_private;
4843 struct drm_i915_gem_object *pctx;
4844 unsigned long pctx_paddr;
4845 u32 pcbr;
4846 int pctx_size = 24*1024;
4847
17b0c1f7
ID
4848 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
4849
c9cddffc
JB
4850 pcbr = I915_READ(VLV_PCBR);
4851 if (pcbr) {
4852 /* BIOS set it up already, grab the pre-alloc'd space */
4853 int pcbr_offset;
4854
4855 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
4856 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
4857 pcbr_offset,
190d6cd5 4858 I915_GTT_OFFSET_NONE,
c9cddffc
JB
4859 pctx_size);
4860 goto out;
4861 }
4862
ce611ef8
VS
4863 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
4864
c9cddffc
JB
4865 /*
4866 * From the Gunit register HAS:
4867 * The Gfx driver is expected to program this register and ensure
4868 * proper allocation within Gfx stolen memory. For example, this
4869 * register should be programmed such than the PCBR range does not
4870 * overlap with other ranges, such as the frame buffer, protected
4871 * memory, or any other relevant ranges.
4872 */
4873 pctx = i915_gem_object_create_stolen(dev, pctx_size);
4874 if (!pctx) {
4875 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
4876 return;
4877 }
4878
4879 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
4880 I915_WRITE(VLV_PCBR, pctx_paddr);
4881
4882out:
ce611ef8 4883 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB
4884 dev_priv->vlv_pctx = pctx;
4885}
4886
ae48434c
ID
4887static void valleyview_cleanup_pctx(struct drm_device *dev)
4888{
4889 struct drm_i915_private *dev_priv = dev->dev_private;
4890
4891 if (WARN_ON(!dev_priv->vlv_pctx))
4892 return;
4893
4894 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
4895 dev_priv->vlv_pctx = NULL;
4896}
4897
4e80519e
ID
4898static void valleyview_init_gt_powersave(struct drm_device *dev)
4899{
4900 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4901 u32 val;
4e80519e
ID
4902
4903 valleyview_setup_pctx(dev);
4904
4905 mutex_lock(&dev_priv->rps.hw_lock);
4906
2bb25c17
VS
4907 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
4908 switch ((val >> 6) & 3) {
4909 case 0:
4910 case 1:
4911 dev_priv->mem_freq = 800;
4912 break;
4913 case 2:
4914 dev_priv->mem_freq = 1066;
4915 break;
4916 case 3:
4917 dev_priv->mem_freq = 1333;
4918 break;
4919 }
80b83b62 4920 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4921
4e80519e
ID
4922 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
4923 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4924 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4925 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID
4926 dev_priv->rps.max_freq);
4927
4928 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
4929 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 4930 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID
4931 dev_priv->rps.efficient_freq);
4932
f8f2b001
D
4933 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
4934 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 4935 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D
4936 dev_priv->rps.rp1_freq);
4937
4e80519e
ID
4938 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
4939 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 4940 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID
4941 dev_priv->rps.min_freq);
4942
aed242ff
CW
4943 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4944
4e80519e
ID
4945 /* Preserve min/max settings in case of re-init */
4946 if (dev_priv->rps.max_freq_softlimit == 0)
4947 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4948
4949 if (dev_priv->rps.min_freq_softlimit == 0)
4950 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
4951
4952 mutex_unlock(&dev_priv->rps.hw_lock);
4953}
4954
38807746
D
4955static void cherryview_init_gt_powersave(struct drm_device *dev)
4956{
2b6b3a09 4957 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 4958 u32 val;
2b6b3a09 4959
38807746 4960 cherryview_setup_pctx(dev);
2b6b3a09
D
4961
4962 mutex_lock(&dev_priv->rps.hw_lock);
4963
a580516d 4964 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 4965 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 4966 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 4967
2bb25c17
VS
4968 switch ((val >> 2) & 0x7) {
4969 case 0:
4970 case 1:
4971 dev_priv->rps.cz_freq = 200;
4972 dev_priv->mem_freq = 1600;
4973 break;
4974 case 2:
4975 dev_priv->rps.cz_freq = 267;
4976 dev_priv->mem_freq = 1600;
4977 break;
4978 case 3:
4979 dev_priv->rps.cz_freq = 333;
4980 dev_priv->mem_freq = 2000;
4981 break;
4982 case 4:
4983 dev_priv->rps.cz_freq = 320;
4984 dev_priv->mem_freq = 1600;
4985 break;
4986 case 5:
4987 dev_priv->rps.cz_freq = 400;
4988 dev_priv->mem_freq = 1600;
4989 break;
4990 }
80b83b62 4991 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 4992
2b6b3a09
D
4993 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
4994 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
4995 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 4996 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D
4997 dev_priv->rps.max_freq);
4998
4999 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5000 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5001 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D
5002 dev_priv->rps.efficient_freq);
5003
7707df4a
D
5004 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5005 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5006 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D
5007 dev_priv->rps.rp1_freq);
5008
5b7c91b7
D
5009 /* PUnit validated range is only [RPe, RP0] */
5010 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5011 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5012 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D
5013 dev_priv->rps.min_freq);
5014
1c14762d
VS
5015 WARN_ONCE((dev_priv->rps.max_freq |
5016 dev_priv->rps.efficient_freq |
5017 dev_priv->rps.rp1_freq |
5018 dev_priv->rps.min_freq) & 1,
5019 "Odd GPU freq values\n");
5020
aed242ff
CW
5021 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5022
2b6b3a09
D
5023 /* Preserve min/max settings in case of re-init */
5024 if (dev_priv->rps.max_freq_softlimit == 0)
5025 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5026
5027 if (dev_priv->rps.min_freq_softlimit == 0)
5028 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5029
5030 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D
5031}
5032
4e80519e
ID
5033static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5034{
5035 valleyview_cleanup_pctx(dev);
5036}
5037
38807746
D
5038static void cherryview_enable_rps(struct drm_device *dev)
5039{
5040 struct drm_i915_private *dev_priv = dev->dev_private;
5041 struct intel_engine_cs *ring;
2b6b3a09 5042 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D
5043 int i;
5044
5045 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5046
5047 gtfifodbg = I915_READ(GTFIFODBG);
5048 if (gtfifodbg) {
5049 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5050 gtfifodbg);
5051 I915_WRITE(GTFIFODBG, gtfifodbg);
5052 }
5053
5054 cherryview_check_pctx(dev_priv);
5055
5056 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5057 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5058 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5059
160614a2
VS
5060 /* Disable RC states. */
5061 I915_WRITE(GEN6_RC_CONTROL, 0);
5062
38807746
D
5063 /* 2a: Program RC6 thresholds.*/
5064 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5065 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5066 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5067
5068 for_each_ring(ring, dev_priv, i)
5069 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5070 I915_WRITE(GEN6_RC_SLEEP, 0);
5071
f4f71c7d
D
5072 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5073 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D
5074
5075 /* allows RC6 residency counter to work */
5076 I915_WRITE(VLV_COUNTER_CONTROL,
5077 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5078 VLV_MEDIA_RC6_COUNT_EN |
5079 VLV_RENDER_RC6_COUNT_EN));
5080
5081 /* For now we assume BIOS is allocating and populating the PCBR */
5082 pcbr = I915_READ(VLV_PCBR);
5083
38807746
D
5084 /* 3: Enable RC6 */
5085 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5086 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5087 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D
5088
5089 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5090
2b6b3a09 5091 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5092 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D
5093 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5094 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5095 I915_WRITE(GEN6_RP_UP_EI, 66000);
5096 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5097
5098 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5099
5100 /* 5: Enable RPS */
5101 I915_WRITE(GEN6_RP_CONTROL,
5102 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5103 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D
5104 GEN6_RP_ENABLE |
5105 GEN6_RP_UP_BUSY_AVG |
5106 GEN6_RP_DOWN_IDLE_AVG);
5107
3ef62342
D
5108 /* Setting Fixed Bias */
5109 val = VLV_OVERRIDE_EN |
5110 VLV_SOC_TDP_EN |
5111 CHV_BIAS_CPU_50_SOC_50;
5112 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5113
2b6b3a09
D
5114 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5115
8d40c3ae
VS
5116 /* RPS code assumes GPLL is used */
5117 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5118
c8e9627d 5119 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D
5120 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5121
5122 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5123 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5124 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D
5125 dev_priv->rps.cur_freq);
5126
5127 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5128 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D
5129 dev_priv->rps.efficient_freq);
5130
5131 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5132
59bad947 5133 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D
5134}
5135
0a073b84
JB
5136static void valleyview_enable_rps(struct drm_device *dev)
5137{
5138 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5139 struct intel_engine_cs *ring;
2a5913a8 5140 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB
5141 int i;
5142
5143 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5144
ae48434c
ID
5145 valleyview_check_pctx(dev_priv);
5146
0a073b84 5147 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB
5148 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5149 gtfifodbg);
0a073b84
JB
5150 I915_WRITE(GTFIFODBG, gtfifodbg);
5151 }
5152
c8d9a590 5153 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5154 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5155
160614a2
VS
5156 /* Disable RC states. */
5157 I915_WRITE(GEN6_RC_CONTROL, 0);
5158
cad725fe 5159 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB
5160 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5161 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5162 I915_WRITE(GEN6_RP_UP_EI, 66000);
5163 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5164
5165 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5166
5167 I915_WRITE(GEN6_RP_CONTROL,
5168 GEN6_RP_MEDIA_TURBO |
5169 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5170 GEN6_RP_MEDIA_IS_GFX |
5171 GEN6_RP_ENABLE |
5172 GEN6_RP_UP_BUSY_AVG |
5173 GEN6_RP_DOWN_IDLE_CONT);
5174
5175 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5176 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5177 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5178
5179 for_each_ring(ring, dev_priv, i)
5180 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5181
2f0aa304 5182 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB
5183
5184 /* allows RC6 residency counter to work */
49798eb2 5185 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D
5186 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5187 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB
5188 VLV_MEDIA_RC6_COUNT_EN |
5189 VLV_RENDER_RC6_COUNT_EN));
31685c25 5190
a2b23fe0 5191 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5192 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW
5193
5194 intel_print_rc6_info(dev, rc6_mode);
5195
a2b23fe0 5196 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5197
3ef62342
D
5198 /* Setting Fixed Bias */
5199 val = VLV_OVERRIDE_EN |
5200 VLV_SOC_TDP_EN |
5201 VLV_BIAS_CPU_125_SOC_875;
5202 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5203
64936258 5204 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5205
8d40c3ae
VS
5206 /* RPS code assumes GPLL is used */
5207 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5208
c8e9627d 5209 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB
5210 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5211
b39fb297 5212 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5213 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5214 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5215 dev_priv->rps.cur_freq);
0a073b84 5216
73008b98 5217 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5218 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5219 dev_priv->rps.efficient_freq);
0a073b84 5220
b39fb297 5221 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5222
59bad947 5223 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB
5224}
5225
dde18883
ED
5226static unsigned long intel_pxfreq(u32 vidfreq)
5227{
5228 unsigned long freq;
5229 int div = (vidfreq & 0x3f0000) >> 16;
5230 int post = (vidfreq & 0x3000) >> 12;
5231 int pre = (vidfreq & 0x7);
5232
5233 if (!pre)
5234 return 0;
5235
5236 freq = ((div * 133333) / ((1<<post) * pre));
5237
5238 return freq;
5239}
5240
eb48eb00
DV
5241static const struct cparams {
5242 u16 i;
5243 u16 t;
5244 u16 m;
5245 u16 c;
5246} cparams[] = {
5247 { 1, 1333, 301, 28664 },
5248 { 1, 1066, 294, 24460 },
5249 { 1, 800, 294, 25192 },
5250 { 0, 1333, 276, 27605 },
5251 { 0, 1066, 276, 27605 },
5252 { 0, 800, 231, 23784 },
5253};
5254
f531dcb2 5255static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV
5256{
5257 u64 total_count, diff, ret;
5258 u32 count1, count2, count3, m = 0, c = 0;
5259 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5260 int i;
5261
02d71956
DV
5262 assert_spin_locked(&mchdev_lock);
5263
20e4d407 5264 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV
5265
5266 /* Prevent division-by-zero if we are asking too fast.
5267 * Also, we don't get interesting results if we are polling
5268 * faster than once in 10ms, so just return the saved value
5269 * in such cases.
5270 */
5271 if (diff1 <= 10)
20e4d407 5272 return dev_priv->ips.chipset_power;
eb48eb00
DV
5273
5274 count1 = I915_READ(DMIEC);
5275 count2 = I915_READ(DDREC);
5276 count3 = I915_READ(CSIEC);
5277
5278 total_count = count1 + count2 + count3;
5279
5280 /* FIXME: handle per-counter overflow */
20e4d407
DV
5281 if (total_count < dev_priv->ips.last_count1) {
5282 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV
5283 diff += total_count;
5284 } else {
20e4d407 5285 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV
5286 }
5287
5288 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV
5289 if (cparams[i].i == dev_priv->ips.c_m &&
5290 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV
5291 m = cparams[i].m;
5292 c = cparams[i].c;
5293 break;
5294 }
5295 }
5296
5297 diff = div_u64(diff, diff1);
5298 ret = ((m * diff) + c);
5299 ret = div_u64(ret, 10);
5300
20e4d407
DV
5301 dev_priv->ips.last_count1 = total_count;
5302 dev_priv->ips.last_time1 = now;
eb48eb00 5303
20e4d407 5304 dev_priv->ips.chipset_power = ret;
eb48eb00
DV
5305
5306 return ret;
5307}
5308
f531dcb2
CW
5309unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5310{
3d13ef2e 5311 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW
5312 unsigned long val;
5313
3d13ef2e 5314 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW
5315 return 0;
5316
5317 spin_lock_irq(&mchdev_lock);
5318
5319 val = __i915_chipset_val(dev_priv);
5320
5321 spin_unlock_irq(&mchdev_lock);
5322
5323 return val;
5324}
5325
eb48eb00
DV
5326unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5327{
5328 unsigned long m, x, b;
5329 u32 tsfs;
5330
5331 tsfs = I915_READ(TSFS);
5332
5333 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5334 x = I915_READ8(TR1);
5335
5336 b = tsfs & TSFS_INTR_MASK;
5337
5338 return ((m * x) / 127) - b;
5339}
5340
d972d6ee
MK
5341static int _pxvid_to_vd(u8 pxvid)
5342{
5343 if (pxvid == 0)
5344 return 0;
5345
5346 if (pxvid >= 8 && pxvid < 31)
5347 pxvid = 31;
5348
5349 return (pxvid + 2) * 125;
5350}
5351
5352static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5353{
3d13ef2e 5354 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK
5355 const int vd = _pxvid_to_vd(pxvid);
5356 const int vm = vd - 1125;
5357
3d13ef2e 5358 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK
5359 return vm > 0 ? vm : 0;
5360
5361 return vd;
eb48eb00
DV
5362}
5363
02d71956 5364static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5365{
5ed0bdf2 5366 u64 now, diff, diffms;
eb48eb00
DV
5367 u32 count;
5368
02d71956 5369 assert_spin_locked(&mchdev_lock);
eb48eb00 5370
5ed0bdf2
TG
5371 now = ktime_get_raw_ns();
5372 diffms = now - dev_priv->ips.last_time2;
5373 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV
5374
5375 /* Don't divide by 0 */
eb48eb00
DV
5376 if (!diffms)
5377 return;
5378
5379 count = I915_READ(GFXEC);
5380
20e4d407
DV
5381 if (count < dev_priv->ips.last_count2) {
5382 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV
5383 diff += count;
5384 } else {
20e4d407 5385 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV
5386 }
5387
20e4d407
DV
5388 dev_priv->ips.last_count2 = count;
5389 dev_priv->ips.last_time2 = now;
eb48eb00
DV
5390
5391 /* More magic constants... */
5392 diff = diff * 1181;
5393 diff = div_u64(diff, diffms * 10);
20e4d407 5394 dev_priv->ips.gfx_power = diff;
eb48eb00
DV
5395}
5396
02d71956
DV
5397void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5398{
3d13ef2e
DL
5399 struct drm_device *dev = dev_priv->dev;
5400
5401 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV
5402 return;
5403
9270388e 5404 spin_lock_irq(&mchdev_lock);
02d71956
DV
5405
5406 __i915_update_gfx_val(dev_priv);
5407
9270388e 5408 spin_unlock_irq(&mchdev_lock);
02d71956
DV
5409}
5410
f531dcb2 5411static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV
5412{
5413 unsigned long t, corr, state1, corr2, state2;
5414 u32 pxvid, ext_v;
5415
02d71956
DV
5416 assert_spin_locked(&mchdev_lock);
5417
b39fb297 5418 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV
5419 pxvid = (pxvid >> 24) & 0x7f;
5420 ext_v = pvid_to_extvid(dev_priv, pxvid);
5421
5422 state1 = ext_v;
5423
5424 t = i915_mch_val(dev_priv);
5425
5426 /* Revel in the empirically derived constants */
5427
5428 /* Correction factor in 1/100000 units */
5429 if (t > 80)
5430 corr = ((t * 2349) + 135940);
5431 else if (t >= 50)
5432 corr = ((t * 964) + 29317);
5433 else /* < 50 */
5434 corr = ((t * 301) + 1004);
5435
5436 corr = corr * ((150142 * state1) / 10000 - 78642);
5437 corr /= 100000;
20e4d407 5438 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV
5439
5440 state2 = (corr2 * state1) / 10000;
5441 state2 /= 100; /* convert to mW */
5442
02d71956 5443 __i915_update_gfx_val(dev_priv);
eb48eb00 5444
20e4d407 5445 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV
5446}
5447
f531dcb2
CW
5448unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5449{
3d13ef2e 5450 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW
5451 unsigned long val;
5452
3d13ef2e 5453 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW
5454 return 0;
5455
5456 spin_lock_irq(&mchdev_lock);
5457
5458 val = __i915_gfx_val(dev_priv);
5459
5460 spin_unlock_irq(&mchdev_lock);
5461
5462 return val;
5463}
5464
eb48eb00
DV
5465/**
5466 * i915_read_mch_val - return value for IPS use
5467 *
5468 * Calculate and return a value for the IPS driver to use when deciding whether
5469 * we have thermal and power headroom to increase CPU or GPU power budget.
5470 */
5471unsigned long i915_read_mch_val(void)
5472{
5473 struct drm_i915_private *dev_priv;
5474 unsigned long chipset_val, graphics_val, ret = 0;
5475
9270388e 5476 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5477 if (!i915_mch_dev)
5478 goto out_unlock;
5479 dev_priv = i915_mch_dev;
5480
f531dcb2
CW
5481 chipset_val = __i915_chipset_val(dev_priv);
5482 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV
5483
5484 ret = chipset_val + graphics_val;
5485
5486out_unlock:
9270388e 5487 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5488
5489 return ret;
5490}
5491EXPORT_SYMBOL_GPL(i915_read_mch_val);
5492
5493/**
5494 * i915_gpu_raise - raise GPU frequency limit
5495 *
5496 * Raise the limit; IPS indicates we have thermal headroom.
5497 */
5498bool i915_gpu_raise(void)
5499{
5500 struct drm_i915_private *dev_priv;
5501 bool ret = true;
5502
9270388e 5503 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5504 if (!i915_mch_dev) {
5505 ret = false;
5506 goto out_unlock;
5507 }
5508 dev_priv = i915_mch_dev;
5509
20e4d407
DV
5510 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5511 dev_priv->ips.max_delay--;
eb48eb00
DV
5512
5513out_unlock:
9270388e 5514 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5515
5516 return ret;
5517}
5518EXPORT_SYMBOL_GPL(i915_gpu_raise);
5519
5520/**
5521 * i915_gpu_lower - lower GPU frequency limit
5522 *
5523 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5524 * frequency maximum.
5525 */
5526bool i915_gpu_lower(void)
5527{
5528 struct drm_i915_private *dev_priv;
5529 bool ret = true;
5530
9270388e 5531 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5532 if (!i915_mch_dev) {
5533 ret = false;
5534 goto out_unlock;
5535 }
5536 dev_priv = i915_mch_dev;
5537
20e4d407
DV
5538 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5539 dev_priv->ips.max_delay++;
eb48eb00
DV
5540
5541out_unlock:
9270388e 5542 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5543
5544 return ret;
5545}
5546EXPORT_SYMBOL_GPL(i915_gpu_lower);
5547
5548/**
5549 * i915_gpu_busy - indicate GPU business to IPS
5550 *
5551 * Tell the IPS driver whether or not the GPU is busy.
5552 */
5553bool i915_gpu_busy(void)
5554{
5555 struct drm_i915_private *dev_priv;
a4872ba6 5556 struct intel_engine_cs *ring;
eb48eb00 5557 bool ret = false;
f047e395 5558 int i;
eb48eb00 5559
9270388e 5560 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5561 if (!i915_mch_dev)
5562 goto out_unlock;
5563 dev_priv = i915_mch_dev;
5564
f047e395
CW
5565 for_each_ring(ring, dev_priv, i)
5566 ret |= !list_empty(&ring->request_list);
eb48eb00
DV
5567
5568out_unlock:
9270388e 5569 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5570
5571 return ret;
5572}
5573EXPORT_SYMBOL_GPL(i915_gpu_busy);
5574
5575/**
5576 * i915_gpu_turbo_disable - disable graphics turbo
5577 *
5578 * Disable graphics turbo by resetting the max frequency and setting the
5579 * current frequency to the default.
5580 */
5581bool i915_gpu_turbo_disable(void)
5582{
5583 struct drm_i915_private *dev_priv;
5584 bool ret = true;
5585
9270388e 5586 spin_lock_irq(&mchdev_lock);
eb48eb00
DV
5587 if (!i915_mch_dev) {
5588 ret = false;
5589 goto out_unlock;
5590 }
5591 dev_priv = i915_mch_dev;
5592
20e4d407 5593 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5594
20e4d407 5595 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV
5596 ret = false;
5597
5598out_unlock:
9270388e 5599 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5600
5601 return ret;
5602}
5603EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5604
5605/**
5606 * Tells the intel_ips driver that the i915 driver is now loaded, if
5607 * IPS got loaded first.
5608 *
5609 * This awkward dance is so that neither module has to depend on the
5610 * other in order for IPS to do the appropriate communication of
5611 * GPU turbo limits to i915.
5612 */
5613static void
5614ips_ping_for_i915_load(void)
5615{
5616 void (*link)(void);
5617
5618 link = symbol_get(ips_link_to_i915_driver);
5619 if (link) {
5620 link();
5621 symbol_put(ips_link_to_i915_driver);
5622 }
5623}
5624
5625void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5626{
02d71956
DV
5627 /* We only register the i915 ips part with intel-ips once everything is
5628 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5629 spin_lock_irq(&mchdev_lock);
eb48eb00 5630 i915_mch_dev = dev_priv;
9270388e 5631 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV
5632
5633 ips_ping_for_i915_load();
5634}
5635
5636void intel_gpu_ips_teardown(void)
5637{
9270388e 5638 spin_lock_irq(&mchdev_lock);
eb48eb00 5639 i915_mch_dev = NULL;
9270388e 5640 spin_unlock_irq(&mchdev_lock);
eb48eb00 5641}
76c3552f 5642
8090c6b9 5643static void intel_init_emon(struct drm_device *dev)
dde18883
ED
5644{
5645 struct drm_i915_private *dev_priv = dev->dev_private;
5646 u32 lcfuse;
5647 u8 pxw[16];
5648 int i;
5649
5650 /* Disable to program */
5651 I915_WRITE(ECR, 0);
5652 POSTING_READ(ECR);
5653
5654 /* Program energy weights for various events */
5655 I915_WRITE(SDEW, 0x15040d00);
5656 I915_WRITE(CSIEW0, 0x007f0000);
5657 I915_WRITE(CSIEW1, 0x1e220004);
5658 I915_WRITE(CSIEW2, 0x04000004);
5659
5660 for (i = 0; i < 5; i++)
5661 I915_WRITE(PEW + (i * 4), 0);
5662 for (i = 0; i < 3; i++)
5663 I915_WRITE(DEW + (i * 4), 0);
5664
5665 /* Program P-state weights to account for frequency power adjustment */
5666 for (i = 0; i < 16; i++) {
5667 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
5668 unsigned long freq = intel_pxfreq(pxvidfreq);
5669 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5670 PXVFREQ_PX_SHIFT;
5671 unsigned long val;
5672
5673 val = vid * vid;
5674 val *= (freq / 1000);
5675 val *= 255;
5676 val /= (127*127*900);
5677 if (val > 0xff)
5678 DRM_ERROR("bad pxval: %ld\n", val);
5679 pxw[i] = val;
5680 }
5681 /* Render standby states get 0 weight */
5682 pxw[14] = 0;
5683 pxw[15] = 0;
5684
5685 for (i = 0; i < 4; i++) {
5686 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5687 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
5688 I915_WRITE(PXW + (i * 4), val);
5689 }
5690
5691 /* Adjust magic regs to magic values (more experimental results) */
5692 I915_WRITE(OGW0, 0);
5693 I915_WRITE(OGW1, 0);
5694 I915_WRITE(EG0, 0x00007f00);
5695 I915_WRITE(EG1, 0x0000000e);
5696 I915_WRITE(EG2, 0x000e0000);
5697 I915_WRITE(EG3, 0x68000300);
5698 I915_WRITE(EG4, 0x42000000);
5699 I915_WRITE(EG5, 0x00140031);
5700 I915_WRITE(EG6, 0);
5701 I915_WRITE(EG7, 0);
5702
5703 for (i = 0; i < 8; i++)
5704 I915_WRITE(PXWL + (i * 4), 0);
5705
5706 /* Enable PMON + select events */
5707 I915_WRITE(ECR, 0x80000019);
5708
5709 lcfuse = I915_READ(LCFUSE02);
5710
20e4d407 5711 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED
5712}
5713
ae48434c
ID
5714void intel_init_gt_powersave(struct drm_device *dev)
5715{
e6069ca8
ID
5716 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
5717
38807746
D
5718 if (IS_CHERRYVIEW(dev))
5719 cherryview_init_gt_powersave(dev);
5720 else if (IS_VALLEYVIEW(dev))
4e80519e 5721 valleyview_init_gt_powersave(dev);
ae48434c
ID
5722}
5723
5724void intel_cleanup_gt_powersave(struct drm_device *dev)
5725{
38807746
D
5726 if (IS_CHERRYVIEW(dev))
5727 return;
5728 else if (IS_VALLEYVIEW(dev))
4e80519e 5729 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID
5730}
5731
dbea3cea
ID
5732static void gen6_suspend_rps(struct drm_device *dev)
5733{
5734 struct drm_i915_private *dev_priv = dev->dev_private;
5735
5736 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
5737
4c2a8897 5738 gen6_disable_rps_interrupts(dev);
dbea3cea
ID
5739}
5740
156c7ca0
JB
5741/**
5742 * intel_suspend_gt_powersave - suspend PM work and helper threads
5743 * @dev: drm device
5744 *
5745 * We don't want to disable RC6 or other features here, we just want
5746 * to make sure any work we've queued has finished and won't bother
5747 * us while we're suspended.
5748 */
5749void intel_suspend_gt_powersave(struct drm_device *dev)
5750{
5751 struct drm_i915_private *dev_priv = dev->dev_private;
5752
d4d70aa5
ID
5753 if (INTEL_INFO(dev)->gen < 6)
5754 return;
5755
dbea3cea 5756 gen6_suspend_rps(dev);
b47adc17
D
5757
5758 /* Force GPU to min freq during suspend */
5759 gen6_rps_idle(dev_priv);
156c7ca0
JB
5760}
5761
8090c6b9
DV
5762void intel_disable_gt_powersave(struct drm_device *dev)
5763{
1a01ab3b
JB
5764 struct drm_i915_private *dev_priv = dev->dev_private;
5765
930ebb46 5766 if (IS_IRONLAKE_M(dev)) {
8090c6b9 5767 ironlake_disable_drps(dev);
38807746 5768 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 5769 intel_suspend_gt_powersave(dev);
e494837a 5770
4fc688ce 5771 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW
5772 if (INTEL_INFO(dev)->gen >= 9)
5773 gen9_disable_rps(dev);
5774 else if (IS_CHERRYVIEW(dev))
38807746
D
5775 cherryview_disable_rps(dev);
5776 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB
5777 valleyview_disable_rps(dev);
5778 else
5779 gen6_disable_rps(dev);
e534770a 5780
c0951f0c 5781 dev_priv->rps.enabled = false;
4fc688ce 5782 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 5783 }
8090c6b9
DV
5784}
5785
1a01ab3b
JB
5786static void intel_gen6_powersave_work(struct work_struct *work)
5787{
5788 struct drm_i915_private *dev_priv =
5789 container_of(work, struct drm_i915_private,
5790 rps.delayed_resume_work.work);
5791 struct drm_device *dev = dev_priv->dev;
5792
4fc688ce 5793 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 5794
4c2a8897 5795 gen6_reset_rps_interrupts(dev);
3cc134e3 5796
38807746
D
5797 if (IS_CHERRYVIEW(dev)) {
5798 cherryview_enable_rps(dev);
5799 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 5800 valleyview_enable_rps(dev);
20e49366 5801 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 5802 gen9_enable_rc6(dev);
20e49366 5803 gen9_enable_rps(dev);
b6fef0ef 5804 __gen6_update_ring_freq(dev);
6edee7f3
BW
5805 } else if (IS_BROADWELL(dev)) {
5806 gen8_enable_rps(dev);
c2bc2fc5 5807 __gen6_update_ring_freq(dev);
0a073b84
JB
5808 } else {
5809 gen6_enable_rps(dev);
c2bc2fc5 5810 __gen6_update_ring_freq(dev);
0a073b84 5811 }
aed242ff
CW
5812
5813 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
5814 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
5815
5816 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
5817 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
5818
c0951f0c 5819 dev_priv->rps.enabled = true;
3cc134e3 5820
4c2a8897 5821 gen6_enable_rps_interrupts(dev);
3cc134e3 5822
4fc688ce 5823 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID
5824
5825 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB
5826}
5827
8090c6b9
DV
5828void intel_enable_gt_powersave(struct drm_device *dev)
5829{
1a01ab3b
JB
5830 struct drm_i915_private *dev_priv = dev->dev_private;
5831
f61018b1
YZ
5832 /* Powersaving is controlled by the host when inside a VM */
5833 if (intel_vgpu_active(dev))
5834 return;
5835
8090c6b9 5836 if (IS_IRONLAKE_M(dev)) {
dc1d0136 5837 mutex_lock(&dev->struct_mutex);
8090c6b9 5838 ironlake_enable_drps(dev);
8090c6b9 5839 intel_init_emon(dev);
dc1d0136 5840 mutex_unlock(&dev->struct_mutex);
38807746 5841 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB
5842 /*
5843 * PCU communication is slow and this doesn't need to be
5844 * done at any specific time, so do this out of our fast path
5845 * to make resume and init faster.
c6df39b5
ID
5846 *
5847 * We depend on the HW RC6 power context save/restore
5848 * mechanism when entering D3 through runtime PM suspend. So
5849 * disable RPM until RPS/RC6 is properly setup. We can only
5850 * get here via the driver load/system resume/runtime resume
5851 * paths, so the _noresume version is enough (and in case of
5852 * runtime resume it's necessary).
1a01ab3b 5853 */
c6df39b5
ID
5854 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
5855 round_jiffies_up_relative(HZ)))
5856 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV
5857 }
5858}
5859
c6df39b5
ID
5860void intel_reset_gt_powersave(struct drm_device *dev)
5861{
5862 struct drm_i915_private *dev_priv = dev->dev_private;
5863
dbea3cea
ID
5864 if (INTEL_INFO(dev)->gen < 6)
5865 return;
5866
5867 gen6_suspend_rps(dev);
c6df39b5 5868 dev_priv->rps.enabled = false;
c6df39b5
ID
5869}
5870
3107bd48
DV
5871static void ibx_init_clock_gating(struct drm_device *dev)
5872{
5873 struct drm_i915_private *dev_priv = dev->dev_private;
5874
5875 /*
5876 * On Ibex Peak and Cougar Point, we need to disable clock
5877 * gating for the panel power sequencer or it will fail to
5878 * start up when no ports are active.
5879 */
5880 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
5881}
5882
0e088b8f
VS
5883static void g4x_disable_trickle_feed(struct drm_device *dev)
5884{
5885 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 5886 enum pipe pipe;
0e088b8f 5887
055e393f 5888 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS
5889 I915_WRITE(DSPCNTR(pipe),
5890 I915_READ(DSPCNTR(pipe)) |
5891 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS
5892
5893 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
5894 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS
5895 }
5896}
5897
017636cc
VS
5898static void ilk_init_lp_watermarks(struct drm_device *dev)
5899{
5900 struct drm_i915_private *dev_priv = dev->dev_private;
5901
5902 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
5903 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
5904 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
5905
5906 /*
5907 * Don't touch WM1S_LP_EN here.
5908 * Doing so could cause underruns.
5909 */
5910}
5911
1fa61106 5912static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
5913{
5914 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 5915 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 5916
f1e8fa56
DL
5917 /*
5918 * Required for FBC
5919 * WaFbcDisableDpfcClockGating:ilk
5920 */
4d47e4f5
DL
5921 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
5922 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
5923 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED
5924
5925 I915_WRITE(PCH_3DCGDIS0,
5926 MARIUNIT_CLOCK_GATE_DISABLE |
5927 SVSMUNIT_CLOCK_GATE_DISABLE);
5928 I915_WRITE(PCH_3DCGDIS1,
5929 VFMUNIT_CLOCK_GATE_DISABLE);
5930
6f1d69b0
ED
5931 /*
5932 * According to the spec the following bits should be set in
5933 * order to enable memory self-refresh
5934 * The bit 22/21 of 0x42004
5935 * The bit 5 of 0x42020
5936 * The bit 15 of 0x45000
5937 */
5938 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5939 (I915_READ(ILK_DISPLAY_CHICKEN2) |
5940 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 5941 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED
5942 I915_WRITE(DISP_ARB_CTL,
5943 (I915_READ(DISP_ARB_CTL) |
5944 DISP_FBC_WM_DIS));
017636cc
VS
5945
5946 ilk_init_lp_watermarks(dev);
6f1d69b0
ED
5947
5948 /*
5949 * Based on the document from hardware guys the following bits
5950 * should be set unconditionally in order to enable FBC.
5951 * The bit 22 of 0x42000
5952 * The bit 22 of 0x42004
5953 * The bit 7,8,9 of 0x42020.
5954 */
5955 if (IS_IRONLAKE_M(dev)) {
4bb35334 5956 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED
5957 I915_WRITE(ILK_DISPLAY_CHICKEN1,
5958 I915_READ(ILK_DISPLAY_CHICKEN1) |
5959 ILK_FBCQ_DIS);
5960 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5961 I915_READ(ILK_DISPLAY_CHICKEN2) |
5962 ILK_DPARB_GATE);
6f1d69b0
ED
5963 }
5964
4d47e4f5
DL
5965 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
5966
6f1d69b0
ED
5967 I915_WRITE(ILK_DISPLAY_CHICKEN2,
5968 I915_READ(ILK_DISPLAY_CHICKEN2) |
5969 ILK_ELPIN_409_SELECT);
5970 I915_WRITE(_3D_CHICKEN2,
5971 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
5972 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 5973
ecdb4eb7 5974 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV
5975 I915_WRITE(CACHE_MODE_0,
5976 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 5977
4e04632e
AG
5978 /* WaDisable_RenderCache_OperationalFlush:ilk */
5979 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
5980
0e088b8f 5981 g4x_disable_trickle_feed(dev);
bdad2b2f 5982
3107bd48
DV
5983 ibx_init_clock_gating(dev);
5984}
5985
5986static void cpt_init_clock_gating(struct drm_device *dev)
5987{
5988 struct drm_i915_private *dev_priv = dev->dev_private;
5989 int pipe;
3f704fa2 5990 uint32_t val;
3107bd48
DV
5991
5992 /*
5993 * On Ibex Peak and Cougar Point, we need to disable clock
5994 * gating for the panel power sequencer or it will fail to
5995 * start up when no ports are active.
5996 */
cd664078
JB
5997 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
5998 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
5999 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV
6000 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6001 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI
6002 /* The below fixes the weird display corruption, a few pixels shifted
6003 * downward, on (only) LVDS of some HP laptops with IVY.
6004 */
055e393f 6005 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ
6006 val = I915_READ(TRANS_CHICKEN2(pipe));
6007 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6008 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6009 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6010 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ
6011 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6012 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6013 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ
6014 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6015 }
3107bd48 6016 /* WADP0ClockGatingDisable */
055e393f 6017 for_each_pipe(dev_priv, pipe) {
3107bd48
DV
6018 I915_WRITE(TRANS_CHICKEN1(pipe),
6019 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6020 }
6f1d69b0
ED
6021}
6022
1d7aaa0c
DV
6023static void gen6_check_mch_setup(struct drm_device *dev)
6024{
6025 struct drm_i915_private *dev_priv = dev->dev_private;
6026 uint32_t tmp;
6027
6028 tmp = I915_READ(MCH_SSKPD);
df662a28
DV
6029 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6030 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6031 tmp);
1d7aaa0c
DV
6032}
6033
1fa61106 6034static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6035{
6036 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6037 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6038
231e54f6 6039 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED
6040
6041 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6042 I915_READ(ILK_DISPLAY_CHICKEN2) |
6043 ILK_ELPIN_409_SELECT);
6044
ecdb4eb7 6045 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV
6046 I915_WRITE(_3D_CHICKEN,
6047 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6048
4e04632e
AG
6049 /* WaDisable_RenderCache_OperationalFlush:snb */
6050 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6051
8d85d272
VS
6052 /*
6053 * BSpec recoomends 8x4 when MSAA is used,
6054 * however in practice 16x4 seems fastest.
c5c98a58
VS
6055 *
6056 * Note that PS/WM thread counts depend on the WIZ hashing
6057 * disable bit, which we don't touch here, but it's good
6058 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS
6059 */
6060 I915_WRITE(GEN6_GT_MODE,
98533251 6061 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6062
017636cc 6063 ilk_init_lp_watermarks(dev);
6f1d69b0 6064
6f1d69b0 6065 I915_WRITE(CACHE_MODE_0,
50743298 6066 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED
6067
6068 I915_WRITE(GEN6_UCGCTL1,
6069 I915_READ(GEN6_UCGCTL1) |
6070 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6071 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6072
6073 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6074 * gating disable must be set. Failure to set it results in
6075 * flickering pixels due to Z write ordering failures after
6076 * some amount of runtime in the Mesa "fire" demo, and Unigine
6077 * Sanctuary and Tropics, and apparently anything else with
6078 * alpha test or pixel discard.
6079 *
6080 * According to the spec, bit 11 (RCCUNIT) must also be set,
6081 * but we didn't debug actual testcases to find it out.
0f846f81 6082 *
ef59318c
VS
6083 * WaDisableRCCUnitClockGating:snb
6084 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED
6085 */
6086 I915_WRITE(GEN6_UCGCTL2,
6087 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6088 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6089
5eb146dd 6090 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS
6091 I915_WRITE(_3D_CHICKEN3,
6092 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6093
e927ecde
VS
6094 /*
6095 * Bspec says:
6096 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6097 * 3DSTATE_SF number of SF output attributes is more than 16."
6098 */
6099 I915_WRITE(_3D_CHICKEN3,
6100 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6101
6f1d69b0
ED
6102 /*
6103 * According to the spec the following bits should be
6104 * set in order to enable memory self-refresh and fbc:
6105 * The bit21 and bit22 of 0x42000
6106 * The bit21 and bit22 of 0x42004
6107 * The bit5 and bit7 of 0x42020
6108 * The bit14 of 0x70180
6109 * The bit14 of 0x71180
4bb35334
DL
6110 *
6111 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED
6112 */
6113 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6114 I915_READ(ILK_DISPLAY_CHICKEN1) |
6115 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6116 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6117 I915_READ(ILK_DISPLAY_CHICKEN2) |
6118 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL
6119 I915_WRITE(ILK_DSPCLK_GATE_D,
6120 I915_READ(ILK_DSPCLK_GATE_D) |
6121 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6122 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6123
0e088b8f 6124 g4x_disable_trickle_feed(dev);
f8f2ac9a 6125
3107bd48 6126 cpt_init_clock_gating(dev);
1d7aaa0c
DV
6127
6128 gen6_check_mch_setup(dev);
6f1d69b0
ED
6129}
6130
6131static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6132{
6133 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6134
3aad9059 6135 /*
46680e0a 6136 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS
6137 *
6138 * This actually overrides the dispatch
6139 * mode for all thread types.
6140 */
6f1d69b0
ED
6141 reg &= ~GEN7_FF_SCHED_MASK;
6142 reg |= GEN7_FF_TS_SCHED_HW;
6143 reg |= GEN7_FF_VS_SCHED_HW;
6144 reg |= GEN7_FF_DS_SCHED_HW;
6145
6146 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6147}
6148
17a303ec
PZ
6149static void lpt_init_clock_gating(struct drm_device *dev)
6150{
6151 struct drm_i915_private *dev_priv = dev->dev_private;
6152
6153 /*
6154 * TODO: this bit should only be enabled when really needed, then
6155 * disabled when not needed anymore in order to save power.
6156 */
6157 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6158 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6159 I915_READ(SOUTH_DSPCLK_GATE_D) |
6160 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ
6161
6162 /* WADPOClockGatingDisable:hsw */
6163 I915_WRITE(_TRANSA_CHICKEN1,
6164 I915_READ(_TRANSA_CHICKEN1) |
6165 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ
6166}
6167
7d708ee4
ID
6168static void lpt_suspend_hw(struct drm_device *dev)
6169{
6170 struct drm_i915_private *dev_priv = dev->dev_private;
6171
6172 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6173 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6174
6175 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6176 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6177 }
6178}
6179
47c2bd97 6180static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW
6181{
6182 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6183 enum pipe pipe;
4d487cff 6184 uint32_t misccpctl;
1020a5c2 6185
7ad0dbab 6186 ilk_init_lp_watermarks(dev);
50ed5fbd 6187
ab57fff1 6188 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6189 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6190
ab57fff1 6191 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW
6192 I915_WRITE(CHICKEN_PAR1_1,
6193 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6194
ab57fff1 6195 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6196 for_each_pipe(dev_priv, pipe) {
07d27e20 6197 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6198 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6199 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6200 }
63801f21 6201
ab57fff1
BW
6202 /* WaVSRefCountFullforceMissDisable:bdw */
6203 /* WaDSRefCountFullforceMissDisable:bdw */
6204 I915_WRITE(GEN7_FF_THREAD_MODE,
6205 I915_READ(GEN7_FF_THREAD_MODE) &
6206 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6207
295e8bb7
VS
6208 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6209 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS
6210
6211 /* WaDisableSDEUnitClockGating:bdw */
6212 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6213 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6214
4d487cff
VS
6215 /*
6216 * WaProgramL3SqcReg1Default:bdw
6217 * WaTempDisableDOPClkGating:bdw
6218 */
6219 misccpctl = I915_READ(GEN7_MISCCPCTL);
6220 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6221 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6222 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6223
6d50b065
VS
6224 /*
6225 * WaGttCachingOffByDefault:bdw
6226 * GTT cache may not work with big pages, so if those
6227 * are ever enabled GTT cache may need to be disabled.
6228 */
6229 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6230
89d6b2b8 6231 lpt_init_clock_gating(dev);
1020a5c2
BW
6232}
6233
cad2a2d7
ED
6234static void haswell_init_clock_gating(struct drm_device *dev)
6235{
6236 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6237
017636cc 6238 ilk_init_lp_watermarks(dev);
cad2a2d7 6239
f3fc4884
FJ
6240 /* L3 caching of data atomics doesn't work -- disable it. */
6241 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6242 I915_WRITE(HSW_ROW_CHICKEN3,
6243 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6244
ecdb4eb7 6245 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED
6246 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6247 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6248 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6249
e36ea7ff
VS
6250 /* WaVSRefCountFullforceMissDisable:hsw */
6251 I915_WRITE(GEN7_FF_THREAD_MODE,
6252 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6253
4e04632e
AG
6254 /* WaDisable_RenderCache_OperationalFlush:hsw */
6255 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6256
fe27c606
CW
6257 /* enable HiZ Raw Stall Optimization */
6258 I915_WRITE(CACHE_MODE_0_GEN7,
6259 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6260
ecdb4eb7 6261 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED
6262 I915_WRITE(CACHE_MODE_1,
6263 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6264
a12c4967
VS
6265 /*
6266 * BSpec recommends 8x4 when MSAA is used,
6267 * however in practice 16x4 seems fastest.
c5c98a58
VS
6268 *
6269 * Note that PS/WM thread counts depend on the WIZ hashing
6270 * disable bit, which we don't touch here, but it's good
6271 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS
6272 */
6273 I915_WRITE(GEN7_GT_MODE,
98533251 6274 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6275
94411593
KG
6276 /* WaSampleCChickenBitEnable:hsw */
6277 I915_WRITE(HALF_SLICE_CHICKEN3,
6278 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6279
ecdb4eb7 6280 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW
6281 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6282
90a88643
PZ
6283 /* WaRsPkgCStateDisplayPMReq:hsw */
6284 I915_WRITE(CHICKEN_PAR1_1,
6285 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6286
17a303ec 6287 lpt_init_clock_gating(dev);
cad2a2d7
ED
6288}
6289
1fa61106 6290static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6291{
6292 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6293 uint32_t snpcr;
6f1d69b0 6294
017636cc 6295 ilk_init_lp_watermarks(dev);
6f1d69b0 6296
231e54f6 6297 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6298
ecdb4eb7 6299 /* WaDisableEarlyCull:ivb */
87f8020e
JB
6300 I915_WRITE(_3D_CHICKEN3,
6301 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6302
ecdb4eb7 6303 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED
6304 I915_WRITE(IVB_CHICKEN3,
6305 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6306 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6307
ecdb4eb7 6308 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB
6309 if (IS_IVB_GT1(dev))
6310 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6311 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6312
4e04632e
AG
6313 /* WaDisable_RenderCache_OperationalFlush:ivb */
6314 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6315
ecdb4eb7 6316 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED
6317 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6318 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6319
ecdb4eb7 6320 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED
6321 I915_WRITE(GEN7_L3CNTLREG1,
6322 GEN7_WA_FOR_GEN7_L3_CONTROL);
6323 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB
6324 GEN7_WA_L3_CHICKEN_MODE);
6325 if (IS_IVB_GT1(dev))
6326 I915_WRITE(GEN7_ROW_CHICKEN2,
6327 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS
6328 else {
6329 /* must write both registers */
6330 I915_WRITE(GEN7_ROW_CHICKEN2,
6331 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB
6332 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6333 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6334 }
6f1d69b0 6335
ecdb4eb7 6336 /* WaForceL3Serialization:ivb */
61939d97
JB
6337 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6338 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6339
1b80a19a 6340 /*
0f846f81 6341 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6342 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB
6343 */
6344 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6345 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6346
ecdb4eb7 6347 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED
6348 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6349 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6350 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6351
0e088b8f 6352 g4x_disable_trickle_feed(dev);
6f1d69b0
ED
6353
6354 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6355
22721343
CW
6356 if (0) { /* causes HiZ corruption on ivb:gt1 */
6357 /* enable HiZ Raw Stall Optimization */
6358 I915_WRITE(CACHE_MODE_0_GEN7,
6359 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6360 }
116f2b6d 6361
ecdb4eb7 6362 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV
6363 I915_WRITE(CACHE_MODE_1,
6364 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6365
a607c1a4
VS
6366 /*
6367 * BSpec recommends 8x4 when MSAA is used,
6368 * however in practice 16x4 seems fastest.
c5c98a58
VS
6369 *
6370 * Note that PS/WM thread counts depend on the WIZ hashing
6371 * disable bit, which we don't touch here, but it's good
6372 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS
6373 */
6374 I915_WRITE(GEN7_GT_MODE,
98533251 6375 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6376
20848223
BW
6377 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6378 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6379 snpcr |= GEN6_MBC_SNPCR_MED;
6380 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6381
ab5c608b
BW
6382 if (!HAS_PCH_NOP(dev))
6383 cpt_init_clock_gating(dev);
1d7aaa0c
DV
6384
6385 gen6_check_mch_setup(dev);
6f1d69b0
ED
6386}
6387
c6beb13e
VS
6388static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6389{
6390 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6391
6392 /*
6393 * Disable trickle feed and enable pnd deadline calculation
6394 */
6395 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6396 I915_WRITE(CBR1_VLV, 0);
6397}
6398
1fa61106 6399static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6400{
6401 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6402
c6beb13e 6403 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6404
ecdb4eb7 6405 /* WaDisableEarlyCull:vlv */
87f8020e
JB
6406 I915_WRITE(_3D_CHICKEN3,
6407 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6408
ecdb4eb7 6409 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED
6410 I915_WRITE(IVB_CHICKEN3,
6411 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6412 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6413
fad7d36e 6414 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6415 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6416 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB
6417 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6418 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6419
4e04632e
AG
6420 /* WaDisable_RenderCache_OperationalFlush:vlv */
6421 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6422
ecdb4eb7 6423 /* WaForceL3Serialization:vlv */
61939d97
JB
6424 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6425 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6426
ecdb4eb7 6427 /* WaDisableDopClockGating:vlv */
8ab43976
JB
6428 I915_WRITE(GEN7_ROW_CHICKEN2,
6429 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6430
ecdb4eb7 6431 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED
6432 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6433 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6434 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6435
46680e0a
VS
6436 gen7_setup_fixed_func_scheduler(dev_priv);
6437
3c0edaeb 6438 /*
0f846f81 6439 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6440 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB
6441 */
6442 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6443 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6444
c98f5062
AG
6445 /* WaDisableL3Bank2xClockGate:vlv
6446 * Disabling L3 clock gating- MMIO 940c[25] = 1
6447 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6448 I915_WRITE(GEN7_UCGCTL4,
6449 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6450
afd58e79
VS
6451 /*
6452 * BSpec says this must be set, even though
6453 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6454 */
6b26c86d
DV
6455 I915_WRITE(CACHE_MODE_1,
6456 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6457
da2518f9
VS
6458 /*
6459 * BSpec recommends 8x4 when MSAA is used,
6460 * however in practice 16x4 seems fastest.
6461 *
6462 * Note that PS/WM thread counts depend on the WIZ hashing
6463 * disable bit, which we don't touch here, but it's good
6464 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6465 */
6466 I915_WRITE(GEN7_GT_MODE,
6467 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6468
031994ee
VS
6469 /*
6470 * WaIncreaseL3CreditsForVLVB0:vlv
6471 * This is the hardware default actually.
6472 */
6473 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6474
2d809570 6475 /*
ecdb4eb7 6476 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB
6477 * Disable clock gating on th GCFG unit to prevent a delay
6478 * in the reporting of vblank events.
6479 */
7a0d1eed 6480 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED
6481}
6482
a4565da8
VS
6483static void cherryview_init_clock_gating(struct drm_device *dev)
6484{
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486
c6beb13e 6487 vlv_init_display_clock_gating(dev_priv);
dd811e70 6488
232ce337
VS
6489 /* WaVSRefCountFullforceMissDisable:chv */
6490 /* WaDSRefCountFullforceMissDisable:chv */
6491 I915_WRITE(GEN7_FF_THREAD_MODE,
6492 I915_READ(GEN7_FF_THREAD_MODE) &
6493 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS
6494
6495 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6496 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6497 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS
6498
6499 /* WaDisableCSUnitClockGating:chv */
6500 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6501 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS
6502
6503 /* WaDisableSDEUnitClockGating:chv */
6504 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6505 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS
6506
6507 /*
6508 * GTT cache may not work with big pages, so if those
6509 * are ever enabled GTT cache may need to be disabled.
6510 */
6511 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS
6512}
6513
1fa61106 6514static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6515{
6516 struct drm_i915_private *dev_priv = dev->dev_private;
6517 uint32_t dspclk_gate;
6518
6519 I915_WRITE(RENCLK_GATE_D1, 0);
6520 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6521 GS_UNIT_CLOCK_GATE_DISABLE |
6522 CL_UNIT_CLOCK_GATE_DISABLE);
6523 I915_WRITE(RAMCLK_GATE_D, 0);
6524 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6525 OVRUNIT_CLOCK_GATE_DISABLE |
6526 OVCUNIT_CLOCK_GATE_DISABLE;
6527 if (IS_GM45(dev))
6528 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6529 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV
6530
6531 /* WaDisableRenderCachePipelinedFlush */
6532 I915_WRITE(CACHE_MODE_0,
6533 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6534
4e04632e
AG
6535 /* WaDisable_RenderCache_OperationalFlush:g4x */
6536 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6537
0e088b8f 6538 g4x_disable_trickle_feed(dev);
6f1d69b0
ED
6539}
6540
1fa61106 6541static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6542{
6543 struct drm_i915_private *dev_priv = dev->dev_private;
6544
6545 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6546 I915_WRITE(RENCLK_GATE_D2, 0);
6547 I915_WRITE(DSPCLK_GATE_D, 0);
6548 I915_WRITE(RAMCLK_GATE_D, 0);
6549 I915_WRITE16(DEUC, 0);
20f94967
VS
6550 I915_WRITE(MI_ARB_STATE,
6551 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG
6552
6553 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6554 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED
6555}
6556
1fa61106 6557static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6558{
6559 struct drm_i915_private *dev_priv = dev->dev_private;
6560
6561 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6562 I965_RCC_CLOCK_GATE_DISABLE |
6563 I965_RCPB_CLOCK_GATE_DISABLE |
6564 I965_ISC_CLOCK_GATE_DISABLE |
6565 I965_FBC_CLOCK_GATE_DISABLE);
6566 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS
6567 I915_WRITE(MI_ARB_STATE,
6568 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG
6569
6570 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6571 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED
6572}
6573
1fa61106 6574static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6575{
6576 struct drm_i915_private *dev_priv = dev->dev_private;
6577 u32 dstate = I915_READ(D_STATE);
6578
6579 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6580 DSTATE_DOT_CLOCK_GATING;
6581 I915_WRITE(D_STATE, dstate);
13a86b85
CW
6582
6583 if (IS_PINEVIEW(dev))
6584 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV
6585
6586 /* IIR "flip pending" means done if this bit is set */
6587 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS
6588
6589 /* interrupts should cause a wake up from C3 */
3299254f 6590 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS
6591
6592 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6593 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS
6594
6595 I915_WRITE(MI_ARB_STATE,
6596 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6597}
6598
1fa61106 6599static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6600{
6601 struct drm_i915_private *dev_priv = dev->dev_private;
6602
6603 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS
6604
6605 /* interrupts should cause a wake up from C3 */
6606 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6607 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS
6608
6609 I915_WRITE(MEM_MODE,
6610 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6611}
6612
1fa61106 6613static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED
6614{
6615 struct drm_i915_private *dev_priv = dev->dev_private;
6616
6617 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS
6618
6619 I915_WRITE(MEM_MODE,
6620 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6621 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED
6622}
6623
6f1d69b0
ED
6624void intel_init_clock_gating(struct drm_device *dev)
6625{
6626 struct drm_i915_private *dev_priv = dev->dev_private;
6627
c57e3551
DL
6628 if (dev_priv->display.init_clock_gating)
6629 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED
6630}
6631
7d708ee4
ID
6632void intel_suspend_hw(struct drm_device *dev)
6633{
6634 if (HAS_PCH_LPT(dev))
6635 lpt_suspend_hw(dev);
6636}
6637
1fa61106
ED
6638/* Set up chip specific power management-related functions */
6639void intel_init_pm(struct drm_device *dev)
6640{
6641 struct drm_i915_private *dev_priv = dev->dev_private;
6642
7ff0ebcc 6643 intel_fbc_init(dev_priv);
1fa61106 6644
c921aba8
DV
6645 /* For cxsr */
6646 if (IS_PINEVIEW(dev))
6647 i915_pineview_get_mem_freq(dev);
6648 else if (IS_GEN5(dev))
6649 i915_ironlake_get_mem_freq(dev);
6650
1fa61106 6651 /* For FIFO watermark updates */
f5ed50cb 6652 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB
6653 skl_setup_wm_latency(dev);
6654
a82abe43
ID
6655 if (IS_BROXTON(dev))
6656 dev_priv->display.init_clock_gating =
6657 bxt_init_clock_gating;
6658 else if (IS_SKYLAKE(dev))
6659 dev_priv->display.init_clock_gating =
6660 skl_init_clock_gating;
2d41c0b5
PB
6661 dev_priv->display.update_wm = skl_update_wm;
6662 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 6663 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6664 ilk_setup_wm_latency(dev);
53615a5e 6665
bd602544
VS
6666 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6667 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6668 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6669 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6670 dev_priv->display.update_wm = ilk_update_wm;
6671 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
6672 } else {
6673 DRM_DEBUG_KMS("Failed to read display plane latency. "
6674 "Disable CxSR\n");
6675 }
6676
6677 if (IS_GEN5(dev))
1fa61106 6678 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6679 else if (IS_GEN6(dev))
1fa61106 6680 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6681 else if (IS_IVYBRIDGE(dev))
1fa61106 6682 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6683 else if (IS_HASWELL(dev))
cad2a2d7 6684 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6685 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6686 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6687 } else if (IS_CHERRYVIEW(dev)) {
ae80152d 6688 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6689 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
a4565da8
VS
6690 dev_priv->display.init_clock_gating =
6691 cherryview_init_clock_gating;
1fa61106
ED
6692 } else if (IS_VALLEYVIEW(dev)) {
6693 dev_priv->display.update_wm = valleyview_update_wm;
01e184cc 6694 dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm;
1fa61106
ED
6695 dev_priv->display.init_clock_gating =
6696 valleyview_init_clock_gating;
1fa61106
ED
6697 } else if (IS_PINEVIEW(dev)) {
6698 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
6699 dev_priv->is_ddr3,
6700 dev_priv->fsb_freq,
6701 dev_priv->mem_freq)) {
6702 DRM_INFO("failed to find known CxSR latency "
6703 "(found ddr%s fsb freq %d, mem freq %d), "
6704 "disabling CxSR\n",
6705 (dev_priv->is_ddr3 == 1) ? "3" : "2",
6706 dev_priv->fsb_freq, dev_priv->mem_freq);
6707 /* Disable CxSR and never update its watermark again */
5209b1f4 6708 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED
6709 dev_priv->display.update_wm = NULL;
6710 } else
6711 dev_priv->display.update_wm = pineview_update_wm;
6712 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
6713 } else if (IS_G4X(dev)) {
6714 dev_priv->display.update_wm = g4x_update_wm;
6715 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
6716 } else if (IS_GEN4(dev)) {
6717 dev_priv->display.update_wm = i965_update_wm;
6718 if (IS_CRESTLINE(dev))
6719 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
6720 else if (IS_BROADWATER(dev))
6721 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
6722 } else if (IS_GEN3(dev)) {
6723 dev_priv->display.update_wm = i9xx_update_wm;
6724 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
6725 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV
6726 } else if (IS_GEN2(dev)) {
6727 if (INTEL_INFO(dev)->num_pipes == 1) {
6728 dev_priv->display.update_wm = i845_update_wm;
1fa61106 6729 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV
6730 } else {
6731 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 6732 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV
6733 }
6734
6735 if (IS_I85X(dev) || IS_I865G(dev))
6736 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
6737 else
6738 dev_priv->display.init_clock_gating = i830_init_clock_gating;
6739 } else {
6740 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED
6741 }
6742}
6743
151a49d0 6744int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 6745{
4fc688ce 6746 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW
6747
6748 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6749 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
6750 return -EAGAIN;
6751 }
6752
6753 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 6754 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW
6755 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6756
6757 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6758 500)) {
6759 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
6760 return -ETIMEDOUT;
6761 }
6762
6763 *val = I915_READ(GEN6_PCODE_DATA);
6764 I915_WRITE(GEN6_PCODE_DATA, 0);
6765
6766 return 0;
6767}
6768
151a49d0 6769int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 6770{
4fc688ce 6771 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW
6772
6773 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
6774 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
6775 return -EAGAIN;
6776 }
6777
6778 I915_WRITE(GEN6_PCODE_DATA, val);
6779 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
6780
6781 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
6782 500)) {
6783 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
6784 return -ETIMEDOUT;
6785 }
6786
6787 I915_WRITE(GEN6_PCODE_DATA, 0);
6788
6789 return 0;
6790}
a0e4e199 6791
dd06f88c 6792static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 6793{
dd06f88c
VS
6794 switch (czclk_freq) {
6795 case 200:
6796 return 10;
6797 case 267:
6798 return 12;
6799 case 320:
6800 case 333:
dd06f88c 6801 return 16;
ab3fb157
VS
6802 case 400:
6803 return 20;
855ba3be
JB
6804 default:
6805 return -1;
6806 }
dd06f88c 6807}
855ba3be 6808
dd06f88c
VS
6809static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
6810{
6811 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
6812
6813 div = vlv_gpu_freq_div(czclk_freq);
6814 if (div < 0)
6815 return div;
6816
6817 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB
6818}
6819
b55dd647 6820static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 6821{
dd06f88c 6822 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 6823
dd06f88c
VS
6824 mul = vlv_gpu_freq_div(czclk_freq);
6825 if (mul < 0)
6826 return mul;
855ba3be 6827
dd06f88c 6828 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB
6829}
6830
b55dd647 6831static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6832{
dd06f88c 6833 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6834
dd06f88c
VS
6835 div = vlv_gpu_freq_div(czclk_freq) / 2;
6836 if (div < 0)
6837 return div;
22b1b2f8 6838
dd06f88c 6839 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D
6840}
6841
b55dd647 6842static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6843{
dd06f88c 6844 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 6845
dd06f88c
VS
6846 mul = vlv_gpu_freq_div(czclk_freq) / 2;
6847 if (mul < 0)
6848 return mul;
22b1b2f8 6849
1c14762d 6850 /* CHV needs even values */
dd06f88c 6851 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D
6852}
6853
616bc820 6854int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 6855{
80b6dda4
AG
6856 if (IS_GEN9(dev_priv->dev))
6857 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
6858 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6859 return chv_gpu_freq(dev_priv, val);
22b1b2f8 6860 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS
6861 return byt_gpu_freq(dev_priv, val);
6862 else
6863 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D
6864}
6865
616bc820
VS
6866int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
6867{
80b6dda4
AG
6868 if (IS_GEN9(dev_priv->dev))
6869 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
6870 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 6871 return chv_freq_opcode(dev_priv, val);
22b1b2f8 6872 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS
6873 return byt_freq_opcode(dev_priv, val);
6874 else
6875 return val / GT_FREQUENCY_MULTIPLIER;
6876}
22b1b2f8 6877
6ad790c0
CW
6878struct request_boost {
6879 struct work_struct work;
eed29a5b 6880 struct drm_i915_gem_request *req;
6ad790c0
CW
6881};
6882
6883static void __intel_rps_boost_work(struct work_struct *work)
6884{
6885 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 6886 struct drm_i915_gem_request *req = boost->req;
6ad790c0 6887
e61b9958
CW
6888 if (!i915_gem_request_completed(req, true))
6889 gen6_rps_boost(to_i915(req->ring->dev), NULL,
6890 req->emitted_jiffies);
6ad790c0 6891
e61b9958 6892 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW
6893 kfree(boost);
6894}
6895
6896void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 6897 struct drm_i915_gem_request *req)
6ad790c0
CW
6898{
6899 struct request_boost *boost;
6900
eed29a5b 6901 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW
6902 return;
6903
e61b9958
CW
6904 if (i915_gem_request_completed(req, true))
6905 return;
6906
6ad790c0
CW
6907 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
6908 if (boost == NULL)
6909 return;
6910
eed29a5b
DV
6911 i915_gem_request_reference(req);
6912 boost->req = req;
6ad790c0
CW
6913
6914 INIT_WORK(&boost->work, __intel_rps_boost_work);
6915 queue_work(to_i915(dev)->wq, &boost->work);
6916}
6917
f742a552 6918void intel_pm_setup(struct drm_device *dev)
907b28c5
CW
6919{
6920 struct drm_i915_private *dev_priv = dev->dev_private;
6921
f742a552 6922 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 6923 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 6924
907b28c5
CW
6925 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
6926 intel_gen6_powersave_work);
1854d5ca 6927 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW
6928 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
6929 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 6930
33688d95 6931 dev_priv->pm.suspended = false;
907b28c5 6932}