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drm/i915: Setup clipped src/dest coordinates during FB reconstruction (v2)
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
a82abe43
ID		 55static void bxt_init_clock_gating(struct drm_device *dev)
56{
32608ca2
ID		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
a7546159
NH		 59 /* WaDisableSDEUnitClockGating:bxt */
60 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
61 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
62
32608ca2
ID		 63 /*
64 * FIXME:
868434c5 65 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 66 */
32608ca2 67 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 68 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 69
70 /*
71 * Wa: Backlight PWM may stop in the asserted state, causing backlight
72 * to stay fully on.
73 */
74 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
75 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
76 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 77}
78
c921aba8
DV		 79static void i915_pineview_get_mem_freq(struct drm_device *dev)
80{
50227e1c 81 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 82 u32 tmp;
83
84 tmp = I915_READ(CLKCFG);
85
86 switch (tmp & CLKCFG_FSB_MASK) {
87 case CLKCFG_FSB_533:
88 dev_priv->fsb_freq = 533; /* 133*4 */
89 break;
90 case CLKCFG_FSB_800:
91 dev_priv->fsb_freq = 800; /* 200*4 */
92 break;
93 case CLKCFG_FSB_667:
94 dev_priv->fsb_freq = 667; /* 167*4 */
95 break;
96 case CLKCFG_FSB_400:
97 dev_priv->fsb_freq = 400; /* 100*4 */
98 break;
99 }
100
101 switch (tmp & CLKCFG_MEM_MASK) {
102 case CLKCFG_MEM_533:
103 dev_priv->mem_freq = 533;
104 break;
105 case CLKCFG_MEM_667:
106 dev_priv->mem_freq = 667;
107 break;
108 case CLKCFG_MEM_800:
109 dev_priv->mem_freq = 800;
110 break;
111 }
112
113 /* detect pineview DDR3 setting */
114 tmp = I915_READ(CSHRDDR3CTL);
115 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
116}
117
118static void i915_ironlake_get_mem_freq(struct drm_device *dev)
119{
50227e1c 120 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 121 u16 ddrpll, csipll;
122
123 ddrpll = I915_READ16(DDRMPLL1);
124 csipll = I915_READ16(CSIPLL0);
125
126 switch (ddrpll & 0xff) {
127 case 0xc:
128 dev_priv->mem_freq = 800;
129 break;
130 case 0x10:
131 dev_priv->mem_freq = 1066;
132 break;
133 case 0x14:
134 dev_priv->mem_freq = 1333;
135 break;
136 case 0x18:
137 dev_priv->mem_freq = 1600;
138 break;
139 default:
140 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
141 ddrpll & 0xff);
142 dev_priv->mem_freq = 0;
143 break;
144 }
145
20e4d407 146 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 147
148 switch (csipll & 0x3ff) {
149 case 0x00c:
150 dev_priv->fsb_freq = 3200;
151 break;
152 case 0x00e:
153 dev_priv->fsb_freq = 3733;
154 break;
155 case 0x010:
156 dev_priv->fsb_freq = 4266;
157 break;
158 case 0x012:
159 dev_priv->fsb_freq = 4800;
160 break;
161 case 0x014:
162 dev_priv->fsb_freq = 5333;
163 break;
164 case 0x016:
165 dev_priv->fsb_freq = 5866;
166 break;
167 case 0x018:
168 dev_priv->fsb_freq = 6400;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
172 csipll & 0x3ff);
173 dev_priv->fsb_freq = 0;
174 break;
175 }
176
177 if (dev_priv->fsb_freq == 3200) {
20e4d407 178 dev_priv->ips.c_m = 0;
c921aba8 179 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 180 dev_priv->ips.c_m = 1;
c921aba8 181 } else {
20e4d407 182 dev_priv->ips.c_m = 2;
c921aba8
DV		 183 }
184}
185
b445e3b0
ED		 186static const struct cxsr_latency cxsr_latency_table[] = {
187 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
188 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
189 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
190 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
191 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
192
193 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
194 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
195 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
196 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
197 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
198
199 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
200 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
201 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
202 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
203 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
204
205 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
206 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
207 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
208 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
209 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
210
211 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
212 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
213 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
214 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
215 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
216
217 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
218 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
219 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
220 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
221 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
222};
223
63c62275 224static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 225 int is_ddr3,
226 int fsb,
227 int mem)
228{
229 const struct cxsr_latency *latency;
230 int i;
231
232 if (fsb == 0 || mem == 0)
233 return NULL;
234
235 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
236 latency = &cxsr_latency_table[i];
237 if (is_desktop == latency->is_desktop &&
238 is_ddr3 == latency->is_ddr3 &&
239 fsb == latency->fsb_freq && mem == latency->mem_freq)
240 return latency;
241 }
242
243 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
244
245 return NULL;
246}
247
fc1ac8de
VS		 248static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
249{
250 u32 val;
251
252 mutex_lock(&dev_priv->rps.hw_lock);
253
254 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
255 if (enable)
256 val &= ~FORCE_DDR_HIGH_FREQ;
257 else
258 val |= FORCE_DDR_HIGH_FREQ;
259 val &= ~FORCE_DDR_LOW_FREQ;
260 val |= FORCE_DDR_FREQ_REQ_ACK;
261 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
262
263 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
264 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
265 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
266
267 mutex_unlock(&dev_priv->rps.hw_lock);
268}
269
cfb41411
VS		 270static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
271{
272 u32 val;
273
274 mutex_lock(&dev_priv->rps.hw_lock);
275
276 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
277 if (enable)
278 val |= DSP_MAXFIFO_PM5_ENABLE;
279 else
280 val &= ~DSP_MAXFIFO_PM5_ENABLE;
281 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
282
283 mutex_unlock(&dev_priv->rps.hw_lock);
284}
285
f4998963
VS		 286#define FW_WM(value, plane) \
287 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
288
5209b1f4 289void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 290{
5209b1f4
ID		 291 struct drm_device *dev = dev_priv->dev;
292 u32 val;
b445e3b0 293
666a4537 294 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 295 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 296 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 297 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 298 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
299 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 300 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 301 } else if (IS_PINEVIEW(dev)) {
302 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
303 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
304 I915_WRITE(DSPFW3, val);
a7a6c498 305 POSTING_READ(DSPFW3);
5209b1f4
ID		 306 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
307 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
308 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
309 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 310 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 311 } else if (IS_I915GM(dev)) {
312 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
313 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
314 I915_WRITE(INSTPM, val);
a7a6c498 315 POSTING_READ(INSTPM);
5209b1f4
ID		 316 } else {
317 return;
318 }
b445e3b0 319
5209b1f4
ID		 320 DRM_DEBUG_KMS("memory self-refresh is %s\n",
321 enable ? "enabled" : "disabled");
b445e3b0
ED		 322}
323
fc1ac8de 324
b445e3b0
ED		 325/*
326 * Latency for FIFO fetches is dependent on several factors:
327 * - memory configuration (speed, channels)
328 * - chipset
329 * - current MCH state
330 * It can be fairly high in some situations, so here we assume a fairly
331 * pessimal value. It's a tradeoff between extra memory fetches (if we
332 * set this value too high, the FIFO will fetch frequently to stay full)
333 * and power consumption (set it too low to save power and we might see
334 * FIFO underruns and display "flicker").
335 *
336 * A value of 5us seems to be a good balance; safe for very low end
337 * platforms but not overly aggressive on lower latency configs.
338 */
5aef6003 339static const int pessimal_latency_ns = 5000;
b445e3b0 340
b5004720
VS		 341#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
342 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
343
344static int vlv_get_fifo_size(struct drm_device *dev,
345 enum pipe pipe, int plane)
346{
347 struct drm_i915_private *dev_priv = dev->dev_private;
348 int sprite0_start, sprite1_start, size;
349
350 switch (pipe) {
351 uint32_t dsparb, dsparb2, dsparb3;
352 case PIPE_A:
353 dsparb = I915_READ(DSPARB);
354 dsparb2 = I915_READ(DSPARB2);
355 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
356 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
357 break;
358 case PIPE_B:
359 dsparb = I915_READ(DSPARB);
360 dsparb2 = I915_READ(DSPARB2);
361 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
362 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
363 break;
364 case PIPE_C:
365 dsparb2 = I915_READ(DSPARB2);
366 dsparb3 = I915_READ(DSPARB3);
367 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
368 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
369 break;
370 default:
371 return 0;
372 }
373
374 switch (plane) {
375 case 0:
376 size = sprite0_start;
377 break;
378 case 1:
379 size = sprite1_start - sprite0_start;
380 break;
381 case 2:
382 size = 512 - 1 - sprite1_start;
383 break;
384 default:
385 return 0;
386 }
387
388 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
389 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
390 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
391 size);
392
393 return size;
394}
395
1fa61106 396static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 397{
398 struct drm_i915_private *dev_priv = dev->dev_private;
399 uint32_t dsparb = I915_READ(DSPARB);
400 int size;
401
402 size = dsparb & 0x7f;
403 if (plane)
404 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
405
406 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
407 plane ? "B" : "A", size);
408
409 return size;
410}
411
feb56b93 412static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 413{
414 struct drm_i915_private *dev_priv = dev->dev_private;
415 uint32_t dsparb = I915_READ(DSPARB);
416 int size;
417
418 size = dsparb & 0x1ff;
419 if (plane)
420 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
421 size >>= 1; /* Convert to cachelines */
422
423 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
424 plane ? "B" : "A", size);
425
426 return size;
427}
428
1fa61106 429static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 430{
431 struct drm_i915_private *dev_priv = dev->dev_private;
432 uint32_t dsparb = I915_READ(DSPARB);
433 int size;
434
435 size = dsparb & 0x7f;
436 size >>= 2; /* Convert to cachelines */
437
438 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
439 plane ? "B" : "A",
440 size);
441
442 return size;
443}
444
b445e3b0
ED		 445/* Pineview has different values for various configs */
446static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 447 .fifo_size = PINEVIEW_DISPLAY_FIFO,
448 .max_wm = PINEVIEW_MAX_WM,
449 .default_wm = PINEVIEW_DFT_WM,
450 .guard_size = PINEVIEW_GUARD_WM,
451 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 452};
453static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 454 .fifo_size = PINEVIEW_DISPLAY_FIFO,
455 .max_wm = PINEVIEW_MAX_WM,
456 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
457 .guard_size = PINEVIEW_GUARD_WM,
458 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 459};
460static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 461 .fifo_size = PINEVIEW_CURSOR_FIFO,
462 .max_wm = PINEVIEW_CURSOR_MAX_WM,
463 .default_wm = PINEVIEW_CURSOR_DFT_WM,
464 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
465 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 466};
467static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 468 .fifo_size = PINEVIEW_CURSOR_FIFO,
469 .max_wm = PINEVIEW_CURSOR_MAX_WM,
470 .default_wm = PINEVIEW_CURSOR_DFT_WM,
471 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
472 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 473};
474static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 475 .fifo_size = G4X_FIFO_SIZE,
476 .max_wm = G4X_MAX_WM,
477 .default_wm = G4X_MAX_WM,
478 .guard_size = 2,
479 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 480};
481static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 482 .fifo_size = I965_CURSOR_FIFO,
483 .max_wm = I965_CURSOR_MAX_WM,
484 .default_wm = I965_CURSOR_DFT_WM,
485 .guard_size = 2,
486 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 487};
488static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 489 .fifo_size = VALLEYVIEW_FIFO_SIZE,
490 .max_wm = VALLEYVIEW_MAX_WM,
491 .default_wm = VALLEYVIEW_MAX_WM,
492 .guard_size = 2,
493 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 494};
495static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 496 .fifo_size = I965_CURSOR_FIFO,
497 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
498 .default_wm = I965_CURSOR_DFT_WM,
499 .guard_size = 2,
500 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 501};
502static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 503 .fifo_size = I965_CURSOR_FIFO,
504 .max_wm = I965_CURSOR_MAX_WM,
505 .default_wm = I965_CURSOR_DFT_WM,
506 .guard_size = 2,
507 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 508};
509static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 510 .fifo_size = I945_FIFO_SIZE,
511 .max_wm = I915_MAX_WM,
512 .default_wm = 1,
513 .guard_size = 2,
514 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 515};
516static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 517 .fifo_size = I915_FIFO_SIZE,
518 .max_wm = I915_MAX_WM,
519 .default_wm = 1,
520 .guard_size = 2,
521 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 522};
9d539105 523static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 524 .fifo_size = I855GM_FIFO_SIZE,
525 .max_wm = I915_MAX_WM,
526 .default_wm = 1,
527 .guard_size = 2,
528 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 529};
9d539105
VS		 530static const struct intel_watermark_params i830_bc_wm_info = {
531 .fifo_size = I855GM_FIFO_SIZE,
532 .max_wm = I915_MAX_WM/2,
533 .default_wm = 1,
534 .guard_size = 2,
535 .cacheline_size = I830_FIFO_LINE_SIZE,
536};
feb56b93 537static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 538 .fifo_size = I830_FIFO_SIZE,
539 .max_wm = I915_MAX_WM,
540 .default_wm = 1,
541 .guard_size = 2,
542 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 543};
544
b445e3b0
ED		 545/**
546 * intel_calculate_wm - calculate watermark level
547 * @clock_in_khz: pixel clock
548 * @wm: chip FIFO params
549 * @pixel_size: display pixel size
550 * @latency_ns: memory latency for the platform
551 *
552 * Calculate the watermark level (the level at which the display plane will
553 * start fetching from memory again). Each chip has a different display
554 * FIFO size and allocation, so the caller needs to figure that out and pass
555 * in the correct intel_watermark_params structure.
556 *
557 * As the pixel clock runs, the FIFO will be drained at a rate that depends
558 * on the pixel size. When it reaches the watermark level, it'll start
559 * fetching FIFO line sized based chunks from memory until the FIFO fills
560 * past the watermark point. If the FIFO drains completely, a FIFO underrun
561 * will occur, and a display engine hang could result.
562 */
563static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
564 const struct intel_watermark_params *wm,
565 int fifo_size,
566 int pixel_size,
567 unsigned long latency_ns)
568{
569 long entries_required, wm_size;
570
571 /*
572 * Note: we need to make sure we don't overflow for various clock &
573 * latency values.
574 * clocks go from a few thousand to several hundred thousand.
575 * latency is usually a few thousand
576 */
577 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
578 1000;
579 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
580
581 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
582
583 wm_size = fifo_size - (entries_required + wm->guard_size);
584
585 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
586
587 /* Don't promote wm_size to unsigned... */
588 if (wm_size > (long)wm->max_wm)
589 wm_size = wm->max_wm;
590 if (wm_size <= 0)
591 wm_size = wm->default_wm;
d6feb196
VS		 592
593 /*
594 * Bspec seems to indicate that the value shouldn't be lower than
595 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
596 * Lets go for 8 which is the burst size since certain platforms
597 * already use a hardcoded 8 (which is what the spec says should be
598 * done).
599 */
600 if (wm_size <= 8)
601 wm_size = 8;
602
b445e3b0
ED		 603 return wm_size;
604}
605
606static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
607{
608 struct drm_crtc *crtc, *enabled = NULL;
609
70e1e0ec 610 for_each_crtc(dev, crtc) {
3490ea5d 611 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 612 if (enabled)
613 return NULL;
614 enabled = crtc;
615 }
616 }
617
618 return enabled;
619}
620
46ba614c 621static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 622{
46ba614c 623 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 624 struct drm_i915_private *dev_priv = dev->dev_private;
625 struct drm_crtc *crtc;
626 const struct cxsr_latency *latency;
627 u32 reg;
628 unsigned long wm;
629
630 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
631 dev_priv->fsb_freq, dev_priv->mem_freq);
632 if (!latency) {
633 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 634 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 635 return;
636 }
637
638 crtc = single_enabled_crtc(dev);
639 if (crtc) {
7c5f93b0 640 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
59bea882 641 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
7c5f93b0 642 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 643
644 /* Display SR */
645 wm = intel_calculate_wm(clock, &pineview_display_wm,
646 pineview_display_wm.fifo_size,
647 pixel_size, latency->display_sr);
648 reg = I915_READ(DSPFW1);
649 reg &= ~DSPFW_SR_MASK;
f4998963 650 reg |= FW_WM(wm, SR);
b445e3b0
ED		 651 I915_WRITE(DSPFW1, reg);
652 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
653
654 /* cursor SR */
655 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
656 pineview_display_wm.fifo_size,
657 pixel_size, latency->cursor_sr);
658 reg = I915_READ(DSPFW3);
659 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 660 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 661 I915_WRITE(DSPFW3, reg);
662
663 /* Display HPLL off SR */
664 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
665 pineview_display_hplloff_wm.fifo_size,
666 pixel_size, latency->display_hpll_disable);
667 reg = I915_READ(DSPFW3);
668 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 669 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 670 I915_WRITE(DSPFW3, reg);
671
672 /* cursor HPLL off SR */
673 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
674 pineview_display_hplloff_wm.fifo_size,
675 pixel_size, latency->cursor_hpll_disable);
676 reg = I915_READ(DSPFW3);
677 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 678 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 679 I915_WRITE(DSPFW3, reg);
680 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
681
5209b1f4 682 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 683 } else {
5209b1f4 684 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 685 }
686}
687
688static bool g4x_compute_wm0(struct drm_device *dev,
689 int plane,
690 const struct intel_watermark_params *display,
691 int display_latency_ns,
692 const struct intel_watermark_params *cursor,
693 int cursor_latency_ns,
694 int *plane_wm,
695 int *cursor_wm)
696{
697 struct drm_crtc *crtc;
4fe8590a 698 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 699 int htotal, hdisplay, clock, pixel_size;
700 int line_time_us, line_count;
701 int entries, tlb_miss;
702
703 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 704 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 705 *cursor_wm = cursor->guard_size;
706 *plane_wm = display->guard_size;
707 return false;
708 }
709
6e3c9717 710 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 711 clock = adjusted_mode->crtc_clock;
fec8cba3 712 htotal = adjusted_mode->crtc_htotal;
6e3c9717 713 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 714 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 715
716 /* Use the small buffer method to calculate plane watermark */
717 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
718 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
719 if (tlb_miss > 0)
720 entries += tlb_miss;
721 entries = DIV_ROUND_UP(entries, display->cacheline_size);
722 *plane_wm = entries + display->guard_size;
723 if (*plane_wm > (int)display->max_wm)
724 *plane_wm = display->max_wm;
725
726 /* Use the large buffer method to calculate cursor watermark */
922044c9 727 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 728 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 729 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 730 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
731 if (tlb_miss > 0)
732 entries += tlb_miss;
733 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
734 *cursor_wm = entries + cursor->guard_size;
735 if (*cursor_wm > (int)cursor->max_wm)
736 *cursor_wm = (int)cursor->max_wm;
737
738 return true;
739}
740
741/*
742 * Check the wm result.
743 *
744 * If any calculated watermark values is larger than the maximum value that
745 * can be programmed into the associated watermark register, that watermark
746 * must be disabled.
747 */
748static bool g4x_check_srwm(struct drm_device *dev,
749 int display_wm, int cursor_wm,
750 const struct intel_watermark_params *display,
751 const struct intel_watermark_params *cursor)
752{
753 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
754 display_wm, cursor_wm);
755
756 if (display_wm > display->max_wm) {
757 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
758 display_wm, display->max_wm);
759 return false;
760 }
761
762 if (cursor_wm > cursor->max_wm) {
763 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
764 cursor_wm, cursor->max_wm);
765 return false;
766 }
767
768 if (!(display_wm || cursor_wm)) {
769 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
770 return false;
771 }
772
773 return true;
774}
775
776static bool g4x_compute_srwm(struct drm_device *dev,
777 int plane,
778 int latency_ns,
779 const struct intel_watermark_params *display,
780 const struct intel_watermark_params *cursor,
781 int *display_wm, int *cursor_wm)
782{
783 struct drm_crtc *crtc;
4fe8590a 784 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 785 int hdisplay, htotal, pixel_size, clock;
786 unsigned long line_time_us;
787 int line_count, line_size;
788 int small, large;
789 int entries;
790
791 if (!latency_ns) {
792 *display_wm = *cursor_wm = 0;
793 return false;
794 }
795
796 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 797 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 798 clock = adjusted_mode->crtc_clock;
fec8cba3 799 htotal = adjusted_mode->crtc_htotal;
6e3c9717 800 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 801 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 802
922044c9 803 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 804 line_count = (latency_ns / line_time_us + 1000) / 1000;
805 line_size = hdisplay * pixel_size;
806
807 /* Use the minimum of the small and large buffer method for primary */
808 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
809 large = line_count * line_size;
810
811 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
812 *display_wm = entries + display->guard_size;
813
814 /* calculate the self-refresh watermark for display cursor */
3dd512fb 815 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 816 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
817 *cursor_wm = entries + cursor->guard_size;
818
819 return g4x_check_srwm(dev,
820 *display_wm, *cursor_wm,
821 display, cursor);
822}
823
15665979
VS		 824#define FW_WM_VLV(value, plane) \
825 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
826
0018fda1
VS		 827static void vlv_write_wm_values(struct intel_crtc *crtc,
828 const struct vlv_wm_values *wm)
829{
830 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
831 enum pipe pipe = crtc->pipe;
832
833 I915_WRITE(VLV_DDL(pipe),
834 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
835 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
836 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
837 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
838
ae80152d 839 I915_WRITE(DSPFW1,
15665979
VS		 840 FW_WM(wm->sr.plane, SR) |
841 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
842 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
843 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 844 I915_WRITE(DSPFW2,
15665979
VS		 845 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
846 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
847 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 848 I915_WRITE(DSPFW3,
15665979 849 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 850
851 if (IS_CHERRYVIEW(dev_priv)) {
852 I915_WRITE(DSPFW7_CHV,
15665979
VS		 853 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
854 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 855 I915_WRITE(DSPFW8_CHV,
15665979
VS		 856 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
857 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 858 I915_WRITE(DSPFW9_CHV,
15665979
VS		 859 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
860 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 861 I915_WRITE(DSPHOWM,
15665979
VS		 862 FW_WM(wm->sr.plane >> 9, SR_HI) |
863 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
864 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
865 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
866 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
867 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
868 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
869 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
870 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
871 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 872 } else {
873 I915_WRITE(DSPFW7,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPHOWM,
15665979
VS		 877 FW_WM(wm->sr.plane >> 9, SR_HI) |
878 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
879 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
880 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
881 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
882 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
883 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 884 }
885
2cb389b7
VS		 886 /* zero (unused) WM1 watermarks */
887 I915_WRITE(DSPFW4, 0);
888 I915_WRITE(DSPFW5, 0);
889 I915_WRITE(DSPFW6, 0);
890 I915_WRITE(DSPHOWM1, 0);
891
ae80152d 892 POSTING_READ(DSPFW1);
0018fda1
VS		 893}
894
15665979
VS		 895#undef FW_WM_VLV
896
6eb1a681
VS		 897enum vlv_wm_level {
898 VLV_WM_LEVEL_PM2,
899 VLV_WM_LEVEL_PM5,
900 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 901};
902
262cd2e1
VS		 903/* latency must be in 0.1us units. */
904static unsigned int vlv_wm_method2(unsigned int pixel_rate,
905 unsigned int pipe_htotal,
906 unsigned int horiz_pixels,
907 unsigned int bytes_per_pixel,
908 unsigned int latency)
909{
910 unsigned int ret;
911
912 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
913 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
914 ret = DIV_ROUND_UP(ret, 64);
915
916 return ret;
917}
918
919static void vlv_setup_wm_latency(struct drm_device *dev)
920{
921 struct drm_i915_private *dev_priv = dev->dev_private;
922
923 /* all latencies in usec */
924 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
925
58590c14
VS		 926 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
927
262cd2e1
VS		 928 if (IS_CHERRYVIEW(dev_priv)) {
929 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
930 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 931
932 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 933 }
934}
935
936static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
937 struct intel_crtc *crtc,
938 const struct intel_plane_state *state,
939 int level)
940{
941 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
942 int clock, htotal, pixel_size, width, wm;
943
944 if (dev_priv->wm.pri_latency[level] == 0)
945 return USHRT_MAX;
946
947 if (!state->visible)
948 return 0;
949
950 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
951 clock = crtc->config->base.adjusted_mode.crtc_clock;
952 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
953 width = crtc->config->pipe_src_w;
954 if (WARN_ON(htotal == 0))
955 htotal = 1;
956
957 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
958 /*
959 * FIXME the formula gives values that are
960 * too big for the cursor FIFO, and hence we
961 * would never be able to use cursors. For
962 * now just hardcode the watermark.
963 */
964 wm = 63;
965 } else {
966 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
967 dev_priv->wm.pri_latency[level] * 10);
968 }
969
970 return min_t(int, wm, USHRT_MAX);
971}
972
54f1b6e1
VS		 973static void vlv_compute_fifo(struct intel_crtc *crtc)
974{
975 struct drm_device *dev = crtc->base.dev;
976 struct vlv_wm_state *wm_state = &crtc->wm_state;
977 struct intel_plane *plane;
978 unsigned int total_rate = 0;
979 const int fifo_size = 512 - 1;
980 int fifo_extra, fifo_left = fifo_size;
981
982 for_each_intel_plane_on_crtc(dev, crtc, plane) {
983 struct intel_plane_state *state =
984 to_intel_plane_state(plane->base.state);
985
986 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
987 continue;
988
989 if (state->visible) {
990 wm_state->num_active_planes++;
991 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
992 }
993 }
994
995 for_each_intel_plane_on_crtc(dev, crtc, plane) {
996 struct intel_plane_state *state =
997 to_intel_plane_state(plane->base.state);
998 unsigned int rate;
999
1000 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1001 plane->wm.fifo_size = 63;
1002 continue;
1003 }
1004
1005 if (!state->visible) {
1006 plane->wm.fifo_size = 0;
1007 continue;
1008 }
1009
1010 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1011 plane->wm.fifo_size = fifo_size * rate / total_rate;
1012 fifo_left -= plane->wm.fifo_size;
1013 }
1014
1015 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1016
1017 /* spread the remainder evenly */
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 int plane_extra;
1020
1021 if (fifo_left == 0)
1022 break;
1023
1024 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1025 continue;
1026
1027 /* give it all to the first plane if none are active */
1028 if (plane->wm.fifo_size == 0 &&
1029 wm_state->num_active_planes)
1030 continue;
1031
1032 plane_extra = min(fifo_extra, fifo_left);
1033 plane->wm.fifo_size += plane_extra;
1034 fifo_left -= plane_extra;
1035 }
1036
1037 WARN_ON(fifo_left != 0);
1038}
1039
262cd2e1
VS		 1040static void vlv_invert_wms(struct intel_crtc *crtc)
1041{
1042 struct vlv_wm_state *wm_state = &crtc->wm_state;
1043 int level;
1044
1045 for (level = 0; level < wm_state->num_levels; level++) {
1046 struct drm_device *dev = crtc->base.dev;
1047 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1048 struct intel_plane *plane;
1049
1050 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1051 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1052
1053 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1054 switch (plane->base.type) {
1055 int sprite;
1056 case DRM_PLANE_TYPE_CURSOR:
1057 wm_state->wm[level].cursor = plane->wm.fifo_size -
1058 wm_state->wm[level].cursor;
1059 break;
1060 case DRM_PLANE_TYPE_PRIMARY:
1061 wm_state->wm[level].primary = plane->wm.fifo_size -
1062 wm_state->wm[level].primary;
1063 break;
1064 case DRM_PLANE_TYPE_OVERLAY:
1065 sprite = plane->plane;
1066 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1067 wm_state->wm[level].sprite[sprite];
1068 break;
1069 }
1070 }
1071 }
1072}
1073
26e1fe4f 1074static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1075{
1076 struct drm_device *dev = crtc->base.dev;
1077 struct vlv_wm_state *wm_state = &crtc->wm_state;
1078 struct intel_plane *plane;
1079 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1080 int level;
1081
1082 memset(wm_state, 0, sizeof(*wm_state));
1083
852eb00d 1084 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1085 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1086
1087 wm_state->num_active_planes = 0;
262cd2e1 1088
54f1b6e1 1089 vlv_compute_fifo(crtc);
262cd2e1
VS		 1090
1091 if (wm_state->num_active_planes != 1)
1092 wm_state->cxsr = false;
1093
1094 if (wm_state->cxsr) {
1095 for (level = 0; level < wm_state->num_levels; level++) {
1096 wm_state->sr[level].plane = sr_fifo_size;
1097 wm_state->sr[level].cursor = 63;
1098 }
1099 }
1100
1101 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1102 struct intel_plane_state *state =
1103 to_intel_plane_state(plane->base.state);
1104
1105 if (!state->visible)
1106 continue;
1107
1108 /* normal watermarks */
1109 for (level = 0; level < wm_state->num_levels; level++) {
1110 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1111 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1112
1113 /* hack */
1114 if (WARN_ON(level == 0 && wm > max_wm))
1115 wm = max_wm;
1116
1117 if (wm > plane->wm.fifo_size)
1118 break;
1119
1120 switch (plane->base.type) {
1121 int sprite;
1122 case DRM_PLANE_TYPE_CURSOR:
1123 wm_state->wm[level].cursor = wm;
1124 break;
1125 case DRM_PLANE_TYPE_PRIMARY:
1126 wm_state->wm[level].primary = wm;
1127 break;
1128 case DRM_PLANE_TYPE_OVERLAY:
1129 sprite = plane->plane;
1130 wm_state->wm[level].sprite[sprite] = wm;
1131 break;
1132 }
1133 }
1134
1135 wm_state->num_levels = level;
1136
1137 if (!wm_state->cxsr)
1138 continue;
1139
1140 /* maxfifo watermarks */
1141 switch (plane->base.type) {
1142 int sprite, level;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 for (level = 0; level < wm_state->num_levels; level++)
1145 wm_state->sr[level].cursor =
5a37ed0a 1146 wm_state->wm[level].cursor;
262cd2e1
VS		 1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 for (level = 0; level < wm_state->num_levels; level++)
1150 wm_state->sr[level].plane =
1151 min(wm_state->sr[level].plane,
1152 wm_state->wm[level].primary);
1153 break;
1154 case DRM_PLANE_TYPE_OVERLAY:
1155 sprite = plane->plane;
1156 for (level = 0; level < wm_state->num_levels; level++)
1157 wm_state->sr[level].plane =
1158 min(wm_state->sr[level].plane,
1159 wm_state->wm[level].sprite[sprite]);
1160 break;
1161 }
1162 }
1163
1164 /* clear any (partially) filled invalid levels */
58590c14 1165 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1166 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1167 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1168 }
1169
1170 vlv_invert_wms(crtc);
1171}
1172
54f1b6e1
VS		 1173#define VLV_FIFO(plane, value) \
1174 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1175
1176static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1177{
1178 struct drm_device *dev = crtc->base.dev;
1179 struct drm_i915_private *dev_priv = to_i915(dev);
1180 struct intel_plane *plane;
1181 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1182
1183 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1184 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1185 WARN_ON(plane->wm.fifo_size != 63);
1186 continue;
1187 }
1188
1189 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1190 sprite0_start = plane->wm.fifo_size;
1191 else if (plane->plane == 0)
1192 sprite1_start = sprite0_start + plane->wm.fifo_size;
1193 else
1194 fifo_size = sprite1_start + plane->wm.fifo_size;
1195 }
1196
1197 WARN_ON(fifo_size != 512 - 1);
1198
1199 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1200 pipe_name(crtc->pipe), sprite0_start,
1201 sprite1_start, fifo_size);
1202
1203 switch (crtc->pipe) {
1204 uint32_t dsparb, dsparb2, dsparb3;
1205 case PIPE_A:
1206 dsparb = I915_READ(DSPARB);
1207 dsparb2 = I915_READ(DSPARB2);
1208
1209 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1210 VLV_FIFO(SPRITEB, 0xff));
1211 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1212 VLV_FIFO(SPRITEB, sprite1_start));
1213
1214 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1215 VLV_FIFO(SPRITEB_HI, 0x1));
1216 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1217 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1218
1219 I915_WRITE(DSPARB, dsparb);
1220 I915_WRITE(DSPARB2, dsparb2);
1221 break;
1222 case PIPE_B:
1223 dsparb = I915_READ(DSPARB);
1224 dsparb2 = I915_READ(DSPARB2);
1225
1226 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1227 VLV_FIFO(SPRITED, 0xff));
1228 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1229 VLV_FIFO(SPRITED, sprite1_start));
1230
1231 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1232 VLV_FIFO(SPRITED_HI, 0xff));
1233 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1234 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1235
1236 I915_WRITE(DSPARB, dsparb);
1237 I915_WRITE(DSPARB2, dsparb2);
1238 break;
1239 case PIPE_C:
1240 dsparb3 = I915_READ(DSPARB3);
1241 dsparb2 = I915_READ(DSPARB2);
1242
1243 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1244 VLV_FIFO(SPRITEF, 0xff));
1245 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1246 VLV_FIFO(SPRITEF, sprite1_start));
1247
1248 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1249 VLV_FIFO(SPRITEF_HI, 0xff));
1250 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1251 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1252
1253 I915_WRITE(DSPARB3, dsparb3);
1254 I915_WRITE(DSPARB2, dsparb2);
1255 break;
1256 default:
1257 break;
1258 }
1259}
1260
1261#undef VLV_FIFO
1262
262cd2e1
VS		 1263static void vlv_merge_wm(struct drm_device *dev,
1264 struct vlv_wm_values *wm)
1265{
1266 struct intel_crtc *crtc;
1267 int num_active_crtcs = 0;
1268
58590c14 1269 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1270 wm->cxsr = true;
1271
1272 for_each_intel_crtc(dev, crtc) {
1273 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1274
1275 if (!crtc->active)
1276 continue;
1277
1278 if (!wm_state->cxsr)
1279 wm->cxsr = false;
1280
1281 num_active_crtcs++;
1282 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1283 }
1284
1285 if (num_active_crtcs != 1)
1286 wm->cxsr = false;
1287
6f9c784b
VS		 1288 if (num_active_crtcs > 1)
1289 wm->level = VLV_WM_LEVEL_PM2;
1290
262cd2e1
VS		 1291 for_each_intel_crtc(dev, crtc) {
1292 struct vlv_wm_state *wm_state = &crtc->wm_state;
1293 enum pipe pipe = crtc->pipe;
1294
1295 if (!crtc->active)
1296 continue;
1297
1298 wm->pipe[pipe] = wm_state->wm[wm->level];
1299 if (wm->cxsr)
1300 wm->sr = wm_state->sr[wm->level];
1301
1302 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1303 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1304 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1305 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1306 }
1307}
1308
1309static void vlv_update_wm(struct drm_crtc *crtc)
1310{
1311 struct drm_device *dev = crtc->dev;
1312 struct drm_i915_private *dev_priv = dev->dev_private;
1313 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1314 enum pipe pipe = intel_crtc->pipe;
1315 struct vlv_wm_values wm = {};
1316
26e1fe4f 1317 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1318 vlv_merge_wm(dev, &wm);
1319
54f1b6e1
VS		 1320 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1321 /* FIXME should be part of crtc atomic commit */
1322 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1323 return;
54f1b6e1 1324 }
262cd2e1
VS		 1325
1326 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1327 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1328 chv_set_memory_dvfs(dev_priv, false);
1329
1330 if (wm.level < VLV_WM_LEVEL_PM5 &&
1331 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1332 chv_set_memory_pm5(dev_priv, false);
1333
852eb00d 1334 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1335 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1336
54f1b6e1
VS		 1337 /* FIXME should be part of crtc atomic commit */
1338 vlv_pipe_set_fifo_size(intel_crtc);
1339
262cd2e1
VS		 1340 vlv_write_wm_values(intel_crtc, &wm);
1341
1342 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1343 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1344 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1345 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1346 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1347
852eb00d 1348 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1349 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1350
1351 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, true);
1354
1355 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1356 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1357 chv_set_memory_dvfs(dev_priv, true);
1358
1359 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1360}
1361
ae80152d
VS		 1362#define single_plane_enabled(mask) is_power_of_2(mask)
1363
46ba614c 1364static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1365{
46ba614c 1366 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1367 static const int sr_latency_ns = 12000;
1368 struct drm_i915_private *dev_priv = dev->dev_private;
1369 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1370 int plane_sr, cursor_sr;
1371 unsigned int enabled = 0;
9858425c 1372 bool cxsr_enabled;
b445e3b0 1373
51cea1f4 1374 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1375 &g4x_wm_info, pessimal_latency_ns,
1376 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1377 &planea_wm, &cursora_wm))
51cea1f4 1378 enabled |= 1 << PIPE_A;
b445e3b0 1379
51cea1f4 1380 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1381 &g4x_wm_info, pessimal_latency_ns,
1382 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1383 &planeb_wm, &cursorb_wm))
51cea1f4 1384 enabled |= 1 << PIPE_B;
b445e3b0 1385
b445e3b0
ED		 1386 if (single_plane_enabled(enabled) &&
1387 g4x_compute_srwm(dev, ffs(enabled) - 1,
1388 sr_latency_ns,
1389 &g4x_wm_info,
1390 &g4x_cursor_wm_info,
52bd02d8 1391 &plane_sr, &cursor_sr)) {
9858425c 1392 cxsr_enabled = true;
52bd02d8 1393 } else {
9858425c 1394 cxsr_enabled = false;
5209b1f4 1395 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1396 plane_sr = cursor_sr = 0;
1397 }
b445e3b0 1398
a5043453
VS		 1399 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1400 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1401 planea_wm, cursora_wm,
1402 planeb_wm, cursorb_wm,
1403 plane_sr, cursor_sr);
1404
1405 I915_WRITE(DSPFW1,
f4998963
VS		 1406 FW_WM(plane_sr, SR) |
1407 FW_WM(cursorb_wm, CURSORB) |
1408 FW_WM(planeb_wm, PLANEB) |
1409 FW_WM(planea_wm, PLANEA));
b445e3b0 1410 I915_WRITE(DSPFW2,
8c919b28 1411 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1412 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1413 /* HPLL off in SR has some issues on G4x... disable it */
1414 I915_WRITE(DSPFW3,
8c919b28 1415 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1416 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1417
1418 if (cxsr_enabled)
1419 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1420}
1421
46ba614c 1422static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1423{
46ba614c 1424 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1425 struct drm_i915_private *dev_priv = dev->dev_private;
1426 struct drm_crtc *crtc;
1427 int srwm = 1;
1428 int cursor_sr = 16;
9858425c 1429 bool cxsr_enabled;
b445e3b0
ED		 1430
1431 /* Calc sr entries for one plane configs */
1432 crtc = single_enabled_crtc(dev);
1433 if (crtc) {
1434 /* self-refresh has much higher latency */
1435 static const int sr_latency_ns = 12000;
124abe07 1436 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1437 int clock = adjusted_mode->crtc_clock;
fec8cba3 1438 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1439 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1440 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1441 unsigned long line_time_us;
1442 int entries;
1443
922044c9 1444 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1445
1446 /* Use ns/us then divide to preserve precision */
1447 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1448 pixel_size * hdisplay;
1449 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1450 srwm = I965_FIFO_SIZE - entries;
1451 if (srwm < 0)
1452 srwm = 1;
1453 srwm &= 0x1ff;
1454 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1455 entries, srwm);
1456
1457 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1458 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1459 entries = DIV_ROUND_UP(entries,
1460 i965_cursor_wm_info.cacheline_size);
1461 cursor_sr = i965_cursor_wm_info.fifo_size -
1462 (entries + i965_cursor_wm_info.guard_size);
1463
1464 if (cursor_sr > i965_cursor_wm_info.max_wm)
1465 cursor_sr = i965_cursor_wm_info.max_wm;
1466
1467 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1468 "cursor %d\n", srwm, cursor_sr);
1469
9858425c 1470 cxsr_enabled = true;
b445e3b0 1471 } else {
9858425c 1472 cxsr_enabled = false;
b445e3b0 1473 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1474 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1475 }
1476
1477 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1478 srwm);
1479
1480 /* 965 has limitations... */
f4998963
VS		 1481 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1482 FW_WM(8, CURSORB) |
1483 FW_WM(8, PLANEB) |
1484 FW_WM(8, PLANEA));
1485 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1486 FW_WM(8, PLANEC_OLD));
b445e3b0 1487 /* update cursor SR watermark */
f4998963 1488 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1489
1490 if (cxsr_enabled)
1491 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1492}
1493
f4998963
VS		 1494#undef FW_WM
1495
46ba614c 1496static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1497{
46ba614c 1498 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1499 struct drm_i915_private *dev_priv = dev->dev_private;
1500 const struct intel_watermark_params *wm_info;
1501 uint32_t fwater_lo;
1502 uint32_t fwater_hi;
1503 int cwm, srwm = 1;
1504 int fifo_size;
1505 int planea_wm, planeb_wm;
1506 struct drm_crtc *crtc, *enabled = NULL;
1507
1508 if (IS_I945GM(dev))
1509 wm_info = &i945_wm_info;
1510 else if (!IS_GEN2(dev))
1511 wm_info = &i915_wm_info;
1512 else
9d539105 1513 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1514
1515 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1516 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1517 if (intel_crtc_active(crtc)) {
241bfc38 1518 const struct drm_display_mode *adjusted_mode;
59bea882 1519 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1520 if (IS_GEN2(dev))
1521 cpp = 4;
1522
6e3c9717 1523 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1524 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1525 wm_info, fifo_size, cpp,
5aef6003 1526 pessimal_latency_ns);
b445e3b0 1527 enabled = crtc;
9d539105 1528 } else {
b445e3b0 1529 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1530 if (planea_wm > (long)wm_info->max_wm)
1531 planea_wm = wm_info->max_wm;
1532 }
1533
1534 if (IS_GEN2(dev))
1535 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1536
1537 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1538 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1539 if (intel_crtc_active(crtc)) {
241bfc38 1540 const struct drm_display_mode *adjusted_mode;
59bea882 1541 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1542 if (IS_GEN2(dev))
1543 cpp = 4;
1544
6e3c9717 1545 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1546 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0
ED		 1549 if (enabled == NULL)
1550 enabled = crtc;
1551 else
1552 enabled = NULL;
9d539105 1553 } else {
b445e3b0 1554 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1555 if (planeb_wm > (long)wm_info->max_wm)
1556 planeb_wm = wm_info->max_wm;
1557 }
b445e3b0
ED		 1558
1559 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1560
2ab1bc9d 1561 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1562 struct drm_i915_gem_object *obj;
2ab1bc9d 1563
59bea882 1564 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1565
1566 /* self-refresh seems busted with untiled */
2ff8fde1 1567 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1568 enabled = NULL;
1569 }
1570
b445e3b0
ED		 1571 /*
1572 * Overlay gets an aggressive default since video jitter is bad.
1573 */
1574 cwm = 2;
1575
1576 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1577 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1578
1579 /* Calc sr entries for one plane configs */
1580 if (HAS_FW_BLC(dev) && enabled) {
1581 /* self-refresh has much higher latency */
1582 static const int sr_latency_ns = 6000;
124abe07 1583 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1584 int clock = adjusted_mode->crtc_clock;
fec8cba3 1585 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1586 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1587 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1588 unsigned long line_time_us;
1589 int entries;
1590
922044c9 1591 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1592
1593 /* Use ns/us then divide to preserve precision */
1594 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1595 pixel_size * hdisplay;
1596 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1597 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1598 srwm = wm_info->fifo_size - entries;
1599 if (srwm < 0)
1600 srwm = 1;
1601
1602 if (IS_I945G(dev) || IS_I945GM(dev))
1603 I915_WRITE(FW_BLC_SELF,
1604 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1605 else if (IS_I915GM(dev))
1606 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1607 }
1608
1609 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1610 planea_wm, planeb_wm, cwm, srwm);
1611
1612 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1613 fwater_hi = (cwm & 0x1f);
1614
1615 /* Set request length to 8 cachelines per fetch */
1616 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1617 fwater_hi = fwater_hi | (1 << 8);
1618
1619 I915_WRITE(FW_BLC, fwater_lo);
1620 I915_WRITE(FW_BLC2, fwater_hi);
1621
5209b1f4
ID		 1622 if (enabled)
1623 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1624}
1625
feb56b93 1626static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1627{
46ba614c 1628 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1629 struct drm_i915_private *dev_priv = dev->dev_private;
1630 struct drm_crtc *crtc;
241bfc38 1631 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1632 uint32_t fwater_lo;
1633 int planea_wm;
1634
1635 crtc = single_enabled_crtc(dev);
1636 if (crtc == NULL)
1637 return;
1638
6e3c9717 1639 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1640 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1641 &i845_wm_info,
b445e3b0 1642 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1643 4, pessimal_latency_ns);
b445e3b0
ED		 1644 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1645 fwater_lo |= (3<<8) | planea_wm;
1646
1647 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1648
1649 I915_WRITE(FW_BLC, fwater_lo);
1650}
1651
8cfb3407 1652uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1653{
fd4daa9c 1654 uint32_t pixel_rate;
801bcfff 1655
8cfb3407 1656 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1657
1658 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1659 * adjust the pixel_rate here. */
1660
8cfb3407 1661 if (pipe_config->pch_pfit.enabled) {
801bcfff 1662 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1663 uint32_t pfit_size = pipe_config->pch_pfit.size;
1664
1665 pipe_w = pipe_config->pipe_src_w;
1666 pipe_h = pipe_config->pipe_src_h;
801bcfff 1667
801bcfff
PZ		 1668 pfit_w = (pfit_size >> 16) & 0xFFFF;
1669 pfit_h = pfit_size & 0xFFFF;
1670 if (pipe_w < pfit_w)
1671 pipe_w = pfit_w;
1672 if (pipe_h < pfit_h)
1673 pipe_h = pfit_h;
1674
1675 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1676 pfit_w * pfit_h);
1677 }
1678
1679 return pixel_rate;
1680}
1681
37126462 1682/* latency must be in 0.1us units. */
23297044 1683static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1684 uint32_t latency)
1685{
1686 uint64_t ret;
1687
3312ba65
VS		 1688 if (WARN(latency == 0, "Latency value missing\n"))
1689 return UINT_MAX;
1690
801bcfff
PZ		 1691 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1692 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1693
1694 return ret;
1695}
1696
37126462 1697/* latency must be in 0.1us units. */
23297044 1698static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1699 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1700 uint32_t latency)
1701{
1702 uint32_t ret;
1703
3312ba65
VS		 1704 if (WARN(latency == 0, "Latency value missing\n"))
1705 return UINT_MAX;
1706
801bcfff
PZ		 1707 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1708 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1709 ret = DIV_ROUND_UP(ret, 64) + 2;
1710 return ret;
1711}
1712
23297044 1713static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1714 uint8_t bytes_per_pixel)
1715{
1716 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1717}
1718
820c1980 1719struct ilk_wm_maximums {
cca32e9a
PZ		 1720 uint16_t pri;
1721 uint16_t spr;
1722 uint16_t cur;
1723 uint16_t fbc;
1724};
1725
37126462
VS		 1726/*
1727 * For both WM_PIPE and WM_LP.
1728 * mem_value must be in 0.1us units.
1729 */
7221fc33 1730static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1731 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1732 uint32_t mem_value,
1733 bool is_lp)
801bcfff 1734{
43d59eda 1735 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
cca32e9a
PZ		 1736 uint32_t method1, method2;
1737
7221fc33 1738 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1739 return 0;
1740
7221fc33 1741 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
cca32e9a
PZ		 1742
1743 if (!is_lp)
1744 return method1;
1745
7221fc33
MR		 1746 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1747 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1748 drm_rect_width(&pstate->dst),
1749 bpp,
cca32e9a
PZ		 1750 mem_value);
1751
1752 return min(method1, method2);
801bcfff
PZ		 1753}
1754
37126462
VS		 1755/*
1756 * For both WM_PIPE and WM_LP.
1757 * mem_value must be in 0.1us units.
1758 */
7221fc33 1759static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1760 const struct intel_plane_state *pstate,
801bcfff
PZ		 1761 uint32_t mem_value)
1762{
43d59eda 1763 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
801bcfff
PZ		 1764 uint32_t method1, method2;
1765
7221fc33 1766 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1767 return 0;
1768
7221fc33
MR		 1769 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), bpp, mem_value);
1770 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1771 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1772 drm_rect_width(&pstate->dst),
1773 bpp,
801bcfff
PZ		 1774 mem_value);
1775 return min(method1, method2);
1776}
1777
37126462
VS		 1778/*
1779 * For both WM_PIPE and WM_LP.
1780 * mem_value must be in 0.1us units.
1781 */
7221fc33 1782static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1783 const struct intel_plane_state *pstate,
801bcfff
PZ		 1784 uint32_t mem_value)
1785{
43d59eda
MR		 1786 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1787
7221fc33 1788 if (!cstate->base.active || !pstate->visible)
801bcfff
PZ		 1789 return 0;
1790
7221fc33
MR		 1791 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1792 cstate->base.adjusted_mode.crtc_htotal,
43d59eda
MR		 1793 drm_rect_width(&pstate->dst),
1794 bpp,
801bcfff
PZ		 1795 mem_value);
1796}
1797
cca32e9a 1798/* Only for WM_LP. */
7221fc33 1799static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1800 const struct intel_plane_state *pstate,
1fda9882 1801 uint32_t pri_val)
cca32e9a 1802{
43d59eda
MR		 1803 int bpp = pstate->base.fb ? pstate->base.fb->bits_per_pixel / 8 : 0;
1804
7221fc33 1805 if (!cstate->base.active || !pstate->visible)
cca32e9a
PZ		 1806 return 0;
1807
43d59eda 1808 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->dst), bpp);
cca32e9a
PZ		 1809}
1810
158ae64f
VS		 1811static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1812{
416f4727
VS		 1813 if (INTEL_INFO(dev)->gen >= 8)
1814 return 3072;
1815 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1816 return 768;
1817 else
1818 return 512;
1819}
1820
4e975081
VS		 1821static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1822 int level, bool is_sprite)
1823{
1824 if (INTEL_INFO(dev)->gen >= 8)
1825 /* BDW primary/sprite plane watermarks */
1826 return level == 0 ? 255 : 2047;
1827 else if (INTEL_INFO(dev)->gen >= 7)
1828 /* IVB/HSW primary/sprite plane watermarks */
1829 return level == 0 ? 127 : 1023;
1830 else if (!is_sprite)
1831 /* ILK/SNB primary plane watermarks */
1832 return level == 0 ? 127 : 511;
1833 else
1834 /* ILK/SNB sprite plane watermarks */
1835 return level == 0 ? 63 : 255;
1836}
1837
1838static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1839 int level)
1840{
1841 if (INTEL_INFO(dev)->gen >= 7)
1842 return level == 0 ? 63 : 255;
1843 else
1844 return level == 0 ? 31 : 63;
1845}
1846
1847static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1848{
1849 if (INTEL_INFO(dev)->gen >= 8)
1850 return 31;
1851 else
1852 return 15;
1853}
1854
158ae64f
VS		 1855/* Calculate the maximum primary/sprite plane watermark */
1856static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1857 int level,
240264f4 1858 const struct intel_wm_config *config,
158ae64f
VS		 1859 enum intel_ddb_partitioning ddb_partitioning,
1860 bool is_sprite)
1861{
1862 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1863
1864 /* if sprites aren't enabled, sprites get nothing */
240264f4 1865 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1866 return 0;
1867
1868 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1869 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1870 fifo_size /= INTEL_INFO(dev)->num_pipes;
1871
1872 /*
1873 * For some reason the non self refresh
1874 * FIFO size is only half of the self
1875 * refresh FIFO size on ILK/SNB.
1876 */
1877 if (INTEL_INFO(dev)->gen <= 6)
1878 fifo_size /= 2;
1879 }
1880
240264f4 1881 if (config->sprites_enabled) {
158ae64f
VS		 1882 /* level 0 is always calculated with 1:1 split */
1883 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1884 if (is_sprite)
1885 fifo_size *= 5;
1886 fifo_size /= 6;
1887 } else {
1888 fifo_size /= 2;
1889 }
1890 }
1891
1892 /* clamp to max that the registers can hold */
4e975081 1893 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1894}
1895
1896/* Calculate the maximum cursor plane watermark */
1897static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1898 int level,
1899 const struct intel_wm_config *config)
158ae64f
VS		 1900{
1901 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1902 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1903 return 64;
1904
1905 /* otherwise just report max that registers can hold */
4e975081 1906 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1907}
1908
d34ff9c6 1909static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1910 int level,
1911 const struct intel_wm_config *config,
1912 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1913 struct ilk_wm_maximums *max)
158ae64f 1914{
240264f4
VS		 1915 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1916 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1917 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1918 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1919}
1920
a3cb4048
VS		 1921static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1922 int level,
1923 struct ilk_wm_maximums *max)
1924{
1925 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1926 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1927 max->cur = ilk_cursor_wm_reg_max(dev, level);
1928 max->fbc = ilk_fbc_wm_reg_max(dev);
1929}
1930
d9395655 1931static bool ilk_validate_wm_level(int level,
820c1980 1932 const struct ilk_wm_maximums *max,
d9395655 1933 struct intel_wm_level *result)
a9786a11
VS		 1934{
1935 bool ret;
1936
1937 /* already determined to be invalid? */
1938 if (!result->enable)
1939 return false;
1940
1941 result->enable = result->pri_val <= max->pri &&
1942 result->spr_val <= max->spr &&
1943 result->cur_val <= max->cur;
1944
1945 ret = result->enable;
1946
1947 /*
1948 * HACK until we can pre-compute everything,
1949 * and thus fail gracefully if LP0 watermarks
1950 * are exceeded...
1951 */
1952 if (level == 0 && !result->enable) {
1953 if (result->pri_val > max->pri)
1954 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1955 level, result->pri_val, max->pri);
1956 if (result->spr_val > max->spr)
1957 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
1958 level, result->spr_val, max->spr);
1959 if (result->cur_val > max->cur)
1960 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
1961 level, result->cur_val, max->cur);
1962
1963 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
1964 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
1965 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
1966 result->enable = true;
1967 }
1968
a9786a11
VS		 1969 return ret;
1970}
1971
d34ff9c6 1972static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 1973 const struct intel_crtc *intel_crtc,
6f5ddd17 1974 int level,
7221fc33 1975 struct intel_crtc_state *cstate,
86c8bbbe
MR		 1976 struct intel_plane_state *pristate,
1977 struct intel_plane_state *sprstate,
1978 struct intel_plane_state *curstate,
1fd527cc 1979 struct intel_wm_level *result)
6f5ddd17
VS		 1980{
1981 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
1982 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
1983 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
1984
1985 /* WM1+ latency values stored in 0.5us units */
1986 if (level > 0) {
1987 pri_latency *= 5;
1988 spr_latency *= 5;
1989 cur_latency *= 5;
1990 }
1991
86c8bbbe
MR		 1992 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
1993 pri_latency, level);
1994 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
1995 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
1996 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
6f5ddd17
VS		 1997 result->enable = true;
1998}
1999
801bcfff
PZ		 2000static uint32_t
2001hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2002{
2003 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2004 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
7c5f93b0 2005 const struct drm_display_mode *adjusted_mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2006 u32 linetime, ips_linetime;
1f8eeabf 2007
3ef00284 2008 if (!intel_crtc->active)
801bcfff 2009 return 0;
1011d8c4 2010
1f8eeabf
ED		 2011 /* The WM are computed with base on how long it takes to fill a single
2012 * row at the given clock rate, multiplied by 8.
2013 * */
124abe07
VS		 2014 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2015 adjusted_mode->crtc_clock);
2016 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
05024da3 2017 dev_priv->cdclk_freq);
1f8eeabf 2018
801bcfff
PZ		 2019 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2020 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2021}
2022
2af30a5c 2023static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2024{
2025 struct drm_i915_private *dev_priv = dev->dev_private;
2026
2af30a5c
PB		 2027 if (IS_GEN9(dev)) {
2028 uint32_t val;
4f947386 2029 int ret, i;
367294be 2030 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2031
2032 /* read the first set of memory latencies[0:3] */
2033 val = 0; /* data0 to be programmed to 0 for first set */
2034 mutex_lock(&dev_priv->rps.hw_lock);
2035 ret = sandybridge_pcode_read(dev_priv,
2036 GEN9_PCODE_READ_MEM_LATENCY,
2037 &val);
2038 mutex_unlock(&dev_priv->rps.hw_lock);
2039
2040 if (ret) {
2041 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2042 return;
2043 }
2044
2045 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2046 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2047 GEN9_MEM_LATENCY_LEVEL_MASK;
2048 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2049 GEN9_MEM_LATENCY_LEVEL_MASK;
2050 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2051 GEN9_MEM_LATENCY_LEVEL_MASK;
2052
2053 /* read the second set of memory latencies[4:7] */
2054 val = 1; /* data0 to be programmed to 1 for second set */
2055 mutex_lock(&dev_priv->rps.hw_lock);
2056 ret = sandybridge_pcode_read(dev_priv,
2057 GEN9_PCODE_READ_MEM_LATENCY,
2058 &val);
2059 mutex_unlock(&dev_priv->rps.hw_lock);
2060 if (ret) {
2061 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2062 return;
2063 }
2064
2065 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2066 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2067 GEN9_MEM_LATENCY_LEVEL_MASK;
2068 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2069 GEN9_MEM_LATENCY_LEVEL_MASK;
2070 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2071 GEN9_MEM_LATENCY_LEVEL_MASK;
2072
367294be 2073 /*
6f97235b
DL		 2074 * WaWmMemoryReadLatency:skl
2075 *
367294be
VK		 2076 * punit doesn't take into account the read latency so we need
2077 * to add 2us to the various latency levels we retrieve from
2078 * the punit.
2079 * - W0 is a bit special in that it's the only level that
2080 * can't be disabled if we want to have display working, so
2081 * we always add 2us there.
2082 * - For levels >=1, punit returns 0us latency when they are
2083 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2084 *
2085 * Additionally, if a level n (n > 1) has a 0us latency, all
2086 * levels m (m >= n) need to be disabled. We make sure to
2087 * sanitize the values out of the punit to satisfy this
2088 * requirement.
367294be
VK		 2089 */
2090 wm[0] += 2;
2091 for (level = 1; level <= max_level; level++)
2092 if (wm[level] != 0)
2093 wm[level] += 2;
4f947386
VK		 2094 else {
2095 for (i = level + 1; i <= max_level; i++)
2096 wm[i] = 0;
367294be 2097
4f947386
VK		 2098 break;
2099 }
2af30a5c 2100 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2101 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2102
2103 wm[0] = (sskpd >> 56) & 0xFF;
2104 if (wm[0] == 0)
2105 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2106 wm[1] = (sskpd >> 4) & 0xFF;
2107 wm[2] = (sskpd >> 12) & 0xFF;
2108 wm[3] = (sskpd >> 20) & 0x1FF;
2109 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2110 } else if (INTEL_INFO(dev)->gen >= 6) {
2111 uint32_t sskpd = I915_READ(MCH_SSKPD);
2112
2113 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2114 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2115 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2116 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2117 } else if (INTEL_INFO(dev)->gen >= 5) {
2118 uint32_t mltr = I915_READ(MLTR_ILK);
2119
2120 /* ILK primary LP0 latency is 700 ns */
2121 wm[0] = 7;
2122 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2123 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2124 }
2125}
2126
53615a5e
VS		 2127static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2128{
2129 /* ILK sprite LP0 latency is 1300 ns */
2130 if (INTEL_INFO(dev)->gen == 5)
2131 wm[0] = 13;
2132}
2133
2134static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2135{
2136 /* ILK cursor LP0 latency is 1300 ns */
2137 if (INTEL_INFO(dev)->gen == 5)
2138 wm[0] = 13;
2139
2140 /* WaDoubleCursorLP3Latency:ivb */
2141 if (IS_IVYBRIDGE(dev))
2142 wm[3] *= 2;
2143}
2144
546c81fd 2145int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2146{
26ec971e 2147 /* how many WM levels are we expecting */
b6e742f6 2148 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2149 return 7;
2150 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2151 return 4;
26ec971e 2152 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2153 return 3;
26ec971e 2154 else
ad0d6dc4
VS		 2155 return 2;
2156}
7526ed79 2157
ad0d6dc4
VS		 2158static void intel_print_wm_latency(struct drm_device *dev,
2159 const char *name,
2af30a5c 2160 const uint16_t wm[8])
ad0d6dc4
VS		 2161{
2162 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2163
2164 for (level = 0; level <= max_level; level++) {
2165 unsigned int latency = wm[level];
2166
2167 if (latency == 0) {
2168 DRM_ERROR("%s WM%d latency not provided\n",
2169 name, level);
2170 continue;
2171 }
2172
2af30a5c
PB		 2173 /*
2174 * - latencies are in us on gen9.
2175 * - before then, WM1+ latency values are in 0.5us units
2176 */
2177 if (IS_GEN9(dev))
2178 latency *= 10;
2179 else if (level > 0)
26ec971e
VS		 2180 latency *= 5;
2181
2182 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2183 name, level, wm[level],
2184 latency / 10, latency % 10);
2185 }
2186}
2187
e95a2f75
VS		 2188static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2189 uint16_t wm[5], uint16_t min)
2190{
2191 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2192
2193 if (wm[0] >= min)
2194 return false;
2195
2196 wm[0] = max(wm[0], min);
2197 for (level = 1; level <= max_level; level++)
2198 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2199
2200 return true;
2201}
2202
2203static void snb_wm_latency_quirk(struct drm_device *dev)
2204{
2205 struct drm_i915_private *dev_priv = dev->dev_private;
2206 bool changed;
2207
2208 /*
2209 * The BIOS provided WM memory latency values are often
2210 * inadequate for high resolution displays. Adjust them.
2211 */
2212 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2213 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2214 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2215
2216 if (!changed)
2217 return;
2218
2219 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2220 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2221 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2222 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2223}
2224
fa50ad61 2225static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2226{
2227 struct drm_i915_private *dev_priv = dev->dev_private;
2228
2229 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2230
2231 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2232 sizeof(dev_priv->wm.pri_latency));
2233 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2234 sizeof(dev_priv->wm.pri_latency));
2235
2236 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2237 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2238
2239 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2240 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2241 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2242
2243 if (IS_GEN6(dev))
2244 snb_wm_latency_quirk(dev);
53615a5e
VS		 2245}
2246
2af30a5c
PB		 2247static void skl_setup_wm_latency(struct drm_device *dev)
2248{
2249 struct drm_i915_private *dev_priv = dev->dev_private;
2250
2251 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2252 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2253}
2254
0b2ae6d7 2255/* Compute new watermarks for the pipe */
86c8bbbe
MR		 2256static int ilk_compute_pipe_wm(struct intel_crtc *intel_crtc,
2257 struct drm_atomic_state *state)
0b2ae6d7 2258{
86c8bbbe
MR		 2259 struct intel_pipe_wm *pipe_wm;
2260 struct drm_device *dev = intel_crtc->base.dev;
d34ff9c6 2261 const struct drm_i915_private *dev_priv = dev->dev_private;
86c8bbbe 2262 struct intel_crtc_state *cstate = NULL;
43d59eda 2263 struct intel_plane *intel_plane;
86c8bbbe
MR		 2264 struct drm_plane_state *ps;
2265 struct intel_plane_state *pristate = NULL;
43d59eda 2266 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2267 struct intel_plane_state *curstate = NULL;
0b2ae6d7
VS		 2268 int level, max_level = ilk_wm_max_level(dev);
2269 /* LP0 watermark maximums depend on this pipe alone */
2270 struct intel_wm_config config = {
2271 .num_pipes_active = 1,
0b2ae6d7 2272 };
820c1980 2273 struct ilk_wm_maximums max;
0b2ae6d7 2274
86c8bbbe
MR		 2275 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
2276 if (IS_ERR(cstate))
2277 return PTR_ERR(cstate);
2278
2279 pipe_wm = &cstate->wm.optimal.ilk;
2280
43d59eda 2281 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
86c8bbbe
MR		 2282 ps = drm_atomic_get_plane_state(state,
2283 &intel_plane->base);
2284 if (IS_ERR(ps))
2285 return PTR_ERR(ps);
2286
2287 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
2288 pristate = to_intel_plane_state(ps);
2289 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
2290 sprstate = to_intel_plane_state(ps);
2291 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2292 curstate = to_intel_plane_state(ps);
43d59eda
MR		 2293 }
2294
2295 config.sprites_enabled = sprstate->visible;
2296 config.sprites_scaled = sprstate->visible &&
2297 (drm_rect_width(&sprstate->dst) != drm_rect_width(&sprstate->src) >> 16 ||
2298 drm_rect_height(&sprstate->dst) != drm_rect_height(&sprstate->src) >> 16);
2299
7221fc33 2300 pipe_wm->pipe_enabled = cstate->base.active;
86c8bbbe 2301 pipe_wm->sprites_enabled = config.sprites_enabled;
43d59eda 2302 pipe_wm->sprites_scaled = config.sprites_scaled;
2a44b76b 2303
7b39a0b7 2304 /* ILK/SNB: LP2+ watermarks only w/o sprites */
43d59eda 2305 if (INTEL_INFO(dev)->gen <= 6 && sprstate->visible)
7b39a0b7
VS		 2306 max_level = 1;
2307
2308 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
43d59eda 2309 if (config.sprites_scaled)
7b39a0b7
VS		 2310 max_level = 0;
2311
86c8bbbe
MR		 2312 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
2313 pristate, sprstate, curstate, &pipe_wm->wm[0]);
0b2ae6d7 2314
a42a5719 2315 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
86c8bbbe
MR		 2316 pipe_wm->linetime = hsw_compute_linetime_wm(dev,
2317 &intel_crtc->base);
0b2ae6d7 2318
a3cb4048
VS		 2319 /* LP0 watermarks always use 1/2 DDB partitioning */
2320 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2321
0b2ae6d7 2322 /* At least LP0 must be valid */
a3cb4048 2323 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
86c8bbbe 2324 return -EINVAL;
a3cb4048
VS		 2325
2326 ilk_compute_wm_reg_maximums(dev, 1, &max);
2327
2328 for (level = 1; level <= max_level; level++) {
2329 struct intel_wm_level wm = {};
2330
86c8bbbe
MR		 2331 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
2332 pristate, sprstate, curstate, &wm);
a3cb4048
VS		 2333
2334 /*
2335 * Disable any watermark level that exceeds the
2336 * register maximums since such watermarks are
2337 * always invalid.
2338 */
2339 if (!ilk_validate_wm_level(level, &max, &wm))
2340 break;
2341
2342 pipe_wm->wm[level] = wm;
2343 }
2344
86c8bbbe 2345 return 0;
0b2ae6d7
VS		 2346}
2347
2348/*
2349 * Merge the watermarks from all active pipes for a specific level.
2350 */
2351static void ilk_merge_wm_level(struct drm_device *dev,
2352 int level,
2353 struct intel_wm_level *ret_wm)
2354{
2355 const struct intel_crtc *intel_crtc;
2356
d52fea5b
VS		 2357 ret_wm->enable = true;
2358
d3fcc808 2359 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2360 const struct intel_crtc_state *cstate =
2361 to_intel_crtc_state(intel_crtc->base.state);
2362 const struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
fe392efd
VS		 2363 const struct intel_wm_level *wm = &active->wm[level];
2364
2365 if (!active->pipe_enabled)
2366 continue;
0b2ae6d7 2367
d52fea5b
VS		 2368 /*
2369 * The watermark values may have been used in the past,
2370 * so we must maintain them in the registers for some
2371 * time even if the level is now disabled.
2372 */
0b2ae6d7 2373 if (!wm->enable)
d52fea5b 2374 ret_wm->enable = false;
0b2ae6d7
VS		 2375
2376 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2377 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2378 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2379 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2380 }
0b2ae6d7
VS		 2381}
2382
2383/*
2384 * Merge all low power watermarks for all active pipes.
2385 */
2386static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2387 const struct intel_wm_config *config,
820c1980 2388 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2389 struct intel_pipe_wm *merged)
2390{
7733b49b 2391 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2392 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2393 int last_enabled_level = max_level;
0b2ae6d7 2394
0ba22e26
VS		 2395 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2396 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2397 config->num_pipes_active > 1)
2398 return;
2399
6c8b6c28
VS		 2400 /* ILK: FBC WM must be disabled always */
2401 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2402
2403 /* merge each WM1+ level */
2404 for (level = 1; level <= max_level; level++) {
2405 struct intel_wm_level *wm = &merged->wm[level];
2406
2407 ilk_merge_wm_level(dev, level, wm);
2408
d52fea5b
VS		 2409 if (level > last_enabled_level)
2410 wm->enable = false;
2411 else if (!ilk_validate_wm_level(level, max, wm))
2412 /* make sure all following levels get disabled */
2413 last_enabled_level = level - 1;
0b2ae6d7
VS		 2414
2415 /*
2416 * The spec says it is preferred to disable
2417 * FBC WMs instead of disabling a WM level.
2418 */
2419 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2420 if (wm->enable)
2421 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2422 wm->fbc_val = 0;
2423 }
2424 }
6c8b6c28
VS		 2425
2426 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2427 /*
2428 * FIXME this is racy. FBC might get enabled later.
2429 * What we should check here is whether FBC can be
2430 * enabled sometime later.
2431 */
7733b49b 2432 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2433 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2434 for (level = 2; level <= max_level; level++) {
2435 struct intel_wm_level *wm = &merged->wm[level];
2436
2437 wm->enable = false;
2438 }
2439 }
0b2ae6d7
VS		 2440}
2441
b380ca3c
VS		 2442static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2443{
2444 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2445 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2446}
2447
a68d68ee
VS		 2448/* The value we need to program into the WM_LPx latency field */
2449static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2450{
2451 struct drm_i915_private *dev_priv = dev->dev_private;
2452
a42a5719 2453 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2454 return 2 * level;
2455 else
2456 return dev_priv->wm.pri_latency[level];
2457}
2458
820c1980 2459static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2460 const struct intel_pipe_wm *merged,
609cedef 2461 enum intel_ddb_partitioning partitioning,
820c1980 2462 struct ilk_wm_values *results)
801bcfff 2463{
0b2ae6d7
VS		 2464 struct intel_crtc *intel_crtc;
2465 int level, wm_lp;
cca32e9a 2466
0362c781 2467 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2468 results->partitioning = partitioning;
cca32e9a 2469
0b2ae6d7 2470 /* LP1+ register values */
cca32e9a 2471 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2472 const struct intel_wm_level *r;
801bcfff 2473
b380ca3c 2474 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2475
0362c781 2476 r = &merged->wm[level];
cca32e9a 2477
d52fea5b
VS		 2478 /*
2479 * Maintain the watermark values even if the level is
2480 * disabled. Doing otherwise could cause underruns.
2481 */
2482 results->wm_lp[wm_lp - 1] =
a68d68ee 2483 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2484 (r->pri_val << WM1_LP_SR_SHIFT) |
2485 r->cur_val;
2486
d52fea5b
VS		 2487 if (r->enable)
2488 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2489
416f4727
VS		 2490 if (INTEL_INFO(dev)->gen >= 8)
2491 results->wm_lp[wm_lp - 1] |=
2492 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2493 else
2494 results->wm_lp[wm_lp - 1] |=
2495 r->fbc_val << WM1_LP_FBC_SHIFT;
2496
d52fea5b
VS		 2497 /*
2498 * Always set WM1S_LP_EN when spr_val != 0, even if the
2499 * level is disabled. Doing otherwise could cause underruns.
2500 */
6cef2b8a
VS		 2501 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2502 WARN_ON(wm_lp != 1);
2503 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2504 } else
2505 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2506 }
801bcfff 2507
0b2ae6d7 2508 /* LP0 register values */
d3fcc808 2509 for_each_intel_crtc(dev, intel_crtc) {
4e0963c7
MR		 2510 const struct intel_crtc_state *cstate =
2511 to_intel_crtc_state(intel_crtc->base.state);
0b2ae6d7 2512 enum pipe pipe = intel_crtc->pipe;
4e0963c7 2513 const struct intel_wm_level *r = &cstate->wm.optimal.ilk.wm[0];
0b2ae6d7
VS		 2514
2515 if (WARN_ON(!r->enable))
2516 continue;
2517
4e0963c7 2518 results->wm_linetime[pipe] = cstate->wm.optimal.ilk.linetime;
1011d8c4 2519
0b2ae6d7
VS		 2520 results->wm_pipe[pipe] =
2521 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2522 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2523 r->cur_val;
801bcfff
PZ		 2524 }
2525}
2526
861f3389
PZ		 2527/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2528 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2529static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2530 struct intel_pipe_wm *r1,
2531 struct intel_pipe_wm *r2)
861f3389 2532{
198a1e9b
VS		 2533 int level, max_level = ilk_wm_max_level(dev);
2534 int level1 = 0, level2 = 0;
861f3389 2535
198a1e9b
VS		 2536 for (level = 1; level <= max_level; level++) {
2537 if (r1->wm[level].enable)
2538 level1 = level;
2539 if (r2->wm[level].enable)
2540 level2 = level;
861f3389
PZ		 2541 }
2542
198a1e9b
VS		 2543 if (level1 == level2) {
2544 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2545 return r2;
2546 else
2547 return r1;
198a1e9b 2548 } else if (level1 > level2) {
861f3389
PZ		 2549 return r1;
2550 } else {
2551 return r2;
2552 }
2553}
2554
49a687c4
VS		 2555/* dirty bits used to track which watermarks need changes */
2556#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2557#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2558#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2559#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2560#define WM_DIRTY_FBC (1 << 24)
2561#define WM_DIRTY_DDB (1 << 25)
2562
055e393f 2563static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2564 const struct ilk_wm_values *old,
2565 const struct ilk_wm_values *new)
49a687c4
VS		 2566{
2567 unsigned int dirty = 0;
2568 enum pipe pipe;
2569 int wm_lp;
2570
055e393f 2571 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2572 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2573 dirty |= WM_DIRTY_LINETIME(pipe);
2574 /* Must disable LP1+ watermarks too */
2575 dirty |= WM_DIRTY_LP_ALL;
2576 }
2577
2578 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2579 dirty |= WM_DIRTY_PIPE(pipe);
2580 /* Must disable LP1+ watermarks too */
2581 dirty |= WM_DIRTY_LP_ALL;
2582 }
2583 }
2584
2585 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2586 dirty |= WM_DIRTY_FBC;
2587 /* Must disable LP1+ watermarks too */
2588 dirty |= WM_DIRTY_LP_ALL;
2589 }
2590
2591 if (old->partitioning != new->partitioning) {
2592 dirty |= WM_DIRTY_DDB;
2593 /* Must disable LP1+ watermarks too */
2594 dirty |= WM_DIRTY_LP_ALL;
2595 }
2596
2597 /* LP1+ watermarks already deemed dirty, no need to continue */
2598 if (dirty & WM_DIRTY_LP_ALL)
2599 return dirty;
2600
2601 /* Find the lowest numbered LP1+ watermark in need of an update... */
2602 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2603 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2604 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2605 break;
2606 }
2607
2608 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2609 for (; wm_lp <= 3; wm_lp++)
2610 dirty |= WM_DIRTY_LP(wm_lp);
2611
2612 return dirty;
2613}
2614
8553c18e
VS		 2615static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2616 unsigned int dirty)
801bcfff 2617{
820c1980 2618 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2619 bool changed = false;
801bcfff 2620
facd619b
VS		 2621 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2622 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2623 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2624 changed = true;
facd619b
VS		 2625 }
2626 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2627 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2628 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2629 changed = true;
facd619b
VS		 2630 }
2631 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2632 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2633 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2634 changed = true;
facd619b 2635 }
801bcfff 2636
facd619b
VS		 2637 /*
2638 * Don't touch WM1S_LP_EN here.
2639 * Doing so could cause underruns.
2640 */
6cef2b8a 2641
8553c18e
VS		 2642 return changed;
2643}
2644
2645/*
2646 * The spec says we shouldn't write when we don't need, because every write
2647 * causes WMs to be re-evaluated, expending some power.
2648 */
820c1980
ID		 2649static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2650 struct ilk_wm_values *results)
8553c18e
VS		 2651{
2652 struct drm_device *dev = dev_priv->dev;
820c1980 2653 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2654 unsigned int dirty;
2655 uint32_t val;
2656
055e393f 2657 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2658 if (!dirty)
2659 return;
2660
2661 _ilk_disable_lp_wm(dev_priv, dirty);
2662
49a687c4 2663 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2664 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2665 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2666 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2667 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2668 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2669
49a687c4 2670 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2671 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2672 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2673 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2674 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2675 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2676
49a687c4 2677 if (dirty & WM_DIRTY_DDB) {
a42a5719 2678 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2679 val = I915_READ(WM_MISC);
2680 if (results->partitioning == INTEL_DDB_PART_1_2)
2681 val &= ~WM_MISC_DATA_PARTITION_5_6;
2682 else
2683 val |= WM_MISC_DATA_PARTITION_5_6;
2684 I915_WRITE(WM_MISC, val);
2685 } else {
2686 val = I915_READ(DISP_ARB_CTL2);
2687 if (results->partitioning == INTEL_DDB_PART_1_2)
2688 val &= ~DISP_DATA_PARTITION_5_6;
2689 else
2690 val |= DISP_DATA_PARTITION_5_6;
2691 I915_WRITE(DISP_ARB_CTL2, val);
2692 }
1011d8c4
PZ		 2693 }
2694
49a687c4 2695 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2696 val = I915_READ(DISP_ARB_CTL);
2697 if (results->enable_fbc_wm)
2698 val &= ~DISP_FBC_WM_DIS;
2699 else
2700 val |= DISP_FBC_WM_DIS;
2701 I915_WRITE(DISP_ARB_CTL, val);
2702 }
2703
954911eb
ID		 2704 if (dirty & WM_DIRTY_LP(1) &&
2705 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2706 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2707
2708 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2709 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2710 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2711 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2712 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2713 }
801bcfff 2714
facd619b 2715 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2716 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2717 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2718 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2719 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2720 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2721
2722 dev_priv->wm.hw = *results;
801bcfff
PZ		 2723}
2724
8553c18e
VS		 2725static bool ilk_disable_lp_wm(struct drm_device *dev)
2726{
2727 struct drm_i915_private *dev_priv = dev->dev_private;
2728
2729 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2730}
2731
b9cec075
DL		 2732/*
2733 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2734 * different active planes.
2735 */
2736
2737#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2738#define BXT_DDB_SIZE 512
b9cec075 2739
024c9045
MR		 2740/*
2741 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2742 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2743 * other universal planes are in indices 1..n. Note that this may leave unused
2744 * indices between the top "sprite" plane and the cursor.
2745 */
2746static int
2747skl_wm_plane_id(const struct intel_plane *plane)
2748{
2749 switch (plane->base.type) {
2750 case DRM_PLANE_TYPE_PRIMARY:
2751 return 0;
2752 case DRM_PLANE_TYPE_CURSOR:
2753 return PLANE_CURSOR;
2754 case DRM_PLANE_TYPE_OVERLAY:
2755 return plane->plane + 1;
2756 default:
2757 MISSING_CASE(plane->base.type);
2758 return plane->plane;
2759 }
2760}
2761
b9cec075
DL		 2762static void
2763skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 2764 const struct intel_crtc_state *cstate,
b9cec075 2765 const struct intel_wm_config *config,
b9cec075
DL		 2766 struct skl_ddb_entry *alloc /* out */)
2767{
024c9045 2768 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 2769 struct drm_crtc *crtc;
2770 unsigned int pipe_size, ddb_size;
2771 int nth_active_pipe;
2772
024c9045 2773 if (!cstate->base.active) {
b9cec075
DL		 2774 alloc->start = 0;
2775 alloc->end = 0;
2776 return;
2777 }
2778
43d735a6
DL		 2779 if (IS_BROXTON(dev))
2780 ddb_size = BXT_DDB_SIZE;
2781 else
2782 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2783
2784 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2785
2786 nth_active_pipe = 0;
2787 for_each_crtc(dev, crtc) {
3ef00284 2788 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2789 continue;
2790
2791 if (crtc == for_crtc)
2792 break;
2793
2794 nth_active_pipe++;
2795 }
2796
2797 pipe_size = ddb_size / config->num_pipes_active;
2798 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2799 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2800}
2801
2802static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2803{
2804 if (config->num_pipes_active == 1)
2805 return 32;
2806
2807 return 8;
2808}
2809
a269c583
DL		 2810static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2811{
2812 entry->start = reg & 0x3ff;
2813 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2814 if (entry->end)
2815 entry->end += 1;
a269c583
DL		 2816}
2817
08db6652
DL		 2818void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2819 struct skl_ddb_allocation *ddb /* out */)
a269c583 2820{
a269c583
DL		 2821 enum pipe pipe;
2822 int plane;
2823 u32 val;
2824
b10f1b20
ML		 2825 memset(ddb, 0, sizeof(*ddb));
2826
a269c583 2827 for_each_pipe(dev_priv, pipe) {
b10f1b20
ML		 2828 if (!intel_display_power_is_enabled(dev_priv, POWER_DOMAIN_PIPE(pipe)))
2829 continue;
2830
dd740780 2831 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2832 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2833 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2834 val);
2835 }
2836
2837 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 2838 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
2839 val);
a269c583
DL		 2840 }
2841}
2842
b9cec075 2843static unsigned int
024c9045
MR		 2844skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
2845 const struct drm_plane_state *pstate,
2846 int y)
b9cec075 2847{
024c9045
MR		 2848 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2849 struct drm_framebuffer *fb = pstate->fb;
2cd601c6
CK		 2850
2851 /* for planar format */
024c9045 2852 if (fb->pixel_format == DRM_FORMAT_NV12) {
2cd601c6 2853 if (y) /* y-plane data rate */
024c9045
MR		 2854 return intel_crtc->config->pipe_src_w *
2855 intel_crtc->config->pipe_src_h *
2856 drm_format_plane_cpp(fb->pixel_format, 0);
2cd601c6 2857 else /* uv-plane data rate */
024c9045
MR		 2858 return (intel_crtc->config->pipe_src_w/2) *
2859 (intel_crtc->config->pipe_src_h/2) *
2860 drm_format_plane_cpp(fb->pixel_format, 1);
2cd601c6
CK		 2861 }
2862
2863 /* for packed formats */
024c9045
MR		 2864 return intel_crtc->config->pipe_src_w *
2865 intel_crtc->config->pipe_src_h *
2866 drm_format_plane_cpp(fb->pixel_format, 0);
b9cec075
DL		 2867}
2868
2869/*
2870 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2871 * a 8192x4096@32bpp framebuffer:
2872 * 3 * 4096 * 8192 * 4 < 2^32
2873 */
2874static unsigned int
024c9045 2875skl_get_total_relative_data_rate(const struct intel_crtc_state *cstate)
b9cec075 2876{
024c9045
MR		 2877 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
2878 struct drm_device *dev = intel_crtc->base.dev;
2879 const struct intel_plane *intel_plane;
b9cec075 2880 unsigned int total_data_rate = 0;
b9cec075 2881
024c9045
MR		 2882 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2883 const struct drm_plane_state *pstate = intel_plane->base.state;
b9cec075 2884
024c9045 2885 if (pstate->fb == NULL)
b9cec075
DL		 2886 continue;
2887
024c9045
MR		 2888 if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
2889 continue;
2890
2891 /* packed/uv */
2892 total_data_rate += skl_plane_relative_data_rate(cstate,
2893 pstate,
2894 0);
2895
2896 if (pstate->fb->pixel_format == DRM_FORMAT_NV12)
2897 /* y-plane */
2898 total_data_rate += skl_plane_relative_data_rate(cstate,
2899 pstate,
2900 1);
b9cec075
DL		 2901 }
2902
2903 return total_data_rate;
2904}
2905
2906static void
024c9045 2907skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 2908 struct skl_ddb_allocation *ddb /* out */)
2909{
024c9045 2910 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075 2911 struct drm_device *dev = crtc->dev;
aa363136
MR		 2912 struct drm_i915_private *dev_priv = to_i915(dev);
2913 struct intel_wm_config *config = &dev_priv->wm.config;
b9cec075 2914 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 2915 struct intel_plane *intel_plane;
b9cec075 2916 enum pipe pipe = intel_crtc->pipe;
34bb56af 2917 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2918 uint16_t alloc_size, start, cursor_blocks;
80958155 2919 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2920 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075 2921 unsigned int total_data_rate;
b9cec075 2922
024c9045 2923 skl_ddb_get_pipe_allocation_limits(dev, cstate, config, alloc);
34bb56af 2924 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2925 if (alloc_size == 0) {
2926 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
4969d33e
MR		 2927 memset(&ddb->plane[pipe][PLANE_CURSOR], 0,
2928 sizeof(ddb->plane[pipe][PLANE_CURSOR]));
b9cec075
DL		 2929 return;
2930 }
2931
2932 cursor_blocks = skl_cursor_allocation(config);
4969d33e
MR		 2933 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
2934 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 2935
2936 alloc_size -= cursor_blocks;
34bb56af 2937 alloc->end -= cursor_blocks;
b9cec075 2938
80958155 2939 /* 1. Allocate the mininum required blocks for each active plane */
024c9045
MR		 2940 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2941 struct drm_plane *plane = &intel_plane->base;
2942 struct drm_framebuffer *fb = plane->state->fb;
2943 int id = skl_wm_plane_id(intel_plane);
80958155 2944
024c9045
MR		 2945 if (fb == NULL)
2946 continue;
2947 if (plane->type == DRM_PLANE_TYPE_CURSOR)
80958155
DL		 2948 continue;
2949
024c9045
MR		 2950 minimum[id] = 8;
2951 alloc_size -= minimum[id];
2952 y_minimum[id] = (fb->pixel_format == DRM_FORMAT_NV12) ? 8 : 0;
2953 alloc_size -= y_minimum[id];
80958155
DL		 2954 }
2955
b9cec075 2956 /*
80958155
DL		 2957 * 2. Distribute the remaining space in proportion to the amount of
2958 * data each plane needs to fetch from memory.
b9cec075
DL		 2959 *
2960 * FIXME: we may not allocate every single block here.
2961 */
024c9045 2962 total_data_rate = skl_get_total_relative_data_rate(cstate);
b9cec075 2963
34bb56af 2964 start = alloc->start;
024c9045
MR		 2965 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2966 struct drm_plane *plane = &intel_plane->base;
2967 struct drm_plane_state *pstate = intel_plane->base.state;
2cd601c6
CK		 2968 unsigned int data_rate, y_data_rate;
2969 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 2970 int id = skl_wm_plane_id(intel_plane);
b9cec075 2971
024c9045
MR		 2972 if (pstate->fb == NULL)
2973 continue;
2974 if (plane->type == DRM_PLANE_TYPE_CURSOR)
b9cec075
DL		 2975 continue;
2976
024c9045 2977 data_rate = skl_plane_relative_data_rate(cstate, pstate, 0);
b9cec075
DL		 2978
2979 /*
2cd601c6 2980 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 2981 * promote the expression to 64 bits to avoid overflowing, the
2982 * result is < available as data_rate / total_data_rate < 1
2983 */
024c9045 2984 plane_blocks = minimum[id];
80958155
DL		 2985 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
2986 total_data_rate);
b9cec075 2987
024c9045
MR		 2988 ddb->plane[pipe][id].start = start;
2989 ddb->plane[pipe][id].end = start + plane_blocks;
b9cec075
DL		 2990
2991 start += plane_blocks;
2cd601c6
CK		 2992
2993 /*
2994 * allocation for y_plane part of planar format:
2995 */
024c9045
MR		 2996 if (pstate->fb->pixel_format == DRM_FORMAT_NV12) {
2997 y_data_rate = skl_plane_relative_data_rate(cstate,
2998 pstate,
2999 1);
3000 y_plane_blocks = y_minimum[id];
2cd601c6
CK		 3001 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3002 total_data_rate);
3003
024c9045
MR		 3004 ddb->y_plane[pipe][id].start = start;
3005 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
2cd601c6
CK		 3006
3007 start += y_plane_blocks;
3008 }
3009
b9cec075
DL		 3010 }
3011
3012}
3013
5cec258b 3014static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3015{
3016 /* TODO: Take into account the scalers once we support them */
2d112de7 3017 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3018}
3019
3020/*
3021 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3022 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3023 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3024 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3025*/
3026static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3027 uint32_t latency)
3028{
3029 uint32_t wm_intermediate_val, ret;
3030
3031 if (latency == 0)
3032 return UINT_MAX;
3033
d4c2aa60 3034 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3035 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3036
3037 return ret;
3038}
3039
3040static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3041 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3042 uint64_t tiling, uint32_t latency)
2d41c0b5 3043{
d4c2aa60
TU		 3044 uint32_t ret;
3045 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3046 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3047
3048 if (latency == 0)
3049 return UINT_MAX;
3050
3051 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3052
3053 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3054 tiling == I915_FORMAT_MOD_Yf_TILED) {
3055 plane_bytes_per_line *= 4;
3056 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3057 plane_blocks_per_line /= 4;
3058 } else {
3059 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3060 }
3061
2d41c0b5
PB		 3062 wm_intermediate_val = latency * pixel_rate;
3063 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3064 plane_blocks_per_line;
2d41c0b5
PB		 3065
3066 return ret;
3067}
3068
2d41c0b5
PB		 3069static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3070 const struct intel_crtc *intel_crtc)
3071{
3072 struct drm_device *dev = intel_crtc->base.dev;
3073 struct drm_i915_private *dev_priv = dev->dev_private;
3074 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
2d41c0b5 3075
e6d90023
KM		 3076 /*
3077 * If ddb allocation of pipes changed, it may require recalculation of
3078 * watermarks
3079 */
3080 if (memcmp(new_ddb->pipe, cur_ddb->pipe, sizeof(new_ddb->pipe)))
2d41c0b5
PB		 3081 return true;
3082
3083 return false;
3084}
3085
d4c2aa60 3086static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
024c9045
MR		 3087 struct intel_crtc_state *cstate,
3088 struct intel_plane *intel_plane,
afb024aa 3089 uint16_t ddb_allocation,
d4c2aa60 3090 int level,
afb024aa
DL		 3091 uint16_t *out_blocks, /* out */
3092 uint8_t *out_lines /* out */)
2d41c0b5 3093{
024c9045
MR		 3094 struct drm_plane *plane = &intel_plane->base;
3095 struct drm_framebuffer *fb = plane->state->fb;
d4c2aa60
TU		 3096 uint32_t latency = dev_priv->wm.skl_latency[level];
3097 uint32_t method1, method2;
3098 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3099 uint32_t res_blocks, res_lines;
3100 uint32_t selected_result;
2cd601c6 3101 uint8_t bytes_per_pixel;
2d41c0b5 3102
024c9045 3103 if (latency == 0 || !cstate->base.active || !fb)
2d41c0b5
PB		 3104 return false;
3105
024c9045
MR		 3106 bytes_per_pixel = drm_format_plane_cpp(fb->pixel_format, 0);
3107 method1 = skl_wm_method1(skl_pipe_pixel_rate(cstate),
2cd601c6 3108 bytes_per_pixel,
d4c2aa60 3109 latency);
024c9045
MR		 3110 method2 = skl_wm_method2(skl_pipe_pixel_rate(cstate),
3111 cstate->base.adjusted_mode.crtc_htotal,
3112 cstate->pipe_src_w,
2cd601c6 3113 bytes_per_pixel,
024c9045 3114 fb->modifier[0],
d4c2aa60 3115 latency);
2d41c0b5 3116
024c9045 3117 plane_bytes_per_line = cstate->pipe_src_w * bytes_per_pixel;
d4c2aa60 3118 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3119
024c9045
MR		 3120 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3121 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3122 uint32_t min_scanlines = 4;
3123 uint32_t y_tile_minimum;
024c9045
MR		 3124 if (intel_rotation_90_or_270(plane->state->rotation)) {
3125 int bpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3126 drm_format_plane_cpp(fb->pixel_format, 1) :
3127 drm_format_plane_cpp(fb->pixel_format, 0);
3128
3129 switch (bpp) {
1fc0a8f7
TU		 3130 case 1:
3131 min_scanlines = 16;
3132 break;
3133 case 2:
3134 min_scanlines = 8;
3135 break;
3136 case 8:
3137 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3138 }
1fc0a8f7
TU		 3139 }
3140 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3141 selected_result = max(method2, y_tile_minimum);
3142 } else {
3143 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3144 selected_result = min(method1, method2);
3145 else
3146 selected_result = method1;
3147 }
2d41c0b5 3148
d4c2aa60
TU		 3149 res_blocks = selected_result + 1;
3150 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3151
0fda6568 3152 if (level >= 1 && level <= 7) {
024c9045
MR		 3153 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3154 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED)
0fda6568
TU		 3155 res_lines += 4;
3156 else
3157 res_blocks++;
3158 }
e6d66171 3159
d4c2aa60 3160 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3161 return false;
3162
3163 *out_blocks = res_blocks;
3164 *out_lines = res_lines;
2d41c0b5
PB		 3165
3166 return true;
3167}
3168
3169static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3170 struct skl_ddb_allocation *ddb,
024c9045 3171 struct intel_crtc_state *cstate,
2d41c0b5 3172 int level,
2d41c0b5
PB		 3173 struct skl_wm_level *result)
3174{
024c9045
MR		 3175 struct drm_device *dev = dev_priv->dev;
3176 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
3177 struct intel_plane *intel_plane;
2d41c0b5 3178 uint16_t ddb_blocks;
024c9045
MR		 3179 enum pipe pipe = intel_crtc->pipe;
3180
3181 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3182 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3183
2d41c0b5
PB		 3184 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3185
d4c2aa60 3186 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
024c9045
MR		 3187 cstate,
3188 intel_plane,
2d41c0b5 3189 ddb_blocks,
d4c2aa60 3190 level,
2d41c0b5
PB		 3191 &result->plane_res_b[i],
3192 &result->plane_res_l[i]);
3193 }
2d41c0b5
PB		 3194}
3195
407b50f3 3196static uint32_t
024c9045 3197skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3198{
024c9045 3199 if (!cstate->base.active)
407b50f3
DL		 3200 return 0;
3201
024c9045 3202 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3203 return 0;
407b50f3 3204
024c9045
MR		 3205 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3206 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3207}
3208
024c9045 3209static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3210 struct skl_wm_level *trans_wm /* out */)
407b50f3 3211{
024c9045 3212 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3213 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3214 struct intel_plane *intel_plane;
9414f563 3215
024c9045 3216 if (!cstate->base.active)
407b50f3 3217 return;
9414f563
DL		 3218
3219 /* Until we know more, just disable transition WMs */
024c9045
MR		 3220 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3221 int i = skl_wm_plane_id(intel_plane);
3222
9414f563 3223 trans_wm->plane_en[i] = false;
024c9045 3224 }
407b50f3
DL		 3225}
3226
024c9045 3227static void skl_compute_pipe_wm(struct intel_crtc_state *cstate,
2d41c0b5 3228 struct skl_ddb_allocation *ddb,
2d41c0b5
PB		 3229 struct skl_pipe_wm *pipe_wm)
3230{
024c9045 3231 struct drm_device *dev = cstate->base.crtc->dev;
2d41c0b5 3232 const struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5
PB		 3233 int level, max_level = ilk_wm_max_level(dev);
3234
3235 for (level = 0; level <= max_level; level++) {
024c9045
MR		 3236 skl_compute_wm_level(dev_priv, ddb, cstate,
3237 level, &pipe_wm->wm[level]);
2d41c0b5 3238 }
024c9045 3239 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3240
024c9045 3241 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
2d41c0b5
PB		 3242}
3243
3244static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3245 struct skl_pipe_wm *p_wm,
3246 struct skl_wm_values *r,
3247 struct intel_crtc *intel_crtc)
3248{
3249 int level, max_level = ilk_wm_max_level(dev);
3250 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3251 uint32_t temp;
3252 int i;
2d41c0b5
PB		 3253
3254 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3255 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3256 temp = 0;
2d41c0b5
PB		 3257
3258 temp |= p_wm->wm[level].plane_res_l[i] <<
3259 PLANE_WM_LINES_SHIFT;
3260 temp |= p_wm->wm[level].plane_res_b[i];
3261 if (p_wm->wm[level].plane_en[i])
3262 temp |= PLANE_WM_EN;
3263
3264 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3265 }
3266
3267 temp = 0;
2d41c0b5 3268
4969d33e
MR		 3269 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3270 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3271
4969d33e 3272 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3273 temp |= PLANE_WM_EN;
3274
4969d33e 3275 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3276
3277 }
3278
9414f563
DL		 3279 /* transition WMs */
3280 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3281 temp = 0;
3282 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3283 temp |= p_wm->trans_wm.plane_res_b[i];
3284 if (p_wm->trans_wm.plane_en[i])
3285 temp |= PLANE_WM_EN;
3286
3287 r->plane_trans[pipe][i] = temp;
3288 }
3289
3290 temp = 0;
4969d33e
MR		 3291 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3292 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3293 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3294 temp |= PLANE_WM_EN;
3295
4969d33e 3296 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3297
2d41c0b5
PB		 3298 r->wm_linetime[pipe] = p_wm->linetime;
3299}
3300
f0f59a00
VS		 3301static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3302 i915_reg_t reg,
16160e3d
DL		 3303 const struct skl_ddb_entry *entry)
3304{
3305 if (entry->end)
3306 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3307 else
3308 I915_WRITE(reg, 0);
3309}
3310
2d41c0b5
PB		 3311static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3312 const struct skl_wm_values *new)
3313{
3314 struct drm_device *dev = dev_priv->dev;
3315 struct intel_crtc *crtc;
3316
19c8054c 3317 for_each_intel_crtc(dev, crtc) {
2d41c0b5
PB		 3318 int i, level, max_level = ilk_wm_max_level(dev);
3319 enum pipe pipe = crtc->pipe;
3320
5d374d96
DL		 3321 if (!new->dirty[pipe])
3322 continue;
8211bd5b 3323
5d374d96 3324 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3325
5d374d96
DL		 3326 for (level = 0; level <= max_level; level++) {
3327 for (i = 0; i < intel_num_planes(crtc); i++)
3328 I915_WRITE(PLANE_WM(pipe, i, level),
3329 new->plane[pipe][i][level]);
3330 I915_WRITE(CUR_WM(pipe, level),
4969d33e 3331 new->plane[pipe][PLANE_CURSOR][level]);
2d41c0b5 3332 }
5d374d96
DL		 3333 for (i = 0; i < intel_num_planes(crtc); i++)
3334 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3335 new->plane_trans[pipe][i]);
4969d33e
MR		 3336 I915_WRITE(CUR_WM_TRANS(pipe),
3337 new->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3338
2cd601c6 3339 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3340 skl_ddb_entry_write(dev_priv,
3341 PLANE_BUF_CFG(pipe, i),
3342 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3343 skl_ddb_entry_write(dev_priv,
3344 PLANE_NV12_BUF_CFG(pipe, i),
3345 &new->ddb.y_plane[pipe][i]);
3346 }
5d374d96
DL		 3347
3348 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
4969d33e 3349 &new->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5 3350 }
2d41c0b5
PB		 3351}
3352
0e8fb7ba
DL		 3353/*
3354 * When setting up a new DDB allocation arrangement, we need to correctly
3355 * sequence the times at which the new allocations for the pipes are taken into
3356 * account or we'll have pipes fetching from space previously allocated to
3357 * another pipe.
3358 *
3359 * Roughly the sequence looks like:
3360 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3361 * overlapping with a previous light-up pipe (another way to put it is:
3362 * pipes with their new allocation strickly included into their old ones).
3363 * 2. re-allocate the other pipes that get their allocation reduced
3364 * 3. allocate the pipes having their allocation increased
3365 *
3366 * Steps 1. and 2. are here to take care of the following case:
3367 * - Initially DDB looks like this:
3368 * | B | C |
3369 * - enable pipe A.
3370 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3371 * allocation
3372 * | A | B | C |
3373 *
3374 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3375 */
3376
d21b795c
DL		 3377static void
3378skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3379{
0e8fb7ba
DL		 3380 int plane;
3381
d21b795c
DL		 3382 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3383
dd740780 3384 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3385 I915_WRITE(PLANE_SURF(pipe, plane),
3386 I915_READ(PLANE_SURF(pipe, plane)));
3387 }
3388 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3389}
3390
3391static bool
3392skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3393 const struct skl_ddb_allocation *new,
3394 enum pipe pipe)
3395{
3396 uint16_t old_size, new_size;
3397
3398 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3399 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3400
3401 return old_size != new_size &&
3402 new->pipe[pipe].start >= old->pipe[pipe].start &&
3403 new->pipe[pipe].end <= old->pipe[pipe].end;
3404}
3405
3406static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3407 struct skl_wm_values *new_values)
3408{
3409 struct drm_device *dev = dev_priv->dev;
3410 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3411 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3412 struct intel_crtc *crtc;
3413 enum pipe pipe;
3414
3415 new_ddb = &new_values->ddb;
3416 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3417
3418 /*
3419 * First pass: flush the pipes with the new allocation contained into
3420 * the old space.
3421 *
3422 * We'll wait for the vblank on those pipes to ensure we can safely
3423 * re-allocate the freed space without this pipe fetching from it.
3424 */
3425 for_each_intel_crtc(dev, crtc) {
3426 if (!crtc->active)
3427 continue;
3428
3429 pipe = crtc->pipe;
3430
3431 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3432 continue;
3433
d21b795c 3434 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3435 intel_wait_for_vblank(dev, pipe);
3436
3437 reallocated[pipe] = true;
3438 }
3439
3440
3441 /*
3442 * Second pass: flush the pipes that are having their allocation
3443 * reduced, but overlapping with a previous allocation.
3444 *
3445 * Here as well we need to wait for the vblank to make sure the freed
3446 * space is not used anymore.
3447 */
3448 for_each_intel_crtc(dev, crtc) {
3449 if (!crtc->active)
3450 continue;
3451
3452 pipe = crtc->pipe;
3453
3454 if (reallocated[pipe])
3455 continue;
3456
3457 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3458 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3459 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3460 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3461 reallocated[pipe] = true;
0e8fb7ba 3462 }
0e8fb7ba
DL		 3463 }
3464
3465 /*
3466 * Third pass: flush the pipes that got more space allocated.
3467 *
3468 * We don't need to actively wait for the update here, next vblank
3469 * will just get more DDB space with the correct WM values.
3470 */
3471 for_each_intel_crtc(dev, crtc) {
3472 if (!crtc->active)
3473 continue;
3474
3475 pipe = crtc->pipe;
3476
3477 /*
3478 * At this point, only the pipes more space than before are
3479 * left to re-allocate.
3480 */
3481 if (reallocated[pipe])
3482 continue;
3483
d21b795c 3484 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3485 }
3486}
3487
2d41c0b5 3488static bool skl_update_pipe_wm(struct drm_crtc *crtc,
2d41c0b5
PB		 3489 struct skl_ddb_allocation *ddb, /* out */
3490 struct skl_pipe_wm *pipe_wm /* out */)
3491{
3492 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3493 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
2d41c0b5 3494
aa363136 3495 skl_allocate_pipe_ddb(cstate, ddb);
024c9045 3496 skl_compute_pipe_wm(cstate, ddb, pipe_wm);
2d41c0b5 3497
4e0963c7 3498 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
2d41c0b5
PB		 3499 return false;
3500
4e0963c7 3501 intel_crtc->wm.active.skl = *pipe_wm;
2cd601c6 3502
2d41c0b5
PB		 3503 return true;
3504}
3505
3506static void skl_update_other_pipe_wm(struct drm_device *dev,
3507 struct drm_crtc *crtc,
2d41c0b5
PB		 3508 struct skl_wm_values *r)
3509{
3510 struct intel_crtc *intel_crtc;
3511 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3512
3513 /*
3514 * If the WM update hasn't changed the allocation for this_crtc (the
3515 * crtc we are currently computing the new WM values for), other
3516 * enabled crtcs will keep the same allocation and we don't need to
3517 * recompute anything for them.
3518 */
3519 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3520 return;
3521
3522 /*
3523 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3524 * other active pipes need new DDB allocation and WM values.
3525 */
19c8054c 3526 for_each_intel_crtc(dev, intel_crtc) {
2d41c0b5
PB		 3527 struct skl_pipe_wm pipe_wm = {};
3528 bool wm_changed;
3529
3530 if (this_crtc->pipe == intel_crtc->pipe)
3531 continue;
3532
3533 if (!intel_crtc->active)
3534 continue;
3535
aa363136 3536 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
2d41c0b5
PB		 3537 &r->ddb, &pipe_wm);
3538
3539 /*
3540 * If we end up re-computing the other pipe WM values, it's
3541 * because it was really needed, so we expect the WM values to
3542 * be different.
3543 */
3544 WARN_ON(!wm_changed);
3545
024c9045 3546 skl_compute_wm_results(dev, &pipe_wm, r, intel_crtc);
2d41c0b5
PB		 3547 r->dirty[intel_crtc->pipe] = true;
3548 }
3549}
3550
adda50b8
BP		 3551static void skl_clear_wm(struct skl_wm_values *watermarks, enum pipe pipe)
3552{
3553 watermarks->wm_linetime[pipe] = 0;
3554 memset(watermarks->plane[pipe], 0,
3555 sizeof(uint32_t) * 8 * I915_MAX_PLANES);
adda50b8
BP		 3556 memset(watermarks->plane_trans[pipe],
3557 0, sizeof(uint32_t) * I915_MAX_PLANES);
4969d33e 3558 watermarks->plane_trans[pipe][PLANE_CURSOR] = 0;
adda50b8
BP		 3559
3560 /* Clear ddb entries for pipe */
3561 memset(&watermarks->ddb.pipe[pipe], 0, sizeof(struct skl_ddb_entry));
3562 memset(&watermarks->ddb.plane[pipe], 0,
3563 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
3564 memset(&watermarks->ddb.y_plane[pipe], 0,
3565 sizeof(struct skl_ddb_entry) * I915_MAX_PLANES);
4969d33e
MR		 3566 memset(&watermarks->ddb.plane[pipe][PLANE_CURSOR], 0,
3567 sizeof(struct skl_ddb_entry));
adda50b8
BP		 3568
3569}
3570
2d41c0b5
PB		 3571static void skl_update_wm(struct drm_crtc *crtc)
3572{
3573 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3574 struct drm_device *dev = crtc->dev;
3575 struct drm_i915_private *dev_priv = dev->dev_private;
2d41c0b5 3576 struct skl_wm_values *results = &dev_priv->wm.skl_results;
4e0963c7
MR		 3577 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3578 struct skl_pipe_wm *pipe_wm = &cstate->wm.optimal.skl;
2d41c0b5 3579
adda50b8
BP		 3580
3581 /* Clear all dirty flags */
3582 memset(results->dirty, 0, sizeof(bool) * I915_MAX_PIPES);
3583
3584 skl_clear_wm(results, intel_crtc->pipe);
2d41c0b5 3585
aa363136 3586 if (!skl_update_pipe_wm(crtc, &results->ddb, pipe_wm))
2d41c0b5
PB		 3587 return;
3588
4e0963c7 3589 skl_compute_wm_results(dev, pipe_wm, results, intel_crtc);
2d41c0b5
PB		 3590 results->dirty[intel_crtc->pipe] = true;
3591
aa363136 3592 skl_update_other_pipe_wm(dev, crtc, results);
2d41c0b5 3593 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3594 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3595
3596 /* store the new configuration */
3597 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3598}
3599
b9d5c839 3600static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 3601{
b9d5c839
VS		 3602 struct drm_device *dev = dev_priv->dev;
3603 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 3604 struct ilk_wm_maximums max;
aa363136 3605 struct intel_wm_config *config = &dev_priv->wm.config;
820c1980 3606 struct ilk_wm_values results = {};
77c122bc 3607 enum intel_ddb_partitioning partitioning;
261a27d1 3608
aa363136
MR		 3609 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_1_2, &max);
3610 ilk_wm_merge(dev, config, &max, &lp_wm_1_2);
a485bfb8
VS		 3611
3612 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 3613 if (INTEL_INFO(dev)->gen >= 7 &&
aa363136
MR		 3614 config->num_pipes_active == 1 && config->sprites_enabled) {
3615 ilk_compute_wm_maximums(dev, 1, config, INTEL_DDB_PART_5_6, &max);
3616 ilk_wm_merge(dev, config, &max, &lp_wm_5_6);
0362c781 3617
820c1980 3618 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3619 } else {
198a1e9b 3620 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3621 }
3622
198a1e9b 3623 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3624 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3625
820c1980 3626 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3627
820c1980 3628 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3629}
3630
b9d5c839
VS		 3631static void ilk_update_wm(struct drm_crtc *crtc)
3632{
3633 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
3634 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3635 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
b9d5c839
VS		 3636
3637 WARN_ON(cstate->base.active != intel_crtc->active);
3638
3639 /*
3640 * IVB workaround: must disable low power watermarks for at least
3641 * one frame before enabling scaling. LP watermarks can be re-enabled
3642 * when scaling is disabled.
3643 *
3644 * WaCxSRDisabledForSpriteScaling:ivb
3645 */
3646 if (cstate->disable_lp_wm) {
3647 ilk_disable_lp_wm(crtc->dev);
3648 intel_wait_for_vblank(crtc->dev, intel_crtc->pipe);
3649 }
3650
4e0963c7 3651 intel_crtc->wm.active.ilk = cstate->wm.optimal.ilk;
b9d5c839
VS		 3652
3653 ilk_program_watermarks(dev_priv);
3654}
3655
3078999f
PB		 3656static void skl_pipe_wm_active_state(uint32_t val,
3657 struct skl_pipe_wm *active,
3658 bool is_transwm,
3659 bool is_cursor,
3660 int i,
3661 int level)
3662{
3663 bool is_enabled = (val & PLANE_WM_EN) != 0;
3664
3665 if (!is_transwm) {
3666 if (!is_cursor) {
3667 active->wm[level].plane_en[i] = is_enabled;
3668 active->wm[level].plane_res_b[i] =
3669 val & PLANE_WM_BLOCKS_MASK;
3670 active->wm[level].plane_res_l[i] =
3671 (val >> PLANE_WM_LINES_SHIFT) &
3672 PLANE_WM_LINES_MASK;
3673 } else {
4969d33e
MR		 3674 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
3675 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 3676 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3677 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3678 (val >> PLANE_WM_LINES_SHIFT) &
3679 PLANE_WM_LINES_MASK;
3680 }
3681 } else {
3682 if (!is_cursor) {
3683 active->trans_wm.plane_en[i] = is_enabled;
3684 active->trans_wm.plane_res_b[i] =
3685 val & PLANE_WM_BLOCKS_MASK;
3686 active->trans_wm.plane_res_l[i] =
3687 (val >> PLANE_WM_LINES_SHIFT) &
3688 PLANE_WM_LINES_MASK;
3689 } else {
4969d33e
MR		 3690 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
3691 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 3692 val & PLANE_WM_BLOCKS_MASK;
4969d33e 3693 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 3694 (val >> PLANE_WM_LINES_SHIFT) &
3695 PLANE_WM_LINES_MASK;
3696 }
3697 }
3698}
3699
3700static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3701{
3702 struct drm_device *dev = crtc->dev;
3703 struct drm_i915_private *dev_priv = dev->dev_private;
3704 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3705 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3706 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3707 struct skl_pipe_wm *active = &cstate->wm.optimal.skl;
3078999f
PB		 3708 enum pipe pipe = intel_crtc->pipe;
3709 int level, i, max_level;
3710 uint32_t temp;
3711
3712 max_level = ilk_wm_max_level(dev);
3713
3714 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3715
3716 for (level = 0; level <= max_level; level++) {
3717 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3718 hw->plane[pipe][i][level] =
3719 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 3720 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 3721 }
3722
3723 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3724 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 3725 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 3726
3ef00284 3727 if (!intel_crtc->active)
3078999f
PB		 3728 return;
3729
3730 hw->dirty[pipe] = true;
3731
3732 active->linetime = hw->wm_linetime[pipe];
3733
3734 for (level = 0; level <= max_level; level++) {
3735 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3736 temp = hw->plane[pipe][i][level];
3737 skl_pipe_wm_active_state(temp, active, false,
3738 false, i, level);
3739 }
4969d33e 3740 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 3741 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3742 }
3743
3744 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3745 temp = hw->plane_trans[pipe][i];
3746 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3747 }
3748
4969d33e 3749 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 3750 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 3751
3752 intel_crtc->wm.active.skl = *active;
3078999f
PB		 3753}
3754
3755void skl_wm_get_hw_state(struct drm_device *dev)
3756{
a269c583
DL		 3757 struct drm_i915_private *dev_priv = dev->dev_private;
3758 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3759 struct drm_crtc *crtc;
3760
a269c583 3761 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3762 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3763 skl_pipe_wm_get_hw_state(crtc);
3764}
3765
243e6a44
VS		 3766static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3767{
3768 struct drm_device *dev = crtc->dev;
3769 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3770 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 3771 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7
MR		 3772 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
3773 struct intel_pipe_wm *active = &cstate->wm.optimal.ilk;
243e6a44 3774 enum pipe pipe = intel_crtc->pipe;
f0f59a00 3775 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 3776 [PIPE_A] = WM0_PIPEA_ILK,
3777 [PIPE_B] = WM0_PIPEB_ILK,
3778 [PIPE_C] = WM0_PIPEC_IVB,
3779 };
3780
3781 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3782 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3783 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3784
3ef00284 3785 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3786
3787 if (active->pipe_enabled) {
243e6a44
VS		 3788 u32 tmp = hw->wm_pipe[pipe];
3789
3790 /*
3791 * For active pipes LP0 watermark is marked as
3792 * enabled, and LP1+ watermaks as disabled since
3793 * we can't really reverse compute them in case
3794 * multiple pipes are active.
3795 */
3796 active->wm[0].enable = true;
3797 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3798 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3799 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3800 active->linetime = hw->wm_linetime[pipe];
3801 } else {
3802 int level, max_level = ilk_wm_max_level(dev);
3803
3804 /*
3805 * For inactive pipes, all watermark levels
3806 * should be marked as enabled but zeroed,
3807 * which is what we'd compute them to.
3808 */
3809 for (level = 0; level <= max_level; level++)
3810 active->wm[level].enable = true;
3811 }
4e0963c7
MR		 3812
3813 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 3814}
3815
6eb1a681
VS		 3816#define _FW_WM(value, plane) \
3817 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3818#define _FW_WM_VLV(value, plane) \
3819 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3820
3821static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3822 struct vlv_wm_values *wm)
3823{
3824 enum pipe pipe;
3825 uint32_t tmp;
3826
3827 for_each_pipe(dev_priv, pipe) {
3828 tmp = I915_READ(VLV_DDL(pipe));
3829
3830 wm->ddl[pipe].primary =
3831 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3832 wm->ddl[pipe].cursor =
3833 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3834 wm->ddl[pipe].sprite[0] =
3835 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3836 wm->ddl[pipe].sprite[1] =
3837 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3838 }
3839
3840 tmp = I915_READ(DSPFW1);
3841 wm->sr.plane = _FW_WM(tmp, SR);
3842 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3843 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3844 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3845
3846 tmp = I915_READ(DSPFW2);
3847 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3848 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3849 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3850
3851 tmp = I915_READ(DSPFW3);
3852 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3853
3854 if (IS_CHERRYVIEW(dev_priv)) {
3855 tmp = I915_READ(DSPFW7_CHV);
3856 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3857 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3858
3859 tmp = I915_READ(DSPFW8_CHV);
3860 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
3861 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
3862
3863 tmp = I915_READ(DSPFW9_CHV);
3864 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
3865 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
3866
3867 tmp = I915_READ(DSPHOWM);
3868 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3869 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
3870 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
3871 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
3872 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3873 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3874 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3875 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3876 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3877 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3878 } else {
3879 tmp = I915_READ(DSPFW7);
3880 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
3881 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
3882
3883 tmp = I915_READ(DSPHOWM);
3884 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
3885 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
3886 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
3887 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
3888 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
3889 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
3890 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
3891 }
3892}
3893
3894#undef _FW_WM
3895#undef _FW_WM_VLV
3896
3897void vlv_wm_get_hw_state(struct drm_device *dev)
3898{
3899 struct drm_i915_private *dev_priv = to_i915(dev);
3900 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
3901 struct intel_plane *plane;
3902 enum pipe pipe;
3903 u32 val;
3904
3905 vlv_read_wm_values(dev_priv, wm);
3906
3907 for_each_intel_plane(dev, plane) {
3908 switch (plane->base.type) {
3909 int sprite;
3910 case DRM_PLANE_TYPE_CURSOR:
3911 plane->wm.fifo_size = 63;
3912 break;
3913 case DRM_PLANE_TYPE_PRIMARY:
3914 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
3915 break;
3916 case DRM_PLANE_TYPE_OVERLAY:
3917 sprite = plane->plane;
3918 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
3919 break;
3920 }
3921 }
3922
3923 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
3924 wm->level = VLV_WM_LEVEL_PM2;
3925
3926 if (IS_CHERRYVIEW(dev_priv)) {
3927 mutex_lock(&dev_priv->rps.hw_lock);
3928
3929 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
3930 if (val & DSP_MAXFIFO_PM5_ENABLE)
3931 wm->level = VLV_WM_LEVEL_PM5;
3932
58590c14
VS		 3933 /*
3934 * If DDR DVFS is disabled in the BIOS, Punit
3935 * will never ack the request. So if that happens
3936 * assume we don't have to enable/disable DDR DVFS
3937 * dynamically. To test that just set the REQ_ACK
3938 * bit to poke the Punit, but don't change the
3939 * HIGH/LOW bits so that we don't actually change
3940 * the current state.
3941 */
6eb1a681 3942 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 3943 val |= FORCE_DDR_FREQ_REQ_ACK;
3944 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
3945
3946 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
3947 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
3948 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
3949 "assuming DDR DVFS is disabled\n");
3950 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
3951 } else {
3952 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
3953 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
3954 wm->level = VLV_WM_LEVEL_DDR_DVFS;
3955 }
6eb1a681
VS		 3956
3957 mutex_unlock(&dev_priv->rps.hw_lock);
3958 }
3959
3960 for_each_pipe(dev_priv, pipe)
3961 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
3962 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
3963 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
3964
3965 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
3966 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
3967}
3968
243e6a44
VS		 3969void ilk_wm_get_hw_state(struct drm_device *dev)
3970{
3971 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3972 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3973 struct drm_crtc *crtc;
3974
70e1e0ec 3975 for_each_crtc(dev, crtc)
243e6a44
VS		 3976 ilk_pipe_wm_get_hw_state(crtc);
3977
3978 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
3979 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
3980 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
3981
3982 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 3983 if (INTEL_INFO(dev)->gen >= 7) {
3984 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
3985 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
3986 }
243e6a44 3987
a42a5719 3988 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 3989 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
3990 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
3991 else if (IS_IVYBRIDGE(dev))
3992 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
3993 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 3994
3995 hw->enable_fbc_wm =
3996 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
3997}
3998
b445e3b0
ED		 3999/**
4000 * intel_update_watermarks - update FIFO watermark values based on current modes
4001 *
4002 * Calculate watermark values for the various WM regs based on current mode
4003 * and plane configuration.
4004 *
4005 * There are several cases to deal with here:
4006 * - normal (i.e. non-self-refresh)
4007 * - self-refresh (SR) mode
4008 * - lines are large relative to FIFO size (buffer can hold up to 2)
4009 * - lines are small relative to FIFO size (buffer can hold more than 2
4010 * lines), so need to account for TLB latency
4011 *
4012 * The normal calculation is:
4013 * watermark = dotclock * bytes per pixel * latency
4014 * where latency is platform & configuration dependent (we assume pessimal
4015 * values here).
4016 *
4017 * The SR calculation is:
4018 * watermark = (trunc(latency/line time)+1) * surface width *
4019 * bytes per pixel
4020 * where
4021 * line time = htotal / dotclock
4022 * surface width = hdisplay for normal plane and 64 for cursor
4023 * and latency is assumed to be high, as above.
4024 *
4025 * The final value programmed to the register should always be rounded up,
4026 * and include an extra 2 entries to account for clock crossings.
4027 *
4028 * We don't use the sprite, so we can ignore that. And on Crestline we have
4029 * to set the non-SR watermarks to 8.
4030 */
46ba614c 4031void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4032{
46ba614c 4033 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4034
4035 if (dev_priv->display.update_wm)
46ba614c 4036 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4037}
4038
9270388e
DV		 4039/**
4040 * Lock protecting IPS related data structures
9270388e
DV		 4041 */
4042DEFINE_SPINLOCK(mchdev_lock);
4043
4044/* Global for IPS driver to get at the current i915 device. Protected by
4045 * mchdev_lock. */
4046static struct drm_i915_private *i915_mch_dev;
4047
2b4e57bd
ED		 4048bool ironlake_set_drps(struct drm_device *dev, u8 val)
4049{
4050 struct drm_i915_private *dev_priv = dev->dev_private;
4051 u16 rgvswctl;
4052
9270388e
DV		 4053 assert_spin_locked(&mchdev_lock);
4054
2b4e57bd
ED		 4055 rgvswctl = I915_READ16(MEMSWCTL);
4056 if (rgvswctl & MEMCTL_CMD_STS) {
4057 DRM_DEBUG("gpu busy, RCS change rejected\n");
4058 return false; /* still busy with another command */
4059 }
4060
4061 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4062 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4063 I915_WRITE16(MEMSWCTL, rgvswctl);
4064 POSTING_READ16(MEMSWCTL);
4065
4066 rgvswctl |= MEMCTL_CMD_STS;
4067 I915_WRITE16(MEMSWCTL, rgvswctl);
4068
4069 return true;
4070}
4071
8090c6b9 4072static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4073{
4074 struct drm_i915_private *dev_priv = dev->dev_private;
4075 u32 rgvmodectl = I915_READ(MEMMODECTL);
4076 u8 fmax, fmin, fstart, vstart;
4077
9270388e
DV		 4078 spin_lock_irq(&mchdev_lock);
4079
2b4e57bd
ED		 4080 /* Enable temp reporting */
4081 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4082 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4083
4084 /* 100ms RC evaluation intervals */
4085 I915_WRITE(RCUPEI, 100000);
4086 I915_WRITE(RCDNEI, 100000);
4087
4088 /* Set max/min thresholds to 90ms and 80ms respectively */
4089 I915_WRITE(RCBMAXAVG, 90000);
4090 I915_WRITE(RCBMINAVG, 80000);
4091
4092 I915_WRITE(MEMIHYST, 1);
4093
4094 /* Set up min, max, and cur for interrupt handling */
4095 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4096 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4097 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4098 MEMMODE_FSTART_SHIFT;
4099
616847e7 4100 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4101 PXVFREQ_PX_SHIFT;
4102
20e4d407
DV		 4103 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4104 dev_priv->ips.fstart = fstart;
2b4e57bd 4105
20e4d407
DV		 4106 dev_priv->ips.max_delay = fstart;
4107 dev_priv->ips.min_delay = fmin;
4108 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4109
4110 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4111 fmax, fmin, fstart);
4112
4113 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4114
4115 /*
4116 * Interrupts will be enabled in ironlake_irq_postinstall
4117 */
4118
4119 I915_WRITE(VIDSTART, vstart);
4120 POSTING_READ(VIDSTART);
4121
4122 rgvmodectl |= MEMMODE_SWMODE_EN;
4123 I915_WRITE(MEMMODECTL, rgvmodectl);
4124
9270388e 4125 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4126 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4127 mdelay(1);
2b4e57bd
ED		 4128
4129 ironlake_set_drps(dev, fstart);
4130
7d81c3e0
VS		 4131 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4132 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4133 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4134 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4135 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4136
4137 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4138}
4139
8090c6b9 4140static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4141{
4142 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4143 u16 rgvswctl;
4144
4145 spin_lock_irq(&mchdev_lock);
4146
4147 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4148
4149 /* Ack interrupts, disable EFC interrupt */
4150 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4151 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4152 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4153 I915_WRITE(DEIIR, DE_PCU_EVENT);
4154 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4155
4156 /* Go back to the starting frequency */
20e4d407 4157 ironlake_set_drps(dev, dev_priv->ips.fstart);
dd92d8de 4158 mdelay(1);
2b4e57bd
ED		 4159 rgvswctl |= MEMCTL_CMD_STS;
4160 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4161 mdelay(1);
2b4e57bd 4162
9270388e 4163 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4164}
4165
acbe9475
DV		 4166/* There's a funny hw issue where the hw returns all 0 when reading from
4167 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4168 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4169 * all limits and the gpu stuck at whatever frequency it is at atm).
4170 */
74ef1173 4171static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4172{
7b9e0ae6 4173 u32 limits;
2b4e57bd 4174
20b46e59
DV		 4175 /* Only set the down limit when we've reached the lowest level to avoid
4176 * getting more interrupts, otherwise leave this clear. This prevents a
4177 * race in the hw when coming out of rc6: There's a tiny window where
4178 * the hw runs at the minimal clock before selecting the desired
4179 * frequency, if the down threshold expires in that window we will not
4180 * receive a down interrupt. */
74ef1173
AG		 4181 if (IS_GEN9(dev_priv->dev)) {
4182 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4183 if (val <= dev_priv->rps.min_freq_softlimit)
4184 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4185 } else {
4186 limits = dev_priv->rps.max_freq_softlimit << 24;
4187 if (val <= dev_priv->rps.min_freq_softlimit)
4188 limits |= dev_priv->rps.min_freq_softlimit << 16;
4189 }
20b46e59
DV		 4190
4191 return limits;
4192}
4193
dd75fdc8
CW		 4194static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4195{
4196 int new_power;
8a586437
AG		 4197 u32 threshold_up = 0, threshold_down = 0; /* in % */
4198 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4199
4200 new_power = dev_priv->rps.power;
4201 switch (dev_priv->rps.power) {
4202 case LOW_POWER:
b39fb297 4203 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4204 new_power = BETWEEN;
4205 break;
4206
4207 case BETWEEN:
b39fb297 4208 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4209 new_power = LOW_POWER;
b39fb297 4210 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4211 new_power = HIGH_POWER;
4212 break;
4213
4214 case HIGH_POWER:
b39fb297 4215 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4216 new_power = BETWEEN;
4217 break;
4218 }
4219 /* Max/min bins are special */
aed242ff 4220 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4221 new_power = LOW_POWER;
aed242ff 4222 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4223 new_power = HIGH_POWER;
4224 if (new_power == dev_priv->rps.power)
4225 return;
4226
4227 /* Note the units here are not exactly 1us, but 1280ns. */
4228 switch (new_power) {
4229 case LOW_POWER:
4230 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4231 ei_up = 16000;
4232 threshold_up = 95;
dd75fdc8
CW		 4233
4234 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4235 ei_down = 32000;
4236 threshold_down = 85;
dd75fdc8
CW		 4237 break;
4238
4239 case BETWEEN:
4240 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4241 ei_up = 13000;
4242 threshold_up = 90;
dd75fdc8
CW		 4243
4244 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4245 ei_down = 32000;
4246 threshold_down = 75;
dd75fdc8
CW		 4247 break;
4248
4249 case HIGH_POWER:
4250 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4251 ei_up = 10000;
4252 threshold_up = 85;
dd75fdc8
CW		 4253
4254 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4255 ei_down = 32000;
4256 threshold_down = 60;
dd75fdc8
CW		 4257 break;
4258 }
4259
8a586437
AG		 4260 I915_WRITE(GEN6_RP_UP_EI,
4261 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4262 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4263 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4264
4265 I915_WRITE(GEN6_RP_DOWN_EI,
4266 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4267 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4268 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4269
4270 I915_WRITE(GEN6_RP_CONTROL,
4271 GEN6_RP_MEDIA_TURBO |
4272 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4273 GEN6_RP_MEDIA_IS_GFX |
4274 GEN6_RP_ENABLE |
4275 GEN6_RP_UP_BUSY_AVG |
4276 GEN6_RP_DOWN_IDLE_AVG);
4277
dd75fdc8 4278 dev_priv->rps.power = new_power;
8fb55197
CW		 4279 dev_priv->rps.up_threshold = threshold_up;
4280 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4281 dev_priv->rps.last_adj = 0;
4282}
4283
2876ce73
CW		 4284static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4285{
4286 u32 mask = 0;
4287
4288 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4289 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4290 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4291 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4292
7b3c29f6
CW		 4293 mask &= dev_priv->pm_rps_events;
4294
59d02a1f 4295 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4296}
4297
b8a5ff8d
JM		 4298/* gen6_set_rps is called to update the frequency request, but should also be
4299 * called when the range (min_delay and max_delay) is modified so that we can
4300 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4301static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4302{
4303 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4304
23eafea6 4305 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4306 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1))
23eafea6
SAK		 4307 return;
4308
4fc688ce 4309 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4310 WARN_ON(val > dev_priv->rps.max_freq);
4311 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4312
eb64cad1
CW		 4313 /* min/max delay may still have been modified so be sure to
4314 * write the limits value.
4315 */
4316 if (val != dev_priv->rps.cur_freq) {
4317 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4318
5704195c
AG		 4319 if (IS_GEN9(dev))
4320 I915_WRITE(GEN6_RPNSWREQ,
4321 GEN9_FREQUENCY(val));
4322 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4323 I915_WRITE(GEN6_RPNSWREQ,
4324 HSW_FREQUENCY(val));
4325 else
4326 I915_WRITE(GEN6_RPNSWREQ,
4327 GEN6_FREQUENCY(val) |
4328 GEN6_OFFSET(0) |
4329 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4330 }
7b9e0ae6 4331
7b9e0ae6
CW		 4332 /* Make sure we continue to get interrupts
4333 * until we hit the minimum or maximum frequencies.
4334 */
74ef1173 4335 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4336 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4337
d5570a72
BW		 4338 POSTING_READ(GEN6_RPNSWREQ);
4339
b39fb297 4340 dev_priv->rps.cur_freq = val;
0f94592e 4341 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4342}
4343
ffe02b40
VS		 4344static void valleyview_set_rps(struct drm_device *dev, u8 val)
4345{
4346 struct drm_i915_private *dev_priv = dev->dev_private;
4347
4348 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4349 WARN_ON(val > dev_priv->rps.max_freq);
4350 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4351
4352 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4353 "Odd GPU freq value\n"))
4354 val &= ~1;
4355
cd25dd5b
D		 4356 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4357
8fb55197 4358 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4359 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4360 if (!IS_CHERRYVIEW(dev_priv))
4361 gen6_set_rps_thresholds(dev_priv, val);
4362 }
ffe02b40 4363
ffe02b40
VS		 4364 dev_priv->rps.cur_freq = val;
4365 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4366}
4367
a7f6e231 4368/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4369 *
4370 * * If Gfx is Idle, then
a7f6e231
D		 4371 * 1. Forcewake Media well.
4372 * 2. Request idle freq.
4373 * 3. Release Forcewake of Media well.
76c3552f
D		 4374*/
4375static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4376{
aed242ff 4377 u32 val = dev_priv->rps.idle_freq;
5549d25f 4378
aed242ff 4379 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4380 return;
4381
a7f6e231
D		 4382 /* Wake up the media well, as that takes a lot less
4383 * power than the Render well. */
4384 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4385 valleyview_set_rps(dev_priv->dev, val);
4386 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4387}
4388
43cf3bf0
CW		 4389void gen6_rps_busy(struct drm_i915_private *dev_priv)
4390{
4391 mutex_lock(&dev_priv->rps.hw_lock);
4392 if (dev_priv->rps.enabled) {
4393 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4394 gen6_rps_reset_ei(dev_priv);
4395 I915_WRITE(GEN6_PMINTRMSK,
4396 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4397 }
4398 mutex_unlock(&dev_priv->rps.hw_lock);
4399}
4400
b29c19b6
CW		 4401void gen6_rps_idle(struct drm_i915_private *dev_priv)
4402{
691bb717
DL		 4403 struct drm_device *dev = dev_priv->dev;
4404
b29c19b6 4405 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4406 if (dev_priv->rps.enabled) {
666a4537 4407 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
76c3552f 4408 vlv_set_rps_idle(dev_priv);
7526ed79 4409 else
aed242ff 4410 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4411 dev_priv->rps.last_adj = 0;
43cf3bf0 4412 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4413 }
8d3afd7d 4414 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4415
8d3afd7d 4416 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4417 while (!list_empty(&dev_priv->rps.clients))
4418 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4419 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4420}
4421
1854d5ca 4422void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4423 struct intel_rps_client *rps,
4424 unsigned long submitted)
b29c19b6 4425{
8d3afd7d
CW		 4426 /* This is intentionally racy! We peek at the state here, then
4427 * validate inside the RPS worker.
4428 */
4429 if (!(dev_priv->mm.busy &&
4430 dev_priv->rps.enabled &&
4431 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4432 return;
43cf3bf0 4433
e61b9958
CW		 4434 /* Force a RPS boost (and don't count it against the client) if
4435 * the GPU is severely congested.
4436 */
d0bc54f2 4437 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4438 rps = NULL;
4439
8d3afd7d
CW		 4440 spin_lock(&dev_priv->rps.client_lock);
4441 if (rps == NULL || list_empty(&rps->link)) {
4442 spin_lock_irq(&dev_priv->irq_lock);
4443 if (dev_priv->rps.interrupts_enabled) {
4444 dev_priv->rps.client_boost = true;
4445 queue_work(dev_priv->wq, &dev_priv->rps.work);
4446 }
4447 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4448
2e1b8730
CW		 4449 if (rps != NULL) {
4450 list_add(&rps->link, &dev_priv->rps.clients);
4451 rps->boosts++;
1854d5ca
CW		 4452 } else
4453 dev_priv->rps.boosts++;
c0951f0c 4454 }
8d3afd7d 4455 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4456}
4457
ffe02b40 4458void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4459{
666a4537 4460 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev))
ffe02b40
VS		 4461 valleyview_set_rps(dev, val);
4462 else
4463 gen6_set_rps(dev, val);
0a073b84
JB		 4464}
4465
20e49366
ZW		 4466static void gen9_disable_rps(struct drm_device *dev)
4467{
4468 struct drm_i915_private *dev_priv = dev->dev_private;
4469
4470 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4471 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4472}
4473
44fc7d5c 4474static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4475{
4476 struct drm_i915_private *dev_priv = dev->dev_private;
4477
4478 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4479 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4480}
4481
38807746
D		 4482static void cherryview_disable_rps(struct drm_device *dev)
4483{
4484 struct drm_i915_private *dev_priv = dev->dev_private;
4485
4486 I915_WRITE(GEN6_RC_CONTROL, 0);
4487}
4488
44fc7d5c
DV		 4489static void valleyview_disable_rps(struct drm_device *dev)
4490{
4491 struct drm_i915_private *dev_priv = dev->dev_private;
4492
98a2e5f9
D		 4493 /* we're doing forcewake before Disabling RC6,
4494 * This what the BIOS expects when going into suspend */
59bad947 4495 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4496
44fc7d5c 4497 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4498
59bad947 4499 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4500}
4501
dc39fff7
BW		 4502static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4503{
666a4537 4504 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
91ca689a
ID		 4505 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4506 mode = GEN6_RC_CTL_RC6_ENABLE;
4507 else
4508 mode = 0;
4509 }
58abf1da
RV		 4510 if (HAS_RC6p(dev))
4511 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4512 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4513 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4514 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4515
4516 else
4517 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4518 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4519}
4520
e6069ca8 4521static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4522{
e7d66d89
DV		 4523 /* No RC6 before Ironlake and code is gone for ilk. */
4524 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4525 return 0;
4526
456470eb 4527 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4528 if (enable_rc6 >= 0) {
4529 int mask;
4530
58abf1da 4531 if (HAS_RC6p(dev))
e6069ca8
ID		 4532 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4533 INTEL_RC6pp_ENABLE;
4534 else
4535 mask = INTEL_RC6_ENABLE;
4536
4537 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4538 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4539 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4540
4541 return enable_rc6 & mask;
4542 }
2b4e57bd 4543
8bade1ad 4544 if (IS_IVYBRIDGE(dev))
cca84a1f 4545 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4546
4547 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4548}
4549
e6069ca8
ID		 4550int intel_enable_rc6(const struct drm_device *dev)
4551{
4552 return i915.enable_rc6;
4553}
4554
93ee2920 4555static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4556{
93ee2920
TR		 4557 struct drm_i915_private *dev_priv = dev->dev_private;
4558 uint32_t rp_state_cap;
4559 u32 ddcc_status = 0;
4560 int ret;
4561
3280e8b0
BW		 4562 /* All of these values are in units of 50MHz */
4563 dev_priv->rps.cur_freq = 0;
93ee2920 4564 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4565 if (IS_BROXTON(dev)) {
4566 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4567 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4568 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4569 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4570 } else {
4571 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4572 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4573 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4574 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4575 }
4576
3280e8b0
BW		 4577 /* hw_max = RP0 until we check for overclocking */
4578 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4579
93ee2920 4580 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
ef11bdb3
RV		 4581 if (IS_HASWELL(dev) || IS_BROADWELL(dev) ||
4582 IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
93ee2920
TR		 4583 ret = sandybridge_pcode_read(dev_priv,
4584 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4585 &ddcc_status);
4586 if (0 == ret)
4587 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4588 clamp_t(u8,
4589 ((ddcc_status >> 8) & 0xff),
4590 dev_priv->rps.min_freq,
4591 dev_priv->rps.max_freq);
93ee2920
TR		 4592 }
4593
ef11bdb3 4594 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
c5e0688c
AG		 4595 /* Store the frequency values in 16.66 MHZ units, which is
4596 the natural hardware unit for SKL */
4597 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4598 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4599 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4600 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4601 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4602 }
4603
aed242ff
CW		 4604 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4605
3280e8b0
BW		 4606 /* Preserve min/max settings in case of re-init */
4607 if (dev_priv->rps.max_freq_softlimit == 0)
4608 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4609
93ee2920
TR		 4610 if (dev_priv->rps.min_freq_softlimit == 0) {
4611 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4612 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4613 max_t(int, dev_priv->rps.efficient_freq,
4614 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4615 else
4616 dev_priv->rps.min_freq_softlimit =
4617 dev_priv->rps.min_freq;
4618 }
3280e8b0
BW		 4619}
4620
b6fef0ef 4621/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4622static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4623{
4624 struct drm_i915_private *dev_priv = dev->dev_private;
4625
4626 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4627
ba1c554c
DL		 4628 gen6_init_rps_frequencies(dev);
4629
23eafea6 4630 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
e87a005d 4631 if (IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
23eafea6
SAK		 4632 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4633 return;
4634 }
4635
0beb059a
AG		 4636 /* Program defaults and thresholds for RPS*/
4637 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4638 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4639
4640 /* 1 second timeout*/
4641 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4642 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4643
b6fef0ef 4644 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4645
0beb059a
AG		 4646 /* Leaning on the below call to gen6_set_rps to program/setup the
4647 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4648 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4649 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4650 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4651
4652 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4653}
4654
4655static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4656{
4657 struct drm_i915_private *dev_priv = dev->dev_private;
4658 struct intel_engine_cs *ring;
4659 uint32_t rc6_mask = 0;
4660 int unused;
4661
4662 /* 1a: Software RC state - RC0 */
4663 I915_WRITE(GEN6_RC_STATE, 0);
4664
4665 /* 1b: Get forcewake during program sequence. Although the driver
4666 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4667 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4668
4669 /* 2a: Disable RC states. */
4670 I915_WRITE(GEN6_RC_CONTROL, 0);
4671
4672 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 4673
4674 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
e7674b8c 4675 if (IS_SKYLAKE(dev))
63a4dec2
SAK		 4676 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
4677 else
4678 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 4679 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4680 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4681 for_each_ring(ring, dev_priv, unused)
4682 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
97c322e7
SAK		 4683
4684 if (HAS_GUC_UCODE(dev))
4685 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
4686
20e49366 4687 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 4688
38c23527
ZW		 4689 /* 2c: Program Coarse Power Gating Policies. */
4690 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4691 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4692
20e49366
ZW		 4693 /* 3a: Enable RC6 */
4694 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4695 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4696 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4697 "on" : "off");
3e7732a0 4698 /* WaRsUseTimeoutMode */
e87a005d 4699 if (IS_SKL_REVID(dev, 0, SKL_REVID_D0) ||
cbdc12a9 4700 IS_BXT_REVID(dev, 0, BXT_REVID_A1)) {
3e7732a0 4701 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 4702 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4703 GEN7_RC_CTL_TO_MODE |
4704 rc6_mask);
3e7732a0
SAK		 4705 } else {
4706 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 4707 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4708 GEN6_RC_CTL_EI_MODE(1) |
4709 rc6_mask);
3e7732a0 4710 }
20e49366 4711
cb07bae0
SK		 4712 /*
4713 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 4714 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 4715 */
06e668ac 4716 if (NEEDS_WaRsDisableCoarsePowerGating(dev))
f2d2fe95
SAK		 4717 I915_WRITE(GEN9_PG_ENABLE, 0);
4718 else
4719 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4720 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 4721
59bad947 4722 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4723
4724}
4725
6edee7f3
BW		 4726static void gen8_enable_rps(struct drm_device *dev)
4727{
4728 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4729 struct intel_engine_cs *ring;
93ee2920 4730 uint32_t rc6_mask = 0;
6edee7f3
BW		 4731 int unused;
4732
4733 /* 1a: Software RC state - RC0 */
4734 I915_WRITE(GEN6_RC_STATE, 0);
4735
4736 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4737 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4738 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4739
4740 /* 2a: Disable RC states. */
4741 I915_WRITE(GEN6_RC_CONTROL, 0);
4742
93ee2920
TR		 4743 /* Initialize rps frequencies */
4744 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4745
4746 /* 2b: Program RC6 thresholds.*/
4747 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4748 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4749 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4750 for_each_ring(ring, dev_priv, unused)
4751 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4752 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4753 if (IS_BROADWELL(dev))
4754 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4755 else
4756 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4757
4758 /* 3: Enable RC6 */
4759 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4760 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4761 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4762 if (IS_BROADWELL(dev))
4763 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4764 GEN7_RC_CTL_TO_MODE |
4765 rc6_mask);
4766 else
4767 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4768 GEN6_RC_CTL_EI_MODE(1) |
4769 rc6_mask);
6edee7f3
BW		 4770
4771 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4772 I915_WRITE(GEN6_RPNSWREQ,
4773 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4774 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4775 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4776 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4777 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4778
4779 /* Docs recommend 900MHz, and 300 MHz respectively */
4780 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4781 dev_priv->rps.max_freq_softlimit << 24 |
4782 dev_priv->rps.min_freq_softlimit << 16);
4783
4784 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4785 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4786 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4787 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4788
4789 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4790
4791 /* 5: Enable RPS */
7526ed79
DV		 4792 I915_WRITE(GEN6_RP_CONTROL,
4793 GEN6_RP_MEDIA_TURBO |
4794 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4795 GEN6_RP_MEDIA_IS_GFX |
4796 GEN6_RP_ENABLE |
4797 GEN6_RP_UP_BUSY_AVG |
4798 GEN6_RP_DOWN_IDLE_AVG);
4799
4800 /* 6: Ring frequency + overclocking (our driver does this later */
4801
c7f3153a 4802 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4803 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4804
59bad947 4805 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4806}
4807
79f5b2c7 4808static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4809{
79f5b2c7 4810 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4811 struct intel_engine_cs *ring;
d060c169 4812 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4813 u32 gtfifodbg;
2b4e57bd 4814 int rc6_mode;
42c0526c 4815 int i, ret;
2b4e57bd 4816
4fc688ce 4817 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4818
2b4e57bd
ED		 4819 /* Here begins a magic sequence of register writes to enable
4820 * auto-downclocking.
4821 *
4822 * Perhaps there might be some value in exposing these to
4823 * userspace...
4824 */
4825 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4826
4827 /* Clear the DBG now so we don't confuse earlier errors */
4828 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4829 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4830 I915_WRITE(GTFIFODBG, gtfifodbg);
4831 }
4832
59bad947 4833 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4834
93ee2920
TR		 4835 /* Initialize rps frequencies */
4836 gen6_init_rps_frequencies(dev);
dd0a1aa1 4837
2b4e57bd
ED		 4838 /* disable the counters and set deterministic thresholds */
4839 I915_WRITE(GEN6_RC_CONTROL, 0);
4840
4841 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4842 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4843 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4844 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4845 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4846
b4519513
CW		 4847 for_each_ring(ring, dev_priv, i)
4848 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4849
4850 I915_WRITE(GEN6_RC_SLEEP, 0);
4851 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4852 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4853 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4854 else
4855 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4856 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4857 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4858
5a7dc92a 4859 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4860 rc6_mode = intel_enable_rc6(dev_priv->dev);
4861 if (rc6_mode & INTEL_RC6_ENABLE)
4862 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4863
5a7dc92a
ED		 4864 /* We don't use those on Haswell */
4865 if (!IS_HASWELL(dev)) {
4866 if (rc6_mode & INTEL_RC6p_ENABLE)
4867 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4868
5a7dc92a
ED		 4869 if (rc6_mode & INTEL_RC6pp_ENABLE)
4870 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4871 }
2b4e57bd 4872
dc39fff7 4873 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4874
4875 I915_WRITE(GEN6_RC_CONTROL,
4876 rc6_mask |
4877 GEN6_RC_CTL_EI_MODE(1) |
4878 GEN6_RC_CTL_HW_ENABLE);
4879
dd75fdc8
CW		 4880 /* Power down if completely idle for over 50ms */
4881 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4882 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4883
42c0526c 4884 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4885 if (ret)
42c0526c 4886 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4887
4888 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4889 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4890 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 4891 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 4892 (pcu_mbox & 0xff) * 50);
b39fb297 4893 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 4894 }
4895
dd75fdc8 4896 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4897 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 4898
31643d54
BW		 4899 rc6vids = 0;
4900 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
4901 if (IS_GEN6(dev) && ret) {
4902 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
4903 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
4904 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
4905 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
4906 rc6vids &= 0xffff00;
4907 rc6vids |= GEN6_ENCODE_RC6_VID(450);
4908 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
4909 if (ret)
4910 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
4911 }
4912
59bad947 4913 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 4914}
4915
c2bc2fc5 4916static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 4917{
79f5b2c7 4918 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 4919 int min_freq = 15;
3ebecd07
CW		 4920 unsigned int gpu_freq;
4921 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 4922 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 4923 int scaling_factor = 180;
eda79642 4924 struct cpufreq_policy *policy;
2b4e57bd 4925
4fc688ce 4926 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4927
eda79642
BW		 4928 policy = cpufreq_cpu_get(0);
4929 if (policy) {
4930 max_ia_freq = policy->cpuinfo.max_freq;
4931 cpufreq_cpu_put(policy);
4932 } else {
4933 /*
4934 * Default to measured freq if none found, PCU will ensure we
4935 * don't go over
4936 */
2b4e57bd 4937 max_ia_freq = tsc_khz;
eda79642 4938 }
2b4e57bd
ED		 4939
4940 /* Convert from kHz to MHz */
4941 max_ia_freq /= 1000;
4942
153b4b95 4943 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 4944 /* convert DDR frequency from units of 266.6MHz to bandwidth */
4945 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 4946
ef11bdb3 4947 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4948 /* Convert GT frequency to 50 HZ units */
4949 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
4950 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
4951 } else {
4952 min_gpu_freq = dev_priv->rps.min_freq;
4953 max_gpu_freq = dev_priv->rps.max_freq;
4954 }
4955
2b4e57bd
ED		 4956 /*
4957 * For each potential GPU frequency, load a ring frequency we'd like
4958 * to use for memory access. We do this by specifying the IA frequency
4959 * the PCU should use as a reference to determine the ring frequency.
4960 */
4c8c7743
AG		 4961 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
4962 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 4963 unsigned int ia_freq = 0, ring_freq = 0;
4964
ef11bdb3 4965 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev)) {
4c8c7743
AG		 4966 /*
4967 * ring_freq = 2 * GT. ring_freq is in 100MHz units
4968 * No floor required for ring frequency on SKL.
4969 */
4970 ring_freq = gpu_freq;
4971 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 4972 /* max(2 * GT, DDR). NB: GT is 50MHz units */
4973 ring_freq = max(min_ring_freq, gpu_freq);
4974 } else if (IS_HASWELL(dev)) {
f6aca45c 4975 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 4976 ring_freq = max(min_ring_freq, ring_freq);
4977 /* leave ia_freq as the default, chosen by cpufreq */
4978 } else {
4979 /* On older processors, there is no separate ring
4980 * clock domain, so in order to boost the bandwidth
4981 * of the ring, we need to upclock the CPU (ia_freq).
4982 *
4983 * For GPU frequencies less than 750MHz,
4984 * just use the lowest ring freq.
4985 */
4986 if (gpu_freq < min_freq)
4987 ia_freq = 800;
4988 else
4989 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
4990 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
4991 }
2b4e57bd 4992
42c0526c
BW		 4993 sandybridge_pcode_write(dev_priv,
4994 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 4995 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
4996 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
4997 gpu_freq);
2b4e57bd 4998 }
2b4e57bd
ED		 4999}
5000
c2bc2fc5
ID		 5001void gen6_update_ring_freq(struct drm_device *dev)
5002{
5003 struct drm_i915_private *dev_priv = dev->dev_private;
5004
97d3308a 5005 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5006 return;
5007
5008 mutex_lock(&dev_priv->rps.hw_lock);
5009 __gen6_update_ring_freq(dev);
5010 mutex_unlock(&dev_priv->rps.hw_lock);
5011}
5012
03af2045 5013static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5014{
095acd5f 5015 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5016 u32 val, rp0;
5017
5b5929cb 5018 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5019
5b5929cb
JN		 5020 switch (INTEL_INFO(dev)->eu_total) {
5021 case 8:
5022 /* (2 * 4) config */
5023 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5024 break;
5025 case 12:
5026 /* (2 * 6) config */
5027 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5028 break;
5029 case 16:
5030 /* (2 * 8) config */
5031 default:
5032 /* Setting (2 * 8) Min RP0 for any other combination */
5033 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5034 break;
095acd5f 5035 }
5b5929cb
JN		 5036
5037 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5038
2b6b3a09
D		 5039 return rp0;
5040}
5041
5042static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5043{
5044 u32 val, rpe;
5045
5046 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5047 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5048
5049 return rpe;
5050}
5051
7707df4a
D		 5052static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5053{
5054 u32 val, rp1;
5055
5b5929cb
JN		 5056 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5057 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5058
7707df4a
D		 5059 return rp1;
5060}
5061
f8f2b001
D		 5062static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5063{
5064 u32 val, rp1;
5065
5066 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5067
5068 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5069
5070 return rp1;
5071}
5072
03af2045 5073static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5074{
5075 u32 val, rp0;
5076
64936258 5077 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5078
5079 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5080 /* Clamp to max */
5081 rp0 = min_t(u32, rp0, 0xea);
5082
5083 return rp0;
5084}
5085
5086static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5087{
5088 u32 val, rpe;
5089
64936258 5090 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5091 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5092 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5093 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5094
5095 return rpe;
5096}
5097
03af2045 5098static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5099{
36146035
ID		 5100 u32 val;
5101
5102 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5103 /*
5104 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5105 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5106 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5107 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5108 * to make sure it matches what Punit accepts.
5109 */
5110 return max_t(u32, val, 0xc0);
0a073b84
JB		 5111}
5112
ae48434c
ID		 5113/* Check that the pctx buffer wasn't move under us. */
5114static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5115{
5116 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5117
5118 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5119 dev_priv->vlv_pctx->stolen->start);
5120}
5121
38807746
D		 5122
5123/* Check that the pcbr address is not empty. */
5124static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5125{
5126 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5127
5128 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5129}
5130
5131static void cherryview_setup_pctx(struct drm_device *dev)
5132{
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 unsigned long pctx_paddr, paddr;
5135 struct i915_gtt *gtt = &dev_priv->gtt;
5136 u32 pcbr;
5137 int pctx_size = 32*1024;
5138
5139 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5140
5141 pcbr = I915_READ(VLV_PCBR);
5142 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5143 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5144 paddr = (dev_priv->mm.stolen_base +
5145 (gtt->stolen_size - pctx_size));
5146
5147 pctx_paddr = (paddr & (~4095));
5148 I915_WRITE(VLV_PCBR, pctx_paddr);
5149 }
ce611ef8
VS		 5150
5151 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5152}
5153
c9cddffc
JB		 5154static void valleyview_setup_pctx(struct drm_device *dev)
5155{
5156 struct drm_i915_private *dev_priv = dev->dev_private;
5157 struct drm_i915_gem_object *pctx;
5158 unsigned long pctx_paddr;
5159 u32 pcbr;
5160 int pctx_size = 24*1024;
5161
17b0c1f7
ID		 5162 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5163
c9cddffc
JB		 5164 pcbr = I915_READ(VLV_PCBR);
5165 if (pcbr) {
5166 /* BIOS set it up already, grab the pre-alloc'd space */
5167 int pcbr_offset;
5168
5169 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5170 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5171 pcbr_offset,
190d6cd5 5172 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5173 pctx_size);
5174 goto out;
5175 }
5176
ce611ef8
VS		 5177 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5178
c9cddffc
JB		 5179 /*
5180 * From the Gunit register HAS:
5181 * The Gfx driver is expected to program this register and ensure
5182 * proper allocation within Gfx stolen memory. For example, this
5183 * register should be programmed such than the PCBR range does not
5184 * overlap with other ranges, such as the frame buffer, protected
5185 * memory, or any other relevant ranges.
5186 */
5187 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5188 if (!pctx) {
5189 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5190 return;
5191 }
5192
5193 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5194 I915_WRITE(VLV_PCBR, pctx_paddr);
5195
5196out:
ce611ef8 5197 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5198 dev_priv->vlv_pctx = pctx;
5199}
5200
ae48434c
ID		 5201static void valleyview_cleanup_pctx(struct drm_device *dev)
5202{
5203 struct drm_i915_private *dev_priv = dev->dev_private;
5204
5205 if (WARN_ON(!dev_priv->vlv_pctx))
5206 return;
5207
5208 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5209 dev_priv->vlv_pctx = NULL;
5210}
5211
4e80519e
ID		 5212static void valleyview_init_gt_powersave(struct drm_device *dev)
5213{
5214 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5215 u32 val;
4e80519e
ID		 5216
5217 valleyview_setup_pctx(dev);
5218
5219 mutex_lock(&dev_priv->rps.hw_lock);
5220
2bb25c17
VS		 5221 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5222 switch ((val >> 6) & 3) {
5223 case 0:
5224 case 1:
5225 dev_priv->mem_freq = 800;
5226 break;
5227 case 2:
5228 dev_priv->mem_freq = 1066;
5229 break;
5230 case 3:
5231 dev_priv->mem_freq = 1333;
5232 break;
5233 }
80b83b62 5234 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5235
4e80519e
ID		 5236 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5237 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5238 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5239 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5240 dev_priv->rps.max_freq);
5241
5242 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5243 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5244 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5245 dev_priv->rps.efficient_freq);
5246
f8f2b001
D		 5247 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5248 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5249 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5250 dev_priv->rps.rp1_freq);
5251
4e80519e
ID		 5252 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5253 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5254 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5255 dev_priv->rps.min_freq);
5256
aed242ff
CW		 5257 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5258
4e80519e
ID		 5259 /* Preserve min/max settings in case of re-init */
5260 if (dev_priv->rps.max_freq_softlimit == 0)
5261 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5262
5263 if (dev_priv->rps.min_freq_softlimit == 0)
5264 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5265
5266 mutex_unlock(&dev_priv->rps.hw_lock);
5267}
5268
38807746
D		 5269static void cherryview_init_gt_powersave(struct drm_device *dev)
5270{
2b6b3a09 5271 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5272 u32 val;
2b6b3a09 5273
38807746 5274 cherryview_setup_pctx(dev);
2b6b3a09
D		 5275
5276 mutex_lock(&dev_priv->rps.hw_lock);
5277
a580516d 5278 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5279 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5280 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5281
2bb25c17 5282 switch ((val >> 2) & 0x7) {
2bb25c17 5283 case 3:
2bb25c17
VS		 5284 dev_priv->mem_freq = 2000;
5285 break;
bfa7df01 5286 default:
2bb25c17
VS		 5287 dev_priv->mem_freq = 1600;
5288 break;
5289 }
80b83b62 5290 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5291
2b6b3a09
D		 5292 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5293 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5294 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5295 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5296 dev_priv->rps.max_freq);
5297
5298 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5299 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5300 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5301 dev_priv->rps.efficient_freq);
5302
7707df4a
D		 5303 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5304 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5305 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5306 dev_priv->rps.rp1_freq);
5307
5b7c91b7
D		 5308 /* PUnit validated range is only [RPe, RP0] */
5309 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5310 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5311 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5312 dev_priv->rps.min_freq);
5313
1c14762d
VS		 5314 WARN_ONCE((dev_priv->rps.max_freq |
5315 dev_priv->rps.efficient_freq |
5316 dev_priv->rps.rp1_freq |
5317 dev_priv->rps.min_freq) & 1,
5318 "Odd GPU freq values\n");
5319
aed242ff
CW		 5320 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5321
2b6b3a09
D		 5322 /* Preserve min/max settings in case of re-init */
5323 if (dev_priv->rps.max_freq_softlimit == 0)
5324 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5325
5326 if (dev_priv->rps.min_freq_softlimit == 0)
5327 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5328
5329 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5330}
5331
4e80519e
ID		 5332static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5333{
5334 valleyview_cleanup_pctx(dev);
5335}
5336
38807746
D		 5337static void cherryview_enable_rps(struct drm_device *dev)
5338{
5339 struct drm_i915_private *dev_priv = dev->dev_private;
5340 struct intel_engine_cs *ring;
2b6b3a09 5341 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5342 int i;
5343
5344 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5345
5346 gtfifodbg = I915_READ(GTFIFODBG);
5347 if (gtfifodbg) {
5348 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5349 gtfifodbg);
5350 I915_WRITE(GTFIFODBG, gtfifodbg);
5351 }
5352
5353 cherryview_check_pctx(dev_priv);
5354
5355 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5356 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5357 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5358
160614a2
VS		 5359 /* Disable RC states. */
5360 I915_WRITE(GEN6_RC_CONTROL, 0);
5361
38807746
D		 5362 /* 2a: Program RC6 thresholds.*/
5363 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5364 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5365 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5366
5367 for_each_ring(ring, dev_priv, i)
5368 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5369 I915_WRITE(GEN6_RC_SLEEP, 0);
5370
f4f71c7d
D		 5371 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5372 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5373
5374 /* allows RC6 residency counter to work */
5375 I915_WRITE(VLV_COUNTER_CONTROL,
5376 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5377 VLV_MEDIA_RC6_COUNT_EN |
5378 VLV_RENDER_RC6_COUNT_EN));
5379
5380 /* For now we assume BIOS is allocating and populating the PCBR */
5381 pcbr = I915_READ(VLV_PCBR);
5382
38807746
D		 5383 /* 3: Enable RC6 */
5384 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5385 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5386 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5387
5388 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5389
2b6b3a09 5390 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5391 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5392 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5393 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5394 I915_WRITE(GEN6_RP_UP_EI, 66000);
5395 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5396
5397 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5398
5399 /* 5: Enable RPS */
5400 I915_WRITE(GEN6_RP_CONTROL,
5401 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5402 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5403 GEN6_RP_ENABLE |
5404 GEN6_RP_UP_BUSY_AVG |
5405 GEN6_RP_DOWN_IDLE_AVG);
5406
3ef62342
D		 5407 /* Setting Fixed Bias */
5408 val = VLV_OVERRIDE_EN |
5409 VLV_SOC_TDP_EN |
5410 CHV_BIAS_CPU_50_SOC_50;
5411 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5412
2b6b3a09
D		 5413 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5414
8d40c3ae
VS		 5415 /* RPS code assumes GPLL is used */
5416 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5417
742f491d 5418 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 5419 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5420
5421 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5422 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5423 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5424 dev_priv->rps.cur_freq);
5425
5426 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5427 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5428 dev_priv->rps.efficient_freq);
5429
5430 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5431
59bad947 5432 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5433}
5434
0a073b84
JB		 5435static void valleyview_enable_rps(struct drm_device *dev)
5436{
5437 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5438 struct intel_engine_cs *ring;
2a5913a8 5439 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5440 int i;
5441
5442 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5443
ae48434c
ID		 5444 valleyview_check_pctx(dev_priv);
5445
0a073b84 5446 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5447 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5448 gtfifodbg);
0a073b84
JB		 5449 I915_WRITE(GTFIFODBG, gtfifodbg);
5450 }
5451
c8d9a590 5452 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5453 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5454
160614a2
VS		 5455 /* Disable RC states. */
5456 I915_WRITE(GEN6_RC_CONTROL, 0);
5457
cad725fe 5458 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5459 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5460 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5461 I915_WRITE(GEN6_RP_UP_EI, 66000);
5462 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5463
5464 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5465
5466 I915_WRITE(GEN6_RP_CONTROL,
5467 GEN6_RP_MEDIA_TURBO |
5468 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5469 GEN6_RP_MEDIA_IS_GFX |
5470 GEN6_RP_ENABLE |
5471 GEN6_RP_UP_BUSY_AVG |
5472 GEN6_RP_DOWN_IDLE_CONT);
5473
5474 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5475 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5476 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5477
5478 for_each_ring(ring, dev_priv, i)
5479 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5480
2f0aa304 5481 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5482
5483 /* allows RC6 residency counter to work */
49798eb2 5484 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5485 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5486 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5487 VLV_MEDIA_RC6_COUNT_EN |
5488 VLV_RENDER_RC6_COUNT_EN));
31685c25 5489
a2b23fe0 5490 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5491 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5492
5493 intel_print_rc6_info(dev, rc6_mode);
5494
a2b23fe0 5495 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5496
3ef62342
D		 5497 /* Setting Fixed Bias */
5498 val = VLV_OVERRIDE_EN |
5499 VLV_SOC_TDP_EN |
5500 VLV_BIAS_CPU_125_SOC_875;
5501 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5502
64936258 5503 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5504
8d40c3ae
VS		 5505 /* RPS code assumes GPLL is used */
5506 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5507
742f491d 5508 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 5509 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5510
b39fb297 5511 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5512 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5513 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5514 dev_priv->rps.cur_freq);
0a073b84 5515
73008b98 5516 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5517 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5518 dev_priv->rps.efficient_freq);
0a073b84 5519
b39fb297 5520 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5521
59bad947 5522 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5523}
5524
dde18883
ED		 5525static unsigned long intel_pxfreq(u32 vidfreq)
5526{
5527 unsigned long freq;
5528 int div = (vidfreq & 0x3f0000) >> 16;
5529 int post = (vidfreq & 0x3000) >> 12;
5530 int pre = (vidfreq & 0x7);
5531
5532 if (!pre)
5533 return 0;
5534
5535 freq = ((div * 133333) / ((1<<post) * pre));
5536
5537 return freq;
5538}
5539
eb48eb00
DV		 5540static const struct cparams {
5541 u16 i;
5542 u16 t;
5543 u16 m;
5544 u16 c;
5545} cparams[] = {
5546 { 1, 1333, 301, 28664 },
5547 { 1, 1066, 294, 24460 },
5548 { 1, 800, 294, 25192 },
5549 { 0, 1333, 276, 27605 },
5550 { 0, 1066, 276, 27605 },
5551 { 0, 800, 231, 23784 },
5552};
5553
f531dcb2 5554static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5555{
5556 u64 total_count, diff, ret;
5557 u32 count1, count2, count3, m = 0, c = 0;
5558 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5559 int i;
5560
02d71956
DV		 5561 assert_spin_locked(&mchdev_lock);
5562
20e4d407 5563 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5564
5565 /* Prevent division-by-zero if we are asking too fast.
5566 * Also, we don't get interesting results if we are polling
5567 * faster than once in 10ms, so just return the saved value
5568 * in such cases.
5569 */
5570 if (diff1 <= 10)
20e4d407 5571 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5572
5573 count1 = I915_READ(DMIEC);
5574 count2 = I915_READ(DDREC);
5575 count3 = I915_READ(CSIEC);
5576
5577 total_count = count1 + count2 + count3;
5578
5579 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5580 if (total_count < dev_priv->ips.last_count1) {
5581 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5582 diff += total_count;
5583 } else {
20e4d407 5584 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5585 }
5586
5587 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5588 if (cparams[i].i == dev_priv->ips.c_m &&
5589 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5590 m = cparams[i].m;
5591 c = cparams[i].c;
5592 break;
5593 }
5594 }
5595
5596 diff = div_u64(diff, diff1);
5597 ret = ((m * diff) + c);
5598 ret = div_u64(ret, 10);
5599
20e4d407
DV		 5600 dev_priv->ips.last_count1 = total_count;
5601 dev_priv->ips.last_time1 = now;
eb48eb00 5602
20e4d407 5603 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5604
5605 return ret;
5606}
5607
f531dcb2
CW		 5608unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5609{
3d13ef2e 5610 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5611 unsigned long val;
5612
3d13ef2e 5613 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5614 return 0;
5615
5616 spin_lock_irq(&mchdev_lock);
5617
5618 val = __i915_chipset_val(dev_priv);
5619
5620 spin_unlock_irq(&mchdev_lock);
5621
5622 return val;
5623}
5624
eb48eb00
DV		 5625unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5626{
5627 unsigned long m, x, b;
5628 u32 tsfs;
5629
5630 tsfs = I915_READ(TSFS);
5631
5632 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5633 x = I915_READ8(TR1);
5634
5635 b = tsfs & TSFS_INTR_MASK;
5636
5637 return ((m * x) / 127) - b;
5638}
5639
d972d6ee
MK		 5640static int _pxvid_to_vd(u8 pxvid)
5641{
5642 if (pxvid == 0)
5643 return 0;
5644
5645 if (pxvid >= 8 && pxvid < 31)
5646 pxvid = 31;
5647
5648 return (pxvid + 2) * 125;
5649}
5650
5651static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5652{
3d13ef2e 5653 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5654 const int vd = _pxvid_to_vd(pxvid);
5655 const int vm = vd - 1125;
5656
3d13ef2e 5657 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5658 return vm > 0 ? vm : 0;
5659
5660 return vd;
eb48eb00
DV		 5661}
5662
02d71956 5663static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5664{
5ed0bdf2 5665 u64 now, diff, diffms;
eb48eb00
DV		 5666 u32 count;
5667
02d71956 5668 assert_spin_locked(&mchdev_lock);
eb48eb00 5669
5ed0bdf2
TG		 5670 now = ktime_get_raw_ns();
5671 diffms = now - dev_priv->ips.last_time2;
5672 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5673
5674 /* Don't divide by 0 */
eb48eb00
DV		 5675 if (!diffms)
5676 return;
5677
5678 count = I915_READ(GFXEC);
5679
20e4d407
DV		 5680 if (count < dev_priv->ips.last_count2) {
5681 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5682 diff += count;
5683 } else {
20e4d407 5684 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5685 }
5686
20e4d407
DV		 5687 dev_priv->ips.last_count2 = count;
5688 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5689
5690 /* More magic constants... */
5691 diff = diff * 1181;
5692 diff = div_u64(diff, diffms * 10);
20e4d407 5693 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5694}
5695
02d71956
DV		 5696void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5697{
3d13ef2e
DL		 5698 struct drm_device *dev = dev_priv->dev;
5699
5700 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5701 return;
5702
9270388e 5703 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5704
5705 __i915_update_gfx_val(dev_priv);
5706
9270388e 5707 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5708}
5709
f531dcb2 5710static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5711{
5712 unsigned long t, corr, state1, corr2, state2;
5713 u32 pxvid, ext_v;
5714
02d71956
DV		 5715 assert_spin_locked(&mchdev_lock);
5716
616847e7 5717 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 5718 pxvid = (pxvid >> 24) & 0x7f;
5719 ext_v = pvid_to_extvid(dev_priv, pxvid);
5720
5721 state1 = ext_v;
5722
5723 t = i915_mch_val(dev_priv);
5724
5725 /* Revel in the empirically derived constants */
5726
5727 /* Correction factor in 1/100000 units */
5728 if (t > 80)
5729 corr = ((t * 2349) + 135940);
5730 else if (t >= 50)
5731 corr = ((t * 964) + 29317);
5732 else /* < 50 */
5733 corr = ((t * 301) + 1004);
5734
5735 corr = corr * ((150142 * state1) / 10000 - 78642);
5736 corr /= 100000;
20e4d407 5737 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5738
5739 state2 = (corr2 * state1) / 10000;
5740 state2 /= 100; /* convert to mW */
5741
02d71956 5742 __i915_update_gfx_val(dev_priv);
eb48eb00 5743
20e4d407 5744 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5745}
5746
f531dcb2
CW		 5747unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5748{
3d13ef2e 5749 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5750 unsigned long val;
5751
3d13ef2e 5752 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5753 return 0;
5754
5755 spin_lock_irq(&mchdev_lock);
5756
5757 val = __i915_gfx_val(dev_priv);
5758
5759 spin_unlock_irq(&mchdev_lock);
5760
5761 return val;
5762}
5763
eb48eb00
DV		 5764/**
5765 * i915_read_mch_val - return value for IPS use
5766 *
5767 * Calculate and return a value for the IPS driver to use when deciding whether
5768 * we have thermal and power headroom to increase CPU or GPU power budget.
5769 */
5770unsigned long i915_read_mch_val(void)
5771{
5772 struct drm_i915_private *dev_priv;
5773 unsigned long chipset_val, graphics_val, ret = 0;
5774
9270388e 5775 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5776 if (!i915_mch_dev)
5777 goto out_unlock;
5778 dev_priv = i915_mch_dev;
5779
f531dcb2
CW		 5780 chipset_val = __i915_chipset_val(dev_priv);
5781 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5782
5783 ret = chipset_val + graphics_val;
5784
5785out_unlock:
9270388e 5786 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5787
5788 return ret;
5789}
5790EXPORT_SYMBOL_GPL(i915_read_mch_val);
5791
5792/**
5793 * i915_gpu_raise - raise GPU frequency limit
5794 *
5795 * Raise the limit; IPS indicates we have thermal headroom.
5796 */
5797bool i915_gpu_raise(void)
5798{
5799 struct drm_i915_private *dev_priv;
5800 bool ret = true;
5801
9270388e 5802 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5803 if (!i915_mch_dev) {
5804 ret = false;
5805 goto out_unlock;
5806 }
5807 dev_priv = i915_mch_dev;
5808
20e4d407
DV		 5809 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5810 dev_priv->ips.max_delay--;
eb48eb00
DV		 5811
5812out_unlock:
9270388e 5813 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5814
5815 return ret;
5816}
5817EXPORT_SYMBOL_GPL(i915_gpu_raise);
5818
5819/**
5820 * i915_gpu_lower - lower GPU frequency limit
5821 *
5822 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5823 * frequency maximum.
5824 */
5825bool i915_gpu_lower(void)
5826{
5827 struct drm_i915_private *dev_priv;
5828 bool ret = true;
5829
9270388e 5830 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5831 if (!i915_mch_dev) {
5832 ret = false;
5833 goto out_unlock;
5834 }
5835 dev_priv = i915_mch_dev;
5836
20e4d407
DV		 5837 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5838 dev_priv->ips.max_delay++;
eb48eb00
DV		 5839
5840out_unlock:
9270388e 5841 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5842
5843 return ret;
5844}
5845EXPORT_SYMBOL_GPL(i915_gpu_lower);
5846
5847/**
5848 * i915_gpu_busy - indicate GPU business to IPS
5849 *
5850 * Tell the IPS driver whether or not the GPU is busy.
5851 */
5852bool i915_gpu_busy(void)
5853{
5854 struct drm_i915_private *dev_priv;
a4872ba6 5855 struct intel_engine_cs *ring;
eb48eb00 5856 bool ret = false;
f047e395 5857 int i;
eb48eb00 5858
9270388e 5859 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5860 if (!i915_mch_dev)
5861 goto out_unlock;
5862 dev_priv = i915_mch_dev;
5863
f047e395
CW		 5864 for_each_ring(ring, dev_priv, i)
5865 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5866
5867out_unlock:
9270388e 5868 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5869
5870 return ret;
5871}
5872EXPORT_SYMBOL_GPL(i915_gpu_busy);
5873
5874/**
5875 * i915_gpu_turbo_disable - disable graphics turbo
5876 *
5877 * Disable graphics turbo by resetting the max frequency and setting the
5878 * current frequency to the default.
5879 */
5880bool i915_gpu_turbo_disable(void)
5881{
5882 struct drm_i915_private *dev_priv;
5883 bool ret = true;
5884
9270388e 5885 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5886 if (!i915_mch_dev) {
5887 ret = false;
5888 goto out_unlock;
5889 }
5890 dev_priv = i915_mch_dev;
5891
20e4d407 5892 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 5893
20e4d407 5894 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 5895 ret = false;
5896
5897out_unlock:
9270388e 5898 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5899
5900 return ret;
5901}
5902EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
5903
5904/**
5905 * Tells the intel_ips driver that the i915 driver is now loaded, if
5906 * IPS got loaded first.
5907 *
5908 * This awkward dance is so that neither module has to depend on the
5909 * other in order for IPS to do the appropriate communication of
5910 * GPU turbo limits to i915.
5911 */
5912static void
5913ips_ping_for_i915_load(void)
5914{
5915 void (*link)(void);
5916
5917 link = symbol_get(ips_link_to_i915_driver);
5918 if (link) {
5919 link();
5920 symbol_put(ips_link_to_i915_driver);
5921 }
5922}
5923
5924void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
5925{
02d71956
DV		 5926 /* We only register the i915 ips part with intel-ips once everything is
5927 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 5928 spin_lock_irq(&mchdev_lock);
eb48eb00 5929 i915_mch_dev = dev_priv;
9270388e 5930 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5931
5932 ips_ping_for_i915_load();
5933}
5934
5935void intel_gpu_ips_teardown(void)
5936{
9270388e 5937 spin_lock_irq(&mchdev_lock);
eb48eb00 5938 i915_mch_dev = NULL;
9270388e 5939 spin_unlock_irq(&mchdev_lock);
eb48eb00 5940}
76c3552f 5941
8090c6b9 5942static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 5943{
5944 struct drm_i915_private *dev_priv = dev->dev_private;
5945 u32 lcfuse;
5946 u8 pxw[16];
5947 int i;
5948
5949 /* Disable to program */
5950 I915_WRITE(ECR, 0);
5951 POSTING_READ(ECR);
5952
5953 /* Program energy weights for various events */
5954 I915_WRITE(SDEW, 0x15040d00);
5955 I915_WRITE(CSIEW0, 0x007f0000);
5956 I915_WRITE(CSIEW1, 0x1e220004);
5957 I915_WRITE(CSIEW2, 0x04000004);
5958
5959 for (i = 0; i < 5; i++)
616847e7 5960 I915_WRITE(PEW(i), 0);
dde18883 5961 for (i = 0; i < 3; i++)
616847e7 5962 I915_WRITE(DEW(i), 0);
dde18883
ED		 5963
5964 /* Program P-state weights to account for frequency power adjustment */
5965 for (i = 0; i < 16; i++) {
616847e7 5966 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 5967 unsigned long freq = intel_pxfreq(pxvidfreq);
5968 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
5969 PXVFREQ_PX_SHIFT;
5970 unsigned long val;
5971
5972 val = vid * vid;
5973 val *= (freq / 1000);
5974 val *= 255;
5975 val /= (127*127*900);
5976 if (val > 0xff)
5977 DRM_ERROR("bad pxval: %ld\n", val);
5978 pxw[i] = val;
5979 }
5980 /* Render standby states get 0 weight */
5981 pxw[14] = 0;
5982 pxw[15] = 0;
5983
5984 for (i = 0; i < 4; i++) {
5985 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
5986 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 5987 I915_WRITE(PXW(i), val);
dde18883
ED		 5988 }
5989
5990 /* Adjust magic regs to magic values (more experimental results) */
5991 I915_WRITE(OGW0, 0);
5992 I915_WRITE(OGW1, 0);
5993 I915_WRITE(EG0, 0x00007f00);
5994 I915_WRITE(EG1, 0x0000000e);
5995 I915_WRITE(EG2, 0x000e0000);
5996 I915_WRITE(EG3, 0x68000300);
5997 I915_WRITE(EG4, 0x42000000);
5998 I915_WRITE(EG5, 0x00140031);
5999 I915_WRITE(EG6, 0);
6000 I915_WRITE(EG7, 0);
6001
6002 for (i = 0; i < 8; i++)
616847e7 6003 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6004
6005 /* Enable PMON + select events */
6006 I915_WRITE(ECR, 0x80000019);
6007
6008 lcfuse = I915_READ(LCFUSE02);
6009
20e4d407 6010 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6011}
6012
ae48434c
ID		 6013void intel_init_gt_powersave(struct drm_device *dev)
6014{
b268c699
ID		 6015 struct drm_i915_private *dev_priv = dev->dev_private;
6016
e6069ca8 6017 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
b268c699
ID		 6018 /*
6019 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6020 * requirement.
6021 */
6022 if (!i915.enable_rc6) {
6023 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6024 intel_runtime_pm_get(dev_priv);
6025 }
e6069ca8 6026
38807746
D		 6027 if (IS_CHERRYVIEW(dev))
6028 cherryview_init_gt_powersave(dev);
6029 else if (IS_VALLEYVIEW(dev))
4e80519e 6030 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6031}
6032
6033void intel_cleanup_gt_powersave(struct drm_device *dev)
6034{
b268c699
ID		 6035 struct drm_i915_private *dev_priv = dev->dev_private;
6036
38807746
D		 6037 if (IS_CHERRYVIEW(dev))
6038 return;
6039 else if (IS_VALLEYVIEW(dev))
4e80519e 6040 valleyview_cleanup_gt_powersave(dev);
b268c699
ID		 6041
6042 if (!i915.enable_rc6)
6043 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6044}
6045
dbea3cea
ID		 6046static void gen6_suspend_rps(struct drm_device *dev)
6047{
6048 struct drm_i915_private *dev_priv = dev->dev_private;
6049
6050 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6051
4c2a8897 6052 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6053}
6054
156c7ca0
JB		 6055/**
6056 * intel_suspend_gt_powersave - suspend PM work and helper threads
6057 * @dev: drm device
6058 *
6059 * We don't want to disable RC6 or other features here, we just want
6060 * to make sure any work we've queued has finished and won't bother
6061 * us while we're suspended.
6062 */
6063void intel_suspend_gt_powersave(struct drm_device *dev)
6064{
6065 struct drm_i915_private *dev_priv = dev->dev_private;
6066
d4d70aa5
ID		 6067 if (INTEL_INFO(dev)->gen < 6)
6068 return;
6069
dbea3cea 6070 gen6_suspend_rps(dev);
b47adc17
D		 6071
6072 /* Force GPU to min freq during suspend */
6073 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6074}
6075
8090c6b9
DV		 6076void intel_disable_gt_powersave(struct drm_device *dev)
6077{
1a01ab3b
JB		 6078 struct drm_i915_private *dev_priv = dev->dev_private;
6079
930ebb46 6080 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6081 ironlake_disable_drps(dev);
38807746 6082 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6083 intel_suspend_gt_powersave(dev);
e494837a 6084
4fc688ce 6085 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6086 if (INTEL_INFO(dev)->gen >= 9)
6087 gen9_disable_rps(dev);
6088 else if (IS_CHERRYVIEW(dev))
38807746
D		 6089 cherryview_disable_rps(dev);
6090 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6091 valleyview_disable_rps(dev);
6092 else
6093 gen6_disable_rps(dev);
e534770a 6094
c0951f0c 6095 dev_priv->rps.enabled = false;
4fc688ce 6096 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6097 }
8090c6b9
DV		 6098}
6099
1a01ab3b
JB		 6100static void intel_gen6_powersave_work(struct work_struct *work)
6101{
6102 struct drm_i915_private *dev_priv =
6103 container_of(work, struct drm_i915_private,
6104 rps.delayed_resume_work.work);
6105 struct drm_device *dev = dev_priv->dev;
6106
4fc688ce 6107 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6108
4c2a8897 6109 gen6_reset_rps_interrupts(dev);
3cc134e3 6110
38807746
D		 6111 if (IS_CHERRYVIEW(dev)) {
6112 cherryview_enable_rps(dev);
6113 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6114 valleyview_enable_rps(dev);
20e49366 6115 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6116 gen9_enable_rc6(dev);
20e49366 6117 gen9_enable_rps(dev);
ef11bdb3 6118 if (IS_SKYLAKE(dev) || IS_KABYLAKE(dev))
cc017fb4 6119 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6120 } else if (IS_BROADWELL(dev)) {
6121 gen8_enable_rps(dev);
c2bc2fc5 6122 __gen6_update_ring_freq(dev);
0a073b84
JB		 6123 } else {
6124 gen6_enable_rps(dev);
c2bc2fc5 6125 __gen6_update_ring_freq(dev);
0a073b84 6126 }
aed242ff
CW		 6127
6128 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6129 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6130
6131 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6132 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6133
c0951f0c 6134 dev_priv->rps.enabled = true;
3cc134e3 6135
4c2a8897 6136 gen6_enable_rps_interrupts(dev);
3cc134e3 6137
4fc688ce 6138 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6139
6140 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6141}
6142
8090c6b9
DV		 6143void intel_enable_gt_powersave(struct drm_device *dev)
6144{
1a01ab3b
JB		 6145 struct drm_i915_private *dev_priv = dev->dev_private;
6146
f61018b1
YZ		 6147 /* Powersaving is controlled by the host when inside a VM */
6148 if (intel_vgpu_active(dev))
6149 return;
6150
8090c6b9 6151 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6152 mutex_lock(&dev->struct_mutex);
8090c6b9 6153 ironlake_enable_drps(dev);
8090c6b9 6154 intel_init_emon(dev);
dc1d0136 6155 mutex_unlock(&dev->struct_mutex);
38807746 6156 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6157 /*
6158 * PCU communication is slow and this doesn't need to be
6159 * done at any specific time, so do this out of our fast path
6160 * to make resume and init faster.
c6df39b5
ID		 6161 *
6162 * We depend on the HW RC6 power context save/restore
6163 * mechanism when entering D3 through runtime PM suspend. So
6164 * disable RPM until RPS/RC6 is properly setup. We can only
6165 * get here via the driver load/system resume/runtime resume
6166 * paths, so the _noresume version is enough (and in case of
6167 * runtime resume it's necessary).
1a01ab3b 6168 */
c6df39b5
ID		 6169 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6170 round_jiffies_up_relative(HZ)))
6171 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6172 }
6173}
6174
c6df39b5
ID		 6175void intel_reset_gt_powersave(struct drm_device *dev)
6176{
6177 struct drm_i915_private *dev_priv = dev->dev_private;
6178
dbea3cea
ID		 6179 if (INTEL_INFO(dev)->gen < 6)
6180 return;
6181
6182 gen6_suspend_rps(dev);
c6df39b5 6183 dev_priv->rps.enabled = false;
c6df39b5
ID		 6184}
6185
3107bd48
DV		 6186static void ibx_init_clock_gating(struct drm_device *dev)
6187{
6188 struct drm_i915_private *dev_priv = dev->dev_private;
6189
6190 /*
6191 * On Ibex Peak and Cougar Point, we need to disable clock
6192 * gating for the panel power sequencer or it will fail to
6193 * start up when no ports are active.
6194 */
6195 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6196}
6197
0e088b8f
VS		 6198static void g4x_disable_trickle_feed(struct drm_device *dev)
6199{
6200 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6201 enum pipe pipe;
0e088b8f 6202
055e393f 6203 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6204 I915_WRITE(DSPCNTR(pipe),
6205 I915_READ(DSPCNTR(pipe)) |
6206 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6207
6208 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6209 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6210 }
6211}
6212
017636cc
VS		 6213static void ilk_init_lp_watermarks(struct drm_device *dev)
6214{
6215 struct drm_i915_private *dev_priv = dev->dev_private;
6216
6217 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6218 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6219 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6220
6221 /*
6222 * Don't touch WM1S_LP_EN here.
6223 * Doing so could cause underruns.
6224 */
6225}
6226
1fa61106 6227static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6228{
6229 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6230 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6231
f1e8fa56
DL		 6232 /*
6233 * Required for FBC
6234 * WaFbcDisableDpfcClockGating:ilk
6235 */
4d47e4f5
DL		 6236 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6237 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6238 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6239
6240 I915_WRITE(PCH_3DCGDIS0,
6241 MARIUNIT_CLOCK_GATE_DISABLE |
6242 SVSMUNIT_CLOCK_GATE_DISABLE);
6243 I915_WRITE(PCH_3DCGDIS1,
6244 VFMUNIT_CLOCK_GATE_DISABLE);
6245
6f1d69b0
ED		 6246 /*
6247 * According to the spec the following bits should be set in
6248 * order to enable memory self-refresh
6249 * The bit 22/21 of 0x42004
6250 * The bit 5 of 0x42020
6251 * The bit 15 of 0x45000
6252 */
6253 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6254 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6255 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6256 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6257 I915_WRITE(DISP_ARB_CTL,
6258 (I915_READ(DISP_ARB_CTL) |
6259 DISP_FBC_WM_DIS));
017636cc
VS		 6260
6261 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6262
6263 /*
6264 * Based on the document from hardware guys the following bits
6265 * should be set unconditionally in order to enable FBC.
6266 * The bit 22 of 0x42000
6267 * The bit 22 of 0x42004
6268 * The bit 7,8,9 of 0x42020.
6269 */
6270 if (IS_IRONLAKE_M(dev)) {
4bb35334 6271 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6272 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6273 I915_READ(ILK_DISPLAY_CHICKEN1) |
6274 ILK_FBCQ_DIS);
6275 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6276 I915_READ(ILK_DISPLAY_CHICKEN2) |
6277 ILK_DPARB_GATE);
6f1d69b0
ED		 6278 }
6279
4d47e4f5
DL		 6280 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6281
6f1d69b0
ED		 6282 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6283 I915_READ(ILK_DISPLAY_CHICKEN2) |
6284 ILK_ELPIN_409_SELECT);
6285 I915_WRITE(_3D_CHICKEN2,
6286 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6287 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6288
ecdb4eb7 6289 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6290 I915_WRITE(CACHE_MODE_0,
6291 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6292
4e04632e
AG		 6293 /* WaDisable_RenderCache_OperationalFlush:ilk */
6294 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6295
0e088b8f 6296 g4x_disable_trickle_feed(dev);
bdad2b2f 6297
3107bd48
DV		 6298 ibx_init_clock_gating(dev);
6299}
6300
6301static void cpt_init_clock_gating(struct drm_device *dev)
6302{
6303 struct drm_i915_private *dev_priv = dev->dev_private;
6304 int pipe;
3f704fa2 6305 uint32_t val;
3107bd48
DV		 6306
6307 /*
6308 * On Ibex Peak and Cougar Point, we need to disable clock
6309 * gating for the panel power sequencer or it will fail to
6310 * start up when no ports are active.
6311 */
cd664078
JB		 6312 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6313 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6314 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6315 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6316 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6317 /* The below fixes the weird display corruption, a few pixels shifted
6318 * downward, on (only) LVDS of some HP laptops with IVY.
6319 */
055e393f 6320 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6321 val = I915_READ(TRANS_CHICKEN2(pipe));
6322 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6323 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6324 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6325 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6326 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6327 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6328 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6329 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6330 }
3107bd48 6331 /* WADP0ClockGatingDisable */
055e393f 6332 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6333 I915_WRITE(TRANS_CHICKEN1(pipe),
6334 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6335 }
6f1d69b0
ED		 6336}
6337
1d7aaa0c
DV		 6338static void gen6_check_mch_setup(struct drm_device *dev)
6339{
6340 struct drm_i915_private *dev_priv = dev->dev_private;
6341 uint32_t tmp;
6342
6343 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6344 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6345 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6346 tmp);
1d7aaa0c
DV		 6347}
6348
1fa61106 6349static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6350{
6351 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6352 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6353
231e54f6 6354 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6355
6356 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6357 I915_READ(ILK_DISPLAY_CHICKEN2) |
6358 ILK_ELPIN_409_SELECT);
6359
ecdb4eb7 6360 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6361 I915_WRITE(_3D_CHICKEN,
6362 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6363
4e04632e
AG		 6364 /* WaDisable_RenderCache_OperationalFlush:snb */
6365 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6366
8d85d272
VS		 6367 /*
6368 * BSpec recoomends 8x4 when MSAA is used,
6369 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6370 *
6371 * Note that PS/WM thread counts depend on the WIZ hashing
6372 * disable bit, which we don't touch here, but it's good
6373 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6374 */
6375 I915_WRITE(GEN6_GT_MODE,
98533251 6376 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6377
017636cc 6378 ilk_init_lp_watermarks(dev);
6f1d69b0 6379
6f1d69b0 6380 I915_WRITE(CACHE_MODE_0,
50743298 6381 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6382
6383 I915_WRITE(GEN6_UCGCTL1,
6384 I915_READ(GEN6_UCGCTL1) |
6385 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6386 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6387
6388 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6389 * gating disable must be set. Failure to set it results in
6390 * flickering pixels due to Z write ordering failures after
6391 * some amount of runtime in the Mesa "fire" demo, and Unigine
6392 * Sanctuary and Tropics, and apparently anything else with
6393 * alpha test or pixel discard.
6394 *
6395 * According to the spec, bit 11 (RCCUNIT) must also be set,
6396 * but we didn't debug actual testcases to find it out.
0f846f81 6397 *
ef59318c
VS		 6398 * WaDisableRCCUnitClockGating:snb
6399 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6400 */
6401 I915_WRITE(GEN6_UCGCTL2,
6402 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6403 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6404
5eb146dd 6405 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6406 I915_WRITE(_3D_CHICKEN3,
6407 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6408
e927ecde
VS		 6409 /*
6410 * Bspec says:
6411 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6412 * 3DSTATE_SF number of SF output attributes is more than 16."
6413 */
6414 I915_WRITE(_3D_CHICKEN3,
6415 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6416
6f1d69b0
ED		 6417 /*
6418 * According to the spec the following bits should be
6419 * set in order to enable memory self-refresh and fbc:
6420 * The bit21 and bit22 of 0x42000
6421 * The bit21 and bit22 of 0x42004
6422 * The bit5 and bit7 of 0x42020
6423 * The bit14 of 0x70180
6424 * The bit14 of 0x71180
4bb35334
DL		 6425 *
6426 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6427 */
6428 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6429 I915_READ(ILK_DISPLAY_CHICKEN1) |
6430 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6431 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6432 I915_READ(ILK_DISPLAY_CHICKEN2) |
6433 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6434 I915_WRITE(ILK_DSPCLK_GATE_D,
6435 I915_READ(ILK_DSPCLK_GATE_D) |
6436 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6437 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6438
0e088b8f 6439 g4x_disable_trickle_feed(dev);
f8f2ac9a 6440
3107bd48 6441 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6442
6443 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6444}
6445
6446static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6447{
6448 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6449
3aad9059 6450 /*
46680e0a 6451 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6452 *
6453 * This actually overrides the dispatch
6454 * mode for all thread types.
6455 */
6f1d69b0
ED		 6456 reg &= ~GEN7_FF_SCHED_MASK;
6457 reg |= GEN7_FF_TS_SCHED_HW;
6458 reg |= GEN7_FF_VS_SCHED_HW;
6459 reg |= GEN7_FF_DS_SCHED_HW;
6460
6461 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6462}
6463
17a303ec
PZ		 6464static void lpt_init_clock_gating(struct drm_device *dev)
6465{
6466 struct drm_i915_private *dev_priv = dev->dev_private;
6467
6468 /*
6469 * TODO: this bit should only be enabled when really needed, then
6470 * disabled when not needed anymore in order to save power.
6471 */
c2699524 6472 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 6473 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6474 I915_READ(SOUTH_DSPCLK_GATE_D) |
6475 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6476
6477 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 6478 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
6479 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 6480 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6481}
6482
7d708ee4
ID		 6483static void lpt_suspend_hw(struct drm_device *dev)
6484{
6485 struct drm_i915_private *dev_priv = dev->dev_private;
6486
c2699524 6487 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 6488 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6489
6490 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6491 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6492 }
6493}
6494
47c2bd97 6495static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6496{
6497 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6498 enum pipe pipe;
4d487cff 6499 uint32_t misccpctl;
1020a5c2 6500
7ad0dbab 6501 ilk_init_lp_watermarks(dev);
50ed5fbd 6502
ab57fff1 6503 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6504 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6505
ab57fff1 6506 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6507 I915_WRITE(CHICKEN_PAR1_1,
6508 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6509
ab57fff1 6510 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6511 for_each_pipe(dev_priv, pipe) {
07d27e20 6512 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6513 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6514 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6515 }
63801f21 6516
ab57fff1
BW		 6517 /* WaVSRefCountFullforceMissDisable:bdw */
6518 /* WaDSRefCountFullforceMissDisable:bdw */
6519 I915_WRITE(GEN7_FF_THREAD_MODE,
6520 I915_READ(GEN7_FF_THREAD_MODE) &
6521 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6522
295e8bb7
VS		 6523 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6524 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6525
6526 /* WaDisableSDEUnitClockGating:bdw */
6527 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6528 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6529
4d487cff
VS		 6530 /*
6531 * WaProgramL3SqcReg1Default:bdw
6532 * WaTempDisableDOPClkGating:bdw
6533 */
6534 misccpctl = I915_READ(GEN7_MISCCPCTL);
6535 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6536 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6537 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6538
6d50b065
VS		 6539 /*
6540 * WaGttCachingOffByDefault:bdw
6541 * GTT cache may not work with big pages, so if those
6542 * are ever enabled GTT cache may need to be disabled.
6543 */
6544 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6545
89d6b2b8 6546 lpt_init_clock_gating(dev);
1020a5c2
BW		 6547}
6548
cad2a2d7
ED		 6549static void haswell_init_clock_gating(struct drm_device *dev)
6550{
6551 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6552
017636cc 6553 ilk_init_lp_watermarks(dev);
cad2a2d7 6554
f3fc4884
FJ		 6555 /* L3 caching of data atomics doesn't work -- disable it. */
6556 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6557 I915_WRITE(HSW_ROW_CHICKEN3,
6558 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6559
ecdb4eb7 6560 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6561 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6562 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6563 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6564
e36ea7ff
VS		 6565 /* WaVSRefCountFullforceMissDisable:hsw */
6566 I915_WRITE(GEN7_FF_THREAD_MODE,
6567 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6568
4e04632e
AG		 6569 /* WaDisable_RenderCache_OperationalFlush:hsw */
6570 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6571
fe27c606
CW		 6572 /* enable HiZ Raw Stall Optimization */
6573 I915_WRITE(CACHE_MODE_0_GEN7,
6574 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6575
ecdb4eb7 6576 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6577 I915_WRITE(CACHE_MODE_1,
6578 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6579
a12c4967
VS		 6580 /*
6581 * BSpec recommends 8x4 when MSAA is used,
6582 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6583 *
6584 * Note that PS/WM thread counts depend on the WIZ hashing
6585 * disable bit, which we don't touch here, but it's good
6586 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6587 */
6588 I915_WRITE(GEN7_GT_MODE,
98533251 6589 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6590
94411593
KG		 6591 /* WaSampleCChickenBitEnable:hsw */
6592 I915_WRITE(HALF_SLICE_CHICKEN3,
6593 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6594
ecdb4eb7 6595 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6596 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6597
90a88643
PZ		 6598 /* WaRsPkgCStateDisplayPMReq:hsw */
6599 I915_WRITE(CHICKEN_PAR1_1,
6600 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6601
17a303ec 6602 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6603}
6604
1fa61106 6605static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6606{
6607 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6608 uint32_t snpcr;
6f1d69b0 6609
017636cc 6610 ilk_init_lp_watermarks(dev);
6f1d69b0 6611
231e54f6 6612 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6613
ecdb4eb7 6614 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6615 I915_WRITE(_3D_CHICKEN3,
6616 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6617
ecdb4eb7 6618 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6619 I915_WRITE(IVB_CHICKEN3,
6620 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6621 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6622
ecdb4eb7 6623 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6624 if (IS_IVB_GT1(dev))
6625 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6626 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6627
4e04632e
AG		 6628 /* WaDisable_RenderCache_OperationalFlush:ivb */
6629 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6630
ecdb4eb7 6631 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6632 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6633 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6634
ecdb4eb7 6635 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6636 I915_WRITE(GEN7_L3CNTLREG1,
6637 GEN7_WA_FOR_GEN7_L3_CONTROL);
6638 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6639 GEN7_WA_L3_CHICKEN_MODE);
6640 if (IS_IVB_GT1(dev))
6641 I915_WRITE(GEN7_ROW_CHICKEN2,
6642 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6643 else {
6644 /* must write both registers */
6645 I915_WRITE(GEN7_ROW_CHICKEN2,
6646 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6647 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6648 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6649 }
6f1d69b0 6650
ecdb4eb7 6651 /* WaForceL3Serialization:ivb */
61939d97
JB		 6652 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6653 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6654
1b80a19a 6655 /*
0f846f81 6656 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6657 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6658 */
6659 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6660 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6661
ecdb4eb7 6662 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6663 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6664 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6665 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6666
0e088b8f 6667 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6668
6669 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6670
22721343
CW		 6671 if (0) { /* causes HiZ corruption on ivb:gt1 */
6672 /* enable HiZ Raw Stall Optimization */
6673 I915_WRITE(CACHE_MODE_0_GEN7,
6674 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6675 }
116f2b6d 6676
ecdb4eb7 6677 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6678 I915_WRITE(CACHE_MODE_1,
6679 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6680
a607c1a4
VS		 6681 /*
6682 * BSpec recommends 8x4 when MSAA is used,
6683 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6684 *
6685 * Note that PS/WM thread counts depend on the WIZ hashing
6686 * disable bit, which we don't touch here, but it's good
6687 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6688 */
6689 I915_WRITE(GEN7_GT_MODE,
98533251 6690 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6691
20848223
BW		 6692 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6693 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6694 snpcr |= GEN6_MBC_SNPCR_MED;
6695 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6696
ab5c608b
BW		 6697 if (!HAS_PCH_NOP(dev))
6698 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6699
6700 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6701}
6702
c6beb13e
VS		 6703static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6704{
6705 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6706
6707 /*
6708 * Disable trickle feed and enable pnd deadline calculation
6709 */
6710 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6711 I915_WRITE(CBR1_VLV, 0);
6712}
6713
1fa61106 6714static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6715{
6716 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6717
c6beb13e 6718 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6719
ecdb4eb7 6720 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6721 I915_WRITE(_3D_CHICKEN3,
6722 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6723
ecdb4eb7 6724 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6725 I915_WRITE(IVB_CHICKEN3,
6726 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6727 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6728
fad7d36e 6729 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6730 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6731 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6732 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6733 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6734
4e04632e
AG		 6735 /* WaDisable_RenderCache_OperationalFlush:vlv */
6736 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6737
ecdb4eb7 6738 /* WaForceL3Serialization:vlv */
61939d97
JB		 6739 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6740 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6741
ecdb4eb7 6742 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6743 I915_WRITE(GEN7_ROW_CHICKEN2,
6744 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6745
ecdb4eb7 6746 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6747 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6748 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6749 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6750
46680e0a
VS		 6751 gen7_setup_fixed_func_scheduler(dev_priv);
6752
3c0edaeb 6753 /*
0f846f81 6754 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6755 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6756 */
6757 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6758 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6759
c98f5062
AG		 6760 /* WaDisableL3Bank2xClockGate:vlv
6761 * Disabling L3 clock gating- MMIO 940c[25] = 1
6762 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6763 I915_WRITE(GEN7_UCGCTL4,
6764 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6765
afd58e79
VS		 6766 /*
6767 * BSpec says this must be set, even though
6768 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6769 */
6b26c86d
DV		 6770 I915_WRITE(CACHE_MODE_1,
6771 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6772
da2518f9
VS		 6773 /*
6774 * BSpec recommends 8x4 when MSAA is used,
6775 * however in practice 16x4 seems fastest.
6776 *
6777 * Note that PS/WM thread counts depend on the WIZ hashing
6778 * disable bit, which we don't touch here, but it's good
6779 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6780 */
6781 I915_WRITE(GEN7_GT_MODE,
6782 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6783
031994ee
VS		 6784 /*
6785 * WaIncreaseL3CreditsForVLVB0:vlv
6786 * This is the hardware default actually.
6787 */
6788 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6789
2d809570 6790 /*
ecdb4eb7 6791 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6792 * Disable clock gating on th GCFG unit to prevent a delay
6793 * in the reporting of vblank events.
6794 */
7a0d1eed 6795 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6796}
6797
a4565da8
VS		 6798static void cherryview_init_clock_gating(struct drm_device *dev)
6799{
6800 struct drm_i915_private *dev_priv = dev->dev_private;
6801
c6beb13e 6802 vlv_init_display_clock_gating(dev_priv);
dd811e70 6803
232ce337
VS		 6804 /* WaVSRefCountFullforceMissDisable:chv */
6805 /* WaDSRefCountFullforceMissDisable:chv */
6806 I915_WRITE(GEN7_FF_THREAD_MODE,
6807 I915_READ(GEN7_FF_THREAD_MODE) &
6808 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6809
6810 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6811 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6812 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6813
6814 /* WaDisableCSUnitClockGating:chv */
6815 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6816 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6817
6818 /* WaDisableSDEUnitClockGating:chv */
6819 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6820 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6821
6822 /*
6823 * GTT cache may not work with big pages, so if those
6824 * are ever enabled GTT cache may need to be disabled.
6825 */
6826 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6827}
6828
1fa61106 6829static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6830{
6831 struct drm_i915_private *dev_priv = dev->dev_private;
6832 uint32_t dspclk_gate;
6833
6834 I915_WRITE(RENCLK_GATE_D1, 0);
6835 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6836 GS_UNIT_CLOCK_GATE_DISABLE |
6837 CL_UNIT_CLOCK_GATE_DISABLE);
6838 I915_WRITE(RAMCLK_GATE_D, 0);
6839 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6840 OVRUNIT_CLOCK_GATE_DISABLE |
6841 OVCUNIT_CLOCK_GATE_DISABLE;
6842 if (IS_GM45(dev))
6843 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6844 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6845
6846 /* WaDisableRenderCachePipelinedFlush */
6847 I915_WRITE(CACHE_MODE_0,
6848 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6849
4e04632e
AG		 6850 /* WaDisable_RenderCache_OperationalFlush:g4x */
6851 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6852
0e088b8f 6853 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6854}
6855
1fa61106 6856static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6857{
6858 struct drm_i915_private *dev_priv = dev->dev_private;
6859
6860 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6861 I915_WRITE(RENCLK_GATE_D2, 0);
6862 I915_WRITE(DSPCLK_GATE_D, 0);
6863 I915_WRITE(RAMCLK_GATE_D, 0);
6864 I915_WRITE16(DEUC, 0);
20f94967
VS		 6865 I915_WRITE(MI_ARB_STATE,
6866 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6867
6868 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6869 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6870}
6871
1fa61106 6872static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6873{
6874 struct drm_i915_private *dev_priv = dev->dev_private;
6875
6876 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6877 I965_RCC_CLOCK_GATE_DISABLE |
6878 I965_RCPB_CLOCK_GATE_DISABLE |
6879 I965_ISC_CLOCK_GATE_DISABLE |
6880 I965_FBC_CLOCK_GATE_DISABLE);
6881 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6882 I915_WRITE(MI_ARB_STATE,
6883 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6884
6885 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6886 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6887}
6888
1fa61106 6889static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6890{
6891 struct drm_i915_private *dev_priv = dev->dev_private;
6892 u32 dstate = I915_READ(D_STATE);
6893
6894 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
6895 DSTATE_DOT_CLOCK_GATING;
6896 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 6897
6898 if (IS_PINEVIEW(dev))
6899 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 6900
6901 /* IIR "flip pending" means done if this bit is set */
6902 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 6903
6904 /* interrupts should cause a wake up from C3 */
3299254f 6905 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 6906
6907 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
6908 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 6909
6910 I915_WRITE(MI_ARB_STATE,
6911 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6912}
6913
1fa61106 6914static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6915{
6916 struct drm_i915_private *dev_priv = dev->dev_private;
6917
6918 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 6919
6920 /* interrupts should cause a wake up from C3 */
6921 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
6922 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 6923
6924 I915_WRITE(MEM_MODE,
6925 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6926}
6927
1fa61106 6928static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6929{
6930 struct drm_i915_private *dev_priv = dev->dev_private;
6931
6932 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 6933
6934 I915_WRITE(MEM_MODE,
6935 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
6936 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 6937}
6938
6f1d69b0
ED		 6939void intel_init_clock_gating(struct drm_device *dev)
6940{
6941 struct drm_i915_private *dev_priv = dev->dev_private;
6942
c57e3551
DL		 6943 if (dev_priv->display.init_clock_gating)
6944 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 6945}
6946
7d708ee4
ID		 6947void intel_suspend_hw(struct drm_device *dev)
6948{
6949 if (HAS_PCH_LPT(dev))
6950 lpt_suspend_hw(dev);
6951}
6952
1fa61106
ED		 6953/* Set up chip specific power management-related functions */
6954void intel_init_pm(struct drm_device *dev)
6955{
6956 struct drm_i915_private *dev_priv = dev->dev_private;
6957
7ff0ebcc 6958 intel_fbc_init(dev_priv);
1fa61106 6959
c921aba8
DV		 6960 /* For cxsr */
6961 if (IS_PINEVIEW(dev))
6962 i915_pineview_get_mem_freq(dev);
6963 else if (IS_GEN5(dev))
6964 i915_ironlake_get_mem_freq(dev);
6965
1fa61106 6966 /* For FIFO watermark updates */
f5ed50cb 6967 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 6968 skl_setup_wm_latency(dev);
6969
a82abe43
ID		 6970 if (IS_BROXTON(dev))
6971 dev_priv->display.init_clock_gating =
6972 bxt_init_clock_gating;
2d41c0b5 6973 dev_priv->display.update_wm = skl_update_wm;
c83155a6 6974 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 6975 ilk_setup_wm_latency(dev);
53615a5e 6976
bd602544
VS		 6977 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
6978 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
6979 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
6980 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
6981 dev_priv->display.update_wm = ilk_update_wm;
86c8bbbe 6982 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
bd602544
VS		 6983 } else {
6984 DRM_DEBUG_KMS("Failed to read display plane latency. "
6985 "Disable CxSR\n");
6986 }
6987
6988 if (IS_GEN5(dev))
1fa61106 6989 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 6990 else if (IS_GEN6(dev))
1fa61106 6991 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 6992 else if (IS_IVYBRIDGE(dev))
1fa61106 6993 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 6994 else if (IS_HASWELL(dev))
cad2a2d7 6995 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 6996 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 6997 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 6998 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 6999 vlv_setup_wm_latency(dev);
7000
7001 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7002 dev_priv->display.init_clock_gating =
7003 cherryview_init_clock_gating;
1fa61106 7004 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7005 vlv_setup_wm_latency(dev);
7006
7007 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7008 dev_priv->display.init_clock_gating =
7009 valleyview_init_clock_gating;
1fa61106
ED		 7010 } else if (IS_PINEVIEW(dev)) {
7011 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7012 dev_priv->is_ddr3,
7013 dev_priv->fsb_freq,
7014 dev_priv->mem_freq)) {
7015 DRM_INFO("failed to find known CxSR latency "
7016 "(found ddr%s fsb freq %d, mem freq %d), "
7017 "disabling CxSR\n",
7018 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7019 dev_priv->fsb_freq, dev_priv->mem_freq);
7020 /* Disable CxSR and never update its watermark again */
5209b1f4 7021 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7022 dev_priv->display.update_wm = NULL;
7023 } else
7024 dev_priv->display.update_wm = pineview_update_wm;
7025 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7026 } else if (IS_G4X(dev)) {
7027 dev_priv->display.update_wm = g4x_update_wm;
7028 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7029 } else if (IS_GEN4(dev)) {
7030 dev_priv->display.update_wm = i965_update_wm;
7031 if (IS_CRESTLINE(dev))
7032 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7033 else if (IS_BROADWATER(dev))
7034 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7035 } else if (IS_GEN3(dev)) {
7036 dev_priv->display.update_wm = i9xx_update_wm;
7037 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7038 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7039 } else if (IS_GEN2(dev)) {
7040 if (INTEL_INFO(dev)->num_pipes == 1) {
7041 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7042 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7043 } else {
7044 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7045 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7046 }
7047
7048 if (IS_I85X(dev) || IS_I865G(dev))
7049 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7050 else
7051 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7052 } else {
7053 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7054 }
7055}
7056
151a49d0 7057int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7058{
4fc688ce 7059 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7060
7061 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7062 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7063 return -EAGAIN;
7064 }
7065
7066 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7067 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7068 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7069
7070 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7071 500)) {
7072 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7073 return -ETIMEDOUT;
7074 }
7075
7076 *val = I915_READ(GEN6_PCODE_DATA);
7077 I915_WRITE(GEN6_PCODE_DATA, 0);
7078
7079 return 0;
7080}
7081
151a49d0 7082int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7083{
4fc688ce 7084 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7085
7086 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7087 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7088 return -EAGAIN;
7089 }
7090
7091 I915_WRITE(GEN6_PCODE_DATA, val);
7092 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7093
7094 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7095 500)) {
7096 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7097 return -ETIMEDOUT;
7098 }
7099
7100 I915_WRITE(GEN6_PCODE_DATA, 0);
7101
7102 return 0;
7103}
a0e4e199 7104
dd06f88c 7105static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7106{
dd06f88c
VS		 7107 switch (czclk_freq) {
7108 case 200:
7109 return 10;
7110 case 267:
7111 return 12;
7112 case 320:
7113 case 333:
dd06f88c 7114 return 16;
ab3fb157
VS		 7115 case 400:
7116 return 20;
855ba3be
JB		 7117 default:
7118 return -1;
7119 }
dd06f88c 7120}
855ba3be 7121
dd06f88c
VS		 7122static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7123{
bfa7df01 7124 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
dd06f88c
VS		 7125
7126 div = vlv_gpu_freq_div(czclk_freq);
7127 if (div < 0)
7128 return div;
7129
7130 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7131}
7132
b55dd647 7133static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7134{
bfa7df01 7135 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
855ba3be 7136
dd06f88c
VS		 7137 mul = vlv_gpu_freq_div(czclk_freq);
7138 if (mul < 0)
7139 return mul;
855ba3be 7140
dd06f88c 7141 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7142}
7143
b55dd647 7144static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7145{
bfa7df01 7146 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7147
dd06f88c
VS		 7148 div = vlv_gpu_freq_div(czclk_freq) / 2;
7149 if (div < 0)
7150 return div;
22b1b2f8 7151
dd06f88c 7152 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7153}
7154
b55dd647 7155static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7156{
bfa7df01 7157 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->czclk_freq, 1000);
22b1b2f8 7158
dd06f88c
VS		 7159 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7160 if (mul < 0)
7161 return mul;
22b1b2f8 7162
1c14762d 7163 /* CHV needs even values */
dd06f88c 7164 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7165}
7166
616bc820 7167int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7168{
80b6dda4 7169 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7170 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7171 GEN9_FREQ_SCALER);
80b6dda4 7172 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7173 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7174 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7175 return byt_gpu_freq(dev_priv, val);
7176 else
7177 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7178}
7179
616bc820
VS		 7180int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7181{
80b6dda4 7182 if (IS_GEN9(dev_priv->dev))
500a3d2e
MK		 7183 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7184 GT_FREQUENCY_MULTIPLIER);
80b6dda4 7185 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7186 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7187 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7188 return byt_freq_opcode(dev_priv, val);
7189 else
500a3d2e 7190 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7191}
22b1b2f8 7192
6ad790c0
CW		 7193struct request_boost {
7194 struct work_struct work;
eed29a5b 7195 struct drm_i915_gem_request *req;
6ad790c0
CW		 7196};
7197
7198static void __intel_rps_boost_work(struct work_struct *work)
7199{
7200 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7201 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7202
e61b9958
CW		 7203 if (!i915_gem_request_completed(req, true))
7204 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7205 req->emitted_jiffies);
6ad790c0 7206
e61b9958 7207 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7208 kfree(boost);
7209}
7210
7211void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7212 struct drm_i915_gem_request *req)
6ad790c0
CW		 7213{
7214 struct request_boost *boost;
7215
eed29a5b 7216 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7217 return;
7218
e61b9958
CW		 7219 if (i915_gem_request_completed(req, true))
7220 return;
7221
6ad790c0
CW		 7222 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7223 if (boost == NULL)
7224 return;
7225
eed29a5b
DV		 7226 i915_gem_request_reference(req);
7227 boost->req = req;
6ad790c0
CW		 7228
7229 INIT_WORK(&boost->work, __intel_rps_boost_work);
7230 queue_work(to_i915(dev)->wq, &boost->work);
7231}
7232
f742a552 7233void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7234{
7235 struct drm_i915_private *dev_priv = dev->dev_private;
7236
f742a552 7237 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7238 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7239
907b28c5
CW		 7240 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7241 intel_gen6_powersave_work);
1854d5ca 7242 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7243 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7244 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7245
33688d95 7246 dev_priv->pm.suspended = false;
1f814dac 7247 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 7248 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 7249}
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