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drm/i915: Use crtc_clock in intel_dump_crtc_timings()
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
1fa61106 46static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 47{
48 struct drm_i915_private *dev_priv = dev->dev_private;
49 u32 fbc_ctl;
50
51 /* Disable compression */
52 fbc_ctl = I915_READ(FBC_CONTROL);
53 if ((fbc_ctl & FBC_CTL_EN) == 0)
54 return;
55
56 fbc_ctl &= ~FBC_CTL_EN;
57 I915_WRITE(FBC_CONTROL, fbc_ctl);
58
59 /* Wait for compressing bit to clear */
60 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
61 DRM_DEBUG_KMS("FBC idle timed out\n");
62 return;
63 }
64
65 DRM_DEBUG_KMS("disabled FBC\n");
66}
67
1fa61106 68static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 69{
70 struct drm_device *dev = crtc->dev;
71 struct drm_i915_private *dev_priv = dev->dev_private;
72 struct drm_framebuffer *fb = crtc->fb;
73 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
74 struct drm_i915_gem_object *obj = intel_fb->obj;
75 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
76 int cfb_pitch;
77 int plane, i;
78 u32 fbc_ctl, fbc_ctl2;
79
5c3fe8b0 80 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 81 if (fb->pitches[0] < cfb_pitch)
82 cfb_pitch = fb->pitches[0];
83
84 /* FBC_CTL wants 64B units */
85 cfb_pitch = (cfb_pitch / 64) - 1;
86 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
87
88 /* Clear old tags */
89 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
90 I915_WRITE(FBC_TAG + (i * 4), 0);
91
92 /* Set it up... */
93 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
94 fbc_ctl2 |= plane;
95 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
96 I915_WRITE(FBC_FENCE_OFF, crtc->y);
97
98 /* enable it... */
99 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
100 if (IS_I945GM(dev))
101 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
102 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
103 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
104 fbc_ctl |= obj->fence_reg;
105 I915_WRITE(FBC_CONTROL, fbc_ctl);
106
84f44ce7
VS		 107 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
108 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 109}
110
1fa61106 111static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 112{
113 struct drm_i915_private *dev_priv = dev->dev_private;
114
115 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
116}
117
1fa61106 118static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 119{
120 struct drm_device *dev = crtc->dev;
121 struct drm_i915_private *dev_priv = dev->dev_private;
122 struct drm_framebuffer *fb = crtc->fb;
123 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
124 struct drm_i915_gem_object *obj = intel_fb->obj;
125 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
126 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
127 unsigned long stall_watermark = 200;
128 u32 dpfc_ctl;
129
130 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
131 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
132 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
133
134 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
135 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
136 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
137 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
138
139 /* enable it... */
140 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
141
84f44ce7 142 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 143}
144
1fa61106 145static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 146{
147 struct drm_i915_private *dev_priv = dev->dev_private;
148 u32 dpfc_ctl;
149
150 /* Disable compression */
151 dpfc_ctl = I915_READ(DPFC_CONTROL);
152 if (dpfc_ctl & DPFC_CTL_EN) {
153 dpfc_ctl &= ~DPFC_CTL_EN;
154 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
155
156 DRM_DEBUG_KMS("disabled FBC\n");
157 }
158}
159
1fa61106 160static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 161{
162 struct drm_i915_private *dev_priv = dev->dev_private;
163
164 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
165}
166
167static void sandybridge_blit_fbc_update(struct drm_device *dev)
168{
169 struct drm_i915_private *dev_priv = dev->dev_private;
170 u32 blt_ecoskpd;
171
172 /* Make sure blitter notifies FBC of writes */
173 gen6_gt_force_wake_get(dev_priv);
174 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
175 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
176 GEN6_BLITTER_LOCK_SHIFT;
177 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
178 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
179 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
180 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
181 GEN6_BLITTER_LOCK_SHIFT);
182 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
183 POSTING_READ(GEN6_BLITTER_ECOSKPD);
184 gen6_gt_force_wake_put(dev_priv);
185}
186
1fa61106 187static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 188{
189 struct drm_device *dev = crtc->dev;
190 struct drm_i915_private *dev_priv = dev->dev_private;
191 struct drm_framebuffer *fb = crtc->fb;
192 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
193 struct drm_i915_gem_object *obj = intel_fb->obj;
194 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
195 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
196 unsigned long stall_watermark = 200;
197 u32 dpfc_ctl;
198
199 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
200 dpfc_ctl &= DPFC_RESERVED;
201 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
202 /* Set persistent mode for front-buffer rendering, ala X. */
203 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
204 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
205 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
206
207 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
208 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
209 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
210 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 211 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 212 /* enable it... */
213 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
214
215 if (IS_GEN6(dev)) {
216 I915_WRITE(SNB_DPFC_CTL_SA,
217 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
218 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
219 sandybridge_blit_fbc_update(dev);
220 }
221
84f44ce7 222 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 223}
224
1fa61106 225static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 226{
227 struct drm_i915_private *dev_priv = dev->dev_private;
228 u32 dpfc_ctl;
229
230 /* Disable compression */
231 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
232 if (dpfc_ctl & DPFC_CTL_EN) {
233 dpfc_ctl &= ~DPFC_CTL_EN;
234 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
235
b74ea102 236 if (IS_IVYBRIDGE(dev))
7dd23ba0 237 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 238 I915_WRITE(ILK_DSPCLK_GATE_D,
239 I915_READ(ILK_DSPCLK_GATE_D) &
240 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
241
d89f2071 242 if (IS_HASWELL(dev))
7dd23ba0 243 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 244 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
245 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
246 ~HSW_DPFC_GATING_DISABLE);
247
85208be0
ED		 248 DRM_DEBUG_KMS("disabled FBC\n");
249 }
250}
251
1fa61106 252static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 253{
254 struct drm_i915_private *dev_priv = dev->dev_private;
255
256 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
257}
258
abe959c7
RV		 259static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
260{
261 struct drm_device *dev = crtc->dev;
262 struct drm_i915_private *dev_priv = dev->dev_private;
263 struct drm_framebuffer *fb = crtc->fb;
264 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
265 struct drm_i915_gem_object *obj = intel_fb->obj;
266 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
267
f343c5f6 268 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 269
270 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
271 IVB_DPFC_CTL_FENCE_EN |
272 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
273
891348b2 274 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 275 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 276 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 277 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 278 I915_WRITE(ILK_DSPCLK_GATE_D,
279 I915_READ(ILK_DSPCLK_GATE_D) |
280 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 281 } else {
7dd23ba0 282 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 283 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
284 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 286 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
287 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
288 HSW_DPFC_GATING_DISABLE);
891348b2 289 }
b74ea102 290
abe959c7
RV		 291 I915_WRITE(SNB_DPFC_CTL_SA,
292 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
293 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
294
295 sandybridge_blit_fbc_update(dev);
296
297 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
298}
299
85208be0
ED		 300bool intel_fbc_enabled(struct drm_device *dev)
301{
302 struct drm_i915_private *dev_priv = dev->dev_private;
303
304 if (!dev_priv->display.fbc_enabled)
305 return false;
306
307 return dev_priv->display.fbc_enabled(dev);
308}
309
310static void intel_fbc_work_fn(struct work_struct *__work)
311{
312 struct intel_fbc_work *work =
313 container_of(to_delayed_work(__work),
314 struct intel_fbc_work, work);
315 struct drm_device *dev = work->crtc->dev;
316 struct drm_i915_private *dev_priv = dev->dev_private;
317
318 mutex_lock(&dev->struct_mutex);
5c3fe8b0 319 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 320 /* Double check that we haven't switched fb without cancelling
321 * the prior work.
322 */
323 if (work->crtc->fb == work->fb) {
324 dev_priv->display.enable_fbc(work->crtc,
325 work->interval);
326
5c3fe8b0
BW		 327 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
328 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
329 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 330 }
331
5c3fe8b0 332 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 333 }
334 mutex_unlock(&dev->struct_mutex);
335
336 kfree(work);
337}
338
339static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
340{
5c3fe8b0 341 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 342 return;
343
344 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
345
346 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 347 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 348 * entirely asynchronously.
349 */
5c3fe8b0 350 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 351 /* tasklet was killed before being run, clean up */
5c3fe8b0 352 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 353
354 /* Mark the work as no longer wanted so that if it does
355 * wake-up (because the work was already running and waiting
356 * for our mutex), it will discover that is no longer
357 * necessary to run.
358 */
5c3fe8b0 359 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 360}
361
b63fb44c 362static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 363{
364 struct intel_fbc_work *work;
365 struct drm_device *dev = crtc->dev;
366 struct drm_i915_private *dev_priv = dev->dev_private;
367
368 if (!dev_priv->display.enable_fbc)
369 return;
370
371 intel_cancel_fbc_work(dev_priv);
372
b14c5679 373 work = kzalloc(sizeof(*work), GFP_KERNEL);
85208be0 374 if (work == NULL) {
6cdcb5e7 375 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 376 dev_priv->display.enable_fbc(crtc, interval);
377 return;
378 }
379
380 work->crtc = crtc;
381 work->fb = crtc->fb;
382 work->interval = interval;
383 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
384
5c3fe8b0 385 dev_priv->fbc.fbc_work = work;
85208be0 386
85208be0
ED		 387 /* Delay the actual enabling to let pageflipping cease and the
388 * display to settle before starting the compression. Note that
389 * this delay also serves a second purpose: it allows for a
390 * vblank to pass after disabling the FBC before we attempt
391 * to modify the control registers.
392 *
393 * A more complicated solution would involve tracking vblanks
394 * following the termination of the page-flipping sequence
395 * and indeed performing the enable as a co-routine and not
396 * waiting synchronously upon the vblank.
7457d617
DL		 397 *
398 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 399 */
400 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
401}
402
403void intel_disable_fbc(struct drm_device *dev)
404{
405 struct drm_i915_private *dev_priv = dev->dev_private;
406
407 intel_cancel_fbc_work(dev_priv);
408
409 if (!dev_priv->display.disable_fbc)
410 return;
411
412 dev_priv->display.disable_fbc(dev);
5c3fe8b0 413 dev_priv->fbc.plane = -1;
85208be0
ED		 414}
415
29ebf90f
CW		 416static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
417 enum no_fbc_reason reason)
418{
419 if (dev_priv->fbc.no_fbc_reason == reason)
420 return false;
421
422 dev_priv->fbc.no_fbc_reason = reason;
423 return true;
424}
425
85208be0
ED		 426/**
427 * intel_update_fbc - enable/disable FBC as needed
428 * @dev: the drm_device
429 *
430 * Set up the framebuffer compression hardware at mode set time. We
431 * enable it if possible:
432 * - plane A only (on pre-965)
433 * - no pixel mulitply/line duplication
434 * - no alpha buffer discard
435 * - no dual wide
f85da868 436 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 437 *
438 * We can't assume that any compression will take place (worst case),
439 * so the compressed buffer has to be the same size as the uncompressed
440 * one. It also must reside (along with the line length buffer) in
441 * stolen memory.
442 *
443 * We need to enable/disable FBC on a global basis.
444 */
445void intel_update_fbc(struct drm_device *dev)
446{
447 struct drm_i915_private *dev_priv = dev->dev_private;
448 struct drm_crtc *crtc = NULL, *tmp_crtc;
449 struct intel_crtc *intel_crtc;
450 struct drm_framebuffer *fb;
451 struct intel_framebuffer *intel_fb;
452 struct drm_i915_gem_object *obj;
ef644fda 453 const struct drm_display_mode *adjusted_mode;
37327abd 454 unsigned int max_width, max_height;
85208be0 455
29ebf90f
CW		 456 if (!I915_HAS_FBC(dev)) {
457 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 458 return;
29ebf90f 459 }
85208be0 460
29ebf90f
CW		 461 if (!i915_powersave) {
462 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
463 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 464 return;
29ebf90f 465 }
85208be0
ED		 466
467 /*
468 * If FBC is already on, we just have to verify that we can
469 * keep it that way...
470 * Need to disable if:
471 * - more than one pipe is active
472 * - changing FBC params (stride, fence, mode)
473 * - new fb is too large to fit in compressed buffer
474 * - going to an unsupported config (interlace, pixel multiply, etc.)
475 */
476 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 477 if (intel_crtc_active(tmp_crtc) &&
478 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 479 if (crtc) {
29ebf90f
CW		 480 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
481 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 482 goto out_disable;
483 }
484 crtc = tmp_crtc;
485 }
486 }
487
488 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 489 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
490 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 491 goto out_disable;
492 }
493
494 intel_crtc = to_intel_crtc(crtc);
495 fb = crtc->fb;
496 intel_fb = to_intel_framebuffer(fb);
497 obj = intel_fb->obj;
ef644fda 498 adjusted_mode = &intel_crtc->config.adjusted_mode;
85208be0 499
8a5729a3
DL		 500 if (i915_enable_fbc < 0 &&
501 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 502 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
503 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 504 goto out_disable;
85208be0 505 }
8a5729a3 506 if (!i915_enable_fbc) {
29ebf90f
CW		 507 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
508 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 509 goto out_disable;
510 }
ef644fda
VS		 511 if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) ||
512 (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
514 DRM_DEBUG_KMS("mode incompatible with compression, "
515 "disabling\n");
85208be0
ED		 516 goto out_disable;
517 }
f85da868
PZ		 518
519 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
37327abd
VS		 520 max_width = 4096;
521 max_height = 2048;
f85da868 522 } else {
37327abd
VS		 523 max_width = 2048;
524 max_height = 1536;
f85da868 525 }
37327abd
VS		 526 if (intel_crtc->config.pipe_src_w > max_width ||
527 intel_crtc->config.pipe_src_h > max_height) {
29ebf90f
CW		 528 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
529 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 530 goto out_disable;
531 }
891348b2
RV		 532 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
533 intel_crtc->plane != 0) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
535 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 536 goto out_disable;
537 }
538
539 /* The use of a CPU fence is mandatory in order to detect writes
540 * by the CPU to the scanout and trigger updates to the FBC.
541 */
542 if (obj->tiling_mode != I915_TILING_X ||
543 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 544 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
545 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 546 goto out_disable;
547 }
548
549 /* If the kernel debugger is active, always disable compression */
550 if (in_dbg_master())
551 goto out_disable;
552
11be49eb 553 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 554 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
555 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 556 goto out_disable;
557 }
558
85208be0
ED		 559 /* If the scanout has not changed, don't modify the FBC settings.
560 * Note that we make the fundamental assumption that the fb->obj
561 * cannot be unpinned (and have its GTT offset and fence revoked)
562 * without first being decoupled from the scanout and FBC disabled.
563 */
5c3fe8b0
BW		 564 if (dev_priv->fbc.plane == intel_crtc->plane &&
565 dev_priv->fbc.fb_id == fb->base.id &&
566 dev_priv->fbc.y == crtc->y)
85208be0
ED		 567 return;
568
569 if (intel_fbc_enabled(dev)) {
570 /* We update FBC along two paths, after changing fb/crtc
571 * configuration (modeswitching) and after page-flipping
572 * finishes. For the latter, we know that not only did
573 * we disable the FBC at the start of the page-flip
574 * sequence, but also more than one vblank has passed.
575 *
576 * For the former case of modeswitching, it is possible
577 * to switch between two FBC valid configurations
578 * instantaneously so we do need to disable the FBC
579 * before we can modify its control registers. We also
580 * have to wait for the next vblank for that to take
581 * effect. However, since we delay enabling FBC we can
582 * assume that a vblank has passed since disabling and
583 * that we can safely alter the registers in the deferred
584 * callback.
585 *
586 * In the scenario that we go from a valid to invalid
587 * and then back to valid FBC configuration we have
588 * no strict enforcement that a vblank occurred since
589 * disabling the FBC. However, along all current pipe
590 * disabling paths we do need to wait for a vblank at
591 * some point. And we wait before enabling FBC anyway.
592 */
593 DRM_DEBUG_KMS("disabling active FBC for update\n");
594 intel_disable_fbc(dev);
595 }
596
597 intel_enable_fbc(crtc, 500);
29ebf90f 598 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 599 return;
600
601out_disable:
602 /* Multiple disables should be harmless */
603 if (intel_fbc_enabled(dev)) {
604 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
605 intel_disable_fbc(dev);
606 }
11be49eb 607 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 608}
609
c921aba8
DV		 610static void i915_pineview_get_mem_freq(struct drm_device *dev)
611{
612 drm_i915_private_t *dev_priv = dev->dev_private;
613 u32 tmp;
614
615 tmp = I915_READ(CLKCFG);
616
617 switch (tmp & CLKCFG_FSB_MASK) {
618 case CLKCFG_FSB_533:
619 dev_priv->fsb_freq = 533; /* 133*4 */
620 break;
621 case CLKCFG_FSB_800:
622 dev_priv->fsb_freq = 800; /* 200*4 */
623 break;
624 case CLKCFG_FSB_667:
625 dev_priv->fsb_freq = 667; /* 167*4 */
626 break;
627 case CLKCFG_FSB_400:
628 dev_priv->fsb_freq = 400; /* 100*4 */
629 break;
630 }
631
632 switch (tmp & CLKCFG_MEM_MASK) {
633 case CLKCFG_MEM_533:
634 dev_priv->mem_freq = 533;
635 break;
636 case CLKCFG_MEM_667:
637 dev_priv->mem_freq = 667;
638 break;
639 case CLKCFG_MEM_800:
640 dev_priv->mem_freq = 800;
641 break;
642 }
643
644 /* detect pineview DDR3 setting */
645 tmp = I915_READ(CSHRDDR3CTL);
646 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
647}
648
649static void i915_ironlake_get_mem_freq(struct drm_device *dev)
650{
651 drm_i915_private_t *dev_priv = dev->dev_private;
652 u16 ddrpll, csipll;
653
654 ddrpll = I915_READ16(DDRMPLL1);
655 csipll = I915_READ16(CSIPLL0);
656
657 switch (ddrpll & 0xff) {
658 case 0xc:
659 dev_priv->mem_freq = 800;
660 break;
661 case 0x10:
662 dev_priv->mem_freq = 1066;
663 break;
664 case 0x14:
665 dev_priv->mem_freq = 1333;
666 break;
667 case 0x18:
668 dev_priv->mem_freq = 1600;
669 break;
670 default:
671 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
672 ddrpll & 0xff);
673 dev_priv->mem_freq = 0;
674 break;
675 }
676
20e4d407 677 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 678
679 switch (csipll & 0x3ff) {
680 case 0x00c:
681 dev_priv->fsb_freq = 3200;
682 break;
683 case 0x00e:
684 dev_priv->fsb_freq = 3733;
685 break;
686 case 0x010:
687 dev_priv->fsb_freq = 4266;
688 break;
689 case 0x012:
690 dev_priv->fsb_freq = 4800;
691 break;
692 case 0x014:
693 dev_priv->fsb_freq = 5333;
694 break;
695 case 0x016:
696 dev_priv->fsb_freq = 5866;
697 break;
698 case 0x018:
699 dev_priv->fsb_freq = 6400;
700 break;
701 default:
702 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
703 csipll & 0x3ff);
704 dev_priv->fsb_freq = 0;
705 break;
706 }
707
708 if (dev_priv->fsb_freq == 3200) {
20e4d407 709 dev_priv->ips.c_m = 0;
c921aba8 710 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 711 dev_priv->ips.c_m = 1;
c921aba8 712 } else {
20e4d407 713 dev_priv->ips.c_m = 2;
c921aba8
DV		 714 }
715}
716
b445e3b0
ED		 717static const struct cxsr_latency cxsr_latency_table[] = {
718 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
719 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
720 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
721 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
722 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
723
724 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
725 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
726 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
727 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
728 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
729
730 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
731 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
732 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
733 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
734 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
735
736 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
737 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
738 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
739 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
740 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
741
742 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
743 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
744 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
745 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
746 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
747
748 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
749 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
750 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
751 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
752 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
753};
754
63c62275 755static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 756 int is_ddr3,
757 int fsb,
758 int mem)
759{
760 const struct cxsr_latency *latency;
761 int i;
762
763 if (fsb == 0 || mem == 0)
764 return NULL;
765
766 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
767 latency = &cxsr_latency_table[i];
768 if (is_desktop == latency->is_desktop &&
769 is_ddr3 == latency->is_ddr3 &&
770 fsb == latency->fsb_freq && mem == latency->mem_freq)
771 return latency;
772 }
773
774 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
775
776 return NULL;
777}
778
1fa61106 779static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 780{
781 struct drm_i915_private *dev_priv = dev->dev_private;
782
783 /* deactivate cxsr */
784 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
785}
786
787/*
788 * Latency for FIFO fetches is dependent on several factors:
789 * - memory configuration (speed, channels)
790 * - chipset
791 * - current MCH state
792 * It can be fairly high in some situations, so here we assume a fairly
793 * pessimal value. It's a tradeoff between extra memory fetches (if we
794 * set this value too high, the FIFO will fetch frequently to stay full)
795 * and power consumption (set it too low to save power and we might see
796 * FIFO underruns and display "flicker").
797 *
798 * A value of 5us seems to be a good balance; safe for very low end
799 * platforms but not overly aggressive on lower latency configs.
800 */
801static const int latency_ns = 5000;
802
1fa61106 803static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 804{
805 struct drm_i915_private *dev_priv = dev->dev_private;
806 uint32_t dsparb = I915_READ(DSPARB);
807 int size;
808
809 size = dsparb & 0x7f;
810 if (plane)
811 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
812
813 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
814 plane ? "B" : "A", size);
815
816 return size;
817}
818
1fa61106 819static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 820{
821 struct drm_i915_private *dev_priv = dev->dev_private;
822 uint32_t dsparb = I915_READ(DSPARB);
823 int size;
824
825 size = dsparb & 0x1ff;
826 if (plane)
827 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
828 size >>= 1; /* Convert to cachelines */
829
830 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
831 plane ? "B" : "A", size);
832
833 return size;
834}
835
1fa61106 836static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 837{
838 struct drm_i915_private *dev_priv = dev->dev_private;
839 uint32_t dsparb = I915_READ(DSPARB);
840 int size;
841
842 size = dsparb & 0x7f;
843 size >>= 2; /* Convert to cachelines */
844
845 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
846 plane ? "B" : "A",
847 size);
848
849 return size;
850}
851
1fa61106 852static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 853{
854 struct drm_i915_private *dev_priv = dev->dev_private;
855 uint32_t dsparb = I915_READ(DSPARB);
856 int size;
857
858 size = dsparb & 0x7f;
859 size >>= 1; /* Convert to cachelines */
860
861 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
862 plane ? "B" : "A", size);
863
864 return size;
865}
866
867/* Pineview has different values for various configs */
868static const struct intel_watermark_params pineview_display_wm = {
869 PINEVIEW_DISPLAY_FIFO,
870 PINEVIEW_MAX_WM,
871 PINEVIEW_DFT_WM,
872 PINEVIEW_GUARD_WM,
873 PINEVIEW_FIFO_LINE_SIZE
874};
875static const struct intel_watermark_params pineview_display_hplloff_wm = {
876 PINEVIEW_DISPLAY_FIFO,
877 PINEVIEW_MAX_WM,
878 PINEVIEW_DFT_HPLLOFF_WM,
879 PINEVIEW_GUARD_WM,
880 PINEVIEW_FIFO_LINE_SIZE
881};
882static const struct intel_watermark_params pineview_cursor_wm = {
883 PINEVIEW_CURSOR_FIFO,
884 PINEVIEW_CURSOR_MAX_WM,
885 PINEVIEW_CURSOR_DFT_WM,
886 PINEVIEW_CURSOR_GUARD_WM,
887 PINEVIEW_FIFO_LINE_SIZE,
888};
889static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
890 PINEVIEW_CURSOR_FIFO,
891 PINEVIEW_CURSOR_MAX_WM,
892 PINEVIEW_CURSOR_DFT_WM,
893 PINEVIEW_CURSOR_GUARD_WM,
894 PINEVIEW_FIFO_LINE_SIZE
895};
896static const struct intel_watermark_params g4x_wm_info = {
897 G4X_FIFO_SIZE,
898 G4X_MAX_WM,
899 G4X_MAX_WM,
900 2,
901 G4X_FIFO_LINE_SIZE,
902};
903static const struct intel_watermark_params g4x_cursor_wm_info = {
904 I965_CURSOR_FIFO,
905 I965_CURSOR_MAX_WM,
906 I965_CURSOR_DFT_WM,
907 2,
908 G4X_FIFO_LINE_SIZE,
909};
910static const struct intel_watermark_params valleyview_wm_info = {
911 VALLEYVIEW_FIFO_SIZE,
912 VALLEYVIEW_MAX_WM,
913 VALLEYVIEW_MAX_WM,
914 2,
915 G4X_FIFO_LINE_SIZE,
916};
917static const struct intel_watermark_params valleyview_cursor_wm_info = {
918 I965_CURSOR_FIFO,
919 VALLEYVIEW_CURSOR_MAX_WM,
920 I965_CURSOR_DFT_WM,
921 2,
922 G4X_FIFO_LINE_SIZE,
923};
924static const struct intel_watermark_params i965_cursor_wm_info = {
925 I965_CURSOR_FIFO,
926 I965_CURSOR_MAX_WM,
927 I965_CURSOR_DFT_WM,
928 2,
929 I915_FIFO_LINE_SIZE,
930};
931static const struct intel_watermark_params i945_wm_info = {
932 I945_FIFO_SIZE,
933 I915_MAX_WM,
934 1,
935 2,
936 I915_FIFO_LINE_SIZE
937};
938static const struct intel_watermark_params i915_wm_info = {
939 I915_FIFO_SIZE,
940 I915_MAX_WM,
941 1,
942 2,
943 I915_FIFO_LINE_SIZE
944};
945static const struct intel_watermark_params i855_wm_info = {
946 I855GM_FIFO_SIZE,
947 I915_MAX_WM,
948 1,
949 2,
950 I830_FIFO_LINE_SIZE
951};
952static const struct intel_watermark_params i830_wm_info = {
953 I830_FIFO_SIZE,
954 I915_MAX_WM,
955 1,
956 2,
957 I830_FIFO_LINE_SIZE
958};
959
960static const struct intel_watermark_params ironlake_display_wm_info = {
961 ILK_DISPLAY_FIFO,
962 ILK_DISPLAY_MAXWM,
963 ILK_DISPLAY_DFTWM,
964 2,
965 ILK_FIFO_LINE_SIZE
966};
967static const struct intel_watermark_params ironlake_cursor_wm_info = {
968 ILK_CURSOR_FIFO,
969 ILK_CURSOR_MAXWM,
970 ILK_CURSOR_DFTWM,
971 2,
972 ILK_FIFO_LINE_SIZE
973};
974static const struct intel_watermark_params ironlake_display_srwm_info = {
975 ILK_DISPLAY_SR_FIFO,
976 ILK_DISPLAY_MAX_SRWM,
977 ILK_DISPLAY_DFT_SRWM,
978 2,
979 ILK_FIFO_LINE_SIZE
980};
981static const struct intel_watermark_params ironlake_cursor_srwm_info = {
982 ILK_CURSOR_SR_FIFO,
983 ILK_CURSOR_MAX_SRWM,
984 ILK_CURSOR_DFT_SRWM,
985 2,
986 ILK_FIFO_LINE_SIZE
987};
988
989static const struct intel_watermark_params sandybridge_display_wm_info = {
990 SNB_DISPLAY_FIFO,
991 SNB_DISPLAY_MAXWM,
992 SNB_DISPLAY_DFTWM,
993 2,
994 SNB_FIFO_LINE_SIZE
995};
996static const struct intel_watermark_params sandybridge_cursor_wm_info = {
997 SNB_CURSOR_FIFO,
998 SNB_CURSOR_MAXWM,
999 SNB_CURSOR_DFTWM,
1000 2,
1001 SNB_FIFO_LINE_SIZE
1002};
1003static const struct intel_watermark_params sandybridge_display_srwm_info = {
1004 SNB_DISPLAY_SR_FIFO,
1005 SNB_DISPLAY_MAX_SRWM,
1006 SNB_DISPLAY_DFT_SRWM,
1007 2,
1008 SNB_FIFO_LINE_SIZE
1009};
1010static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1011 SNB_CURSOR_SR_FIFO,
1012 SNB_CURSOR_MAX_SRWM,
1013 SNB_CURSOR_DFT_SRWM,
1014 2,
1015 SNB_FIFO_LINE_SIZE
1016};
1017
1018
1019/**
1020 * intel_calculate_wm - calculate watermark level
1021 * @clock_in_khz: pixel clock
1022 * @wm: chip FIFO params
1023 * @pixel_size: display pixel size
1024 * @latency_ns: memory latency for the platform
1025 *
1026 * Calculate the watermark level (the level at which the display plane will
1027 * start fetching from memory again). Each chip has a different display
1028 * FIFO size and allocation, so the caller needs to figure that out and pass
1029 * in the correct intel_watermark_params structure.
1030 *
1031 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1032 * on the pixel size. When it reaches the watermark level, it'll start
1033 * fetching FIFO line sized based chunks from memory until the FIFO fills
1034 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1035 * will occur, and a display engine hang could result.
1036 */
1037static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1038 const struct intel_watermark_params *wm,
1039 int fifo_size,
1040 int pixel_size,
1041 unsigned long latency_ns)
1042{
1043 long entries_required, wm_size;
1044
1045 /*
1046 * Note: we need to make sure we don't overflow for various clock &
1047 * latency values.
1048 * clocks go from a few thousand to several hundred thousand.
1049 * latency is usually a few thousand
1050 */
1051 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1052 1000;
1053 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1054
1055 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1056
1057 wm_size = fifo_size - (entries_required + wm->guard_size);
1058
1059 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1060
1061 /* Don't promote wm_size to unsigned... */
1062 if (wm_size > (long)wm->max_wm)
1063 wm_size = wm->max_wm;
1064 if (wm_size <= 0)
1065 wm_size = wm->default_wm;
1066 return wm_size;
1067}
1068
1069static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1070{
1071 struct drm_crtc *crtc, *enabled = NULL;
1072
1073 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1074 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1075 if (enabled)
1076 return NULL;
1077 enabled = crtc;
1078 }
1079 }
1080
1081 return enabled;
1082}
1083
46ba614c 1084static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1085{
46ba614c 1086 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1087 struct drm_i915_private *dev_priv = dev->dev_private;
1088 struct drm_crtc *crtc;
1089 const struct cxsr_latency *latency;
1090 u32 reg;
1091 unsigned long wm;
1092
1093 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1094 dev_priv->fsb_freq, dev_priv->mem_freq);
1095 if (!latency) {
1096 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1097 pineview_disable_cxsr(dev);
1098 return;
1099 }
1100
1101 crtc = single_enabled_crtc(dev);
1102 if (crtc) {
4fe8590a 1103 int clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
b445e3b0
ED		 1104 int pixel_size = crtc->fb->bits_per_pixel / 8;
1105
1106 /* Display SR */
1107 wm = intel_calculate_wm(clock, &pineview_display_wm,
1108 pineview_display_wm.fifo_size,
1109 pixel_size, latency->display_sr);
1110 reg = I915_READ(DSPFW1);
1111 reg &= ~DSPFW_SR_MASK;
1112 reg |= wm << DSPFW_SR_SHIFT;
1113 I915_WRITE(DSPFW1, reg);
1114 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1115
1116 /* cursor SR */
1117 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1118 pineview_display_wm.fifo_size,
1119 pixel_size, latency->cursor_sr);
1120 reg = I915_READ(DSPFW3);
1121 reg &= ~DSPFW_CURSOR_SR_MASK;
1122 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1123 I915_WRITE(DSPFW3, reg);
1124
1125 /* Display HPLL off SR */
1126 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1127 pineview_display_hplloff_wm.fifo_size,
1128 pixel_size, latency->display_hpll_disable);
1129 reg = I915_READ(DSPFW3);
1130 reg &= ~DSPFW_HPLL_SR_MASK;
1131 reg |= wm & DSPFW_HPLL_SR_MASK;
1132 I915_WRITE(DSPFW3, reg);
1133
1134 /* cursor HPLL off SR */
1135 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1136 pineview_display_hplloff_wm.fifo_size,
1137 pixel_size, latency->cursor_hpll_disable);
1138 reg = I915_READ(DSPFW3);
1139 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1140 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1141 I915_WRITE(DSPFW3, reg);
1142 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1143
1144 /* activate cxsr */
1145 I915_WRITE(DSPFW3,
1146 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1147 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1148 } else {
1149 pineview_disable_cxsr(dev);
1150 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1151 }
1152}
1153
1154static bool g4x_compute_wm0(struct drm_device *dev,
1155 int plane,
1156 const struct intel_watermark_params *display,
1157 int display_latency_ns,
1158 const struct intel_watermark_params *cursor,
1159 int cursor_latency_ns,
1160 int *plane_wm,
1161 int *cursor_wm)
1162{
1163 struct drm_crtc *crtc;
4fe8590a 1164 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1165 int htotal, hdisplay, clock, pixel_size;
1166 int line_time_us, line_count;
1167 int entries, tlb_miss;
1168
1169 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1170 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1171 *cursor_wm = cursor->guard_size;
1172 *plane_wm = display->guard_size;
1173 return false;
1174 }
1175
4fe8590a
VS		 1176 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1177 clock = adjusted_mode->clock;
1178 htotal = adjusted_mode->htotal;
37327abd 1179 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1180 pixel_size = crtc->fb->bits_per_pixel / 8;
1181
1182 /* Use the small buffer method to calculate plane watermark */
1183 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1184 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1185 if (tlb_miss > 0)
1186 entries += tlb_miss;
1187 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1188 *plane_wm = entries + display->guard_size;
1189 if (*plane_wm > (int)display->max_wm)
1190 *plane_wm = display->max_wm;
1191
1192 /* Use the large buffer method to calculate cursor watermark */
1193 line_time_us = ((htotal * 1000) / clock);
1194 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1195 entries = line_count * 64 * pixel_size;
1196 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1197 if (tlb_miss > 0)
1198 entries += tlb_miss;
1199 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1200 *cursor_wm = entries + cursor->guard_size;
1201 if (*cursor_wm > (int)cursor->max_wm)
1202 *cursor_wm = (int)cursor->max_wm;
1203
1204 return true;
1205}
1206
1207/*
1208 * Check the wm result.
1209 *
1210 * If any calculated watermark values is larger than the maximum value that
1211 * can be programmed into the associated watermark register, that watermark
1212 * must be disabled.
1213 */
1214static bool g4x_check_srwm(struct drm_device *dev,
1215 int display_wm, int cursor_wm,
1216 const struct intel_watermark_params *display,
1217 const struct intel_watermark_params *cursor)
1218{
1219 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1220 display_wm, cursor_wm);
1221
1222 if (display_wm > display->max_wm) {
1223 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1224 display_wm, display->max_wm);
1225 return false;
1226 }
1227
1228 if (cursor_wm > cursor->max_wm) {
1229 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1230 cursor_wm, cursor->max_wm);
1231 return false;
1232 }
1233
1234 if (!(display_wm || cursor_wm)) {
1235 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1236 return false;
1237 }
1238
1239 return true;
1240}
1241
1242static bool g4x_compute_srwm(struct drm_device *dev,
1243 int plane,
1244 int latency_ns,
1245 const struct intel_watermark_params *display,
1246 const struct intel_watermark_params *cursor,
1247 int *display_wm, int *cursor_wm)
1248{
1249 struct drm_crtc *crtc;
4fe8590a 1250 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1251 int hdisplay, htotal, pixel_size, clock;
1252 unsigned long line_time_us;
1253 int line_count, line_size;
1254 int small, large;
1255 int entries;
1256
1257 if (!latency_ns) {
1258 *display_wm = *cursor_wm = 0;
1259 return false;
1260 }
1261
1262 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a
VS		 1263 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1264 clock = adjusted_mode->clock;
1265 htotal = adjusted_mode->htotal;
37327abd 1266 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1267 pixel_size = crtc->fb->bits_per_pixel / 8;
1268
1269 line_time_us = (htotal * 1000) / clock;
1270 line_count = (latency_ns / line_time_us + 1000) / 1000;
1271 line_size = hdisplay * pixel_size;
1272
1273 /* Use the minimum of the small and large buffer method for primary */
1274 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1275 large = line_count * line_size;
1276
1277 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1278 *display_wm = entries + display->guard_size;
1279
1280 /* calculate the self-refresh watermark for display cursor */
1281 entries = line_count * pixel_size * 64;
1282 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1283 *cursor_wm = entries + cursor->guard_size;
1284
1285 return g4x_check_srwm(dev,
1286 *display_wm, *cursor_wm,
1287 display, cursor);
1288}
1289
1290static bool vlv_compute_drain_latency(struct drm_device *dev,
1291 int plane,
1292 int *plane_prec_mult,
1293 int *plane_dl,
1294 int *cursor_prec_mult,
1295 int *cursor_dl)
1296{
1297 struct drm_crtc *crtc;
1298 int clock, pixel_size;
1299 int entries;
1300
1301 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1302 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1303 return false;
1304
4fe8590a 1305 clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
b445e3b0
ED		 1306 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1307
1308 entries = (clock / 1000) * pixel_size;
1309 *plane_prec_mult = (entries > 256) ?
1310 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1311 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1312 pixel_size);
1313
1314 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1315 *cursor_prec_mult = (entries > 256) ?
1316 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1317 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1318
1319 return true;
1320}
1321
1322/*
1323 * Update drain latency registers of memory arbiter
1324 *
1325 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1326 * to be programmed. Each plane has a drain latency multiplier and a drain
1327 * latency value.
1328 */
1329
1330static void vlv_update_drain_latency(struct drm_device *dev)
1331{
1332 struct drm_i915_private *dev_priv = dev->dev_private;
1333 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1334 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1335 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1336 either 16 or 32 */
1337
1338 /* For plane A, Cursor A */
1339 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1340 &cursor_prec_mult, &cursora_dl)) {
1341 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1342 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1343 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1344 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1345
1346 I915_WRITE(VLV_DDL1, cursora_prec |
1347 (cursora_dl << DDL_CURSORA_SHIFT) |
1348 planea_prec | planea_dl);
1349 }
1350
1351 /* For plane B, Cursor B */
1352 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1353 &cursor_prec_mult, &cursorb_dl)) {
1354 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1355 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1356 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1357 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1358
1359 I915_WRITE(VLV_DDL2, cursorb_prec |
1360 (cursorb_dl << DDL_CURSORB_SHIFT) |
1361 planeb_prec | planeb_dl);
1362 }
1363}
1364
1365#define single_plane_enabled(mask) is_power_of_2(mask)
1366
46ba614c 1367static void valleyview_update_wm(struct drm_crtc *crtc)
b445e3b0 1368{
46ba614c 1369 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
af6c4575 1374 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1375 unsigned int enabled = 0;
1376
1377 vlv_update_drain_latency(dev);
1378
51cea1f4 1379 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
51cea1f4 1383 enabled |= 1 << PIPE_A;
b445e3b0 1384
51cea1f4 1385 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
51cea1f4 1389 enabled |= 1 << PIPE_B;
b445e3b0 1390
b445e3b0
ED		 1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1393 sr_latency_ns,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
af6c4575
CW		 1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 2*sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
52bd02d8 1401 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1403 } else {
b445e3b0
ED		 1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1406 plane_sr = cursor_sr = 0;
1407 }
b445e3b0
ED		 1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
8c919b28 1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 I915_WRITE(DSPFW3,
8c919b28
CW		 1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1425}
1426
46ba614c 1427static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1428{
46ba614c 1429 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1430 static const int sr_latency_ns = 12000;
1431 struct drm_i915_private *dev_priv = dev->dev_private;
1432 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1433 int plane_sr, cursor_sr;
1434 unsigned int enabled = 0;
1435
51cea1f4 1436 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1437 &g4x_wm_info, latency_ns,
1438 &g4x_cursor_wm_info, latency_ns,
1439 &planea_wm, &cursora_wm))
51cea1f4 1440 enabled |= 1 << PIPE_A;
b445e3b0 1441
51cea1f4 1442 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1443 &g4x_wm_info, latency_ns,
1444 &g4x_cursor_wm_info, latency_ns,
1445 &planeb_wm, &cursorb_wm))
51cea1f4 1446 enabled |= 1 << PIPE_B;
b445e3b0 1447
b445e3b0
ED		 1448 if (single_plane_enabled(enabled) &&
1449 g4x_compute_srwm(dev, ffs(enabled) - 1,
1450 sr_latency_ns,
1451 &g4x_wm_info,
1452 &g4x_cursor_wm_info,
52bd02d8 1453 &plane_sr, &cursor_sr)) {
b445e3b0 1454 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1455 } else {
b445e3b0
ED		 1456 I915_WRITE(FW_BLC_SELF,
1457 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1458 plane_sr = cursor_sr = 0;
1459 }
b445e3b0
ED		 1460
1461 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1462 planea_wm, cursora_wm,
1463 planeb_wm, cursorb_wm,
1464 plane_sr, cursor_sr);
1465
1466 I915_WRITE(DSPFW1,
1467 (plane_sr << DSPFW_SR_SHIFT) |
1468 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1469 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1470 planea_wm);
1471 I915_WRITE(DSPFW2,
8c919b28 1472 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1473 (cursora_wm << DSPFW_CURSORA_SHIFT));
1474 /* HPLL off in SR has some issues on G4x... disable it */
1475 I915_WRITE(DSPFW3,
8c919b28 1476 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1477 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1478}
1479
46ba614c 1480static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1481{
46ba614c 1482 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1483 struct drm_i915_private *dev_priv = dev->dev_private;
1484 struct drm_crtc *crtc;
1485 int srwm = 1;
1486 int cursor_sr = 16;
1487
1488 /* Calc sr entries for one plane configs */
1489 crtc = single_enabled_crtc(dev);
1490 if (crtc) {
1491 /* self-refresh has much higher latency */
1492 static const int sr_latency_ns = 12000;
4fe8590a
VS		 1493 const struct drm_display_mode *adjusted_mode =
1494 &to_intel_crtc(crtc)->config.adjusted_mode;
1495 int clock = adjusted_mode->clock;
1496 int htotal = adjusted_mode->htotal;
37327abd 1497 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1498 int pixel_size = crtc->fb->bits_per_pixel / 8;
1499 unsigned long line_time_us;
1500 int entries;
1501
1502 line_time_us = ((htotal * 1000) / clock);
1503
1504 /* Use ns/us then divide to preserve precision */
1505 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1506 pixel_size * hdisplay;
1507 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1508 srwm = I965_FIFO_SIZE - entries;
1509 if (srwm < 0)
1510 srwm = 1;
1511 srwm &= 0x1ff;
1512 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1513 entries, srwm);
1514
1515 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1516 pixel_size * 64;
1517 entries = DIV_ROUND_UP(entries,
1518 i965_cursor_wm_info.cacheline_size);
1519 cursor_sr = i965_cursor_wm_info.fifo_size -
1520 (entries + i965_cursor_wm_info.guard_size);
1521
1522 if (cursor_sr > i965_cursor_wm_info.max_wm)
1523 cursor_sr = i965_cursor_wm_info.max_wm;
1524
1525 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1526 "cursor %d\n", srwm, cursor_sr);
1527
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1530 } else {
1531 /* Turn off self refresh if both pipes are enabled */
1532 if (IS_CRESTLINE(dev))
1533 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1534 & ~FW_BLC_SELF_EN);
1535 }
1536
1537 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1538 srwm);
1539
1540 /* 965 has limitations... */
1541 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1542 (8 << 16) | (8 << 8) | (8 << 0));
1543 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1544 /* update cursor SR watermark */
1545 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1546}
1547
46ba614c 1548static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1549{
46ba614c 1550 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1551 struct drm_i915_private *dev_priv = dev->dev_private;
1552 const struct intel_watermark_params *wm_info;
1553 uint32_t fwater_lo;
1554 uint32_t fwater_hi;
1555 int cwm, srwm = 1;
1556 int fifo_size;
1557 int planea_wm, planeb_wm;
1558 struct drm_crtc *crtc, *enabled = NULL;
1559
1560 if (IS_I945GM(dev))
1561 wm_info = &i945_wm_info;
1562 else if (!IS_GEN2(dev))
1563 wm_info = &i915_wm_info;
1564 else
1565 wm_info = &i855_wm_info;
1566
1567 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1568 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1569 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1570 int cpp = crtc->fb->bits_per_pixel / 8;
1571 if (IS_GEN2(dev))
1572 cpp = 4;
1573
4fe8590a 1574 planea_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
b9e0bda3 1575 wm_info, fifo_size, cpp,
b445e3b0
ED		 1576 latency_ns);
1577 enabled = crtc;
1578 } else
1579 planea_wm = fifo_size - wm_info->guard_size;
1580
1581 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1582 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1583 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1584 int cpp = crtc->fb->bits_per_pixel / 8;
1585 if (IS_GEN2(dev))
1586 cpp = 4;
1587
4fe8590a 1588 planeb_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
b9e0bda3 1589 wm_info, fifo_size, cpp,
b445e3b0
ED		 1590 latency_ns);
1591 if (enabled == NULL)
1592 enabled = crtc;
1593 else
1594 enabled = NULL;
1595 } else
1596 planeb_wm = fifo_size - wm_info->guard_size;
1597
1598 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1599
1600 /*
1601 * Overlay gets an aggressive default since video jitter is bad.
1602 */
1603 cwm = 2;
1604
1605 /* Play safe and disable self-refresh before adjusting watermarks. */
1606 if (IS_I945G(dev) || IS_I945GM(dev))
1607 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1608 else if (IS_I915GM(dev))
1609 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1610
1611 /* Calc sr entries for one plane configs */
1612 if (HAS_FW_BLC(dev) && enabled) {
1613 /* self-refresh has much higher latency */
1614 static const int sr_latency_ns = 6000;
4fe8590a
VS		 1615 const struct drm_display_mode *adjusted_mode =
1616 &to_intel_crtc(enabled)->config.adjusted_mode;
1617 int clock = adjusted_mode->clock;
1618 int htotal = adjusted_mode->htotal;
37327abd 1619 int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1620 int pixel_size = enabled->fb->bits_per_pixel / 8;
1621 unsigned long line_time_us;
1622 int entries;
1623
1624 line_time_us = (htotal * 1000) / clock;
1625
1626 /* Use ns/us then divide to preserve precision */
1627 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1628 pixel_size * hdisplay;
1629 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1630 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1631 srwm = wm_info->fifo_size - entries;
1632 if (srwm < 0)
1633 srwm = 1;
1634
1635 if (IS_I945G(dev) || IS_I945GM(dev))
1636 I915_WRITE(FW_BLC_SELF,
1637 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1638 else if (IS_I915GM(dev))
1639 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1640 }
1641
1642 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1643 planea_wm, planeb_wm, cwm, srwm);
1644
1645 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1646 fwater_hi = (cwm & 0x1f);
1647
1648 /* Set request length to 8 cachelines per fetch */
1649 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1650 fwater_hi = fwater_hi | (1 << 8);
1651
1652 I915_WRITE(FW_BLC, fwater_lo);
1653 I915_WRITE(FW_BLC2, fwater_hi);
1654
1655 if (HAS_FW_BLC(dev)) {
1656 if (enabled) {
1657 if (IS_I945G(dev) || IS_I945GM(dev))
1658 I915_WRITE(FW_BLC_SELF,
1659 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1660 else if (IS_I915GM(dev))
1661 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1662 DRM_DEBUG_KMS("memory self refresh enabled\n");
1663 } else
1664 DRM_DEBUG_KMS("memory self refresh disabled\n");
1665 }
1666}
1667
46ba614c 1668static void i830_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1669{
46ba614c 1670 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1671 struct drm_i915_private *dev_priv = dev->dev_private;
1672 struct drm_crtc *crtc;
1673 uint32_t fwater_lo;
1674 int planea_wm;
1675
1676 crtc = single_enabled_crtc(dev);
1677 if (crtc == NULL)
1678 return;
1679
4fe8590a
VS		 1680 planea_wm = intel_calculate_wm(to_intel_crtc(crtc)->config.adjusted_mode.clock,
1681 &i830_wm_info,
b445e3b0 1682 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1683 4, latency_ns);
b445e3b0
ED		 1684 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1685 fwater_lo |= (3<<8) | planea_wm;
1686
1687 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1688
1689 I915_WRITE(FW_BLC, fwater_lo);
1690}
1691
b445e3b0
ED		 1692/*
1693 * Check the wm result.
1694 *
1695 * If any calculated watermark values is larger than the maximum value that
1696 * can be programmed into the associated watermark register, that watermark
1697 * must be disabled.
1698 */
1699static bool ironlake_check_srwm(struct drm_device *dev, int level,
1700 int fbc_wm, int display_wm, int cursor_wm,
1701 const struct intel_watermark_params *display,
1702 const struct intel_watermark_params *cursor)
1703{
1704 struct drm_i915_private *dev_priv = dev->dev_private;
1705
1706 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1707 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1708
1709 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1710 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1711 fbc_wm, SNB_FBC_MAX_SRWM, level);
1712
1713 /* fbc has it's own way to disable FBC WM */
1714 I915_WRITE(DISP_ARB_CTL,
1715 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1716 return false;
615aaa5f
VS		 1717 } else if (INTEL_INFO(dev)->gen >= 6) {
1718 /* enable FBC WM (except on ILK, where it must remain off) */
1719 I915_WRITE(DISP_ARB_CTL,
1720 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1721 }
1722
1723 if (display_wm > display->max_wm) {
1724 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1725 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1726 return false;
1727 }
1728
1729 if (cursor_wm > cursor->max_wm) {
1730 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1731 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1732 return false;
1733 }
1734
1735 if (!(fbc_wm || display_wm || cursor_wm)) {
1736 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1737 return false;
1738 }
1739
1740 return true;
1741}
1742
1743/*
1744 * Compute watermark values of WM[1-3],
1745 */
1746static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1747 int latency_ns,
1748 const struct intel_watermark_params *display,
1749 const struct intel_watermark_params *cursor,
1750 int *fbc_wm, int *display_wm, int *cursor_wm)
1751{
1752 struct drm_crtc *crtc;
4fe8590a 1753 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1754 unsigned long line_time_us;
1755 int hdisplay, htotal, pixel_size, clock;
1756 int line_count, line_size;
1757 int small, large;
1758 int entries;
1759
1760 if (!latency_ns) {
1761 *fbc_wm = *display_wm = *cursor_wm = 0;
1762 return false;
1763 }
1764
1765 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a
VS		 1766 adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode;
1767 clock = adjusted_mode->clock;
1768 htotal = adjusted_mode->htotal;
37327abd 1769 hdisplay = to_intel_crtc(crtc)->config.pipe_src_w;
b445e3b0
ED		 1770 pixel_size = crtc->fb->bits_per_pixel / 8;
1771
1772 line_time_us = (htotal * 1000) / clock;
1773 line_count = (latency_ns / line_time_us + 1000) / 1000;
1774 line_size = hdisplay * pixel_size;
1775
1776 /* Use the minimum of the small and large buffer method for primary */
1777 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1778 large = line_count * line_size;
1779
1780 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1781 *display_wm = entries + display->guard_size;
1782
1783 /*
1784 * Spec says:
1785 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1786 */
1787 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1788
1789 /* calculate the self-refresh watermark for display cursor */
1790 entries = line_count * pixel_size * 64;
1791 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1792 *cursor_wm = entries + cursor->guard_size;
1793
1794 return ironlake_check_srwm(dev, level,
1795 *fbc_wm, *display_wm, *cursor_wm,
1796 display, cursor);
1797}
1798
46ba614c 1799static void ironlake_update_wm(struct drm_crtc *crtc)
b445e3b0 1800{
46ba614c 1801 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1802 struct drm_i915_private *dev_priv = dev->dev_private;
1803 int fbc_wm, plane_wm, cursor_wm;
1804 unsigned int enabled;
1805
1806 enabled = 0;
51cea1f4 1807 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1808 &ironlake_display_wm_info,
b0aea5dc 1809 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1810 &ironlake_cursor_wm_info,
b0aea5dc 1811 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1812 &plane_wm, &cursor_wm)) {
1813 I915_WRITE(WM0_PIPEA_ILK,
1814 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1815 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1816 " plane %d, " "cursor: %d\n",
1817 plane_wm, cursor_wm);
51cea1f4 1818 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1819 }
1820
51cea1f4 1821 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1822 &ironlake_display_wm_info,
b0aea5dc 1823 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1824 &ironlake_cursor_wm_info,
b0aea5dc 1825 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1826 &plane_wm, &cursor_wm)) {
1827 I915_WRITE(WM0_PIPEB_ILK,
1828 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1829 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1830 " plane %d, cursor: %d\n",
1831 plane_wm, cursor_wm);
51cea1f4 1832 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1833 }
1834
1835 /*
1836 * Calculate and update the self-refresh watermark only when one
1837 * display plane is used.
1838 */
1839 I915_WRITE(WM3_LP_ILK, 0);
1840 I915_WRITE(WM2_LP_ILK, 0);
1841 I915_WRITE(WM1_LP_ILK, 0);
1842
1843 if (!single_plane_enabled(enabled))
1844 return;
1845 enabled = ffs(enabled) - 1;
1846
1847 /* WM1 */
1848 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1849 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1850 &ironlake_display_srwm_info,
1851 &ironlake_cursor_srwm_info,
1852 &fbc_wm, &plane_wm, &cursor_wm))
1853 return;
1854
1855 I915_WRITE(WM1_LP_ILK,
1856 WM1_LP_SR_EN |
b0aea5dc 1857 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1858 (fbc_wm << WM1_LP_FBC_SHIFT) |
1859 (plane_wm << WM1_LP_SR_SHIFT) |
1860 cursor_wm);
1861
1862 /* WM2 */
1863 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1864 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1865 &ironlake_display_srwm_info,
1866 &ironlake_cursor_srwm_info,
1867 &fbc_wm, &plane_wm, &cursor_wm))
1868 return;
1869
1870 I915_WRITE(WM2_LP_ILK,
1871 WM2_LP_EN |
b0aea5dc 1872 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1873 (fbc_wm << WM1_LP_FBC_SHIFT) |
1874 (plane_wm << WM1_LP_SR_SHIFT) |
1875 cursor_wm);
1876
1877 /*
1878 * WM3 is unsupported on ILK, probably because we don't have latency
1879 * data for that power state
1880 */
1881}
1882
46ba614c 1883static void sandybridge_update_wm(struct drm_crtc *crtc)
b445e3b0 1884{
46ba614c 1885 struct drm_device *dev = crtc->dev;
b445e3b0 1886 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1887 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1888 u32 val;
1889 int fbc_wm, plane_wm, cursor_wm;
1890 unsigned int enabled;
1891
1892 enabled = 0;
51cea1f4 1893 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1894 &sandybridge_display_wm_info, latency,
1895 &sandybridge_cursor_wm_info, latency,
1896 &plane_wm, &cursor_wm)) {
1897 val = I915_READ(WM0_PIPEA_ILK);
1898 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1899 I915_WRITE(WM0_PIPEA_ILK, val |
1900 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1901 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1902 " plane %d, " "cursor: %d\n",
1903 plane_wm, cursor_wm);
51cea1f4 1904 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1905 }
1906
51cea1f4 1907 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1908 &sandybridge_display_wm_info, latency,
1909 &sandybridge_cursor_wm_info, latency,
1910 &plane_wm, &cursor_wm)) {
1911 val = I915_READ(WM0_PIPEB_ILK);
1912 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1913 I915_WRITE(WM0_PIPEB_ILK, val |
1914 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1915 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1916 " plane %d, cursor: %d\n",
1917 plane_wm, cursor_wm);
51cea1f4 1918 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1919 }
1920
c43d0188
CW		 1921 /*
1922 * Calculate and update the self-refresh watermark only when one
1923 * display plane is used.
1924 *
1925 * SNB support 3 levels of watermark.
1926 *
1927 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1928 * and disabled in the descending order
1929 *
1930 */
1931 I915_WRITE(WM3_LP_ILK, 0);
1932 I915_WRITE(WM2_LP_ILK, 0);
1933 I915_WRITE(WM1_LP_ILK, 0);
1934
1935 if (!single_plane_enabled(enabled) ||
1936 dev_priv->sprite_scaling_enabled)
1937 return;
1938 enabled = ffs(enabled) - 1;
1939
1940 /* WM1 */
1941 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1942 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1943 &sandybridge_display_srwm_info,
1944 &sandybridge_cursor_srwm_info,
1945 &fbc_wm, &plane_wm, &cursor_wm))
1946 return;
1947
1948 I915_WRITE(WM1_LP_ILK,
1949 WM1_LP_SR_EN |
b0aea5dc 1950 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1951 (fbc_wm << WM1_LP_FBC_SHIFT) |
1952 (plane_wm << WM1_LP_SR_SHIFT) |
1953 cursor_wm);
1954
1955 /* WM2 */
1956 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1957 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1958 &sandybridge_display_srwm_info,
1959 &sandybridge_cursor_srwm_info,
1960 &fbc_wm, &plane_wm, &cursor_wm))
1961 return;
1962
1963 I915_WRITE(WM2_LP_ILK,
1964 WM2_LP_EN |
b0aea5dc 1965 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1966 (fbc_wm << WM1_LP_FBC_SHIFT) |
1967 (plane_wm << WM1_LP_SR_SHIFT) |
1968 cursor_wm);
1969
1970 /* WM3 */
1971 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1972 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1973 &sandybridge_display_srwm_info,
1974 &sandybridge_cursor_srwm_info,
1975 &fbc_wm, &plane_wm, &cursor_wm))
1976 return;
1977
1978 I915_WRITE(WM3_LP_ILK,
1979 WM3_LP_EN |
b0aea5dc 1980 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1981 (fbc_wm << WM1_LP_FBC_SHIFT) |
1982 (plane_wm << WM1_LP_SR_SHIFT) |
1983 cursor_wm);
1984}
1985
46ba614c 1986static void ivybridge_update_wm(struct drm_crtc *crtc)
c43d0188 1987{
46ba614c 1988 struct drm_device *dev = crtc->dev;
c43d0188 1989 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1990 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 1991 u32 val;
1992 int fbc_wm, plane_wm, cursor_wm;
1993 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1994 unsigned int enabled;
1995
1996 enabled = 0;
51cea1f4 1997 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1998 &sandybridge_display_wm_info, latency,
1999 &sandybridge_cursor_wm_info, latency,
2000 &plane_wm, &cursor_wm)) {
2001 val = I915_READ(WM0_PIPEA_ILK);
2002 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003 I915_WRITE(WM0_PIPEA_ILK, val |
2004 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
2006 " plane %d, " "cursor: %d\n",
2007 plane_wm, cursor_wm);
51cea1f4 2008 enabled |= 1 << PIPE_A;
c43d0188
CW		 2009 }
2010
51cea1f4 2011 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2012 &sandybridge_display_wm_info, latency,
2013 &sandybridge_cursor_wm_info, latency,
2014 &plane_wm, &cursor_wm)) {
2015 val = I915_READ(WM0_PIPEB_ILK);
2016 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2017 I915_WRITE(WM0_PIPEB_ILK, val |
2018 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2019 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2020 " plane %d, cursor: %d\n",
2021 plane_wm, cursor_wm);
51cea1f4 2022 enabled |= 1 << PIPE_B;
c43d0188
CW		 2023 }
2024
51cea1f4 2025 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2026 &sandybridge_display_wm_info, latency,
2027 &sandybridge_cursor_wm_info, latency,
2028 &plane_wm, &cursor_wm)) {
2029 val = I915_READ(WM0_PIPEC_IVB);
2030 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2031 I915_WRITE(WM0_PIPEC_IVB, val |
2032 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2033 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2034 " plane %d, cursor: %d\n",
2035 plane_wm, cursor_wm);
51cea1f4 2036 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2037 }
2038
2039 /*
2040 * Calculate and update the self-refresh watermark only when one
2041 * display plane is used.
2042 *
2043 * SNB support 3 levels of watermark.
2044 *
2045 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2046 * and disabled in the descending order
2047 *
2048 */
2049 I915_WRITE(WM3_LP_ILK, 0);
2050 I915_WRITE(WM2_LP_ILK, 0);
2051 I915_WRITE(WM1_LP_ILK, 0);
2052
2053 if (!single_plane_enabled(enabled) ||
2054 dev_priv->sprite_scaling_enabled)
2055 return;
2056 enabled = ffs(enabled) - 1;
2057
2058 /* WM1 */
2059 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2060 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2061 &sandybridge_display_srwm_info,
2062 &sandybridge_cursor_srwm_info,
2063 &fbc_wm, &plane_wm, &cursor_wm))
2064 return;
2065
2066 I915_WRITE(WM1_LP_ILK,
2067 WM1_LP_SR_EN |
b0aea5dc 2068 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2069 (fbc_wm << WM1_LP_FBC_SHIFT) |
2070 (plane_wm << WM1_LP_SR_SHIFT) |
2071 cursor_wm);
2072
2073 /* WM2 */
2074 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2075 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2076 &sandybridge_display_srwm_info,
2077 &sandybridge_cursor_srwm_info,
2078 &fbc_wm, &plane_wm, &cursor_wm))
2079 return;
2080
2081 I915_WRITE(WM2_LP_ILK,
2082 WM2_LP_EN |
b0aea5dc 2083 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2084 (fbc_wm << WM1_LP_FBC_SHIFT) |
2085 (plane_wm << WM1_LP_SR_SHIFT) |
2086 cursor_wm);
2087
c43d0188 2088 /* WM3, note we have to correct the cursor latency */
b445e3b0 2089 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2090 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2091 &sandybridge_display_srwm_info,
2092 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2093 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2094 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2095 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2096 &sandybridge_display_srwm_info,
2097 &sandybridge_cursor_srwm_info,
2098 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2099 return;
2100
2101 I915_WRITE(WM3_LP_ILK,
2102 WM3_LP_EN |
b0aea5dc 2103 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2104 (fbc_wm << WM1_LP_FBC_SHIFT) |
2105 (plane_wm << WM1_LP_SR_SHIFT) |
2106 cursor_wm);
2107}
2108
3658729a
VS		 2109static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2110 struct drm_crtc *crtc)
801bcfff
PZ		 2111{
2112 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
fd4daa9c 2113 uint32_t pixel_rate;
801bcfff 2114
ff9a6750 2115 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2116
2117 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2118 * adjust the pixel_rate here. */
2119
fd4daa9c 2120 if (intel_crtc->config.pch_pfit.enabled) {
801bcfff 2121 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
fd4daa9c 2122 uint32_t pfit_size = intel_crtc->config.pch_pfit.size;
801bcfff 2123
37327abd
VS		 2124 pipe_w = intel_crtc->config.pipe_src_w;
2125 pipe_h = intel_crtc->config.pipe_src_h;
801bcfff
PZ		 2126 pfit_w = (pfit_size >> 16) & 0xFFFF;
2127 pfit_h = pfit_size & 0xFFFF;
2128 if (pipe_w < pfit_w)
2129 pipe_w = pfit_w;
2130 if (pipe_h < pfit_h)
2131 pipe_h = pfit_h;
2132
2133 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2134 pfit_w * pfit_h);
2135 }
2136
2137 return pixel_rate;
2138}
2139
37126462 2140/* latency must be in 0.1us units. */
23297044 2141static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2142 uint32_t latency)
2143{
2144 uint64_t ret;
2145
3312ba65
VS		 2146 if (WARN(latency == 0, "Latency value missing\n"))
2147 return UINT_MAX;
2148
801bcfff
PZ		 2149 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2150 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2151
2152 return ret;
2153}
2154
37126462 2155/* latency must be in 0.1us units. */
23297044 2156static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2157 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2158 uint32_t latency)
2159{
2160 uint32_t ret;
2161
3312ba65
VS		 2162 if (WARN(latency == 0, "Latency value missing\n"))
2163 return UINT_MAX;
2164
801bcfff
PZ		 2165 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2166 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2167 ret = DIV_ROUND_UP(ret, 64) + 2;
2168 return ret;
2169}
2170
23297044 2171static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2172 uint8_t bytes_per_pixel)
2173{
2174 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2175}
2176
801bcfff
PZ		 2177struct hsw_pipe_wm_parameters {
2178 bool active;
801bcfff
PZ		 2179 uint32_t pipe_htotal;
2180 uint32_t pixel_rate;
c35426d2
VS		 2181 struct intel_plane_wm_parameters pri;
2182 struct intel_plane_wm_parameters spr;
2183 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 2184};
2185
cca32e9a
PZ		 2186struct hsw_wm_maximums {
2187 uint16_t pri;
2188 uint16_t spr;
2189 uint16_t cur;
2190 uint16_t fbc;
2191};
2192
801bcfff
PZ		 2193struct hsw_wm_values {
2194 uint32_t wm_pipe[3];
2195 uint32_t wm_lp[3];
2196 uint32_t wm_lp_spr[3];
2197 uint32_t wm_linetime[3];
cca32e9a 2198 bool enable_fbc_wm;
801bcfff
PZ		 2199};
2200
240264f4
VS		 2201/* used in computing the new watermarks state */
2202struct intel_wm_config {
2203 unsigned int num_pipes_active;
2204 bool sprites_enabled;
2205 bool sprites_scaled;
2206 bool fbc_wm_enabled;
2207};
2208
37126462
VS		 2209/*
2210 * For both WM_PIPE and WM_LP.
2211 * mem_value must be in 0.1us units.
2212 */
ac830fe1 2213static uint32_t ilk_compute_pri_wm(const struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2214 uint32_t mem_value,
2215 bool is_lp)
801bcfff 2216{
cca32e9a
PZ		 2217 uint32_t method1, method2;
2218
c35426d2 2219 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 2220 return 0;
2221
23297044 2222 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2223 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2224 mem_value);
2225
2226 if (!is_lp)
2227 return method1;
2228
23297044 2229 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 2230 params->pipe_htotal,
c35426d2
VS		 2231 params->pri.horiz_pixels,
2232 params->pri.bytes_per_pixel,
cca32e9a
PZ		 2233 mem_value);
2234
2235 return min(method1, method2);
801bcfff
PZ		 2236}
2237
37126462
VS		 2238/*
2239 * For both WM_PIPE and WM_LP.
2240 * mem_value must be in 0.1us units.
2241 */
ac830fe1 2242static uint32_t ilk_compute_spr_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2243 uint32_t mem_value)
2244{
2245 uint32_t method1, method2;
2246
c35426d2 2247 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 2248 return 0;
2249
23297044 2250 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 2251 params->spr.bytes_per_pixel,
801bcfff 2252 mem_value);
23297044 2253 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 2254 params->pipe_htotal,
c35426d2
VS		 2255 params->spr.horiz_pixels,
2256 params->spr.bytes_per_pixel,
801bcfff
PZ		 2257 mem_value);
2258 return min(method1, method2);
2259}
2260
37126462
VS		 2261/*
2262 * For both WM_PIPE and WM_LP.
2263 * mem_value must be in 0.1us units.
2264 */
ac830fe1 2265static uint32_t ilk_compute_cur_wm(const struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2266 uint32_t mem_value)
2267{
c35426d2 2268 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 2269 return 0;
2270
23297044 2271 return ilk_wm_method2(params->pixel_rate,
801bcfff 2272 params->pipe_htotal,
c35426d2
VS		 2273 params->cur.horiz_pixels,
2274 params->cur.bytes_per_pixel,
801bcfff
PZ		 2275 mem_value);
2276}
2277
cca32e9a 2278/* Only for WM_LP. */
ac830fe1 2279static uint32_t ilk_compute_fbc_wm(const struct hsw_pipe_wm_parameters *params,
1fda9882 2280 uint32_t pri_val)
cca32e9a 2281{
c35426d2 2282 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 2283 return 0;
2284
23297044 2285 return ilk_wm_fbc(pri_val,
c35426d2
VS		 2286 params->pri.horiz_pixels,
2287 params->pri.bytes_per_pixel);
cca32e9a
PZ		 2288}
2289
158ae64f
VS		 2290static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
2291{
2292 if (INTEL_INFO(dev)->gen >= 7)
2293 return 768;
2294 else
2295 return 512;
2296}
2297
2298/* Calculate the maximum primary/sprite plane watermark */
2299static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
2300 int level,
240264f4 2301 const struct intel_wm_config *config,
158ae64f
VS		 2302 enum intel_ddb_partitioning ddb_partitioning,
2303 bool is_sprite)
2304{
2305 unsigned int fifo_size = ilk_display_fifo_size(dev);
2306 unsigned int max;
2307
2308 /* if sprites aren't enabled, sprites get nothing */
240264f4 2309 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 2310 return 0;
2311
2312 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 2313 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 2314 fifo_size /= INTEL_INFO(dev)->num_pipes;
2315
2316 /*
2317 * For some reason the non self refresh
2318 * FIFO size is only half of the self
2319 * refresh FIFO size on ILK/SNB.
2320 */
2321 if (INTEL_INFO(dev)->gen <= 6)
2322 fifo_size /= 2;
2323 }
2324
240264f4 2325 if (config->sprites_enabled) {
158ae64f
VS		 2326 /* level 0 is always calculated with 1:1 split */
2327 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
2328 if (is_sprite)
2329 fifo_size *= 5;
2330 fifo_size /= 6;
2331 } else {
2332 fifo_size /= 2;
2333 }
2334 }
2335
2336 /* clamp to max that the registers can hold */
2337 if (INTEL_INFO(dev)->gen >= 7)
2338 /* IVB/HSW primary/sprite plane watermarks */
2339 max = level == 0 ? 127 : 1023;
2340 else if (!is_sprite)
2341 /* ILK/SNB primary plane watermarks */
2342 max = level == 0 ? 127 : 511;
2343 else
2344 /* ILK/SNB sprite plane watermarks */
2345 max = level == 0 ? 63 : 255;
2346
2347 return min(fifo_size, max);
2348}
2349
2350/* Calculate the maximum cursor plane watermark */
2351static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 2352 int level,
2353 const struct intel_wm_config *config)
158ae64f
VS		 2354{
2355 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 2356 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 2357 return 64;
2358
2359 /* otherwise just report max that registers can hold */
2360 if (INTEL_INFO(dev)->gen >= 7)
2361 return level == 0 ? 63 : 255;
2362 else
2363 return level == 0 ? 31 : 63;
2364}
2365
2366/* Calculate the maximum FBC watermark */
2367static unsigned int ilk_fbc_wm_max(void)
2368{
2369 /* max that registers can hold */
2370 return 15;
2371}
2372
2373static void ilk_wm_max(struct drm_device *dev,
2374 int level,
240264f4 2375 const struct intel_wm_config *config,
158ae64f
VS		 2376 enum intel_ddb_partitioning ddb_partitioning,
2377 struct hsw_wm_maximums *max)
2378{
240264f4
VS		 2379 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
2380 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
2381 max->cur = ilk_cursor_wm_max(dev, level, config);
158ae64f
VS		 2382 max->fbc = ilk_fbc_wm_max();
2383}
2384
a9786a11
VS		 2385static bool ilk_check_wm(int level,
2386 const struct hsw_wm_maximums *max,
1fd527cc 2387 struct intel_wm_level *result)
a9786a11
VS		 2388{
2389 bool ret;
2390
2391 /* already determined to be invalid? */
2392 if (!result->enable)
2393 return false;
2394
2395 result->enable = result->pri_val <= max->pri &&
2396 result->spr_val <= max->spr &&
2397 result->cur_val <= max->cur;
2398
2399 ret = result->enable;
2400
2401 /*
2402 * HACK until we can pre-compute everything,
2403 * and thus fail gracefully if LP0 watermarks
2404 * are exceeded...
2405 */
2406 if (level == 0 && !result->enable) {
2407 if (result->pri_val > max->pri)
2408 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2409 level, result->pri_val, max->pri);
2410 if (result->spr_val > max->spr)
2411 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2412 level, result->spr_val, max->spr);
2413 if (result->cur_val > max->cur)
2414 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2415 level, result->cur_val, max->cur);
2416
2417 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2418 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2419 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2420 result->enable = true;
2421 }
2422
2423 DRM_DEBUG_KMS("WM%d: %sabled\n", level, result->enable ? "en" : "dis");
2424
2425 return ret;
2426}
2427
6f5ddd17
VS		 2428static void ilk_compute_wm_level(struct drm_i915_private *dev_priv,
2429 int level,
ac830fe1 2430 const struct hsw_pipe_wm_parameters *p,
1fd527cc 2431 struct intel_wm_level *result)
6f5ddd17
VS		 2432{
2433 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2434 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2435 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2436
2437 /* WM1+ latency values stored in 0.5us units */
2438 if (level > 0) {
2439 pri_latency *= 5;
2440 spr_latency *= 5;
2441 cur_latency *= 5;
2442 }
2443
2444 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2445 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2446 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2447 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2448 result->enable = true;
2449}
2450
5b77da33 2451static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
ac830fe1
VS		 2452 int level, const struct hsw_wm_maximums *max,
2453 const struct hsw_pipe_wm_parameters *params,
1fd527cc 2454 struct intel_wm_level *result)
cca32e9a
PZ		 2455{
2456 enum pipe pipe;
1fd527cc 2457 struct intel_wm_level res[3];
6f5ddd17
VS		 2458
2459 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++)
2460 ilk_compute_wm_level(dev_priv, level, &params[pipe], &res[pipe]);
cca32e9a 2461
6f5ddd17
VS		 2462 result->pri_val = max3(res[0].pri_val, res[1].pri_val, res[2].pri_val);
2463 result->spr_val = max3(res[0].spr_val, res[1].spr_val, res[2].spr_val);
2464 result->cur_val = max3(res[0].cur_val, res[1].cur_val, res[2].cur_val);
2465 result->fbc_val = max3(res[0].fbc_val, res[1].fbc_val, res[2].fbc_val);
2466 result->enable = true;
cca32e9a 2467
a9786a11 2468 return ilk_check_wm(level, max, result);
cca32e9a
PZ		 2469}
2470
8de123a5
VS		 2471
2472static uint32_t hsw_compute_wm_pipe(struct drm_device *dev,
ac830fe1 2473 const struct hsw_pipe_wm_parameters *params)
801bcfff 2474{
8de123a5
VS		 2475 struct drm_i915_private *dev_priv = dev->dev_private;
2476 struct intel_wm_config config = {
2477 .num_pipes_active = 1,
2478 .sprites_enabled = params->spr.enabled,
2479 .sprites_scaled = params->spr.scaled,
2480 };
2481 struct hsw_wm_maximums max;
2482 struct intel_wm_level res;
2483
2484 if (!params->active)
2485 return 0;
2486
2487 ilk_wm_max(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
801bcfff 2488
8de123a5 2489 ilk_compute_wm_level(dev_priv, 0, params, &res);
801bcfff 2490
8de123a5 2491 ilk_check_wm(0, &max, &res);
801bcfff 2492
8de123a5
VS		 2493 return (res.pri_val << WM0_PIPE_PLANE_SHIFT) |
2494 (res.spr_val << WM0_PIPE_SPRITE_SHIFT) |
2495 res.cur_val;
801bcfff
PZ		 2496}
2497
2498static uint32_t
2499hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2500{
2501 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2502 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2503 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2504 u32 linetime, ips_linetime;
1f8eeabf 2505
801bcfff
PZ		 2506 if (!intel_crtc_active(crtc))
2507 return 0;
1011d8c4 2508
1f8eeabf
ED		 2509 /* The WM are computed with base on how long it takes to fill a single
2510 * row at the given clock rate, multiplied by 8.
2511 * */
85a02deb
PZ		 2512 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2513 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2514 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2515
801bcfff
PZ		 2516 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2517 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2518}
2519
12b134df
VS		 2520static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2521{
2522 struct drm_i915_private *dev_priv = dev->dev_private;
2523
2524 if (IS_HASWELL(dev)) {
2525 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2526
2527 wm[0] = (sskpd >> 56) & 0xFF;
2528 if (wm[0] == 0)
2529 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2530 wm[1] = (sskpd >> 4) & 0xFF;
2531 wm[2] = (sskpd >> 12) & 0xFF;
2532 wm[3] = (sskpd >> 20) & 0x1FF;
2533 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2534 } else if (INTEL_INFO(dev)->gen >= 6) {
2535 uint32_t sskpd = I915_READ(MCH_SSKPD);
2536
2537 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2538 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2539 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2540 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2541 } else if (INTEL_INFO(dev)->gen >= 5) {
2542 uint32_t mltr = I915_READ(MLTR_ILK);
2543
2544 /* ILK primary LP0 latency is 700 ns */
2545 wm[0] = 7;
2546 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2547 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2548 }
2549}
2550
53615a5e
VS		 2551static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2552{
2553 /* ILK sprite LP0 latency is 1300 ns */
2554 if (INTEL_INFO(dev)->gen == 5)
2555 wm[0] = 13;
2556}
2557
2558static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2559{
2560 /* ILK cursor LP0 latency is 1300 ns */
2561 if (INTEL_INFO(dev)->gen == 5)
2562 wm[0] = 13;
2563
2564 /* WaDoubleCursorLP3Latency:ivb */
2565 if (IS_IVYBRIDGE(dev))
2566 wm[3] *= 2;
2567}
2568
ad0d6dc4 2569static int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2570{
26ec971e
VS		 2571 /* how many WM levels are we expecting */
2572 if (IS_HASWELL(dev))
ad0d6dc4 2573 return 4;
26ec971e 2574 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2575 return 3;
26ec971e 2576 else
ad0d6dc4
VS		 2577 return 2;
2578}
2579
2580static void intel_print_wm_latency(struct drm_device *dev,
2581 const char *name,
2582 const uint16_t wm[5])
2583{
2584 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2585
2586 for (level = 0; level <= max_level; level++) {
2587 unsigned int latency = wm[level];
2588
2589 if (latency == 0) {
2590 DRM_ERROR("%s WM%d latency not provided\n",
2591 name, level);
2592 continue;
2593 }
2594
2595 /* WM1+ latency values in 0.5us units */
2596 if (level > 0)
2597 latency *= 5;
2598
2599 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2600 name, level, wm[level],
2601 latency / 10, latency % 10);
2602 }
2603}
2604
53615a5e
VS		 2605static void intel_setup_wm_latency(struct drm_device *dev)
2606{
2607 struct drm_i915_private *dev_priv = dev->dev_private;
2608
2609 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2610
2611 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2612 sizeof(dev_priv->wm.pri_latency));
2613 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2614 sizeof(dev_priv->wm.pri_latency));
2615
2616 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2617 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2618
2619 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2620 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2621 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2622}
2623
801bcfff
PZ		 2624static void hsw_compute_wm_parameters(struct drm_device *dev,
2625 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2626 struct hsw_wm_maximums *lp_max_1_2,
2627 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2628{
1011d8c4 2629 struct drm_crtc *crtc;
801bcfff 2630 struct drm_plane *plane;
1011d8c4 2631 enum pipe pipe;
240264f4 2632 struct intel_wm_config config = {};
1011d8c4 2633
801bcfff
PZ		 2634 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2635 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2636 struct hsw_pipe_wm_parameters *p;
2637
2638 pipe = intel_crtc->pipe;
2639 p = &params[pipe];
2640
2641 p->active = intel_crtc_active(crtc);
2642 if (!p->active)
2643 continue;
2644
240264f4 2645 config.num_pipes_active++;
cca32e9a 2646
801bcfff 2647 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2648 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
c35426d2
VS		 2649 p->pri.bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2650 p->cur.bytes_per_pixel = 4;
37327abd 2651 p->pri.horiz_pixels = intel_crtc->config.pipe_src_w;
c35426d2
VS		 2652 p->cur.horiz_pixels = 64;
2653 /* TODO: for now, assume primary and cursor planes are always enabled. */
2654 p->pri.enabled = true;
2655 p->cur.enabled = true;
801bcfff
PZ		 2656 }
2657
2658 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2659 struct intel_plane *intel_plane = to_intel_plane(plane);
2660 struct hsw_pipe_wm_parameters *p;
2661
2662 pipe = intel_plane->pipe;
2663 p = &params[pipe];
2664
c35426d2 2665 p->spr = intel_plane->wm;
cca32e9a 2666
c35426d2
VS		 2667 config.sprites_enabled |= p->spr.enabled;
2668 config.sprites_scaled |= p->spr.scaled;
cca32e9a
PZ		 2669 }
2670
240264f4 2671 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_1_2, lp_max_1_2);
158ae64f
VS		 2672
2673 /* 5/6 split only in single pipe config on IVB+ */
240264f4
VS		 2674 if (INTEL_INFO(dev)->gen >= 7 && config.num_pipes_active <= 1)
2675 ilk_wm_max(dev, 1, &config, INTEL_DDB_PART_5_6, lp_max_5_6);
158ae64f
VS		 2676 else
2677 *lp_max_5_6 = *lp_max_1_2;
801bcfff
PZ		 2678}
2679
2680static void hsw_compute_wm_results(struct drm_device *dev,
ac830fe1
VS		 2681 const struct hsw_pipe_wm_parameters *params,
2682 const struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2683 struct hsw_wm_values *results)
2684{
2685 struct drm_i915_private *dev_priv = dev->dev_private;
2686 struct drm_crtc *crtc;
1fd527cc 2687 struct intel_wm_level lp_results[4] = {};
801bcfff 2688 enum pipe pipe;
cca32e9a
PZ		 2689 int level, max_level, wm_lp;
2690
2691 for (level = 1; level <= 4; level++)
5b77da33
VS		 2692 if (!hsw_compute_lp_wm(dev_priv, level,
2693 lp_maximums, params,
cca32e9a
PZ		 2694 &lp_results[level - 1]))
2695 break;
2696 max_level = level - 1;
2697
5c536613
VS		 2698 memset(results, 0, sizeof(*results));
2699
cca32e9a
PZ		 2700 /* The spec says it is preferred to disable FBC WMs instead of disabling
2701 * a WM level. */
2702 results->enable_fbc_wm = true;
2703 for (level = 1; level <= max_level; level++) {
16e54061 2704 if (lp_results[level - 1].fbc_val > lp_maximums->fbc) {
cca32e9a 2705 results->enable_fbc_wm = false;
71fff20f 2706 lp_results[level - 1].fbc_val = 0;
cca32e9a
PZ		 2707 }
2708 }
2709
cca32e9a 2710 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2711 const struct intel_wm_level *r;
801bcfff 2712
cca32e9a
PZ		 2713 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2714 if (level > max_level)
2715 break;
2716
2717 r = &lp_results[level - 1];
2718 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2719 r->fbc_val,
2720 r->pri_val,
2721 r->cur_val);
2722 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2723 }
801bcfff
PZ		 2724
2725 for_each_pipe(pipe)
8de123a5 2726 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev,
801bcfff 2727 &params[pipe]);
1011d8c4
PZ		 2728
2729 for_each_pipe(pipe) {
2730 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2731 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2732 }
2733}
2734
861f3389
PZ		 2735/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2736 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2737static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2738 struct hsw_wm_values *r2)
861f3389
PZ		 2739{
2740 int i, val_r1 = 0, val_r2 = 0;
2741
2742 for (i = 0; i < 3; i++) {
2743 if (r1->wm_lp[i] & WM3_LP_EN)
2744 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2745 if (r2->wm_lp[i] & WM3_LP_EN)
2746 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2747 }
2748
2749 if (val_r1 == val_r2) {
2750 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2751 return r2;
2752 else
2753 return r1;
2754 } else if (val_r1 > val_r2) {
2755 return r1;
2756 } else {
2757 return r2;
2758 }
2759}
2760
801bcfff
PZ		 2761/*
2762 * The spec says we shouldn't write when we don't need, because every write
2763 * causes WMs to be re-evaluated, expending some power.
2764 */
2765static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2766 struct hsw_wm_values *results,
77c122bc 2767 enum intel_ddb_partitioning partitioning)
801bcfff
PZ		 2768{
2769 struct hsw_wm_values previous;
2770 uint32_t val;
77c122bc 2771 enum intel_ddb_partitioning prev_partitioning;
cca32e9a 2772 bool prev_enable_fbc_wm;
801bcfff
PZ		 2773
2774 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2775 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2776 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2777 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2778 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2779 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2780 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2781 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2782 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2783 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2784 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2785 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2786
2787 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
77c122bc 2788 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
801bcfff 2789
cca32e9a
PZ		 2790 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2791
801bcfff
PZ		 2792 if (memcmp(results->wm_pipe, previous.wm_pipe,
2793 sizeof(results->wm_pipe)) == 0 &&
2794 memcmp(results->wm_lp, previous.wm_lp,
2795 sizeof(results->wm_lp)) == 0 &&
2796 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2797 sizeof(results->wm_lp_spr)) == 0 &&
2798 memcmp(results->wm_linetime, previous.wm_linetime,
2799 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2800 partitioning == prev_partitioning &&
2801 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2802 return;
2803
2804 if (previous.wm_lp[2] != 0)
2805 I915_WRITE(WM3_LP_ILK, 0);
2806 if (previous.wm_lp[1] != 0)
2807 I915_WRITE(WM2_LP_ILK, 0);
2808 if (previous.wm_lp[0] != 0)
2809 I915_WRITE(WM1_LP_ILK, 0);
2810
2811 if (previous.wm_pipe[0] != results->wm_pipe[0])
2812 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2813 if (previous.wm_pipe[1] != results->wm_pipe[1])
2814 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2815 if (previous.wm_pipe[2] != results->wm_pipe[2])
2816 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2817
2818 if (previous.wm_linetime[0] != results->wm_linetime[0])
2819 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2820 if (previous.wm_linetime[1] != results->wm_linetime[1])
2821 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2822 if (previous.wm_linetime[2] != results->wm_linetime[2])
2823 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2824
2825 if (prev_partitioning != partitioning) {
2826 val = I915_READ(WM_MISC);
77c122bc 2827 if (partitioning == INTEL_DDB_PART_1_2)
801bcfff
PZ		 2828 val &= ~WM_MISC_DATA_PARTITION_5_6;
2829 else
2830 val |= WM_MISC_DATA_PARTITION_5_6;
2831 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2832 }
2833
cca32e9a
PZ		 2834 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2835 val = I915_READ(DISP_ARB_CTL);
2836 if (results->enable_fbc_wm)
2837 val &= ~DISP_FBC_WM_DIS;
2838 else
2839 val |= DISP_FBC_WM_DIS;
2840 I915_WRITE(DISP_ARB_CTL, val);
2841 }
2842
801bcfff
PZ		 2843 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2844 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2845 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2846 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2847 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2848 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2849
2850 if (results->wm_lp[0] != 0)
2851 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2852 if (results->wm_lp[1] != 0)
2853 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2854 if (results->wm_lp[2] != 0)
2855 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2856}
2857
46ba614c 2858static void haswell_update_wm(struct drm_crtc *crtc)
801bcfff 2859{
46ba614c 2860 struct drm_device *dev = crtc->dev;
801bcfff 2861 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2862 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2863 struct hsw_pipe_wm_parameters params[3];
861f3389 2864 struct hsw_wm_values results_1_2, results_5_6, *best_results;
77c122bc 2865 enum intel_ddb_partitioning partitioning;
861f3389 2866
12b134df 2867 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2868
53615a5e 2869 hsw_compute_wm_results(dev, params,
53615a5e 2870 &lp_max_1_2, &results_1_2);
861f3389 2871 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2872 hsw_compute_wm_results(dev, params,
53615a5e 2873 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2874 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2875 } else {
2876 best_results = &results_1_2;
2877 }
2878
2879 partitioning = (best_results == &results_1_2) ?
77c122bc 2880 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 2881
861f3389 2882 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2883}
2884
adf3d35e
VS		 2885static void haswell_update_sprite_wm(struct drm_plane *plane,
2886 struct drm_crtc *crtc,
526682e9 2887 uint32_t sprite_width, int pixel_size,
bdd57d03 2888 bool enabled, bool scaled)
526682e9 2889{
adf3d35e 2890 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 2891
adf3d35e
VS		 2892 intel_plane->wm.enabled = enabled;
2893 intel_plane->wm.scaled = scaled;
2894 intel_plane->wm.horiz_pixels = sprite_width;
2895 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 2896
46ba614c 2897 haswell_update_wm(crtc);
526682e9
PZ		 2898}
2899
b445e3b0
ED		 2900static bool
2901sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2902 uint32_t sprite_width, int pixel_size,
2903 const struct intel_watermark_params *display,
2904 int display_latency_ns, int *sprite_wm)
2905{
2906 struct drm_crtc *crtc;
2907 int clock;
2908 int entries, tlb_miss;
2909
2910 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2911 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2912 *sprite_wm = display->guard_size;
2913 return false;
2914 }
2915
4fe8590a 2916 clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
b445e3b0
ED		 2917
2918 /* Use the small buffer method to calculate the sprite watermark */
2919 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2920 tlb_miss = display->fifo_size*display->cacheline_size -
2921 sprite_width * 8;
2922 if (tlb_miss > 0)
2923 entries += tlb_miss;
2924 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2925 *sprite_wm = entries + display->guard_size;
2926 if (*sprite_wm > (int)display->max_wm)
2927 *sprite_wm = display->max_wm;
2928
2929 return true;
2930}
2931
2932static bool
2933sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2934 uint32_t sprite_width, int pixel_size,
2935 const struct intel_watermark_params *display,
2936 int latency_ns, int *sprite_wm)
2937{
2938 struct drm_crtc *crtc;
2939 unsigned long line_time_us;
2940 int clock;
2941 int line_count, line_size;
2942 int small, large;
2943 int entries;
2944
2945 if (!latency_ns) {
2946 *sprite_wm = 0;
2947 return false;
2948 }
2949
2950 crtc = intel_get_crtc_for_plane(dev, plane);
4fe8590a 2951 clock = to_intel_crtc(crtc)->config.adjusted_mode.clock;
b445e3b0
ED		 2952 if (!clock) {
2953 *sprite_wm = 0;
2954 return false;
2955 }
2956
2957 line_time_us = (sprite_width * 1000) / clock;
2958 if (!line_time_us) {
2959 *sprite_wm = 0;
2960 return false;
2961 }
2962
2963 line_count = (latency_ns / line_time_us + 1000) / 1000;
2964 line_size = sprite_width * pixel_size;
2965
2966 /* Use the minimum of the small and large buffer method for primary */
2967 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2968 large = line_count * line_size;
2969
2970 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2971 *sprite_wm = entries + display->guard_size;
2972
2973 return *sprite_wm > 0x3ff ? false : true;
2974}
2975
adf3d35e
VS		 2976static void sandybridge_update_sprite_wm(struct drm_plane *plane,
2977 struct drm_crtc *crtc,
4c4ff43a 2978 uint32_t sprite_width, int pixel_size,
39db4a4d 2979 bool enabled, bool scaled)
b445e3b0 2980{
adf3d35e 2981 struct drm_device *dev = plane->dev;
b445e3b0 2982 struct drm_i915_private *dev_priv = dev->dev_private;
adf3d35e 2983 int pipe = to_intel_plane(plane)->pipe;
b0aea5dc 2984 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2985 u32 val;
2986 int sprite_wm, reg;
2987 int ret;
2988
39db4a4d 2989 if (!enabled)
4c4ff43a
PZ		 2990 return;
2991
b445e3b0
ED		 2992 switch (pipe) {
2993 case 0:
2994 reg = WM0_PIPEA_ILK;
2995 break;
2996 case 1:
2997 reg = WM0_PIPEB_ILK;
2998 break;
2999 case 2:
3000 reg = WM0_PIPEC_IVB;
3001 break;
3002 default:
3003 return; /* bad pipe */
3004 }
3005
3006 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
3007 &sandybridge_display_wm_info,
3008 latency, &sprite_wm);
3009 if (!ret) {
84f44ce7
VS		 3010 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
3011 pipe_name(pipe));
b445e3b0
ED		 3012 return;
3013 }
3014
3015 val = I915_READ(reg);
3016 val &= ~WM0_PIPE_SPRITE_MASK;
3017 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 3018 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 3019
3020
3021 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3022 pixel_size,
3023 &sandybridge_display_srwm_info,
b0aea5dc 3024 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 3025 &sprite_wm);
3026 if (!ret) {
84f44ce7
VS		 3027 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
3028 pipe_name(pipe));
b445e3b0
ED		 3029 return;
3030 }
3031 I915_WRITE(WM1S_LP_ILK, sprite_wm);
3032
3033 /* Only IVB has two more LP watermarks for sprite */
3034 if (!IS_IVYBRIDGE(dev))
3035 return;
3036
3037 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3038 pixel_size,
3039 &sandybridge_display_srwm_info,
b0aea5dc 3040 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 3041 &sprite_wm);
3042 if (!ret) {
84f44ce7
VS		 3043 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
3044 pipe_name(pipe));
b445e3b0
ED		 3045 return;
3046 }
3047 I915_WRITE(WM2S_LP_IVB, sprite_wm);
3048
3049 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
3050 pixel_size,
3051 &sandybridge_display_srwm_info,
b0aea5dc 3052 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 3053 &sprite_wm);
3054 if (!ret) {
84f44ce7
VS		 3055 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
3056 pipe_name(pipe));
b445e3b0
ED		 3057 return;
3058 }
3059 I915_WRITE(WM3S_LP_IVB, sprite_wm);
3060}
3061
3062/**
3063 * intel_update_watermarks - update FIFO watermark values based on current modes
3064 *
3065 * Calculate watermark values for the various WM regs based on current mode
3066 * and plane configuration.
3067 *
3068 * There are several cases to deal with here:
3069 * - normal (i.e. non-self-refresh)
3070 * - self-refresh (SR) mode
3071 * - lines are large relative to FIFO size (buffer can hold up to 2)
3072 * - lines are small relative to FIFO size (buffer can hold more than 2
3073 * lines), so need to account for TLB latency
3074 *
3075 * The normal calculation is:
3076 * watermark = dotclock * bytes per pixel * latency
3077 * where latency is platform & configuration dependent (we assume pessimal
3078 * values here).
3079 *
3080 * The SR calculation is:
3081 * watermark = (trunc(latency/line time)+1) * surface width *
3082 * bytes per pixel
3083 * where
3084 * line time = htotal / dotclock
3085 * surface width = hdisplay for normal plane and 64 for cursor
3086 * and latency is assumed to be high, as above.
3087 *
3088 * The final value programmed to the register should always be rounded up,
3089 * and include an extra 2 entries to account for clock crossings.
3090 *
3091 * We don't use the sprite, so we can ignore that. And on Crestline we have
3092 * to set the non-SR watermarks to 8.
3093 */
46ba614c 3094void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 3095{
46ba614c 3096 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 3097
3098 if (dev_priv->display.update_wm)
46ba614c 3099 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 3100}
3101
adf3d35e
VS		 3102void intel_update_sprite_watermarks(struct drm_plane *plane,
3103 struct drm_crtc *crtc,
4c4ff43a 3104 uint32_t sprite_width, int pixel_size,
39db4a4d 3105 bool enabled, bool scaled)
b445e3b0 3106{
adf3d35e 3107 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 3108
3109 if (dev_priv->display.update_sprite_wm)
adf3d35e 3110 dev_priv->display.update_sprite_wm(plane, crtc, sprite_width,
39db4a4d 3111 pixel_size, enabled, scaled);
b445e3b0
ED		 3112}
3113
2b4e57bd
ED		 3114static struct drm_i915_gem_object *
3115intel_alloc_context_page(struct drm_device *dev)
3116{
3117 struct drm_i915_gem_object *ctx;
3118 int ret;
3119
3120 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3121
3122 ctx = i915_gem_alloc_object(dev, 4096);
3123 if (!ctx) {
3124 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
3125 return NULL;
3126 }
3127
c37e2204 3128 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 3129 if (ret) {
3130 DRM_ERROR("failed to pin power context: %d\n", ret);
3131 goto err_unref;
3132 }
3133
3134 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
3135 if (ret) {
3136 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
3137 goto err_unpin;
3138 }
3139
3140 return ctx;
3141
3142err_unpin:
3143 i915_gem_object_unpin(ctx);
3144err_unref:
3145 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3146 return NULL;
3147}
3148
9270388e
DV		 3149/**
3150 * Lock protecting IPS related data structures
9270388e
DV		 3151 */
3152DEFINE_SPINLOCK(mchdev_lock);
3153
3154/* Global for IPS driver to get at the current i915 device. Protected by
3155 * mchdev_lock. */
3156static struct drm_i915_private *i915_mch_dev;
3157
2b4e57bd
ED		 3158bool ironlake_set_drps(struct drm_device *dev, u8 val)
3159{
3160 struct drm_i915_private *dev_priv = dev->dev_private;
3161 u16 rgvswctl;
3162
9270388e
DV		 3163 assert_spin_locked(&mchdev_lock);
3164
2b4e57bd
ED		 3165 rgvswctl = I915_READ16(MEMSWCTL);
3166 if (rgvswctl & MEMCTL_CMD_STS) {
3167 DRM_DEBUG("gpu busy, RCS change rejected\n");
3168 return false; /* still busy with another command */
3169 }
3170
3171 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3172 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3173 I915_WRITE16(MEMSWCTL, rgvswctl);
3174 POSTING_READ16(MEMSWCTL);
3175
3176 rgvswctl |= MEMCTL_CMD_STS;
3177 I915_WRITE16(MEMSWCTL, rgvswctl);
3178
3179 return true;
3180}
3181
8090c6b9 3182static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3183{
3184 struct drm_i915_private *dev_priv = dev->dev_private;
3185 u32 rgvmodectl = I915_READ(MEMMODECTL);
3186 u8 fmax, fmin, fstart, vstart;
3187
9270388e
DV		 3188 spin_lock_irq(&mchdev_lock);
3189
2b4e57bd
ED		 3190 /* Enable temp reporting */
3191 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3192 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3193
3194 /* 100ms RC evaluation intervals */
3195 I915_WRITE(RCUPEI, 100000);
3196 I915_WRITE(RCDNEI, 100000);
3197
3198 /* Set max/min thresholds to 90ms and 80ms respectively */
3199 I915_WRITE(RCBMAXAVG, 90000);
3200 I915_WRITE(RCBMINAVG, 80000);
3201
3202 I915_WRITE(MEMIHYST, 1);
3203
3204 /* Set up min, max, and cur for interrupt handling */
3205 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3206 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3207 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3208 MEMMODE_FSTART_SHIFT;
3209
3210 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3211 PXVFREQ_PX_SHIFT;
3212
20e4d407
DV		 3213 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3214 dev_priv->ips.fstart = fstart;
2b4e57bd 3215
20e4d407
DV		 3216 dev_priv->ips.max_delay = fstart;
3217 dev_priv->ips.min_delay = fmin;
3218 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3219
3220 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3221 fmax, fmin, fstart);
3222
3223 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3224
3225 /*
3226 * Interrupts will be enabled in ironlake_irq_postinstall
3227 */
3228
3229 I915_WRITE(VIDSTART, vstart);
3230 POSTING_READ(VIDSTART);
3231
3232 rgvmodectl |= MEMMODE_SWMODE_EN;
3233 I915_WRITE(MEMMODECTL, rgvmodectl);
3234
9270388e 3235 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3236 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3237 mdelay(1);
2b4e57bd
ED		 3238
3239 ironlake_set_drps(dev, fstart);
3240
20e4d407 3241 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3242 I915_READ(0x112e0);
20e4d407
DV		 3243 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3244 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3245 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3246
3247 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3248}
3249
8090c6b9 3250static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3251{
3252 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3253 u16 rgvswctl;
3254
3255 spin_lock_irq(&mchdev_lock);
3256
3257 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3258
3259 /* Ack interrupts, disable EFC interrupt */
3260 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3261 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3262 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3263 I915_WRITE(DEIIR, DE_PCU_EVENT);
3264 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3265
3266 /* Go back to the starting frequency */
20e4d407 3267 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3268 mdelay(1);
2b4e57bd
ED		 3269 rgvswctl |= MEMCTL_CMD_STS;
3270 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3271 mdelay(1);
2b4e57bd 3272
9270388e 3273 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3274}
3275
acbe9475
DV		 3276/* There's a funny hw issue where the hw returns all 0 when reading from
3277 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3278 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3279 * all limits and the gpu stuck at whatever frequency it is at atm).
3280 */
65bccb5c 3281static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3282{
7b9e0ae6 3283 u32 limits;
2b4e57bd 3284
7b9e0ae6 3285 limits = 0;
c6a828d3
DV		 3286
3287 if (*val >= dev_priv->rps.max_delay)
3288 *val = dev_priv->rps.max_delay;
3289 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3290
3291 /* Only set the down limit when we've reached the lowest level to avoid
3292 * getting more interrupts, otherwise leave this clear. This prevents a
3293 * race in the hw when coming out of rc6: There's a tiny window where
3294 * the hw runs at the minimal clock before selecting the desired
3295 * frequency, if the down threshold expires in that window we will not
3296 * receive a down interrupt. */
c6a828d3
DV		 3297 if (*val <= dev_priv->rps.min_delay) {
3298 *val = dev_priv->rps.min_delay;
3299 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3300 }
3301
3302 return limits;
3303}
3304
3305void gen6_set_rps(struct drm_device *dev, u8 val)
3306{
3307 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3308 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3309
4fc688ce 3310 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3311 WARN_ON(val > dev_priv->rps.max_delay);
3312 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3313
c6a828d3 3314 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3315 return;
3316
92bd1bf0
RV		 3317 if (IS_HASWELL(dev))
3318 I915_WRITE(GEN6_RPNSWREQ,
3319 HSW_FREQUENCY(val));
3320 else
3321 I915_WRITE(GEN6_RPNSWREQ,
3322 GEN6_FREQUENCY(val) |
3323 GEN6_OFFSET(0) |
3324 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3325
3326 /* Make sure we continue to get interrupts
3327 * until we hit the minimum or maximum frequencies.
3328 */
3329 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3330
d5570a72
BW		 3331 POSTING_READ(GEN6_RPNSWREQ);
3332
c6a828d3 3333 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3334
3335 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3336}
3337
80814ae4
VS		 3338/*
3339 * Wait until the previous freq change has completed,
3340 * or the timeout elapsed, and then update our notion
3341 * of the current GPU frequency.
3342 */
3343static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3344{
80814ae4
VS		 3345 u32 pval;
3346
3347 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3348
e8474409
VS		 3349 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3350 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3351
3352 pval >>= 8;
3353
3354 if (pval != dev_priv->rps.cur_delay)
3355 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3356 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3357 dev_priv->rps.cur_delay,
3358 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3359
3360 dev_priv->rps.cur_delay = pval;
3361}
3362
0a073b84
JB		 3363void valleyview_set_rps(struct drm_device *dev, u8 val)
3364{
3365 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3366
3367 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3368
3369 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3370 WARN_ON(val > dev_priv->rps.max_delay);
3371 WARN_ON(val < dev_priv->rps.min_delay);
3372
80814ae4
VS		 3373 vlv_update_rps_cur_delay(dev_priv);
3374
73008b98 3375 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3376 vlv_gpu_freq(dev_priv->mem_freq,
3377 dev_priv->rps.cur_delay),
73008b98
VS		 3378 dev_priv->rps.cur_delay,
3379 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3380
3381 if (val == dev_priv->rps.cur_delay)
3382 return;
3383
ae99258f 3384 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3385
80814ae4 3386 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3387
3388 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3389}
3390
44fc7d5c 3391static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3392{
3393 struct drm_i915_private *dev_priv = dev->dev_private;
3394
2b4e57bd 3395 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3396 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3397 /* Complete PM interrupt masking here doesn't race with the rps work
3398 * item again unmasking PM interrupts because that is using a different
3399 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3400 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3401
59cdb63d 3402 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3403 dev_priv->rps.pm_iir = 0;
59cdb63d 3404 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3405
4848405c 3406 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3407}
3408
44fc7d5c 3409static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3410{
3411 struct drm_i915_private *dev_priv = dev->dev_private;
3412
3413 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3414 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3415
44fc7d5c
DV		 3416 gen6_disable_rps_interrupts(dev);
3417}
3418
3419static void valleyview_disable_rps(struct drm_device *dev)
3420{
3421 struct drm_i915_private *dev_priv = dev->dev_private;
3422
3423 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3424
44fc7d5c 3425 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3426
3427 if (dev_priv->vlv_pctx) {
3428 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3429 dev_priv->vlv_pctx = NULL;
3430 }
d20d4f0c
JB		 3431}
3432
2b4e57bd
ED		 3433int intel_enable_rc6(const struct drm_device *dev)
3434{
eb4926e4
DL		 3435 /* No RC6 before Ironlake */
3436 if (INTEL_INFO(dev)->gen < 5)
3437 return 0;
3438
456470eb 3439 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3440 if (i915_enable_rc6 >= 0)
3441 return i915_enable_rc6;
3442
6567d748
CW		 3443 /* Disable RC6 on Ironlake */
3444 if (INTEL_INFO(dev)->gen == 5)
3445 return 0;
2b4e57bd 3446
456470eb
DV		 3447 if (IS_HASWELL(dev)) {
3448 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3449 return INTEL_RC6_ENABLE;
456470eb 3450 }
2b4e57bd 3451
456470eb 3452 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3453 if (INTEL_INFO(dev)->gen == 6) {
3454 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3455 return INTEL_RC6_ENABLE;
3456 }
456470eb 3457
2b4e57bd
ED		 3458 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3459 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3460}
3461
44fc7d5c
DV		 3462static void gen6_enable_rps_interrupts(struct drm_device *dev)
3463{
3464 struct drm_i915_private *dev_priv = dev->dev_private;
a9c1f90c 3465 u32 enabled_intrs;
44fc7d5c
DV		 3466
3467 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3468 WARN_ON(dev_priv->rps.pm_iir);
edbfdb45 3469 snb_enable_pm_irq(dev_priv, GEN6_PM_RPS_EVENTS);
44fc7d5c
DV		 3470 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3471 spin_unlock_irq(&dev_priv->irq_lock);
a9c1f90c 3472
fd547d25 3473 /* only unmask PM interrupts we need. Mask all others. */
a9c1f90c
MK		 3474 enabled_intrs = GEN6_PM_RPS_EVENTS;
3475
3476 /* IVB and SNB hard hangs on looping batchbuffer
3477 * if GEN6_PM_UP_EI_EXPIRED is masked.
3478 */
3479 if (INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev))
3480 enabled_intrs |= GEN6_PM_RP_UP_EI_EXPIRED;
3481
3482 I915_WRITE(GEN6_PMINTRMSK, ~enabled_intrs);
44fc7d5c
DV		 3483}
3484
79f5b2c7 3485static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3486{
79f5b2c7 3487 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3488 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3489 u32 rp_state_cap;
3490 u32 gt_perf_status;
31643d54 3491 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3492 u32 gtfifodbg;
2b4e57bd 3493 int rc6_mode;
42c0526c 3494 int i, ret;
2b4e57bd 3495
4fc688ce 3496 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3497
2b4e57bd
ED		 3498 /* Here begins a magic sequence of register writes to enable
3499 * auto-downclocking.
3500 *
3501 * Perhaps there might be some value in exposing these to
3502 * userspace...
3503 */
3504 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3505
3506 /* Clear the DBG now so we don't confuse earlier errors */
3507 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3508 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3509 I915_WRITE(GTFIFODBG, gtfifodbg);
3510 }
3511
3512 gen6_gt_force_wake_get(dev_priv);
3513
7b9e0ae6
CW		 3514 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3515 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3516
31c77388
BW		 3517 /* In units of 50MHz */
3518 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3519 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3520 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3521
2b4e57bd
ED		 3522 /* disable the counters and set deterministic thresholds */
3523 I915_WRITE(GEN6_RC_CONTROL, 0);
3524
3525 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3526 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3527 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3528 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3529 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3530
b4519513
CW		 3531 for_each_ring(ring, dev_priv, i)
3532 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3533
3534 I915_WRITE(GEN6_RC_SLEEP, 0);
3535 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
351aa566
SM		 3536 if (INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev))
3537 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
3538 else
3539 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3540 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3541 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3542
5a7dc92a 3543 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3544 rc6_mode = intel_enable_rc6(dev_priv->dev);
3545 if (rc6_mode & INTEL_RC6_ENABLE)
3546 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3547
5a7dc92a
ED		 3548 /* We don't use those on Haswell */
3549 if (!IS_HASWELL(dev)) {
3550 if (rc6_mode & INTEL_RC6p_ENABLE)
3551 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3552
5a7dc92a
ED		 3553 if (rc6_mode & INTEL_RC6pp_ENABLE)
3554 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3555 }
2b4e57bd
ED		 3556
3557 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3558 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3559 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3560 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3561
3562 I915_WRITE(GEN6_RC_CONTROL,
3563 rc6_mask |
3564 GEN6_RC_CTL_EI_MODE(1) |
3565 GEN6_RC_CTL_HW_ENABLE);
3566
92bd1bf0
RV		 3567 if (IS_HASWELL(dev)) {
3568 I915_WRITE(GEN6_RPNSWREQ,
3569 HSW_FREQUENCY(10));
3570 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3571 HSW_FREQUENCY(12));
3572 } else {
3573 I915_WRITE(GEN6_RPNSWREQ,
3574 GEN6_FREQUENCY(10) |
3575 GEN6_OFFSET(0) |
3576 GEN6_AGGRESSIVE_TURBO);
3577 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3578 GEN6_FREQUENCY(12));
3579 }
2b4e57bd
ED		 3580
3581 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3582 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3583 dev_priv->rps.max_delay << 24 |
3584 dev_priv->rps.min_delay << 16);
5a7dc92a 3585
1ee9ae32
DV		 3586 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3587 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3588 I915_WRITE(GEN6_RP_UP_EI, 66000);
3589 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3590
2b4e57bd
ED		 3591 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3592 I915_WRITE(GEN6_RP_CONTROL,
3593 GEN6_RP_MEDIA_TURBO |
89ba829e 3594 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3595 GEN6_RP_MEDIA_IS_GFX |
3596 GEN6_RP_ENABLE |
3597 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3598 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3599
42c0526c 3600 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3601 if (!ret) {
42c0526c
BW		 3602 pcu_mbox = 0;
3603 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3604 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3605 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3606 (dev_priv->rps.max_delay & 0xff) * 50,
3607 (pcu_mbox & 0xff) * 50);
31c77388 3608 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3609 }
3610 } else {
3611 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3612 }
3613
7b9e0ae6 3614 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3615
44fc7d5c 3616 gen6_enable_rps_interrupts(dev);
2b4e57bd 3617
31643d54
BW		 3618 rc6vids = 0;
3619 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3620 if (IS_GEN6(dev) && ret) {
3621 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3622 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3623 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3624 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3625 rc6vids &= 0xffff00;
3626 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3627 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3628 if (ret)
3629 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3630 }
3631
2b4e57bd 3632 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3633}
3634
c67a470b 3635void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3636{
79f5b2c7 3637 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3638 int min_freq = 15;
3ebecd07
CW		 3639 unsigned int gpu_freq;
3640 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3641 int scaling_factor = 180;
3642
4fc688ce 3643 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3644
2b4e57bd
ED		 3645 max_ia_freq = cpufreq_quick_get_max(0);
3646 /*
3647 * Default to measured freq if none found, PCU will ensure we don't go
3648 * over
3649 */
3650 if (!max_ia_freq)
3651 max_ia_freq = tsc_khz;
3652
3653 /* Convert from kHz to MHz */
3654 max_ia_freq /= 1000;
3655
3ebecd07
CW		 3656 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3657 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3658 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3659
2b4e57bd
ED		 3660 /*
3661 * For each potential GPU frequency, load a ring frequency we'd like
3662 * to use for memory access. We do this by specifying the IA frequency
3663 * the PCU should use as a reference to determine the ring frequency.
3664 */
c6a828d3 3665 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3666 gpu_freq--) {
c6a828d3 3667 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3668 unsigned int ia_freq = 0, ring_freq = 0;
3669
3670 if (IS_HASWELL(dev)) {
3671 ring_freq = (gpu_freq * 5 + 3) / 4;
3672 ring_freq = max(min_ring_freq, ring_freq);
3673 /* leave ia_freq as the default, chosen by cpufreq */
3674 } else {
3675 /* On older processors, there is no separate ring
3676 * clock domain, so in order to boost the bandwidth
3677 * of the ring, we need to upclock the CPU (ia_freq).
3678 *
3679 * For GPU frequencies less than 750MHz,
3680 * just use the lowest ring freq.
3681 */
3682 if (gpu_freq < min_freq)
3683 ia_freq = 800;
3684 else
3685 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3686 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3687 }
2b4e57bd 3688
42c0526c
BW		 3689 sandybridge_pcode_write(dev_priv,
3690 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3691 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3692 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3693 gpu_freq);
2b4e57bd 3694 }
2b4e57bd
ED		 3695}
3696
0a073b84
JB		 3697int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3698{
3699 u32 val, rp0;
3700
64936258 3701 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3702
3703 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3704 /* Clamp to max */
3705 rp0 = min_t(u32, rp0, 0xea);
3706
3707 return rp0;
3708}
3709
3710static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3711{
3712 u32 val, rpe;
3713
64936258 3714 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3715 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3716 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3717 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3718
3719 return rpe;
3720}
3721
3722int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3723{
64936258 3724 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3725}
3726
52ceb908
JB		 3727static void vlv_rps_timer_work(struct work_struct *work)
3728{
3729 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3730 rps.vlv_work.work);
3731
3732 /*
3733 * Timer fired, we must be idle. Drop to min voltage state.
3734 * Note: we use RPe here since it should match the
3735 * Vmin we were shooting for. That should give us better
3736 * perf when we come back out of RC6 than if we used the
3737 * min freq available.
3738 */
3739 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3740 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3741 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3742 mutex_unlock(&dev_priv->rps.hw_lock);
3743}
3744
c9cddffc
JB		 3745static void valleyview_setup_pctx(struct drm_device *dev)
3746{
3747 struct drm_i915_private *dev_priv = dev->dev_private;
3748 struct drm_i915_gem_object *pctx;
3749 unsigned long pctx_paddr;
3750 u32 pcbr;
3751 int pctx_size = 24*1024;
3752
3753 pcbr = I915_READ(VLV_PCBR);
3754 if (pcbr) {
3755 /* BIOS set it up already, grab the pre-alloc'd space */
3756 int pcbr_offset;
3757
3758 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3759 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3760 pcbr_offset,
190d6cd5 3761 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3762 pctx_size);
3763 goto out;
3764 }
3765
3766 /*
3767 * From the Gunit register HAS:
3768 * The Gfx driver is expected to program this register and ensure
3769 * proper allocation within Gfx stolen memory. For example, this
3770 * register should be programmed such than the PCBR range does not
3771 * overlap with other ranges, such as the frame buffer, protected
3772 * memory, or any other relevant ranges.
3773 */
3774 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3775 if (!pctx) {
3776 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3777 return;
3778 }
3779
3780 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3781 I915_WRITE(VLV_PCBR, pctx_paddr);
3782
3783out:
3784 dev_priv->vlv_pctx = pctx;
3785}
3786
0a073b84
JB		 3787static void valleyview_enable_rps(struct drm_device *dev)
3788{
3789 struct drm_i915_private *dev_priv = dev->dev_private;
3790 struct intel_ring_buffer *ring;
a2b23fe0 3791 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 3792 int i;
3793
3794 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3795
3796 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3797 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3798 I915_WRITE(GTFIFODBG, gtfifodbg);
3799 }
3800
c9cddffc
JB		 3801 valleyview_setup_pctx(dev);
3802
0a073b84
JB		 3803 gen6_gt_force_wake_get(dev_priv);
3804
3805 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3806 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3807 I915_WRITE(GEN6_RP_UP_EI, 66000);
3808 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3809
3810 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3811
3812 I915_WRITE(GEN6_RP_CONTROL,
3813 GEN6_RP_MEDIA_TURBO |
3814 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3815 GEN6_RP_MEDIA_IS_GFX |
3816 GEN6_RP_ENABLE |
3817 GEN6_RP_UP_BUSY_AVG |
3818 GEN6_RP_DOWN_IDLE_CONT);
3819
3820 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3821 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3822 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3823
3824 for_each_ring(ring, dev_priv, i)
3825 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3826
3827 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3828
3829 /* allows RC6 residency counter to work */
3830 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
a2b23fe0
JB		 3831 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
3832 rc6_mode = GEN7_RC_CTL_TO_MODE;
3833 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 3834
64936258 3835 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3836 switch ((val >> 6) & 3) {
3837 case 0:
3838 case 1:
3839 dev_priv->mem_freq = 800;
3840 break;
3841 case 2:
3842 dev_priv->mem_freq = 1066;
3843 break;
3844 case 3:
3845 dev_priv->mem_freq = 1333;
3846 break;
3847 }
0a073b84
JB		 3848 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3849
3850 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3851 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3852
0a073b84 3853 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3854 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3855 vlv_gpu_freq(dev_priv->mem_freq,
3856 dev_priv->rps.cur_delay),
3857 dev_priv->rps.cur_delay);
0a073b84
JB		 3858
3859 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3860 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3861 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3862 vlv_gpu_freq(dev_priv->mem_freq,
3863 dev_priv->rps.max_delay),
3864 dev_priv->rps.max_delay);
0a073b84 3865
73008b98
VS		 3866 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3867 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3868 vlv_gpu_freq(dev_priv->mem_freq,
3869 dev_priv->rps.rpe_delay),
3870 dev_priv->rps.rpe_delay);
0a073b84 3871
73008b98
VS		 3872 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3873 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3874 vlv_gpu_freq(dev_priv->mem_freq,
3875 dev_priv->rps.min_delay),
3876 dev_priv->rps.min_delay);
0a073b84 3877
73008b98
VS		 3878 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3879 vlv_gpu_freq(dev_priv->mem_freq,
3880 dev_priv->rps.rpe_delay),
3881 dev_priv->rps.rpe_delay);
0a073b84 3882
52ceb908
JB		 3883 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3884
73008b98 3885 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3886
44fc7d5c 3887 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3888
3889 gen6_gt_force_wake_put(dev_priv);
3890}
3891
930ebb46 3892void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3893{
3894 struct drm_i915_private *dev_priv = dev->dev_private;
3895
3e373948
DV		 3896 if (dev_priv->ips.renderctx) {
3897 i915_gem_object_unpin(dev_priv->ips.renderctx);
3898 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3899 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3900 }
3901
3e373948
DV		 3902 if (dev_priv->ips.pwrctx) {
3903 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3904 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3905 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3906 }
3907}
3908
930ebb46 3909static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3910{
3911 struct drm_i915_private *dev_priv = dev->dev_private;
3912
3913 if (I915_READ(PWRCTXA)) {
3914 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3915 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3916 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3917 50);
3918
3919 I915_WRITE(PWRCTXA, 0);
3920 POSTING_READ(PWRCTXA);
3921
3922 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3923 POSTING_READ(RSTDBYCTL);
3924 }
2b4e57bd
ED		 3925}
3926
3927static int ironlake_setup_rc6(struct drm_device *dev)
3928{
3929 struct drm_i915_private *dev_priv = dev->dev_private;
3930
3e373948
DV		 3931 if (dev_priv->ips.renderctx == NULL)
3932 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3933 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3934 return -ENOMEM;
3935
3e373948
DV		 3936 if (dev_priv->ips.pwrctx == NULL)
3937 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3938 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3939 ironlake_teardown_rc6(dev);
3940 return -ENOMEM;
3941 }
3942
3943 return 0;
3944}
3945
930ebb46 3946static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3947{
3948 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3949 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3950 bool was_interruptible;
2b4e57bd
ED		 3951 int ret;
3952
3953 /* rc6 disabled by default due to repeated reports of hanging during
3954 * boot and resume.
3955 */
3956 if (!intel_enable_rc6(dev))
3957 return;
3958
79f5b2c7
DV		 3959 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3960
2b4e57bd 3961 ret = ironlake_setup_rc6(dev);
79f5b2c7 3962 if (ret)
2b4e57bd 3963 return;
2b4e57bd 3964
3e960501
CW		 3965 was_interruptible = dev_priv->mm.interruptible;
3966 dev_priv->mm.interruptible = false;
3967
2b4e57bd
ED		 3968 /*
3969 * GPU can automatically power down the render unit if given a page
3970 * to save state.
3971 */
6d90c952 3972 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3973 if (ret) {
3974 ironlake_teardown_rc6(dev);
3e960501 3975 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3976 return;
3977 }
3978
6d90c952
DV		 3979 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3980 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3981 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3982 MI_MM_SPACE_GTT |
3983 MI_SAVE_EXT_STATE_EN |
3984 MI_RESTORE_EXT_STATE_EN |
3985 MI_RESTORE_INHIBIT);
3986 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3987 intel_ring_emit(ring, MI_NOOP);
3988 intel_ring_emit(ring, MI_FLUSH);
3989 intel_ring_advance(ring);
2b4e57bd
ED		 3990
3991 /*
3992 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3993 * does an implicit flush, combined with MI_FLUSH above, it should be
3994 * safe to assume that renderctx is valid
3995 */
3e960501
CW		 3996 ret = intel_ring_idle(ring);
3997 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3998 if (ret) {
def27a58 3999 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 4000 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 4001 return;
4002 }
4003
f343c5f6 4004 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 4005 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 4006}
4007
dde18883
ED		 4008static unsigned long intel_pxfreq(u32 vidfreq)
4009{
4010 unsigned long freq;
4011 int div = (vidfreq & 0x3f0000) >> 16;
4012 int post = (vidfreq & 0x3000) >> 12;
4013 int pre = (vidfreq & 0x7);
4014
4015 if (!pre)
4016 return 0;
4017
4018 freq = ((div * 133333) / ((1<<post) * pre));
4019
4020 return freq;
4021}
4022
eb48eb00
DV		 4023static const struct cparams {
4024 u16 i;
4025 u16 t;
4026 u16 m;
4027 u16 c;
4028} cparams[] = {
4029 { 1, 1333, 301, 28664 },
4030 { 1, 1066, 294, 24460 },
4031 { 1, 800, 294, 25192 },
4032 { 0, 1333, 276, 27605 },
4033 { 0, 1066, 276, 27605 },
4034 { 0, 800, 231, 23784 },
4035};
4036
f531dcb2 4037static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4038{
4039 u64 total_count, diff, ret;
4040 u32 count1, count2, count3, m = 0, c = 0;
4041 unsigned long now = jiffies_to_msecs(jiffies), diff1;
4042 int i;
4043
02d71956
DV		 4044 assert_spin_locked(&mchdev_lock);
4045
20e4d407 4046 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 4047
4048 /* Prevent division-by-zero if we are asking too fast.
4049 * Also, we don't get interesting results if we are polling
4050 * faster than once in 10ms, so just return the saved value
4051 * in such cases.
4052 */
4053 if (diff1 <= 10)
20e4d407 4054 return dev_priv->ips.chipset_power;
eb48eb00
DV		 4055
4056 count1 = I915_READ(DMIEC);
4057 count2 = I915_READ(DDREC);
4058 count3 = I915_READ(CSIEC);
4059
4060 total_count = count1 + count2 + count3;
4061
4062 /* FIXME: handle per-counter overflow */
20e4d407
DV		 4063 if (total_count < dev_priv->ips.last_count1) {
4064 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 4065 diff += total_count;
4066 } else {
20e4d407 4067 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 4068 }
4069
4070 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 4071 if (cparams[i].i == dev_priv->ips.c_m &&
4072 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 4073 m = cparams[i].m;
4074 c = cparams[i].c;
4075 break;
4076 }
4077 }
4078
4079 diff = div_u64(diff, diff1);
4080 ret = ((m * diff) + c);
4081 ret = div_u64(ret, 10);
4082
20e4d407
DV		 4083 dev_priv->ips.last_count1 = total_count;
4084 dev_priv->ips.last_time1 = now;
eb48eb00 4085
20e4d407 4086 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 4087
4088 return ret;
4089}
4090
f531dcb2
CW		 4091unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
4092{
4093 unsigned long val;
4094
4095 if (dev_priv->info->gen != 5)
4096 return 0;
4097
4098 spin_lock_irq(&mchdev_lock);
4099
4100 val = __i915_chipset_val(dev_priv);
4101
4102 spin_unlock_irq(&mchdev_lock);
4103
4104 return val;
4105}
4106
eb48eb00
DV		 4107unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
4108{
4109 unsigned long m, x, b;
4110 u32 tsfs;
4111
4112 tsfs = I915_READ(TSFS);
4113
4114 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
4115 x = I915_READ8(TR1);
4116
4117 b = tsfs & TSFS_INTR_MASK;
4118
4119 return ((m * x) / 127) - b;
4120}
4121
4122static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
4123{
4124 static const struct v_table {
4125 u16 vd; /* in .1 mil */
4126 u16 vm; /* in .1 mil */
4127 } v_table[] = {
4128 { 0, 0, },
4129 { 375, 0, },
4130 { 500, 0, },
4131 { 625, 0, },
4132 { 750, 0, },
4133 { 875, 0, },
4134 { 1000, 0, },
4135 { 1125, 0, },
4136 { 4125, 3000, },
4137 { 4125, 3000, },
4138 { 4125, 3000, },
4139 { 4125, 3000, },
4140 { 4125, 3000, },
4141 { 4125, 3000, },
4142 { 4125, 3000, },
4143 { 4125, 3000, },
4144 { 4125, 3000, },
4145 { 4125, 3000, },
4146 { 4125, 3000, },
4147 { 4125, 3000, },
4148 { 4125, 3000, },
4149 { 4125, 3000, },
4150 { 4125, 3000, },
4151 { 4125, 3000, },
4152 { 4125, 3000, },
4153 { 4125, 3000, },
4154 { 4125, 3000, },
4155 { 4125, 3000, },
4156 { 4125, 3000, },
4157 { 4125, 3000, },
4158 { 4125, 3000, },
4159 { 4125, 3000, },
4160 { 4250, 3125, },
4161 { 4375, 3250, },
4162 { 4500, 3375, },
4163 { 4625, 3500, },
4164 { 4750, 3625, },
4165 { 4875, 3750, },
4166 { 5000, 3875, },
4167 { 5125, 4000, },
4168 { 5250, 4125, },
4169 { 5375, 4250, },
4170 { 5500, 4375, },
4171 { 5625, 4500, },
4172 { 5750, 4625, },
4173 { 5875, 4750, },
4174 { 6000, 4875, },
4175 { 6125, 5000, },
4176 { 6250, 5125, },
4177 { 6375, 5250, },
4178 { 6500, 5375, },
4179 { 6625, 5500, },
4180 { 6750, 5625, },
4181 { 6875, 5750, },
4182 { 7000, 5875, },
4183 { 7125, 6000, },
4184 { 7250, 6125, },
4185 { 7375, 6250, },
4186 { 7500, 6375, },
4187 { 7625, 6500, },
4188 { 7750, 6625, },
4189 { 7875, 6750, },
4190 { 8000, 6875, },
4191 { 8125, 7000, },
4192 { 8250, 7125, },
4193 { 8375, 7250, },
4194 { 8500, 7375, },
4195 { 8625, 7500, },
4196 { 8750, 7625, },
4197 { 8875, 7750, },
4198 { 9000, 7875, },
4199 { 9125, 8000, },
4200 { 9250, 8125, },
4201 { 9375, 8250, },
4202 { 9500, 8375, },
4203 { 9625, 8500, },
4204 { 9750, 8625, },
4205 { 9875, 8750, },
4206 { 10000, 8875, },
4207 { 10125, 9000, },
4208 { 10250, 9125, },
4209 { 10375, 9250, },
4210 { 10500, 9375, },
4211 { 10625, 9500, },
4212 { 10750, 9625, },
4213 { 10875, 9750, },
4214 { 11000, 9875, },
4215 { 11125, 10000, },
4216 { 11250, 10125, },
4217 { 11375, 10250, },
4218 { 11500, 10375, },
4219 { 11625, 10500, },
4220 { 11750, 10625, },
4221 { 11875, 10750, },
4222 { 12000, 10875, },
4223 { 12125, 11000, },
4224 { 12250, 11125, },
4225 { 12375, 11250, },
4226 { 12500, 11375, },
4227 { 12625, 11500, },
4228 { 12750, 11625, },
4229 { 12875, 11750, },
4230 { 13000, 11875, },
4231 { 13125, 12000, },
4232 { 13250, 12125, },
4233 { 13375, 12250, },
4234 { 13500, 12375, },
4235 { 13625, 12500, },
4236 { 13750, 12625, },
4237 { 13875, 12750, },
4238 { 14000, 12875, },
4239 { 14125, 13000, },
4240 { 14250, 13125, },
4241 { 14375, 13250, },
4242 { 14500, 13375, },
4243 { 14625, 13500, },
4244 { 14750, 13625, },
4245 { 14875, 13750, },
4246 { 15000, 13875, },
4247 { 15125, 14000, },
4248 { 15250, 14125, },
4249 { 15375, 14250, },
4250 { 15500, 14375, },
4251 { 15625, 14500, },
4252 { 15750, 14625, },
4253 { 15875, 14750, },
4254 { 16000, 14875, },
4255 { 16125, 15000, },
4256 };
4257 if (dev_priv->info->is_mobile)
4258 return v_table[pxvid].vm;
4259 else
4260 return v_table[pxvid].vd;
4261}
4262
02d71956 4263static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4264{
4265 struct timespec now, diff1;
4266 u64 diff;
4267 unsigned long diffms;
4268 u32 count;
4269
02d71956 4270 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4271
4272 getrawmonotonic(&now);
20e4d407 4273 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4274
4275 /* Don't divide by 0 */
4276 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4277 if (!diffms)
4278 return;
4279
4280 count = I915_READ(GFXEC);
4281
20e4d407
DV		 4282 if (count < dev_priv->ips.last_count2) {
4283 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4284 diff += count;
4285 } else {
20e4d407 4286 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4287 }
4288
20e4d407
DV		 4289 dev_priv->ips.last_count2 = count;
4290 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4291
4292 /* More magic constants... */
4293 diff = diff * 1181;
4294 diff = div_u64(diff, diffms * 10);
20e4d407 4295 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4296}
4297
02d71956
DV		 4298void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4299{
4300 if (dev_priv->info->gen != 5)
4301 return;
4302
9270388e 4303 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4304
4305 __i915_update_gfx_val(dev_priv);
4306
9270388e 4307 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4308}
4309
f531dcb2 4310static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4311{
4312 unsigned long t, corr, state1, corr2, state2;
4313 u32 pxvid, ext_v;
4314
02d71956
DV		 4315 assert_spin_locked(&mchdev_lock);
4316
c6a828d3 4317 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4318 pxvid = (pxvid >> 24) & 0x7f;
4319 ext_v = pvid_to_extvid(dev_priv, pxvid);
4320
4321 state1 = ext_v;
4322
4323 t = i915_mch_val(dev_priv);
4324
4325 /* Revel in the empirically derived constants */
4326
4327 /* Correction factor in 1/100000 units */
4328 if (t > 80)
4329 corr = ((t * 2349) + 135940);
4330 else if (t >= 50)
4331 corr = ((t * 964) + 29317);
4332 else /* < 50 */
4333 corr = ((t * 301) + 1004);
4334
4335 corr = corr * ((150142 * state1) / 10000 - 78642);
4336 corr /= 100000;
20e4d407 4337 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4338
4339 state2 = (corr2 * state1) / 10000;
4340 state2 /= 100; /* convert to mW */
4341
02d71956 4342 __i915_update_gfx_val(dev_priv);
eb48eb00 4343
20e4d407 4344 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4345}
4346
f531dcb2
CW		 4347unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4348{
4349 unsigned long val;
4350
4351 if (dev_priv->info->gen != 5)
4352 return 0;
4353
4354 spin_lock_irq(&mchdev_lock);
4355
4356 val = __i915_gfx_val(dev_priv);
4357
4358 spin_unlock_irq(&mchdev_lock);
4359
4360 return val;
4361}
4362
eb48eb00
DV		 4363/**
4364 * i915_read_mch_val - return value for IPS use
4365 *
4366 * Calculate and return a value for the IPS driver to use when deciding whether
4367 * we have thermal and power headroom to increase CPU or GPU power budget.
4368 */
4369unsigned long i915_read_mch_val(void)
4370{
4371 struct drm_i915_private *dev_priv;
4372 unsigned long chipset_val, graphics_val, ret = 0;
4373
9270388e 4374 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4375 if (!i915_mch_dev)
4376 goto out_unlock;
4377 dev_priv = i915_mch_dev;
4378
f531dcb2
CW		 4379 chipset_val = __i915_chipset_val(dev_priv);
4380 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4381
4382 ret = chipset_val + graphics_val;
4383
4384out_unlock:
9270388e 4385 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4386
4387 return ret;
4388}
4389EXPORT_SYMBOL_GPL(i915_read_mch_val);
4390
4391/**
4392 * i915_gpu_raise - raise GPU frequency limit
4393 *
4394 * Raise the limit; IPS indicates we have thermal headroom.
4395 */
4396bool i915_gpu_raise(void)
4397{
4398 struct drm_i915_private *dev_priv;
4399 bool ret = true;
4400
9270388e 4401 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4402 if (!i915_mch_dev) {
4403 ret = false;
4404 goto out_unlock;
4405 }
4406 dev_priv = i915_mch_dev;
4407
20e4d407
DV		 4408 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4409 dev_priv->ips.max_delay--;
eb48eb00
DV		 4410
4411out_unlock:
9270388e 4412 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4413
4414 return ret;
4415}
4416EXPORT_SYMBOL_GPL(i915_gpu_raise);
4417
4418/**
4419 * i915_gpu_lower - lower GPU frequency limit
4420 *
4421 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4422 * frequency maximum.
4423 */
4424bool i915_gpu_lower(void)
4425{
4426 struct drm_i915_private *dev_priv;
4427 bool ret = true;
4428
9270388e 4429 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4430 if (!i915_mch_dev) {
4431 ret = false;
4432 goto out_unlock;
4433 }
4434 dev_priv = i915_mch_dev;
4435
20e4d407
DV		 4436 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4437 dev_priv->ips.max_delay++;
eb48eb00
DV		 4438
4439out_unlock:
9270388e 4440 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4441
4442 return ret;
4443}
4444EXPORT_SYMBOL_GPL(i915_gpu_lower);
4445
4446/**
4447 * i915_gpu_busy - indicate GPU business to IPS
4448 *
4449 * Tell the IPS driver whether or not the GPU is busy.
4450 */
4451bool i915_gpu_busy(void)
4452{
4453 struct drm_i915_private *dev_priv;
f047e395 4454 struct intel_ring_buffer *ring;
eb48eb00 4455 bool ret = false;
f047e395 4456 int i;
eb48eb00 4457
9270388e 4458 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4459 if (!i915_mch_dev)
4460 goto out_unlock;
4461 dev_priv = i915_mch_dev;
4462
f047e395
CW		 4463 for_each_ring(ring, dev_priv, i)
4464 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4465
4466out_unlock:
9270388e 4467 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4468
4469 return ret;
4470}
4471EXPORT_SYMBOL_GPL(i915_gpu_busy);
4472
4473/**
4474 * i915_gpu_turbo_disable - disable graphics turbo
4475 *
4476 * Disable graphics turbo by resetting the max frequency and setting the
4477 * current frequency to the default.
4478 */
4479bool i915_gpu_turbo_disable(void)
4480{
4481 struct drm_i915_private *dev_priv;
4482 bool ret = true;
4483
9270388e 4484 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4485 if (!i915_mch_dev) {
4486 ret = false;
4487 goto out_unlock;
4488 }
4489 dev_priv = i915_mch_dev;
4490
20e4d407 4491 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4492
20e4d407 4493 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4494 ret = false;
4495
4496out_unlock:
9270388e 4497 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4498
4499 return ret;
4500}
4501EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4502
4503/**
4504 * Tells the intel_ips driver that the i915 driver is now loaded, if
4505 * IPS got loaded first.
4506 *
4507 * This awkward dance is so that neither module has to depend on the
4508 * other in order for IPS to do the appropriate communication of
4509 * GPU turbo limits to i915.
4510 */
4511static void
4512ips_ping_for_i915_load(void)
4513{
4514 void (*link)(void);
4515
4516 link = symbol_get(ips_link_to_i915_driver);
4517 if (link) {
4518 link();
4519 symbol_put(ips_link_to_i915_driver);
4520 }
4521}
4522
4523void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4524{
02d71956
DV		 4525 /* We only register the i915 ips part with intel-ips once everything is
4526 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4527 spin_lock_irq(&mchdev_lock);
eb48eb00 4528 i915_mch_dev = dev_priv;
9270388e 4529 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4530
4531 ips_ping_for_i915_load();
4532}
4533
4534void intel_gpu_ips_teardown(void)
4535{
9270388e 4536 spin_lock_irq(&mchdev_lock);
eb48eb00 4537 i915_mch_dev = NULL;
9270388e 4538 spin_unlock_irq(&mchdev_lock);
eb48eb00 4539}
8090c6b9 4540static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4541{
4542 struct drm_i915_private *dev_priv = dev->dev_private;
4543 u32 lcfuse;
4544 u8 pxw[16];
4545 int i;
4546
4547 /* Disable to program */
4548 I915_WRITE(ECR, 0);
4549 POSTING_READ(ECR);
4550
4551 /* Program energy weights for various events */
4552 I915_WRITE(SDEW, 0x15040d00);
4553 I915_WRITE(CSIEW0, 0x007f0000);
4554 I915_WRITE(CSIEW1, 0x1e220004);
4555 I915_WRITE(CSIEW2, 0x04000004);
4556
4557 for (i = 0; i < 5; i++)
4558 I915_WRITE(PEW + (i * 4), 0);
4559 for (i = 0; i < 3; i++)
4560 I915_WRITE(DEW + (i * 4), 0);
4561
4562 /* Program P-state weights to account for frequency power adjustment */
4563 for (i = 0; i < 16; i++) {
4564 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4565 unsigned long freq = intel_pxfreq(pxvidfreq);
4566 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4567 PXVFREQ_PX_SHIFT;
4568 unsigned long val;
4569
4570 val = vid * vid;
4571 val *= (freq / 1000);
4572 val *= 255;
4573 val /= (127*127*900);
4574 if (val > 0xff)
4575 DRM_ERROR("bad pxval: %ld\n", val);
4576 pxw[i] = val;
4577 }
4578 /* Render standby states get 0 weight */
4579 pxw[14] = 0;
4580 pxw[15] = 0;
4581
4582 for (i = 0; i < 4; i++) {
4583 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4584 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4585 I915_WRITE(PXW + (i * 4), val);
4586 }
4587
4588 /* Adjust magic regs to magic values (more experimental results) */
4589 I915_WRITE(OGW0, 0);
4590 I915_WRITE(OGW1, 0);
4591 I915_WRITE(EG0, 0x00007f00);
4592 I915_WRITE(EG1, 0x0000000e);
4593 I915_WRITE(EG2, 0x000e0000);
4594 I915_WRITE(EG3, 0x68000300);
4595 I915_WRITE(EG4, 0x42000000);
4596 I915_WRITE(EG5, 0x00140031);
4597 I915_WRITE(EG6, 0);
4598 I915_WRITE(EG7, 0);
4599
4600 for (i = 0; i < 8; i++)
4601 I915_WRITE(PXWL + (i * 4), 0);
4602
4603 /* Enable PMON + select events */
4604 I915_WRITE(ECR, 0x80000019);
4605
4606 lcfuse = I915_READ(LCFUSE02);
4607
20e4d407 4608 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4609}
4610
8090c6b9
DV		 4611void intel_disable_gt_powersave(struct drm_device *dev)
4612{
1a01ab3b
JB		 4613 struct drm_i915_private *dev_priv = dev->dev_private;
4614
fd0c0642
DV		 4615 /* Interrupts should be disabled already to avoid re-arming. */
4616 WARN_ON(dev->irq_enabled);
4617
930ebb46 4618 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4619 ironlake_disable_drps(dev);
930ebb46 4620 ironlake_disable_rc6(dev);
0a073b84 4621 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4622 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4623 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4624 if (IS_VALLEYVIEW(dev))
4625 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4626 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4627 if (IS_VALLEYVIEW(dev))
4628 valleyview_disable_rps(dev);
4629 else
4630 gen6_disable_rps(dev);
4fc688ce 4631 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4632 }
8090c6b9
DV		 4633}
4634
1a01ab3b
JB		 4635static void intel_gen6_powersave_work(struct work_struct *work)
4636{
4637 struct drm_i915_private *dev_priv =
4638 container_of(work, struct drm_i915_private,
4639 rps.delayed_resume_work.work);
4640 struct drm_device *dev = dev_priv->dev;
4641
4fc688ce 4642 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4643
4644 if (IS_VALLEYVIEW(dev)) {
4645 valleyview_enable_rps(dev);
4646 } else {
4647 gen6_enable_rps(dev);
4648 gen6_update_ring_freq(dev);
4649 }
4fc688ce 4650 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4651}
4652
8090c6b9
DV		 4653void intel_enable_gt_powersave(struct drm_device *dev)
4654{
1a01ab3b
JB		 4655 struct drm_i915_private *dev_priv = dev->dev_private;
4656
8090c6b9
DV		 4657 if (IS_IRONLAKE_M(dev)) {
4658 ironlake_enable_drps(dev);
4659 ironlake_enable_rc6(dev);
4660 intel_init_emon(dev);
0a073b84 4661 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4662 /*
4663 * PCU communication is slow and this doesn't need to be
4664 * done at any specific time, so do this out of our fast path
4665 * to make resume and init faster.
4666 */
4667 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4668 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4669 }
4670}
4671
3107bd48
DV		 4672static void ibx_init_clock_gating(struct drm_device *dev)
4673{
4674 struct drm_i915_private *dev_priv = dev->dev_private;
4675
4676 /*
4677 * On Ibex Peak and Cougar Point, we need to disable clock
4678 * gating for the panel power sequencer or it will fail to
4679 * start up when no ports are active.
4680 */
4681 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4682}
4683
0e088b8f
VS		 4684static void g4x_disable_trickle_feed(struct drm_device *dev)
4685{
4686 struct drm_i915_private *dev_priv = dev->dev_private;
4687 int pipe;
4688
4689 for_each_pipe(pipe) {
4690 I915_WRITE(DSPCNTR(pipe),
4691 I915_READ(DSPCNTR(pipe)) |
4692 DISPPLANE_TRICKLE_FEED_DISABLE);
4693 intel_flush_display_plane(dev_priv, pipe);
4694 }
4695}
4696
1fa61106 4697static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4698{
4699 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4700 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4701
f1e8fa56
DL		 4702 /*
4703 * Required for FBC
4704 * WaFbcDisableDpfcClockGating:ilk
4705 */
4d47e4f5
DL		 4706 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4707 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4708 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4709
4710 I915_WRITE(PCH_3DCGDIS0,
4711 MARIUNIT_CLOCK_GATE_DISABLE |
4712 SVSMUNIT_CLOCK_GATE_DISABLE);
4713 I915_WRITE(PCH_3DCGDIS1,
4714 VFMUNIT_CLOCK_GATE_DISABLE);
4715
6f1d69b0
ED		 4716 /*
4717 * According to the spec the following bits should be set in
4718 * order to enable memory self-refresh
4719 * The bit 22/21 of 0x42004
4720 * The bit 5 of 0x42020
4721 * The bit 15 of 0x45000
4722 */
4723 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4724 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4725 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4726 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4727 I915_WRITE(DISP_ARB_CTL,
4728 (I915_READ(DISP_ARB_CTL) |
4729 DISP_FBC_WM_DIS));
4730 I915_WRITE(WM3_LP_ILK, 0);
4731 I915_WRITE(WM2_LP_ILK, 0);
4732 I915_WRITE(WM1_LP_ILK, 0);
4733
4734 /*
4735 * Based on the document from hardware guys the following bits
4736 * should be set unconditionally in order to enable FBC.
4737 * The bit 22 of 0x42000
4738 * The bit 22 of 0x42004
4739 * The bit 7,8,9 of 0x42020.
4740 */
4741 if (IS_IRONLAKE_M(dev)) {
4bb35334 4742 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4743 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4744 I915_READ(ILK_DISPLAY_CHICKEN1) |
4745 ILK_FBCQ_DIS);
4746 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4747 I915_READ(ILK_DISPLAY_CHICKEN2) |
4748 ILK_DPARB_GATE);
6f1d69b0
ED		 4749 }
4750
4d47e4f5
DL		 4751 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4752
6f1d69b0
ED		 4753 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4754 I915_READ(ILK_DISPLAY_CHICKEN2) |
4755 ILK_ELPIN_409_SELECT);
4756 I915_WRITE(_3D_CHICKEN2,
4757 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4758 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4759
ecdb4eb7 4760 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4761 I915_WRITE(CACHE_MODE_0,
4762 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4763
0e088b8f 4764 g4x_disable_trickle_feed(dev);
bdad2b2f 4765
3107bd48
DV		 4766 ibx_init_clock_gating(dev);
4767}
4768
4769static void cpt_init_clock_gating(struct drm_device *dev)
4770{
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772 int pipe;
3f704fa2 4773 uint32_t val;
3107bd48
DV		 4774
4775 /*
4776 * On Ibex Peak and Cougar Point, we need to disable clock
4777 * gating for the panel power sequencer or it will fail to
4778 * start up when no ports are active.
4779 */
4780 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4781 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4782 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4783 /* The below fixes the weird display corruption, a few pixels shifted
4784 * downward, on (only) LVDS of some HP laptops with IVY.
4785 */
3f704fa2 4786 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4787 val = I915_READ(TRANS_CHICKEN2(pipe));
4788 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4789 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4790 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4791 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4792 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4793 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4794 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4795 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4796 }
3107bd48
DV		 4797 /* WADP0ClockGatingDisable */
4798 for_each_pipe(pipe) {
4799 I915_WRITE(TRANS_CHICKEN1(pipe),
4800 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4801 }
6f1d69b0
ED		 4802}
4803
1d7aaa0c
DV		 4804static void gen6_check_mch_setup(struct drm_device *dev)
4805{
4806 struct drm_i915_private *dev_priv = dev->dev_private;
4807 uint32_t tmp;
4808
4809 tmp = I915_READ(MCH_SSKPD);
4810 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4811 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4812 DRM_INFO("This can cause pipe underruns and display issues.\n");
4813 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4814 }
4815}
4816
1fa61106 4817static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4818{
4819 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4820 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4821
231e54f6 4822 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4823
4824 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4825 I915_READ(ILK_DISPLAY_CHICKEN2) |
4826 ILK_ELPIN_409_SELECT);
4827
ecdb4eb7 4828 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4829 I915_WRITE(_3D_CHICKEN,
4830 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4831
ecdb4eb7 4832 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4833 if (IS_SNB_GT1(dev))
4834 I915_WRITE(GEN6_GT_MODE,
4835 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4836
6f1d69b0
ED		 4837 I915_WRITE(WM3_LP_ILK, 0);
4838 I915_WRITE(WM2_LP_ILK, 0);
4839 I915_WRITE(WM1_LP_ILK, 0);
4840
6f1d69b0 4841 I915_WRITE(CACHE_MODE_0,
50743298 4842 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4843
4844 I915_WRITE(GEN6_UCGCTL1,
4845 I915_READ(GEN6_UCGCTL1) |
4846 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4847 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4848
4849 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4850 * gating disable must be set. Failure to set it results in
4851 * flickering pixels due to Z write ordering failures after
4852 * some amount of runtime in the Mesa "fire" demo, and Unigine
4853 * Sanctuary and Tropics, and apparently anything else with
4854 * alpha test or pixel discard.
4855 *
4856 * According to the spec, bit 11 (RCCUNIT) must also be set,
4857 * but we didn't debug actual testcases to find it out.
0f846f81 4858 *
ecdb4eb7
DL		 4859 * Also apply WaDisableVDSUnitClockGating:snb and
4860 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4861 */
4862 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4863 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4864 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4865 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4866
4867 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4868 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4869 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4870
4871 /*
4872 * According to the spec the following bits should be
4873 * set in order to enable memory self-refresh and fbc:
4874 * The bit21 and bit22 of 0x42000
4875 * The bit21 and bit22 of 0x42004
4876 * The bit5 and bit7 of 0x42020
4877 * The bit14 of 0x70180
4878 * The bit14 of 0x71180
4bb35334
DL		 4879 *
4880 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4881 */
4882 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4883 I915_READ(ILK_DISPLAY_CHICKEN1) |
4884 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4885 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4886 I915_READ(ILK_DISPLAY_CHICKEN2) |
4887 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4888 I915_WRITE(ILK_DSPCLK_GATE_D,
4889 I915_READ(ILK_DSPCLK_GATE_D) |
4890 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4891 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4892
0e088b8f 4893 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4894
4895 /* The default value should be 0x200 according to docs, but the two
4896 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4897 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4898 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4899
4900 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4901
4902 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4903}
4904
4905static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4906{
4907 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4908
4909 reg &= ~GEN7_FF_SCHED_MASK;
4910 reg |= GEN7_FF_TS_SCHED_HW;
4911 reg |= GEN7_FF_VS_SCHED_HW;
4912 reg |= GEN7_FF_DS_SCHED_HW;
4913
41c0b3a8
BW		 4914 if (IS_HASWELL(dev_priv->dev))
4915 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4916
6f1d69b0
ED		 4917 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4918}
4919
17a303ec
PZ		 4920static void lpt_init_clock_gating(struct drm_device *dev)
4921{
4922 struct drm_i915_private *dev_priv = dev->dev_private;
4923
4924 /*
4925 * TODO: this bit should only be enabled when really needed, then
4926 * disabled when not needed anymore in order to save power.
4927 */
4928 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4929 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4930 I915_READ(SOUTH_DSPCLK_GATE_D) |
4931 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4932
4933 /* WADPOClockGatingDisable:hsw */
4934 I915_WRITE(_TRANSA_CHICKEN1,
4935 I915_READ(_TRANSA_CHICKEN1) |
4936 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4937}
4938
7d708ee4
ID		 4939static void lpt_suspend_hw(struct drm_device *dev)
4940{
4941 struct drm_i915_private *dev_priv = dev->dev_private;
4942
4943 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4944 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4945
4946 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4947 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4948 }
4949}
4950
cad2a2d7
ED		 4951static void haswell_init_clock_gating(struct drm_device *dev)
4952{
4953 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4954
4955 I915_WRITE(WM3_LP_ILK, 0);
4956 I915_WRITE(WM2_LP_ILK, 0);
4957 I915_WRITE(WM1_LP_ILK, 0);
4958
4959 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4960 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4961 */
4962 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4963
ecdb4eb7 4964 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4965 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4966 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4967
ecdb4eb7 4968 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4969 I915_WRITE(GEN7_L3CNTLREG1,
4970 GEN7_WA_FOR_GEN7_L3_CONTROL);
4971 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4972 GEN7_WA_L3_CHICKEN_MODE);
4973
ecdb4eb7 4974 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4975 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4976 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4977 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4978
ecdb4eb7 4979 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4980 gen7_setup_fixed_func_scheduler(dev_priv);
4981
ecdb4eb7 4982 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4983 I915_WRITE(CACHE_MODE_1,
4984 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4985
ecdb4eb7 4986 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4987 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4988
90a88643
PZ		 4989 /* WaRsPkgCStateDisplayPMReq:hsw */
4990 I915_WRITE(CHICKEN_PAR1_1,
4991 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4992
17a303ec 4993 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4994}
4995
1fa61106 4996static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4997{
4998 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4999 uint32_t snpcr;
6f1d69b0 5000
6f1d69b0
ED		 5001 I915_WRITE(WM3_LP_ILK, 0);
5002 I915_WRITE(WM2_LP_ILK, 0);
5003 I915_WRITE(WM1_LP_ILK, 0);
5004
231e54f6 5005 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5006
ecdb4eb7 5007 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 5008 I915_WRITE(_3D_CHICKEN3,
5009 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5010
ecdb4eb7 5011 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 5012 I915_WRITE(IVB_CHICKEN3,
5013 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5014 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5015
ecdb4eb7 5016 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 5017 if (IS_IVB_GT1(dev))
5018 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
5019 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5020 else
5021 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
5022 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
5023
ecdb4eb7 5024 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 5025 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5026 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5027
ecdb4eb7 5028 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 5029 I915_WRITE(GEN7_L3CNTLREG1,
5030 GEN7_WA_FOR_GEN7_L3_CONTROL);
5031 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 5032 GEN7_WA_L3_CHICKEN_MODE);
5033 if (IS_IVB_GT1(dev))
5034 I915_WRITE(GEN7_ROW_CHICKEN2,
5035 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5036 else
5037 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
5038 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5039
6f1d69b0 5040
ecdb4eb7 5041 /* WaForceL3Serialization:ivb */
61939d97
JB		 5042 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5043 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5044
0f846f81
JB		 5045 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5046 * gating disable must be set. Failure to set it results in
5047 * flickering pixels due to Z write ordering failures after
5048 * some amount of runtime in the Mesa "fire" demo, and Unigine
5049 * Sanctuary and Tropics, and apparently anything else with
5050 * alpha test or pixel discard.
5051 *
5052 * According to the spec, bit 11 (RCCUNIT) must also be set,
5053 * but we didn't debug actual testcases to find it out.
5054 *
5055 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5056 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 5057 */
5058 I915_WRITE(GEN6_UCGCTL2,
5059 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5060 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5061
ecdb4eb7 5062 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 5063 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5064 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5065 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5066
0e088b8f 5067 g4x_disable_trickle_feed(dev);
6f1d69b0 5068
ecdb4eb7 5069 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 5070 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 5071
ecdb4eb7 5072 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 5073 I915_WRITE(CACHE_MODE_1,
5074 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 5075
5076 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
5077 snpcr &= ~GEN6_MBC_SNPCR_MASK;
5078 snpcr |= GEN6_MBC_SNPCR_MED;
5079 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 5080
ab5c608b
BW		 5081 if (!HAS_PCH_NOP(dev))
5082 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 5083
5084 gen6_check_mch_setup(dev);
6f1d69b0
ED		 5085}
5086
1fa61106 5087static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5088{
5089 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 5090
d7fe0cc0 5091 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 5092
ecdb4eb7 5093 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 5094 I915_WRITE(_3D_CHICKEN3,
5095 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
5096
ecdb4eb7 5097 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 5098 I915_WRITE(IVB_CHICKEN3,
5099 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
5100 CHICKEN3_DGMG_DONE_FIX_DISABLE);
5101
ecdb4eb7 5102 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 5103 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 5104 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
5105 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 5106
ecdb4eb7 5107 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 5108 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
5109 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
5110
ecdb4eb7 5111 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 5112 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 5113 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
5114
ecdb4eb7 5115 /* WaForceL3Serialization:vlv */
61939d97
JB		 5116 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
5117 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
5118
ecdb4eb7 5119 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 5120 I915_WRITE(GEN7_ROW_CHICKEN2,
5121 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
5122
ecdb4eb7 5123 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 5124 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
5125 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
5126 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
5127
0f846f81
JB		 5128 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
5129 * gating disable must be set. Failure to set it results in
5130 * flickering pixels due to Z write ordering failures after
5131 * some amount of runtime in the Mesa "fire" demo, and Unigine
5132 * Sanctuary and Tropics, and apparently anything else with
5133 * alpha test or pixel discard.
5134 *
5135 * According to the spec, bit 11 (RCCUNIT) must also be set,
5136 * but we didn't debug actual testcases to find it out.
5137 *
5138 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5139 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5140 *
ecdb4eb7
DL		 5141 * Also apply WaDisableVDSUnitClockGating:vlv and
5142 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5143 */
5144 I915_WRITE(GEN6_UCGCTL2,
5145 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5146 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5147 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5148 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5149 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5150
e3f33d46
JB		 5151 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5152
e0d8d59b 5153 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5154
6b26c86d
DV		 5155 I915_WRITE(CACHE_MODE_1,
5156 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5157
2d809570 5158 /*
ecdb4eb7 5159 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5160 * Disable clock gating on th GCFG unit to prevent a delay
5161 * in the reporting of vblank events.
5162 */
4e8c84a5
JB		 5163 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5164
5165 /* Conservative clock gating settings for now */
5166 I915_WRITE(0x9400, 0xffffffff);
5167 I915_WRITE(0x9404, 0xffffffff);
5168 I915_WRITE(0x9408, 0xffffffff);
5169 I915_WRITE(0x940c, 0xffffffff);
5170 I915_WRITE(0x9410, 0xffffffff);
5171 I915_WRITE(0x9414, 0xffffffff);
5172 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5173}
5174
1fa61106 5175static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5176{
5177 struct drm_i915_private *dev_priv = dev->dev_private;
5178 uint32_t dspclk_gate;
5179
5180 I915_WRITE(RENCLK_GATE_D1, 0);
5181 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5182 GS_UNIT_CLOCK_GATE_DISABLE |
5183 CL_UNIT_CLOCK_GATE_DISABLE);
5184 I915_WRITE(RAMCLK_GATE_D, 0);
5185 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5186 OVRUNIT_CLOCK_GATE_DISABLE |
5187 OVCUNIT_CLOCK_GATE_DISABLE;
5188 if (IS_GM45(dev))
5189 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5190 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5191
5192 /* WaDisableRenderCachePipelinedFlush */
5193 I915_WRITE(CACHE_MODE_0,
5194 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5195
0e088b8f 5196 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5197}
5198
1fa61106 5199static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5200{
5201 struct drm_i915_private *dev_priv = dev->dev_private;
5202
5203 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5204 I915_WRITE(RENCLK_GATE_D2, 0);
5205 I915_WRITE(DSPCLK_GATE_D, 0);
5206 I915_WRITE(RAMCLK_GATE_D, 0);
5207 I915_WRITE16(DEUC, 0);
20f94967
VS		 5208 I915_WRITE(MI_ARB_STATE,
5209 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5210}
5211
1fa61106 5212static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5213{
5214 struct drm_i915_private *dev_priv = dev->dev_private;
5215
5216 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5217 I965_RCC_CLOCK_GATE_DISABLE |
5218 I965_RCPB_CLOCK_GATE_DISABLE |
5219 I965_ISC_CLOCK_GATE_DISABLE |
5220 I965_FBC_CLOCK_GATE_DISABLE);
5221 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5222 I915_WRITE(MI_ARB_STATE,
5223 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5224}
5225
1fa61106 5226static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5227{
5228 struct drm_i915_private *dev_priv = dev->dev_private;
5229 u32 dstate = I915_READ(D_STATE);
5230
5231 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5232 DSTATE_DOT_CLOCK_GATING;
5233 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5234
5235 if (IS_PINEVIEW(dev))
5236 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5237
5238 /* IIR "flip pending" means done if this bit is set */
5239 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5240}
5241
1fa61106 5242static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5243{
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245
5246 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5247}
5248
1fa61106 5249static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5250{
5251 struct drm_i915_private *dev_priv = dev->dev_private;
5252
5253 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5254}
5255
6f1d69b0
ED		 5256void intel_init_clock_gating(struct drm_device *dev)
5257{
5258 struct drm_i915_private *dev_priv = dev->dev_private;
5259
5260 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5261}
5262
7d708ee4
ID		 5263void intel_suspend_hw(struct drm_device *dev)
5264{
5265 if (HAS_PCH_LPT(dev))
5266 lpt_suspend_hw(dev);
5267}
5268
15d199ea
PZ		 5269/**
5270 * We should only use the power well if we explicitly asked the hardware to
5271 * enable it, so check if it's enabled and also check if we've requested it to
5272 * be enabled.
5273 */
b97186f0
PZ		 5274bool intel_display_power_enabled(struct drm_device *dev,
5275 enum intel_display_power_domain domain)
15d199ea
PZ		 5276{
5277 struct drm_i915_private *dev_priv = dev->dev_private;
5278
b97186f0
PZ		 5279 if (!HAS_POWER_WELL(dev))
5280 return true;
5281
5282 switch (domain) {
5283 case POWER_DOMAIN_PIPE_A:
5284 case POWER_DOMAIN_TRANSCODER_EDP:
5285 return true;
cdf8dd7f 5286 case POWER_DOMAIN_VGA:
b97186f0
PZ		 5287 case POWER_DOMAIN_PIPE_B:
5288 case POWER_DOMAIN_PIPE_C:
5289 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5290 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5291 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5292 case POWER_DOMAIN_TRANSCODER_A:
5293 case POWER_DOMAIN_TRANSCODER_B:
5294 case POWER_DOMAIN_TRANSCODER_C:
15d199ea 5295 return I915_READ(HSW_PWR_WELL_DRIVER) ==
6aedd1f5 5296 (HSW_PWR_WELL_ENABLE_REQUEST | HSW_PWR_WELL_STATE_ENABLED);
b97186f0
PZ		 5297 default:
5298 BUG();
5299 }
15d199ea
PZ		 5300}
5301
a38911a3 5302static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5303{
5304 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5305 bool is_enabled, enable_requested;
5306 uint32_t tmp;
d0d3e513 5307
fa42e23c 5308 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
6aedd1f5
PZ		 5309 is_enabled = tmp & HSW_PWR_WELL_STATE_ENABLED;
5310 enable_requested = tmp & HSW_PWR_WELL_ENABLE_REQUEST;
d0d3e513 5311
fa42e23c
PZ		 5312 if (enable) {
5313 if (!enable_requested)
6aedd1f5
PZ		 5314 I915_WRITE(HSW_PWR_WELL_DRIVER,
5315 HSW_PWR_WELL_ENABLE_REQUEST);
d0d3e513 5316
fa42e23c
PZ		 5317 if (!is_enabled) {
5318 DRM_DEBUG_KMS("Enabling power well\n");
5319 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
6aedd1f5 5320 HSW_PWR_WELL_STATE_ENABLED), 20))
fa42e23c
PZ		 5321 DRM_ERROR("Timeout enabling power well\n");
5322 }
5323 } else {
5324 if (enable_requested) {
9dbd8feb
PZ		 5325 unsigned long irqflags;
5326 enum pipe p;
5327
fa42e23c 5328 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
9dbd8feb 5329 POSTING_READ(HSW_PWR_WELL_DRIVER);
fa42e23c 5330 DRM_DEBUG_KMS("Requesting to disable the power well\n");
9dbd8feb
PZ		 5331
5332 /*
5333 * After this, the registers on the pipes that are part
5334 * of the power well will become zero, so we have to
5335 * adjust our counters according to that.
5336 *
5337 * FIXME: Should we do this in general in
5338 * drm_vblank_post_modeset?
5339 */
5340 spin_lock_irqsave(&dev->vbl_lock, irqflags);
5341 for_each_pipe(p)
5342 if (p != PIPE_A)
5343 dev->last_vblank[p] = 0;
5344 spin_unlock_irqrestore(&dev->vbl_lock, irqflags);
d0d3e513
ED		 5345 }
5346 }
fa42e23c 5347}
d0d3e513 5348
2d66aef5
VS		 5349static void __intel_power_well_get(struct i915_power_well *power_well)
5350{
5351 if (!power_well->count++)
5352 __intel_set_power_well(power_well->device, true);
5353}
5354
5355static void __intel_power_well_put(struct i915_power_well *power_well)
5356{
5357 WARN_ON(!power_well->count);
5358 if (!--power_well->count)
5359 __intel_set_power_well(power_well->device, false);
5360}
5361
6765625e
VS		 5362void intel_display_power_get(struct drm_device *dev,
5363 enum intel_display_power_domain domain)
5364{
5365 struct drm_i915_private *dev_priv = dev->dev_private;
5366 struct i915_power_well *power_well = &dev_priv->power_well;
5367
5368 if (!HAS_POWER_WELL(dev))
5369 return;
5370
5371 switch (domain) {
5372 case POWER_DOMAIN_PIPE_A:
5373 case POWER_DOMAIN_TRANSCODER_EDP:
5374 return;
cdf8dd7f 5375 case POWER_DOMAIN_VGA:
6765625e
VS		 5376 case POWER_DOMAIN_PIPE_B:
5377 case POWER_DOMAIN_PIPE_C:
5378 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5379 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5380 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5381 case POWER_DOMAIN_TRANSCODER_A:
5382 case POWER_DOMAIN_TRANSCODER_B:
5383 case POWER_DOMAIN_TRANSCODER_C:
5384 spin_lock_irq(&power_well->lock);
2d66aef5 5385 __intel_power_well_get(power_well);
6765625e
VS		 5386 spin_unlock_irq(&power_well->lock);
5387 return;
5388 default:
5389 BUG();
5390 }
5391}
5392
5393void intel_display_power_put(struct drm_device *dev,
5394 enum intel_display_power_domain domain)
5395{
5396 struct drm_i915_private *dev_priv = dev->dev_private;
5397 struct i915_power_well *power_well = &dev_priv->power_well;
5398
5399 if (!HAS_POWER_WELL(dev))
5400 return;
5401
5402 switch (domain) {
5403 case POWER_DOMAIN_PIPE_A:
5404 case POWER_DOMAIN_TRANSCODER_EDP:
5405 return;
cdf8dd7f 5406 case POWER_DOMAIN_VGA:
6765625e
VS		 5407 case POWER_DOMAIN_PIPE_B:
5408 case POWER_DOMAIN_PIPE_C:
5409 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5410 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5411 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5412 case POWER_DOMAIN_TRANSCODER_A:
5413 case POWER_DOMAIN_TRANSCODER_B:
5414 case POWER_DOMAIN_TRANSCODER_C:
5415 spin_lock_irq(&power_well->lock);
2d66aef5 5416 __intel_power_well_put(power_well);
6765625e
VS		 5417 spin_unlock_irq(&power_well->lock);
5418 return;
5419 default:
5420 BUG();
5421 }
5422}
5423
a38911a3
WX		 5424static struct i915_power_well *hsw_pwr;
5425
5426/* Display audio driver power well request */
5427void i915_request_power_well(void)
5428{
5429 if (WARN_ON(!hsw_pwr))
5430 return;
5431
5432 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5433 __intel_power_well_get(hsw_pwr);
a38911a3
WX		 5434 spin_unlock_irq(&hsw_pwr->lock);
5435}
5436EXPORT_SYMBOL_GPL(i915_request_power_well);
5437
5438/* Display audio driver power well release */
5439void i915_release_power_well(void)
5440{
5441 if (WARN_ON(!hsw_pwr))
5442 return;
5443
5444 spin_lock_irq(&hsw_pwr->lock);
2d66aef5 5445 __intel_power_well_put(hsw_pwr);
a38911a3
WX		 5446 spin_unlock_irq(&hsw_pwr->lock);
5447}
5448EXPORT_SYMBOL_GPL(i915_release_power_well);
5449
5450int i915_init_power_well(struct drm_device *dev)
5451{
5452 struct drm_i915_private *dev_priv = dev->dev_private;
5453
5454 hsw_pwr = &dev_priv->power_well;
5455
5456 hsw_pwr->device = dev;
5457 spin_lock_init(&hsw_pwr->lock);
5458 hsw_pwr->count = 0;
5459
5460 return 0;
5461}
5462
5463void i915_remove_power_well(struct drm_device *dev)
5464{
5465 hsw_pwr = NULL;
5466}
5467
5468void intel_set_power_well(struct drm_device *dev, bool enable)
5469{
5470 struct drm_i915_private *dev_priv = dev->dev_private;
5471 struct i915_power_well *power_well = &dev_priv->power_well;
5472
5473 if (!HAS_POWER_WELL(dev))
5474 return;
5475
5476 if (!i915_disable_power_well && !enable)
5477 return;
5478
5479 spin_lock_irq(&power_well->lock);
9cdb826c
VS		 5480
5481 /*
5482 * This function will only ever contribute one
5483 * to the power well reference count. i915_request
5484 * is what tracks whether we have or have not
5485 * added the one to the reference count.
5486 */
5487 if (power_well->i915_request == enable)
5488 goto out;
5489
a38911a3
WX		 5490 power_well->i915_request = enable;
5491
2d66aef5
VS		 5492 if (enable)
5493 __intel_power_well_get(power_well);
5494 else
5495 __intel_power_well_put(power_well);
a38911a3 5496
9cdb826c
VS		 5497 out:
5498 spin_unlock_irq(&power_well->lock);
5499}
5500
5501void intel_resume_power_well(struct drm_device *dev)
5502{
5503 struct drm_i915_private *dev_priv = dev->dev_private;
5504 struct i915_power_well *power_well = &dev_priv->power_well;
5505
5506 if (!HAS_POWER_WELL(dev))
5507 return;
5508
5509 spin_lock_irq(&power_well->lock);
5510 __intel_set_power_well(dev, power_well->count > 0);
a38911a3
WX		 5511 spin_unlock_irq(&power_well->lock);
5512}
5513
fa42e23c
PZ		 5514/*
5515 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5516 * when not needed anymore. We have 4 registers that can request the power well
5517 * to be enabled, and it will only be disabled if none of the registers is
5518 * requesting it to be enabled.
d0d3e513 5519 */
fa42e23c 5520void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5521{
5522 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5523
86d52df6 5524 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5525 return;
5526
fa42e23c
PZ		 5527 /* For now, we need the power well to be always enabled. */
5528 intel_set_power_well(dev, true);
9cdb826c 5529 intel_resume_power_well(dev);
d0d3e513 5530
fa42e23c
PZ		 5531 /* We're taking over the BIOS, so clear any requests made by it since
5532 * the driver is in charge now. */
6aedd1f5 5533 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE_REQUEST)
fa42e23c 5534 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5535}
5536
c67a470b
PZ		 5537/* Disables PC8 so we can use the GMBUS and DP AUX interrupts. */
5538void intel_aux_display_runtime_get(struct drm_i915_private *dev_priv)
5539{
5540 hsw_disable_package_c8(dev_priv);
5541}
5542
5543void intel_aux_display_runtime_put(struct drm_i915_private *dev_priv)
5544{
5545 hsw_enable_package_c8(dev_priv);
5546}
5547
1fa61106
ED		 5548/* Set up chip specific power management-related functions */
5549void intel_init_pm(struct drm_device *dev)
5550{
5551 struct drm_i915_private *dev_priv = dev->dev_private;
5552
5553 if (I915_HAS_FBC(dev)) {
5554 if (HAS_PCH_SPLIT(dev)) {
5555 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5556 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5557 dev_priv->display.enable_fbc =
5558 gen7_enable_fbc;
5559 else
5560 dev_priv->display.enable_fbc =
5561 ironlake_enable_fbc;
1fa61106
ED		 5562 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5563 } else if (IS_GM45(dev)) {
5564 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5565 dev_priv->display.enable_fbc = g4x_enable_fbc;
5566 dev_priv->display.disable_fbc = g4x_disable_fbc;
5567 } else if (IS_CRESTLINE(dev)) {
5568 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5569 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5570 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5571 }
5572 /* 855GM needs testing */
5573 }
5574
c921aba8
DV		 5575 /* For cxsr */
5576 if (IS_PINEVIEW(dev))
5577 i915_pineview_get_mem_freq(dev);
5578 else if (IS_GEN5(dev))
5579 i915_ironlake_get_mem_freq(dev);
5580
1fa61106
ED		 5581 /* For FIFO watermark updates */
5582 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5583 intel_setup_wm_latency(dev);
5584
1fa61106 5585 if (IS_GEN5(dev)) {
53615a5e
VS		 5586 if (dev_priv->wm.pri_latency[1] &&
5587 dev_priv->wm.spr_latency[1] &&
5588 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5589 dev_priv->display.update_wm = ironlake_update_wm;
5590 else {
5591 DRM_DEBUG_KMS("Failed to get proper latency. "
5592 "Disable CxSR\n");
5593 dev_priv->display.update_wm = NULL;
5594 }
5595 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5596 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5597 if (dev_priv->wm.pri_latency[0] &&
5598 dev_priv->wm.spr_latency[0] &&
5599 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5600 dev_priv->display.update_wm = sandybridge_update_wm;
5601 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5602 } else {
5603 DRM_DEBUG_KMS("Failed to read display plane latency. "
5604 "Disable CxSR\n");
5605 dev_priv->display.update_wm = NULL;
5606 }
5607 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5608 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5609 if (dev_priv->wm.pri_latency[0] &&
5610 dev_priv->wm.spr_latency[0] &&
5611 dev_priv->wm.cur_latency[0]) {
c43d0188 5612 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5613 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5614 } else {
5615 DRM_DEBUG_KMS("Failed to read display plane latency. "
5616 "Disable CxSR\n");
5617 dev_priv->display.update_wm = NULL;
5618 }
5619 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5620 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5621 if (dev_priv->wm.pri_latency[0] &&
5622 dev_priv->wm.spr_latency[0] &&
5623 dev_priv->wm.cur_latency[0]) {
1011d8c4 5624 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5625 dev_priv->display.update_sprite_wm =
5626 haswell_update_sprite_wm;
6b8a5eeb
ED		 5627 } else {
5628 DRM_DEBUG_KMS("Failed to read display plane latency. "
5629 "Disable CxSR\n");
5630 dev_priv->display.update_wm = NULL;
5631 }
cad2a2d7 5632 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5633 } else
5634 dev_priv->display.update_wm = NULL;
5635 } else if (IS_VALLEYVIEW(dev)) {
5636 dev_priv->display.update_wm = valleyview_update_wm;
5637 dev_priv->display.init_clock_gating =
5638 valleyview_init_clock_gating;
1fa61106
ED		 5639 } else if (IS_PINEVIEW(dev)) {
5640 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5641 dev_priv->is_ddr3,
5642 dev_priv->fsb_freq,
5643 dev_priv->mem_freq)) {
5644 DRM_INFO("failed to find known CxSR latency "
5645 "(found ddr%s fsb freq %d, mem freq %d), "
5646 "disabling CxSR\n",
5647 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5648 dev_priv->fsb_freq, dev_priv->mem_freq);
5649 /* Disable CxSR and never update its watermark again */
5650 pineview_disable_cxsr(dev);
5651 dev_priv->display.update_wm = NULL;
5652 } else
5653 dev_priv->display.update_wm = pineview_update_wm;
5654 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5655 } else if (IS_G4X(dev)) {
5656 dev_priv->display.update_wm = g4x_update_wm;
5657 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5658 } else if (IS_GEN4(dev)) {
5659 dev_priv->display.update_wm = i965_update_wm;
5660 if (IS_CRESTLINE(dev))
5661 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5662 else if (IS_BROADWATER(dev))
5663 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5664 } else if (IS_GEN3(dev)) {
5665 dev_priv->display.update_wm = i9xx_update_wm;
5666 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5667 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5668 } else if (IS_I865G(dev)) {
5669 dev_priv->display.update_wm = i830_update_wm;
5670 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5671 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5672 } else if (IS_I85X(dev)) {
5673 dev_priv->display.update_wm = i9xx_update_wm;
5674 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5675 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5676 } else {
5677 dev_priv->display.update_wm = i830_update_wm;
5678 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5679 if (IS_845G(dev))
5680 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5681 else
5682 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5683 }
5684}
5685
42c0526c
BW		 5686int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5687{
4fc688ce 5688 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5689
5690 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5691 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5692 return -EAGAIN;
5693 }
5694
5695 I915_WRITE(GEN6_PCODE_DATA, *val);
5696 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5697
5698 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5699 500)) {
5700 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5701 return -ETIMEDOUT;
5702 }
5703
5704 *val = I915_READ(GEN6_PCODE_DATA);
5705 I915_WRITE(GEN6_PCODE_DATA, 0);
5706
5707 return 0;
5708}
5709
5710int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5711{
4fc688ce 5712 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5713
5714 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5715 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5716 return -EAGAIN;
5717 }
5718
5719 I915_WRITE(GEN6_PCODE_DATA, val);
5720 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5721
5722 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5723 500)) {
5724 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5725 return -ETIMEDOUT;
5726 }
5727
5728 I915_WRITE(GEN6_PCODE_DATA, 0);
5729
5730 return 0;
5731}
a0e4e199 5732
855ba3be
JB		 5733int vlv_gpu_freq(int ddr_freq, int val)
5734{
5735 int mult, base;
5736
5737 switch (ddr_freq) {
5738 case 800:
5739 mult = 20;
5740 base = 120;
5741 break;
5742 case 1066:
5743 mult = 22;
5744 base = 133;
5745 break;
5746 case 1333:
5747 mult = 21;
5748 base = 125;
5749 break;
5750 default:
5751 return -1;
5752 }
5753
5754 return ((val - 0xbd) * mult) + base;
5755}
5756
5757int vlv_freq_opcode(int ddr_freq, int val)
5758{
5759 int mult, base;
5760
5761 switch (ddr_freq) {
5762 case 800:
5763 mult = 20;
5764 base = 120;
5765 break;
5766 case 1066:
5767 mult = 22;
5768 base = 133;
5769 break;
5770 case 1333:
5771 mult = 21;
5772 base = 125;
5773 break;
5774 default:
5775 return -1;
5776 }
5777
5778 val /= mult;
5779 val -= base / mult;
5780 val += 0xbd;
5781
5782 if (val > 0xea)
5783 val = 0xea;
5784
5785 return val;
5786}
5787
907b28c5
CW		 5788void intel_pm_init(struct drm_device *dev)
5789{
5790 struct drm_i915_private *dev_priv = dev->dev_private;
5791
5792 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5793 intel_gen6_powersave_work);
5794}
5795
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