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drm/i915: clean up crtc timings computation
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
424/**
425 * intel_update_fbc - enable/disable FBC as needed
426 * @dev: the drm_device
427 *
428 * Set up the framebuffer compression hardware at mode set time. We
429 * enable it if possible:
430 * - plane A only (on pre-965)
431 * - no pixel mulitply/line duplication
432 * - no alpha buffer discard
433 * - no dual wide
f85da868 434 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 435 *
436 * We can't assume that any compression will take place (worst case),
437 * so the compressed buffer has to be the same size as the uncompressed
438 * one. It also must reside (along with the line length buffer) in
439 * stolen memory.
440 *
441 * We need to enable/disable FBC on a global basis.
442 */
443void intel_update_fbc(struct drm_device *dev)
444{
445 struct drm_i915_private *dev_priv = dev->dev_private;
446 struct drm_crtc *crtc = NULL, *tmp_crtc;
447 struct intel_crtc *intel_crtc;
448 struct drm_framebuffer *fb;
449 struct intel_framebuffer *intel_fb;
450 struct drm_i915_gem_object *obj;
f85da868 451 unsigned int max_hdisplay, max_vdisplay;
85208be0 452
85208be0
ED		 453 if (!i915_powersave)
454 return;
455
456 if (!I915_HAS_FBC(dev))
457 return;
458
459 /*
460 * If FBC is already on, we just have to verify that we can
461 * keep it that way...
462 * Need to disable if:
463 * - more than one pipe is active
464 * - changing FBC params (stride, fence, mode)
465 * - new fb is too large to fit in compressed buffer
466 * - going to an unsupported config (interlace, pixel multiply, etc.)
467 */
468 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 469 if (intel_crtc_active(tmp_crtc) &&
470 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 471 if (crtc) {
472 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
5c3fe8b0
BW		 473 dev_priv->fbc.no_fbc_reason =
474 FBC_MULTIPLE_PIPES;
85208be0
ED		 475 goto out_disable;
476 }
477 crtc = tmp_crtc;
478 }
479 }
480
481 if (!crtc || crtc->fb == NULL) {
482 DRM_DEBUG_KMS("no output, disabling\n");
5c3fe8b0 483 dev_priv->fbc.no_fbc_reason = FBC_NO_OUTPUT;
85208be0
ED		 484 goto out_disable;
485 }
486
487 intel_crtc = to_intel_crtc(crtc);
488 fb = crtc->fb;
489 intel_fb = to_intel_framebuffer(fb);
490 obj = intel_fb->obj;
491
8a5729a3
DL		 492 if (i915_enable_fbc < 0 &&
493 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
494 DRM_DEBUG_KMS("disabled per chip default\n");
5c3fe8b0 495 dev_priv->fbc.no_fbc_reason = FBC_CHIP_DEFAULT;
8a5729a3 496 goto out_disable;
85208be0 497 }
8a5729a3 498 if (!i915_enable_fbc) {
85208be0 499 DRM_DEBUG_KMS("fbc disabled per module param\n");
5c3fe8b0 500 dev_priv->fbc.no_fbc_reason = FBC_MODULE_PARAM;
85208be0
ED		 501 goto out_disable;
502 }
85208be0
ED		 503 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
504 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
505 DRM_DEBUG_KMS("mode incompatible with compression, "
506 "disabling\n");
5c3fe8b0 507 dev_priv->fbc.no_fbc_reason = FBC_UNSUPPORTED_MODE;
85208be0
ED		 508 goto out_disable;
509 }
f85da868
PZ		 510
511 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
512 max_hdisplay = 4096;
513 max_vdisplay = 2048;
514 } else {
515 max_hdisplay = 2048;
516 max_vdisplay = 1536;
517 }
518 if ((crtc->mode.hdisplay > max_hdisplay) ||
519 (crtc->mode.vdisplay > max_vdisplay)) {
85208be0 520 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
5c3fe8b0 521 dev_priv->fbc.no_fbc_reason = FBC_MODE_TOO_LARGE;
85208be0
ED		 522 goto out_disable;
523 }
891348b2
RV		 524 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
525 intel_crtc->plane != 0) {
85208be0 526 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
5c3fe8b0 527 dev_priv->fbc.no_fbc_reason = FBC_BAD_PLANE;
85208be0
ED		 528 goto out_disable;
529 }
530
531 /* The use of a CPU fence is mandatory in order to detect writes
532 * by the CPU to the scanout and trigger updates to the FBC.
533 */
534 if (obj->tiling_mode != I915_TILING_X ||
535 obj->fence_reg == I915_FENCE_REG_NONE) {
536 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
5c3fe8b0 537 dev_priv->fbc.no_fbc_reason = FBC_NOT_TILED;
85208be0
ED		 538 goto out_disable;
539 }
540
541 /* If the kernel debugger is active, always disable compression */
542 if (in_dbg_master())
543 goto out_disable;
544
11be49eb 545 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
11be49eb 546 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
5c3fe8b0 547 dev_priv->fbc.no_fbc_reason = FBC_STOLEN_TOO_SMALL;
11be49eb
CW		 548 goto out_disable;
549 }
550
85208be0
ED		 551 /* If the scanout has not changed, don't modify the FBC settings.
552 * Note that we make the fundamental assumption that the fb->obj
553 * cannot be unpinned (and have its GTT offset and fence revoked)
554 * without first being decoupled from the scanout and FBC disabled.
555 */
5c3fe8b0
BW		 556 if (dev_priv->fbc.plane == intel_crtc->plane &&
557 dev_priv->fbc.fb_id == fb->base.id &&
558 dev_priv->fbc.y == crtc->y)
85208be0
ED		 559 return;
560
561 if (intel_fbc_enabled(dev)) {
562 /* We update FBC along two paths, after changing fb/crtc
563 * configuration (modeswitching) and after page-flipping
564 * finishes. For the latter, we know that not only did
565 * we disable the FBC at the start of the page-flip
566 * sequence, but also more than one vblank has passed.
567 *
568 * For the former case of modeswitching, it is possible
569 * to switch between two FBC valid configurations
570 * instantaneously so we do need to disable the FBC
571 * before we can modify its control registers. We also
572 * have to wait for the next vblank for that to take
573 * effect. However, since we delay enabling FBC we can
574 * assume that a vblank has passed since disabling and
575 * that we can safely alter the registers in the deferred
576 * callback.
577 *
578 * In the scenario that we go from a valid to invalid
579 * and then back to valid FBC configuration we have
580 * no strict enforcement that a vblank occurred since
581 * disabling the FBC. However, along all current pipe
582 * disabling paths we do need to wait for a vblank at
583 * some point. And we wait before enabling FBC anyway.
584 */
585 DRM_DEBUG_KMS("disabling active FBC for update\n");
586 intel_disable_fbc(dev);
587 }
588
589 intel_enable_fbc(crtc, 500);
590 return;
591
592out_disable:
593 /* Multiple disables should be harmless */
594 if (intel_fbc_enabled(dev)) {
595 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
596 intel_disable_fbc(dev);
597 }
11be49eb 598 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 599}
600
c921aba8
DV		 601static void i915_pineview_get_mem_freq(struct drm_device *dev)
602{
603 drm_i915_private_t *dev_priv = dev->dev_private;
604 u32 tmp;
605
606 tmp = I915_READ(CLKCFG);
607
608 switch (tmp & CLKCFG_FSB_MASK) {
609 case CLKCFG_FSB_533:
610 dev_priv->fsb_freq = 533; /* 133*4 */
611 break;
612 case CLKCFG_FSB_800:
613 dev_priv->fsb_freq = 800; /* 200*4 */
614 break;
615 case CLKCFG_FSB_667:
616 dev_priv->fsb_freq = 667; /* 167*4 */
617 break;
618 case CLKCFG_FSB_400:
619 dev_priv->fsb_freq = 400; /* 100*4 */
620 break;
621 }
622
623 switch (tmp & CLKCFG_MEM_MASK) {
624 case CLKCFG_MEM_533:
625 dev_priv->mem_freq = 533;
626 break;
627 case CLKCFG_MEM_667:
628 dev_priv->mem_freq = 667;
629 break;
630 case CLKCFG_MEM_800:
631 dev_priv->mem_freq = 800;
632 break;
633 }
634
635 /* detect pineview DDR3 setting */
636 tmp = I915_READ(CSHRDDR3CTL);
637 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
638}
639
640static void i915_ironlake_get_mem_freq(struct drm_device *dev)
641{
642 drm_i915_private_t *dev_priv = dev->dev_private;
643 u16 ddrpll, csipll;
644
645 ddrpll = I915_READ16(DDRMPLL1);
646 csipll = I915_READ16(CSIPLL0);
647
648 switch (ddrpll & 0xff) {
649 case 0xc:
650 dev_priv->mem_freq = 800;
651 break;
652 case 0x10:
653 dev_priv->mem_freq = 1066;
654 break;
655 case 0x14:
656 dev_priv->mem_freq = 1333;
657 break;
658 case 0x18:
659 dev_priv->mem_freq = 1600;
660 break;
661 default:
662 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
663 ddrpll & 0xff);
664 dev_priv->mem_freq = 0;
665 break;
666 }
667
20e4d407 668 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 669
670 switch (csipll & 0x3ff) {
671 case 0x00c:
672 dev_priv->fsb_freq = 3200;
673 break;
674 case 0x00e:
675 dev_priv->fsb_freq = 3733;
676 break;
677 case 0x010:
678 dev_priv->fsb_freq = 4266;
679 break;
680 case 0x012:
681 dev_priv->fsb_freq = 4800;
682 break;
683 case 0x014:
684 dev_priv->fsb_freq = 5333;
685 break;
686 case 0x016:
687 dev_priv->fsb_freq = 5866;
688 break;
689 case 0x018:
690 dev_priv->fsb_freq = 6400;
691 break;
692 default:
693 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
694 csipll & 0x3ff);
695 dev_priv->fsb_freq = 0;
696 break;
697 }
698
699 if (dev_priv->fsb_freq == 3200) {
20e4d407 700 dev_priv->ips.c_m = 0;
c921aba8 701 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 702 dev_priv->ips.c_m = 1;
c921aba8 703 } else {
20e4d407 704 dev_priv->ips.c_m = 2;
c921aba8
DV		 705 }
706}
707
b445e3b0
ED		 708static const struct cxsr_latency cxsr_latency_table[] = {
709 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
710 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
711 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
712 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
713 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
714
715 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
716 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
717 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
718 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
719 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
720
721 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
722 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
723 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
724 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
725 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
726
727 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
728 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
729 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
730 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
731 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
732
733 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
734 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
735 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
736 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
737 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
738
739 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
740 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
741 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
742 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
743 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
744};
745
63c62275 746static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 747 int is_ddr3,
748 int fsb,
749 int mem)
750{
751 const struct cxsr_latency *latency;
752 int i;
753
754 if (fsb == 0 || mem == 0)
755 return NULL;
756
757 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
758 latency = &cxsr_latency_table[i];
759 if (is_desktop == latency->is_desktop &&
760 is_ddr3 == latency->is_ddr3 &&
761 fsb == latency->fsb_freq && mem == latency->mem_freq)
762 return latency;
763 }
764
765 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
766
767 return NULL;
768}
769
1fa61106 770static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 771{
772 struct drm_i915_private *dev_priv = dev->dev_private;
773
774 /* deactivate cxsr */
775 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
776}
777
778/*
779 * Latency for FIFO fetches is dependent on several factors:
780 * - memory configuration (speed, channels)
781 * - chipset
782 * - current MCH state
783 * It can be fairly high in some situations, so here we assume a fairly
784 * pessimal value. It's a tradeoff between extra memory fetches (if we
785 * set this value too high, the FIFO will fetch frequently to stay full)
786 * and power consumption (set it too low to save power and we might see
787 * FIFO underruns and display "flicker").
788 *
789 * A value of 5us seems to be a good balance; safe for very low end
790 * platforms but not overly aggressive on lower latency configs.
791 */
792static const int latency_ns = 5000;
793
1fa61106 794static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 795{
796 struct drm_i915_private *dev_priv = dev->dev_private;
797 uint32_t dsparb = I915_READ(DSPARB);
798 int size;
799
800 size = dsparb & 0x7f;
801 if (plane)
802 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
803
804 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
805 plane ? "B" : "A", size);
806
807 return size;
808}
809
1fa61106 810static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 811{
812 struct drm_i915_private *dev_priv = dev->dev_private;
813 uint32_t dsparb = I915_READ(DSPARB);
814 int size;
815
816 size = dsparb & 0x1ff;
817 if (plane)
818 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
819 size >>= 1; /* Convert to cachelines */
820
821 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
822 plane ? "B" : "A", size);
823
824 return size;
825}
826
1fa61106 827static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 828{
829 struct drm_i915_private *dev_priv = dev->dev_private;
830 uint32_t dsparb = I915_READ(DSPARB);
831 int size;
832
833 size = dsparb & 0x7f;
834 size >>= 2; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A",
838 size);
839
840 return size;
841}
842
1fa61106 843static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 844{
845 struct drm_i915_private *dev_priv = dev->dev_private;
846 uint32_t dsparb = I915_READ(DSPARB);
847 int size;
848
849 size = dsparb & 0x7f;
850 size >>= 1; /* Convert to cachelines */
851
852 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
853 plane ? "B" : "A", size);
854
855 return size;
856}
857
858/* Pineview has different values for various configs */
859static const struct intel_watermark_params pineview_display_wm = {
860 PINEVIEW_DISPLAY_FIFO,
861 PINEVIEW_MAX_WM,
862 PINEVIEW_DFT_WM,
863 PINEVIEW_GUARD_WM,
864 PINEVIEW_FIFO_LINE_SIZE
865};
866static const struct intel_watermark_params pineview_display_hplloff_wm = {
867 PINEVIEW_DISPLAY_FIFO,
868 PINEVIEW_MAX_WM,
869 PINEVIEW_DFT_HPLLOFF_WM,
870 PINEVIEW_GUARD_WM,
871 PINEVIEW_FIFO_LINE_SIZE
872};
873static const struct intel_watermark_params pineview_cursor_wm = {
874 PINEVIEW_CURSOR_FIFO,
875 PINEVIEW_CURSOR_MAX_WM,
876 PINEVIEW_CURSOR_DFT_WM,
877 PINEVIEW_CURSOR_GUARD_WM,
878 PINEVIEW_FIFO_LINE_SIZE,
879};
880static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
881 PINEVIEW_CURSOR_FIFO,
882 PINEVIEW_CURSOR_MAX_WM,
883 PINEVIEW_CURSOR_DFT_WM,
884 PINEVIEW_CURSOR_GUARD_WM,
885 PINEVIEW_FIFO_LINE_SIZE
886};
887static const struct intel_watermark_params g4x_wm_info = {
888 G4X_FIFO_SIZE,
889 G4X_MAX_WM,
890 G4X_MAX_WM,
891 2,
892 G4X_FIFO_LINE_SIZE,
893};
894static const struct intel_watermark_params g4x_cursor_wm_info = {
895 I965_CURSOR_FIFO,
896 I965_CURSOR_MAX_WM,
897 I965_CURSOR_DFT_WM,
898 2,
899 G4X_FIFO_LINE_SIZE,
900};
901static const struct intel_watermark_params valleyview_wm_info = {
902 VALLEYVIEW_FIFO_SIZE,
903 VALLEYVIEW_MAX_WM,
904 VALLEYVIEW_MAX_WM,
905 2,
906 G4X_FIFO_LINE_SIZE,
907};
908static const struct intel_watermark_params valleyview_cursor_wm_info = {
909 I965_CURSOR_FIFO,
910 VALLEYVIEW_CURSOR_MAX_WM,
911 I965_CURSOR_DFT_WM,
912 2,
913 G4X_FIFO_LINE_SIZE,
914};
915static const struct intel_watermark_params i965_cursor_wm_info = {
916 I965_CURSOR_FIFO,
917 I965_CURSOR_MAX_WM,
918 I965_CURSOR_DFT_WM,
919 2,
920 I915_FIFO_LINE_SIZE,
921};
922static const struct intel_watermark_params i945_wm_info = {
923 I945_FIFO_SIZE,
924 I915_MAX_WM,
925 1,
926 2,
927 I915_FIFO_LINE_SIZE
928};
929static const struct intel_watermark_params i915_wm_info = {
930 I915_FIFO_SIZE,
931 I915_MAX_WM,
932 1,
933 2,
934 I915_FIFO_LINE_SIZE
935};
936static const struct intel_watermark_params i855_wm_info = {
937 I855GM_FIFO_SIZE,
938 I915_MAX_WM,
939 1,
940 2,
941 I830_FIFO_LINE_SIZE
942};
943static const struct intel_watermark_params i830_wm_info = {
944 I830_FIFO_SIZE,
945 I915_MAX_WM,
946 1,
947 2,
948 I830_FIFO_LINE_SIZE
949};
950
951static const struct intel_watermark_params ironlake_display_wm_info = {
952 ILK_DISPLAY_FIFO,
953 ILK_DISPLAY_MAXWM,
954 ILK_DISPLAY_DFTWM,
955 2,
956 ILK_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params ironlake_cursor_wm_info = {
959 ILK_CURSOR_FIFO,
960 ILK_CURSOR_MAXWM,
961 ILK_CURSOR_DFTWM,
962 2,
963 ILK_FIFO_LINE_SIZE
964};
965static const struct intel_watermark_params ironlake_display_srwm_info = {
966 ILK_DISPLAY_SR_FIFO,
967 ILK_DISPLAY_MAX_SRWM,
968 ILK_DISPLAY_DFT_SRWM,
969 2,
970 ILK_FIFO_LINE_SIZE
971};
972static const struct intel_watermark_params ironlake_cursor_srwm_info = {
973 ILK_CURSOR_SR_FIFO,
974 ILK_CURSOR_MAX_SRWM,
975 ILK_CURSOR_DFT_SRWM,
976 2,
977 ILK_FIFO_LINE_SIZE
978};
979
980static const struct intel_watermark_params sandybridge_display_wm_info = {
981 SNB_DISPLAY_FIFO,
982 SNB_DISPLAY_MAXWM,
983 SNB_DISPLAY_DFTWM,
984 2,
985 SNB_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params sandybridge_cursor_wm_info = {
988 SNB_CURSOR_FIFO,
989 SNB_CURSOR_MAXWM,
990 SNB_CURSOR_DFTWM,
991 2,
992 SNB_FIFO_LINE_SIZE
993};
994static const struct intel_watermark_params sandybridge_display_srwm_info = {
995 SNB_DISPLAY_SR_FIFO,
996 SNB_DISPLAY_MAX_SRWM,
997 SNB_DISPLAY_DFT_SRWM,
998 2,
999 SNB_FIFO_LINE_SIZE
1000};
1001static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1002 SNB_CURSOR_SR_FIFO,
1003 SNB_CURSOR_MAX_SRWM,
1004 SNB_CURSOR_DFT_SRWM,
1005 2,
1006 SNB_FIFO_LINE_SIZE
1007};
1008
1009
1010/**
1011 * intel_calculate_wm - calculate watermark level
1012 * @clock_in_khz: pixel clock
1013 * @wm: chip FIFO params
1014 * @pixel_size: display pixel size
1015 * @latency_ns: memory latency for the platform
1016 *
1017 * Calculate the watermark level (the level at which the display plane will
1018 * start fetching from memory again). Each chip has a different display
1019 * FIFO size and allocation, so the caller needs to figure that out and pass
1020 * in the correct intel_watermark_params structure.
1021 *
1022 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1023 * on the pixel size. When it reaches the watermark level, it'll start
1024 * fetching FIFO line sized based chunks from memory until the FIFO fills
1025 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1026 * will occur, and a display engine hang could result.
1027 */
1028static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1029 const struct intel_watermark_params *wm,
1030 int fifo_size,
1031 int pixel_size,
1032 unsigned long latency_ns)
1033{
1034 long entries_required, wm_size;
1035
1036 /*
1037 * Note: we need to make sure we don't overflow for various clock &
1038 * latency values.
1039 * clocks go from a few thousand to several hundred thousand.
1040 * latency is usually a few thousand
1041 */
1042 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1043 1000;
1044 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1045
1046 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1047
1048 wm_size = fifo_size - (entries_required + wm->guard_size);
1049
1050 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1051
1052 /* Don't promote wm_size to unsigned... */
1053 if (wm_size > (long)wm->max_wm)
1054 wm_size = wm->max_wm;
1055 if (wm_size <= 0)
1056 wm_size = wm->default_wm;
1057 return wm_size;
1058}
1059
1060static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1061{
1062 struct drm_crtc *crtc, *enabled = NULL;
1063
1064 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1065 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1066 if (enabled)
1067 return NULL;
1068 enabled = crtc;
1069 }
1070 }
1071
1072 return enabled;
1073}
1074
1fa61106 1075static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1076{
1077 struct drm_i915_private *dev_priv = dev->dev_private;
1078 struct drm_crtc *crtc;
1079 const struct cxsr_latency *latency;
1080 u32 reg;
1081 unsigned long wm;
1082
1083 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1084 dev_priv->fsb_freq, dev_priv->mem_freq);
1085 if (!latency) {
1086 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1087 pineview_disable_cxsr(dev);
1088 return;
1089 }
1090
1091 crtc = single_enabled_crtc(dev);
1092 if (crtc) {
1093 int clock = crtc->mode.clock;
1094 int pixel_size = crtc->fb->bits_per_pixel / 8;
1095
1096 /* Display SR */
1097 wm = intel_calculate_wm(clock, &pineview_display_wm,
1098 pineview_display_wm.fifo_size,
1099 pixel_size, latency->display_sr);
1100 reg = I915_READ(DSPFW1);
1101 reg &= ~DSPFW_SR_MASK;
1102 reg |= wm << DSPFW_SR_SHIFT;
1103 I915_WRITE(DSPFW1, reg);
1104 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1105
1106 /* cursor SR */
1107 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1108 pineview_display_wm.fifo_size,
1109 pixel_size, latency->cursor_sr);
1110 reg = I915_READ(DSPFW3);
1111 reg &= ~DSPFW_CURSOR_SR_MASK;
1112 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1113 I915_WRITE(DSPFW3, reg);
1114
1115 /* Display HPLL off SR */
1116 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1117 pineview_display_hplloff_wm.fifo_size,
1118 pixel_size, latency->display_hpll_disable);
1119 reg = I915_READ(DSPFW3);
1120 reg &= ~DSPFW_HPLL_SR_MASK;
1121 reg |= wm & DSPFW_HPLL_SR_MASK;
1122 I915_WRITE(DSPFW3, reg);
1123
1124 /* cursor HPLL off SR */
1125 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1126 pineview_display_hplloff_wm.fifo_size,
1127 pixel_size, latency->cursor_hpll_disable);
1128 reg = I915_READ(DSPFW3);
1129 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1130 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1131 I915_WRITE(DSPFW3, reg);
1132 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1133
1134 /* activate cxsr */
1135 I915_WRITE(DSPFW3,
1136 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1137 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1138 } else {
1139 pineview_disable_cxsr(dev);
1140 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1141 }
1142}
1143
1144static bool g4x_compute_wm0(struct drm_device *dev,
1145 int plane,
1146 const struct intel_watermark_params *display,
1147 int display_latency_ns,
1148 const struct intel_watermark_params *cursor,
1149 int cursor_latency_ns,
1150 int *plane_wm,
1151 int *cursor_wm)
1152{
1153 struct drm_crtc *crtc;
1154 int htotal, hdisplay, clock, pixel_size;
1155 int line_time_us, line_count;
1156 int entries, tlb_miss;
1157
1158 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1159 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1160 *cursor_wm = cursor->guard_size;
1161 *plane_wm = display->guard_size;
1162 return false;
1163 }
1164
1165 htotal = crtc->mode.htotal;
1166 hdisplay = crtc->mode.hdisplay;
1167 clock = crtc->mode.clock;
1168 pixel_size = crtc->fb->bits_per_pixel / 8;
1169
1170 /* Use the small buffer method to calculate plane watermark */
1171 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1172 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1173 if (tlb_miss > 0)
1174 entries += tlb_miss;
1175 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1176 *plane_wm = entries + display->guard_size;
1177 if (*plane_wm > (int)display->max_wm)
1178 *plane_wm = display->max_wm;
1179
1180 /* Use the large buffer method to calculate cursor watermark */
1181 line_time_us = ((htotal * 1000) / clock);
1182 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1183 entries = line_count * 64 * pixel_size;
1184 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1185 if (tlb_miss > 0)
1186 entries += tlb_miss;
1187 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1188 *cursor_wm = entries + cursor->guard_size;
1189 if (*cursor_wm > (int)cursor->max_wm)
1190 *cursor_wm = (int)cursor->max_wm;
1191
1192 return true;
1193}
1194
1195/*
1196 * Check the wm result.
1197 *
1198 * If any calculated watermark values is larger than the maximum value that
1199 * can be programmed into the associated watermark register, that watermark
1200 * must be disabled.
1201 */
1202static bool g4x_check_srwm(struct drm_device *dev,
1203 int display_wm, int cursor_wm,
1204 const struct intel_watermark_params *display,
1205 const struct intel_watermark_params *cursor)
1206{
1207 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1208 display_wm, cursor_wm);
1209
1210 if (display_wm > display->max_wm) {
1211 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1212 display_wm, display->max_wm);
1213 return false;
1214 }
1215
1216 if (cursor_wm > cursor->max_wm) {
1217 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1218 cursor_wm, cursor->max_wm);
1219 return false;
1220 }
1221
1222 if (!(display_wm || cursor_wm)) {
1223 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1224 return false;
1225 }
1226
1227 return true;
1228}
1229
1230static bool g4x_compute_srwm(struct drm_device *dev,
1231 int plane,
1232 int latency_ns,
1233 const struct intel_watermark_params *display,
1234 const struct intel_watermark_params *cursor,
1235 int *display_wm, int *cursor_wm)
1236{
1237 struct drm_crtc *crtc;
1238 int hdisplay, htotal, pixel_size, clock;
1239 unsigned long line_time_us;
1240 int line_count, line_size;
1241 int small, large;
1242 int entries;
1243
1244 if (!latency_ns) {
1245 *display_wm = *cursor_wm = 0;
1246 return false;
1247 }
1248
1249 crtc = intel_get_crtc_for_plane(dev, plane);
1250 hdisplay = crtc->mode.hdisplay;
1251 htotal = crtc->mode.htotal;
1252 clock = crtc->mode.clock;
1253 pixel_size = crtc->fb->bits_per_pixel / 8;
1254
1255 line_time_us = (htotal * 1000) / clock;
1256 line_count = (latency_ns / line_time_us + 1000) / 1000;
1257 line_size = hdisplay * pixel_size;
1258
1259 /* Use the minimum of the small and large buffer method for primary */
1260 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1261 large = line_count * line_size;
1262
1263 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1264 *display_wm = entries + display->guard_size;
1265
1266 /* calculate the self-refresh watermark for display cursor */
1267 entries = line_count * pixel_size * 64;
1268 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1269 *cursor_wm = entries + cursor->guard_size;
1270
1271 return g4x_check_srwm(dev,
1272 *display_wm, *cursor_wm,
1273 display, cursor);
1274}
1275
1276static bool vlv_compute_drain_latency(struct drm_device *dev,
1277 int plane,
1278 int *plane_prec_mult,
1279 int *plane_dl,
1280 int *cursor_prec_mult,
1281 int *cursor_dl)
1282{
1283 struct drm_crtc *crtc;
1284 int clock, pixel_size;
1285 int entries;
1286
1287 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1288 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1289 return false;
1290
1291 clock = crtc->mode.clock; /* VESA DOT Clock */
1292 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1293
1294 entries = (clock / 1000) * pixel_size;
1295 *plane_prec_mult = (entries > 256) ?
1296 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1297 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1298 pixel_size);
1299
1300 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1301 *cursor_prec_mult = (entries > 256) ?
1302 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1303 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1304
1305 return true;
1306}
1307
1308/*
1309 * Update drain latency registers of memory arbiter
1310 *
1311 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1312 * to be programmed. Each plane has a drain latency multiplier and a drain
1313 * latency value.
1314 */
1315
1316static void vlv_update_drain_latency(struct drm_device *dev)
1317{
1318 struct drm_i915_private *dev_priv = dev->dev_private;
1319 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1320 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1321 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1322 either 16 or 32 */
1323
1324 /* For plane A, Cursor A */
1325 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1326 &cursor_prec_mult, &cursora_dl)) {
1327 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1328 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1329 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1330 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1331
1332 I915_WRITE(VLV_DDL1, cursora_prec |
1333 (cursora_dl << DDL_CURSORA_SHIFT) |
1334 planea_prec | planea_dl);
1335 }
1336
1337 /* For plane B, Cursor B */
1338 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1339 &cursor_prec_mult, &cursorb_dl)) {
1340 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1341 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1342 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1344
1345 I915_WRITE(VLV_DDL2, cursorb_prec |
1346 (cursorb_dl << DDL_CURSORB_SHIFT) |
1347 planeb_prec | planeb_dl);
1348 }
1349}
1350
1351#define single_plane_enabled(mask) is_power_of_2(mask)
1352
1fa61106 1353static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1354{
1355 static const int sr_latency_ns = 12000;
1356 struct drm_i915_private *dev_priv = dev->dev_private;
1357 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1358 int plane_sr, cursor_sr;
af6c4575 1359 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1360 unsigned int enabled = 0;
1361
1362 vlv_update_drain_latency(dev);
1363
51cea1f4 1364 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1365 &valleyview_wm_info, latency_ns,
1366 &valleyview_cursor_wm_info, latency_ns,
1367 &planea_wm, &cursora_wm))
51cea1f4 1368 enabled |= 1 << PIPE_A;
b445e3b0 1369
51cea1f4 1370 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1371 &valleyview_wm_info, latency_ns,
1372 &valleyview_cursor_wm_info, latency_ns,
1373 &planeb_wm, &cursorb_wm))
51cea1f4 1374 enabled |= 1 << PIPE_B;
b445e3b0 1375
b445e3b0
ED		 1376 if (single_plane_enabled(enabled) &&
1377 g4x_compute_srwm(dev, ffs(enabled) - 1,
1378 sr_latency_ns,
1379 &valleyview_wm_info,
1380 &valleyview_cursor_wm_info,
af6c4575
CW		 1381 &plane_sr, &ignore_cursor_sr) &&
1382 g4x_compute_srwm(dev, ffs(enabled) - 1,
1383 2*sr_latency_ns,
1384 &valleyview_wm_info,
1385 &valleyview_cursor_wm_info,
52bd02d8 1386 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1387 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1388 } else {
b445e3b0
ED		 1389 I915_WRITE(FW_BLC_SELF_VLV,
1390 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1391 plane_sr = cursor_sr = 0;
1392 }
b445e3b0
ED		 1393
1394 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1395 planea_wm, cursora_wm,
1396 planeb_wm, cursorb_wm,
1397 plane_sr, cursor_sr);
1398
1399 I915_WRITE(DSPFW1,
1400 (plane_sr << DSPFW_SR_SHIFT) |
1401 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1402 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1403 planea_wm);
1404 I915_WRITE(DSPFW2,
8c919b28 1405 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1406 (cursora_wm << DSPFW_CURSORA_SHIFT));
1407 I915_WRITE(DSPFW3,
8c919b28
CW		 1408 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1409 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1410}
1411
1fa61106 1412static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1413{
1414 static const int sr_latency_ns = 12000;
1415 struct drm_i915_private *dev_priv = dev->dev_private;
1416 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1417 int plane_sr, cursor_sr;
1418 unsigned int enabled = 0;
1419
51cea1f4 1420 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1421 &g4x_wm_info, latency_ns,
1422 &g4x_cursor_wm_info, latency_ns,
1423 &planea_wm, &cursora_wm))
51cea1f4 1424 enabled |= 1 << PIPE_A;
b445e3b0 1425
51cea1f4 1426 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1427 &g4x_wm_info, latency_ns,
1428 &g4x_cursor_wm_info, latency_ns,
1429 &planeb_wm, &cursorb_wm))
51cea1f4 1430 enabled |= 1 << PIPE_B;
b445e3b0 1431
b445e3b0
ED		 1432 if (single_plane_enabled(enabled) &&
1433 g4x_compute_srwm(dev, ffs(enabled) - 1,
1434 sr_latency_ns,
1435 &g4x_wm_info,
1436 &g4x_cursor_wm_info,
52bd02d8 1437 &plane_sr, &cursor_sr)) {
b445e3b0 1438 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1439 } else {
b445e3b0
ED		 1440 I915_WRITE(FW_BLC_SELF,
1441 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1442 plane_sr = cursor_sr = 0;
1443 }
b445e3b0
ED		 1444
1445 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1446 planea_wm, cursora_wm,
1447 planeb_wm, cursorb_wm,
1448 plane_sr, cursor_sr);
1449
1450 I915_WRITE(DSPFW1,
1451 (plane_sr << DSPFW_SR_SHIFT) |
1452 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1453 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1454 planea_wm);
1455 I915_WRITE(DSPFW2,
8c919b28 1456 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1457 (cursora_wm << DSPFW_CURSORA_SHIFT));
1458 /* HPLL off in SR has some issues on G4x... disable it */
1459 I915_WRITE(DSPFW3,
8c919b28 1460 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1461 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1462}
1463
1fa61106 1464static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1465{
1466 struct drm_i915_private *dev_priv = dev->dev_private;
1467 struct drm_crtc *crtc;
1468 int srwm = 1;
1469 int cursor_sr = 16;
1470
1471 /* Calc sr entries for one plane configs */
1472 crtc = single_enabled_crtc(dev);
1473 if (crtc) {
1474 /* self-refresh has much higher latency */
1475 static const int sr_latency_ns = 12000;
1476 int clock = crtc->mode.clock;
1477 int htotal = crtc->mode.htotal;
1478 int hdisplay = crtc->mode.hdisplay;
1479 int pixel_size = crtc->fb->bits_per_pixel / 8;
1480 unsigned long line_time_us;
1481 int entries;
1482
1483 line_time_us = ((htotal * 1000) / clock);
1484
1485 /* Use ns/us then divide to preserve precision */
1486 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1487 pixel_size * hdisplay;
1488 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1489 srwm = I965_FIFO_SIZE - entries;
1490 if (srwm < 0)
1491 srwm = 1;
1492 srwm &= 0x1ff;
1493 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1494 entries, srwm);
1495
1496 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1497 pixel_size * 64;
1498 entries = DIV_ROUND_UP(entries,
1499 i965_cursor_wm_info.cacheline_size);
1500 cursor_sr = i965_cursor_wm_info.fifo_size -
1501 (entries + i965_cursor_wm_info.guard_size);
1502
1503 if (cursor_sr > i965_cursor_wm_info.max_wm)
1504 cursor_sr = i965_cursor_wm_info.max_wm;
1505
1506 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1507 "cursor %d\n", srwm, cursor_sr);
1508
1509 if (IS_CRESTLINE(dev))
1510 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1511 } else {
1512 /* Turn off self refresh if both pipes are enabled */
1513 if (IS_CRESTLINE(dev))
1514 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1515 & ~FW_BLC_SELF_EN);
1516 }
1517
1518 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1519 srwm);
1520
1521 /* 965 has limitations... */
1522 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1523 (8 << 16) | (8 << 8) | (8 << 0));
1524 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1525 /* update cursor SR watermark */
1526 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1527}
1528
1fa61106 1529static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1530{
1531 struct drm_i915_private *dev_priv = dev->dev_private;
1532 const struct intel_watermark_params *wm_info;
1533 uint32_t fwater_lo;
1534 uint32_t fwater_hi;
1535 int cwm, srwm = 1;
1536 int fifo_size;
1537 int planea_wm, planeb_wm;
1538 struct drm_crtc *crtc, *enabled = NULL;
1539
1540 if (IS_I945GM(dev))
1541 wm_info = &i945_wm_info;
1542 else if (!IS_GEN2(dev))
1543 wm_info = &i915_wm_info;
1544 else
1545 wm_info = &i855_wm_info;
1546
1547 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1548 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1549 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1550 int cpp = crtc->fb->bits_per_pixel / 8;
1551 if (IS_GEN2(dev))
1552 cpp = 4;
1553
b445e3b0 1554 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1555 wm_info, fifo_size, cpp,
b445e3b0
ED		 1556 latency_ns);
1557 enabled = crtc;
1558 } else
1559 planea_wm = fifo_size - wm_info->guard_size;
1560
1561 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1562 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1563 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1564 int cpp = crtc->fb->bits_per_pixel / 8;
1565 if (IS_GEN2(dev))
1566 cpp = 4;
1567
b445e3b0 1568 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1569 wm_info, fifo_size, cpp,
b445e3b0
ED		 1570 latency_ns);
1571 if (enabled == NULL)
1572 enabled = crtc;
1573 else
1574 enabled = NULL;
1575 } else
1576 planeb_wm = fifo_size - wm_info->guard_size;
1577
1578 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1579
1580 /*
1581 * Overlay gets an aggressive default since video jitter is bad.
1582 */
1583 cwm = 2;
1584
1585 /* Play safe and disable self-refresh before adjusting watermarks. */
1586 if (IS_I945G(dev) || IS_I945GM(dev))
1587 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1588 else if (IS_I915GM(dev))
1589 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1590
1591 /* Calc sr entries for one plane configs */
1592 if (HAS_FW_BLC(dev) && enabled) {
1593 /* self-refresh has much higher latency */
1594 static const int sr_latency_ns = 6000;
1595 int clock = enabled->mode.clock;
1596 int htotal = enabled->mode.htotal;
1597 int hdisplay = enabled->mode.hdisplay;
1598 int pixel_size = enabled->fb->bits_per_pixel / 8;
1599 unsigned long line_time_us;
1600 int entries;
1601
1602 line_time_us = (htotal * 1000) / clock;
1603
1604 /* Use ns/us then divide to preserve precision */
1605 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1606 pixel_size * hdisplay;
1607 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1608 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1609 srwm = wm_info->fifo_size - entries;
1610 if (srwm < 0)
1611 srwm = 1;
1612
1613 if (IS_I945G(dev) || IS_I945GM(dev))
1614 I915_WRITE(FW_BLC_SELF,
1615 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1616 else if (IS_I915GM(dev))
1617 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1618 }
1619
1620 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1621 planea_wm, planeb_wm, cwm, srwm);
1622
1623 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1624 fwater_hi = (cwm & 0x1f);
1625
1626 /* Set request length to 8 cachelines per fetch */
1627 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1628 fwater_hi = fwater_hi | (1 << 8);
1629
1630 I915_WRITE(FW_BLC, fwater_lo);
1631 I915_WRITE(FW_BLC2, fwater_hi);
1632
1633 if (HAS_FW_BLC(dev)) {
1634 if (enabled) {
1635 if (IS_I945G(dev) || IS_I945GM(dev))
1636 I915_WRITE(FW_BLC_SELF,
1637 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1638 else if (IS_I915GM(dev))
1639 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1640 DRM_DEBUG_KMS("memory self refresh enabled\n");
1641 } else
1642 DRM_DEBUG_KMS("memory self refresh disabled\n");
1643 }
1644}
1645
1fa61106 1646static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1647{
1648 struct drm_i915_private *dev_priv = dev->dev_private;
1649 struct drm_crtc *crtc;
1650 uint32_t fwater_lo;
1651 int planea_wm;
1652
1653 crtc = single_enabled_crtc(dev);
1654 if (crtc == NULL)
1655 return;
1656
1657 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1658 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1659 4, latency_ns);
b445e3b0
ED		 1660 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1661 fwater_lo |= (3<<8) | planea_wm;
1662
1663 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1664
1665 I915_WRITE(FW_BLC, fwater_lo);
1666}
1667
1668#define ILK_LP0_PLANE_LATENCY 700
1669#define ILK_LP0_CURSOR_LATENCY 1300
1670
1671/*
1672 * Check the wm result.
1673 *
1674 * If any calculated watermark values is larger than the maximum value that
1675 * can be programmed into the associated watermark register, that watermark
1676 * must be disabled.
1677 */
1678static bool ironlake_check_srwm(struct drm_device *dev, int level,
1679 int fbc_wm, int display_wm, int cursor_wm,
1680 const struct intel_watermark_params *display,
1681 const struct intel_watermark_params *cursor)
1682{
1683 struct drm_i915_private *dev_priv = dev->dev_private;
1684
1685 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1686 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1687
1688 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1689 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1690 fbc_wm, SNB_FBC_MAX_SRWM, level);
1691
1692 /* fbc has it's own way to disable FBC WM */
1693 I915_WRITE(DISP_ARB_CTL,
1694 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1695 return false;
615aaa5f
VS		 1696 } else if (INTEL_INFO(dev)->gen >= 6) {
1697 /* enable FBC WM (except on ILK, where it must remain off) */
1698 I915_WRITE(DISP_ARB_CTL,
1699 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1700 }
1701
1702 if (display_wm > display->max_wm) {
1703 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1704 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1705 return false;
1706 }
1707
1708 if (cursor_wm > cursor->max_wm) {
1709 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1710 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1711 return false;
1712 }
1713
1714 if (!(fbc_wm || display_wm || cursor_wm)) {
1715 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1716 return false;
1717 }
1718
1719 return true;
1720}
1721
1722/*
1723 * Compute watermark values of WM[1-3],
1724 */
1725static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1726 int latency_ns,
1727 const struct intel_watermark_params *display,
1728 const struct intel_watermark_params *cursor,
1729 int *fbc_wm, int *display_wm, int *cursor_wm)
1730{
1731 struct drm_crtc *crtc;
1732 unsigned long line_time_us;
1733 int hdisplay, htotal, pixel_size, clock;
1734 int line_count, line_size;
1735 int small, large;
1736 int entries;
1737
1738 if (!latency_ns) {
1739 *fbc_wm = *display_wm = *cursor_wm = 0;
1740 return false;
1741 }
1742
1743 crtc = intel_get_crtc_for_plane(dev, plane);
1744 hdisplay = crtc->mode.hdisplay;
1745 htotal = crtc->mode.htotal;
1746 clock = crtc->mode.clock;
1747 pixel_size = crtc->fb->bits_per_pixel / 8;
1748
1749 line_time_us = (htotal * 1000) / clock;
1750 line_count = (latency_ns / line_time_us + 1000) / 1000;
1751 line_size = hdisplay * pixel_size;
1752
1753 /* Use the minimum of the small and large buffer method for primary */
1754 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1755 large = line_count * line_size;
1756
1757 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1758 *display_wm = entries + display->guard_size;
1759
1760 /*
1761 * Spec says:
1762 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1763 */
1764 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1765
1766 /* calculate the self-refresh watermark for display cursor */
1767 entries = line_count * pixel_size * 64;
1768 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1769 *cursor_wm = entries + cursor->guard_size;
1770
1771 return ironlake_check_srwm(dev, level,
1772 *fbc_wm, *display_wm, *cursor_wm,
1773 display, cursor);
1774}
1775
1fa61106 1776static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1777{
1778 struct drm_i915_private *dev_priv = dev->dev_private;
1779 int fbc_wm, plane_wm, cursor_wm;
1780 unsigned int enabled;
1781
1782 enabled = 0;
51cea1f4 1783 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1784 &ironlake_display_wm_info,
1785 ILK_LP0_PLANE_LATENCY,
1786 &ironlake_cursor_wm_info,
1787 ILK_LP0_CURSOR_LATENCY,
1788 &plane_wm, &cursor_wm)) {
1789 I915_WRITE(WM0_PIPEA_ILK,
1790 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1791 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1792 " plane %d, " "cursor: %d\n",
1793 plane_wm, cursor_wm);
51cea1f4 1794 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1795 }
1796
51cea1f4 1797 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1798 &ironlake_display_wm_info,
1799 ILK_LP0_PLANE_LATENCY,
1800 &ironlake_cursor_wm_info,
1801 ILK_LP0_CURSOR_LATENCY,
1802 &plane_wm, &cursor_wm)) {
1803 I915_WRITE(WM0_PIPEB_ILK,
1804 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1805 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1806 " plane %d, cursor: %d\n",
1807 plane_wm, cursor_wm);
51cea1f4 1808 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1809 }
1810
1811 /*
1812 * Calculate and update the self-refresh watermark only when one
1813 * display plane is used.
1814 */
1815 I915_WRITE(WM3_LP_ILK, 0);
1816 I915_WRITE(WM2_LP_ILK, 0);
1817 I915_WRITE(WM1_LP_ILK, 0);
1818
1819 if (!single_plane_enabled(enabled))
1820 return;
1821 enabled = ffs(enabled) - 1;
1822
1823 /* WM1 */
1824 if (!ironlake_compute_srwm(dev, 1, enabled,
1825 ILK_READ_WM1_LATENCY() * 500,
1826 &ironlake_display_srwm_info,
1827 &ironlake_cursor_srwm_info,
1828 &fbc_wm, &plane_wm, &cursor_wm))
1829 return;
1830
1831 I915_WRITE(WM1_LP_ILK,
1832 WM1_LP_SR_EN |
1833 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1834 (fbc_wm << WM1_LP_FBC_SHIFT) |
1835 (plane_wm << WM1_LP_SR_SHIFT) |
1836 cursor_wm);
1837
1838 /* WM2 */
1839 if (!ironlake_compute_srwm(dev, 2, enabled,
1840 ILK_READ_WM2_LATENCY() * 500,
1841 &ironlake_display_srwm_info,
1842 &ironlake_cursor_srwm_info,
1843 &fbc_wm, &plane_wm, &cursor_wm))
1844 return;
1845
1846 I915_WRITE(WM2_LP_ILK,
1847 WM2_LP_EN |
1848 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1849 (fbc_wm << WM1_LP_FBC_SHIFT) |
1850 (plane_wm << WM1_LP_SR_SHIFT) |
1851 cursor_wm);
1852
1853 /*
1854 * WM3 is unsupported on ILK, probably because we don't have latency
1855 * data for that power state
1856 */
1857}
1858
1fa61106 1859static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1860{
1861 struct drm_i915_private *dev_priv = dev->dev_private;
1862 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1863 u32 val;
1864 int fbc_wm, plane_wm, cursor_wm;
1865 unsigned int enabled;
1866
1867 enabled = 0;
51cea1f4 1868 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1869 &sandybridge_display_wm_info, latency,
1870 &sandybridge_cursor_wm_info, latency,
1871 &plane_wm, &cursor_wm)) {
1872 val = I915_READ(WM0_PIPEA_ILK);
1873 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1874 I915_WRITE(WM0_PIPEA_ILK, val |
1875 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1876 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1877 " plane %d, " "cursor: %d\n",
1878 plane_wm, cursor_wm);
51cea1f4 1879 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1880 }
1881
51cea1f4 1882 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1883 &sandybridge_display_wm_info, latency,
1884 &sandybridge_cursor_wm_info, latency,
1885 &plane_wm, &cursor_wm)) {
1886 val = I915_READ(WM0_PIPEB_ILK);
1887 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1888 I915_WRITE(WM0_PIPEB_ILK, val |
1889 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1890 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1891 " plane %d, cursor: %d\n",
1892 plane_wm, cursor_wm);
51cea1f4 1893 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1894 }
1895
c43d0188
CW		 1896 /*
1897 * Calculate and update the self-refresh watermark only when one
1898 * display plane is used.
1899 *
1900 * SNB support 3 levels of watermark.
1901 *
1902 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1903 * and disabled in the descending order
1904 *
1905 */
1906 I915_WRITE(WM3_LP_ILK, 0);
1907 I915_WRITE(WM2_LP_ILK, 0);
1908 I915_WRITE(WM1_LP_ILK, 0);
1909
1910 if (!single_plane_enabled(enabled) ||
1911 dev_priv->sprite_scaling_enabled)
1912 return;
1913 enabled = ffs(enabled) - 1;
1914
1915 /* WM1 */
1916 if (!ironlake_compute_srwm(dev, 1, enabled,
1917 SNB_READ_WM1_LATENCY() * 500,
1918 &sandybridge_display_srwm_info,
1919 &sandybridge_cursor_srwm_info,
1920 &fbc_wm, &plane_wm, &cursor_wm))
1921 return;
1922
1923 I915_WRITE(WM1_LP_ILK,
1924 WM1_LP_SR_EN |
1925 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1926 (fbc_wm << WM1_LP_FBC_SHIFT) |
1927 (plane_wm << WM1_LP_SR_SHIFT) |
1928 cursor_wm);
1929
1930 /* WM2 */
1931 if (!ironlake_compute_srwm(dev, 2, enabled,
1932 SNB_READ_WM2_LATENCY() * 500,
1933 &sandybridge_display_srwm_info,
1934 &sandybridge_cursor_srwm_info,
1935 &fbc_wm, &plane_wm, &cursor_wm))
1936 return;
1937
1938 I915_WRITE(WM2_LP_ILK,
1939 WM2_LP_EN |
1940 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1941 (fbc_wm << WM1_LP_FBC_SHIFT) |
1942 (plane_wm << WM1_LP_SR_SHIFT) |
1943 cursor_wm);
1944
1945 /* WM3 */
1946 if (!ironlake_compute_srwm(dev, 3, enabled,
1947 SNB_READ_WM3_LATENCY() * 500,
1948 &sandybridge_display_srwm_info,
1949 &sandybridge_cursor_srwm_info,
1950 &fbc_wm, &plane_wm, &cursor_wm))
1951 return;
1952
1953 I915_WRITE(WM3_LP_ILK,
1954 WM3_LP_EN |
1955 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1956 (fbc_wm << WM1_LP_FBC_SHIFT) |
1957 (plane_wm << WM1_LP_SR_SHIFT) |
1958 cursor_wm);
1959}
1960
1961static void ivybridge_update_wm(struct drm_device *dev)
1962{
1963 struct drm_i915_private *dev_priv = dev->dev_private;
1964 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1965 u32 val;
1966 int fbc_wm, plane_wm, cursor_wm;
1967 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1968 unsigned int enabled;
1969
1970 enabled = 0;
51cea1f4 1971 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1972 &sandybridge_display_wm_info, latency,
1973 &sandybridge_cursor_wm_info, latency,
1974 &plane_wm, &cursor_wm)) {
1975 val = I915_READ(WM0_PIPEA_ILK);
1976 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1977 I915_WRITE(WM0_PIPEA_ILK, val |
1978 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1979 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1980 " plane %d, " "cursor: %d\n",
1981 plane_wm, cursor_wm);
51cea1f4 1982 enabled |= 1 << PIPE_A;
c43d0188
CW		 1983 }
1984
51cea1f4 1985 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1986 &sandybridge_display_wm_info, latency,
1987 &sandybridge_cursor_wm_info, latency,
1988 &plane_wm, &cursor_wm)) {
1989 val = I915_READ(WM0_PIPEB_ILK);
1990 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1991 I915_WRITE(WM0_PIPEB_ILK, val |
1992 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1993 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1994 " plane %d, cursor: %d\n",
1995 plane_wm, cursor_wm);
51cea1f4 1996 enabled |= 1 << PIPE_B;
c43d0188
CW		 1997 }
1998
51cea1f4 1999 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2000 &sandybridge_display_wm_info, latency,
2001 &sandybridge_cursor_wm_info, latency,
2002 &plane_wm, &cursor_wm)) {
2003 val = I915_READ(WM0_PIPEC_IVB);
2004 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2005 I915_WRITE(WM0_PIPEC_IVB, val |
2006 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2007 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2008 " plane %d, cursor: %d\n",
2009 plane_wm, cursor_wm);
51cea1f4 2010 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2011 }
2012
2013 /*
2014 * Calculate and update the self-refresh watermark only when one
2015 * display plane is used.
2016 *
2017 * SNB support 3 levels of watermark.
2018 *
2019 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2020 * and disabled in the descending order
2021 *
2022 */
2023 I915_WRITE(WM3_LP_ILK, 0);
2024 I915_WRITE(WM2_LP_ILK, 0);
2025 I915_WRITE(WM1_LP_ILK, 0);
2026
2027 if (!single_plane_enabled(enabled) ||
2028 dev_priv->sprite_scaling_enabled)
2029 return;
2030 enabled = ffs(enabled) - 1;
2031
2032 /* WM1 */
2033 if (!ironlake_compute_srwm(dev, 1, enabled,
2034 SNB_READ_WM1_LATENCY() * 500,
2035 &sandybridge_display_srwm_info,
2036 &sandybridge_cursor_srwm_info,
2037 &fbc_wm, &plane_wm, &cursor_wm))
2038 return;
2039
2040 I915_WRITE(WM1_LP_ILK,
2041 WM1_LP_SR_EN |
2042 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2043 (fbc_wm << WM1_LP_FBC_SHIFT) |
2044 (plane_wm << WM1_LP_SR_SHIFT) |
2045 cursor_wm);
2046
2047 /* WM2 */
2048 if (!ironlake_compute_srwm(dev, 2, enabled,
2049 SNB_READ_WM2_LATENCY() * 500,
2050 &sandybridge_display_srwm_info,
2051 &sandybridge_cursor_srwm_info,
2052 &fbc_wm, &plane_wm, &cursor_wm))
2053 return;
2054
2055 I915_WRITE(WM2_LP_ILK,
2056 WM2_LP_EN |
2057 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2058 (fbc_wm << WM1_LP_FBC_SHIFT) |
2059 (plane_wm << WM1_LP_SR_SHIFT) |
2060 cursor_wm);
2061
c43d0188 2062 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2063 if (!ironlake_compute_srwm(dev, 3, enabled,
2064 SNB_READ_WM3_LATENCY() * 500,
2065 &sandybridge_display_srwm_info,
2066 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2067 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2068 !ironlake_compute_srwm(dev, 3, enabled,
2069 2 * SNB_READ_WM3_LATENCY() * 500,
2070 &sandybridge_display_srwm_info,
2071 &sandybridge_cursor_srwm_info,
2072 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2073 return;
2074
2075 I915_WRITE(WM3_LP_ILK,
2076 WM3_LP_EN |
2077 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2078 (fbc_wm << WM1_LP_FBC_SHIFT) |
2079 (plane_wm << WM1_LP_SR_SHIFT) |
2080 cursor_wm);
2081}
2082
801bcfff
PZ		 2083static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2084 struct drm_crtc *crtc)
2085{
2086 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2087 uint32_t pixel_rate, pfit_size;
2088
ff9a6750 2089 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2090
2091 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2092 * adjust the pixel_rate here. */
2093
2094 pfit_size = intel_crtc->config.pch_pfit.size;
2095 if (pfit_size) {
2096 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2097
2098 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2099 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2100 pfit_w = (pfit_size >> 16) & 0xFFFF;
2101 pfit_h = pfit_size & 0xFFFF;
2102 if (pipe_w < pfit_w)
2103 pipe_w = pfit_w;
2104 if (pipe_h < pfit_h)
2105 pipe_h = pfit_h;
2106
2107 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2108 pfit_w * pfit_h);
2109 }
2110
2111 return pixel_rate;
2112}
2113
2114static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2115 uint32_t latency)
2116{
2117 uint64_t ret;
2118
2119 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2120 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2121
2122 return ret;
2123}
2124
2125static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2126 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2127 uint32_t latency)
2128{
2129 uint32_t ret;
2130
2131 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2132 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2133 ret = DIV_ROUND_UP(ret, 64) + 2;
2134 return ret;
2135}
2136
cca32e9a
PZ		 2137static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2138 uint8_t bytes_per_pixel)
2139{
2140 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2141}
2142
801bcfff
PZ		 2143struct hsw_pipe_wm_parameters {
2144 bool active;
2145 bool sprite_enabled;
2146 uint8_t pri_bytes_per_pixel;
2147 uint8_t spr_bytes_per_pixel;
2148 uint8_t cur_bytes_per_pixel;
2149 uint32_t pri_horiz_pixels;
2150 uint32_t spr_horiz_pixels;
2151 uint32_t cur_horiz_pixels;
2152 uint32_t pipe_htotal;
2153 uint32_t pixel_rate;
2154};
2155
cca32e9a
PZ		 2156struct hsw_wm_maximums {
2157 uint16_t pri;
2158 uint16_t spr;
2159 uint16_t cur;
2160 uint16_t fbc;
2161};
2162
2163struct hsw_lp_wm_result {
2164 bool enable;
2165 bool fbc_enable;
2166 uint32_t pri_val;
2167 uint32_t spr_val;
2168 uint32_t cur_val;
2169 uint32_t fbc_val;
2170};
2171
801bcfff
PZ		 2172struct hsw_wm_values {
2173 uint32_t wm_pipe[3];
2174 uint32_t wm_lp[3];
2175 uint32_t wm_lp_spr[3];
2176 uint32_t wm_linetime[3];
cca32e9a 2177 bool enable_fbc_wm;
801bcfff
PZ		 2178};
2179
2180enum hsw_data_buf_partitioning {
2181 HSW_DATA_BUF_PART_1_2,
2182 HSW_DATA_BUF_PART_5_6,
2183};
2184
cca32e9a
PZ		 2185/* For both WM_PIPE and WM_LP. */
2186static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2187 uint32_t mem_value,
2188 bool is_lp)
801bcfff 2189{
cca32e9a
PZ		 2190 uint32_t method1, method2;
2191
801bcfff
PZ		 2192 /* TODO: for now, assume the primary plane is always enabled. */
2193 if (!params->active)
2194 return 0;
2195
cca32e9a
PZ		 2196 method1 = hsw_wm_method1(params->pixel_rate,
2197 params->pri_bytes_per_pixel,
2198 mem_value);
2199
2200 if (!is_lp)
2201 return method1;
2202
2203 method2 = hsw_wm_method2(params->pixel_rate,
2204 params->pipe_htotal,
2205 params->pri_horiz_pixels,
2206 params->pri_bytes_per_pixel,
2207 mem_value);
2208
2209 return min(method1, method2);
801bcfff
PZ		 2210}
2211
2212/* For both WM_PIPE and WM_LP. */
2213static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2214 uint32_t mem_value)
2215{
2216 uint32_t method1, method2;
2217
2218 if (!params->active || !params->sprite_enabled)
2219 return 0;
2220
2221 method1 = hsw_wm_method1(params->pixel_rate,
2222 params->spr_bytes_per_pixel,
2223 mem_value);
2224 method2 = hsw_wm_method2(params->pixel_rate,
2225 params->pipe_htotal,
2226 params->spr_horiz_pixels,
2227 params->spr_bytes_per_pixel,
2228 mem_value);
2229 return min(method1, method2);
2230}
2231
2232/* For both WM_PIPE and WM_LP. */
2233static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2234 uint32_t mem_value)
2235{
2236 if (!params->active)
2237 return 0;
2238
2239 return hsw_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->cur_horiz_pixels,
2242 params->cur_bytes_per_pixel,
2243 mem_value);
2244}
2245
cca32e9a
PZ		 2246/* Only for WM_LP. */
2247static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2248 uint32_t pri_val,
2249 uint32_t mem_value)
2250{
2251 if (!params->active)
2252 return 0;
2253
2254 return hsw_wm_fbc(pri_val,
2255 params->pri_horiz_pixels,
2256 params->pri_bytes_per_pixel);
2257}
2258
2259static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2260 struct hsw_pipe_wm_parameters *params,
2261 struct hsw_lp_wm_result *result)
2262{
2263 enum pipe pipe;
2264 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2265
2266 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2267 struct hsw_pipe_wm_parameters *p = &params[pipe];
2268
2269 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2270 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2271 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2272 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2273 }
2274
2275 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2276 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2277 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2278 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2279
2280 if (result->fbc_val > max->fbc) {
2281 result->fbc_enable = false;
2282 result->fbc_val = 0;
2283 } else {
2284 result->fbc_enable = true;
2285 }
2286
2287 result->enable = result->pri_val <= max->pri &&
2288 result->spr_val <= max->spr &&
2289 result->cur_val <= max->cur;
2290 return result->enable;
2291}
2292
801bcfff
PZ		 2293static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2294 uint32_t mem_value, enum pipe pipe,
2295 struct hsw_pipe_wm_parameters *params)
2296{
2297 uint32_t pri_val, cur_val, spr_val;
2298
cca32e9a 2299 pri_val = hsw_compute_pri_wm(params, mem_value, false);
801bcfff
PZ		 2300 spr_val = hsw_compute_spr_wm(params, mem_value);
2301 cur_val = hsw_compute_cur_wm(params, mem_value);
2302
2303 WARN(pri_val > 127,
2304 "Primary WM error, mode not supported for pipe %c\n",
2305 pipe_name(pipe));
2306 WARN(spr_val > 127,
2307 "Sprite WM error, mode not supported for pipe %c\n",
2308 pipe_name(pipe));
2309 WARN(cur_val > 63,
2310 "Cursor WM error, mode not supported for pipe %c\n",
2311 pipe_name(pipe));
2312
2313 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2314 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2315 cur_val;
2316}
2317
2318static uint32_t
2319hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2320{
2321 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2322 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2323 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2324 u32 linetime, ips_linetime;
1f8eeabf 2325
801bcfff
PZ		 2326 if (!intel_crtc_active(crtc))
2327 return 0;
1011d8c4 2328
1f8eeabf
ED		 2329 /* The WM are computed with base on how long it takes to fill a single
2330 * row at the given clock rate, multiplied by 8.
2331 * */
85a02deb
PZ		 2332 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2333 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2334 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2335
801bcfff
PZ		 2336 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2337 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2338}
2339
801bcfff
PZ		 2340static void hsw_compute_wm_parameters(struct drm_device *dev,
2341 struct hsw_pipe_wm_parameters *params,
cca32e9a 2342 uint32_t *wm,
861f3389
PZ		 2343 struct hsw_wm_maximums *lp_max_1_2,
2344 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4
PZ		 2345{
2346 struct drm_i915_private *dev_priv = dev->dev_private;
2347 struct drm_crtc *crtc;
801bcfff
PZ		 2348 struct drm_plane *plane;
2349 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4 2350 enum pipe pipe;
cca32e9a 2351 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2352
801bcfff
PZ		 2353 if ((sskpd >> 56) & 0xFF)
2354 wm[0] = (sskpd >> 56) & 0xFF;
2355 else
2356 wm[0] = sskpd & 0xF;
2357 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2358 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2359 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2360 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2361
2362 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2363 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2364 struct hsw_pipe_wm_parameters *p;
2365
2366 pipe = intel_crtc->pipe;
2367 p = &params[pipe];
2368
2369 p->active = intel_crtc_active(crtc);
2370 if (!p->active)
2371 continue;
2372
cca32e9a
PZ		 2373 pipes_active++;
2374
801bcfff
PZ		 2375 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2376 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2377 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2378 p->cur_bytes_per_pixel = 4;
2379 p->pri_horiz_pixels =
2380 intel_crtc->config.requested_mode.hdisplay;
2381 p->cur_horiz_pixels = 64;
2382 }
2383
2384 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2385 struct intel_plane *intel_plane = to_intel_plane(plane);
2386 struct hsw_pipe_wm_parameters *p;
2387
2388 pipe = intel_plane->pipe;
2389 p = &params[pipe];
2390
2391 p->sprite_enabled = intel_plane->wm.enable;
2392 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2393 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2394
2395 if (p->sprite_enabled)
2396 sprites_enabled++;
2397 }
2398
2399 if (pipes_active > 1) {
861f3389
PZ		 2400 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2401 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2402 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2403 } else {
2404 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2405 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2406 lp_max_1_2->spr = 384;
861f3389
PZ		 2407 lp_max_5_6->spr = 640;
2408 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2409 }
861f3389 2410 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2411}
2412
2413static void hsw_compute_wm_results(struct drm_device *dev,
2414 struct hsw_pipe_wm_parameters *params,
2415 uint32_t *wm,
cca32e9a 2416 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2417 struct hsw_wm_values *results)
2418{
2419 struct drm_i915_private *dev_priv = dev->dev_private;
2420 struct drm_crtc *crtc;
cca32e9a 2421 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2422 enum pipe pipe;
cca32e9a
PZ		 2423 int level, max_level, wm_lp;
2424
2425 for (level = 1; level <= 4; level++)
2426 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2427 &lp_results[level - 1]))
2428 break;
2429 max_level = level - 1;
2430
2431 /* The spec says it is preferred to disable FBC WMs instead of disabling
2432 * a WM level. */
2433 results->enable_fbc_wm = true;
2434 for (level = 1; level <= max_level; level++) {
2435 if (!lp_results[level - 1].fbc_enable) {
2436 results->enable_fbc_wm = false;
2437 break;
2438 }
2439 }
2440
2441 memset(results, 0, sizeof(*results));
2442 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2443 const struct hsw_lp_wm_result *r;
801bcfff 2444
cca32e9a
PZ		 2445 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2446 if (level > max_level)
2447 break;
2448
2449 r = &lp_results[level - 1];
2450 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2451 r->fbc_val,
2452 r->pri_val,
2453 r->cur_val);
2454 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2455 }
801bcfff
PZ		 2456
2457 for_each_pipe(pipe)
2458 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2459 pipe,
2460 &params[pipe]);
1011d8c4
PZ		 2461
2462 for_each_pipe(pipe) {
2463 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2464 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2465 }
2466}
2467
861f3389
PZ		 2468/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2469 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2470static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2471 struct hsw_wm_values *r2)
861f3389
PZ		 2472{
2473 int i, val_r1 = 0, val_r2 = 0;
2474
2475 for (i = 0; i < 3; i++) {
2476 if (r1->wm_lp[i] & WM3_LP_EN)
2477 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2478 if (r2->wm_lp[i] & WM3_LP_EN)
2479 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2480 }
2481
2482 if (val_r1 == val_r2) {
2483 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2484 return r2;
2485 else
2486 return r1;
2487 } else if (val_r1 > val_r2) {
2488 return r1;
2489 } else {
2490 return r2;
2491 }
2492}
2493
801bcfff
PZ		 2494/*
2495 * The spec says we shouldn't write when we don't need, because every write
2496 * causes WMs to be re-evaluated, expending some power.
2497 */
2498static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2499 struct hsw_wm_values *results,
2500 enum hsw_data_buf_partitioning partitioning)
2501{
2502 struct hsw_wm_values previous;
2503 uint32_t val;
2504 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2505 bool prev_enable_fbc_wm;
801bcfff
PZ		 2506
2507 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2508 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2509 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2510 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2511 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2512 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2513 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2514 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2515 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2516 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2517 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2518 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2519
2520 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2521 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2522
cca32e9a
PZ		 2523 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2524
801bcfff
PZ		 2525 if (memcmp(results->wm_pipe, previous.wm_pipe,
2526 sizeof(results->wm_pipe)) == 0 &&
2527 memcmp(results->wm_lp, previous.wm_lp,
2528 sizeof(results->wm_lp)) == 0 &&
2529 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2530 sizeof(results->wm_lp_spr)) == 0 &&
2531 memcmp(results->wm_linetime, previous.wm_linetime,
2532 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2533 partitioning == prev_partitioning &&
2534 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2535 return;
2536
2537 if (previous.wm_lp[2] != 0)
2538 I915_WRITE(WM3_LP_ILK, 0);
2539 if (previous.wm_lp[1] != 0)
2540 I915_WRITE(WM2_LP_ILK, 0);
2541 if (previous.wm_lp[0] != 0)
2542 I915_WRITE(WM1_LP_ILK, 0);
2543
2544 if (previous.wm_pipe[0] != results->wm_pipe[0])
2545 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2546 if (previous.wm_pipe[1] != results->wm_pipe[1])
2547 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2548 if (previous.wm_pipe[2] != results->wm_pipe[2])
2549 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2550
2551 if (previous.wm_linetime[0] != results->wm_linetime[0])
2552 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2553 if (previous.wm_linetime[1] != results->wm_linetime[1])
2554 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2555 if (previous.wm_linetime[2] != results->wm_linetime[2])
2556 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2557
2558 if (prev_partitioning != partitioning) {
2559 val = I915_READ(WM_MISC);
2560 if (partitioning == HSW_DATA_BUF_PART_1_2)
2561 val &= ~WM_MISC_DATA_PARTITION_5_6;
2562 else
2563 val |= WM_MISC_DATA_PARTITION_5_6;
2564 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2565 }
2566
cca32e9a
PZ		 2567 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2568 val = I915_READ(DISP_ARB_CTL);
2569 if (results->enable_fbc_wm)
2570 val &= ~DISP_FBC_WM_DIS;
2571 else
2572 val |= DISP_FBC_WM_DIS;
2573 I915_WRITE(DISP_ARB_CTL, val);
2574 }
2575
801bcfff
PZ		 2576 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2577 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2578 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2579 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2580 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2581 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2582
2583 if (results->wm_lp[0] != 0)
2584 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2585 if (results->wm_lp[1] != 0)
2586 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2587 if (results->wm_lp[2] != 0)
2588 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2589}
2590
2591static void haswell_update_wm(struct drm_device *dev)
2592{
2593 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2594 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2595 struct hsw_pipe_wm_parameters params[3];
861f3389 2596 struct hsw_wm_values results_1_2, results_5_6, *best_results;
801bcfff 2597 uint32_t wm[5];
861f3389
PZ		 2598 enum hsw_data_buf_partitioning partitioning;
2599
2600 hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
2601
2602 hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
2603 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2604 hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
2605 &results_5_6);
2606 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2607 } else {
2608 best_results = &results_1_2;
2609 }
2610
2611 partitioning = (best_results == &results_1_2) ?
2612 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2613
861f3389 2614 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2615}
2616
526682e9
PZ		 2617static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2618 uint32_t sprite_width, int pixel_size,
2619 bool enable)
2620{
2621 struct drm_plane *plane;
2622
2623 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2624 struct intel_plane *intel_plane = to_intel_plane(plane);
2625
2626 if (intel_plane->pipe == pipe) {
2627 intel_plane->wm.enable = enable;
2628 intel_plane->wm.horiz_pixels = sprite_width + 1;
2629 intel_plane->wm.bytes_per_pixel = pixel_size;
2630 break;
2631 }
2632 }
2633
2634 haswell_update_wm(dev);
2635}
2636
b445e3b0
ED		 2637static bool
2638sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2639 uint32_t sprite_width, int pixel_size,
2640 const struct intel_watermark_params *display,
2641 int display_latency_ns, int *sprite_wm)
2642{
2643 struct drm_crtc *crtc;
2644 int clock;
2645 int entries, tlb_miss;
2646
2647 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2648 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2649 *sprite_wm = display->guard_size;
2650 return false;
2651 }
2652
2653 clock = crtc->mode.clock;
2654
2655 /* Use the small buffer method to calculate the sprite watermark */
2656 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2657 tlb_miss = display->fifo_size*display->cacheline_size -
2658 sprite_width * 8;
2659 if (tlb_miss > 0)
2660 entries += tlb_miss;
2661 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2662 *sprite_wm = entries + display->guard_size;
2663 if (*sprite_wm > (int)display->max_wm)
2664 *sprite_wm = display->max_wm;
2665
2666 return true;
2667}
2668
2669static bool
2670sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2671 uint32_t sprite_width, int pixel_size,
2672 const struct intel_watermark_params *display,
2673 int latency_ns, int *sprite_wm)
2674{
2675 struct drm_crtc *crtc;
2676 unsigned long line_time_us;
2677 int clock;
2678 int line_count, line_size;
2679 int small, large;
2680 int entries;
2681
2682 if (!latency_ns) {
2683 *sprite_wm = 0;
2684 return false;
2685 }
2686
2687 crtc = intel_get_crtc_for_plane(dev, plane);
2688 clock = crtc->mode.clock;
2689 if (!clock) {
2690 *sprite_wm = 0;
2691 return false;
2692 }
2693
2694 line_time_us = (sprite_width * 1000) / clock;
2695 if (!line_time_us) {
2696 *sprite_wm = 0;
2697 return false;
2698 }
2699
2700 line_count = (latency_ns / line_time_us + 1000) / 1000;
2701 line_size = sprite_width * pixel_size;
2702
2703 /* Use the minimum of the small and large buffer method for primary */
2704 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2705 large = line_count * line_size;
2706
2707 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2708 *sprite_wm = entries + display->guard_size;
2709
2710 return *sprite_wm > 0x3ff ? false : true;
2711}
2712
1fa61106 2713static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2714 uint32_t sprite_width, int pixel_size,
2715 bool enable)
b445e3b0
ED		 2716{
2717 struct drm_i915_private *dev_priv = dev->dev_private;
2718 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2719 u32 val;
2720 int sprite_wm, reg;
2721 int ret;
2722
4c4ff43a
PZ		 2723 if (!enable)
2724 return;
2725
b445e3b0
ED		 2726 switch (pipe) {
2727 case 0:
2728 reg = WM0_PIPEA_ILK;
2729 break;
2730 case 1:
2731 reg = WM0_PIPEB_ILK;
2732 break;
2733 case 2:
2734 reg = WM0_PIPEC_IVB;
2735 break;
2736 default:
2737 return; /* bad pipe */
2738 }
2739
2740 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2741 &sandybridge_display_wm_info,
2742 latency, &sprite_wm);
2743 if (!ret) {
84f44ce7
VS		 2744 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2745 pipe_name(pipe));
b445e3b0
ED		 2746 return;
2747 }
2748
2749 val = I915_READ(reg);
2750 val &= ~WM0_PIPE_SPRITE_MASK;
2751 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2752 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2753
2754
2755 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2756 pixel_size,
2757 &sandybridge_display_srwm_info,
2758 SNB_READ_WM1_LATENCY() * 500,
2759 &sprite_wm);
2760 if (!ret) {
84f44ce7
VS		 2761 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2762 pipe_name(pipe));
b445e3b0
ED		 2763 return;
2764 }
2765 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2766
2767 /* Only IVB has two more LP watermarks for sprite */
2768 if (!IS_IVYBRIDGE(dev))
2769 return;
2770
2771 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2772 pixel_size,
2773 &sandybridge_display_srwm_info,
2774 SNB_READ_WM2_LATENCY() * 500,
2775 &sprite_wm);
2776 if (!ret) {
84f44ce7
VS		 2777 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2778 pipe_name(pipe));
b445e3b0
ED		 2779 return;
2780 }
2781 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2782
2783 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2784 pixel_size,
2785 &sandybridge_display_srwm_info,
2786 SNB_READ_WM3_LATENCY() * 500,
2787 &sprite_wm);
2788 if (!ret) {
84f44ce7
VS		 2789 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2790 pipe_name(pipe));
b445e3b0
ED		 2791 return;
2792 }
2793 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2794}
2795
2796/**
2797 * intel_update_watermarks - update FIFO watermark values based on current modes
2798 *
2799 * Calculate watermark values for the various WM regs based on current mode
2800 * and plane configuration.
2801 *
2802 * There are several cases to deal with here:
2803 * - normal (i.e. non-self-refresh)
2804 * - self-refresh (SR) mode
2805 * - lines are large relative to FIFO size (buffer can hold up to 2)
2806 * - lines are small relative to FIFO size (buffer can hold more than 2
2807 * lines), so need to account for TLB latency
2808 *
2809 * The normal calculation is:
2810 * watermark = dotclock * bytes per pixel * latency
2811 * where latency is platform & configuration dependent (we assume pessimal
2812 * values here).
2813 *
2814 * The SR calculation is:
2815 * watermark = (trunc(latency/line time)+1) * surface width *
2816 * bytes per pixel
2817 * where
2818 * line time = htotal / dotclock
2819 * surface width = hdisplay for normal plane and 64 for cursor
2820 * and latency is assumed to be high, as above.
2821 *
2822 * The final value programmed to the register should always be rounded up,
2823 * and include an extra 2 entries to account for clock crossings.
2824 *
2825 * We don't use the sprite, so we can ignore that. And on Crestline we have
2826 * to set the non-SR watermarks to 8.
2827 */
2828void intel_update_watermarks(struct drm_device *dev)
2829{
2830 struct drm_i915_private *dev_priv = dev->dev_private;
2831
2832 if (dev_priv->display.update_wm)
2833 dev_priv->display.update_wm(dev);
2834}
2835
2836void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2837 uint32_t sprite_width, int pixel_size,
2838 bool enable)
b445e3b0
ED		 2839{
2840 struct drm_i915_private *dev_priv = dev->dev_private;
2841
2842 if (dev_priv->display.update_sprite_wm)
2843 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2844 pixel_size, enable);
b445e3b0
ED		 2845}
2846
2b4e57bd
ED		 2847static struct drm_i915_gem_object *
2848intel_alloc_context_page(struct drm_device *dev)
2849{
2850 struct drm_i915_gem_object *ctx;
2851 int ret;
2852
2853 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2854
2855 ctx = i915_gem_alloc_object(dev, 4096);
2856 if (!ctx) {
2857 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2858 return NULL;
2859 }
2860
86a1ee26 2861 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2862 if (ret) {
2863 DRM_ERROR("failed to pin power context: %d\n", ret);
2864 goto err_unref;
2865 }
2866
2867 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2868 if (ret) {
2869 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2870 goto err_unpin;
2871 }
2872
2873 return ctx;
2874
2875err_unpin:
2876 i915_gem_object_unpin(ctx);
2877err_unref:
2878 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2879 return NULL;
2880}
2881
9270388e
DV		 2882/**
2883 * Lock protecting IPS related data structures
9270388e
DV		 2884 */
2885DEFINE_SPINLOCK(mchdev_lock);
2886
2887/* Global for IPS driver to get at the current i915 device. Protected by
2888 * mchdev_lock. */
2889static struct drm_i915_private *i915_mch_dev;
2890
2b4e57bd
ED		 2891bool ironlake_set_drps(struct drm_device *dev, u8 val)
2892{
2893 struct drm_i915_private *dev_priv = dev->dev_private;
2894 u16 rgvswctl;
2895
9270388e
DV		 2896 assert_spin_locked(&mchdev_lock);
2897
2b4e57bd
ED		 2898 rgvswctl = I915_READ16(MEMSWCTL);
2899 if (rgvswctl & MEMCTL_CMD_STS) {
2900 DRM_DEBUG("gpu busy, RCS change rejected\n");
2901 return false; /* still busy with another command */
2902 }
2903
2904 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2905 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2906 I915_WRITE16(MEMSWCTL, rgvswctl);
2907 POSTING_READ16(MEMSWCTL);
2908
2909 rgvswctl |= MEMCTL_CMD_STS;
2910 I915_WRITE16(MEMSWCTL, rgvswctl);
2911
2912 return true;
2913}
2914
8090c6b9 2915static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2916{
2917 struct drm_i915_private *dev_priv = dev->dev_private;
2918 u32 rgvmodectl = I915_READ(MEMMODECTL);
2919 u8 fmax, fmin, fstart, vstart;
2920
9270388e
DV		 2921 spin_lock_irq(&mchdev_lock);
2922
2b4e57bd
ED		 2923 /* Enable temp reporting */
2924 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2925 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2926
2927 /* 100ms RC evaluation intervals */
2928 I915_WRITE(RCUPEI, 100000);
2929 I915_WRITE(RCDNEI, 100000);
2930
2931 /* Set max/min thresholds to 90ms and 80ms respectively */
2932 I915_WRITE(RCBMAXAVG, 90000);
2933 I915_WRITE(RCBMINAVG, 80000);
2934
2935 I915_WRITE(MEMIHYST, 1);
2936
2937 /* Set up min, max, and cur for interrupt handling */
2938 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2939 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2940 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2941 MEMMODE_FSTART_SHIFT;
2942
2943 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2944 PXVFREQ_PX_SHIFT;
2945
20e4d407
DV		 2946 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2947 dev_priv->ips.fstart = fstart;
2b4e57bd 2948
20e4d407
DV		 2949 dev_priv->ips.max_delay = fstart;
2950 dev_priv->ips.min_delay = fmin;
2951 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2952
2953 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2954 fmax, fmin, fstart);
2955
2956 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2957
2958 /*
2959 * Interrupts will be enabled in ironlake_irq_postinstall
2960 */
2961
2962 I915_WRITE(VIDSTART, vstart);
2963 POSTING_READ(VIDSTART);
2964
2965 rgvmodectl |= MEMMODE_SWMODE_EN;
2966 I915_WRITE(MEMMODECTL, rgvmodectl);
2967
9270388e 2968 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2969 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2970 mdelay(1);
2b4e57bd
ED		 2971
2972 ironlake_set_drps(dev, fstart);
2973
20e4d407 2974 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2975 I915_READ(0x112e0);
20e4d407
DV		 2976 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2977 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2978 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2979
2980 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2981}
2982
8090c6b9 2983static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2984{
2985 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2986 u16 rgvswctl;
2987
2988 spin_lock_irq(&mchdev_lock);
2989
2990 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2991
2992 /* Ack interrupts, disable EFC interrupt */
2993 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2994 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2995 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2996 I915_WRITE(DEIIR, DE_PCU_EVENT);
2997 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2998
2999 /* Go back to the starting frequency */
20e4d407 3000 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3001 mdelay(1);
2b4e57bd
ED		 3002 rgvswctl |= MEMCTL_CMD_STS;
3003 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3004 mdelay(1);
2b4e57bd 3005
9270388e 3006 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3007}
3008
acbe9475
DV		 3009/* There's a funny hw issue where the hw returns all 0 when reading from
3010 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3011 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3012 * all limits and the gpu stuck at whatever frequency it is at atm).
3013 */
65bccb5c 3014static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3015{
7b9e0ae6 3016 u32 limits;
2b4e57bd 3017
7b9e0ae6 3018 limits = 0;
c6a828d3
DV		 3019
3020 if (*val >= dev_priv->rps.max_delay)
3021 *val = dev_priv->rps.max_delay;
3022 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3023
3024 /* Only set the down limit when we've reached the lowest level to avoid
3025 * getting more interrupts, otherwise leave this clear. This prevents a
3026 * race in the hw when coming out of rc6: There's a tiny window where
3027 * the hw runs at the minimal clock before selecting the desired
3028 * frequency, if the down threshold expires in that window we will not
3029 * receive a down interrupt. */
c6a828d3
DV		 3030 if (*val <= dev_priv->rps.min_delay) {
3031 *val = dev_priv->rps.min_delay;
3032 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3033 }
3034
3035 return limits;
3036}
3037
3038void gen6_set_rps(struct drm_device *dev, u8 val)
3039{
3040 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3041 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3042
4fc688ce 3043 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3044 WARN_ON(val > dev_priv->rps.max_delay);
3045 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3046
c6a828d3 3047 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3048 return;
3049
92bd1bf0
RV		 3050 if (IS_HASWELL(dev))
3051 I915_WRITE(GEN6_RPNSWREQ,
3052 HSW_FREQUENCY(val));
3053 else
3054 I915_WRITE(GEN6_RPNSWREQ,
3055 GEN6_FREQUENCY(val) |
3056 GEN6_OFFSET(0) |
3057 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3058
3059 /* Make sure we continue to get interrupts
3060 * until we hit the minimum or maximum frequencies.
3061 */
3062 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3063
d5570a72
BW		 3064 POSTING_READ(GEN6_RPNSWREQ);
3065
c6a828d3 3066 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3067
3068 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3069}
3070
80814ae4
VS		 3071/*
3072 * Wait until the previous freq change has completed,
3073 * or the timeout elapsed, and then update our notion
3074 * of the current GPU frequency.
3075 */
3076static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3077{
80814ae4
VS		 3078 u32 pval;
3079
3080 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3081
e8474409
VS		 3082 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3083 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3084
3085 pval >>= 8;
3086
3087 if (pval != dev_priv->rps.cur_delay)
3088 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3089 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3090 dev_priv->rps.cur_delay,
3091 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3092
3093 dev_priv->rps.cur_delay = pval;
3094}
3095
0a073b84
JB		 3096void valleyview_set_rps(struct drm_device *dev, u8 val)
3097{
3098 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3099
3100 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3101
3102 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3103 WARN_ON(val > dev_priv->rps.max_delay);
3104 WARN_ON(val < dev_priv->rps.min_delay);
3105
80814ae4
VS		 3106 vlv_update_rps_cur_delay(dev_priv);
3107
73008b98 3108 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3109 vlv_gpu_freq(dev_priv->mem_freq,
3110 dev_priv->rps.cur_delay),
73008b98
VS		 3111 dev_priv->rps.cur_delay,
3112 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3113
3114 if (val == dev_priv->rps.cur_delay)
3115 return;
3116
ae99258f 3117 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3118
80814ae4 3119 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3120
3121 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3122}
3123
44fc7d5c 3124static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3125{
3126 struct drm_i915_private *dev_priv = dev->dev_private;
3127
2b4e57bd 3128 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3129 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3130 /* Complete PM interrupt masking here doesn't race with the rps work
3131 * item again unmasking PM interrupts because that is using a different
3132 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3133 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3134
59cdb63d 3135 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3136 dev_priv->rps.pm_iir = 0;
59cdb63d 3137 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3138
4848405c 3139 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3140}
3141
44fc7d5c 3142static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3143{
3144 struct drm_i915_private *dev_priv = dev->dev_private;
3145
3146 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3147 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3148
44fc7d5c
DV		 3149 gen6_disable_rps_interrupts(dev);
3150}
3151
3152static void valleyview_disable_rps(struct drm_device *dev)
3153{
3154 struct drm_i915_private *dev_priv = dev->dev_private;
3155
3156 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3157
44fc7d5c 3158 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3159
3160 if (dev_priv->vlv_pctx) {
3161 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3162 dev_priv->vlv_pctx = NULL;
3163 }
d20d4f0c
JB		 3164}
3165
2b4e57bd
ED		 3166int intel_enable_rc6(const struct drm_device *dev)
3167{
eb4926e4
DL		 3168 /* No RC6 before Ironlake */
3169 if (INTEL_INFO(dev)->gen < 5)
3170 return 0;
3171
456470eb 3172 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3173 if (i915_enable_rc6 >= 0)
3174 return i915_enable_rc6;
3175
6567d748
CW		 3176 /* Disable RC6 on Ironlake */
3177 if (INTEL_INFO(dev)->gen == 5)
3178 return 0;
2b4e57bd 3179
456470eb
DV		 3180 if (IS_HASWELL(dev)) {
3181 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3182 return INTEL_RC6_ENABLE;
456470eb 3183 }
2b4e57bd 3184
456470eb 3185 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3186 if (INTEL_INFO(dev)->gen == 6) {
3187 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3188 return INTEL_RC6_ENABLE;
3189 }
456470eb 3190
2b4e57bd
ED		 3191 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3192 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3193}
3194
44fc7d5c
DV		 3195static void gen6_enable_rps_interrupts(struct drm_device *dev)
3196{
3197 struct drm_i915_private *dev_priv = dev->dev_private;
3198
3199 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3200 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3201 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3202 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3203 spin_unlock_irq(&dev_priv->irq_lock);
3204 /* unmask all PM interrupts */
3205 I915_WRITE(GEN6_PMINTRMSK, 0);
3206}
3207
79f5b2c7 3208static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3209{
79f5b2c7 3210 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3211 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3212 u32 rp_state_cap;
3213 u32 gt_perf_status;
31643d54 3214 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3215 u32 gtfifodbg;
2b4e57bd 3216 int rc6_mode;
42c0526c 3217 int i, ret;
2b4e57bd 3218
4fc688ce 3219 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3220
2b4e57bd
ED		 3221 /* Here begins a magic sequence of register writes to enable
3222 * auto-downclocking.
3223 *
3224 * Perhaps there might be some value in exposing these to
3225 * userspace...
3226 */
3227 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3228
3229 /* Clear the DBG now so we don't confuse earlier errors */
3230 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3231 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3232 I915_WRITE(GTFIFODBG, gtfifodbg);
3233 }
3234
3235 gen6_gt_force_wake_get(dev_priv);
3236
7b9e0ae6
CW		 3237 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3238 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3239
31c77388
BW		 3240 /* In units of 50MHz */
3241 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3242 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3243 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3244
2b4e57bd
ED		 3245 /* disable the counters and set deterministic thresholds */
3246 I915_WRITE(GEN6_RC_CONTROL, 0);
3247
3248 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3249 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3250 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3251 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3252 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3253
b4519513
CW		 3254 for_each_ring(ring, dev_priv, i)
3255 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3256
3257 I915_WRITE(GEN6_RC_SLEEP, 0);
3258 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3259 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3260 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3261 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3262
5a7dc92a 3263 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3264 rc6_mode = intel_enable_rc6(dev_priv->dev);
3265 if (rc6_mode & INTEL_RC6_ENABLE)
3266 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3267
5a7dc92a
ED		 3268 /* We don't use those on Haswell */
3269 if (!IS_HASWELL(dev)) {
3270 if (rc6_mode & INTEL_RC6p_ENABLE)
3271 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3272
5a7dc92a
ED		 3273 if (rc6_mode & INTEL_RC6pp_ENABLE)
3274 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3275 }
2b4e57bd
ED		 3276
3277 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3278 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3279 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3280 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3281
3282 I915_WRITE(GEN6_RC_CONTROL,
3283 rc6_mask |
3284 GEN6_RC_CTL_EI_MODE(1) |
3285 GEN6_RC_CTL_HW_ENABLE);
3286
92bd1bf0
RV		 3287 if (IS_HASWELL(dev)) {
3288 I915_WRITE(GEN6_RPNSWREQ,
3289 HSW_FREQUENCY(10));
3290 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3291 HSW_FREQUENCY(12));
3292 } else {
3293 I915_WRITE(GEN6_RPNSWREQ,
3294 GEN6_FREQUENCY(10) |
3295 GEN6_OFFSET(0) |
3296 GEN6_AGGRESSIVE_TURBO);
3297 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3298 GEN6_FREQUENCY(12));
3299 }
2b4e57bd
ED		 3300
3301 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3302 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3303 dev_priv->rps.max_delay << 24 |
3304 dev_priv->rps.min_delay << 16);
5a7dc92a 3305
1ee9ae32
DV		 3306 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3307 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3308 I915_WRITE(GEN6_RP_UP_EI, 66000);
3309 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3310
2b4e57bd
ED		 3311 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3312 I915_WRITE(GEN6_RP_CONTROL,
3313 GEN6_RP_MEDIA_TURBO |
89ba829e 3314 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3315 GEN6_RP_MEDIA_IS_GFX |
3316 GEN6_RP_ENABLE |
3317 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3318 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3319
42c0526c 3320 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3321 if (!ret) {
42c0526c
BW		 3322 pcu_mbox = 0;
3323 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3324 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3325 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3326 (dev_priv->rps.max_delay & 0xff) * 50,
3327 (pcu_mbox & 0xff) * 50);
31c77388 3328 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3329 }
3330 } else {
3331 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3332 }
3333
7b9e0ae6 3334 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3335
44fc7d5c 3336 gen6_enable_rps_interrupts(dev);
2b4e57bd 3337
31643d54
BW		 3338 rc6vids = 0;
3339 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3340 if (IS_GEN6(dev) && ret) {
3341 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3342 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3343 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3344 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3345 rc6vids &= 0xffff00;
3346 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3347 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3348 if (ret)
3349 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3350 }
3351
2b4e57bd 3352 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3353}
3354
79f5b2c7 3355static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3356{
79f5b2c7 3357 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3358 int min_freq = 15;
3ebecd07
CW		 3359 unsigned int gpu_freq;
3360 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3361 int scaling_factor = 180;
3362
4fc688ce 3363 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3364
2b4e57bd
ED		 3365 max_ia_freq = cpufreq_quick_get_max(0);
3366 /*
3367 * Default to measured freq if none found, PCU will ensure we don't go
3368 * over
3369 */
3370 if (!max_ia_freq)
3371 max_ia_freq = tsc_khz;
3372
3373 /* Convert from kHz to MHz */
3374 max_ia_freq /= 1000;
3375
3ebecd07
CW		 3376 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3377 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3378 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3379
2b4e57bd
ED		 3380 /*
3381 * For each potential GPU frequency, load a ring frequency we'd like
3382 * to use for memory access. We do this by specifying the IA frequency
3383 * the PCU should use as a reference to determine the ring frequency.
3384 */
c6a828d3 3385 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3386 gpu_freq--) {
c6a828d3 3387 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3388 unsigned int ia_freq = 0, ring_freq = 0;
3389
3390 if (IS_HASWELL(dev)) {
3391 ring_freq = (gpu_freq * 5 + 3) / 4;
3392 ring_freq = max(min_ring_freq, ring_freq);
3393 /* leave ia_freq as the default, chosen by cpufreq */
3394 } else {
3395 /* On older processors, there is no separate ring
3396 * clock domain, so in order to boost the bandwidth
3397 * of the ring, we need to upclock the CPU (ia_freq).
3398 *
3399 * For GPU frequencies less than 750MHz,
3400 * just use the lowest ring freq.
3401 */
3402 if (gpu_freq < min_freq)
3403 ia_freq = 800;
3404 else
3405 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3406 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3407 }
2b4e57bd 3408
42c0526c
BW		 3409 sandybridge_pcode_write(dev_priv,
3410 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3411 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3412 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3413 gpu_freq);
2b4e57bd 3414 }
2b4e57bd
ED		 3415}
3416
0a073b84
JB		 3417int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3418{
3419 u32 val, rp0;
3420
64936258 3421 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3422
3423 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3424 /* Clamp to max */
3425 rp0 = min_t(u32, rp0, 0xea);
3426
3427 return rp0;
3428}
3429
3430static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3431{
3432 u32 val, rpe;
3433
64936258 3434 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3435 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3436 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3437 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3438
3439 return rpe;
3440}
3441
3442int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3443{
64936258 3444 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3445}
3446
52ceb908
JB		 3447static void vlv_rps_timer_work(struct work_struct *work)
3448{
3449 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3450 rps.vlv_work.work);
3451
3452 /*
3453 * Timer fired, we must be idle. Drop to min voltage state.
3454 * Note: we use RPe here since it should match the
3455 * Vmin we were shooting for. That should give us better
3456 * perf when we come back out of RC6 than if we used the
3457 * min freq available.
3458 */
3459 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3460 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3461 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3462 mutex_unlock(&dev_priv->rps.hw_lock);
3463}
3464
c9cddffc
JB		 3465static void valleyview_setup_pctx(struct drm_device *dev)
3466{
3467 struct drm_i915_private *dev_priv = dev->dev_private;
3468 struct drm_i915_gem_object *pctx;
3469 unsigned long pctx_paddr;
3470 u32 pcbr;
3471 int pctx_size = 24*1024;
3472
3473 pcbr = I915_READ(VLV_PCBR);
3474 if (pcbr) {
3475 /* BIOS set it up already, grab the pre-alloc'd space */
3476 int pcbr_offset;
3477
3478 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3479 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3480 pcbr_offset,
190d6cd5 3481 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3482 pctx_size);
3483 goto out;
3484 }
3485
3486 /*
3487 * From the Gunit register HAS:
3488 * The Gfx driver is expected to program this register and ensure
3489 * proper allocation within Gfx stolen memory. For example, this
3490 * register should be programmed such than the PCBR range does not
3491 * overlap with other ranges, such as the frame buffer, protected
3492 * memory, or any other relevant ranges.
3493 */
3494 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3495 if (!pctx) {
3496 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3497 return;
3498 }
3499
3500 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3501 I915_WRITE(VLV_PCBR, pctx_paddr);
3502
3503out:
3504 dev_priv->vlv_pctx = pctx;
3505}
3506
0a073b84
JB		 3507static void valleyview_enable_rps(struct drm_device *dev)
3508{
3509 struct drm_i915_private *dev_priv = dev->dev_private;
3510 struct intel_ring_buffer *ring;
73008b98 3511 u32 gtfifodbg, val;
0a073b84
JB		 3512 int i;
3513
3514 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3515
3516 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3517 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3518 I915_WRITE(GTFIFODBG, gtfifodbg);
3519 }
3520
c9cddffc
JB		 3521 valleyview_setup_pctx(dev);
3522
0a073b84
JB		 3523 gen6_gt_force_wake_get(dev_priv);
3524
3525 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3526 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3527 I915_WRITE(GEN6_RP_UP_EI, 66000);
3528 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3529
3530 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3531
3532 I915_WRITE(GEN6_RP_CONTROL,
3533 GEN6_RP_MEDIA_TURBO |
3534 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3535 GEN6_RP_MEDIA_IS_GFX |
3536 GEN6_RP_ENABLE |
3537 GEN6_RP_UP_BUSY_AVG |
3538 GEN6_RP_DOWN_IDLE_CONT);
3539
3540 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3541 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3542 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3543
3544 for_each_ring(ring, dev_priv, i)
3545 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3546
3547 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3548
3549 /* allows RC6 residency counter to work */
3550 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3551 I915_WRITE(GEN6_RC_CONTROL,
3552 GEN7_RC_CTL_TO_MODE);
3553
64936258 3554 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3555 switch ((val >> 6) & 3) {
3556 case 0:
3557 case 1:
3558 dev_priv->mem_freq = 800;
3559 break;
3560 case 2:
3561 dev_priv->mem_freq = 1066;
3562 break;
3563 case 3:
3564 dev_priv->mem_freq = 1333;
3565 break;
3566 }
0a073b84
JB		 3567 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3568
3569 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3570 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3571
0a073b84 3572 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3573 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3574 vlv_gpu_freq(dev_priv->mem_freq,
3575 dev_priv->rps.cur_delay),
3576 dev_priv->rps.cur_delay);
0a073b84
JB		 3577
3578 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3579 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3580 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3581 vlv_gpu_freq(dev_priv->mem_freq,
3582 dev_priv->rps.max_delay),
3583 dev_priv->rps.max_delay);
0a073b84 3584
73008b98
VS		 3585 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3586 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3587 vlv_gpu_freq(dev_priv->mem_freq,
3588 dev_priv->rps.rpe_delay),
3589 dev_priv->rps.rpe_delay);
0a073b84 3590
73008b98
VS		 3591 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3592 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3593 vlv_gpu_freq(dev_priv->mem_freq,
3594 dev_priv->rps.min_delay),
3595 dev_priv->rps.min_delay);
0a073b84 3596
73008b98
VS		 3597 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3598 vlv_gpu_freq(dev_priv->mem_freq,
3599 dev_priv->rps.rpe_delay),
3600 dev_priv->rps.rpe_delay);
0a073b84 3601
52ceb908
JB		 3602 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3603
73008b98 3604 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3605
44fc7d5c 3606 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3607
3608 gen6_gt_force_wake_put(dev_priv);
3609}
3610
930ebb46 3611void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3612{
3613 struct drm_i915_private *dev_priv = dev->dev_private;
3614
3e373948
DV		 3615 if (dev_priv->ips.renderctx) {
3616 i915_gem_object_unpin(dev_priv->ips.renderctx);
3617 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3618 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3619 }
3620
3e373948
DV		 3621 if (dev_priv->ips.pwrctx) {
3622 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3623 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3624 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3625 }
3626}
3627
930ebb46 3628static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3629{
3630 struct drm_i915_private *dev_priv = dev->dev_private;
3631
3632 if (I915_READ(PWRCTXA)) {
3633 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3634 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3635 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3636 50);
3637
3638 I915_WRITE(PWRCTXA, 0);
3639 POSTING_READ(PWRCTXA);
3640
3641 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3642 POSTING_READ(RSTDBYCTL);
3643 }
2b4e57bd
ED		 3644}
3645
3646static int ironlake_setup_rc6(struct drm_device *dev)
3647{
3648 struct drm_i915_private *dev_priv = dev->dev_private;
3649
3e373948
DV		 3650 if (dev_priv->ips.renderctx == NULL)
3651 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3652 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3653 return -ENOMEM;
3654
3e373948
DV		 3655 if (dev_priv->ips.pwrctx == NULL)
3656 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3657 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3658 ironlake_teardown_rc6(dev);
3659 return -ENOMEM;
3660 }
3661
3662 return 0;
3663}
3664
930ebb46 3665static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3666{
3667 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3668 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3669 bool was_interruptible;
2b4e57bd
ED		 3670 int ret;
3671
3672 /* rc6 disabled by default due to repeated reports of hanging during
3673 * boot and resume.
3674 */
3675 if (!intel_enable_rc6(dev))
3676 return;
3677
79f5b2c7
DV		 3678 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3679
2b4e57bd 3680 ret = ironlake_setup_rc6(dev);
79f5b2c7 3681 if (ret)
2b4e57bd 3682 return;
2b4e57bd 3683
3e960501
CW		 3684 was_interruptible = dev_priv->mm.interruptible;
3685 dev_priv->mm.interruptible = false;
3686
2b4e57bd
ED		 3687 /*
3688 * GPU can automatically power down the render unit if given a page
3689 * to save state.
3690 */
6d90c952 3691 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3692 if (ret) {
3693 ironlake_teardown_rc6(dev);
3e960501 3694 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3695 return;
3696 }
3697
6d90c952
DV		 3698 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3699 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3700 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3701 MI_MM_SPACE_GTT |
3702 MI_SAVE_EXT_STATE_EN |
3703 MI_RESTORE_EXT_STATE_EN |
3704 MI_RESTORE_INHIBIT);
3705 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3706 intel_ring_emit(ring, MI_NOOP);
3707 intel_ring_emit(ring, MI_FLUSH);
3708 intel_ring_advance(ring);
2b4e57bd
ED		 3709
3710 /*
3711 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3712 * does an implicit flush, combined with MI_FLUSH above, it should be
3713 * safe to assume that renderctx is valid
3714 */
3e960501
CW		 3715 ret = intel_ring_idle(ring);
3716 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3717 if (ret) {
def27a58 3718 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3719 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3720 return;
3721 }
3722
f343c5f6 3723 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3724 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3725}
3726
dde18883
ED		 3727static unsigned long intel_pxfreq(u32 vidfreq)
3728{
3729 unsigned long freq;
3730 int div = (vidfreq & 0x3f0000) >> 16;
3731 int post = (vidfreq & 0x3000) >> 12;
3732 int pre = (vidfreq & 0x7);
3733
3734 if (!pre)
3735 return 0;
3736
3737 freq = ((div * 133333) / ((1<<post) * pre));
3738
3739 return freq;
3740}
3741
eb48eb00
DV		 3742static const struct cparams {
3743 u16 i;
3744 u16 t;
3745 u16 m;
3746 u16 c;
3747} cparams[] = {
3748 { 1, 1333, 301, 28664 },
3749 { 1, 1066, 294, 24460 },
3750 { 1, 800, 294, 25192 },
3751 { 0, 1333, 276, 27605 },
3752 { 0, 1066, 276, 27605 },
3753 { 0, 800, 231, 23784 },
3754};
3755
f531dcb2 3756static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3757{
3758 u64 total_count, diff, ret;
3759 u32 count1, count2, count3, m = 0, c = 0;
3760 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3761 int i;
3762
02d71956
DV		 3763 assert_spin_locked(&mchdev_lock);
3764
20e4d407 3765 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3766
3767 /* Prevent division-by-zero if we are asking too fast.
3768 * Also, we don't get interesting results if we are polling
3769 * faster than once in 10ms, so just return the saved value
3770 * in such cases.
3771 */
3772 if (diff1 <= 10)
20e4d407 3773 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3774
3775 count1 = I915_READ(DMIEC);
3776 count2 = I915_READ(DDREC);
3777 count3 = I915_READ(CSIEC);
3778
3779 total_count = count1 + count2 + count3;
3780
3781 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3782 if (total_count < dev_priv->ips.last_count1) {
3783 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3784 diff += total_count;
3785 } else {
20e4d407 3786 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3787 }
3788
3789 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3790 if (cparams[i].i == dev_priv->ips.c_m &&
3791 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3792 m = cparams[i].m;
3793 c = cparams[i].c;
3794 break;
3795 }
3796 }
3797
3798 diff = div_u64(diff, diff1);
3799 ret = ((m * diff) + c);
3800 ret = div_u64(ret, 10);
3801
20e4d407
DV		 3802 dev_priv->ips.last_count1 = total_count;
3803 dev_priv->ips.last_time1 = now;
eb48eb00 3804
20e4d407 3805 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3806
3807 return ret;
3808}
3809
f531dcb2
CW		 3810unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3811{
3812 unsigned long val;
3813
3814 if (dev_priv->info->gen != 5)
3815 return 0;
3816
3817 spin_lock_irq(&mchdev_lock);
3818
3819 val = __i915_chipset_val(dev_priv);
3820
3821 spin_unlock_irq(&mchdev_lock);
3822
3823 return val;
3824}
3825
eb48eb00
DV		 3826unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3827{
3828 unsigned long m, x, b;
3829 u32 tsfs;
3830
3831 tsfs = I915_READ(TSFS);
3832
3833 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3834 x = I915_READ8(TR1);
3835
3836 b = tsfs & TSFS_INTR_MASK;
3837
3838 return ((m * x) / 127) - b;
3839}
3840
3841static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3842{
3843 static const struct v_table {
3844 u16 vd; /* in .1 mil */
3845 u16 vm; /* in .1 mil */
3846 } v_table[] = {
3847 { 0, 0, },
3848 { 375, 0, },
3849 { 500, 0, },
3850 { 625, 0, },
3851 { 750, 0, },
3852 { 875, 0, },
3853 { 1000, 0, },
3854 { 1125, 0, },
3855 { 4125, 3000, },
3856 { 4125, 3000, },
3857 { 4125, 3000, },
3858 { 4125, 3000, },
3859 { 4125, 3000, },
3860 { 4125, 3000, },
3861 { 4125, 3000, },
3862 { 4125, 3000, },
3863 { 4125, 3000, },
3864 { 4125, 3000, },
3865 { 4125, 3000, },
3866 { 4125, 3000, },
3867 { 4125, 3000, },
3868 { 4125, 3000, },
3869 { 4125, 3000, },
3870 { 4125, 3000, },
3871 { 4125, 3000, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4125, 3000, },
3878 { 4125, 3000, },
3879 { 4250, 3125, },
3880 { 4375, 3250, },
3881 { 4500, 3375, },
3882 { 4625, 3500, },
3883 { 4750, 3625, },
3884 { 4875, 3750, },
3885 { 5000, 3875, },
3886 { 5125, 4000, },
3887 { 5250, 4125, },
3888 { 5375, 4250, },
3889 { 5500, 4375, },
3890 { 5625, 4500, },
3891 { 5750, 4625, },
3892 { 5875, 4750, },
3893 { 6000, 4875, },
3894 { 6125, 5000, },
3895 { 6250, 5125, },
3896 { 6375, 5250, },
3897 { 6500, 5375, },
3898 { 6625, 5500, },
3899 { 6750, 5625, },
3900 { 6875, 5750, },
3901 { 7000, 5875, },
3902 { 7125, 6000, },
3903 { 7250, 6125, },
3904 { 7375, 6250, },
3905 { 7500, 6375, },
3906 { 7625, 6500, },
3907 { 7750, 6625, },
3908 { 7875, 6750, },
3909 { 8000, 6875, },
3910 { 8125, 7000, },
3911 { 8250, 7125, },
3912 { 8375, 7250, },
3913 { 8500, 7375, },
3914 { 8625, 7500, },
3915 { 8750, 7625, },
3916 { 8875, 7750, },
3917 { 9000, 7875, },
3918 { 9125, 8000, },
3919 { 9250, 8125, },
3920 { 9375, 8250, },
3921 { 9500, 8375, },
3922 { 9625, 8500, },
3923 { 9750, 8625, },
3924 { 9875, 8750, },
3925 { 10000, 8875, },
3926 { 10125, 9000, },
3927 { 10250, 9125, },
3928 { 10375, 9250, },
3929 { 10500, 9375, },
3930 { 10625, 9500, },
3931 { 10750, 9625, },
3932 { 10875, 9750, },
3933 { 11000, 9875, },
3934 { 11125, 10000, },
3935 { 11250, 10125, },
3936 { 11375, 10250, },
3937 { 11500, 10375, },
3938 { 11625, 10500, },
3939 { 11750, 10625, },
3940 { 11875, 10750, },
3941 { 12000, 10875, },
3942 { 12125, 11000, },
3943 { 12250, 11125, },
3944 { 12375, 11250, },
3945 { 12500, 11375, },
3946 { 12625, 11500, },
3947 { 12750, 11625, },
3948 { 12875, 11750, },
3949 { 13000, 11875, },
3950 { 13125, 12000, },
3951 { 13250, 12125, },
3952 { 13375, 12250, },
3953 { 13500, 12375, },
3954 { 13625, 12500, },
3955 { 13750, 12625, },
3956 { 13875, 12750, },
3957 { 14000, 12875, },
3958 { 14125, 13000, },
3959 { 14250, 13125, },
3960 { 14375, 13250, },
3961 { 14500, 13375, },
3962 { 14625, 13500, },
3963 { 14750, 13625, },
3964 { 14875, 13750, },
3965 { 15000, 13875, },
3966 { 15125, 14000, },
3967 { 15250, 14125, },
3968 { 15375, 14250, },
3969 { 15500, 14375, },
3970 { 15625, 14500, },
3971 { 15750, 14625, },
3972 { 15875, 14750, },
3973 { 16000, 14875, },
3974 { 16125, 15000, },
3975 };
3976 if (dev_priv->info->is_mobile)
3977 return v_table[pxvid].vm;
3978 else
3979 return v_table[pxvid].vd;
3980}
3981
02d71956 3982static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3983{
3984 struct timespec now, diff1;
3985 u64 diff;
3986 unsigned long diffms;
3987 u32 count;
3988
02d71956 3989 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3990
3991 getrawmonotonic(&now);
20e4d407 3992 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3993
3994 /* Don't divide by 0 */
3995 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3996 if (!diffms)
3997 return;
3998
3999 count = I915_READ(GFXEC);
4000
20e4d407
DV		 4001 if (count < dev_priv->ips.last_count2) {
4002 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4003 diff += count;
4004 } else {
20e4d407 4005 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4006 }
4007
20e4d407
DV		 4008 dev_priv->ips.last_count2 = count;
4009 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4010
4011 /* More magic constants... */
4012 diff = diff * 1181;
4013 diff = div_u64(diff, diffms * 10);
20e4d407 4014 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4015}
4016
02d71956
DV		 4017void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4018{
4019 if (dev_priv->info->gen != 5)
4020 return;
4021
9270388e 4022 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4023
4024 __i915_update_gfx_val(dev_priv);
4025
9270388e 4026 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4027}
4028
f531dcb2 4029static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4030{
4031 unsigned long t, corr, state1, corr2, state2;
4032 u32 pxvid, ext_v;
4033
02d71956
DV		 4034 assert_spin_locked(&mchdev_lock);
4035
c6a828d3 4036 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4037 pxvid = (pxvid >> 24) & 0x7f;
4038 ext_v = pvid_to_extvid(dev_priv, pxvid);
4039
4040 state1 = ext_v;
4041
4042 t = i915_mch_val(dev_priv);
4043
4044 /* Revel in the empirically derived constants */
4045
4046 /* Correction factor in 1/100000 units */
4047 if (t > 80)
4048 corr = ((t * 2349) + 135940);
4049 else if (t >= 50)
4050 corr = ((t * 964) + 29317);
4051 else /* < 50 */
4052 corr = ((t * 301) + 1004);
4053
4054 corr = corr * ((150142 * state1) / 10000 - 78642);
4055 corr /= 100000;
20e4d407 4056 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4057
4058 state2 = (corr2 * state1) / 10000;
4059 state2 /= 100; /* convert to mW */
4060
02d71956 4061 __i915_update_gfx_val(dev_priv);
eb48eb00 4062
20e4d407 4063 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4064}
4065
f531dcb2
CW		 4066unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4067{
4068 unsigned long val;
4069
4070 if (dev_priv->info->gen != 5)
4071 return 0;
4072
4073 spin_lock_irq(&mchdev_lock);
4074
4075 val = __i915_gfx_val(dev_priv);
4076
4077 spin_unlock_irq(&mchdev_lock);
4078
4079 return val;
4080}
4081
eb48eb00
DV		 4082/**
4083 * i915_read_mch_val - return value for IPS use
4084 *
4085 * Calculate and return a value for the IPS driver to use when deciding whether
4086 * we have thermal and power headroom to increase CPU or GPU power budget.
4087 */
4088unsigned long i915_read_mch_val(void)
4089{
4090 struct drm_i915_private *dev_priv;
4091 unsigned long chipset_val, graphics_val, ret = 0;
4092
9270388e 4093 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4094 if (!i915_mch_dev)
4095 goto out_unlock;
4096 dev_priv = i915_mch_dev;
4097
f531dcb2
CW		 4098 chipset_val = __i915_chipset_val(dev_priv);
4099 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4100
4101 ret = chipset_val + graphics_val;
4102
4103out_unlock:
9270388e 4104 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4105
4106 return ret;
4107}
4108EXPORT_SYMBOL_GPL(i915_read_mch_val);
4109
4110/**
4111 * i915_gpu_raise - raise GPU frequency limit
4112 *
4113 * Raise the limit; IPS indicates we have thermal headroom.
4114 */
4115bool i915_gpu_raise(void)
4116{
4117 struct drm_i915_private *dev_priv;
4118 bool ret = true;
4119
9270388e 4120 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4121 if (!i915_mch_dev) {
4122 ret = false;
4123 goto out_unlock;
4124 }
4125 dev_priv = i915_mch_dev;
4126
20e4d407
DV		 4127 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4128 dev_priv->ips.max_delay--;
eb48eb00
DV		 4129
4130out_unlock:
9270388e 4131 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4132
4133 return ret;
4134}
4135EXPORT_SYMBOL_GPL(i915_gpu_raise);
4136
4137/**
4138 * i915_gpu_lower - lower GPU frequency limit
4139 *
4140 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4141 * frequency maximum.
4142 */
4143bool i915_gpu_lower(void)
4144{
4145 struct drm_i915_private *dev_priv;
4146 bool ret = true;
4147
9270388e 4148 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4149 if (!i915_mch_dev) {
4150 ret = false;
4151 goto out_unlock;
4152 }
4153 dev_priv = i915_mch_dev;
4154
20e4d407
DV		 4155 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4156 dev_priv->ips.max_delay++;
eb48eb00
DV		 4157
4158out_unlock:
9270388e 4159 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4160
4161 return ret;
4162}
4163EXPORT_SYMBOL_GPL(i915_gpu_lower);
4164
4165/**
4166 * i915_gpu_busy - indicate GPU business to IPS
4167 *
4168 * Tell the IPS driver whether or not the GPU is busy.
4169 */
4170bool i915_gpu_busy(void)
4171{
4172 struct drm_i915_private *dev_priv;
f047e395 4173 struct intel_ring_buffer *ring;
eb48eb00 4174 bool ret = false;
f047e395 4175 int i;
eb48eb00 4176
9270388e 4177 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4178 if (!i915_mch_dev)
4179 goto out_unlock;
4180 dev_priv = i915_mch_dev;
4181
f047e395
CW		 4182 for_each_ring(ring, dev_priv, i)
4183 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4184
4185out_unlock:
9270388e 4186 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4187
4188 return ret;
4189}
4190EXPORT_SYMBOL_GPL(i915_gpu_busy);
4191
4192/**
4193 * i915_gpu_turbo_disable - disable graphics turbo
4194 *
4195 * Disable graphics turbo by resetting the max frequency and setting the
4196 * current frequency to the default.
4197 */
4198bool i915_gpu_turbo_disable(void)
4199{
4200 struct drm_i915_private *dev_priv;
4201 bool ret = true;
4202
9270388e 4203 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4204 if (!i915_mch_dev) {
4205 ret = false;
4206 goto out_unlock;
4207 }
4208 dev_priv = i915_mch_dev;
4209
20e4d407 4210 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4211
20e4d407 4212 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4213 ret = false;
4214
4215out_unlock:
9270388e 4216 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4217
4218 return ret;
4219}
4220EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4221
4222/**
4223 * Tells the intel_ips driver that the i915 driver is now loaded, if
4224 * IPS got loaded first.
4225 *
4226 * This awkward dance is so that neither module has to depend on the
4227 * other in order for IPS to do the appropriate communication of
4228 * GPU turbo limits to i915.
4229 */
4230static void
4231ips_ping_for_i915_load(void)
4232{
4233 void (*link)(void);
4234
4235 link = symbol_get(ips_link_to_i915_driver);
4236 if (link) {
4237 link();
4238 symbol_put(ips_link_to_i915_driver);
4239 }
4240}
4241
4242void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4243{
02d71956
DV		 4244 /* We only register the i915 ips part with intel-ips once everything is
4245 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4246 spin_lock_irq(&mchdev_lock);
eb48eb00 4247 i915_mch_dev = dev_priv;
9270388e 4248 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4249
4250 ips_ping_for_i915_load();
4251}
4252
4253void intel_gpu_ips_teardown(void)
4254{
9270388e 4255 spin_lock_irq(&mchdev_lock);
eb48eb00 4256 i915_mch_dev = NULL;
9270388e 4257 spin_unlock_irq(&mchdev_lock);
eb48eb00 4258}
8090c6b9 4259static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4260{
4261 struct drm_i915_private *dev_priv = dev->dev_private;
4262 u32 lcfuse;
4263 u8 pxw[16];
4264 int i;
4265
4266 /* Disable to program */
4267 I915_WRITE(ECR, 0);
4268 POSTING_READ(ECR);
4269
4270 /* Program energy weights for various events */
4271 I915_WRITE(SDEW, 0x15040d00);
4272 I915_WRITE(CSIEW0, 0x007f0000);
4273 I915_WRITE(CSIEW1, 0x1e220004);
4274 I915_WRITE(CSIEW2, 0x04000004);
4275
4276 for (i = 0; i < 5; i++)
4277 I915_WRITE(PEW + (i * 4), 0);
4278 for (i = 0; i < 3; i++)
4279 I915_WRITE(DEW + (i * 4), 0);
4280
4281 /* Program P-state weights to account for frequency power adjustment */
4282 for (i = 0; i < 16; i++) {
4283 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4284 unsigned long freq = intel_pxfreq(pxvidfreq);
4285 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4286 PXVFREQ_PX_SHIFT;
4287 unsigned long val;
4288
4289 val = vid * vid;
4290 val *= (freq / 1000);
4291 val *= 255;
4292 val /= (127*127*900);
4293 if (val > 0xff)
4294 DRM_ERROR("bad pxval: %ld\n", val);
4295 pxw[i] = val;
4296 }
4297 /* Render standby states get 0 weight */
4298 pxw[14] = 0;
4299 pxw[15] = 0;
4300
4301 for (i = 0; i < 4; i++) {
4302 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4303 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4304 I915_WRITE(PXW + (i * 4), val);
4305 }
4306
4307 /* Adjust magic regs to magic values (more experimental results) */
4308 I915_WRITE(OGW0, 0);
4309 I915_WRITE(OGW1, 0);
4310 I915_WRITE(EG0, 0x00007f00);
4311 I915_WRITE(EG1, 0x0000000e);
4312 I915_WRITE(EG2, 0x000e0000);
4313 I915_WRITE(EG3, 0x68000300);
4314 I915_WRITE(EG4, 0x42000000);
4315 I915_WRITE(EG5, 0x00140031);
4316 I915_WRITE(EG6, 0);
4317 I915_WRITE(EG7, 0);
4318
4319 for (i = 0; i < 8; i++)
4320 I915_WRITE(PXWL + (i * 4), 0);
4321
4322 /* Enable PMON + select events */
4323 I915_WRITE(ECR, 0x80000019);
4324
4325 lcfuse = I915_READ(LCFUSE02);
4326
20e4d407 4327 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4328}
4329
8090c6b9
DV		 4330void intel_disable_gt_powersave(struct drm_device *dev)
4331{
1a01ab3b
JB		 4332 struct drm_i915_private *dev_priv = dev->dev_private;
4333
fd0c0642
DV		 4334 /* Interrupts should be disabled already to avoid re-arming. */
4335 WARN_ON(dev->irq_enabled);
4336
930ebb46 4337 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4338 ironlake_disable_drps(dev);
930ebb46 4339 ironlake_disable_rc6(dev);
0a073b84 4340 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4341 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4342 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4343 if (IS_VALLEYVIEW(dev))
4344 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4345 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4346 if (IS_VALLEYVIEW(dev))
4347 valleyview_disable_rps(dev);
4348 else
4349 gen6_disable_rps(dev);
4fc688ce 4350 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4351 }
8090c6b9
DV		 4352}
4353
1a01ab3b
JB		 4354static void intel_gen6_powersave_work(struct work_struct *work)
4355{
4356 struct drm_i915_private *dev_priv =
4357 container_of(work, struct drm_i915_private,
4358 rps.delayed_resume_work.work);
4359 struct drm_device *dev = dev_priv->dev;
4360
4fc688ce 4361 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4362
4363 if (IS_VALLEYVIEW(dev)) {
4364 valleyview_enable_rps(dev);
4365 } else {
4366 gen6_enable_rps(dev);
4367 gen6_update_ring_freq(dev);
4368 }
4fc688ce 4369 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4370}
4371
8090c6b9
DV		 4372void intel_enable_gt_powersave(struct drm_device *dev)
4373{
1a01ab3b
JB		 4374 struct drm_i915_private *dev_priv = dev->dev_private;
4375
8090c6b9
DV		 4376 if (IS_IRONLAKE_M(dev)) {
4377 ironlake_enable_drps(dev);
4378 ironlake_enable_rc6(dev);
4379 intel_init_emon(dev);
0a073b84 4380 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4381 /*
4382 * PCU communication is slow and this doesn't need to be
4383 * done at any specific time, so do this out of our fast path
4384 * to make resume and init faster.
4385 */
4386 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4387 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4388 }
4389}
4390
3107bd48
DV		 4391static void ibx_init_clock_gating(struct drm_device *dev)
4392{
4393 struct drm_i915_private *dev_priv = dev->dev_private;
4394
4395 /*
4396 * On Ibex Peak and Cougar Point, we need to disable clock
4397 * gating for the panel power sequencer or it will fail to
4398 * start up when no ports are active.
4399 */
4400 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4401}
4402
0e088b8f
VS		 4403static void g4x_disable_trickle_feed(struct drm_device *dev)
4404{
4405 struct drm_i915_private *dev_priv = dev->dev_private;
4406 int pipe;
4407
4408 for_each_pipe(pipe) {
4409 I915_WRITE(DSPCNTR(pipe),
4410 I915_READ(DSPCNTR(pipe)) |
4411 DISPPLANE_TRICKLE_FEED_DISABLE);
4412 intel_flush_display_plane(dev_priv, pipe);
4413 }
4414}
4415
1fa61106 4416static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4417{
4418 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4419 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4420
f1e8fa56
DL		 4421 /*
4422 * Required for FBC
4423 * WaFbcDisableDpfcClockGating:ilk
4424 */
4d47e4f5
DL		 4425 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4426 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4427 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4428
4429 I915_WRITE(PCH_3DCGDIS0,
4430 MARIUNIT_CLOCK_GATE_DISABLE |
4431 SVSMUNIT_CLOCK_GATE_DISABLE);
4432 I915_WRITE(PCH_3DCGDIS1,
4433 VFMUNIT_CLOCK_GATE_DISABLE);
4434
6f1d69b0
ED		 4435 /*
4436 * According to the spec the following bits should be set in
4437 * order to enable memory self-refresh
4438 * The bit 22/21 of 0x42004
4439 * The bit 5 of 0x42020
4440 * The bit 15 of 0x45000
4441 */
4442 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4443 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4444 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4445 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4446 I915_WRITE(DISP_ARB_CTL,
4447 (I915_READ(DISP_ARB_CTL) |
4448 DISP_FBC_WM_DIS));
4449 I915_WRITE(WM3_LP_ILK, 0);
4450 I915_WRITE(WM2_LP_ILK, 0);
4451 I915_WRITE(WM1_LP_ILK, 0);
4452
4453 /*
4454 * Based on the document from hardware guys the following bits
4455 * should be set unconditionally in order to enable FBC.
4456 * The bit 22 of 0x42000
4457 * The bit 22 of 0x42004
4458 * The bit 7,8,9 of 0x42020.
4459 */
4460 if (IS_IRONLAKE_M(dev)) {
4bb35334 4461 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4462 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4463 I915_READ(ILK_DISPLAY_CHICKEN1) |
4464 ILK_FBCQ_DIS);
4465 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4466 I915_READ(ILK_DISPLAY_CHICKEN2) |
4467 ILK_DPARB_GATE);
6f1d69b0
ED		 4468 }
4469
4d47e4f5
DL		 4470 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4471
6f1d69b0
ED		 4472 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4473 I915_READ(ILK_DISPLAY_CHICKEN2) |
4474 ILK_ELPIN_409_SELECT);
4475 I915_WRITE(_3D_CHICKEN2,
4476 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4477 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4478
ecdb4eb7 4479 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4480 I915_WRITE(CACHE_MODE_0,
4481 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4482
0e088b8f 4483 g4x_disable_trickle_feed(dev);
bdad2b2f 4484
3107bd48
DV		 4485 ibx_init_clock_gating(dev);
4486}
4487
4488static void cpt_init_clock_gating(struct drm_device *dev)
4489{
4490 struct drm_i915_private *dev_priv = dev->dev_private;
4491 int pipe;
3f704fa2 4492 uint32_t val;
3107bd48
DV		 4493
4494 /*
4495 * On Ibex Peak and Cougar Point, we need to disable clock
4496 * gating for the panel power sequencer or it will fail to
4497 * start up when no ports are active.
4498 */
4499 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4500 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4501 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4502 /* The below fixes the weird display corruption, a few pixels shifted
4503 * downward, on (only) LVDS of some HP laptops with IVY.
4504 */
3f704fa2 4505 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4506 val = I915_READ(TRANS_CHICKEN2(pipe));
4507 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4508 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4509 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4510 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4511 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4512 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4513 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4514 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4515 }
3107bd48
DV		 4516 /* WADP0ClockGatingDisable */
4517 for_each_pipe(pipe) {
4518 I915_WRITE(TRANS_CHICKEN1(pipe),
4519 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4520 }
6f1d69b0
ED		 4521}
4522
1d7aaa0c
DV		 4523static void gen6_check_mch_setup(struct drm_device *dev)
4524{
4525 struct drm_i915_private *dev_priv = dev->dev_private;
4526 uint32_t tmp;
4527
4528 tmp = I915_READ(MCH_SSKPD);
4529 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4530 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4531 DRM_INFO("This can cause pipe underruns and display issues.\n");
4532 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4533 }
4534}
4535
1fa61106 4536static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4537{
4538 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4539 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4540
231e54f6 4541 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4542
4543 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4544 I915_READ(ILK_DISPLAY_CHICKEN2) |
4545 ILK_ELPIN_409_SELECT);
4546
ecdb4eb7 4547 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4548 I915_WRITE(_3D_CHICKEN,
4549 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4550
ecdb4eb7 4551 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4552 if (IS_SNB_GT1(dev))
4553 I915_WRITE(GEN6_GT_MODE,
4554 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4555
6f1d69b0
ED		 4556 I915_WRITE(WM3_LP_ILK, 0);
4557 I915_WRITE(WM2_LP_ILK, 0);
4558 I915_WRITE(WM1_LP_ILK, 0);
4559
6f1d69b0 4560 I915_WRITE(CACHE_MODE_0,
50743298 4561 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4562
4563 I915_WRITE(GEN6_UCGCTL1,
4564 I915_READ(GEN6_UCGCTL1) |
4565 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4566 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4567
4568 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4569 * gating disable must be set. Failure to set it results in
4570 * flickering pixels due to Z write ordering failures after
4571 * some amount of runtime in the Mesa "fire" demo, and Unigine
4572 * Sanctuary and Tropics, and apparently anything else with
4573 * alpha test or pixel discard.
4574 *
4575 * According to the spec, bit 11 (RCCUNIT) must also be set,
4576 * but we didn't debug actual testcases to find it out.
0f846f81 4577 *
ecdb4eb7
DL		 4578 * Also apply WaDisableVDSUnitClockGating:snb and
4579 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4580 */
4581 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4582 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4583 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4584 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4585
4586 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4587 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4588 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4589
4590 /*
4591 * According to the spec the following bits should be
4592 * set in order to enable memory self-refresh and fbc:
4593 * The bit21 and bit22 of 0x42000
4594 * The bit21 and bit22 of 0x42004
4595 * The bit5 and bit7 of 0x42020
4596 * The bit14 of 0x70180
4597 * The bit14 of 0x71180
4bb35334
DL		 4598 *
4599 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4600 */
4601 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4602 I915_READ(ILK_DISPLAY_CHICKEN1) |
4603 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4604 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4605 I915_READ(ILK_DISPLAY_CHICKEN2) |
4606 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4607 I915_WRITE(ILK_DSPCLK_GATE_D,
4608 I915_READ(ILK_DSPCLK_GATE_D) |
4609 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4610 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4611
ecdb4eb7 4612 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4613 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4614 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4615
0e088b8f 4616 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4617
4618 /* The default value should be 0x200 according to docs, but the two
4619 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4620 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4621 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4622
4623 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4624
4625 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4626}
4627
4628static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4629{
4630 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4631
4632 reg &= ~GEN7_FF_SCHED_MASK;
4633 reg |= GEN7_FF_TS_SCHED_HW;
4634 reg |= GEN7_FF_VS_SCHED_HW;
4635 reg |= GEN7_FF_DS_SCHED_HW;
4636
41c0b3a8
BW		 4637 if (IS_HASWELL(dev_priv->dev))
4638 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4639
6f1d69b0
ED		 4640 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4641}
4642
17a303ec
PZ		 4643static void lpt_init_clock_gating(struct drm_device *dev)
4644{
4645 struct drm_i915_private *dev_priv = dev->dev_private;
4646
4647 /*
4648 * TODO: this bit should only be enabled when really needed, then
4649 * disabled when not needed anymore in order to save power.
4650 */
4651 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4652 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4653 I915_READ(SOUTH_DSPCLK_GATE_D) |
4654 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4655
4656 /* WADPOClockGatingDisable:hsw */
4657 I915_WRITE(_TRANSA_CHICKEN1,
4658 I915_READ(_TRANSA_CHICKEN1) |
4659 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4660}
4661
7d708ee4
ID		 4662static void lpt_suspend_hw(struct drm_device *dev)
4663{
4664 struct drm_i915_private *dev_priv = dev->dev_private;
4665
4666 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4667 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4668
4669 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4670 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4671 }
4672}
4673
cad2a2d7
ED		 4674static void haswell_init_clock_gating(struct drm_device *dev)
4675{
4676 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4677
4678 I915_WRITE(WM3_LP_ILK, 0);
4679 I915_WRITE(WM2_LP_ILK, 0);
4680 I915_WRITE(WM1_LP_ILK, 0);
4681
4682 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4683 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4684 */
4685 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4686
ecdb4eb7 4687 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4688 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4689 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4690
ecdb4eb7 4691 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4692 I915_WRITE(GEN7_L3CNTLREG1,
4693 GEN7_WA_FOR_GEN7_L3_CONTROL);
4694 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4695 GEN7_WA_L3_CHICKEN_MODE);
4696
ecdb4eb7 4697 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4698 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4699 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4700 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4701
0e088b8f 4702 g4x_disable_trickle_feed(dev);
cad2a2d7 4703
ecdb4eb7 4704 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4705 gen7_setup_fixed_func_scheduler(dev_priv);
4706
ecdb4eb7 4707 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4708 I915_WRITE(CACHE_MODE_1,
4709 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4710
ecdb4eb7 4711 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4712 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4713 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4714
ecdb4eb7 4715 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4716 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4717
90a88643
PZ		 4718 /* WaRsPkgCStateDisplayPMReq:hsw */
4719 I915_WRITE(CHICKEN_PAR1_1,
4720 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4721
17a303ec 4722 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4723}
4724
1fa61106 4725static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4726{
4727 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4728 uint32_t snpcr;
6f1d69b0 4729
6f1d69b0
ED		 4730 I915_WRITE(WM3_LP_ILK, 0);
4731 I915_WRITE(WM2_LP_ILK, 0);
4732 I915_WRITE(WM1_LP_ILK, 0);
4733
231e54f6 4734 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4735
ecdb4eb7 4736 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4737 I915_WRITE(_3D_CHICKEN3,
4738 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4739
ecdb4eb7 4740 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4741 I915_WRITE(IVB_CHICKEN3,
4742 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4743 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4744
ecdb4eb7 4745 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4746 if (IS_IVB_GT1(dev))
4747 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4748 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4749 else
4750 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4751 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4752
ecdb4eb7 4753 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4754 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4755 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4756
ecdb4eb7 4757 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4758 I915_WRITE(GEN7_L3CNTLREG1,
4759 GEN7_WA_FOR_GEN7_L3_CONTROL);
4760 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4761 GEN7_WA_L3_CHICKEN_MODE);
4762 if (IS_IVB_GT1(dev))
4763 I915_WRITE(GEN7_ROW_CHICKEN2,
4764 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4765 else
4766 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4767 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4768
6f1d69b0 4769
ecdb4eb7 4770 /* WaForceL3Serialization:ivb */
61939d97
JB		 4771 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4772 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4773
0f846f81
JB		 4774 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4775 * gating disable must be set. Failure to set it results in
4776 * flickering pixels due to Z write ordering failures after
4777 * some amount of runtime in the Mesa "fire" demo, and Unigine
4778 * Sanctuary and Tropics, and apparently anything else with
4779 * alpha test or pixel discard.
4780 *
4781 * According to the spec, bit 11 (RCCUNIT) must also be set,
4782 * but we didn't debug actual testcases to find it out.
4783 *
4784 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4785 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4786 */
4787 I915_WRITE(GEN6_UCGCTL2,
4788 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4789 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4790
ecdb4eb7 4791 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4792 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4793 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4794 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4795
0e088b8f 4796 g4x_disable_trickle_feed(dev);
6f1d69b0 4797
ecdb4eb7 4798 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4799 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4800 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4801
ecdb4eb7 4802 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4803 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4804
ecdb4eb7 4805 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4806 I915_WRITE(CACHE_MODE_1,
4807 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4808
4809 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4810 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4811 snpcr |= GEN6_MBC_SNPCR_MED;
4812 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4813
ab5c608b
BW		 4814 if (!HAS_PCH_NOP(dev))
4815 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4816
4817 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4818}
4819
1fa61106 4820static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4821{
4822 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4823
d7fe0cc0 4824 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4825
ecdb4eb7 4826 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4827 I915_WRITE(_3D_CHICKEN3,
4828 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4829
ecdb4eb7 4830 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4831 I915_WRITE(IVB_CHICKEN3,
4832 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4833 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4834
ecdb4eb7 4835 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4836 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4837 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4838 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4839
ecdb4eb7 4840 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4841 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4842 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4843
ecdb4eb7 4844 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4845 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4846 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4847
ecdb4eb7 4848 /* WaForceL3Serialization:vlv */
61939d97
JB		 4849 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4850 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4851
ecdb4eb7 4852 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4853 I915_WRITE(GEN7_ROW_CHICKEN2,
4854 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4855
ecdb4eb7 4856 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4857 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4858 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4859 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4860
ecdb4eb7 4861 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4862 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4863 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4864
0f846f81
JB		 4865
4866 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4867 * gating disable must be set. Failure to set it results in
4868 * flickering pixels due to Z write ordering failures after
4869 * some amount of runtime in the Mesa "fire" demo, and Unigine
4870 * Sanctuary and Tropics, and apparently anything else with
4871 * alpha test or pixel discard.
4872 *
4873 * According to the spec, bit 11 (RCCUNIT) must also be set,
4874 * but we didn't debug actual testcases to find it out.
4875 *
4876 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4877 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4878 *
ecdb4eb7
DL		 4879 * Also apply WaDisableVDSUnitClockGating:vlv and
4880 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4881 */
4882 I915_WRITE(GEN6_UCGCTL2,
4883 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4884 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4885 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4886 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4887 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4888
e3f33d46
JB		 4889 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4890
e0d8d59b 4891 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4892
6b26c86d
DV		 4893 I915_WRITE(CACHE_MODE_1,
4894 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4895
2d809570 4896 /*
ecdb4eb7 4897 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4898 * Disable clock gating on th GCFG unit to prevent a delay
4899 * in the reporting of vblank events.
4900 */
4e8c84a5
JB		 4901 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4902
4903 /* Conservative clock gating settings for now */
4904 I915_WRITE(0x9400, 0xffffffff);
4905 I915_WRITE(0x9404, 0xffffffff);
4906 I915_WRITE(0x9408, 0xffffffff);
4907 I915_WRITE(0x940c, 0xffffffff);
4908 I915_WRITE(0x9410, 0xffffffff);
4909 I915_WRITE(0x9414, 0xffffffff);
4910 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4911}
4912
1fa61106 4913static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4914{
4915 struct drm_i915_private *dev_priv = dev->dev_private;
4916 uint32_t dspclk_gate;
4917
4918 I915_WRITE(RENCLK_GATE_D1, 0);
4919 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4920 GS_UNIT_CLOCK_GATE_DISABLE |
4921 CL_UNIT_CLOCK_GATE_DISABLE);
4922 I915_WRITE(RAMCLK_GATE_D, 0);
4923 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4924 OVRUNIT_CLOCK_GATE_DISABLE |
4925 OVCUNIT_CLOCK_GATE_DISABLE;
4926 if (IS_GM45(dev))
4927 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4928 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4929
4930 /* WaDisableRenderCachePipelinedFlush */
4931 I915_WRITE(CACHE_MODE_0,
4932 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 4933
0e088b8f 4934 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 4935}
4936
1fa61106 4937static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4938{
4939 struct drm_i915_private *dev_priv = dev->dev_private;
4940
4941 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4942 I915_WRITE(RENCLK_GATE_D2, 0);
4943 I915_WRITE(DSPCLK_GATE_D, 0);
4944 I915_WRITE(RAMCLK_GATE_D, 0);
4945 I915_WRITE16(DEUC, 0);
20f94967
VS		 4946 I915_WRITE(MI_ARB_STATE,
4947 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4948}
4949
1fa61106 4950static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4951{
4952 struct drm_i915_private *dev_priv = dev->dev_private;
4953
4954 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4955 I965_RCC_CLOCK_GATE_DISABLE |
4956 I965_RCPB_CLOCK_GATE_DISABLE |
4957 I965_ISC_CLOCK_GATE_DISABLE |
4958 I965_FBC_CLOCK_GATE_DISABLE);
4959 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 4960 I915_WRITE(MI_ARB_STATE,
4961 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4962}
4963
1fa61106 4964static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4965{
4966 struct drm_i915_private *dev_priv = dev->dev_private;
4967 u32 dstate = I915_READ(D_STATE);
4968
4969 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4970 DSTATE_DOT_CLOCK_GATING;
4971 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4972
4973 if (IS_PINEVIEW(dev))
4974 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4975
4976 /* IIR "flip pending" means done if this bit is set */
4977 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4978}
4979
1fa61106 4980static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4981{
4982 struct drm_i915_private *dev_priv = dev->dev_private;
4983
4984 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4985}
4986
1fa61106 4987static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4988{
4989 struct drm_i915_private *dev_priv = dev->dev_private;
4990
4991 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4992}
4993
6f1d69b0
ED		 4994void intel_init_clock_gating(struct drm_device *dev)
4995{
4996 struct drm_i915_private *dev_priv = dev->dev_private;
4997
4998 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4999}
5000
7d708ee4
ID		 5001void intel_suspend_hw(struct drm_device *dev)
5002{
5003 if (HAS_PCH_LPT(dev))
5004 lpt_suspend_hw(dev);
5005}
5006
15d199ea
PZ		 5007/**
5008 * We should only use the power well if we explicitly asked the hardware to
5009 * enable it, so check if it's enabled and also check if we've requested it to
5010 * be enabled.
5011 */
b97186f0
PZ		 5012bool intel_display_power_enabled(struct drm_device *dev,
5013 enum intel_display_power_domain domain)
15d199ea
PZ		 5014{
5015 struct drm_i915_private *dev_priv = dev->dev_private;
5016
b97186f0
PZ		 5017 if (!HAS_POWER_WELL(dev))
5018 return true;
5019
5020 switch (domain) {
5021 case POWER_DOMAIN_PIPE_A:
5022 case POWER_DOMAIN_TRANSCODER_EDP:
5023 return true;
5024 case POWER_DOMAIN_PIPE_B:
5025 case POWER_DOMAIN_PIPE_C:
5026 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5027 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5028 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5029 case POWER_DOMAIN_TRANSCODER_A:
5030 case POWER_DOMAIN_TRANSCODER_B:
5031 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5032 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5033 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5034 default:
5035 BUG();
5036 }
15d199ea
PZ		 5037}
5038
a38911a3 5039static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5040{
5041 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5042 bool is_enabled, enable_requested;
5043 uint32_t tmp;
d0d3e513 5044
fa42e23c
PZ		 5045 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5046 is_enabled = tmp & HSW_PWR_WELL_STATE;
5047 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5048
fa42e23c
PZ		 5049 if (enable) {
5050 if (!enable_requested)
5051 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5052
fa42e23c
PZ		 5053 if (!is_enabled) {
5054 DRM_DEBUG_KMS("Enabling power well\n");
5055 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5056 HSW_PWR_WELL_STATE), 20))
5057 DRM_ERROR("Timeout enabling power well\n");
5058 }
5059 } else {
5060 if (enable_requested) {
5061 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5062 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5063 }
5064 }
fa42e23c 5065}
d0d3e513 5066
a38911a3
WX		 5067static struct i915_power_well *hsw_pwr;
5068
5069/* Display audio driver power well request */
5070void i915_request_power_well(void)
5071{
5072 if (WARN_ON(!hsw_pwr))
5073 return;
5074
5075 spin_lock_irq(&hsw_pwr->lock);
5076 if (!hsw_pwr->count++ &&
5077 !hsw_pwr->i915_request)
5078 __intel_set_power_well(hsw_pwr->device, true);
5079 spin_unlock_irq(&hsw_pwr->lock);
5080}
5081EXPORT_SYMBOL_GPL(i915_request_power_well);
5082
5083/* Display audio driver power well release */
5084void i915_release_power_well(void)
5085{
5086 if (WARN_ON(!hsw_pwr))
5087 return;
5088
5089 spin_lock_irq(&hsw_pwr->lock);
5090 WARN_ON(!hsw_pwr->count);
5091 if (!--hsw_pwr->count &&
5092 !hsw_pwr->i915_request)
5093 __intel_set_power_well(hsw_pwr->device, false);
5094 spin_unlock_irq(&hsw_pwr->lock);
5095}
5096EXPORT_SYMBOL_GPL(i915_release_power_well);
5097
5098int i915_init_power_well(struct drm_device *dev)
5099{
5100 struct drm_i915_private *dev_priv = dev->dev_private;
5101
5102 hsw_pwr = &dev_priv->power_well;
5103
5104 hsw_pwr->device = dev;
5105 spin_lock_init(&hsw_pwr->lock);
5106 hsw_pwr->count = 0;
5107
5108 return 0;
5109}
5110
5111void i915_remove_power_well(struct drm_device *dev)
5112{
5113 hsw_pwr = NULL;
5114}
5115
5116void intel_set_power_well(struct drm_device *dev, bool enable)
5117{
5118 struct drm_i915_private *dev_priv = dev->dev_private;
5119 struct i915_power_well *power_well = &dev_priv->power_well;
5120
5121 if (!HAS_POWER_WELL(dev))
5122 return;
5123
5124 if (!i915_disable_power_well && !enable)
5125 return;
5126
5127 spin_lock_irq(&power_well->lock);
5128 power_well->i915_request = enable;
5129
5130 /* only reject "disable" power well request */
5131 if (power_well->count && !enable) {
5132 spin_unlock_irq(&power_well->lock);
5133 return;
5134 }
5135
5136 __intel_set_power_well(dev, enable);
5137 spin_unlock_irq(&power_well->lock);
5138}
5139
fa42e23c
PZ		 5140/*
5141 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5142 * when not needed anymore. We have 4 registers that can request the power well
5143 * to be enabled, and it will only be disabled if none of the registers is
5144 * requesting it to be enabled.
d0d3e513 5145 */
fa42e23c 5146void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5147{
5148 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5149
86d52df6 5150 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5151 return;
5152
fa42e23c
PZ		 5153 /* For now, we need the power well to be always enabled. */
5154 intel_set_power_well(dev, true);
d0d3e513 5155
fa42e23c
PZ		 5156 /* We're taking over the BIOS, so clear any requests made by it since
5157 * the driver is in charge now. */
5158 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5159 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5160}
5161
1fa61106
ED		 5162/* Set up chip specific power management-related functions */
5163void intel_init_pm(struct drm_device *dev)
5164{
5165 struct drm_i915_private *dev_priv = dev->dev_private;
5166
5167 if (I915_HAS_FBC(dev)) {
5168 if (HAS_PCH_SPLIT(dev)) {
5169 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5170 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5171 dev_priv->display.enable_fbc =
5172 gen7_enable_fbc;
5173 else
5174 dev_priv->display.enable_fbc =
5175 ironlake_enable_fbc;
1fa61106
ED		 5176 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5177 } else if (IS_GM45(dev)) {
5178 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5179 dev_priv->display.enable_fbc = g4x_enable_fbc;
5180 dev_priv->display.disable_fbc = g4x_disable_fbc;
5181 } else if (IS_CRESTLINE(dev)) {
5182 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5183 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5184 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5185 }
5186 /* 855GM needs testing */
5187 }
5188
c921aba8
DV		 5189 /* For cxsr */
5190 if (IS_PINEVIEW(dev))
5191 i915_pineview_get_mem_freq(dev);
5192 else if (IS_GEN5(dev))
5193 i915_ironlake_get_mem_freq(dev);
5194
1fa61106
ED		 5195 /* For FIFO watermark updates */
5196 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 5197 if (IS_GEN5(dev)) {
5198 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5199 dev_priv->display.update_wm = ironlake_update_wm;
5200 else {
5201 DRM_DEBUG_KMS("Failed to get proper latency. "
5202 "Disable CxSR\n");
5203 dev_priv->display.update_wm = NULL;
5204 }
5205 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5206 } else if (IS_GEN6(dev)) {
5207 if (SNB_READ_WM0_LATENCY()) {
5208 dev_priv->display.update_wm = sandybridge_update_wm;
5209 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5210 } else {
5211 DRM_DEBUG_KMS("Failed to read display plane latency. "
5212 "Disable CxSR\n");
5213 dev_priv->display.update_wm = NULL;
5214 }
5215 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5216 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 5217 if (SNB_READ_WM0_LATENCY()) {
c43d0188 5218 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5219 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5220 } else {
5221 DRM_DEBUG_KMS("Failed to read display plane latency. "
5222 "Disable CxSR\n");
5223 dev_priv->display.update_wm = NULL;
5224 }
5225 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5226 } else if (IS_HASWELL(dev)) {
3e1f7266 5227 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 5228 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5229 dev_priv->display.update_sprite_wm =
5230 haswell_update_sprite_wm;
6b8a5eeb
ED		 5231 } else {
5232 DRM_DEBUG_KMS("Failed to read display plane latency. "
5233 "Disable CxSR\n");
5234 dev_priv->display.update_wm = NULL;
5235 }
cad2a2d7 5236 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5237 } else
5238 dev_priv->display.update_wm = NULL;
5239 } else if (IS_VALLEYVIEW(dev)) {
5240 dev_priv->display.update_wm = valleyview_update_wm;
5241 dev_priv->display.init_clock_gating =
5242 valleyview_init_clock_gating;
1fa61106
ED		 5243 } else if (IS_PINEVIEW(dev)) {
5244 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5245 dev_priv->is_ddr3,
5246 dev_priv->fsb_freq,
5247 dev_priv->mem_freq)) {
5248 DRM_INFO("failed to find known CxSR latency "
5249 "(found ddr%s fsb freq %d, mem freq %d), "
5250 "disabling CxSR\n",
5251 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5252 dev_priv->fsb_freq, dev_priv->mem_freq);
5253 /* Disable CxSR and never update its watermark again */
5254 pineview_disable_cxsr(dev);
5255 dev_priv->display.update_wm = NULL;
5256 } else
5257 dev_priv->display.update_wm = pineview_update_wm;
5258 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5259 } else if (IS_G4X(dev)) {
5260 dev_priv->display.update_wm = g4x_update_wm;
5261 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5262 } else if (IS_GEN4(dev)) {
5263 dev_priv->display.update_wm = i965_update_wm;
5264 if (IS_CRESTLINE(dev))
5265 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5266 else if (IS_BROADWATER(dev))
5267 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5268 } else if (IS_GEN3(dev)) {
5269 dev_priv->display.update_wm = i9xx_update_wm;
5270 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5271 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5272 } else if (IS_I865G(dev)) {
5273 dev_priv->display.update_wm = i830_update_wm;
5274 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5275 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5276 } else if (IS_I85X(dev)) {
5277 dev_priv->display.update_wm = i9xx_update_wm;
5278 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5279 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5280 } else {
5281 dev_priv->display.update_wm = i830_update_wm;
5282 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5283 if (IS_845G(dev))
5284 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5285 else
5286 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5287 }
5288}
5289
42c0526c
BW		 5290int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5291{
4fc688ce 5292 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5293
5294 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5295 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5296 return -EAGAIN;
5297 }
5298
5299 I915_WRITE(GEN6_PCODE_DATA, *val);
5300 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5301
5302 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5303 500)) {
5304 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5305 return -ETIMEDOUT;
5306 }
5307
5308 *val = I915_READ(GEN6_PCODE_DATA);
5309 I915_WRITE(GEN6_PCODE_DATA, 0);
5310
5311 return 0;
5312}
5313
5314int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5315{
4fc688ce 5316 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5317
5318 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5319 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5320 return -EAGAIN;
5321 }
5322
5323 I915_WRITE(GEN6_PCODE_DATA, val);
5324 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5325
5326 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5327 500)) {
5328 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5329 return -ETIMEDOUT;
5330 }
5331
5332 I915_WRITE(GEN6_PCODE_DATA, 0);
5333
5334 return 0;
5335}
a0e4e199 5336
855ba3be
JB		 5337int vlv_gpu_freq(int ddr_freq, int val)
5338{
5339 int mult, base;
5340
5341 switch (ddr_freq) {
5342 case 800:
5343 mult = 20;
5344 base = 120;
5345 break;
5346 case 1066:
5347 mult = 22;
5348 base = 133;
5349 break;
5350 case 1333:
5351 mult = 21;
5352 base = 125;
5353 break;
5354 default:
5355 return -1;
5356 }
5357
5358 return ((val - 0xbd) * mult) + base;
5359}
5360
5361int vlv_freq_opcode(int ddr_freq, int val)
5362{
5363 int mult, base;
5364
5365 switch (ddr_freq) {
5366 case 800:
5367 mult = 20;
5368 base = 120;
5369 break;
5370 case 1066:
5371 mult = 22;
5372 base = 133;
5373 break;
5374 case 1333:
5375 mult = 21;
5376 base = 125;
5377 break;
5378 default:
5379 return -1;
5380 }
5381
5382 val /= mult;
5383 val -= base / mult;
5384 val += 0xbd;
5385
5386 if (val > 0xea)
5387 val = 0xea;
5388
5389 return val;
5390}
5391
907b28c5
CW		 5392void intel_pm_init(struct drm_device *dev)
5393{
5394 struct drm_i915_private *dev_priv = dev->dev_private;
5395
5396 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5397 intel_gen6_powersave_work);
5398}
5399
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