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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
da2078cd DL |
55 | static void gen9_init_clock_gating(struct drm_device *dev) |
56 | { | |
acd5c346 DL |
57 | struct drm_i915_private *dev_priv = dev->dev_private; |
58 | ||
77719d28 DL |
59 | /* WaEnableLbsSlaRetryTimerDecrement:skl */ |
60 | I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) | | |
61 | GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE); | |
62 | } | |
91e41d16 | 63 | |
45db2194 | 64 | static void skl_init_clock_gating(struct drm_device *dev) |
da2078cd | 65 | { |
acd5c346 | 66 | struct drm_i915_private *dev_priv = dev->dev_private; |
3ca5da43 | 67 | |
77719d28 DL |
68 | gen9_init_clock_gating(dev); |
69 | ||
3dcd020a HN |
70 | if (INTEL_REVID(dev) == SKL_REVID_A0) { |
71 | /* | |
72 | * WaDisableSDEUnitClockGating:skl | |
9253c2e5 | 73 | * WaSetGAPSunitClckGateDisable:skl |
3dcd020a HN |
74 | */ |
75 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
9253c2e5 | 76 | GEN8_GAPSUNIT_CLOCK_GATE_DISABLE | |
3dcd020a HN |
77 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); |
78 | } | |
8bc0ccf6 | 79 | |
2caa3b26 | 80 | if (INTEL_REVID(dev) <= SKL_REVID_D0) { |
81e231af DL |
81 | /* WaDisableHDCInvalidation:skl */ |
82 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | | |
83 | BDW_DISABLE_HDC_INVALIDATION); | |
84 | ||
2caa3b26 DL |
85 | /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */ |
86 | I915_WRITE(FF_SLICE_CS_CHICKEN2, | |
87 | I915_READ(FF_SLICE_CS_CHICKEN2) | | |
88 | GEN9_TSG_BARRIER_ACK_DISABLE); | |
89 | } | |
81e231af | 90 | |
8bc0ccf6 DL |
91 | if (INTEL_REVID(dev) <= SKL_REVID_E0) |
92 | /* WaDisableLSQCROPERFforOCL:skl */ | |
93 | I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) | | |
94 | GEN8_LQSC_RO_PERF_DIS); | |
da2078cd DL |
95 | } |
96 | ||
c921aba8 DV |
97 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
98 | { | |
50227e1c | 99 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
100 | u32 tmp; |
101 | ||
102 | tmp = I915_READ(CLKCFG); | |
103 | ||
104 | switch (tmp & CLKCFG_FSB_MASK) { | |
105 | case CLKCFG_FSB_533: | |
106 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
107 | break; | |
108 | case CLKCFG_FSB_800: | |
109 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
110 | break; | |
111 | case CLKCFG_FSB_667: | |
112 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
113 | break; | |
114 | case CLKCFG_FSB_400: | |
115 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
116 | break; | |
117 | } | |
118 | ||
119 | switch (tmp & CLKCFG_MEM_MASK) { | |
120 | case CLKCFG_MEM_533: | |
121 | dev_priv->mem_freq = 533; | |
122 | break; | |
123 | case CLKCFG_MEM_667: | |
124 | dev_priv->mem_freq = 667; | |
125 | break; | |
126 | case CLKCFG_MEM_800: | |
127 | dev_priv->mem_freq = 800; | |
128 | break; | |
129 | } | |
130 | ||
131 | /* detect pineview DDR3 setting */ | |
132 | tmp = I915_READ(CSHRDDR3CTL); | |
133 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
134 | } | |
135 | ||
136 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
137 | { | |
50227e1c | 138 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
139 | u16 ddrpll, csipll; |
140 | ||
141 | ddrpll = I915_READ16(DDRMPLL1); | |
142 | csipll = I915_READ16(CSIPLL0); | |
143 | ||
144 | switch (ddrpll & 0xff) { | |
145 | case 0xc: | |
146 | dev_priv->mem_freq = 800; | |
147 | break; | |
148 | case 0x10: | |
149 | dev_priv->mem_freq = 1066; | |
150 | break; | |
151 | case 0x14: | |
152 | dev_priv->mem_freq = 1333; | |
153 | break; | |
154 | case 0x18: | |
155 | dev_priv->mem_freq = 1600; | |
156 | break; | |
157 | default: | |
158 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
159 | ddrpll & 0xff); | |
160 | dev_priv->mem_freq = 0; | |
161 | break; | |
162 | } | |
163 | ||
20e4d407 | 164 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
165 | |
166 | switch (csipll & 0x3ff) { | |
167 | case 0x00c: | |
168 | dev_priv->fsb_freq = 3200; | |
169 | break; | |
170 | case 0x00e: | |
171 | dev_priv->fsb_freq = 3733; | |
172 | break; | |
173 | case 0x010: | |
174 | dev_priv->fsb_freq = 4266; | |
175 | break; | |
176 | case 0x012: | |
177 | dev_priv->fsb_freq = 4800; | |
178 | break; | |
179 | case 0x014: | |
180 | dev_priv->fsb_freq = 5333; | |
181 | break; | |
182 | case 0x016: | |
183 | dev_priv->fsb_freq = 5866; | |
184 | break; | |
185 | case 0x018: | |
186 | dev_priv->fsb_freq = 6400; | |
187 | break; | |
188 | default: | |
189 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
190 | csipll & 0x3ff); | |
191 | dev_priv->fsb_freq = 0; | |
192 | break; | |
193 | } | |
194 | ||
195 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 196 | dev_priv->ips.c_m = 0; |
c921aba8 | 197 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 198 | dev_priv->ips.c_m = 1; |
c921aba8 | 199 | } else { |
20e4d407 | 200 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
201 | } |
202 | } | |
203 | ||
b445e3b0 ED |
204 | static const struct cxsr_latency cxsr_latency_table[] = { |
205 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
206 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
207 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
208 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
209 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
210 | ||
211 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
212 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
213 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
214 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
215 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
216 | ||
217 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
218 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
219 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
220 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
221 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
222 | ||
223 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
224 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
225 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
226 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
227 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
228 | ||
229 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
230 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
231 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
232 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
233 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
234 | ||
235 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
236 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
237 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
238 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
239 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
240 | }; | |
241 | ||
63c62275 | 242 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
243 | int is_ddr3, |
244 | int fsb, | |
245 | int mem) | |
246 | { | |
247 | const struct cxsr_latency *latency; | |
248 | int i; | |
249 | ||
250 | if (fsb == 0 || mem == 0) | |
251 | return NULL; | |
252 | ||
253 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
254 | latency = &cxsr_latency_table[i]; | |
255 | if (is_desktop == latency->is_desktop && | |
256 | is_ddr3 == latency->is_ddr3 && | |
257 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
258 | return latency; | |
259 | } | |
260 | ||
261 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
262 | ||
263 | return NULL; | |
264 | } | |
265 | ||
fc1ac8de VS |
266 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
267 | { | |
268 | u32 val; | |
269 | ||
270 | mutex_lock(&dev_priv->rps.hw_lock); | |
271 | ||
272 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
273 | if (enable) | |
274 | val &= ~FORCE_DDR_HIGH_FREQ; | |
275 | else | |
276 | val |= FORCE_DDR_HIGH_FREQ; | |
277 | val &= ~FORCE_DDR_LOW_FREQ; | |
278 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
279 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
280 | ||
281 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
282 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
283 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
284 | ||
285 | mutex_unlock(&dev_priv->rps.hw_lock); | |
286 | } | |
287 | ||
cfb41411 VS |
288 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
289 | { | |
290 | u32 val; | |
291 | ||
292 | mutex_lock(&dev_priv->rps.hw_lock); | |
293 | ||
294 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
295 | if (enable) | |
296 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
297 | else | |
298 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
299 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
300 | ||
301 | mutex_unlock(&dev_priv->rps.hw_lock); | |
302 | } | |
303 | ||
5209b1f4 | 304 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 305 | { |
5209b1f4 ID |
306 | struct drm_device *dev = dev_priv->dev; |
307 | u32 val; | |
b445e3b0 | 308 | |
5209b1f4 ID |
309 | if (IS_VALLEYVIEW(dev)) { |
310 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
cfb41411 VS |
311 | if (IS_CHERRYVIEW(dev)) |
312 | chv_set_memory_pm5(dev_priv, enable); | |
5209b1f4 ID |
313 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { |
314 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
315 | } else if (IS_PINEVIEW(dev)) { | |
316 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
317 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
318 | I915_WRITE(DSPFW3, val); | |
319 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
320 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
321 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
322 | I915_WRITE(FW_BLC_SELF, val); | |
323 | } else if (IS_I915GM(dev)) { | |
324 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
325 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
326 | I915_WRITE(INSTPM, val); | |
327 | } else { | |
328 | return; | |
329 | } | |
b445e3b0 | 330 | |
5209b1f4 ID |
331 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
332 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
333 | } |
334 | ||
fc1ac8de | 335 | |
b445e3b0 ED |
336 | /* |
337 | * Latency for FIFO fetches is dependent on several factors: | |
338 | * - memory configuration (speed, channels) | |
339 | * - chipset | |
340 | * - current MCH state | |
341 | * It can be fairly high in some situations, so here we assume a fairly | |
342 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
343 | * set this value too high, the FIFO will fetch frequently to stay full) | |
344 | * and power consumption (set it too low to save power and we might see | |
345 | * FIFO underruns and display "flicker"). | |
346 | * | |
347 | * A value of 5us seems to be a good balance; safe for very low end | |
348 | * platforms but not overly aggressive on lower latency configs. | |
349 | */ | |
5aef6003 | 350 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 351 | |
b5004720 VS |
352 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
353 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
354 | ||
355 | static int vlv_get_fifo_size(struct drm_device *dev, | |
356 | enum pipe pipe, int plane) | |
357 | { | |
358 | struct drm_i915_private *dev_priv = dev->dev_private; | |
359 | int sprite0_start, sprite1_start, size; | |
360 | ||
361 | switch (pipe) { | |
362 | uint32_t dsparb, dsparb2, dsparb3; | |
363 | case PIPE_A: | |
364 | dsparb = I915_READ(DSPARB); | |
365 | dsparb2 = I915_READ(DSPARB2); | |
366 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
367 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
368 | break; | |
369 | case PIPE_B: | |
370 | dsparb = I915_READ(DSPARB); | |
371 | dsparb2 = I915_READ(DSPARB2); | |
372 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
373 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
374 | break; | |
375 | case PIPE_C: | |
376 | dsparb2 = I915_READ(DSPARB2); | |
377 | dsparb3 = I915_READ(DSPARB3); | |
378 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
379 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
380 | break; | |
381 | default: | |
382 | return 0; | |
383 | } | |
384 | ||
385 | switch (plane) { | |
386 | case 0: | |
387 | size = sprite0_start; | |
388 | break; | |
389 | case 1: | |
390 | size = sprite1_start - sprite0_start; | |
391 | break; | |
392 | case 2: | |
393 | size = 512 - 1 - sprite1_start; | |
394 | break; | |
395 | default: | |
396 | return 0; | |
397 | } | |
398 | ||
399 | DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n", | |
400 | pipe_name(pipe), plane == 0 ? "primary" : "sprite", | |
401 | plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1), | |
402 | size); | |
403 | ||
404 | return size; | |
405 | } | |
406 | ||
1fa61106 | 407 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
408 | { |
409 | struct drm_i915_private *dev_priv = dev->dev_private; | |
410 | uint32_t dsparb = I915_READ(DSPARB); | |
411 | int size; | |
412 | ||
413 | size = dsparb & 0x7f; | |
414 | if (plane) | |
415 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
416 | ||
417 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
418 | plane ? "B" : "A", size); | |
419 | ||
420 | return size; | |
421 | } | |
422 | ||
feb56b93 | 423 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
424 | { |
425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
426 | uint32_t dsparb = I915_READ(DSPARB); | |
427 | int size; | |
428 | ||
429 | size = dsparb & 0x1ff; | |
430 | if (plane) | |
431 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
432 | size >>= 1; /* Convert to cachelines */ | |
433 | ||
434 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
435 | plane ? "B" : "A", size); | |
436 | ||
437 | return size; | |
438 | } | |
439 | ||
1fa61106 | 440 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
441 | { |
442 | struct drm_i915_private *dev_priv = dev->dev_private; | |
443 | uint32_t dsparb = I915_READ(DSPARB); | |
444 | int size; | |
445 | ||
446 | size = dsparb & 0x7f; | |
447 | size >>= 2; /* Convert to cachelines */ | |
448 | ||
449 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
450 | plane ? "B" : "A", | |
451 | size); | |
452 | ||
453 | return size; | |
454 | } | |
455 | ||
b445e3b0 ED |
456 | /* Pineview has different values for various configs */ |
457 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
458 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
459 | .max_wm = PINEVIEW_MAX_WM, | |
460 | .default_wm = PINEVIEW_DFT_WM, | |
461 | .guard_size = PINEVIEW_GUARD_WM, | |
462 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
463 | }; |
464 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
465 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
466 | .max_wm = PINEVIEW_MAX_WM, | |
467 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
468 | .guard_size = PINEVIEW_GUARD_WM, | |
469 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
470 | }; |
471 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
472 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
473 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
474 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
475 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
476 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
477 | }; |
478 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
479 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
480 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
481 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
482 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
483 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
484 | }; |
485 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
486 | .fifo_size = G4X_FIFO_SIZE, |
487 | .max_wm = G4X_MAX_WM, | |
488 | .default_wm = G4X_MAX_WM, | |
489 | .guard_size = 2, | |
490 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
491 | }; |
492 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
493 | .fifo_size = I965_CURSOR_FIFO, |
494 | .max_wm = I965_CURSOR_MAX_WM, | |
495 | .default_wm = I965_CURSOR_DFT_WM, | |
496 | .guard_size = 2, | |
497 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
498 | }; |
499 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
500 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
501 | .max_wm = VALLEYVIEW_MAX_WM, | |
502 | .default_wm = VALLEYVIEW_MAX_WM, | |
503 | .guard_size = 2, | |
504 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
505 | }; |
506 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
507 | .fifo_size = I965_CURSOR_FIFO, |
508 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
509 | .default_wm = I965_CURSOR_DFT_WM, | |
510 | .guard_size = 2, | |
511 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
512 | }; |
513 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
514 | .fifo_size = I965_CURSOR_FIFO, |
515 | .max_wm = I965_CURSOR_MAX_WM, | |
516 | .default_wm = I965_CURSOR_DFT_WM, | |
517 | .guard_size = 2, | |
518 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
519 | }; |
520 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
521 | .fifo_size = I945_FIFO_SIZE, |
522 | .max_wm = I915_MAX_WM, | |
523 | .default_wm = 1, | |
524 | .guard_size = 2, | |
525 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
526 | }; |
527 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
528 | .fifo_size = I915_FIFO_SIZE, |
529 | .max_wm = I915_MAX_WM, | |
530 | .default_wm = 1, | |
531 | .guard_size = 2, | |
532 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 533 | }; |
9d539105 | 534 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
535 | .fifo_size = I855GM_FIFO_SIZE, |
536 | .max_wm = I915_MAX_WM, | |
537 | .default_wm = 1, | |
538 | .guard_size = 2, | |
539 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 540 | }; |
9d539105 VS |
541 | static const struct intel_watermark_params i830_bc_wm_info = { |
542 | .fifo_size = I855GM_FIFO_SIZE, | |
543 | .max_wm = I915_MAX_WM/2, | |
544 | .default_wm = 1, | |
545 | .guard_size = 2, | |
546 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
547 | }; | |
feb56b93 | 548 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
549 | .fifo_size = I830_FIFO_SIZE, |
550 | .max_wm = I915_MAX_WM, | |
551 | .default_wm = 1, | |
552 | .guard_size = 2, | |
553 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
554 | }; |
555 | ||
b445e3b0 ED |
556 | /** |
557 | * intel_calculate_wm - calculate watermark level | |
558 | * @clock_in_khz: pixel clock | |
559 | * @wm: chip FIFO params | |
560 | * @pixel_size: display pixel size | |
561 | * @latency_ns: memory latency for the platform | |
562 | * | |
563 | * Calculate the watermark level (the level at which the display plane will | |
564 | * start fetching from memory again). Each chip has a different display | |
565 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
566 | * in the correct intel_watermark_params structure. | |
567 | * | |
568 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
569 | * on the pixel size. When it reaches the watermark level, it'll start | |
570 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
571 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
572 | * will occur, and a display engine hang could result. | |
573 | */ | |
574 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
575 | const struct intel_watermark_params *wm, | |
576 | int fifo_size, | |
577 | int pixel_size, | |
578 | unsigned long latency_ns) | |
579 | { | |
580 | long entries_required, wm_size; | |
581 | ||
582 | /* | |
583 | * Note: we need to make sure we don't overflow for various clock & | |
584 | * latency values. | |
585 | * clocks go from a few thousand to several hundred thousand. | |
586 | * latency is usually a few thousand | |
587 | */ | |
588 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
589 | 1000; | |
590 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
591 | ||
592 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
593 | ||
594 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
595 | ||
596 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
597 | ||
598 | /* Don't promote wm_size to unsigned... */ | |
599 | if (wm_size > (long)wm->max_wm) | |
600 | wm_size = wm->max_wm; | |
601 | if (wm_size <= 0) | |
602 | wm_size = wm->default_wm; | |
d6feb196 VS |
603 | |
604 | /* | |
605 | * Bspec seems to indicate that the value shouldn't be lower than | |
606 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
607 | * Lets go for 8 which is the burst size since certain platforms | |
608 | * already use a hardcoded 8 (which is what the spec says should be | |
609 | * done). | |
610 | */ | |
611 | if (wm_size <= 8) | |
612 | wm_size = 8; | |
613 | ||
b445e3b0 ED |
614 | return wm_size; |
615 | } | |
616 | ||
617 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
618 | { | |
619 | struct drm_crtc *crtc, *enabled = NULL; | |
620 | ||
70e1e0ec | 621 | for_each_crtc(dev, crtc) { |
3490ea5d | 622 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
623 | if (enabled) |
624 | return NULL; | |
625 | enabled = crtc; | |
626 | } | |
627 | } | |
628 | ||
629 | return enabled; | |
630 | } | |
631 | ||
46ba614c | 632 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 633 | { |
46ba614c | 634 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
635 | struct drm_i915_private *dev_priv = dev->dev_private; |
636 | struct drm_crtc *crtc; | |
637 | const struct cxsr_latency *latency; | |
638 | u32 reg; | |
639 | unsigned long wm; | |
640 | ||
641 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
642 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
643 | if (!latency) { | |
644 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 645 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
646 | return; |
647 | } | |
648 | ||
649 | crtc = single_enabled_crtc(dev); | |
650 | if (crtc) { | |
241bfc38 | 651 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 652 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
241bfc38 DL |
653 | int clock; |
654 | ||
6e3c9717 | 655 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 656 | clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
657 | |
658 | /* Display SR */ | |
659 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
660 | pineview_display_wm.fifo_size, | |
661 | pixel_size, latency->display_sr); | |
662 | reg = I915_READ(DSPFW1); | |
663 | reg &= ~DSPFW_SR_MASK; | |
664 | reg |= wm << DSPFW_SR_SHIFT; | |
665 | I915_WRITE(DSPFW1, reg); | |
666 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
667 | ||
668 | /* cursor SR */ | |
669 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
670 | pineview_display_wm.fifo_size, | |
671 | pixel_size, latency->cursor_sr); | |
672 | reg = I915_READ(DSPFW3); | |
673 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
674 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
675 | I915_WRITE(DSPFW3, reg); | |
676 | ||
677 | /* Display HPLL off SR */ | |
678 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
679 | pineview_display_hplloff_wm.fifo_size, | |
680 | pixel_size, latency->display_hpll_disable); | |
681 | reg = I915_READ(DSPFW3); | |
682 | reg &= ~DSPFW_HPLL_SR_MASK; | |
683 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
684 | I915_WRITE(DSPFW3, reg); | |
685 | ||
686 | /* cursor HPLL off SR */ | |
687 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
688 | pineview_display_hplloff_wm.fifo_size, | |
689 | pixel_size, latency->cursor_hpll_disable); | |
690 | reg = I915_READ(DSPFW3); | |
691 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
692 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
693 | I915_WRITE(DSPFW3, reg); | |
694 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
695 | ||
5209b1f4 | 696 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 697 | } else { |
5209b1f4 | 698 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
699 | } |
700 | } | |
701 | ||
702 | static bool g4x_compute_wm0(struct drm_device *dev, | |
703 | int plane, | |
704 | const struct intel_watermark_params *display, | |
705 | int display_latency_ns, | |
706 | const struct intel_watermark_params *cursor, | |
707 | int cursor_latency_ns, | |
708 | int *plane_wm, | |
709 | int *cursor_wm) | |
710 | { | |
711 | struct drm_crtc *crtc; | |
4fe8590a | 712 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
713 | int htotal, hdisplay, clock, pixel_size; |
714 | int line_time_us, line_count; | |
715 | int entries, tlb_miss; | |
716 | ||
717 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 718 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
719 | *cursor_wm = cursor->guard_size; |
720 | *plane_wm = display->guard_size; | |
721 | return false; | |
722 | } | |
723 | ||
6e3c9717 | 724 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 725 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 726 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 727 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 728 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
729 | |
730 | /* Use the small buffer method to calculate plane watermark */ | |
731 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
732 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
733 | if (tlb_miss > 0) | |
734 | entries += tlb_miss; | |
735 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
736 | *plane_wm = entries + display->guard_size; | |
737 | if (*plane_wm > (int)display->max_wm) | |
738 | *plane_wm = display->max_wm; | |
739 | ||
740 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 741 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 742 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
3dd512fb | 743 | entries = line_count * crtc->cursor->state->crtc_w * pixel_size; |
b445e3b0 ED |
744 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
745 | if (tlb_miss > 0) | |
746 | entries += tlb_miss; | |
747 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
748 | *cursor_wm = entries + cursor->guard_size; | |
749 | if (*cursor_wm > (int)cursor->max_wm) | |
750 | *cursor_wm = (int)cursor->max_wm; | |
751 | ||
752 | return true; | |
753 | } | |
754 | ||
755 | /* | |
756 | * Check the wm result. | |
757 | * | |
758 | * If any calculated watermark values is larger than the maximum value that | |
759 | * can be programmed into the associated watermark register, that watermark | |
760 | * must be disabled. | |
761 | */ | |
762 | static bool g4x_check_srwm(struct drm_device *dev, | |
763 | int display_wm, int cursor_wm, | |
764 | const struct intel_watermark_params *display, | |
765 | const struct intel_watermark_params *cursor) | |
766 | { | |
767 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
768 | display_wm, cursor_wm); | |
769 | ||
770 | if (display_wm > display->max_wm) { | |
771 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
772 | display_wm, display->max_wm); | |
773 | return false; | |
774 | } | |
775 | ||
776 | if (cursor_wm > cursor->max_wm) { | |
777 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
778 | cursor_wm, cursor->max_wm); | |
779 | return false; | |
780 | } | |
781 | ||
782 | if (!(display_wm || cursor_wm)) { | |
783 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
784 | return false; | |
785 | } | |
786 | ||
787 | return true; | |
788 | } | |
789 | ||
790 | static bool g4x_compute_srwm(struct drm_device *dev, | |
791 | int plane, | |
792 | int latency_ns, | |
793 | const struct intel_watermark_params *display, | |
794 | const struct intel_watermark_params *cursor, | |
795 | int *display_wm, int *cursor_wm) | |
796 | { | |
797 | struct drm_crtc *crtc; | |
4fe8590a | 798 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
799 | int hdisplay, htotal, pixel_size, clock; |
800 | unsigned long line_time_us; | |
801 | int line_count, line_size; | |
802 | int small, large; | |
803 | int entries; | |
804 | ||
805 | if (!latency_ns) { | |
806 | *display_wm = *cursor_wm = 0; | |
807 | return false; | |
808 | } | |
809 | ||
810 | crtc = intel_get_crtc_for_plane(dev, plane); | |
6e3c9717 | 811 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 812 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 813 | htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 814 | hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 815 | pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 | 816 | |
922044c9 | 817 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
818 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
819 | line_size = hdisplay * pixel_size; | |
820 | ||
821 | /* Use the minimum of the small and large buffer method for primary */ | |
822 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
823 | large = line_count * line_size; | |
824 | ||
825 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
826 | *display_wm = entries + display->guard_size; | |
827 | ||
828 | /* calculate the self-refresh watermark for display cursor */ | |
3dd512fb | 829 | entries = line_count * pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
830 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
831 | *cursor_wm = entries + cursor->guard_size; | |
832 | ||
833 | return g4x_check_srwm(dev, | |
834 | *display_wm, *cursor_wm, | |
835 | display, cursor); | |
836 | } | |
837 | ||
15665979 VS |
838 | #define FW_WM(value, plane) \ |
839 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
840 | #define FW_WM_VLV(value, plane) \ | |
841 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
842 | ||
0018fda1 VS |
843 | static void vlv_write_wm_values(struct intel_crtc *crtc, |
844 | const struct vlv_wm_values *wm) | |
845 | { | |
846 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
847 | enum pipe pipe = crtc->pipe; | |
848 | ||
849 | I915_WRITE(VLV_DDL(pipe), | |
850 | (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) | | |
851 | (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) | | |
852 | (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) | | |
853 | (wm->ddl[pipe].primary << DDL_PLANE_SHIFT)); | |
854 | ||
ae80152d | 855 | I915_WRITE(DSPFW1, |
15665979 VS |
856 | FW_WM(wm->sr.plane, SR) | |
857 | FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) | | |
858 | FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) | | |
859 | FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA)); | |
ae80152d | 860 | I915_WRITE(DSPFW2, |
15665979 VS |
861 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) | |
862 | FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) | | |
863 | FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA)); | |
ae80152d | 864 | I915_WRITE(DSPFW3, |
15665979 | 865 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
866 | |
867 | if (IS_CHERRYVIEW(dev_priv)) { | |
868 | I915_WRITE(DSPFW7_CHV, | |
15665979 VS |
869 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
870 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 871 | I915_WRITE(DSPFW8_CHV, |
15665979 VS |
872 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) | |
873 | FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE)); | |
ae80152d | 874 | I915_WRITE(DSPFW9_CHV, |
15665979 VS |
875 | FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) | |
876 | FW_WM(wm->pipe[PIPE_C].cursor, CURSORC)); | |
ae80152d | 877 | I915_WRITE(DSPHOWM, |
15665979 VS |
878 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
879 | FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) | | |
880 | FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) | | |
881 | FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) | | |
882 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
883 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
884 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
885 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
886 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
887 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
888 | } else { |
889 | I915_WRITE(DSPFW7, | |
15665979 VS |
890 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) | |
891 | FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC)); | |
ae80152d | 892 | I915_WRITE(DSPHOWM, |
15665979 VS |
893 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
894 | FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) | | |
895 | FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) | | |
896 | FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) | | |
897 | FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) | | |
898 | FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) | | |
899 | FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI)); | |
ae80152d VS |
900 | } |
901 | ||
902 | POSTING_READ(DSPFW1); | |
903 | ||
0018fda1 VS |
904 | dev_priv->wm.vlv = *wm; |
905 | } | |
906 | ||
15665979 VS |
907 | #undef FW_WM |
908 | #undef FW_WM_VLV | |
909 | ||
341c526f | 910 | static uint8_t vlv_compute_drain_latency(struct drm_crtc *crtc, |
883a3d2f | 911 | struct drm_plane *plane) |
b445e3b0 | 912 | { |
5e56ba45 | 913 | struct drm_device *dev = crtc->dev; |
883a3d2f VS |
914 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
915 | int entries, prec_mult, drain_latency, pixel_size; | |
916 | int clock = intel_crtc->config->base.adjusted_mode.crtc_clock; | |
341c526f | 917 | const int high_precision = IS_CHERRYVIEW(dev) ? 16 : 64; |
b445e3b0 | 918 | |
883a3d2f VS |
919 | /* |
920 | * FIXME the plane might have an fb | |
921 | * but be invisible (eg. due to clipping) | |
922 | */ | |
923 | if (!intel_crtc->active || !plane->state->fb) | |
924 | return 0; | |
925 | ||
0948c265 | 926 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
341c526f | 927 | return 0; |
b445e3b0 | 928 | |
883a3d2f VS |
929 | pixel_size = drm_format_plane_cpp(plane->state->fb->pixel_format, 0); |
930 | ||
0948c265 | 931 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
341c526f | 932 | return 0; |
b445e3b0 | 933 | |
a398e9c7 | 934 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
abfc00b5 | 935 | |
341c526f VS |
936 | prec_mult = high_precision; |
937 | drain_latency = 64 * prec_mult * 4 / entries; | |
b445e3b0 | 938 | |
341c526f VS |
939 | if (drain_latency > DRAIN_LATENCY_MASK) { |
940 | prec_mult /= 2; | |
941 | drain_latency = 64 * prec_mult * 4 / entries; | |
abfc00b5 VS |
942 | } |
943 | ||
341c526f VS |
944 | if (drain_latency > DRAIN_LATENCY_MASK) |
945 | drain_latency = DRAIN_LATENCY_MASK; | |
b445e3b0 | 946 | |
341c526f VS |
947 | return drain_latency | (prec_mult == high_precision ? |
948 | DDL_PRECISION_HIGH : DDL_PRECISION_LOW); | |
b445e3b0 ED |
949 | } |
950 | ||
ae80152d VS |
951 | static int vlv_compute_wm(struct intel_crtc *crtc, |
952 | struct intel_plane *plane, | |
953 | int fifo_size) | |
b445e3b0 | 954 | { |
ae80152d | 955 | int clock, entries, pixel_size; |
b445e3b0 | 956 | |
ae80152d VS |
957 | /* |
958 | * FIXME the plane might have an fb | |
959 | * but be invisible (eg. due to clipping) | |
960 | */ | |
961 | if (!crtc->active || !plane->base.state->fb) | |
962 | return 0; | |
0948c265 | 963 | |
ae80152d VS |
964 | pixel_size = drm_format_plane_cpp(plane->base.state->fb->pixel_format, 0); |
965 | clock = crtc->config->base.adjusted_mode.crtc_clock; | |
b445e3b0 | 966 | |
ae80152d | 967 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
b445e3b0 | 968 | |
ae80152d VS |
969 | /* |
970 | * Set up the watermark such that we don't start issuing memory | |
971 | * requests until we are within PND's max deadline value (256us). | |
972 | * Idea being to be idle as long as possible while still taking | |
973 | * advatange of PND's deadline scheduling. The limit of 8 | |
974 | * cachelines (used when the FIFO will anyway drain in less time | |
975 | * than 256us) should match what we would be done if trickle | |
976 | * feed were enabled. | |
977 | */ | |
978 | return fifo_size - clamp(DIV_ROUND_UP(256 * entries, 64), 0, fifo_size - 8); | |
979 | } | |
980 | ||
981 | static bool vlv_compute_sr_wm(struct drm_device *dev, | |
982 | struct vlv_wm_values *wm) | |
b445e3b0 | 983 | { |
ae80152d VS |
984 | struct drm_i915_private *dev_priv = to_i915(dev); |
985 | struct drm_crtc *crtc; | |
986 | enum pipe pipe = INVALID_PIPE; | |
987 | int num_planes = 0; | |
988 | int fifo_size = 0; | |
989 | struct intel_plane *plane; | |
b445e3b0 | 990 | |
ae80152d | 991 | wm->sr.cursor = wm->sr.plane = 0; |
b445e3b0 | 992 | |
ae80152d VS |
993 | crtc = single_enabled_crtc(dev); |
994 | /* maxfifo not supported on pipe C */ | |
995 | if (crtc && to_intel_crtc(crtc)->pipe != PIPE_C) { | |
996 | pipe = to_intel_crtc(crtc)->pipe; | |
997 | num_planes = !!wm->pipe[pipe].primary + | |
998 | !!wm->pipe[pipe].sprite[0] + | |
999 | !!wm->pipe[pipe].sprite[1]; | |
1000 | fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; | |
1001 | } | |
b445e3b0 | 1002 | |
ae80152d VS |
1003 | if (fifo_size == 0 || num_planes > 1) |
1004 | return false; | |
b445e3b0 | 1005 | |
ae80152d VS |
1006 | wm->sr.cursor = vlv_compute_wm(to_intel_crtc(crtc), |
1007 | to_intel_plane(crtc->cursor), 0x3f); | |
b445e3b0 | 1008 | |
ae80152d VS |
1009 | list_for_each_entry(plane, &dev->mode_config.plane_list, base.head) { |
1010 | if (plane->base.type == DRM_PLANE_TYPE_CURSOR) | |
1011 | continue; | |
b445e3b0 | 1012 | |
ae80152d VS |
1013 | if (plane->pipe != pipe) |
1014 | continue; | |
9858425c | 1015 | |
ae80152d VS |
1016 | wm->sr.plane = vlv_compute_wm(to_intel_crtc(crtc), |
1017 | plane, fifo_size); | |
1018 | if (wm->sr.plane != 0) | |
1019 | break; | |
1020 | } | |
1021 | ||
1022 | return true; | |
b445e3b0 ED |
1023 | } |
1024 | ||
ae80152d | 1025 | static void valleyview_update_wm(struct drm_crtc *crtc) |
3c2777fd VS |
1026 | { |
1027 | struct drm_device *dev = crtc->dev; | |
3c2777fd | 1028 | struct drm_i915_private *dev_priv = dev->dev_private; |
ae80152d VS |
1029 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1030 | enum pipe pipe = intel_crtc->pipe; | |
3c2777fd | 1031 | bool cxsr_enabled; |
ae80152d | 1032 | struct vlv_wm_values wm = dev_priv->wm.vlv; |
3c2777fd | 1033 | |
ae80152d VS |
1034 | wm.ddl[pipe].primary = vlv_compute_drain_latency(crtc, crtc->primary); |
1035 | wm.pipe[pipe].primary = vlv_compute_wm(intel_crtc, | |
1036 | to_intel_plane(crtc->primary), | |
1037 | vlv_get_fifo_size(dev, pipe, 0)); | |
3c2777fd | 1038 | |
ae80152d VS |
1039 | wm.ddl[pipe].cursor = vlv_compute_drain_latency(crtc, crtc->cursor); |
1040 | wm.pipe[pipe].cursor = vlv_compute_wm(intel_crtc, | |
1041 | to_intel_plane(crtc->cursor), | |
1042 | 0x3f); | |
3c2777fd | 1043 | |
ae80152d | 1044 | cxsr_enabled = vlv_compute_sr_wm(dev, &wm); |
3c2777fd | 1045 | |
ae80152d VS |
1046 | if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0) |
1047 | return; | |
3c2777fd | 1048 | |
ae80152d VS |
1049 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, " |
1050 | "SR: plane=%d, cursor=%d\n", pipe_name(pipe), | |
1051 | wm.pipe[pipe].primary, wm.pipe[pipe].cursor, | |
1052 | wm.sr.plane, wm.sr.cursor); | |
3c2777fd | 1053 | |
fc1ac8de VS |
1054 | /* |
1055 | * FIXME DDR DVFS introduces massive memory latencies which | |
1056 | * are not known to system agent so any deadline specified | |
1057 | * by the display may not be respected. To support DDR DVFS | |
1058 | * the watermark code needs to be rewritten to essentially | |
1059 | * bypass deadline mechanism and rely solely on the | |
1060 | * watermarks. For now disable DDR DVFS. | |
1061 | */ | |
1062 | if (IS_CHERRYVIEW(dev_priv)) | |
1063 | chv_set_memory_dvfs(dev_priv, false); | |
1064 | ||
ae80152d VS |
1065 | if (!cxsr_enabled) |
1066 | intel_set_memory_cxsr(dev_priv, false); | |
3c2777fd | 1067 | |
ae80152d | 1068 | vlv_write_wm_values(intel_crtc, &wm); |
3c2777fd VS |
1069 | |
1070 | if (cxsr_enabled) | |
1071 | intel_set_memory_cxsr(dev_priv, true); | |
1072 | } | |
1073 | ||
01e184cc GB |
1074 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
1075 | struct drm_crtc *crtc, | |
1076 | uint32_t sprite_width, | |
1077 | uint32_t sprite_height, | |
1078 | int pixel_size, | |
1079 | bool enabled, bool scaled) | |
1080 | { | |
1081 | struct drm_device *dev = crtc->dev; | |
1082 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0018fda1 VS |
1083 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1084 | enum pipe pipe = intel_crtc->pipe; | |
01e184cc | 1085 | int sprite = to_intel_plane(plane)->plane; |
ae80152d | 1086 | bool cxsr_enabled; |
0018fda1 | 1087 | struct vlv_wm_values wm = dev_priv->wm.vlv; |
01e184cc | 1088 | |
ae80152d | 1089 | if (enabled) { |
0018fda1 | 1090 | wm.ddl[pipe].sprite[sprite] = |
883a3d2f | 1091 | vlv_compute_drain_latency(crtc, plane); |
ae80152d VS |
1092 | |
1093 | wm.pipe[pipe].sprite[sprite] = | |
1094 | vlv_compute_wm(intel_crtc, | |
1095 | to_intel_plane(plane), | |
1096 | vlv_get_fifo_size(dev, pipe, sprite+1)); | |
1097 | } else { | |
0018fda1 | 1098 | wm.ddl[pipe].sprite[sprite] = 0; |
ae80152d VS |
1099 | wm.pipe[pipe].sprite[sprite] = 0; |
1100 | } | |
1101 | ||
1102 | cxsr_enabled = vlv_compute_sr_wm(dev, &wm); | |
1103 | ||
1104 | if (memcmp(&wm, &dev_priv->wm.vlv, sizeof(wm)) == 0) | |
1105 | return; | |
1106 | ||
1107 | DRM_DEBUG_KMS("Setting FIFO watermarks - %c: sprite %c=%d, " | |
1108 | "SR: plane=%d, cursor=%d\n", pipe_name(pipe), | |
1109 | sprite_name(pipe, sprite), | |
1110 | wm.pipe[pipe].sprite[sprite], | |
1111 | wm.sr.plane, wm.sr.cursor); | |
1112 | ||
1113 | if (!cxsr_enabled) | |
1114 | intel_set_memory_cxsr(dev_priv, false); | |
01e184cc | 1115 | |
0018fda1 | 1116 | vlv_write_wm_values(intel_crtc, &wm); |
ae80152d VS |
1117 | |
1118 | if (cxsr_enabled) | |
1119 | intel_set_memory_cxsr(dev_priv, true); | |
01e184cc GB |
1120 | } |
1121 | ||
ae80152d VS |
1122 | #define single_plane_enabled(mask) is_power_of_2(mask) |
1123 | ||
46ba614c | 1124 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1125 | { |
46ba614c | 1126 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1127 | static const int sr_latency_ns = 12000; |
1128 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1129 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1130 | int plane_sr, cursor_sr; | |
1131 | unsigned int enabled = 0; | |
9858425c | 1132 | bool cxsr_enabled; |
b445e3b0 | 1133 | |
51cea1f4 | 1134 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1135 | &g4x_wm_info, pessimal_latency_ns, |
1136 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1137 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1138 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1139 | |
51cea1f4 | 1140 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1141 | &g4x_wm_info, pessimal_latency_ns, |
1142 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1143 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1144 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1145 | |
b445e3b0 ED |
1146 | if (single_plane_enabled(enabled) && |
1147 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1148 | sr_latency_ns, | |
1149 | &g4x_wm_info, | |
1150 | &g4x_cursor_wm_info, | |
52bd02d8 | 1151 | &plane_sr, &cursor_sr)) { |
9858425c | 1152 | cxsr_enabled = true; |
52bd02d8 | 1153 | } else { |
9858425c | 1154 | cxsr_enabled = false; |
5209b1f4 | 1155 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1156 | plane_sr = cursor_sr = 0; |
1157 | } | |
b445e3b0 | 1158 | |
a5043453 VS |
1159 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1160 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1161 | planea_wm, cursora_wm, |
1162 | planeb_wm, cursorb_wm, | |
1163 | plane_sr, cursor_sr); | |
1164 | ||
1165 | I915_WRITE(DSPFW1, | |
1166 | (plane_sr << DSPFW_SR_SHIFT) | | |
1167 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1168 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1169 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1170 | I915_WRITE(DSPFW2, |
8c919b28 | 1171 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1172 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1173 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1174 | I915_WRITE(DSPFW3, | |
8c919b28 | 1175 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 | 1176 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
9858425c ID |
1177 | |
1178 | if (cxsr_enabled) | |
1179 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1180 | } |
1181 | ||
46ba614c | 1182 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1183 | { |
46ba614c | 1184 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1185 | struct drm_i915_private *dev_priv = dev->dev_private; |
1186 | struct drm_crtc *crtc; | |
1187 | int srwm = 1; | |
1188 | int cursor_sr = 16; | |
9858425c | 1189 | bool cxsr_enabled; |
b445e3b0 ED |
1190 | |
1191 | /* Calc sr entries for one plane configs */ | |
1192 | crtc = single_enabled_crtc(dev); | |
1193 | if (crtc) { | |
1194 | /* self-refresh has much higher latency */ | |
1195 | static const int sr_latency_ns = 12000; | |
4fe8590a | 1196 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1197 | &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1198 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1199 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1200 | int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w; |
59bea882 | 1201 | int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1202 | unsigned long line_time_us; |
1203 | int entries; | |
1204 | ||
922044c9 | 1205 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1206 | |
1207 | /* Use ns/us then divide to preserve precision */ | |
1208 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1209 | pixel_size * hdisplay; | |
1210 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1211 | srwm = I965_FIFO_SIZE - entries; | |
1212 | if (srwm < 0) | |
1213 | srwm = 1; | |
1214 | srwm &= 0x1ff; | |
1215 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1216 | entries, srwm); | |
1217 | ||
1218 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
3dd512fb | 1219 | pixel_size * crtc->cursor->state->crtc_w; |
b445e3b0 ED |
1220 | entries = DIV_ROUND_UP(entries, |
1221 | i965_cursor_wm_info.cacheline_size); | |
1222 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1223 | (entries + i965_cursor_wm_info.guard_size); | |
1224 | ||
1225 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1226 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1227 | ||
1228 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1229 | "cursor %d\n", srwm, cursor_sr); | |
1230 | ||
9858425c | 1231 | cxsr_enabled = true; |
b445e3b0 | 1232 | } else { |
9858425c | 1233 | cxsr_enabled = false; |
b445e3b0 | 1234 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1235 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1236 | } |
1237 | ||
1238 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1239 | srwm); | |
1240 | ||
1241 | /* 965 has limitations... */ | |
1242 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
0a560674 VS |
1243 | (8 << DSPFW_CURSORB_SHIFT) | |
1244 | (8 << DSPFW_PLANEB_SHIFT) | | |
1245 | (8 << DSPFW_PLANEA_SHIFT)); | |
1246 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | | |
1247 | (8 << DSPFW_PLANEC_SHIFT_OLD)); | |
b445e3b0 ED |
1248 | /* update cursor SR watermark */ |
1249 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1250 | |
1251 | if (cxsr_enabled) | |
1252 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1253 | } |
1254 | ||
46ba614c | 1255 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1256 | { |
46ba614c | 1257 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1258 | struct drm_i915_private *dev_priv = dev->dev_private; |
1259 | const struct intel_watermark_params *wm_info; | |
1260 | uint32_t fwater_lo; | |
1261 | uint32_t fwater_hi; | |
1262 | int cwm, srwm = 1; | |
1263 | int fifo_size; | |
1264 | int planea_wm, planeb_wm; | |
1265 | struct drm_crtc *crtc, *enabled = NULL; | |
1266 | ||
1267 | if (IS_I945GM(dev)) | |
1268 | wm_info = &i945_wm_info; | |
1269 | else if (!IS_GEN2(dev)) | |
1270 | wm_info = &i915_wm_info; | |
1271 | else | |
9d539105 | 1272 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1273 | |
1274 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1275 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1276 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1277 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1278 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1279 | if (IS_GEN2(dev)) |
1280 | cpp = 4; | |
1281 | ||
6e3c9717 | 1282 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1283 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1284 | wm_info, fifo_size, cpp, |
5aef6003 | 1285 | pessimal_latency_ns); |
b445e3b0 | 1286 | enabled = crtc; |
9d539105 | 1287 | } else { |
b445e3b0 | 1288 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1289 | if (planea_wm > (long)wm_info->max_wm) |
1290 | planea_wm = wm_info->max_wm; | |
1291 | } | |
1292 | ||
1293 | if (IS_GEN2(dev)) | |
1294 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1295 | |
1296 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1297 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1298 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1299 | const struct drm_display_mode *adjusted_mode; |
59bea882 | 1300 | int cpp = crtc->primary->state->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1301 | if (IS_GEN2(dev)) |
1302 | cpp = 4; | |
1303 | ||
6e3c9717 | 1304 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1305 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 1306 | wm_info, fifo_size, cpp, |
5aef6003 | 1307 | pessimal_latency_ns); |
b445e3b0 ED |
1308 | if (enabled == NULL) |
1309 | enabled = crtc; | |
1310 | else | |
1311 | enabled = NULL; | |
9d539105 | 1312 | } else { |
b445e3b0 | 1313 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1314 | if (planeb_wm > (long)wm_info->max_wm) |
1315 | planeb_wm = wm_info->max_wm; | |
1316 | } | |
b445e3b0 ED |
1317 | |
1318 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1319 | ||
2ab1bc9d | 1320 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1321 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1322 | |
59bea882 | 1323 | obj = intel_fb_obj(enabled->primary->state->fb); |
2ab1bc9d DV |
1324 | |
1325 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1326 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1327 | enabled = NULL; |
1328 | } | |
1329 | ||
b445e3b0 ED |
1330 | /* |
1331 | * Overlay gets an aggressive default since video jitter is bad. | |
1332 | */ | |
1333 | cwm = 2; | |
1334 | ||
1335 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1336 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1337 | |
1338 | /* Calc sr entries for one plane configs */ | |
1339 | if (HAS_FW_BLC(dev) && enabled) { | |
1340 | /* self-refresh has much higher latency */ | |
1341 | static const int sr_latency_ns = 6000; | |
4fe8590a | 1342 | const struct drm_display_mode *adjusted_mode = |
6e3c9717 | 1343 | &to_intel_crtc(enabled)->config->base.adjusted_mode; |
241bfc38 | 1344 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1345 | int htotal = adjusted_mode->crtc_htotal; |
6e3c9717 | 1346 | int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w; |
59bea882 | 1347 | int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1348 | unsigned long line_time_us; |
1349 | int entries; | |
1350 | ||
922044c9 | 1351 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1352 | |
1353 | /* Use ns/us then divide to preserve precision */ | |
1354 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1355 | pixel_size * hdisplay; | |
1356 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1357 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1358 | srwm = wm_info->fifo_size - entries; | |
1359 | if (srwm < 0) | |
1360 | srwm = 1; | |
1361 | ||
1362 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1363 | I915_WRITE(FW_BLC_SELF, | |
1364 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1365 | else if (IS_I915GM(dev)) | |
1366 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1367 | } | |
1368 | ||
1369 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1370 | planea_wm, planeb_wm, cwm, srwm); | |
1371 | ||
1372 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1373 | fwater_hi = (cwm & 0x1f); | |
1374 | ||
1375 | /* Set request length to 8 cachelines per fetch */ | |
1376 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1377 | fwater_hi = fwater_hi | (1 << 8); | |
1378 | ||
1379 | I915_WRITE(FW_BLC, fwater_lo); | |
1380 | I915_WRITE(FW_BLC2, fwater_hi); | |
1381 | ||
5209b1f4 ID |
1382 | if (enabled) |
1383 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1384 | } |
1385 | ||
feb56b93 | 1386 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1387 | { |
46ba614c | 1388 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1389 | struct drm_i915_private *dev_priv = dev->dev_private; |
1390 | struct drm_crtc *crtc; | |
241bfc38 | 1391 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1392 | uint32_t fwater_lo; |
1393 | int planea_wm; | |
1394 | ||
1395 | crtc = single_enabled_crtc(dev); | |
1396 | if (crtc == NULL) | |
1397 | return; | |
1398 | ||
6e3c9717 | 1399 | adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode; |
241bfc38 | 1400 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 1401 | &i845_wm_info, |
b445e3b0 | 1402 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1403 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1404 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1405 | fwater_lo |= (3<<8) | planea_wm; | |
1406 | ||
1407 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1408 | ||
1409 | I915_WRITE(FW_BLC, fwater_lo); | |
1410 | } | |
1411 | ||
3658729a VS |
1412 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1413 | struct drm_crtc *crtc) | |
801bcfff PZ |
1414 | { |
1415 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1416 | uint32_t pixel_rate; |
801bcfff | 1417 | |
6e3c9717 | 1418 | pixel_rate = intel_crtc->config->base.adjusted_mode.crtc_clock; |
801bcfff PZ |
1419 | |
1420 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1421 | * adjust the pixel_rate here. */ | |
1422 | ||
6e3c9717 | 1423 | if (intel_crtc->config->pch_pfit.enabled) { |
801bcfff | 1424 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
6e3c9717 | 1425 | uint32_t pfit_size = intel_crtc->config->pch_pfit.size; |
801bcfff | 1426 | |
6e3c9717 ACO |
1427 | pipe_w = intel_crtc->config->pipe_src_w; |
1428 | pipe_h = intel_crtc->config->pipe_src_h; | |
801bcfff PZ |
1429 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1430 | pfit_h = pfit_size & 0xFFFF; | |
1431 | if (pipe_w < pfit_w) | |
1432 | pipe_w = pfit_w; | |
1433 | if (pipe_h < pfit_h) | |
1434 | pipe_h = pfit_h; | |
1435 | ||
1436 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1437 | pfit_w * pfit_h); | |
1438 | } | |
1439 | ||
1440 | return pixel_rate; | |
1441 | } | |
1442 | ||
37126462 | 1443 | /* latency must be in 0.1us units. */ |
23297044 | 1444 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1445 | uint32_t latency) |
1446 | { | |
1447 | uint64_t ret; | |
1448 | ||
3312ba65 VS |
1449 | if (WARN(latency == 0, "Latency value missing\n")) |
1450 | return UINT_MAX; | |
1451 | ||
801bcfff PZ |
1452 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1453 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1454 | ||
1455 | return ret; | |
1456 | } | |
1457 | ||
37126462 | 1458 | /* latency must be in 0.1us units. */ |
23297044 | 1459 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1460 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1461 | uint32_t latency) | |
1462 | { | |
1463 | uint32_t ret; | |
1464 | ||
3312ba65 VS |
1465 | if (WARN(latency == 0, "Latency value missing\n")) |
1466 | return UINT_MAX; | |
1467 | ||
801bcfff PZ |
1468 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1469 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1470 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1471 | return ret; | |
1472 | } | |
1473 | ||
23297044 | 1474 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1475 | uint8_t bytes_per_pixel) |
1476 | { | |
1477 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1478 | } | |
1479 | ||
2ac96d2a PB |
1480 | struct skl_pipe_wm_parameters { |
1481 | bool active; | |
1482 | uint32_t pipe_htotal; | |
1483 | uint32_t pixel_rate; /* in KHz */ | |
1484 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1485 | struct intel_plane_wm_parameters cursor; | |
1486 | }; | |
1487 | ||
820c1980 | 1488 | struct ilk_pipe_wm_parameters { |
801bcfff | 1489 | bool active; |
801bcfff PZ |
1490 | uint32_t pipe_htotal; |
1491 | uint32_t pixel_rate; | |
c35426d2 VS |
1492 | struct intel_plane_wm_parameters pri; |
1493 | struct intel_plane_wm_parameters spr; | |
1494 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1495 | }; |
1496 | ||
820c1980 | 1497 | struct ilk_wm_maximums { |
cca32e9a PZ |
1498 | uint16_t pri; |
1499 | uint16_t spr; | |
1500 | uint16_t cur; | |
1501 | uint16_t fbc; | |
1502 | }; | |
1503 | ||
240264f4 VS |
1504 | /* used in computing the new watermarks state */ |
1505 | struct intel_wm_config { | |
1506 | unsigned int num_pipes_active; | |
1507 | bool sprites_enabled; | |
1508 | bool sprites_scaled; | |
240264f4 VS |
1509 | }; |
1510 | ||
37126462 VS |
1511 | /* |
1512 | * For both WM_PIPE and WM_LP. | |
1513 | * mem_value must be in 0.1us units. | |
1514 | */ | |
820c1980 | 1515 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1516 | uint32_t mem_value, |
1517 | bool is_lp) | |
801bcfff | 1518 | { |
cca32e9a PZ |
1519 | uint32_t method1, method2; |
1520 | ||
c35426d2 | 1521 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
1522 | return 0; |
1523 | ||
23297044 | 1524 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1525 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
1526 | mem_value); |
1527 | ||
1528 | if (!is_lp) | |
1529 | return method1; | |
1530 | ||
23297044 | 1531 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 1532 | params->pipe_htotal, |
c35426d2 VS |
1533 | params->pri.horiz_pixels, |
1534 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
1535 | mem_value); |
1536 | ||
1537 | return min(method1, method2); | |
801bcfff PZ |
1538 | } |
1539 | ||
37126462 VS |
1540 | /* |
1541 | * For both WM_PIPE and WM_LP. | |
1542 | * mem_value must be in 0.1us units. | |
1543 | */ | |
820c1980 | 1544 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1545 | uint32_t mem_value) |
1546 | { | |
1547 | uint32_t method1, method2; | |
1548 | ||
c35426d2 | 1549 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
1550 | return 0; |
1551 | ||
23297044 | 1552 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 1553 | params->spr.bytes_per_pixel, |
801bcfff | 1554 | mem_value); |
23297044 | 1555 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 1556 | params->pipe_htotal, |
c35426d2 VS |
1557 | params->spr.horiz_pixels, |
1558 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
1559 | mem_value); |
1560 | return min(method1, method2); | |
1561 | } | |
1562 | ||
37126462 VS |
1563 | /* |
1564 | * For both WM_PIPE and WM_LP. | |
1565 | * mem_value must be in 0.1us units. | |
1566 | */ | |
820c1980 | 1567 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
1568 | uint32_t mem_value) |
1569 | { | |
c35426d2 | 1570 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
1571 | return 0; |
1572 | ||
23297044 | 1573 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 1574 | params->pipe_htotal, |
c35426d2 VS |
1575 | params->cur.horiz_pixels, |
1576 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
1577 | mem_value); |
1578 | } | |
1579 | ||
cca32e9a | 1580 | /* Only for WM_LP. */ |
820c1980 | 1581 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 1582 | uint32_t pri_val) |
cca32e9a | 1583 | { |
c35426d2 | 1584 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
1585 | return 0; |
1586 | ||
23297044 | 1587 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
1588 | params->pri.horiz_pixels, |
1589 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
1590 | } |
1591 | ||
158ae64f VS |
1592 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
1593 | { | |
416f4727 VS |
1594 | if (INTEL_INFO(dev)->gen >= 8) |
1595 | return 3072; | |
1596 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
1597 | return 768; |
1598 | else | |
1599 | return 512; | |
1600 | } | |
1601 | ||
4e975081 VS |
1602 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
1603 | int level, bool is_sprite) | |
1604 | { | |
1605 | if (INTEL_INFO(dev)->gen >= 8) | |
1606 | /* BDW primary/sprite plane watermarks */ | |
1607 | return level == 0 ? 255 : 2047; | |
1608 | else if (INTEL_INFO(dev)->gen >= 7) | |
1609 | /* IVB/HSW primary/sprite plane watermarks */ | |
1610 | return level == 0 ? 127 : 1023; | |
1611 | else if (!is_sprite) | |
1612 | /* ILK/SNB primary plane watermarks */ | |
1613 | return level == 0 ? 127 : 511; | |
1614 | else | |
1615 | /* ILK/SNB sprite plane watermarks */ | |
1616 | return level == 0 ? 63 : 255; | |
1617 | } | |
1618 | ||
1619 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
1620 | int level) | |
1621 | { | |
1622 | if (INTEL_INFO(dev)->gen >= 7) | |
1623 | return level == 0 ? 63 : 255; | |
1624 | else | |
1625 | return level == 0 ? 31 : 63; | |
1626 | } | |
1627 | ||
1628 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
1629 | { | |
1630 | if (INTEL_INFO(dev)->gen >= 8) | |
1631 | return 31; | |
1632 | else | |
1633 | return 15; | |
1634 | } | |
1635 | ||
158ae64f VS |
1636 | /* Calculate the maximum primary/sprite plane watermark */ |
1637 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
1638 | int level, | |
240264f4 | 1639 | const struct intel_wm_config *config, |
158ae64f VS |
1640 | enum intel_ddb_partitioning ddb_partitioning, |
1641 | bool is_sprite) | |
1642 | { | |
1643 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
1644 | |
1645 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 1646 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
1647 | return 0; |
1648 | ||
1649 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 1650 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
1651 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
1652 | ||
1653 | /* | |
1654 | * For some reason the non self refresh | |
1655 | * FIFO size is only half of the self | |
1656 | * refresh FIFO size on ILK/SNB. | |
1657 | */ | |
1658 | if (INTEL_INFO(dev)->gen <= 6) | |
1659 | fifo_size /= 2; | |
1660 | } | |
1661 | ||
240264f4 | 1662 | if (config->sprites_enabled) { |
158ae64f VS |
1663 | /* level 0 is always calculated with 1:1 split */ |
1664 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
1665 | if (is_sprite) | |
1666 | fifo_size *= 5; | |
1667 | fifo_size /= 6; | |
1668 | } else { | |
1669 | fifo_size /= 2; | |
1670 | } | |
1671 | } | |
1672 | ||
1673 | /* clamp to max that the registers can hold */ | |
4e975081 | 1674 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
1675 | } |
1676 | ||
1677 | /* Calculate the maximum cursor plane watermark */ | |
1678 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
1679 | int level, |
1680 | const struct intel_wm_config *config) | |
158ae64f VS |
1681 | { |
1682 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 1683 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
1684 | return 64; |
1685 | ||
1686 | /* otherwise just report max that registers can hold */ | |
4e975081 | 1687 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
1688 | } |
1689 | ||
d34ff9c6 | 1690 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
1691 | int level, |
1692 | const struct intel_wm_config *config, | |
1693 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 1694 | struct ilk_wm_maximums *max) |
158ae64f | 1695 | { |
240264f4 VS |
1696 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
1697 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
1698 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 1699 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
1700 | } |
1701 | ||
a3cb4048 VS |
1702 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
1703 | int level, | |
1704 | struct ilk_wm_maximums *max) | |
1705 | { | |
1706 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
1707 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
1708 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
1709 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
1710 | } | |
1711 | ||
d9395655 | 1712 | static bool ilk_validate_wm_level(int level, |
820c1980 | 1713 | const struct ilk_wm_maximums *max, |
d9395655 | 1714 | struct intel_wm_level *result) |
a9786a11 VS |
1715 | { |
1716 | bool ret; | |
1717 | ||
1718 | /* already determined to be invalid? */ | |
1719 | if (!result->enable) | |
1720 | return false; | |
1721 | ||
1722 | result->enable = result->pri_val <= max->pri && | |
1723 | result->spr_val <= max->spr && | |
1724 | result->cur_val <= max->cur; | |
1725 | ||
1726 | ret = result->enable; | |
1727 | ||
1728 | /* | |
1729 | * HACK until we can pre-compute everything, | |
1730 | * and thus fail gracefully if LP0 watermarks | |
1731 | * are exceeded... | |
1732 | */ | |
1733 | if (level == 0 && !result->enable) { | |
1734 | if (result->pri_val > max->pri) | |
1735 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
1736 | level, result->pri_val, max->pri); | |
1737 | if (result->spr_val > max->spr) | |
1738 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
1739 | level, result->spr_val, max->spr); | |
1740 | if (result->cur_val > max->cur) | |
1741 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
1742 | level, result->cur_val, max->cur); | |
1743 | ||
1744 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
1745 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
1746 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
1747 | result->enable = true; | |
1748 | } | |
1749 | ||
a9786a11 VS |
1750 | return ret; |
1751 | } | |
1752 | ||
d34ff9c6 | 1753 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 1754 | int level, |
820c1980 | 1755 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 1756 | struct intel_wm_level *result) |
6f5ddd17 VS |
1757 | { |
1758 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
1759 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
1760 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
1761 | ||
1762 | /* WM1+ latency values stored in 0.5us units */ | |
1763 | if (level > 0) { | |
1764 | pri_latency *= 5; | |
1765 | spr_latency *= 5; | |
1766 | cur_latency *= 5; | |
1767 | } | |
1768 | ||
1769 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
1770 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
1771 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
1772 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
1773 | result->enable = true; | |
1774 | } | |
1775 | ||
801bcfff PZ |
1776 | static uint32_t |
1777 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
1778 | { |
1779 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 1780 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
6e3c9717 | 1781 | struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode; |
85a02deb | 1782 | u32 linetime, ips_linetime; |
1f8eeabf | 1783 | |
3ef00284 | 1784 | if (!intel_crtc->active) |
801bcfff | 1785 | return 0; |
1011d8c4 | 1786 | |
1f8eeabf ED |
1787 | /* The WM are computed with base on how long it takes to fill a single |
1788 | * row at the given clock rate, multiplied by 8. | |
1789 | * */ | |
fec8cba3 JB |
1790 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
1791 | mode->crtc_clock); | |
1792 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 1793 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 1794 | |
801bcfff PZ |
1795 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
1796 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
1797 | } |
1798 | ||
2af30a5c | 1799 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
1800 | { |
1801 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1802 | ||
2af30a5c PB |
1803 | if (IS_GEN9(dev)) { |
1804 | uint32_t val; | |
4f947386 | 1805 | int ret, i; |
367294be | 1806 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
1807 | |
1808 | /* read the first set of memory latencies[0:3] */ | |
1809 | val = 0; /* data0 to be programmed to 0 for first set */ | |
1810 | mutex_lock(&dev_priv->rps.hw_lock); | |
1811 | ret = sandybridge_pcode_read(dev_priv, | |
1812 | GEN9_PCODE_READ_MEM_LATENCY, | |
1813 | &val); | |
1814 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1815 | ||
1816 | if (ret) { | |
1817 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1818 | return; | |
1819 | } | |
1820 | ||
1821 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1822 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1823 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1824 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1825 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1826 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1827 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1828 | ||
1829 | /* read the second set of memory latencies[4:7] */ | |
1830 | val = 1; /* data0 to be programmed to 1 for second set */ | |
1831 | mutex_lock(&dev_priv->rps.hw_lock); | |
1832 | ret = sandybridge_pcode_read(dev_priv, | |
1833 | GEN9_PCODE_READ_MEM_LATENCY, | |
1834 | &val); | |
1835 | mutex_unlock(&dev_priv->rps.hw_lock); | |
1836 | if (ret) { | |
1837 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
1838 | return; | |
1839 | } | |
1840 | ||
1841 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
1842 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
1843 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1844 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
1845 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1846 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
1847 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
1848 | ||
367294be | 1849 | /* |
6f97235b DL |
1850 | * WaWmMemoryReadLatency:skl |
1851 | * | |
367294be VK |
1852 | * punit doesn't take into account the read latency so we need |
1853 | * to add 2us to the various latency levels we retrieve from | |
1854 | * the punit. | |
1855 | * - W0 is a bit special in that it's the only level that | |
1856 | * can't be disabled if we want to have display working, so | |
1857 | * we always add 2us there. | |
1858 | * - For levels >=1, punit returns 0us latency when they are | |
1859 | * disabled, so we respect that and don't add 2us then | |
4f947386 VK |
1860 | * |
1861 | * Additionally, if a level n (n > 1) has a 0us latency, all | |
1862 | * levels m (m >= n) need to be disabled. We make sure to | |
1863 | * sanitize the values out of the punit to satisfy this | |
1864 | * requirement. | |
367294be VK |
1865 | */ |
1866 | wm[0] += 2; | |
1867 | for (level = 1; level <= max_level; level++) | |
1868 | if (wm[level] != 0) | |
1869 | wm[level] += 2; | |
4f947386 VK |
1870 | else { |
1871 | for (i = level + 1; i <= max_level; i++) | |
1872 | wm[i] = 0; | |
367294be | 1873 | |
4f947386 VK |
1874 | break; |
1875 | } | |
2af30a5c | 1876 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
1877 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
1878 | ||
1879 | wm[0] = (sskpd >> 56) & 0xFF; | |
1880 | if (wm[0] == 0) | |
1881 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
1882 | wm[1] = (sskpd >> 4) & 0xFF; |
1883 | wm[2] = (sskpd >> 12) & 0xFF; | |
1884 | wm[3] = (sskpd >> 20) & 0x1FF; | |
1885 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
1886 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1887 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
1888 | ||
1889 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
1890 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
1891 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
1892 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
1893 | } else if (INTEL_INFO(dev)->gen >= 5) { |
1894 | uint32_t mltr = I915_READ(MLTR_ILK); | |
1895 | ||
1896 | /* ILK primary LP0 latency is 700 ns */ | |
1897 | wm[0] = 7; | |
1898 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
1899 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
1900 | } |
1901 | } | |
1902 | ||
53615a5e VS |
1903 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
1904 | { | |
1905 | /* ILK sprite LP0 latency is 1300 ns */ | |
1906 | if (INTEL_INFO(dev)->gen == 5) | |
1907 | wm[0] = 13; | |
1908 | } | |
1909 | ||
1910 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
1911 | { | |
1912 | /* ILK cursor LP0 latency is 1300 ns */ | |
1913 | if (INTEL_INFO(dev)->gen == 5) | |
1914 | wm[0] = 13; | |
1915 | ||
1916 | /* WaDoubleCursorLP3Latency:ivb */ | |
1917 | if (IS_IVYBRIDGE(dev)) | |
1918 | wm[3] *= 2; | |
1919 | } | |
1920 | ||
546c81fd | 1921 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 1922 | { |
26ec971e | 1923 | /* how many WM levels are we expecting */ |
2af30a5c PB |
1924 | if (IS_GEN9(dev)) |
1925 | return 7; | |
1926 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 1927 | return 4; |
26ec971e | 1928 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 1929 | return 3; |
26ec971e | 1930 | else |
ad0d6dc4 VS |
1931 | return 2; |
1932 | } | |
7526ed79 | 1933 | |
ad0d6dc4 VS |
1934 | static void intel_print_wm_latency(struct drm_device *dev, |
1935 | const char *name, | |
2af30a5c | 1936 | const uint16_t wm[8]) |
ad0d6dc4 VS |
1937 | { |
1938 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
1939 | |
1940 | for (level = 0; level <= max_level; level++) { | |
1941 | unsigned int latency = wm[level]; | |
1942 | ||
1943 | if (latency == 0) { | |
1944 | DRM_ERROR("%s WM%d latency not provided\n", | |
1945 | name, level); | |
1946 | continue; | |
1947 | } | |
1948 | ||
2af30a5c PB |
1949 | /* |
1950 | * - latencies are in us on gen9. | |
1951 | * - before then, WM1+ latency values are in 0.5us units | |
1952 | */ | |
1953 | if (IS_GEN9(dev)) | |
1954 | latency *= 10; | |
1955 | else if (level > 0) | |
26ec971e VS |
1956 | latency *= 5; |
1957 | ||
1958 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
1959 | name, level, wm[level], | |
1960 | latency / 10, latency % 10); | |
1961 | } | |
1962 | } | |
1963 | ||
e95a2f75 VS |
1964 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
1965 | uint16_t wm[5], uint16_t min) | |
1966 | { | |
1967 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
1968 | ||
1969 | if (wm[0] >= min) | |
1970 | return false; | |
1971 | ||
1972 | wm[0] = max(wm[0], min); | |
1973 | for (level = 1; level <= max_level; level++) | |
1974 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
1975 | ||
1976 | return true; | |
1977 | } | |
1978 | ||
1979 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
1980 | { | |
1981 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1982 | bool changed; | |
1983 | ||
1984 | /* | |
1985 | * The BIOS provided WM memory latency values are often | |
1986 | * inadequate for high resolution displays. Adjust them. | |
1987 | */ | |
1988 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
1989 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
1990 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
1991 | ||
1992 | if (!changed) | |
1993 | return; | |
1994 | ||
1995 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
1996 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
1997 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
1998 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
1999 | } | |
2000 | ||
fa50ad61 | 2001 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2002 | { |
2003 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2004 | ||
2005 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2006 | ||
2007 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2008 | sizeof(dev_priv->wm.pri_latency)); | |
2009 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2010 | sizeof(dev_priv->wm.pri_latency)); | |
2011 | ||
2012 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2013 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2014 | |
2015 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2016 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2017 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2018 | |
2019 | if (IS_GEN6(dev)) | |
2020 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2021 | } |
2022 | ||
2af30a5c PB |
2023 | static void skl_setup_wm_latency(struct drm_device *dev) |
2024 | { | |
2025 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2026 | ||
2027 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
2028 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
2029 | } | |
2030 | ||
820c1980 | 2031 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 2032 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 2033 | { |
7c4a395f VS |
2034 | struct drm_device *dev = crtc->dev; |
2035 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2036 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2037 | struct drm_plane *plane; |
1011d8c4 | 2038 | |
3ef00284 | 2039 | if (!intel_crtc->active) |
2a44b76b | 2040 | return; |
801bcfff | 2041 | |
2a44b76b | 2042 | p->active = true; |
6e3c9717 | 2043 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
2a44b76b | 2044 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); |
c9f038a1 MR |
2045 | |
2046 | if (crtc->primary->state->fb) { | |
2047 | p->pri.enabled = true; | |
2048 | p->pri.bytes_per_pixel = | |
2049 | crtc->primary->state->fb->bits_per_pixel / 8; | |
2050 | } else { | |
2051 | p->pri.enabled = false; | |
2052 | p->pri.bytes_per_pixel = 0; | |
2053 | } | |
2054 | ||
2055 | if (crtc->cursor->state->fb) { | |
2056 | p->cur.enabled = true; | |
2057 | p->cur.bytes_per_pixel = 4; | |
2058 | } else { | |
2059 | p->cur.enabled = false; | |
2060 | p->cur.bytes_per_pixel = 0; | |
2061 | } | |
6e3c9717 | 2062 | p->pri.horiz_pixels = intel_crtc->config->pipe_src_w; |
3dd512fb | 2063 | p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w; |
7c4a395f | 2064 | |
af2b653b | 2065 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 2066 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 2067 | |
2a44b76b | 2068 | if (intel_plane->pipe == pipe) { |
7c4a395f | 2069 | p->spr = intel_plane->wm; |
2a44b76b VS |
2070 | break; |
2071 | } | |
2072 | } | |
2073 | } | |
2074 | ||
2075 | static void ilk_compute_wm_config(struct drm_device *dev, | |
2076 | struct intel_wm_config *config) | |
2077 | { | |
2078 | struct intel_crtc *intel_crtc; | |
2079 | ||
2080 | /* Compute the currently _active_ config */ | |
d3fcc808 | 2081 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 2082 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 2083 | |
2a44b76b VS |
2084 | if (!wm->pipe_enabled) |
2085 | continue; | |
cca32e9a | 2086 | |
2a44b76b VS |
2087 | config->sprites_enabled |= wm->sprites_enabled; |
2088 | config->sprites_scaled |= wm->sprites_scaled; | |
2089 | config->num_pipes_active++; | |
cca32e9a | 2090 | } |
801bcfff PZ |
2091 | } |
2092 | ||
0b2ae6d7 VS |
2093 | /* Compute new watermarks for the pipe */ |
2094 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2095 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2096 | struct intel_pipe_wm *pipe_wm) |
2097 | { | |
2098 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2099 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2100 | int level, max_level = ilk_wm_max_level(dev); |
2101 | /* LP0 watermark maximums depend on this pipe alone */ | |
2102 | struct intel_wm_config config = { | |
2103 | .num_pipes_active = 1, | |
2104 | .sprites_enabled = params->spr.enabled, | |
2105 | .sprites_scaled = params->spr.scaled, | |
2106 | }; | |
820c1980 | 2107 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2108 | |
2a44b76b VS |
2109 | pipe_wm->pipe_enabled = params->active; |
2110 | pipe_wm->sprites_enabled = params->spr.enabled; | |
2111 | pipe_wm->sprites_scaled = params->spr.scaled; | |
2112 | ||
7b39a0b7 VS |
2113 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2114 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2115 | max_level = 1; | |
2116 | ||
2117 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2118 | if (params->spr.scaled) | |
2119 | max_level = 0; | |
2120 | ||
a3cb4048 | 2121 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 2122 | |
a42a5719 | 2123 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2124 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2125 | |
a3cb4048 VS |
2126 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2127 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2128 | ||
0b2ae6d7 | 2129 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2130 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2131 | return false; | |
2132 | ||
2133 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2134 | ||
2135 | for (level = 1; level <= max_level; level++) { | |
2136 | struct intel_wm_level wm = {}; | |
2137 | ||
2138 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2139 | ||
2140 | /* | |
2141 | * Disable any watermark level that exceeds the | |
2142 | * register maximums since such watermarks are | |
2143 | * always invalid. | |
2144 | */ | |
2145 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2146 | break; | |
2147 | ||
2148 | pipe_wm->wm[level] = wm; | |
2149 | } | |
2150 | ||
2151 | return true; | |
0b2ae6d7 VS |
2152 | } |
2153 | ||
2154 | /* | |
2155 | * Merge the watermarks from all active pipes for a specific level. | |
2156 | */ | |
2157 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2158 | int level, | |
2159 | struct intel_wm_level *ret_wm) | |
2160 | { | |
2161 | const struct intel_crtc *intel_crtc; | |
2162 | ||
d52fea5b VS |
2163 | ret_wm->enable = true; |
2164 | ||
d3fcc808 | 2165 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2166 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2167 | const struct intel_wm_level *wm = &active->wm[level]; | |
2168 | ||
2169 | if (!active->pipe_enabled) | |
2170 | continue; | |
0b2ae6d7 | 2171 | |
d52fea5b VS |
2172 | /* |
2173 | * The watermark values may have been used in the past, | |
2174 | * so we must maintain them in the registers for some | |
2175 | * time even if the level is now disabled. | |
2176 | */ | |
0b2ae6d7 | 2177 | if (!wm->enable) |
d52fea5b | 2178 | ret_wm->enable = false; |
0b2ae6d7 VS |
2179 | |
2180 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2181 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2182 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2183 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2184 | } | |
0b2ae6d7 VS |
2185 | } |
2186 | ||
2187 | /* | |
2188 | * Merge all low power watermarks for all active pipes. | |
2189 | */ | |
2190 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2191 | const struct intel_wm_config *config, |
820c1980 | 2192 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2193 | struct intel_pipe_wm *merged) |
2194 | { | |
2195 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2196 | int last_enabled_level = max_level; |
0b2ae6d7 | 2197 | |
0ba22e26 VS |
2198 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2199 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2200 | config->num_pipes_active > 1) | |
2201 | return; | |
2202 | ||
6c8b6c28 VS |
2203 | /* ILK: FBC WM must be disabled always */ |
2204 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2205 | |
2206 | /* merge each WM1+ level */ | |
2207 | for (level = 1; level <= max_level; level++) { | |
2208 | struct intel_wm_level *wm = &merged->wm[level]; | |
2209 | ||
2210 | ilk_merge_wm_level(dev, level, wm); | |
2211 | ||
d52fea5b VS |
2212 | if (level > last_enabled_level) |
2213 | wm->enable = false; | |
2214 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2215 | /* make sure all following levels get disabled */ | |
2216 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2217 | |
2218 | /* | |
2219 | * The spec says it is preferred to disable | |
2220 | * FBC WMs instead of disabling a WM level. | |
2221 | */ | |
2222 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2223 | if (wm->enable) |
2224 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2225 | wm->fbc_val = 0; |
2226 | } | |
2227 | } | |
6c8b6c28 VS |
2228 | |
2229 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2230 | /* | |
2231 | * FIXME this is racy. FBC might get enabled later. | |
2232 | * What we should check here is whether FBC can be | |
2233 | * enabled sometime later. | |
2234 | */ | |
2235 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2236 | for (level = 2; level <= max_level; level++) { | |
2237 | struct intel_wm_level *wm = &merged->wm[level]; | |
2238 | ||
2239 | wm->enable = false; | |
2240 | } | |
2241 | } | |
0b2ae6d7 VS |
2242 | } |
2243 | ||
b380ca3c VS |
2244 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2245 | { | |
2246 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2247 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2248 | } | |
2249 | ||
a68d68ee VS |
2250 | /* The value we need to program into the WM_LPx latency field */ |
2251 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2252 | { | |
2253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2254 | ||
a42a5719 | 2255 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2256 | return 2 * level; |
2257 | else | |
2258 | return dev_priv->wm.pri_latency[level]; | |
2259 | } | |
2260 | ||
820c1980 | 2261 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2262 | const struct intel_pipe_wm *merged, |
609cedef | 2263 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2264 | struct ilk_wm_values *results) |
801bcfff | 2265 | { |
0b2ae6d7 VS |
2266 | struct intel_crtc *intel_crtc; |
2267 | int level, wm_lp; | |
cca32e9a | 2268 | |
0362c781 | 2269 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2270 | results->partitioning = partitioning; |
cca32e9a | 2271 | |
0b2ae6d7 | 2272 | /* LP1+ register values */ |
cca32e9a | 2273 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2274 | const struct intel_wm_level *r; |
801bcfff | 2275 | |
b380ca3c | 2276 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2277 | |
0362c781 | 2278 | r = &merged->wm[level]; |
cca32e9a | 2279 | |
d52fea5b VS |
2280 | /* |
2281 | * Maintain the watermark values even if the level is | |
2282 | * disabled. Doing otherwise could cause underruns. | |
2283 | */ | |
2284 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2285 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2286 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2287 | r->cur_val; | |
2288 | ||
d52fea5b VS |
2289 | if (r->enable) |
2290 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2291 | ||
416f4727 VS |
2292 | if (INTEL_INFO(dev)->gen >= 8) |
2293 | results->wm_lp[wm_lp - 1] |= | |
2294 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2295 | else | |
2296 | results->wm_lp[wm_lp - 1] |= | |
2297 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2298 | ||
d52fea5b VS |
2299 | /* |
2300 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2301 | * level is disabled. Doing otherwise could cause underruns. | |
2302 | */ | |
6cef2b8a VS |
2303 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2304 | WARN_ON(wm_lp != 1); | |
2305 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2306 | } else | |
2307 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2308 | } |
801bcfff | 2309 | |
0b2ae6d7 | 2310 | /* LP0 register values */ |
d3fcc808 | 2311 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2312 | enum pipe pipe = intel_crtc->pipe; |
2313 | const struct intel_wm_level *r = | |
2314 | &intel_crtc->wm.active.wm[0]; | |
2315 | ||
2316 | if (WARN_ON(!r->enable)) | |
2317 | continue; | |
2318 | ||
2319 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2320 | |
0b2ae6d7 VS |
2321 | results->wm_pipe[pipe] = |
2322 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2323 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2324 | r->cur_val; | |
801bcfff PZ |
2325 | } |
2326 | } | |
2327 | ||
861f3389 PZ |
2328 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2329 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2330 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2331 | struct intel_pipe_wm *r1, |
2332 | struct intel_pipe_wm *r2) | |
861f3389 | 2333 | { |
198a1e9b VS |
2334 | int level, max_level = ilk_wm_max_level(dev); |
2335 | int level1 = 0, level2 = 0; | |
861f3389 | 2336 | |
198a1e9b VS |
2337 | for (level = 1; level <= max_level; level++) { |
2338 | if (r1->wm[level].enable) | |
2339 | level1 = level; | |
2340 | if (r2->wm[level].enable) | |
2341 | level2 = level; | |
861f3389 PZ |
2342 | } |
2343 | ||
198a1e9b VS |
2344 | if (level1 == level2) { |
2345 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2346 | return r2; |
2347 | else | |
2348 | return r1; | |
198a1e9b | 2349 | } else if (level1 > level2) { |
861f3389 PZ |
2350 | return r1; |
2351 | } else { | |
2352 | return r2; | |
2353 | } | |
2354 | } | |
2355 | ||
49a687c4 VS |
2356 | /* dirty bits used to track which watermarks need changes */ |
2357 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2358 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2359 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2360 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2361 | #define WM_DIRTY_FBC (1 << 24) | |
2362 | #define WM_DIRTY_DDB (1 << 25) | |
2363 | ||
055e393f | 2364 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2365 | const struct ilk_wm_values *old, |
2366 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2367 | { |
2368 | unsigned int dirty = 0; | |
2369 | enum pipe pipe; | |
2370 | int wm_lp; | |
2371 | ||
055e393f | 2372 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2373 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2374 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2375 | /* Must disable LP1+ watermarks too */ | |
2376 | dirty |= WM_DIRTY_LP_ALL; | |
2377 | } | |
2378 | ||
2379 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2380 | dirty |= WM_DIRTY_PIPE(pipe); | |
2381 | /* Must disable LP1+ watermarks too */ | |
2382 | dirty |= WM_DIRTY_LP_ALL; | |
2383 | } | |
2384 | } | |
2385 | ||
2386 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2387 | dirty |= WM_DIRTY_FBC; | |
2388 | /* Must disable LP1+ watermarks too */ | |
2389 | dirty |= WM_DIRTY_LP_ALL; | |
2390 | } | |
2391 | ||
2392 | if (old->partitioning != new->partitioning) { | |
2393 | dirty |= WM_DIRTY_DDB; | |
2394 | /* Must disable LP1+ watermarks too */ | |
2395 | dirty |= WM_DIRTY_LP_ALL; | |
2396 | } | |
2397 | ||
2398 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2399 | if (dirty & WM_DIRTY_LP_ALL) | |
2400 | return dirty; | |
2401 | ||
2402 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2403 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2404 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2405 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2406 | break; | |
2407 | } | |
2408 | ||
2409 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2410 | for (; wm_lp <= 3; wm_lp++) | |
2411 | dirty |= WM_DIRTY_LP(wm_lp); | |
2412 | ||
2413 | return dirty; | |
2414 | } | |
2415 | ||
8553c18e VS |
2416 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2417 | unsigned int dirty) | |
801bcfff | 2418 | { |
820c1980 | 2419 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2420 | bool changed = false; |
801bcfff | 2421 | |
facd619b VS |
2422 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2423 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2424 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2425 | changed = true; |
facd619b VS |
2426 | } |
2427 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2428 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2429 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2430 | changed = true; |
facd619b VS |
2431 | } |
2432 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2433 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2434 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2435 | changed = true; |
facd619b | 2436 | } |
801bcfff | 2437 | |
facd619b VS |
2438 | /* |
2439 | * Don't touch WM1S_LP_EN here. | |
2440 | * Doing so could cause underruns. | |
2441 | */ | |
6cef2b8a | 2442 | |
8553c18e VS |
2443 | return changed; |
2444 | } | |
2445 | ||
2446 | /* | |
2447 | * The spec says we shouldn't write when we don't need, because every write | |
2448 | * causes WMs to be re-evaluated, expending some power. | |
2449 | */ | |
820c1980 ID |
2450 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2451 | struct ilk_wm_values *results) | |
8553c18e VS |
2452 | { |
2453 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2454 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2455 | unsigned int dirty; |
2456 | uint32_t val; | |
2457 | ||
055e393f | 2458 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2459 | if (!dirty) |
2460 | return; | |
2461 | ||
2462 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2463 | ||
49a687c4 | 2464 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2465 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2466 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2467 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2468 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2469 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2470 | ||
49a687c4 | 2471 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2472 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2473 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2474 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2475 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2476 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2477 | ||
49a687c4 | 2478 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2479 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2480 | val = I915_READ(WM_MISC); |
2481 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2482 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2483 | else | |
2484 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2485 | I915_WRITE(WM_MISC, val); | |
2486 | } else { | |
2487 | val = I915_READ(DISP_ARB_CTL2); | |
2488 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2489 | val &= ~DISP_DATA_PARTITION_5_6; | |
2490 | else | |
2491 | val |= DISP_DATA_PARTITION_5_6; | |
2492 | I915_WRITE(DISP_ARB_CTL2, val); | |
2493 | } | |
1011d8c4 PZ |
2494 | } |
2495 | ||
49a687c4 | 2496 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2497 | val = I915_READ(DISP_ARB_CTL); |
2498 | if (results->enable_fbc_wm) | |
2499 | val &= ~DISP_FBC_WM_DIS; | |
2500 | else | |
2501 | val |= DISP_FBC_WM_DIS; | |
2502 | I915_WRITE(DISP_ARB_CTL, val); | |
2503 | } | |
2504 | ||
954911eb ID |
2505 | if (dirty & WM_DIRTY_LP(1) && |
2506 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2507 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2508 | ||
2509 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2510 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2511 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2512 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2513 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2514 | } | |
801bcfff | 2515 | |
facd619b | 2516 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2517 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2518 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2519 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2520 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2521 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2522 | |
2523 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2524 | } |
2525 | ||
8553c18e VS |
2526 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2527 | { | |
2528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2529 | ||
2530 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2531 | } | |
2532 | ||
b9cec075 DL |
2533 | /* |
2534 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2535 | * different active planes. | |
2536 | */ | |
2537 | ||
2538 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
2539 | ||
2540 | static void | |
2541 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
2542 | struct drm_crtc *for_crtc, | |
2543 | const struct intel_wm_config *config, | |
2544 | const struct skl_pipe_wm_parameters *params, | |
2545 | struct skl_ddb_entry *alloc /* out */) | |
2546 | { | |
2547 | struct drm_crtc *crtc; | |
2548 | unsigned int pipe_size, ddb_size; | |
2549 | int nth_active_pipe; | |
2550 | ||
2551 | if (!params->active) { | |
2552 | alloc->start = 0; | |
2553 | alloc->end = 0; | |
2554 | return; | |
2555 | } | |
2556 | ||
2557 | ddb_size = SKL_DDB_SIZE; | |
2558 | ||
2559 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
2560 | ||
2561 | nth_active_pipe = 0; | |
2562 | for_each_crtc(dev, crtc) { | |
3ef00284 | 2563 | if (!to_intel_crtc(crtc)->active) |
b9cec075 DL |
2564 | continue; |
2565 | ||
2566 | if (crtc == for_crtc) | |
2567 | break; | |
2568 | ||
2569 | nth_active_pipe++; | |
2570 | } | |
2571 | ||
2572 | pipe_size = ddb_size / config->num_pipes_active; | |
2573 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
16160e3d | 2574 | alloc->end = alloc->start + pipe_size; |
b9cec075 DL |
2575 | } |
2576 | ||
2577 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
2578 | { | |
2579 | if (config->num_pipes_active == 1) | |
2580 | return 32; | |
2581 | ||
2582 | return 8; | |
2583 | } | |
2584 | ||
a269c583 DL |
2585 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
2586 | { | |
2587 | entry->start = reg & 0x3ff; | |
2588 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
2589 | if (entry->end) |
2590 | entry->end += 1; | |
a269c583 DL |
2591 | } |
2592 | ||
08db6652 DL |
2593 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
2594 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 2595 | { |
a269c583 DL |
2596 | enum pipe pipe; |
2597 | int plane; | |
2598 | u32 val; | |
2599 | ||
2600 | for_each_pipe(dev_priv, pipe) { | |
dd740780 | 2601 | for_each_plane(dev_priv, pipe, plane) { |
a269c583 DL |
2602 | val = I915_READ(PLANE_BUF_CFG(pipe, plane)); |
2603 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane], | |
2604 | val); | |
2605 | } | |
2606 | ||
2607 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
2608 | skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val); | |
2609 | } | |
2610 | } | |
2611 | ||
b9cec075 DL |
2612 | static unsigned int |
2613 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) | |
2614 | { | |
2615 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; | |
2616 | } | |
2617 | ||
2618 | /* | |
2619 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
2620 | * a 8192x4096@32bpp framebuffer: | |
2621 | * 3 * 4096 * 8192 * 4 < 2^32 | |
2622 | */ | |
2623 | static unsigned int | |
2624 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, | |
2625 | const struct skl_pipe_wm_parameters *params) | |
2626 | { | |
2627 | unsigned int total_data_rate = 0; | |
2628 | int plane; | |
2629 | ||
2630 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
2631 | const struct intel_plane_wm_parameters *p; | |
2632 | ||
2633 | p = ¶ms->plane[plane]; | |
2634 | if (!p->enabled) | |
2635 | continue; | |
2636 | ||
2637 | total_data_rate += skl_plane_relative_data_rate(p); | |
2638 | } | |
2639 | ||
2640 | return total_data_rate; | |
2641 | } | |
2642 | ||
2643 | static void | |
2644 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, | |
2645 | const struct intel_wm_config *config, | |
2646 | const struct skl_pipe_wm_parameters *params, | |
2647 | struct skl_ddb_allocation *ddb /* out */) | |
2648 | { | |
2649 | struct drm_device *dev = crtc->dev; | |
dd740780 | 2650 | struct drm_i915_private *dev_priv = dev->dev_private; |
b9cec075 DL |
2651 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2652 | enum pipe pipe = intel_crtc->pipe; | |
34bb56af | 2653 | struct skl_ddb_entry *alloc = &ddb->pipe[pipe]; |
b9cec075 | 2654 | uint16_t alloc_size, start, cursor_blocks; |
80958155 | 2655 | uint16_t minimum[I915_MAX_PLANES]; |
b9cec075 DL |
2656 | unsigned int total_data_rate; |
2657 | int plane; | |
2658 | ||
34bb56af DL |
2659 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc); |
2660 | alloc_size = skl_ddb_entry_size(alloc); | |
b9cec075 DL |
2661 | if (alloc_size == 0) { |
2662 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
2663 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); | |
2664 | return; | |
2665 | } | |
2666 | ||
2667 | cursor_blocks = skl_cursor_allocation(config); | |
34bb56af DL |
2668 | ddb->cursor[pipe].start = alloc->end - cursor_blocks; |
2669 | ddb->cursor[pipe].end = alloc->end; | |
b9cec075 DL |
2670 | |
2671 | alloc_size -= cursor_blocks; | |
34bb56af | 2672 | alloc->end -= cursor_blocks; |
b9cec075 | 2673 | |
80958155 | 2674 | /* 1. Allocate the mininum required blocks for each active plane */ |
dd740780 | 2675 | for_each_plane(dev_priv, pipe, plane) { |
80958155 DL |
2676 | const struct intel_plane_wm_parameters *p; |
2677 | ||
2678 | p = ¶ms->plane[plane]; | |
2679 | if (!p->enabled) | |
2680 | continue; | |
2681 | ||
2682 | minimum[plane] = 8; | |
2683 | alloc_size -= minimum[plane]; | |
2684 | } | |
2685 | ||
b9cec075 | 2686 | /* |
80958155 DL |
2687 | * 2. Distribute the remaining space in proportion to the amount of |
2688 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
2689 | * |
2690 | * FIXME: we may not allocate every single block here. | |
2691 | */ | |
2692 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); | |
2693 | ||
34bb56af | 2694 | start = alloc->start; |
b9cec075 DL |
2695 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { |
2696 | const struct intel_plane_wm_parameters *p; | |
2697 | unsigned int data_rate; | |
2698 | uint16_t plane_blocks; | |
2699 | ||
2700 | p = ¶ms->plane[plane]; | |
2701 | if (!p->enabled) | |
2702 | continue; | |
2703 | ||
2704 | data_rate = skl_plane_relative_data_rate(p); | |
2705 | ||
2706 | /* | |
2707 | * promote the expression to 64 bits to avoid overflowing, the | |
2708 | * result is < available as data_rate / total_data_rate < 1 | |
2709 | */ | |
80958155 DL |
2710 | plane_blocks = minimum[plane]; |
2711 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, | |
2712 | total_data_rate); | |
b9cec075 DL |
2713 | |
2714 | ddb->plane[pipe][plane].start = start; | |
16160e3d | 2715 | ddb->plane[pipe][plane].end = start + plane_blocks; |
b9cec075 DL |
2716 | |
2717 | start += plane_blocks; | |
2718 | } | |
2719 | ||
2720 | } | |
2721 | ||
5cec258b | 2722 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config) |
2d41c0b5 PB |
2723 | { |
2724 | /* TODO: Take into account the scalers once we support them */ | |
2d112de7 | 2725 | return config->base.adjusted_mode.crtc_clock; |
2d41c0b5 PB |
2726 | } |
2727 | ||
2728 | /* | |
2729 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
2730 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
2731 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
2732 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
2733 | */ | |
2734 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
2735 | uint32_t latency) | |
2736 | { | |
2737 | uint32_t wm_intermediate_val, ret; | |
2738 | ||
2739 | if (latency == 0) | |
2740 | return UINT_MAX; | |
2741 | ||
d4c2aa60 | 2742 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512; |
2d41c0b5 PB |
2743 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); |
2744 | ||
2745 | return ret; | |
2746 | } | |
2747 | ||
2748 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
2749 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
0fda6568 | 2750 | uint64_t tiling, uint32_t latency) |
2d41c0b5 | 2751 | { |
d4c2aa60 TU |
2752 | uint32_t ret; |
2753 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2754 | uint32_t wm_intermediate_val; | |
2d41c0b5 PB |
2755 | |
2756 | if (latency == 0) | |
2757 | return UINT_MAX; | |
2758 | ||
2759 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
0fda6568 TU |
2760 | |
2761 | if (tiling == I915_FORMAT_MOD_Y_TILED || | |
2762 | tiling == I915_FORMAT_MOD_Yf_TILED) { | |
2763 | plane_bytes_per_line *= 4; | |
2764 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
2765 | plane_blocks_per_line /= 4; | |
2766 | } else { | |
2767 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); | |
2768 | } | |
2769 | ||
2d41c0b5 PB |
2770 | wm_intermediate_val = latency * pixel_rate; |
2771 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
d4c2aa60 | 2772 | plane_blocks_per_line; |
2d41c0b5 PB |
2773 | |
2774 | return ret; | |
2775 | } | |
2776 | ||
2d41c0b5 PB |
2777 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, |
2778 | const struct intel_crtc *intel_crtc) | |
2779 | { | |
2780 | struct drm_device *dev = intel_crtc->base.dev; | |
2781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2782 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
2783 | enum pipe pipe = intel_crtc->pipe; | |
2784 | ||
2785 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
2786 | sizeof(new_ddb->plane[pipe]))) | |
2787 | return true; | |
2788 | ||
2789 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], | |
2790 | sizeof(new_ddb->cursor[pipe]))) | |
2791 | return true; | |
2792 | ||
2793 | return false; | |
2794 | } | |
2795 | ||
2796 | static void skl_compute_wm_global_parameters(struct drm_device *dev, | |
2797 | struct intel_wm_config *config) | |
2798 | { | |
2799 | struct drm_crtc *crtc; | |
2800 | struct drm_plane *plane; | |
2801 | ||
2802 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3ef00284 | 2803 | config->num_pipes_active += to_intel_crtc(crtc)->active; |
2d41c0b5 PB |
2804 | |
2805 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
2806 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2807 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2808 | ||
2809 | config->sprites_enabled |= intel_plane->wm.enabled; | |
2810 | config->sprites_scaled |= intel_plane->wm.scaled; | |
2811 | } | |
2812 | } | |
2813 | ||
2814 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
2815 | struct skl_pipe_wm_parameters *p) | |
2816 | { | |
2817 | struct drm_device *dev = crtc->dev; | |
2818 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2819 | enum pipe pipe = intel_crtc->pipe; | |
2820 | struct drm_plane *plane; | |
0fda6568 | 2821 | struct drm_framebuffer *fb; |
2d41c0b5 PB |
2822 | int i = 1; /* Index for sprite planes start */ |
2823 | ||
3ef00284 | 2824 | p->active = intel_crtc->active; |
2d41c0b5 | 2825 | if (p->active) { |
6e3c9717 ACO |
2826 | p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal; |
2827 | p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config); | |
2d41c0b5 | 2828 | |
0fda6568 | 2829 | fb = crtc->primary->state->fb; |
c9f038a1 MR |
2830 | if (fb) { |
2831 | p->plane[0].enabled = true; | |
2832 | p->plane[0].bytes_per_pixel = fb->bits_per_pixel / 8; | |
0fda6568 | 2833 | p->plane[0].tiling = fb->modifier[0]; |
c9f038a1 MR |
2834 | } else { |
2835 | p->plane[0].enabled = false; | |
2836 | p->plane[0].bytes_per_pixel = 0; | |
2837 | p->plane[0].tiling = DRM_FORMAT_MOD_NONE; | |
2838 | } | |
2839 | p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w; | |
2840 | p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h; | |
2d41c0b5 | 2841 | |
c9f038a1 MR |
2842 | fb = crtc->cursor->state->fb; |
2843 | if (fb) { | |
2844 | p->cursor.enabled = true; | |
2845 | p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8; | |
2846 | p->cursor.horiz_pixels = crtc->cursor->state->crtc_w; | |
2847 | p->cursor.vert_pixels = crtc->cursor->state->crtc_h; | |
2848 | } else { | |
2849 | p->cursor.enabled = false; | |
2850 | p->cursor.bytes_per_pixel = 0; | |
2851 | p->cursor.horiz_pixels = 64; | |
2852 | p->cursor.vert_pixels = 64; | |
2853 | } | |
2d41c0b5 PB |
2854 | } |
2855 | ||
2856 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
2857 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
2858 | ||
a712f8eb SJ |
2859 | if (intel_plane->pipe == pipe && |
2860 | plane->type == DRM_PLANE_TYPE_OVERLAY) | |
2d41c0b5 PB |
2861 | p->plane[i++] = intel_plane->wm; |
2862 | } | |
2863 | } | |
2864 | ||
d4c2aa60 TU |
2865 | static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
2866 | struct skl_pipe_wm_parameters *p, | |
afb024aa DL |
2867 | struct intel_plane_wm_parameters *p_params, |
2868 | uint16_t ddb_allocation, | |
d4c2aa60 | 2869 | int level, |
afb024aa DL |
2870 | uint16_t *out_blocks, /* out */ |
2871 | uint8_t *out_lines /* out */) | |
2d41c0b5 | 2872 | { |
d4c2aa60 TU |
2873 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
2874 | uint32_t method1, method2; | |
2875 | uint32_t plane_bytes_per_line, plane_blocks_per_line; | |
2876 | uint32_t res_blocks, res_lines; | |
2877 | uint32_t selected_result; | |
2d41c0b5 | 2878 | |
d4c2aa60 | 2879 | if (latency == 0 || !p->active || !p_params->enabled) |
2d41c0b5 PB |
2880 | return false; |
2881 | ||
2882 | method1 = skl_wm_method1(p->pixel_rate, | |
2883 | p_params->bytes_per_pixel, | |
d4c2aa60 | 2884 | latency); |
2d41c0b5 PB |
2885 | method2 = skl_wm_method2(p->pixel_rate, |
2886 | p->pipe_htotal, | |
2887 | p_params->horiz_pixels, | |
2888 | p_params->bytes_per_pixel, | |
0fda6568 | 2889 | p_params->tiling, |
d4c2aa60 | 2890 | latency); |
2d41c0b5 PB |
2891 | |
2892 | plane_bytes_per_line = p_params->horiz_pixels * | |
2893 | p_params->bytes_per_pixel; | |
d4c2aa60 | 2894 | plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512); |
2d41c0b5 | 2895 | |
0fda6568 TU |
2896 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || |
2897 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) { | |
2898 | uint32_t y_tile_minimum = plane_blocks_per_line * 4; | |
2899 | selected_result = max(method2, y_tile_minimum); | |
2900 | } else { | |
2901 | if ((ddb_allocation / plane_blocks_per_line) >= 1) | |
2902 | selected_result = min(method1, method2); | |
2903 | else | |
2904 | selected_result = method1; | |
2905 | } | |
2d41c0b5 | 2906 | |
d4c2aa60 TU |
2907 | res_blocks = selected_result + 1; |
2908 | res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line); | |
e6d66171 | 2909 | |
0fda6568 TU |
2910 | if (level >= 1 && level <= 7) { |
2911 | if (p_params->tiling == I915_FORMAT_MOD_Y_TILED || | |
2912 | p_params->tiling == I915_FORMAT_MOD_Yf_TILED) | |
2913 | res_lines += 4; | |
2914 | else | |
2915 | res_blocks++; | |
2916 | } | |
e6d66171 | 2917 | |
d4c2aa60 | 2918 | if (res_blocks >= ddb_allocation || res_lines > 31) |
e6d66171 DL |
2919 | return false; |
2920 | ||
2921 | *out_blocks = res_blocks; | |
2922 | *out_lines = res_lines; | |
2d41c0b5 PB |
2923 | |
2924 | return true; | |
2925 | } | |
2926 | ||
2927 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
2928 | struct skl_ddb_allocation *ddb, | |
2929 | struct skl_pipe_wm_parameters *p, | |
2930 | enum pipe pipe, | |
2931 | int level, | |
2932 | int num_planes, | |
2933 | struct skl_wm_level *result) | |
2934 | { | |
2d41c0b5 PB |
2935 | uint16_t ddb_blocks; |
2936 | int i; | |
2937 | ||
2938 | for (i = 0; i < num_planes; i++) { | |
2939 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); | |
2940 | ||
d4c2aa60 TU |
2941 | result->plane_en[i] = skl_compute_plane_wm(dev_priv, |
2942 | p, &p->plane[i], | |
2d41c0b5 | 2943 | ddb_blocks, |
d4c2aa60 | 2944 | level, |
2d41c0b5 PB |
2945 | &result->plane_res_b[i], |
2946 | &result->plane_res_l[i]); | |
2947 | } | |
2948 | ||
2949 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); | |
d4c2aa60 TU |
2950 | result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor, |
2951 | ddb_blocks, level, | |
2952 | &result->cursor_res_b, | |
2d41c0b5 PB |
2953 | &result->cursor_res_l); |
2954 | } | |
2955 | ||
407b50f3 DL |
2956 | static uint32_t |
2957 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) | |
2958 | { | |
3ef00284 | 2959 | if (!to_intel_crtc(crtc)->active) |
407b50f3 DL |
2960 | return 0; |
2961 | ||
2962 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); | |
2963 | ||
2964 | } | |
2965 | ||
2966 | static void skl_compute_transition_wm(struct drm_crtc *crtc, | |
2967 | struct skl_pipe_wm_parameters *params, | |
9414f563 | 2968 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 2969 | { |
9414f563 DL |
2970 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
2971 | int i; | |
2972 | ||
407b50f3 DL |
2973 | if (!params->active) |
2974 | return; | |
9414f563 DL |
2975 | |
2976 | /* Until we know more, just disable transition WMs */ | |
2977 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
2978 | trans_wm->plane_en[i] = false; | |
2979 | trans_wm->cursor_en = false; | |
407b50f3 DL |
2980 | } |
2981 | ||
2d41c0b5 PB |
2982 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, |
2983 | struct skl_ddb_allocation *ddb, | |
2984 | struct skl_pipe_wm_parameters *params, | |
2985 | struct skl_pipe_wm *pipe_wm) | |
2986 | { | |
2987 | struct drm_device *dev = crtc->dev; | |
2988 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
2989 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2990 | int level, max_level = ilk_wm_max_level(dev); | |
2991 | ||
2992 | for (level = 0; level <= max_level; level++) { | |
2993 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, | |
2994 | level, intel_num_planes(intel_crtc), | |
2995 | &pipe_wm->wm[level]); | |
2996 | } | |
2997 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); | |
2998 | ||
9414f563 | 2999 | skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm); |
2d41c0b5 PB |
3000 | } |
3001 | ||
3002 | static void skl_compute_wm_results(struct drm_device *dev, | |
3003 | struct skl_pipe_wm_parameters *p, | |
3004 | struct skl_pipe_wm *p_wm, | |
3005 | struct skl_wm_values *r, | |
3006 | struct intel_crtc *intel_crtc) | |
3007 | { | |
3008 | int level, max_level = ilk_wm_max_level(dev); | |
3009 | enum pipe pipe = intel_crtc->pipe; | |
9414f563 DL |
3010 | uint32_t temp; |
3011 | int i; | |
2d41c0b5 PB |
3012 | |
3013 | for (level = 0; level <= max_level; level++) { | |
2d41c0b5 PB |
3014 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { |
3015 | temp = 0; | |
2d41c0b5 PB |
3016 | |
3017 | temp |= p_wm->wm[level].plane_res_l[i] << | |
3018 | PLANE_WM_LINES_SHIFT; | |
3019 | temp |= p_wm->wm[level].plane_res_b[i]; | |
3020 | if (p_wm->wm[level].plane_en[i]) | |
3021 | temp |= PLANE_WM_EN; | |
3022 | ||
3023 | r->plane[pipe][i][level] = temp; | |
2d41c0b5 PB |
3024 | } |
3025 | ||
3026 | temp = 0; | |
2d41c0b5 PB |
3027 | |
3028 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; | |
3029 | temp |= p_wm->wm[level].cursor_res_b; | |
3030 | ||
3031 | if (p_wm->wm[level].cursor_en) | |
3032 | temp |= PLANE_WM_EN; | |
3033 | ||
3034 | r->cursor[pipe][level] = temp; | |
2d41c0b5 PB |
3035 | |
3036 | } | |
3037 | ||
9414f563 DL |
3038 | /* transition WMs */ |
3039 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3040 | temp = 0; | |
3041 | temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT; | |
3042 | temp |= p_wm->trans_wm.plane_res_b[i]; | |
3043 | if (p_wm->trans_wm.plane_en[i]) | |
3044 | temp |= PLANE_WM_EN; | |
3045 | ||
3046 | r->plane_trans[pipe][i] = temp; | |
3047 | } | |
3048 | ||
3049 | temp = 0; | |
3050 | temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT; | |
3051 | temp |= p_wm->trans_wm.cursor_res_b; | |
3052 | if (p_wm->trans_wm.cursor_en) | |
3053 | temp |= PLANE_WM_EN; | |
3054 | ||
3055 | r->cursor_trans[pipe] = temp; | |
3056 | ||
2d41c0b5 PB |
3057 | r->wm_linetime[pipe] = p_wm->linetime; |
3058 | } | |
3059 | ||
16160e3d DL |
3060 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg, |
3061 | const struct skl_ddb_entry *entry) | |
3062 | { | |
3063 | if (entry->end) | |
3064 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
3065 | else | |
3066 | I915_WRITE(reg, 0); | |
3067 | } | |
3068 | ||
2d41c0b5 PB |
3069 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, |
3070 | const struct skl_wm_values *new) | |
3071 | { | |
3072 | struct drm_device *dev = dev_priv->dev; | |
3073 | struct intel_crtc *crtc; | |
3074 | ||
3075 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3076 | int i, level, max_level = ilk_wm_max_level(dev); | |
3077 | enum pipe pipe = crtc->pipe; | |
3078 | ||
5d374d96 DL |
3079 | if (!new->dirty[pipe]) |
3080 | continue; | |
8211bd5b | 3081 | |
5d374d96 | 3082 | I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]); |
8211bd5b | 3083 | |
5d374d96 DL |
3084 | for (level = 0; level <= max_level; level++) { |
3085 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3086 | I915_WRITE(PLANE_WM(pipe, i, level), | |
3087 | new->plane[pipe][i][level]); | |
3088 | I915_WRITE(CUR_WM(pipe, level), | |
3089 | new->cursor[pipe][level]); | |
2d41c0b5 | 3090 | } |
5d374d96 DL |
3091 | for (i = 0; i < intel_num_planes(crtc); i++) |
3092 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
3093 | new->plane_trans[pipe][i]); | |
3094 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); | |
3095 | ||
3096 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3097 | skl_ddb_entry_write(dev_priv, | |
3098 | PLANE_BUF_CFG(pipe, i), | |
3099 | &new->ddb.plane[pipe][i]); | |
3100 | ||
3101 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), | |
3102 | &new->ddb.cursor[pipe]); | |
2d41c0b5 | 3103 | } |
2d41c0b5 PB |
3104 | } |
3105 | ||
0e8fb7ba DL |
3106 | /* |
3107 | * When setting up a new DDB allocation arrangement, we need to correctly | |
3108 | * sequence the times at which the new allocations for the pipes are taken into | |
3109 | * account or we'll have pipes fetching from space previously allocated to | |
3110 | * another pipe. | |
3111 | * | |
3112 | * Roughly the sequence looks like: | |
3113 | * 1. re-allocate the pipe(s) with the allocation being reduced and not | |
3114 | * overlapping with a previous light-up pipe (another way to put it is: | |
3115 | * pipes with their new allocation strickly included into their old ones). | |
3116 | * 2. re-allocate the other pipes that get their allocation reduced | |
3117 | * 3. allocate the pipes having their allocation increased | |
3118 | * | |
3119 | * Steps 1. and 2. are here to take care of the following case: | |
3120 | * - Initially DDB looks like this: | |
3121 | * | B | C | | |
3122 | * - enable pipe A. | |
3123 | * - pipe B has a reduced DDB allocation that overlaps with the old pipe C | |
3124 | * allocation | |
3125 | * | A | B | C | | |
3126 | * | |
3127 | * We need to sequence the re-allocation: C, B, A (and not B, C, A). | |
3128 | */ | |
3129 | ||
d21b795c DL |
3130 | static void |
3131 | skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass) | |
0e8fb7ba | 3132 | { |
0e8fb7ba DL |
3133 | int plane; |
3134 | ||
d21b795c DL |
3135 | DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass); |
3136 | ||
dd740780 | 3137 | for_each_plane(dev_priv, pipe, plane) { |
0e8fb7ba DL |
3138 | I915_WRITE(PLANE_SURF(pipe, plane), |
3139 | I915_READ(PLANE_SURF(pipe, plane))); | |
3140 | } | |
3141 | I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe))); | |
3142 | } | |
3143 | ||
3144 | static bool | |
3145 | skl_ddb_allocation_included(const struct skl_ddb_allocation *old, | |
3146 | const struct skl_ddb_allocation *new, | |
3147 | enum pipe pipe) | |
3148 | { | |
3149 | uint16_t old_size, new_size; | |
3150 | ||
3151 | old_size = skl_ddb_entry_size(&old->pipe[pipe]); | |
3152 | new_size = skl_ddb_entry_size(&new->pipe[pipe]); | |
3153 | ||
3154 | return old_size != new_size && | |
3155 | new->pipe[pipe].start >= old->pipe[pipe].start && | |
3156 | new->pipe[pipe].end <= old->pipe[pipe].end; | |
3157 | } | |
3158 | ||
3159 | static void skl_flush_wm_values(struct drm_i915_private *dev_priv, | |
3160 | struct skl_wm_values *new_values) | |
3161 | { | |
3162 | struct drm_device *dev = dev_priv->dev; | |
3163 | struct skl_ddb_allocation *cur_ddb, *new_ddb; | |
3164 | bool reallocated[I915_MAX_PIPES] = {false, false, false}; | |
3165 | struct intel_crtc *crtc; | |
3166 | enum pipe pipe; | |
3167 | ||
3168 | new_ddb = &new_values->ddb; | |
3169 | cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3170 | ||
3171 | /* | |
3172 | * First pass: flush the pipes with the new allocation contained into | |
3173 | * the old space. | |
3174 | * | |
3175 | * We'll wait for the vblank on those pipes to ensure we can safely | |
3176 | * re-allocate the freed space without this pipe fetching from it. | |
3177 | */ | |
3178 | for_each_intel_crtc(dev, crtc) { | |
3179 | if (!crtc->active) | |
3180 | continue; | |
3181 | ||
3182 | pipe = crtc->pipe; | |
3183 | ||
3184 | if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe)) | |
3185 | continue; | |
3186 | ||
d21b795c | 3187 | skl_wm_flush_pipe(dev_priv, pipe, 1); |
0e8fb7ba DL |
3188 | intel_wait_for_vblank(dev, pipe); |
3189 | ||
3190 | reallocated[pipe] = true; | |
3191 | } | |
3192 | ||
3193 | ||
3194 | /* | |
3195 | * Second pass: flush the pipes that are having their allocation | |
3196 | * reduced, but overlapping with a previous allocation. | |
3197 | * | |
3198 | * Here as well we need to wait for the vblank to make sure the freed | |
3199 | * space is not used anymore. | |
3200 | */ | |
3201 | for_each_intel_crtc(dev, crtc) { | |
3202 | if (!crtc->active) | |
3203 | continue; | |
3204 | ||
3205 | pipe = crtc->pipe; | |
3206 | ||
3207 | if (reallocated[pipe]) | |
3208 | continue; | |
3209 | ||
3210 | if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) < | |
3211 | skl_ddb_entry_size(&cur_ddb->pipe[pipe])) { | |
d21b795c | 3212 | skl_wm_flush_pipe(dev_priv, pipe, 2); |
0e8fb7ba | 3213 | intel_wait_for_vblank(dev, pipe); |
d9d8e6b3 | 3214 | reallocated[pipe] = true; |
0e8fb7ba | 3215 | } |
0e8fb7ba DL |
3216 | } |
3217 | ||
3218 | /* | |
3219 | * Third pass: flush the pipes that got more space allocated. | |
3220 | * | |
3221 | * We don't need to actively wait for the update here, next vblank | |
3222 | * will just get more DDB space with the correct WM values. | |
3223 | */ | |
3224 | for_each_intel_crtc(dev, crtc) { | |
3225 | if (!crtc->active) | |
3226 | continue; | |
3227 | ||
3228 | pipe = crtc->pipe; | |
3229 | ||
3230 | /* | |
3231 | * At this point, only the pipes more space than before are | |
3232 | * left to re-allocate. | |
3233 | */ | |
3234 | if (reallocated[pipe]) | |
3235 | continue; | |
3236 | ||
d21b795c | 3237 | skl_wm_flush_pipe(dev_priv, pipe, 3); |
0e8fb7ba DL |
3238 | } |
3239 | } | |
3240 | ||
2d41c0b5 PB |
3241 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, |
3242 | struct skl_pipe_wm_parameters *params, | |
3243 | struct intel_wm_config *config, | |
3244 | struct skl_ddb_allocation *ddb, /* out */ | |
3245 | struct skl_pipe_wm *pipe_wm /* out */) | |
3246 | { | |
3247 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3248 | ||
3249 | skl_compute_wm_pipe_parameters(crtc, params); | |
b9cec075 | 3250 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
2d41c0b5 PB |
3251 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
3252 | ||
3253 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) | |
3254 | return false; | |
3255 | ||
3256 | intel_crtc->wm.skl_active = *pipe_wm; | |
3257 | return true; | |
3258 | } | |
3259 | ||
3260 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3261 | struct drm_crtc *crtc, | |
3262 | struct intel_wm_config *config, | |
3263 | struct skl_wm_values *r) | |
3264 | { | |
3265 | struct intel_crtc *intel_crtc; | |
3266 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3267 | ||
3268 | /* | |
3269 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3270 | * crtc we are currently computing the new WM values for), other | |
3271 | * enabled crtcs will keep the same allocation and we don't need to | |
3272 | * recompute anything for them. | |
3273 | */ | |
3274 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3275 | return; | |
3276 | ||
3277 | /* | |
3278 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3279 | * other active pipes need new DDB allocation and WM values. | |
3280 | */ | |
3281 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3282 | base.head) { | |
3283 | struct skl_pipe_wm_parameters params = {}; | |
3284 | struct skl_pipe_wm pipe_wm = {}; | |
3285 | bool wm_changed; | |
3286 | ||
3287 | if (this_crtc->pipe == intel_crtc->pipe) | |
3288 | continue; | |
3289 | ||
3290 | if (!intel_crtc->active) | |
3291 | continue; | |
3292 | ||
3293 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, | |
3294 | ¶ms, config, | |
3295 | &r->ddb, &pipe_wm); | |
3296 | ||
3297 | /* | |
3298 | * If we end up re-computing the other pipe WM values, it's | |
3299 | * because it was really needed, so we expect the WM values to | |
3300 | * be different. | |
3301 | */ | |
3302 | WARN_ON(!wm_changed); | |
3303 | ||
3304 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); | |
3305 | r->dirty[intel_crtc->pipe] = true; | |
3306 | } | |
3307 | } | |
3308 | ||
3309 | static void skl_update_wm(struct drm_crtc *crtc) | |
3310 | { | |
3311 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3312 | struct drm_device *dev = crtc->dev; | |
3313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3314 | struct skl_pipe_wm_parameters params = {}; | |
3315 | struct skl_wm_values *results = &dev_priv->wm.skl_results; | |
3316 | struct skl_pipe_wm pipe_wm = {}; | |
3317 | struct intel_wm_config config = {}; | |
3318 | ||
3319 | memset(results, 0, sizeof(*results)); | |
3320 | ||
3321 | skl_compute_wm_global_parameters(dev, &config); | |
3322 | ||
3323 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, | |
3324 | &results->ddb, &pipe_wm)) | |
3325 | return; | |
3326 | ||
3327 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); | |
3328 | results->dirty[intel_crtc->pipe] = true; | |
3329 | ||
3330 | skl_update_other_pipe_wm(dev, crtc, &config, results); | |
3331 | skl_write_wm_values(dev_priv, results); | |
0e8fb7ba | 3332 | skl_flush_wm_values(dev_priv, results); |
53b0deb4 DL |
3333 | |
3334 | /* store the new configuration */ | |
3335 | dev_priv->wm.skl_hw = *results; | |
2d41c0b5 PB |
3336 | } |
3337 | ||
3338 | static void | |
3339 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3340 | uint32_t sprite_width, uint32_t sprite_height, | |
3341 | int pixel_size, bool enabled, bool scaled) | |
3342 | { | |
3343 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
0fda6568 | 3344 | struct drm_framebuffer *fb = plane->state->fb; |
2d41c0b5 PB |
3345 | |
3346 | intel_plane->wm.enabled = enabled; | |
3347 | intel_plane->wm.scaled = scaled; | |
3348 | intel_plane->wm.horiz_pixels = sprite_width; | |
3349 | intel_plane->wm.vert_pixels = sprite_height; | |
3350 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
0fda6568 TU |
3351 | intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE; |
3352 | /* | |
3353 | * Framebuffer can be NULL on plane disable, but it does not | |
3354 | * matter for watermarks if we assume no tiling in that case. | |
3355 | */ | |
3356 | if (fb) | |
3357 | intel_plane->wm.tiling = fb->modifier[0]; | |
2d41c0b5 PB |
3358 | |
3359 | skl_update_wm(crtc); | |
3360 | } | |
3361 | ||
820c1980 | 3362 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 3363 | { |
7c4a395f | 3364 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 3365 | struct drm_device *dev = crtc->dev; |
801bcfff | 3366 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
3367 | struct ilk_wm_maximums max; |
3368 | struct ilk_pipe_wm_parameters params = {}; | |
3369 | struct ilk_wm_values results = {}; | |
77c122bc | 3370 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 3371 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 3372 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 3373 | struct intel_wm_config config = {}; |
7c4a395f | 3374 | |
2a44b76b | 3375 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
3376 | |
3377 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
3378 | ||
3379 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3380 | return; | |
861f3389 | 3381 | |
7c4a395f | 3382 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 3383 | |
2a44b76b VS |
3384 | ilk_compute_wm_config(dev, &config); |
3385 | ||
34982fe1 | 3386 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 3387 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
3388 | |
3389 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
3390 | if (INTEL_INFO(dev)->gen >= 7 && |
3391 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 3392 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 3393 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 3394 | |
820c1980 | 3395 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3396 | } else { |
198a1e9b | 3397 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3398 | } |
3399 | ||
198a1e9b | 3400 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3401 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3402 | |
820c1980 | 3403 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3404 | |
820c1980 | 3405 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3406 | } |
3407 | ||
ed57cb8a DL |
3408 | static void |
3409 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3410 | struct drm_crtc *crtc, | |
3411 | uint32_t sprite_width, uint32_t sprite_height, | |
3412 | int pixel_size, bool enabled, bool scaled) | |
526682e9 | 3413 | { |
8553c18e | 3414 | struct drm_device *dev = plane->dev; |
adf3d35e | 3415 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 3416 | |
adf3d35e VS |
3417 | intel_plane->wm.enabled = enabled; |
3418 | intel_plane->wm.scaled = scaled; | |
3419 | intel_plane->wm.horiz_pixels = sprite_width; | |
ed57cb8a | 3420 | intel_plane->wm.vert_pixels = sprite_width; |
adf3d35e | 3421 | intel_plane->wm.bytes_per_pixel = pixel_size; |
526682e9 | 3422 | |
8553c18e VS |
3423 | /* |
3424 | * IVB workaround: must disable low power watermarks for at least | |
3425 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3426 | * when scaling is disabled. | |
3427 | * | |
3428 | * WaCxSRDisabledForSpriteScaling:ivb | |
3429 | */ | |
3430 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3431 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3432 | ||
820c1980 | 3433 | ilk_update_wm(crtc); |
526682e9 PZ |
3434 | } |
3435 | ||
3078999f PB |
3436 | static void skl_pipe_wm_active_state(uint32_t val, |
3437 | struct skl_pipe_wm *active, | |
3438 | bool is_transwm, | |
3439 | bool is_cursor, | |
3440 | int i, | |
3441 | int level) | |
3442 | { | |
3443 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3444 | ||
3445 | if (!is_transwm) { | |
3446 | if (!is_cursor) { | |
3447 | active->wm[level].plane_en[i] = is_enabled; | |
3448 | active->wm[level].plane_res_b[i] = | |
3449 | val & PLANE_WM_BLOCKS_MASK; | |
3450 | active->wm[level].plane_res_l[i] = | |
3451 | (val >> PLANE_WM_LINES_SHIFT) & | |
3452 | PLANE_WM_LINES_MASK; | |
3453 | } else { | |
3454 | active->wm[level].cursor_en = is_enabled; | |
3455 | active->wm[level].cursor_res_b = | |
3456 | val & PLANE_WM_BLOCKS_MASK; | |
3457 | active->wm[level].cursor_res_l = | |
3458 | (val >> PLANE_WM_LINES_SHIFT) & | |
3459 | PLANE_WM_LINES_MASK; | |
3460 | } | |
3461 | } else { | |
3462 | if (!is_cursor) { | |
3463 | active->trans_wm.plane_en[i] = is_enabled; | |
3464 | active->trans_wm.plane_res_b[i] = | |
3465 | val & PLANE_WM_BLOCKS_MASK; | |
3466 | active->trans_wm.plane_res_l[i] = | |
3467 | (val >> PLANE_WM_LINES_SHIFT) & | |
3468 | PLANE_WM_LINES_MASK; | |
3469 | } else { | |
3470 | active->trans_wm.cursor_en = is_enabled; | |
3471 | active->trans_wm.cursor_res_b = | |
3472 | val & PLANE_WM_BLOCKS_MASK; | |
3473 | active->trans_wm.cursor_res_l = | |
3474 | (val >> PLANE_WM_LINES_SHIFT) & | |
3475 | PLANE_WM_LINES_MASK; | |
3476 | } | |
3477 | } | |
3478 | } | |
3479 | ||
3480 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3481 | { | |
3482 | struct drm_device *dev = crtc->dev; | |
3483 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3484 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3485 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3486 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; | |
3487 | enum pipe pipe = intel_crtc->pipe; | |
3488 | int level, i, max_level; | |
3489 | uint32_t temp; | |
3490 | ||
3491 | max_level = ilk_wm_max_level(dev); | |
3492 | ||
3493 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3494 | ||
3495 | for (level = 0; level <= max_level; level++) { | |
3496 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3497 | hw->plane[pipe][i][level] = | |
3498 | I915_READ(PLANE_WM(pipe, i, level)); | |
3499 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); | |
3500 | } | |
3501 | ||
3502 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3503 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
3504 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); | |
3505 | ||
3ef00284 | 3506 | if (!intel_crtc->active) |
3078999f PB |
3507 | return; |
3508 | ||
3509 | hw->dirty[pipe] = true; | |
3510 | ||
3511 | active->linetime = hw->wm_linetime[pipe]; | |
3512 | ||
3513 | for (level = 0; level <= max_level; level++) { | |
3514 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3515 | temp = hw->plane[pipe][i][level]; | |
3516 | skl_pipe_wm_active_state(temp, active, false, | |
3517 | false, i, level); | |
3518 | } | |
3519 | temp = hw->cursor[pipe][level]; | |
3520 | skl_pipe_wm_active_state(temp, active, false, true, i, level); | |
3521 | } | |
3522 | ||
3523 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3524 | temp = hw->plane_trans[pipe][i]; | |
3525 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3526 | } | |
3527 | ||
3528 | temp = hw->cursor_trans[pipe]; | |
3529 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); | |
3530 | } | |
3531 | ||
3532 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3533 | { | |
a269c583 DL |
3534 | struct drm_i915_private *dev_priv = dev->dev_private; |
3535 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; | |
3078999f PB |
3536 | struct drm_crtc *crtc; |
3537 | ||
a269c583 | 3538 | skl_ddb_get_hw_state(dev_priv, ddb); |
3078999f PB |
3539 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) |
3540 | skl_pipe_wm_get_hw_state(crtc); | |
3541 | } | |
3542 | ||
243e6a44 VS |
3543 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3544 | { | |
3545 | struct drm_device *dev = crtc->dev; | |
3546 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3547 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3548 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3549 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
3550 | enum pipe pipe = intel_crtc->pipe; | |
3551 | static const unsigned int wm0_pipe_reg[] = { | |
3552 | [PIPE_A] = WM0_PIPEA_ILK, | |
3553 | [PIPE_B] = WM0_PIPEB_ILK, | |
3554 | [PIPE_C] = WM0_PIPEC_IVB, | |
3555 | }; | |
3556 | ||
3557 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3558 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3559 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3560 | |
3ef00284 | 3561 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
3562 | |
3563 | if (active->pipe_enabled) { | |
243e6a44 VS |
3564 | u32 tmp = hw->wm_pipe[pipe]; |
3565 | ||
3566 | /* | |
3567 | * For active pipes LP0 watermark is marked as | |
3568 | * enabled, and LP1+ watermaks as disabled since | |
3569 | * we can't really reverse compute them in case | |
3570 | * multiple pipes are active. | |
3571 | */ | |
3572 | active->wm[0].enable = true; | |
3573 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3574 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3575 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3576 | active->linetime = hw->wm_linetime[pipe]; | |
3577 | } else { | |
3578 | int level, max_level = ilk_wm_max_level(dev); | |
3579 | ||
3580 | /* | |
3581 | * For inactive pipes, all watermark levels | |
3582 | * should be marked as enabled but zeroed, | |
3583 | * which is what we'd compute them to. | |
3584 | */ | |
3585 | for (level = 0; level <= max_level; level++) | |
3586 | active->wm[level].enable = true; | |
3587 | } | |
3588 | } | |
3589 | ||
3590 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
3591 | { | |
3592 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3593 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3594 | struct drm_crtc *crtc; |
3595 | ||
70e1e0ec | 3596 | for_each_crtc(dev, crtc) |
243e6a44 VS |
3597 | ilk_pipe_wm_get_hw_state(crtc); |
3598 | ||
3599 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3600 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3601 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3602 | ||
3603 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
3604 | if (INTEL_INFO(dev)->gen >= 7) { |
3605 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3606 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3607 | } | |
243e6a44 | 3608 | |
a42a5719 | 3609 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
3610 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
3611 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3612 | else if (IS_IVYBRIDGE(dev)) | |
3613 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3614 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3615 | |
3616 | hw->enable_fbc_wm = | |
3617 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3618 | } | |
3619 | ||
b445e3b0 ED |
3620 | /** |
3621 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3622 | * | |
3623 | * Calculate watermark values for the various WM regs based on current mode | |
3624 | * and plane configuration. | |
3625 | * | |
3626 | * There are several cases to deal with here: | |
3627 | * - normal (i.e. non-self-refresh) | |
3628 | * - self-refresh (SR) mode | |
3629 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3630 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3631 | * lines), so need to account for TLB latency | |
3632 | * | |
3633 | * The normal calculation is: | |
3634 | * watermark = dotclock * bytes per pixel * latency | |
3635 | * where latency is platform & configuration dependent (we assume pessimal | |
3636 | * values here). | |
3637 | * | |
3638 | * The SR calculation is: | |
3639 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3640 | * bytes per pixel | |
3641 | * where | |
3642 | * line time = htotal / dotclock | |
3643 | * surface width = hdisplay for normal plane and 64 for cursor | |
3644 | * and latency is assumed to be high, as above. | |
3645 | * | |
3646 | * The final value programmed to the register should always be rounded up, | |
3647 | * and include an extra 2 entries to account for clock crossings. | |
3648 | * | |
3649 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3650 | * to set the non-SR watermarks to 8. | |
3651 | */ | |
46ba614c | 3652 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 3653 | { |
46ba614c | 3654 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
3655 | |
3656 | if (dev_priv->display.update_wm) | |
46ba614c | 3657 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
3658 | } |
3659 | ||
adf3d35e VS |
3660 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
3661 | struct drm_crtc *crtc, | |
ed57cb8a DL |
3662 | uint32_t sprite_width, |
3663 | uint32_t sprite_height, | |
3664 | int pixel_size, | |
39db4a4d | 3665 | bool enabled, bool scaled) |
b445e3b0 | 3666 | { |
adf3d35e | 3667 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
3668 | |
3669 | if (dev_priv->display.update_sprite_wm) | |
ed57cb8a DL |
3670 | dev_priv->display.update_sprite_wm(plane, crtc, |
3671 | sprite_width, sprite_height, | |
39db4a4d | 3672 | pixel_size, enabled, scaled); |
b445e3b0 ED |
3673 | } |
3674 | ||
9270388e DV |
3675 | /** |
3676 | * Lock protecting IPS related data structures | |
9270388e DV |
3677 | */ |
3678 | DEFINE_SPINLOCK(mchdev_lock); | |
3679 | ||
3680 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3681 | * mchdev_lock. */ | |
3682 | static struct drm_i915_private *i915_mch_dev; | |
3683 | ||
2b4e57bd ED |
3684 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
3685 | { | |
3686 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3687 | u16 rgvswctl; | |
3688 | ||
9270388e DV |
3689 | assert_spin_locked(&mchdev_lock); |
3690 | ||
2b4e57bd ED |
3691 | rgvswctl = I915_READ16(MEMSWCTL); |
3692 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3693 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3694 | return false; /* still busy with another command */ | |
3695 | } | |
3696 | ||
3697 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3698 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3699 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3700 | POSTING_READ16(MEMSWCTL); | |
3701 | ||
3702 | rgvswctl |= MEMCTL_CMD_STS; | |
3703 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3704 | ||
3705 | return true; | |
3706 | } | |
3707 | ||
8090c6b9 | 3708 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
3709 | { |
3710 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3711 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3712 | u8 fmax, fmin, fstart, vstart; | |
3713 | ||
9270388e DV |
3714 | spin_lock_irq(&mchdev_lock); |
3715 | ||
2b4e57bd ED |
3716 | /* Enable temp reporting */ |
3717 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3718 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3719 | ||
3720 | /* 100ms RC evaluation intervals */ | |
3721 | I915_WRITE(RCUPEI, 100000); | |
3722 | I915_WRITE(RCDNEI, 100000); | |
3723 | ||
3724 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3725 | I915_WRITE(RCBMAXAVG, 90000); | |
3726 | I915_WRITE(RCBMINAVG, 80000); | |
3727 | ||
3728 | I915_WRITE(MEMIHYST, 1); | |
3729 | ||
3730 | /* Set up min, max, and cur for interrupt handling */ | |
3731 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3732 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3733 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3734 | MEMMODE_FSTART_SHIFT; | |
3735 | ||
3736 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3737 | PXVFREQ_PX_SHIFT; | |
3738 | ||
20e4d407 DV |
3739 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
3740 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 3741 | |
20e4d407 DV |
3742 | dev_priv->ips.max_delay = fstart; |
3743 | dev_priv->ips.min_delay = fmin; | |
3744 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
3745 | |
3746 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3747 | fmax, fmin, fstart); | |
3748 | ||
3749 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3750 | ||
3751 | /* | |
3752 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3753 | */ | |
3754 | ||
3755 | I915_WRITE(VIDSTART, vstart); | |
3756 | POSTING_READ(VIDSTART); | |
3757 | ||
3758 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3759 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3760 | ||
9270388e | 3761 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 3762 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 3763 | mdelay(1); |
2b4e57bd ED |
3764 | |
3765 | ironlake_set_drps(dev, fstart); | |
3766 | ||
20e4d407 | 3767 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 3768 | I915_READ(0x112e0); |
20e4d407 DV |
3769 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
3770 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
5ed0bdf2 | 3771 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
3772 | |
3773 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
3774 | } |
3775 | ||
8090c6b9 | 3776 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
3777 | { |
3778 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
3779 | u16 rgvswctl; |
3780 | ||
3781 | spin_lock_irq(&mchdev_lock); | |
3782 | ||
3783 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
3784 | |
3785 | /* Ack interrupts, disable EFC interrupt */ | |
3786 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
3787 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
3788 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
3789 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
3790 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
3791 | ||
3792 | /* Go back to the starting frequency */ | |
20e4d407 | 3793 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 3794 | mdelay(1); |
2b4e57bd ED |
3795 | rgvswctl |= MEMCTL_CMD_STS; |
3796 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 3797 | mdelay(1); |
2b4e57bd | 3798 | |
9270388e | 3799 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
3800 | } |
3801 | ||
acbe9475 DV |
3802 | /* There's a funny hw issue where the hw returns all 0 when reading from |
3803 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
3804 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
3805 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
3806 | */ | |
6917c7b9 | 3807 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 3808 | { |
7b9e0ae6 | 3809 | u32 limits; |
2b4e57bd | 3810 | |
20b46e59 DV |
3811 | /* Only set the down limit when we've reached the lowest level to avoid |
3812 | * getting more interrupts, otherwise leave this clear. This prevents a | |
3813 | * race in the hw when coming out of rc6: There's a tiny window where | |
3814 | * the hw runs at the minimal clock before selecting the desired | |
3815 | * frequency, if the down threshold expires in that window we will not | |
3816 | * receive a down interrupt. */ | |
b39fb297 BW |
3817 | limits = dev_priv->rps.max_freq_softlimit << 24; |
3818 | if (val <= dev_priv->rps.min_freq_softlimit) | |
3819 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
3820 | |
3821 | return limits; | |
3822 | } | |
3823 | ||
dd75fdc8 CW |
3824 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
3825 | { | |
3826 | int new_power; | |
3827 | ||
3828 | new_power = dev_priv->rps.power; | |
3829 | switch (dev_priv->rps.power) { | |
3830 | case LOW_POWER: | |
b39fb297 | 3831 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3832 | new_power = BETWEEN; |
3833 | break; | |
3834 | ||
3835 | case BETWEEN: | |
b39fb297 | 3836 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 3837 | new_power = LOW_POWER; |
b39fb297 | 3838 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3839 | new_power = HIGH_POWER; |
3840 | break; | |
3841 | ||
3842 | case HIGH_POWER: | |
b39fb297 | 3843 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
3844 | new_power = BETWEEN; |
3845 | break; | |
3846 | } | |
3847 | /* Max/min bins are special */ | |
b39fb297 | 3848 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 3849 | new_power = LOW_POWER; |
b39fb297 | 3850 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
3851 | new_power = HIGH_POWER; |
3852 | if (new_power == dev_priv->rps.power) | |
3853 | return; | |
3854 | ||
3855 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
3856 | switch (new_power) { | |
3857 | case LOW_POWER: | |
3858 | /* Upclock if more than 95% busy over 16ms */ | |
3859 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
3860 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
3861 | ||
3862 | /* Downclock if less than 85% busy over 32ms */ | |
3863 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3864 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
3865 | ||
3866 | I915_WRITE(GEN6_RP_CONTROL, | |
3867 | GEN6_RP_MEDIA_TURBO | | |
3868 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3869 | GEN6_RP_MEDIA_IS_GFX | | |
3870 | GEN6_RP_ENABLE | | |
3871 | GEN6_RP_UP_BUSY_AVG | | |
3872 | GEN6_RP_DOWN_IDLE_AVG); | |
3873 | break; | |
3874 | ||
3875 | case BETWEEN: | |
3876 | /* Upclock if more than 90% busy over 13ms */ | |
3877 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
3878 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
3879 | ||
3880 | /* Downclock if less than 75% busy over 32ms */ | |
3881 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3882 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
3883 | ||
3884 | I915_WRITE(GEN6_RP_CONTROL, | |
3885 | GEN6_RP_MEDIA_TURBO | | |
3886 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3887 | GEN6_RP_MEDIA_IS_GFX | | |
3888 | GEN6_RP_ENABLE | | |
3889 | GEN6_RP_UP_BUSY_AVG | | |
3890 | GEN6_RP_DOWN_IDLE_AVG); | |
3891 | break; | |
3892 | ||
3893 | case HIGH_POWER: | |
3894 | /* Upclock if more than 85% busy over 10ms */ | |
3895 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
3896 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
3897 | ||
3898 | /* Downclock if less than 60% busy over 32ms */ | |
3899 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
3900 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
3901 | ||
3902 | I915_WRITE(GEN6_RP_CONTROL, | |
3903 | GEN6_RP_MEDIA_TURBO | | |
3904 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
3905 | GEN6_RP_MEDIA_IS_GFX | | |
3906 | GEN6_RP_ENABLE | | |
3907 | GEN6_RP_UP_BUSY_AVG | | |
3908 | GEN6_RP_DOWN_IDLE_AVG); | |
3909 | break; | |
3910 | } | |
3911 | ||
3912 | dev_priv->rps.power = new_power; | |
3913 | dev_priv->rps.last_adj = 0; | |
3914 | } | |
3915 | ||
2876ce73 CW |
3916 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
3917 | { | |
3918 | u32 mask = 0; | |
3919 | ||
3920 | if (val > dev_priv->rps.min_freq_softlimit) | |
3921 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
3922 | if (val < dev_priv->rps.max_freq_softlimit) | |
3923 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
3924 | ||
7b3c29f6 CW |
3925 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
3926 | mask &= dev_priv->pm_rps_events; | |
3927 | ||
59d02a1f | 3928 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
3929 | } |
3930 | ||
b8a5ff8d JM |
3931 | /* gen6_set_rps is called to update the frequency request, but should also be |
3932 | * called when the range (min_delay and max_delay) is modified so that we can | |
3933 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
ffe02b40 | 3934 | static void gen6_set_rps(struct drm_device *dev, u8 val) |
20b46e59 DV |
3935 | { |
3936 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 3937 | |
4fc688ce | 3938 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
3939 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
3940 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 3941 | |
eb64cad1 CW |
3942 | /* min/max delay may still have been modified so be sure to |
3943 | * write the limits value. | |
3944 | */ | |
3945 | if (val != dev_priv->rps.cur_freq) { | |
3946 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 3947 | |
50e6a2a7 | 3948 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
eb64cad1 CW |
3949 | I915_WRITE(GEN6_RPNSWREQ, |
3950 | HSW_FREQUENCY(val)); | |
3951 | else | |
3952 | I915_WRITE(GEN6_RPNSWREQ, | |
3953 | GEN6_FREQUENCY(val) | | |
3954 | GEN6_OFFSET(0) | | |
3955 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 3956 | } |
7b9e0ae6 | 3957 | |
7b9e0ae6 CW |
3958 | /* Make sure we continue to get interrupts |
3959 | * until we hit the minimum or maximum frequencies. | |
3960 | */ | |
eb64cad1 | 3961 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
2876ce73 | 3962 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 3963 | |
d5570a72 BW |
3964 | POSTING_READ(GEN6_RPNSWREQ); |
3965 | ||
b39fb297 | 3966 | dev_priv->rps.cur_freq = val; |
be2cde9a | 3967 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
3968 | } |
3969 | ||
ffe02b40 VS |
3970 | static void valleyview_set_rps(struct drm_device *dev, u8 val) |
3971 | { | |
3972 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3973 | ||
3974 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
3975 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); | |
3976 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
3977 | ||
3978 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), | |
3979 | "Odd GPU freq value\n")) | |
3980 | val &= ~1; | |
3981 | ||
3982 | if (val != dev_priv->rps.cur_freq) | |
3983 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); | |
3984 | ||
3985 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); | |
3986 | ||
3987 | dev_priv->rps.cur_freq = val; | |
3988 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
3989 | } | |
3990 | ||
76c3552f D |
3991 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
3992 | * | |
3993 | * * If Gfx is Idle, then | |
3994 | * 1. Mask Turbo interrupts | |
3995 | * 2. Bring up Gfx clock | |
3996 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
3997 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
3998 | * 5. Unmask Turbo interrupts | |
3999 | */ | |
4000 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
4001 | { | |
5549d25f D |
4002 | struct drm_device *dev = dev_priv->dev; |
4003 | ||
21a11fff VS |
4004 | /* CHV and latest VLV don't need to force the gfx clock */ |
4005 | if (IS_CHERRYVIEW(dev) || dev->pdev->revision >= 0xd) { | |
5549d25f D |
4006 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
4007 | return; | |
4008 | } | |
4009 | ||
76c3552f D |
4010 | /* |
4011 | * When we are idle. Drop to min voltage state. | |
4012 | */ | |
4013 | ||
b39fb297 | 4014 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
4015 | return; |
4016 | ||
4017 | /* Mask turbo interrupt so that they will not come in between */ | |
f24eeb19 ID |
4018 | I915_WRITE(GEN6_PMINTRMSK, |
4019 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
76c3552f | 4020 | |
650ad970 | 4021 | vlv_force_gfx_clock(dev_priv, true); |
76c3552f | 4022 | |
b39fb297 | 4023 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
4024 | |
4025 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 4026 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
4027 | |
4028 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
2837ac40 | 4029 | & GENFREQSTATUS) == 0, 100)) |
76c3552f D |
4030 | DRM_ERROR("timed out waiting for Punit\n"); |
4031 | ||
650ad970 | 4032 | vlv_force_gfx_clock(dev_priv, false); |
76c3552f | 4033 | |
2876ce73 CW |
4034 | I915_WRITE(GEN6_PMINTRMSK, |
4035 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
76c3552f D |
4036 | } |
4037 | ||
b29c19b6 CW |
4038 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4039 | { | |
691bb717 DL |
4040 | struct drm_device *dev = dev_priv->dev; |
4041 | ||
b29c19b6 | 4042 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4043 | if (dev_priv->rps.enabled) { |
21a11fff | 4044 | if (IS_VALLEYVIEW(dev)) |
76c3552f | 4045 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 4046 | else |
b39fb297 | 4047 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c0951f0c CW |
4048 | dev_priv->rps.last_adj = 0; |
4049 | } | |
b29c19b6 CW |
4050 | mutex_unlock(&dev_priv->rps.hw_lock); |
4051 | } | |
4052 | ||
4053 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
4054 | { | |
4055 | mutex_lock(&dev_priv->rps.hw_lock); | |
c0951f0c | 4056 | if (dev_priv->rps.enabled) { |
ffe02b40 | 4057 | intel_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c CW |
4058 | dev_priv->rps.last_adj = 0; |
4059 | } | |
b29c19b6 CW |
4060 | mutex_unlock(&dev_priv->rps.hw_lock); |
4061 | } | |
4062 | ||
ffe02b40 | 4063 | void intel_set_rps(struct drm_device *dev, u8 val) |
0a073b84 | 4064 | { |
ffe02b40 VS |
4065 | if (IS_VALLEYVIEW(dev)) |
4066 | valleyview_set_rps(dev, val); | |
4067 | else | |
4068 | gen6_set_rps(dev, val); | |
0a073b84 JB |
4069 | } |
4070 | ||
20e49366 ZW |
4071 | static void gen9_disable_rps(struct drm_device *dev) |
4072 | { | |
4073 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4074 | ||
4075 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
38c23527 | 4076 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
4077 | } |
4078 | ||
44fc7d5c | 4079 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
4080 | { |
4081 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4082 | ||
4083 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 4084 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
44fc7d5c DV |
4085 | } |
4086 | ||
38807746 D |
4087 | static void cherryview_disable_rps(struct drm_device *dev) |
4088 | { | |
4089 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4090 | ||
4091 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4092 | } | |
4093 | ||
44fc7d5c DV |
4094 | static void valleyview_disable_rps(struct drm_device *dev) |
4095 | { | |
4096 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4097 | ||
98a2e5f9 D |
4098 | /* we're doing forcewake before Disabling RC6, |
4099 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 4100 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 4101 | |
44fc7d5c | 4102 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 4103 | |
59bad947 | 4104 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
4105 | } |
4106 | ||
dc39fff7 BW |
4107 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4108 | { | |
91ca689a ID |
4109 | if (IS_VALLEYVIEW(dev)) { |
4110 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
4111 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
4112 | else | |
4113 | mode = 0; | |
4114 | } | |
58abf1da RV |
4115 | if (HAS_RC6p(dev)) |
4116 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
4117 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
4118 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
4119 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
4120 | ||
4121 | else | |
4122 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
4123 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
4124 | } |
4125 | ||
e6069ca8 | 4126 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 4127 | { |
eb4926e4 DL |
4128 | /* No RC6 before Ironlake */ |
4129 | if (INTEL_INFO(dev)->gen < 5) | |
4130 | return 0; | |
4131 | ||
e6069ca8 ID |
4132 | /* RC6 is only on Ironlake mobile not on desktop */ |
4133 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
4134 | return 0; | |
4135 | ||
456470eb | 4136 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4137 | if (enable_rc6 >= 0) { |
4138 | int mask; | |
4139 | ||
58abf1da | 4140 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4141 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4142 | INTEL_RC6pp_ENABLE; | |
4143 | else | |
4144 | mask = INTEL_RC6_ENABLE; | |
4145 | ||
4146 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4147 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4148 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4149 | |
4150 | return enable_rc6 & mask; | |
4151 | } | |
2b4e57bd | 4152 | |
6567d748 CW |
4153 | /* Disable RC6 on Ironlake */ |
4154 | if (INTEL_INFO(dev)->gen == 5) | |
4155 | return 0; | |
2b4e57bd | 4156 | |
8bade1ad | 4157 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4158 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4159 | |
4160 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4161 | } |
4162 | ||
e6069ca8 ID |
4163 | int intel_enable_rc6(const struct drm_device *dev) |
4164 | { | |
4165 | return i915.enable_rc6; | |
4166 | } | |
4167 | ||
93ee2920 | 4168 | static void gen6_init_rps_frequencies(struct drm_device *dev) |
3280e8b0 | 4169 | { |
93ee2920 TR |
4170 | struct drm_i915_private *dev_priv = dev->dev_private; |
4171 | uint32_t rp_state_cap; | |
4172 | u32 ddcc_status = 0; | |
4173 | int ret; | |
4174 | ||
4175 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3280e8b0 BW |
4176 | /* All of these values are in units of 50MHz */ |
4177 | dev_priv->rps.cur_freq = 0; | |
93ee2920 | 4178 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
3280e8b0 | 4179 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
93ee2920 | 4180 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; |
3280e8b0 | 4181 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; |
3280e8b0 BW |
4182 | /* hw_max = RP0 until we check for overclocking */ |
4183 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4184 | ||
93ee2920 TR |
4185 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
4186 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { | |
4187 | ret = sandybridge_pcode_read(dev_priv, | |
4188 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
4189 | &ddcc_status); | |
4190 | if (0 == ret) | |
4191 | dev_priv->rps.efficient_freq = | |
46efa4ab TR |
4192 | clamp_t(u8, |
4193 | ((ddcc_status >> 8) & 0xff), | |
4194 | dev_priv->rps.min_freq, | |
4195 | dev_priv->rps.max_freq); | |
93ee2920 TR |
4196 | } |
4197 | ||
3280e8b0 BW |
4198 | /* Preserve min/max settings in case of re-init */ |
4199 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4200 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4201 | ||
93ee2920 TR |
4202 | if (dev_priv->rps.min_freq_softlimit == 0) { |
4203 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
4204 | dev_priv->rps.min_freq_softlimit = | |
f4ab408c TR |
4205 | /* max(RPe, 450 MHz) */ |
4206 | max(dev_priv->rps.efficient_freq, (u8) 9); | |
93ee2920 TR |
4207 | else |
4208 | dev_priv->rps.min_freq_softlimit = | |
4209 | dev_priv->rps.min_freq; | |
4210 | } | |
3280e8b0 BW |
4211 | } |
4212 | ||
b6fef0ef | 4213 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
20e49366 | 4214 | static void gen9_enable_rps(struct drm_device *dev) |
b6fef0ef JB |
4215 | { |
4216 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4217 | ||
4218 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); | |
4219 | ||
ba1c554c DL |
4220 | gen6_init_rps_frequencies(dev); |
4221 | ||
b6fef0ef JB |
4222 | I915_WRITE(GEN6_RPNSWREQ, 0xc800000); |
4223 | I915_WRITE(GEN6_RC_VIDEO_FREQ, 0xc800000); | |
4224 | ||
4225 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); | |
4226 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, 0x12060000); | |
4227 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 0xe808); | |
4228 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 0x3bd08); | |
4229 | I915_WRITE(GEN6_RP_UP_EI, 0x101d0); | |
4230 | I915_WRITE(GEN6_RP_DOWN_EI, 0x55730); | |
4231 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); | |
4232 | I915_WRITE(GEN6_PMINTRMSK, 0x6); | |
4233 | I915_WRITE(GEN6_RP_CONTROL, GEN6_RP_MEDIA_TURBO | | |
4234 | GEN6_RP_MEDIA_HW_MODE | GEN6_RP_MEDIA_IS_GFX | | |
4235 | GEN6_RP_ENABLE | GEN6_RP_UP_BUSY_AVG | | |
4236 | GEN6_RP_DOWN_IDLE_AVG); | |
4237 | ||
4238 | gen6_enable_rps_interrupts(dev); | |
4239 | ||
4240 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
4241 | } | |
4242 | ||
4243 | static void gen9_enable_rc6(struct drm_device *dev) | |
20e49366 ZW |
4244 | { |
4245 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4246 | struct intel_engine_cs *ring; | |
4247 | uint32_t rc6_mask = 0; | |
4248 | int unused; | |
4249 | ||
4250 | /* 1a: Software RC state - RC0 */ | |
4251 | I915_WRITE(GEN6_RC_STATE, 0); | |
4252 | ||
4253 | /* 1b: Get forcewake during program sequence. Although the driver | |
4254 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4255 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4256 | |
4257 | /* 2a: Disable RC states. */ | |
4258 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4259 | ||
4260 | /* 2b: Program RC6 thresholds.*/ | |
4261 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
4262 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4263 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4264 | for_each_ring(ring, dev_priv, unused) | |
4265 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4266 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4267 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ | |
4268 | ||
38c23527 ZW |
4269 | /* 2c: Program Coarse Power Gating Policies. */ |
4270 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
4271 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
4272 | ||
20e49366 ZW |
4273 | /* 3a: Enable RC6 */ |
4274 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4275 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
4276 | DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
4277 | "on" : "off"); | |
4278 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4279 | GEN6_RC_CTL_EI_MODE(1) | | |
4280 | rc6_mask); | |
4281 | ||
38c23527 ZW |
4282 | /* 3b: Enable Coarse Power Gating only when RC6 is enabled */ |
4283 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? 3 : 0); | |
4284 | ||
59bad947 | 4285 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
4286 | |
4287 | } | |
4288 | ||
6edee7f3 BW |
4289 | static void gen8_enable_rps(struct drm_device *dev) |
4290 | { | |
4291 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4292 | struct intel_engine_cs *ring; |
93ee2920 | 4293 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
4294 | int unused; |
4295 | ||
4296 | /* 1a: Software RC state - RC0 */ | |
4297 | I915_WRITE(GEN6_RC_STATE, 0); | |
4298 | ||
4299 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4300 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4301 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4302 | |
4303 | /* 2a: Disable RC states. */ | |
4304 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4305 | ||
93ee2920 TR |
4306 | /* Initialize rps frequencies */ |
4307 | gen6_init_rps_frequencies(dev); | |
6edee7f3 BW |
4308 | |
4309 | /* 2b: Program RC6 thresholds.*/ | |
4310 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4311 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4312 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4313 | for_each_ring(ring, dev_priv, unused) | |
4314 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4315 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4316 | if (IS_BROADWELL(dev)) |
4317 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4318 | else | |
4319 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4320 | |
4321 | /* 3: Enable RC6 */ | |
4322 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4323 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4324 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4325 | if (IS_BROADWELL(dev)) |
4326 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4327 | GEN7_RC_CTL_TO_MODE | | |
4328 | rc6_mask); | |
4329 | else | |
4330 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4331 | GEN6_RC_CTL_EI_MODE(1) | | |
4332 | rc6_mask); | |
6edee7f3 BW |
4333 | |
4334 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4335 | I915_WRITE(GEN6_RPNSWREQ, |
4336 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4337 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4338 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4339 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4340 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4341 | ||
4342 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4343 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4344 | dev_priv->rps.max_freq_softlimit << 24 | | |
4345 | dev_priv->rps.min_freq_softlimit << 16); | |
4346 | ||
4347 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4348 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4349 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4350 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4351 | ||
4352 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4353 | |
4354 | /* 5: Enable RPS */ | |
7526ed79 DV |
4355 | I915_WRITE(GEN6_RP_CONTROL, |
4356 | GEN6_RP_MEDIA_TURBO | | |
4357 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4358 | GEN6_RP_MEDIA_IS_GFX | | |
4359 | GEN6_RP_ENABLE | | |
4360 | GEN6_RP_UP_BUSY_AVG | | |
4361 | GEN6_RP_DOWN_IDLE_AVG); | |
4362 | ||
4363 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4364 | ||
c7f3153a TR |
4365 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
4366 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
7526ed79 | 4367 | |
59bad947 | 4368 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4369 | } |
4370 | ||
79f5b2c7 | 4371 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4372 | { |
79f5b2c7 | 4373 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4374 | struct intel_engine_cs *ring; |
d060c169 | 4375 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4376 | u32 gtfifodbg; |
2b4e57bd | 4377 | int rc6_mode; |
42c0526c | 4378 | int i, ret; |
2b4e57bd | 4379 | |
4fc688ce | 4380 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4381 | |
2b4e57bd ED |
4382 | /* Here begins a magic sequence of register writes to enable |
4383 | * auto-downclocking. | |
4384 | * | |
4385 | * Perhaps there might be some value in exposing these to | |
4386 | * userspace... | |
4387 | */ | |
4388 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4389 | |
4390 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4391 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4392 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4393 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4394 | } | |
4395 | ||
59bad947 | 4396 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4397 | |
93ee2920 TR |
4398 | /* Initialize rps frequencies */ |
4399 | gen6_init_rps_frequencies(dev); | |
dd0a1aa1 | 4400 | |
2b4e57bd ED |
4401 | /* disable the counters and set deterministic thresholds */ |
4402 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4403 | ||
4404 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4405 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4406 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4407 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4408 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4409 | ||
b4519513 CW |
4410 | for_each_ring(ring, dev_priv, i) |
4411 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4412 | |
4413 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4414 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4415 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4416 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4417 | else | |
4418 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4419 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4420 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4421 | ||
5a7dc92a | 4422 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4423 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4424 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4425 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4426 | ||
5a7dc92a ED |
4427 | /* We don't use those on Haswell */ |
4428 | if (!IS_HASWELL(dev)) { | |
4429 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4430 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4431 | |
5a7dc92a ED |
4432 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4433 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4434 | } | |
2b4e57bd | 4435 | |
dc39fff7 | 4436 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4437 | |
4438 | I915_WRITE(GEN6_RC_CONTROL, | |
4439 | rc6_mask | | |
4440 | GEN6_RC_CTL_EI_MODE(1) | | |
4441 | GEN6_RC_CTL_HW_ENABLE); | |
4442 | ||
dd75fdc8 CW |
4443 | /* Power down if completely idle for over 50ms */ |
4444 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4445 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4446 | |
42c0526c | 4447 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4448 | if (ret) |
42c0526c | 4449 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4450 | |
4451 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4452 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4453 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4454 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4455 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4456 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4457 | } |
4458 | ||
dd75fdc8 | 4459 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 4460 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 4461 | |
31643d54 BW |
4462 | rc6vids = 0; |
4463 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4464 | if (IS_GEN6(dev) && ret) { | |
4465 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4466 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4467 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4468 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4469 | rc6vids &= 0xffff00; | |
4470 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4471 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4472 | if (ret) | |
4473 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4474 | } | |
4475 | ||
59bad947 | 4476 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4477 | } |
4478 | ||
c2bc2fc5 | 4479 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4480 | { |
79f5b2c7 | 4481 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4482 | int min_freq = 15; |
3ebecd07 CW |
4483 | unsigned int gpu_freq; |
4484 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 4485 | int scaling_factor = 180; |
eda79642 | 4486 | struct cpufreq_policy *policy; |
2b4e57bd | 4487 | |
4fc688ce | 4488 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4489 | |
eda79642 BW |
4490 | policy = cpufreq_cpu_get(0); |
4491 | if (policy) { | |
4492 | max_ia_freq = policy->cpuinfo.max_freq; | |
4493 | cpufreq_cpu_put(policy); | |
4494 | } else { | |
4495 | /* | |
4496 | * Default to measured freq if none found, PCU will ensure we | |
4497 | * don't go over | |
4498 | */ | |
2b4e57bd | 4499 | max_ia_freq = tsc_khz; |
eda79642 | 4500 | } |
2b4e57bd ED |
4501 | |
4502 | /* Convert from kHz to MHz */ | |
4503 | max_ia_freq /= 1000; | |
4504 | ||
153b4b95 | 4505 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4506 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4507 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4508 | |
2b4e57bd ED |
4509 | /* |
4510 | * For each potential GPU frequency, load a ring frequency we'd like | |
4511 | * to use for memory access. We do this by specifying the IA frequency | |
4512 | * the PCU should use as a reference to determine the ring frequency. | |
4513 | */ | |
6985b352 | 4514 | for (gpu_freq = dev_priv->rps.max_freq; gpu_freq >= dev_priv->rps.min_freq; |
2b4e57bd | 4515 | gpu_freq--) { |
6985b352 | 4516 | int diff = dev_priv->rps.max_freq - gpu_freq; |
3ebecd07 CW |
4517 | unsigned int ia_freq = 0, ring_freq = 0; |
4518 | ||
46c764d4 BW |
4519 | if (INTEL_INFO(dev)->gen >= 8) { |
4520 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4521 | ring_freq = max(min_ring_freq, gpu_freq); | |
4522 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4523 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4524 | ring_freq = max(min_ring_freq, ring_freq); |
4525 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4526 | } else { | |
4527 | /* On older processors, there is no separate ring | |
4528 | * clock domain, so in order to boost the bandwidth | |
4529 | * of the ring, we need to upclock the CPU (ia_freq). | |
4530 | * | |
4531 | * For GPU frequencies less than 750MHz, | |
4532 | * just use the lowest ring freq. | |
4533 | */ | |
4534 | if (gpu_freq < min_freq) | |
4535 | ia_freq = 800; | |
4536 | else | |
4537 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4538 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4539 | } | |
2b4e57bd | 4540 | |
42c0526c BW |
4541 | sandybridge_pcode_write(dev_priv, |
4542 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4543 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4544 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4545 | gpu_freq); | |
2b4e57bd | 4546 | } |
2b4e57bd ED |
4547 | } |
4548 | ||
c2bc2fc5 ID |
4549 | void gen6_update_ring_freq(struct drm_device *dev) |
4550 | { | |
4551 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4552 | ||
4553 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4554 | return; | |
4555 | ||
4556 | mutex_lock(&dev_priv->rps.hw_lock); | |
4557 | __gen6_update_ring_freq(dev); | |
4558 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4559 | } | |
4560 | ||
03af2045 | 4561 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 4562 | { |
095acd5f | 4563 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
4564 | u32 val, rp0; |
4565 | ||
095acd5f D |
4566 | if (dev->pdev->revision >= 0x20) { |
4567 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
2b6b3a09 | 4568 | |
095acd5f D |
4569 | switch (INTEL_INFO(dev)->eu_total) { |
4570 | case 8: | |
4571 | /* (2 * 4) config */ | |
4572 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
4573 | break; | |
4574 | case 12: | |
4575 | /* (2 * 6) config */ | |
4576 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
4577 | break; | |
4578 | case 16: | |
4579 | /* (2 * 8) config */ | |
4580 | default: | |
4581 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
4582 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
4583 | break; | |
4584 | } | |
4585 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
4586 | } else { | |
4587 | /* For pre-production hardware */ | |
4588 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4589 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4590 | PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4591 | } | |
2b6b3a09 D |
4592 | return rp0; |
4593 | } | |
4594 | ||
4595 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4596 | { | |
4597 | u32 val, rpe; | |
4598 | ||
4599 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4600 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4601 | ||
4602 | return rpe; | |
4603 | } | |
4604 | ||
7707df4a D |
4605 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4606 | { | |
095acd5f | 4607 | struct drm_device *dev = dev_priv->dev; |
7707df4a D |
4608 | u32 val, rp1; |
4609 | ||
095acd5f D |
4610 | if (dev->pdev->revision >= 0x20) { |
4611 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); | |
4612 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
4613 | } else { | |
4614 | /* For pre-production hardware */ | |
4615 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4616 | rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & | |
4617 | PUNIT_GPU_STATUS_MAX_FREQ_MASK); | |
4618 | } | |
7707df4a D |
4619 | return rp1; |
4620 | } | |
4621 | ||
03af2045 | 4622 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 | 4623 | { |
095acd5f | 4624 | struct drm_device *dev = dev_priv->dev; |
2b6b3a09 D |
4625 | u32 val, rpn; |
4626 | ||
095acd5f D |
4627 | if (dev->pdev->revision >= 0x20) { |
4628 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
4629 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
4630 | FB_GFX_FREQ_FUSE_MASK); | |
4631 | } else { /* For pre-production hardware */ | |
4632 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4633 | rpn = ((val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & | |
4634 | PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK); | |
4635 | } | |
4636 | ||
2b6b3a09 D |
4637 | return rpn; |
4638 | } | |
4639 | ||
f8f2b001 D |
4640 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4641 | { | |
4642 | u32 val, rp1; | |
4643 | ||
4644 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4645 | ||
4646 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4647 | ||
4648 | return rp1; | |
4649 | } | |
4650 | ||
03af2045 | 4651 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
4652 | { |
4653 | u32 val, rp0; | |
4654 | ||
64936258 | 4655 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
4656 | |
4657 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4658 | /* Clamp to max */ | |
4659 | rp0 = min_t(u32, rp0, 0xea); | |
4660 | ||
4661 | return rp0; | |
4662 | } | |
4663 | ||
4664 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4665 | { | |
4666 | u32 val, rpe; | |
4667 | ||
64936258 | 4668 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 4669 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 4670 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
4671 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
4672 | ||
4673 | return rpe; | |
4674 | } | |
4675 | ||
03af2045 | 4676 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 4677 | { |
64936258 | 4678 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
4679 | } |
4680 | ||
ae48434c ID |
4681 | /* Check that the pctx buffer wasn't move under us. */ |
4682 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4683 | { | |
4684 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4685 | ||
4686 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4687 | dev_priv->vlv_pctx->stolen->start); | |
4688 | } | |
4689 | ||
38807746 D |
4690 | |
4691 | /* Check that the pcbr address is not empty. */ | |
4692 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4693 | { | |
4694 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4695 | ||
4696 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4697 | } | |
4698 | ||
4699 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4700 | { | |
4701 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4702 | unsigned long pctx_paddr, paddr; | |
4703 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4704 | u32 pcbr; | |
4705 | int pctx_size = 32*1024; | |
4706 | ||
4707 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4708 | ||
4709 | pcbr = I915_READ(VLV_PCBR); | |
4710 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 4711 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 D |
4712 | paddr = (dev_priv->mm.stolen_base + |
4713 | (gtt->stolen_size - pctx_size)); | |
4714 | ||
4715 | pctx_paddr = (paddr & (~4095)); | |
4716 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4717 | } | |
ce611ef8 VS |
4718 | |
4719 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
4720 | } |
4721 | ||
c9cddffc JB |
4722 | static void valleyview_setup_pctx(struct drm_device *dev) |
4723 | { | |
4724 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4725 | struct drm_i915_gem_object *pctx; | |
4726 | unsigned long pctx_paddr; | |
4727 | u32 pcbr; | |
4728 | int pctx_size = 24*1024; | |
4729 | ||
17b0c1f7 ID |
4730 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4731 | ||
c9cddffc JB |
4732 | pcbr = I915_READ(VLV_PCBR); |
4733 | if (pcbr) { | |
4734 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4735 | int pcbr_offset; | |
4736 | ||
4737 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4738 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4739 | pcbr_offset, | |
190d6cd5 | 4740 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
4741 | pctx_size); |
4742 | goto out; | |
4743 | } | |
4744 | ||
ce611ef8 VS |
4745 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
4746 | ||
c9cddffc JB |
4747 | /* |
4748 | * From the Gunit register HAS: | |
4749 | * The Gfx driver is expected to program this register and ensure | |
4750 | * proper allocation within Gfx stolen memory. For example, this | |
4751 | * register should be programmed such than the PCBR range does not | |
4752 | * overlap with other ranges, such as the frame buffer, protected | |
4753 | * memory, or any other relevant ranges. | |
4754 | */ | |
4755 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4756 | if (!pctx) { | |
4757 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4758 | return; | |
4759 | } | |
4760 | ||
4761 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4762 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4763 | ||
4764 | out: | |
ce611ef8 | 4765 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
4766 | dev_priv->vlv_pctx = pctx; |
4767 | } | |
4768 | ||
ae48434c ID |
4769 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
4770 | { | |
4771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4772 | ||
4773 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4774 | return; | |
4775 | ||
4776 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4777 | dev_priv->vlv_pctx = NULL; | |
4778 | } | |
4779 | ||
4e80519e ID |
4780 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
4781 | { | |
4782 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 4783 | u32 val; |
4e80519e ID |
4784 | |
4785 | valleyview_setup_pctx(dev); | |
4786 | ||
4787 | mutex_lock(&dev_priv->rps.hw_lock); | |
4788 | ||
2bb25c17 VS |
4789 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
4790 | switch ((val >> 6) & 3) { | |
4791 | case 0: | |
4792 | case 1: | |
4793 | dev_priv->mem_freq = 800; | |
4794 | break; | |
4795 | case 2: | |
4796 | dev_priv->mem_freq = 1066; | |
4797 | break; | |
4798 | case 3: | |
4799 | dev_priv->mem_freq = 1333; | |
4800 | break; | |
4801 | } | |
80b83b62 | 4802 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4803 | |
4e80519e ID |
4804 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
4805 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4806 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4807 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
4808 | dev_priv->rps.max_freq); |
4809 | ||
4810 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4811 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4812 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
4813 | dev_priv->rps.efficient_freq); |
4814 | ||
f8f2b001 D |
4815 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
4816 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4817 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
4818 | dev_priv->rps.rp1_freq); |
4819 | ||
4e80519e ID |
4820 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
4821 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4822 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e ID |
4823 | dev_priv->rps.min_freq); |
4824 | ||
4825 | /* Preserve min/max settings in case of re-init */ | |
4826 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4827 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4828 | ||
4829 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4830 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4831 | ||
4832 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4833 | } | |
4834 | ||
38807746 D |
4835 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
4836 | { | |
2b6b3a09 | 4837 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 4838 | u32 val; |
2b6b3a09 | 4839 | |
38807746 | 4840 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
4841 | |
4842 | mutex_lock(&dev_priv->rps.hw_lock); | |
4843 | ||
c6e8f39d VS |
4844 | mutex_lock(&dev_priv->dpio_lock); |
4845 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); | |
4846 | mutex_unlock(&dev_priv->dpio_lock); | |
4847 | ||
2bb25c17 VS |
4848 | switch ((val >> 2) & 0x7) { |
4849 | case 0: | |
4850 | case 1: | |
4851 | dev_priv->rps.cz_freq = 200; | |
4852 | dev_priv->mem_freq = 1600; | |
4853 | break; | |
4854 | case 2: | |
4855 | dev_priv->rps.cz_freq = 267; | |
4856 | dev_priv->mem_freq = 1600; | |
4857 | break; | |
4858 | case 3: | |
4859 | dev_priv->rps.cz_freq = 333; | |
4860 | dev_priv->mem_freq = 2000; | |
4861 | break; | |
4862 | case 4: | |
4863 | dev_priv->rps.cz_freq = 320; | |
4864 | dev_priv->mem_freq = 1600; | |
4865 | break; | |
4866 | case 5: | |
4867 | dev_priv->rps.cz_freq = 400; | |
4868 | dev_priv->mem_freq = 1600; | |
4869 | break; | |
4870 | } | |
80b83b62 | 4871 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 4872 | |
2b6b3a09 D |
4873 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
4874 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4875 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4876 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
4877 | dev_priv->rps.max_freq); |
4878 | ||
4879 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
4880 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4881 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
4882 | dev_priv->rps.efficient_freq); |
4883 | ||
7707df4a D |
4884 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
4885 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4886 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
4887 | dev_priv->rps.rp1_freq); |
4888 | ||
2b6b3a09 D |
4889 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
4890 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4891 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
4892 | dev_priv->rps.min_freq); |
4893 | ||
1c14762d VS |
4894 | WARN_ONCE((dev_priv->rps.max_freq | |
4895 | dev_priv->rps.efficient_freq | | |
4896 | dev_priv->rps.rp1_freq | | |
4897 | dev_priv->rps.min_freq) & 1, | |
4898 | "Odd GPU freq values\n"); | |
4899 | ||
2b6b3a09 D |
4900 | /* Preserve min/max settings in case of re-init */ |
4901 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4902 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4903 | ||
4904 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4905 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4906 | ||
4907 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
4908 | } |
4909 | ||
4e80519e ID |
4910 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
4911 | { | |
4912 | valleyview_cleanup_pctx(dev); | |
4913 | } | |
4914 | ||
38807746 D |
4915 | static void cherryview_enable_rps(struct drm_device *dev) |
4916 | { | |
4917 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4918 | struct intel_engine_cs *ring; | |
2b6b3a09 | 4919 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
4920 | int i; |
4921 | ||
4922 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
4923 | ||
4924 | gtfifodbg = I915_READ(GTFIFODBG); | |
4925 | if (gtfifodbg) { | |
4926 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
4927 | gtfifodbg); | |
4928 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4929 | } | |
4930 | ||
4931 | cherryview_check_pctx(dev_priv); | |
4932 | ||
4933 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
4934 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 4935 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 4936 | |
160614a2 VS |
4937 | /* Disable RC states. */ |
4938 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4939 | ||
38807746 D |
4940 | /* 2a: Program RC6 thresholds.*/ |
4941 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4942 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4943 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4944 | ||
4945 | for_each_ring(ring, dev_priv, i) | |
4946 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4947 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4948 | ||
af5a75a3 VS |
4949 | /* TO threshold set to 1750 us ( 0x557 * 1.28 us) */ |
4950 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); | |
38807746 D |
4951 | |
4952 | /* allows RC6 residency counter to work */ | |
4953 | I915_WRITE(VLV_COUNTER_CONTROL, | |
4954 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
4955 | VLV_MEDIA_RC6_COUNT_EN | | |
4956 | VLV_RENDER_RC6_COUNT_EN)); | |
4957 | ||
4958 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
4959 | pcbr = I915_READ(VLV_PCBR); | |
4960 | ||
38807746 D |
4961 | /* 3: Enable RC6 */ |
4962 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
4963 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 4964 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
4965 | |
4966 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
4967 | ||
2b6b3a09 | 4968 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 4969 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
4970 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
4971 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
4972 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
4973 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
4974 | ||
4975 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
4976 | ||
4977 | /* 5: Enable RPS */ | |
4978 | I915_WRITE(GEN6_RP_CONTROL, | |
4979 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 4980 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
4981 | GEN6_RP_ENABLE | |
4982 | GEN6_RP_UP_BUSY_AVG | | |
4983 | GEN6_RP_DOWN_IDLE_AVG); | |
4984 | ||
4985 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4986 | ||
8d40c3ae VS |
4987 | /* RPS code assumes GPLL is used */ |
4988 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
4989 | ||
c8e9627d | 4990 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
2b6b3a09 D |
4991 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
4992 | ||
4993 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
4994 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 4995 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
2b6b3a09 D |
4996 | dev_priv->rps.cur_freq); |
4997 | ||
4998 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
7c59a9c1 | 4999 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
5000 | dev_priv->rps.efficient_freq); |
5001 | ||
5002 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
5003 | ||
59bad947 | 5004 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
5005 | } |
5006 | ||
0a073b84 JB |
5007 | static void valleyview_enable_rps(struct drm_device *dev) |
5008 | { | |
5009 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5010 | struct intel_engine_cs *ring; |
2a5913a8 | 5011 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
5012 | int i; |
5013 | ||
5014 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5015 | ||
ae48434c ID |
5016 | valleyview_check_pctx(dev_priv); |
5017 | ||
0a073b84 | 5018 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
5019 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5020 | gtfifodbg); | |
0a073b84 JB |
5021 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5022 | } | |
5023 | ||
c8d9a590 | 5024 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 5025 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 5026 | |
160614a2 VS |
5027 | /* Disable RC states. */ |
5028 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
5029 | ||
cad725fe | 5030 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
5031 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
5032 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5033 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5034 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5035 | ||
5036 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5037 | ||
5038 | I915_WRITE(GEN6_RP_CONTROL, | |
5039 | GEN6_RP_MEDIA_TURBO | | |
5040 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5041 | GEN6_RP_MEDIA_IS_GFX | | |
5042 | GEN6_RP_ENABLE | | |
5043 | GEN6_RP_UP_BUSY_AVG | | |
5044 | GEN6_RP_DOWN_IDLE_CONT); | |
5045 | ||
5046 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
5047 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5048 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5049 | ||
5050 | for_each_ring(ring, dev_priv, i) | |
5051 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5052 | ||
2f0aa304 | 5053 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
5054 | |
5055 | /* allows RC6 residency counter to work */ | |
49798eb2 | 5056 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
5057 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5058 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
5059 | VLV_MEDIA_RC6_COUNT_EN | |
5060 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 5061 | |
a2b23fe0 | 5062 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 5063 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
5064 | |
5065 | intel_print_rc6_info(dev, rc6_mode); | |
5066 | ||
a2b23fe0 | 5067 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 5068 | |
64936258 | 5069 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 5070 | |
8d40c3ae VS |
5071 | /* RPS code assumes GPLL is used */ |
5072 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
5073 | ||
c8e9627d | 5074 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no"); |
0a073b84 JB |
5075 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
5076 | ||
b39fb297 | 5077 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 5078 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 5079 | intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
b39fb297 | 5080 | dev_priv->rps.cur_freq); |
0a073b84 | 5081 | |
73008b98 | 5082 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
7c59a9c1 | 5083 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
b39fb297 | 5084 | dev_priv->rps.efficient_freq); |
0a073b84 | 5085 | |
b39fb297 | 5086 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 5087 | |
59bad947 | 5088 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
5089 | } |
5090 | ||
dde18883 ED |
5091 | static unsigned long intel_pxfreq(u32 vidfreq) |
5092 | { | |
5093 | unsigned long freq; | |
5094 | int div = (vidfreq & 0x3f0000) >> 16; | |
5095 | int post = (vidfreq & 0x3000) >> 12; | |
5096 | int pre = (vidfreq & 0x7); | |
5097 | ||
5098 | if (!pre) | |
5099 | return 0; | |
5100 | ||
5101 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5102 | ||
5103 | return freq; | |
5104 | } | |
5105 | ||
eb48eb00 DV |
5106 | static const struct cparams { |
5107 | u16 i; | |
5108 | u16 t; | |
5109 | u16 m; | |
5110 | u16 c; | |
5111 | } cparams[] = { | |
5112 | { 1, 1333, 301, 28664 }, | |
5113 | { 1, 1066, 294, 24460 }, | |
5114 | { 1, 800, 294, 25192 }, | |
5115 | { 0, 1333, 276, 27605 }, | |
5116 | { 0, 1066, 276, 27605 }, | |
5117 | { 0, 800, 231, 23784 }, | |
5118 | }; | |
5119 | ||
f531dcb2 | 5120 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5121 | { |
5122 | u64 total_count, diff, ret; | |
5123 | u32 count1, count2, count3, m = 0, c = 0; | |
5124 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5125 | int i; | |
5126 | ||
02d71956 DV |
5127 | assert_spin_locked(&mchdev_lock); |
5128 | ||
20e4d407 | 5129 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5130 | |
5131 | /* Prevent division-by-zero if we are asking too fast. | |
5132 | * Also, we don't get interesting results if we are polling | |
5133 | * faster than once in 10ms, so just return the saved value | |
5134 | * in such cases. | |
5135 | */ | |
5136 | if (diff1 <= 10) | |
20e4d407 | 5137 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5138 | |
5139 | count1 = I915_READ(DMIEC); | |
5140 | count2 = I915_READ(DDREC); | |
5141 | count3 = I915_READ(CSIEC); | |
5142 | ||
5143 | total_count = count1 + count2 + count3; | |
5144 | ||
5145 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5146 | if (total_count < dev_priv->ips.last_count1) { |
5147 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5148 | diff += total_count; |
5149 | } else { | |
20e4d407 | 5150 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5151 | } |
5152 | ||
5153 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5154 | if (cparams[i].i == dev_priv->ips.c_m && |
5155 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5156 | m = cparams[i].m; |
5157 | c = cparams[i].c; | |
5158 | break; | |
5159 | } | |
5160 | } | |
5161 | ||
5162 | diff = div_u64(diff, diff1); | |
5163 | ret = ((m * diff) + c); | |
5164 | ret = div_u64(ret, 10); | |
5165 | ||
20e4d407 DV |
5166 | dev_priv->ips.last_count1 = total_count; |
5167 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5168 | |
20e4d407 | 5169 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5170 | |
5171 | return ret; | |
5172 | } | |
5173 | ||
f531dcb2 CW |
5174 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5175 | { | |
3d13ef2e | 5176 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5177 | unsigned long val; |
5178 | ||
3d13ef2e | 5179 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5180 | return 0; |
5181 | ||
5182 | spin_lock_irq(&mchdev_lock); | |
5183 | ||
5184 | val = __i915_chipset_val(dev_priv); | |
5185 | ||
5186 | spin_unlock_irq(&mchdev_lock); | |
5187 | ||
5188 | return val; | |
5189 | } | |
5190 | ||
eb48eb00 DV |
5191 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5192 | { | |
5193 | unsigned long m, x, b; | |
5194 | u32 tsfs; | |
5195 | ||
5196 | tsfs = I915_READ(TSFS); | |
5197 | ||
5198 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5199 | x = I915_READ8(TR1); | |
5200 | ||
5201 | b = tsfs & TSFS_INTR_MASK; | |
5202 | ||
5203 | return ((m * x) / 127) - b; | |
5204 | } | |
5205 | ||
d972d6ee MK |
5206 | static int _pxvid_to_vd(u8 pxvid) |
5207 | { | |
5208 | if (pxvid == 0) | |
5209 | return 0; | |
5210 | ||
5211 | if (pxvid >= 8 && pxvid < 31) | |
5212 | pxvid = 31; | |
5213 | ||
5214 | return (pxvid + 2) * 125; | |
5215 | } | |
5216 | ||
5217 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 5218 | { |
3d13ef2e | 5219 | struct drm_device *dev = dev_priv->dev; |
d972d6ee MK |
5220 | const int vd = _pxvid_to_vd(pxvid); |
5221 | const int vm = vd - 1125; | |
5222 | ||
3d13ef2e | 5223 | if (INTEL_INFO(dev)->is_mobile) |
d972d6ee MK |
5224 | return vm > 0 ? vm : 0; |
5225 | ||
5226 | return vd; | |
eb48eb00 DV |
5227 | } |
5228 | ||
02d71956 | 5229 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5230 | { |
5ed0bdf2 | 5231 | u64 now, diff, diffms; |
eb48eb00 DV |
5232 | u32 count; |
5233 | ||
02d71956 | 5234 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5235 | |
5ed0bdf2 TG |
5236 | now = ktime_get_raw_ns(); |
5237 | diffms = now - dev_priv->ips.last_time2; | |
5238 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5239 | |
5240 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5241 | if (!diffms) |
5242 | return; | |
5243 | ||
5244 | count = I915_READ(GFXEC); | |
5245 | ||
20e4d407 DV |
5246 | if (count < dev_priv->ips.last_count2) { |
5247 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5248 | diff += count; |
5249 | } else { | |
20e4d407 | 5250 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5251 | } |
5252 | ||
20e4d407 DV |
5253 | dev_priv->ips.last_count2 = count; |
5254 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5255 | |
5256 | /* More magic constants... */ | |
5257 | diff = diff * 1181; | |
5258 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5259 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5260 | } |
5261 | ||
02d71956 DV |
5262 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5263 | { | |
3d13ef2e DL |
5264 | struct drm_device *dev = dev_priv->dev; |
5265 | ||
5266 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5267 | return; |
5268 | ||
9270388e | 5269 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5270 | |
5271 | __i915_update_gfx_val(dev_priv); | |
5272 | ||
9270388e | 5273 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5274 | } |
5275 | ||
f531dcb2 | 5276 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5277 | { |
5278 | unsigned long t, corr, state1, corr2, state2; | |
5279 | u32 pxvid, ext_v; | |
5280 | ||
02d71956 DV |
5281 | assert_spin_locked(&mchdev_lock); |
5282 | ||
b39fb297 | 5283 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
5284 | pxvid = (pxvid >> 24) & 0x7f; |
5285 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5286 | ||
5287 | state1 = ext_v; | |
5288 | ||
5289 | t = i915_mch_val(dev_priv); | |
5290 | ||
5291 | /* Revel in the empirically derived constants */ | |
5292 | ||
5293 | /* Correction factor in 1/100000 units */ | |
5294 | if (t > 80) | |
5295 | corr = ((t * 2349) + 135940); | |
5296 | else if (t >= 50) | |
5297 | corr = ((t * 964) + 29317); | |
5298 | else /* < 50 */ | |
5299 | corr = ((t * 301) + 1004); | |
5300 | ||
5301 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5302 | corr /= 100000; | |
20e4d407 | 5303 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5304 | |
5305 | state2 = (corr2 * state1) / 10000; | |
5306 | state2 /= 100; /* convert to mW */ | |
5307 | ||
02d71956 | 5308 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5309 | |
20e4d407 | 5310 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5311 | } |
5312 | ||
f531dcb2 CW |
5313 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5314 | { | |
3d13ef2e | 5315 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5316 | unsigned long val; |
5317 | ||
3d13ef2e | 5318 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5319 | return 0; |
5320 | ||
5321 | spin_lock_irq(&mchdev_lock); | |
5322 | ||
5323 | val = __i915_gfx_val(dev_priv); | |
5324 | ||
5325 | spin_unlock_irq(&mchdev_lock); | |
5326 | ||
5327 | return val; | |
5328 | } | |
5329 | ||
eb48eb00 DV |
5330 | /** |
5331 | * i915_read_mch_val - return value for IPS use | |
5332 | * | |
5333 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5334 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5335 | */ | |
5336 | unsigned long i915_read_mch_val(void) | |
5337 | { | |
5338 | struct drm_i915_private *dev_priv; | |
5339 | unsigned long chipset_val, graphics_val, ret = 0; | |
5340 | ||
9270388e | 5341 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5342 | if (!i915_mch_dev) |
5343 | goto out_unlock; | |
5344 | dev_priv = i915_mch_dev; | |
5345 | ||
f531dcb2 CW |
5346 | chipset_val = __i915_chipset_val(dev_priv); |
5347 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5348 | |
5349 | ret = chipset_val + graphics_val; | |
5350 | ||
5351 | out_unlock: | |
9270388e | 5352 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5353 | |
5354 | return ret; | |
5355 | } | |
5356 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5357 | ||
5358 | /** | |
5359 | * i915_gpu_raise - raise GPU frequency limit | |
5360 | * | |
5361 | * Raise the limit; IPS indicates we have thermal headroom. | |
5362 | */ | |
5363 | bool i915_gpu_raise(void) | |
5364 | { | |
5365 | struct drm_i915_private *dev_priv; | |
5366 | bool ret = true; | |
5367 | ||
9270388e | 5368 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5369 | if (!i915_mch_dev) { |
5370 | ret = false; | |
5371 | goto out_unlock; | |
5372 | } | |
5373 | dev_priv = i915_mch_dev; | |
5374 | ||
20e4d407 DV |
5375 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5376 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5377 | |
5378 | out_unlock: | |
9270388e | 5379 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5380 | |
5381 | return ret; | |
5382 | } | |
5383 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5384 | ||
5385 | /** | |
5386 | * i915_gpu_lower - lower GPU frequency limit | |
5387 | * | |
5388 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5389 | * frequency maximum. | |
5390 | */ | |
5391 | bool i915_gpu_lower(void) | |
5392 | { | |
5393 | struct drm_i915_private *dev_priv; | |
5394 | bool ret = true; | |
5395 | ||
9270388e | 5396 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5397 | if (!i915_mch_dev) { |
5398 | ret = false; | |
5399 | goto out_unlock; | |
5400 | } | |
5401 | dev_priv = i915_mch_dev; | |
5402 | ||
20e4d407 DV |
5403 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5404 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5405 | |
5406 | out_unlock: | |
9270388e | 5407 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5408 | |
5409 | return ret; | |
5410 | } | |
5411 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5412 | ||
5413 | /** | |
5414 | * i915_gpu_busy - indicate GPU business to IPS | |
5415 | * | |
5416 | * Tell the IPS driver whether or not the GPU is busy. | |
5417 | */ | |
5418 | bool i915_gpu_busy(void) | |
5419 | { | |
5420 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5421 | struct intel_engine_cs *ring; |
eb48eb00 | 5422 | bool ret = false; |
f047e395 | 5423 | int i; |
eb48eb00 | 5424 | |
9270388e | 5425 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5426 | if (!i915_mch_dev) |
5427 | goto out_unlock; | |
5428 | dev_priv = i915_mch_dev; | |
5429 | ||
f047e395 CW |
5430 | for_each_ring(ring, dev_priv, i) |
5431 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5432 | |
5433 | out_unlock: | |
9270388e | 5434 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5435 | |
5436 | return ret; | |
5437 | } | |
5438 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5439 | ||
5440 | /** | |
5441 | * i915_gpu_turbo_disable - disable graphics turbo | |
5442 | * | |
5443 | * Disable graphics turbo by resetting the max frequency and setting the | |
5444 | * current frequency to the default. | |
5445 | */ | |
5446 | bool i915_gpu_turbo_disable(void) | |
5447 | { | |
5448 | struct drm_i915_private *dev_priv; | |
5449 | bool ret = true; | |
5450 | ||
9270388e | 5451 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5452 | if (!i915_mch_dev) { |
5453 | ret = false; | |
5454 | goto out_unlock; | |
5455 | } | |
5456 | dev_priv = i915_mch_dev; | |
5457 | ||
20e4d407 | 5458 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5459 | |
20e4d407 | 5460 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5461 | ret = false; |
5462 | ||
5463 | out_unlock: | |
9270388e | 5464 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5465 | |
5466 | return ret; | |
5467 | } | |
5468 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5469 | ||
5470 | /** | |
5471 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5472 | * IPS got loaded first. | |
5473 | * | |
5474 | * This awkward dance is so that neither module has to depend on the | |
5475 | * other in order for IPS to do the appropriate communication of | |
5476 | * GPU turbo limits to i915. | |
5477 | */ | |
5478 | static void | |
5479 | ips_ping_for_i915_load(void) | |
5480 | { | |
5481 | void (*link)(void); | |
5482 | ||
5483 | link = symbol_get(ips_link_to_i915_driver); | |
5484 | if (link) { | |
5485 | link(); | |
5486 | symbol_put(ips_link_to_i915_driver); | |
5487 | } | |
5488 | } | |
5489 | ||
5490 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5491 | { | |
02d71956 DV |
5492 | /* We only register the i915 ips part with intel-ips once everything is |
5493 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5494 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5495 | i915_mch_dev = dev_priv; |
9270388e | 5496 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5497 | |
5498 | ips_ping_for_i915_load(); | |
5499 | } | |
5500 | ||
5501 | void intel_gpu_ips_teardown(void) | |
5502 | { | |
9270388e | 5503 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5504 | i915_mch_dev = NULL; |
9270388e | 5505 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5506 | } |
76c3552f | 5507 | |
8090c6b9 | 5508 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5509 | { |
5510 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5511 | u32 lcfuse; | |
5512 | u8 pxw[16]; | |
5513 | int i; | |
5514 | ||
5515 | /* Disable to program */ | |
5516 | I915_WRITE(ECR, 0); | |
5517 | POSTING_READ(ECR); | |
5518 | ||
5519 | /* Program energy weights for various events */ | |
5520 | I915_WRITE(SDEW, 0x15040d00); | |
5521 | I915_WRITE(CSIEW0, 0x007f0000); | |
5522 | I915_WRITE(CSIEW1, 0x1e220004); | |
5523 | I915_WRITE(CSIEW2, 0x04000004); | |
5524 | ||
5525 | for (i = 0; i < 5; i++) | |
5526 | I915_WRITE(PEW + (i * 4), 0); | |
5527 | for (i = 0; i < 3; i++) | |
5528 | I915_WRITE(DEW + (i * 4), 0); | |
5529 | ||
5530 | /* Program P-state weights to account for frequency power adjustment */ | |
5531 | for (i = 0; i < 16; i++) { | |
5532 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5533 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5534 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5535 | PXVFREQ_PX_SHIFT; | |
5536 | unsigned long val; | |
5537 | ||
5538 | val = vid * vid; | |
5539 | val *= (freq / 1000); | |
5540 | val *= 255; | |
5541 | val /= (127*127*900); | |
5542 | if (val > 0xff) | |
5543 | DRM_ERROR("bad pxval: %ld\n", val); | |
5544 | pxw[i] = val; | |
5545 | } | |
5546 | /* Render standby states get 0 weight */ | |
5547 | pxw[14] = 0; | |
5548 | pxw[15] = 0; | |
5549 | ||
5550 | for (i = 0; i < 4; i++) { | |
5551 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5552 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5553 | I915_WRITE(PXW + (i * 4), val); | |
5554 | } | |
5555 | ||
5556 | /* Adjust magic regs to magic values (more experimental results) */ | |
5557 | I915_WRITE(OGW0, 0); | |
5558 | I915_WRITE(OGW1, 0); | |
5559 | I915_WRITE(EG0, 0x00007f00); | |
5560 | I915_WRITE(EG1, 0x0000000e); | |
5561 | I915_WRITE(EG2, 0x000e0000); | |
5562 | I915_WRITE(EG3, 0x68000300); | |
5563 | I915_WRITE(EG4, 0x42000000); | |
5564 | I915_WRITE(EG5, 0x00140031); | |
5565 | I915_WRITE(EG6, 0); | |
5566 | I915_WRITE(EG7, 0); | |
5567 | ||
5568 | for (i = 0; i < 8; i++) | |
5569 | I915_WRITE(PXWL + (i * 4), 0); | |
5570 | ||
5571 | /* Enable PMON + select events */ | |
5572 | I915_WRITE(ECR, 0x80000019); | |
5573 | ||
5574 | lcfuse = I915_READ(LCFUSE02); | |
5575 | ||
20e4d407 | 5576 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5577 | } |
5578 | ||
ae48434c ID |
5579 | void intel_init_gt_powersave(struct drm_device *dev) |
5580 | { | |
e6069ca8 ID |
5581 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5582 | ||
38807746 D |
5583 | if (IS_CHERRYVIEW(dev)) |
5584 | cherryview_init_gt_powersave(dev); | |
5585 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5586 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
5587 | } |
5588 | ||
5589 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5590 | { | |
38807746 D |
5591 | if (IS_CHERRYVIEW(dev)) |
5592 | return; | |
5593 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5594 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
5595 | } |
5596 | ||
dbea3cea ID |
5597 | static void gen6_suspend_rps(struct drm_device *dev) |
5598 | { | |
5599 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5600 | ||
5601 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
5602 | ||
5603 | /* | |
5604 | * TODO: disable RPS interrupts on GEN9+ too once RPS support | |
5605 | * is added for it. | |
5606 | */ | |
5607 | if (INTEL_INFO(dev)->gen < 9) | |
5608 | gen6_disable_rps_interrupts(dev); | |
5609 | } | |
5610 | ||
156c7ca0 JB |
5611 | /** |
5612 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
5613 | * @dev: drm device | |
5614 | * | |
5615 | * We don't want to disable RC6 or other features here, we just want | |
5616 | * to make sure any work we've queued has finished and won't bother | |
5617 | * us while we're suspended. | |
5618 | */ | |
5619 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
5620 | { | |
5621 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5622 | ||
d4d70aa5 ID |
5623 | if (INTEL_INFO(dev)->gen < 6) |
5624 | return; | |
5625 | ||
dbea3cea | 5626 | gen6_suspend_rps(dev); |
b47adc17 D |
5627 | |
5628 | /* Force GPU to min freq during suspend */ | |
5629 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
5630 | } |
5631 | ||
8090c6b9 DV |
5632 | void intel_disable_gt_powersave(struct drm_device *dev) |
5633 | { | |
1a01ab3b JB |
5634 | struct drm_i915_private *dev_priv = dev->dev_private; |
5635 | ||
930ebb46 | 5636 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 5637 | ironlake_disable_drps(dev); |
38807746 | 5638 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 5639 | intel_suspend_gt_powersave(dev); |
e494837a | 5640 | |
4fc688ce | 5641 | mutex_lock(&dev_priv->rps.hw_lock); |
20e49366 ZW |
5642 | if (INTEL_INFO(dev)->gen >= 9) |
5643 | gen9_disable_rps(dev); | |
5644 | else if (IS_CHERRYVIEW(dev)) | |
38807746 D |
5645 | cherryview_disable_rps(dev); |
5646 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
5647 | valleyview_disable_rps(dev); |
5648 | else | |
5649 | gen6_disable_rps(dev); | |
e534770a | 5650 | |
c0951f0c | 5651 | dev_priv->rps.enabled = false; |
4fc688ce | 5652 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 5653 | } |
8090c6b9 DV |
5654 | } |
5655 | ||
1a01ab3b JB |
5656 | static void intel_gen6_powersave_work(struct work_struct *work) |
5657 | { | |
5658 | struct drm_i915_private *dev_priv = | |
5659 | container_of(work, struct drm_i915_private, | |
5660 | rps.delayed_resume_work.work); | |
5661 | struct drm_device *dev = dev_priv->dev; | |
5662 | ||
4fc688ce | 5663 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 5664 | |
3cc134e3 ID |
5665 | /* |
5666 | * TODO: reset/enable RPS interrupts on GEN9+ too, once RPS support is | |
5667 | * added for it. | |
5668 | */ | |
5669 | if (INTEL_INFO(dev)->gen < 9) | |
5670 | gen6_reset_rps_interrupts(dev); | |
5671 | ||
38807746 D |
5672 | if (IS_CHERRYVIEW(dev)) { |
5673 | cherryview_enable_rps(dev); | |
5674 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 5675 | valleyview_enable_rps(dev); |
20e49366 | 5676 | } else if (INTEL_INFO(dev)->gen >= 9) { |
b6fef0ef | 5677 | gen9_enable_rc6(dev); |
20e49366 | 5678 | gen9_enable_rps(dev); |
b6fef0ef | 5679 | __gen6_update_ring_freq(dev); |
6edee7f3 BW |
5680 | } else if (IS_BROADWELL(dev)) { |
5681 | gen8_enable_rps(dev); | |
c2bc2fc5 | 5682 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
5683 | } else { |
5684 | gen6_enable_rps(dev); | |
c2bc2fc5 | 5685 | __gen6_update_ring_freq(dev); |
0a073b84 | 5686 | } |
c0951f0c | 5687 | dev_priv->rps.enabled = true; |
3cc134e3 ID |
5688 | |
5689 | if (INTEL_INFO(dev)->gen < 9) | |
5690 | gen6_enable_rps_interrupts(dev); | |
5691 | ||
4fc688ce | 5692 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
5693 | |
5694 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
5695 | } |
5696 | ||
8090c6b9 DV |
5697 | void intel_enable_gt_powersave(struct drm_device *dev) |
5698 | { | |
1a01ab3b JB |
5699 | struct drm_i915_private *dev_priv = dev->dev_private; |
5700 | ||
f61018b1 YZ |
5701 | /* Powersaving is controlled by the host when inside a VM */ |
5702 | if (intel_vgpu_active(dev)) | |
5703 | return; | |
5704 | ||
8090c6b9 | 5705 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 5706 | mutex_lock(&dev->struct_mutex); |
8090c6b9 | 5707 | ironlake_enable_drps(dev); |
8090c6b9 | 5708 | intel_init_emon(dev); |
dc1d0136 | 5709 | mutex_unlock(&dev->struct_mutex); |
38807746 | 5710 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
5711 | /* |
5712 | * PCU communication is slow and this doesn't need to be | |
5713 | * done at any specific time, so do this out of our fast path | |
5714 | * to make resume and init faster. | |
c6df39b5 ID |
5715 | * |
5716 | * We depend on the HW RC6 power context save/restore | |
5717 | * mechanism when entering D3 through runtime PM suspend. So | |
5718 | * disable RPM until RPS/RC6 is properly setup. We can only | |
5719 | * get here via the driver load/system resume/runtime resume | |
5720 | * paths, so the _noresume version is enough (and in case of | |
5721 | * runtime resume it's necessary). | |
1a01ab3b | 5722 | */ |
c6df39b5 ID |
5723 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
5724 | round_jiffies_up_relative(HZ))) | |
5725 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
5726 | } |
5727 | } | |
5728 | ||
c6df39b5 ID |
5729 | void intel_reset_gt_powersave(struct drm_device *dev) |
5730 | { | |
5731 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5732 | ||
dbea3cea ID |
5733 | if (INTEL_INFO(dev)->gen < 6) |
5734 | return; | |
5735 | ||
5736 | gen6_suspend_rps(dev); | |
c6df39b5 | 5737 | dev_priv->rps.enabled = false; |
c6df39b5 ID |
5738 | } |
5739 | ||
3107bd48 DV |
5740 | static void ibx_init_clock_gating(struct drm_device *dev) |
5741 | { | |
5742 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5743 | ||
5744 | /* | |
5745 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5746 | * gating for the panel power sequencer or it will fail to | |
5747 | * start up when no ports are active. | |
5748 | */ | |
5749 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
5750 | } | |
5751 | ||
0e088b8f VS |
5752 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
5753 | { | |
5754 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5755 | int pipe; | |
5756 | ||
055e393f | 5757 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
5758 | I915_WRITE(DSPCNTR(pipe), |
5759 | I915_READ(DSPCNTR(pipe)) | | |
5760 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 5761 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
5762 | } |
5763 | } | |
5764 | ||
017636cc VS |
5765 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
5766 | { | |
5767 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5768 | ||
5769 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
5770 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
5771 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
5772 | ||
5773 | /* | |
5774 | * Don't touch WM1S_LP_EN here. | |
5775 | * Doing so could cause underruns. | |
5776 | */ | |
5777 | } | |
5778 | ||
1fa61106 | 5779 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5780 | { |
5781 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5782 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5783 | |
f1e8fa56 DL |
5784 | /* |
5785 | * Required for FBC | |
5786 | * WaFbcDisableDpfcClockGating:ilk | |
5787 | */ | |
4d47e4f5 DL |
5788 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
5789 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
5790 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
5791 | |
5792 | I915_WRITE(PCH_3DCGDIS0, | |
5793 | MARIUNIT_CLOCK_GATE_DISABLE | | |
5794 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
5795 | I915_WRITE(PCH_3DCGDIS1, | |
5796 | VFMUNIT_CLOCK_GATE_DISABLE); | |
5797 | ||
6f1d69b0 ED |
5798 | /* |
5799 | * According to the spec the following bits should be set in | |
5800 | * order to enable memory self-refresh | |
5801 | * The bit 22/21 of 0x42004 | |
5802 | * The bit 5 of 0x42020 | |
5803 | * The bit 15 of 0x45000 | |
5804 | */ | |
5805 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5806 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5807 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 5808 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
5809 | I915_WRITE(DISP_ARB_CTL, |
5810 | (I915_READ(DISP_ARB_CTL) | | |
5811 | DISP_FBC_WM_DIS)); | |
017636cc VS |
5812 | |
5813 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
5814 | |
5815 | /* | |
5816 | * Based on the document from hardware guys the following bits | |
5817 | * should be set unconditionally in order to enable FBC. | |
5818 | * The bit 22 of 0x42000 | |
5819 | * The bit 22 of 0x42004 | |
5820 | * The bit 7,8,9 of 0x42020. | |
5821 | */ | |
5822 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 5823 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
5824 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
5825 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5826 | ILK_FBCQ_DIS); | |
5827 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5828 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5829 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
5830 | } |
5831 | ||
4d47e4f5 DL |
5832 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
5833 | ||
6f1d69b0 ED |
5834 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
5835 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5836 | ILK_ELPIN_409_SELECT); | |
5837 | I915_WRITE(_3D_CHICKEN2, | |
5838 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
5839 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 5840 | |
ecdb4eb7 | 5841 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
5842 | I915_WRITE(CACHE_MODE_0, |
5843 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 5844 | |
4e04632e AG |
5845 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
5846 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5847 | ||
0e088b8f | 5848 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 5849 | |
3107bd48 DV |
5850 | ibx_init_clock_gating(dev); |
5851 | } | |
5852 | ||
5853 | static void cpt_init_clock_gating(struct drm_device *dev) | |
5854 | { | |
5855 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5856 | int pipe; | |
3f704fa2 | 5857 | uint32_t val; |
3107bd48 DV |
5858 | |
5859 | /* | |
5860 | * On Ibex Peak and Cougar Point, we need to disable clock | |
5861 | * gating for the panel power sequencer or it will fail to | |
5862 | * start up when no ports are active. | |
5863 | */ | |
cd664078 JB |
5864 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
5865 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
5866 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
5867 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
5868 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
5869 | /* The below fixes the weird display corruption, a few pixels shifted |
5870 | * downward, on (only) LVDS of some HP laptops with IVY. | |
5871 | */ | |
055e393f | 5872 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
5873 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
5874 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
5875 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 5876 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 5877 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
5878 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
5879 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
5880 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
5881 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
5882 | } | |
3107bd48 | 5883 | /* WADP0ClockGatingDisable */ |
055e393f | 5884 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
5885 | I915_WRITE(TRANS_CHICKEN1(pipe), |
5886 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
5887 | } | |
6f1d69b0 ED |
5888 | } |
5889 | ||
1d7aaa0c DV |
5890 | static void gen6_check_mch_setup(struct drm_device *dev) |
5891 | { | |
5892 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5893 | uint32_t tmp; | |
5894 | ||
5895 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
5896 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
5897 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
5898 | tmp); | |
1d7aaa0c DV |
5899 | } |
5900 | ||
1fa61106 | 5901 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
5902 | { |
5903 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 5904 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 5905 | |
231e54f6 | 5906 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
5907 | |
5908 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5909 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5910 | ILK_ELPIN_409_SELECT); | |
5911 | ||
ecdb4eb7 | 5912 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
5913 | I915_WRITE(_3D_CHICKEN, |
5914 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
5915 | ||
4e04632e AG |
5916 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
5917 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
5918 | ||
8d85d272 VS |
5919 | /* |
5920 | * BSpec recoomends 8x4 when MSAA is used, | |
5921 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
5922 | * |
5923 | * Note that PS/WM thread counts depend on the WIZ hashing | |
5924 | * disable bit, which we don't touch here, but it's good | |
5925 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
5926 | */ |
5927 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 5928 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 5929 | |
017636cc | 5930 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 5931 | |
6f1d69b0 | 5932 | I915_WRITE(CACHE_MODE_0, |
50743298 | 5933 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
5934 | |
5935 | I915_WRITE(GEN6_UCGCTL1, | |
5936 | I915_READ(GEN6_UCGCTL1) | | |
5937 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
5938 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
5939 | ||
5940 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
5941 | * gating disable must be set. Failure to set it results in | |
5942 | * flickering pixels due to Z write ordering failures after | |
5943 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
5944 | * Sanctuary and Tropics, and apparently anything else with | |
5945 | * alpha test or pixel discard. | |
5946 | * | |
5947 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
5948 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 5949 | * |
ef59318c VS |
5950 | * WaDisableRCCUnitClockGating:snb |
5951 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
5952 | */ |
5953 | I915_WRITE(GEN6_UCGCTL2, | |
5954 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
5955 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
5956 | ||
5eb146dd | 5957 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
5958 | I915_WRITE(_3D_CHICKEN3, |
5959 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 5960 | |
e927ecde VS |
5961 | /* |
5962 | * Bspec says: | |
5963 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
5964 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
5965 | */ | |
5966 | I915_WRITE(_3D_CHICKEN3, | |
5967 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
5968 | ||
6f1d69b0 ED |
5969 | /* |
5970 | * According to the spec the following bits should be | |
5971 | * set in order to enable memory self-refresh and fbc: | |
5972 | * The bit21 and bit22 of 0x42000 | |
5973 | * The bit21 and bit22 of 0x42004 | |
5974 | * The bit5 and bit7 of 0x42020 | |
5975 | * The bit14 of 0x70180 | |
5976 | * The bit14 of 0x71180 | |
4bb35334 DL |
5977 | * |
5978 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
5979 | */ |
5980 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
5981 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
5982 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
5983 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
5984 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
5985 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
5986 | I915_WRITE(ILK_DSPCLK_GATE_D, |
5987 | I915_READ(ILK_DSPCLK_GATE_D) | | |
5988 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
5989 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 5990 | |
0e088b8f | 5991 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 5992 | |
3107bd48 | 5993 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
5994 | |
5995 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
5996 | } |
5997 | ||
5998 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
5999 | { | |
6000 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
6001 | ||
3aad9059 | 6002 | /* |
46680e0a | 6003 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
6004 | * |
6005 | * This actually overrides the dispatch | |
6006 | * mode for all thread types. | |
6007 | */ | |
6f1d69b0 ED |
6008 | reg &= ~GEN7_FF_SCHED_MASK; |
6009 | reg |= GEN7_FF_TS_SCHED_HW; | |
6010 | reg |= GEN7_FF_VS_SCHED_HW; | |
6011 | reg |= GEN7_FF_DS_SCHED_HW; | |
6012 | ||
6013 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
6014 | } | |
6015 | ||
17a303ec PZ |
6016 | static void lpt_init_clock_gating(struct drm_device *dev) |
6017 | { | |
6018 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6019 | ||
6020 | /* | |
6021 | * TODO: this bit should only be enabled when really needed, then | |
6022 | * disabled when not needed anymore in order to save power. | |
6023 | */ | |
6024 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
6025 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
6026 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6027 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6028 | |
6029 | /* WADPOClockGatingDisable:hsw */ | |
6030 | I915_WRITE(_TRANSA_CHICKEN1, | |
6031 | I915_READ(_TRANSA_CHICKEN1) | | |
6032 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
6033 | } |
6034 | ||
7d708ee4 ID |
6035 | static void lpt_suspend_hw(struct drm_device *dev) |
6036 | { | |
6037 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6038 | ||
6039 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6040 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6041 | ||
6042 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6043 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6044 | } | |
6045 | } | |
6046 | ||
47c2bd97 | 6047 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6048 | { |
6049 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6050 | enum pipe pipe; |
1020a5c2 BW |
6051 | |
6052 | I915_WRITE(WM3_LP_ILK, 0); | |
6053 | I915_WRITE(WM2_LP_ILK, 0); | |
6054 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd | 6055 | |
ab57fff1 | 6056 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6057 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6058 | |
ab57fff1 | 6059 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6060 | I915_WRITE(CHICKEN_PAR1_1, |
6061 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6062 | ||
ab57fff1 | 6063 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6064 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6065 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6066 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6067 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6068 | } |
63801f21 | 6069 | |
ab57fff1 BW |
6070 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6071 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6072 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6073 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6074 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6075 | |
295e8bb7 VS |
6076 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6077 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6078 | |
6079 | /* WaDisableSDEUnitClockGating:bdw */ | |
6080 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6081 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6082 | |
89d6b2b8 | 6083 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6084 | } |
6085 | ||
cad2a2d7 ED |
6086 | static void haswell_init_clock_gating(struct drm_device *dev) |
6087 | { | |
6088 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6089 | |
017636cc | 6090 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6091 | |
f3fc4884 FJ |
6092 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6093 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6094 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6095 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6096 | ||
ecdb4eb7 | 6097 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6098 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6099 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6100 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6101 | ||
e36ea7ff VS |
6102 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6103 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6104 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6105 | |
4e04632e AG |
6106 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6107 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6108 | ||
fe27c606 CW |
6109 | /* enable HiZ Raw Stall Optimization */ |
6110 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6111 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6112 | ||
ecdb4eb7 | 6113 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6114 | I915_WRITE(CACHE_MODE_1, |
6115 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6116 | |
a12c4967 VS |
6117 | /* |
6118 | * BSpec recommends 8x4 when MSAA is used, | |
6119 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6120 | * |
6121 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6122 | * disable bit, which we don't touch here, but it's good | |
6123 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6124 | */ |
6125 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6126 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 6127 | |
94411593 KG |
6128 | /* WaSampleCChickenBitEnable:hsw */ |
6129 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
6130 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
6131 | ||
ecdb4eb7 | 6132 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6133 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6134 | ||
90a88643 PZ |
6135 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6136 | I915_WRITE(CHICKEN_PAR1_1, | |
6137 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6138 | |
17a303ec | 6139 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6140 | } |
6141 | ||
1fa61106 | 6142 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6143 | { |
6144 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6145 | uint32_t snpcr; |
6f1d69b0 | 6146 | |
017636cc | 6147 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6148 | |
231e54f6 | 6149 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6150 | |
ecdb4eb7 | 6151 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6152 | I915_WRITE(_3D_CHICKEN3, |
6153 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6154 | ||
ecdb4eb7 | 6155 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6156 | I915_WRITE(IVB_CHICKEN3, |
6157 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6158 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6159 | ||
ecdb4eb7 | 6160 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6161 | if (IS_IVB_GT1(dev)) |
6162 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6163 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6164 | |
4e04632e AG |
6165 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6166 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6167 | ||
ecdb4eb7 | 6168 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6169 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6170 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6171 | ||
ecdb4eb7 | 6172 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6173 | I915_WRITE(GEN7_L3CNTLREG1, |
6174 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6175 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6176 | GEN7_WA_L3_CHICKEN_MODE); |
6177 | if (IS_IVB_GT1(dev)) | |
6178 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6179 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6180 | else { |
6181 | /* must write both registers */ | |
6182 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6183 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6184 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6185 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6186 | } |
6f1d69b0 | 6187 | |
ecdb4eb7 | 6188 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6189 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6190 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6191 | ||
1b80a19a | 6192 | /* |
0f846f81 | 6193 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6194 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6195 | */ |
6196 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6197 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6198 | |
ecdb4eb7 | 6199 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6200 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6201 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6202 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6203 | ||
0e088b8f | 6204 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6205 | |
6206 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6207 | |
22721343 CW |
6208 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6209 | /* enable HiZ Raw Stall Optimization */ | |
6210 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6211 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6212 | } | |
116f2b6d | 6213 | |
ecdb4eb7 | 6214 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6215 | I915_WRITE(CACHE_MODE_1, |
6216 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6217 | |
a607c1a4 VS |
6218 | /* |
6219 | * BSpec recommends 8x4 when MSAA is used, | |
6220 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6221 | * |
6222 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6223 | * disable bit, which we don't touch here, but it's good | |
6224 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6225 | */ |
6226 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 6227 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 6228 | |
20848223 BW |
6229 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6230 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6231 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6232 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6233 | |
ab5c608b BW |
6234 | if (!HAS_PCH_NOP(dev)) |
6235 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6236 | |
6237 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6238 | } |
6239 | ||
c6beb13e VS |
6240 | static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv) |
6241 | { | |
6242 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6243 | ||
6244 | /* | |
6245 | * Disable trickle feed and enable pnd deadline calculation | |
6246 | */ | |
6247 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
6248 | I915_WRITE(CBR1_VLV, 0); | |
6249 | } | |
6250 | ||
1fa61106 | 6251 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6252 | { |
6253 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6254 | |
c6beb13e | 6255 | vlv_init_display_clock_gating(dev_priv); |
6f1d69b0 | 6256 | |
ecdb4eb7 | 6257 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6258 | I915_WRITE(_3D_CHICKEN3, |
6259 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6260 | ||
ecdb4eb7 | 6261 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6262 | I915_WRITE(IVB_CHICKEN3, |
6263 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6264 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6265 | ||
fad7d36e | 6266 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6267 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6268 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6269 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6270 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6271 | |
4e04632e AG |
6272 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6273 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6274 | ||
ecdb4eb7 | 6275 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6276 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6277 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6278 | ||
ecdb4eb7 | 6279 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6280 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6281 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6282 | ||
ecdb4eb7 | 6283 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6284 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6285 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6286 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6287 | ||
46680e0a VS |
6288 | gen7_setup_fixed_func_scheduler(dev_priv); |
6289 | ||
3c0edaeb | 6290 | /* |
0f846f81 | 6291 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6292 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6293 | */ |
6294 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6295 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6296 | |
c98f5062 AG |
6297 | /* WaDisableL3Bank2xClockGate:vlv |
6298 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6299 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6300 | I915_WRITE(GEN7_UCGCTL4, | |
6301 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6302 | |
afd58e79 VS |
6303 | /* |
6304 | * BSpec says this must be set, even though | |
6305 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6306 | */ | |
6b26c86d DV |
6307 | I915_WRITE(CACHE_MODE_1, |
6308 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6309 | |
da2518f9 VS |
6310 | /* |
6311 | * BSpec recommends 8x4 when MSAA is used, | |
6312 | * however in practice 16x4 seems fastest. | |
6313 | * | |
6314 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6315 | * disable bit, which we don't touch here, but it's good | |
6316 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
6317 | */ | |
6318 | I915_WRITE(GEN7_GT_MODE, | |
6319 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
6320 | ||
031994ee VS |
6321 | /* |
6322 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6323 | * This is the hardware default actually. | |
6324 | */ | |
6325 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6326 | ||
2d809570 | 6327 | /* |
ecdb4eb7 | 6328 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6329 | * Disable clock gating on th GCFG unit to prevent a delay |
6330 | * in the reporting of vblank events. | |
6331 | */ | |
7a0d1eed | 6332 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6333 | } |
6334 | ||
a4565da8 VS |
6335 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6336 | { | |
6337 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6338 | ||
c6beb13e | 6339 | vlv_init_display_clock_gating(dev_priv); |
dd811e70 | 6340 | |
232ce337 VS |
6341 | /* WaVSRefCountFullforceMissDisable:chv */ |
6342 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6343 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6344 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6345 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6346 | |
6347 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6348 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6349 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6350 | |
6351 | /* WaDisableCSUnitClockGating:chv */ | |
6352 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6353 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6354 | |
6355 | /* WaDisableSDEUnitClockGating:chv */ | |
6356 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6357 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
a4565da8 VS |
6358 | } |
6359 | ||
1fa61106 | 6360 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6361 | { |
6362 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6363 | uint32_t dspclk_gate; | |
6364 | ||
6365 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6366 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6367 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6368 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6369 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6370 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6371 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6372 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6373 | if (IS_GM45(dev)) | |
6374 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6375 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6376 | |
6377 | /* WaDisableRenderCachePipelinedFlush */ | |
6378 | I915_WRITE(CACHE_MODE_0, | |
6379 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6380 | |
4e04632e AG |
6381 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6382 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6383 | ||
0e088b8f | 6384 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6385 | } |
6386 | ||
1fa61106 | 6387 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6388 | { |
6389 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6390 | ||
6391 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6392 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6393 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6394 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6395 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6396 | I915_WRITE(MI_ARB_STATE, |
6397 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6398 | |
6399 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6400 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6401 | } |
6402 | ||
1fa61106 | 6403 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6404 | { |
6405 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6406 | ||
6407 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6408 | I965_RCC_CLOCK_GATE_DISABLE | | |
6409 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6410 | I965_ISC_CLOCK_GATE_DISABLE | | |
6411 | I965_FBC_CLOCK_GATE_DISABLE); | |
6412 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6413 | I915_WRITE(MI_ARB_STATE, |
6414 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6415 | |
6416 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6417 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6418 | } |
6419 | ||
1fa61106 | 6420 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6421 | { |
6422 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6423 | u32 dstate = I915_READ(D_STATE); | |
6424 | ||
6425 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6426 | DSTATE_DOT_CLOCK_GATING; | |
6427 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6428 | |
6429 | if (IS_PINEVIEW(dev)) | |
6430 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6431 | |
6432 | /* IIR "flip pending" means done if this bit is set */ | |
6433 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6434 | |
6435 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6436 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6437 | |
6438 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6439 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6440 | |
6441 | I915_WRITE(MI_ARB_STATE, | |
6442 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6443 | } |
6444 | ||
1fa61106 | 6445 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6446 | { |
6447 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6448 | ||
6449 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6450 | |
6451 | /* interrupts should cause a wake up from C3 */ | |
6452 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6453 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6454 | |
6455 | I915_WRITE(MEM_MODE, | |
6456 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6457 | } |
6458 | ||
1fa61106 | 6459 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6460 | { |
6461 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6462 | ||
6463 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6464 | |
6465 | I915_WRITE(MEM_MODE, | |
6466 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6467 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6468 | } |
6469 | ||
6f1d69b0 ED |
6470 | void intel_init_clock_gating(struct drm_device *dev) |
6471 | { | |
6472 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6473 | ||
c57e3551 DL |
6474 | if (dev_priv->display.init_clock_gating) |
6475 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6476 | } |
6477 | ||
7d708ee4 ID |
6478 | void intel_suspend_hw(struct drm_device *dev) |
6479 | { | |
6480 | if (HAS_PCH_LPT(dev)) | |
6481 | lpt_suspend_hw(dev); | |
6482 | } | |
6483 | ||
1fa61106 ED |
6484 | /* Set up chip specific power management-related functions */ |
6485 | void intel_init_pm(struct drm_device *dev) | |
6486 | { | |
6487 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6488 | ||
7ff0ebcc | 6489 | intel_fbc_init(dev_priv); |
1fa61106 | 6490 | |
c921aba8 DV |
6491 | /* For cxsr */ |
6492 | if (IS_PINEVIEW(dev)) | |
6493 | i915_pineview_get_mem_freq(dev); | |
6494 | else if (IS_GEN5(dev)) | |
6495 | i915_ironlake_get_mem_freq(dev); | |
6496 | ||
1fa61106 | 6497 | /* For FIFO watermark updates */ |
f5ed50cb | 6498 | if (INTEL_INFO(dev)->gen >= 9) { |
2af30a5c PB |
6499 | skl_setup_wm_latency(dev); |
6500 | ||
45db2194 | 6501 | dev_priv->display.init_clock_gating = skl_init_clock_gating; |
2d41c0b5 PB |
6502 | dev_priv->display.update_wm = skl_update_wm; |
6503 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; | |
c83155a6 | 6504 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 6505 | ilk_setup_wm_latency(dev); |
53615a5e | 6506 | |
bd602544 VS |
6507 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6508 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6509 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6510 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6511 | dev_priv->display.update_wm = ilk_update_wm; | |
6512 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6513 | } else { | |
6514 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6515 | "Disable CxSR\n"); | |
6516 | } | |
6517 | ||
6518 | if (IS_GEN5(dev)) | |
1fa61106 | 6519 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6520 | else if (IS_GEN6(dev)) |
1fa61106 | 6521 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6522 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6523 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6524 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6525 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6526 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 6527 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 6528 | } else if (IS_CHERRYVIEW(dev)) { |
ae80152d | 6529 | dev_priv->display.update_wm = valleyview_update_wm; |
01e184cc | 6530 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
a4565da8 VS |
6531 | dev_priv->display.init_clock_gating = |
6532 | cherryview_init_clock_gating; | |
1fa61106 ED |
6533 | } else if (IS_VALLEYVIEW(dev)) { |
6534 | dev_priv->display.update_wm = valleyview_update_wm; | |
01e184cc | 6535 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
1fa61106 ED |
6536 | dev_priv->display.init_clock_gating = |
6537 | valleyview_init_clock_gating; | |
1fa61106 ED |
6538 | } else if (IS_PINEVIEW(dev)) { |
6539 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6540 | dev_priv->is_ddr3, | |
6541 | dev_priv->fsb_freq, | |
6542 | dev_priv->mem_freq)) { | |
6543 | DRM_INFO("failed to find known CxSR latency " | |
6544 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6545 | "disabling CxSR\n", | |
6546 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6547 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6548 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6549 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6550 | dev_priv->display.update_wm = NULL; |
6551 | } else | |
6552 | dev_priv->display.update_wm = pineview_update_wm; | |
6553 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6554 | } else if (IS_G4X(dev)) { | |
6555 | dev_priv->display.update_wm = g4x_update_wm; | |
6556 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6557 | } else if (IS_GEN4(dev)) { | |
6558 | dev_priv->display.update_wm = i965_update_wm; | |
6559 | if (IS_CRESTLINE(dev)) | |
6560 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6561 | else if (IS_BROADWATER(dev)) | |
6562 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6563 | } else if (IS_GEN3(dev)) { | |
6564 | dev_priv->display.update_wm = i9xx_update_wm; | |
6565 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6566 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6567 | } else if (IS_GEN2(dev)) { |
6568 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6569 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6570 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6571 | } else { |
6572 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6573 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6574 | } |
6575 | ||
6576 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6577 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6578 | else | |
6579 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6580 | } else { | |
6581 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6582 | } |
6583 | } | |
6584 | ||
151a49d0 | 6585 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 6586 | { |
4fc688ce | 6587 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6588 | |
6589 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6590 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6591 | return -EAGAIN; | |
6592 | } | |
6593 | ||
6594 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
dddab346 | 6595 | I915_WRITE(GEN6_PCODE_DATA1, 0); |
42c0526c BW |
6596 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
6597 | ||
6598 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6599 | 500)) { | |
6600 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6601 | return -ETIMEDOUT; | |
6602 | } | |
6603 | ||
6604 | *val = I915_READ(GEN6_PCODE_DATA); | |
6605 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6606 | ||
6607 | return 0; | |
6608 | } | |
6609 | ||
151a49d0 | 6610 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val) |
42c0526c | 6611 | { |
4fc688ce | 6612 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6613 | |
6614 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6615 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
6616 | return -EAGAIN; | |
6617 | } | |
6618 | ||
6619 | I915_WRITE(GEN6_PCODE_DATA, val); | |
6620 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
6621 | ||
6622 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6623 | 500)) { | |
6624 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
6625 | return -ETIMEDOUT; | |
6626 | } | |
6627 | ||
6628 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
6629 | ||
6630 | return 0; | |
6631 | } | |
a0e4e199 | 6632 | |
dd06f88c | 6633 | static int vlv_gpu_freq_div(unsigned int czclk_freq) |
855ba3be | 6634 | { |
dd06f88c VS |
6635 | switch (czclk_freq) { |
6636 | case 200: | |
6637 | return 10; | |
6638 | case 267: | |
6639 | return 12; | |
6640 | case 320: | |
6641 | case 333: | |
dd06f88c | 6642 | return 16; |
ab3fb157 VS |
6643 | case 400: |
6644 | return 20; | |
855ba3be JB |
6645 | default: |
6646 | return -1; | |
6647 | } | |
dd06f88c | 6648 | } |
855ba3be | 6649 | |
dd06f88c VS |
6650 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
6651 | { | |
6652 | int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); | |
6653 | ||
6654 | div = vlv_gpu_freq_div(czclk_freq); | |
6655 | if (div < 0) | |
6656 | return div; | |
6657 | ||
6658 | return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div); | |
855ba3be JB |
6659 | } |
6660 | ||
b55dd647 | 6661 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 6662 | { |
dd06f88c | 6663 | int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4); |
855ba3be | 6664 | |
dd06f88c VS |
6665 | mul = vlv_gpu_freq_div(czclk_freq); |
6666 | if (mul < 0) | |
6667 | return mul; | |
855ba3be | 6668 | |
dd06f88c | 6669 | return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6; |
855ba3be JB |
6670 | } |
6671 | ||
b55dd647 | 6672 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6673 | { |
dd06f88c | 6674 | int div, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6675 | |
dd06f88c VS |
6676 | div = vlv_gpu_freq_div(czclk_freq) / 2; |
6677 | if (div < 0) | |
6678 | return div; | |
22b1b2f8 | 6679 | |
dd06f88c | 6680 | return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2; |
22b1b2f8 D |
6681 | } |
6682 | ||
b55dd647 | 6683 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6684 | { |
dd06f88c | 6685 | int mul, czclk_freq = dev_priv->rps.cz_freq; |
22b1b2f8 | 6686 | |
dd06f88c VS |
6687 | mul = vlv_gpu_freq_div(czclk_freq) / 2; |
6688 | if (mul < 0) | |
6689 | return mul; | |
22b1b2f8 | 6690 | |
1c14762d | 6691 | /* CHV needs even values */ |
dd06f88c | 6692 | return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2; |
22b1b2f8 D |
6693 | } |
6694 | ||
616bc820 | 6695 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 6696 | { |
22b1b2f8 | 6697 | if (IS_CHERRYVIEW(dev_priv->dev)) |
616bc820 | 6698 | return chv_gpu_freq(dev_priv, val); |
22b1b2f8 | 6699 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6700 | return byt_gpu_freq(dev_priv, val); |
6701 | else | |
6702 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
6703 | } |
6704 | ||
616bc820 VS |
6705 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
6706 | { | |
22b1b2f8 | 6707 | if (IS_CHERRYVIEW(dev_priv->dev)) |
616bc820 | 6708 | return chv_freq_opcode(dev_priv, val); |
22b1b2f8 | 6709 | else if (IS_VALLEYVIEW(dev_priv->dev)) |
616bc820 VS |
6710 | return byt_freq_opcode(dev_priv, val); |
6711 | else | |
6712 | return val / GT_FREQUENCY_MULTIPLIER; | |
6713 | } | |
22b1b2f8 | 6714 | |
f742a552 | 6715 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
6716 | { |
6717 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6718 | ||
f742a552 DV |
6719 | mutex_init(&dev_priv->rps.hw_lock); |
6720 | ||
907b28c5 CW |
6721 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
6722 | intel_gen6_powersave_work); | |
5d584b2e | 6723 | |
33688d95 | 6724 | dev_priv->pm.suspended = false; |
907b28c5 | 6725 | } |