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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
9c2f7a9d | 29 | #include <drm/drm_plane_helper.h> |
85208be0 ED |
30 | #include "i915_drv.h" |
31 | #include "intel_drv.h" | |
eb48eb00 DV |
32 | #include "../../../platform/x86/intel_ips.h" |
33 | #include <linux/module.h> | |
c8fe32c1 | 34 | #include <drm/drm_atomic_helper.h> |
85208be0 | 35 | |
dc39fff7 | 36 | /** |
18afd443 JN |
37 | * DOC: RC6 |
38 | * | |
dc39fff7 BW |
39 | * RC6 is a special power stage which allows the GPU to enter an very |
40 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
41 | * stage is entered automatically when the GPU is idle when RC6 support is | |
42 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
43 | * | |
44 | * There are different RC6 modes available in Intel GPU, which differentiate | |
45 | * among each other with the latency required to enter and leave RC6 and | |
46 | * voltage consumed by the GPU in different states. | |
47 | * | |
48 | * The combination of the following flags define which states GPU is allowed | |
49 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
50 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
51 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
52 | * which brings the most power savings; deeper states save more power, but | |
53 | * require higher latency to switch to and wake up. | |
54 | */ | |
55 | #define INTEL_RC6_ENABLE (1<<0) | |
56 | #define INTEL_RC6p_ENABLE (1<<1) | |
57 | #define INTEL_RC6pp_ENABLE (1<<2) | |
58 | ||
46f16e63 | 59 | static void gen9_init_clock_gating(struct drm_i915_private *dev_priv) |
a82abe43 | 60 | { |
82525c17 | 61 | /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl,cfl */ |
dc00b6a0 DV |
62 | I915_WRITE(CHICKEN_PAR1_1, |
63 | I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP); | |
64 | ||
2e2adb05 VS |
65 | /* |
66 | * Display WA#0390: skl,bxt,kbl,glk | |
67 | * | |
68 | * Must match Sampler, Pixel Back End, and Media | |
69 | * (0xE194 bit 8, 0x7014 bit 13, 0x4DDC bits 27 and 31). | |
70 | * | |
71 | * Including bits outside the page in the hash would | |
72 | * require 2 (or 4?) MiB alignment of resources. Just | |
73 | * assume the defaul hashing mode which only uses bits | |
74 | * within the page. | |
75 | */ | |
76 | I915_WRITE(CHICKEN_PAR1_1, | |
77 | I915_READ(CHICKEN_PAR1_1) & ~SKL_RC_HASH_OUTSIDE); | |
78 | ||
b033bb6d MK |
79 | I915_WRITE(GEN8_CONFIG0, |
80 | I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES); | |
590e8ff0 | 81 | |
82525c17 | 82 | /* WaEnableChickenDCPR:skl,bxt,kbl,glk,cfl */ |
590e8ff0 MK |
83 | I915_WRITE(GEN8_CHICKEN_DCPR_1, |
84 | I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); | |
0f78dee6 | 85 | |
82525c17 RV |
86 | /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl,cfl */ |
87 | /* WaFbcWakeMemOn:skl,bxt,kbl,glk,cfl */ | |
303d4ea5 MK |
88 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | |
89 | DISP_FBC_WM_DIS | | |
90 | DISP_FBC_MEMORY_WAKE); | |
d1b4eefd | 91 | |
82525c17 | 92 | /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl,cfl */ |
d1b4eefd MK |
93 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | |
94 | ILK_DPFC_DISABLE_DUMMY0); | |
32087d14 PP |
95 | |
96 | if (IS_SKYLAKE(dev_priv)) { | |
97 | /* WaDisableDopClockGating */ | |
98 | I915_WRITE(GEN7_MISCCPCTL, I915_READ(GEN7_MISCCPCTL) | |
99 | & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
100 | } | |
b033bb6d MK |
101 | } |
102 | ||
46f16e63 | 103 | static void bxt_init_clock_gating(struct drm_i915_private *dev_priv) |
b033bb6d | 104 | { |
46f16e63 | 105 | gen9_init_clock_gating(dev_priv); |
b033bb6d | 106 | |
a7546159 NH |
107 | /* WaDisableSDEUnitClockGating:bxt */ |
108 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
109 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
110 | ||
32608ca2 ID |
111 | /* |
112 | * FIXME: | |
868434c5 | 113 | * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only. |
32608ca2 | 114 | */ |
32608ca2 | 115 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | |
868434c5 | 116 | GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ); |
d965e7ac ID |
117 | |
118 | /* | |
119 | * Wa: Backlight PWM may stop in the asserted state, causing backlight | |
120 | * to stay fully on. | |
121 | */ | |
8aeaf64c JN |
122 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | |
123 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
a82abe43 ID |
124 | } |
125 | ||
9fb5026f ACO |
126 | static void glk_init_clock_gating(struct drm_i915_private *dev_priv) |
127 | { | |
128 | gen9_init_clock_gating(dev_priv); | |
129 | ||
130 | /* | |
131 | * WaDisablePWMClockGating:glk | |
132 | * Backlight PWM may stop in the asserted state, causing backlight | |
133 | * to stay fully on. | |
134 | */ | |
135 | I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) | | |
136 | PWM1_GATING_DIS | PWM2_GATING_DIS); | |
f4f4b59b ACO |
137 | |
138 | /* WaDDIIOTimeout:glk */ | |
139 | if (IS_GLK_REVID(dev_priv, 0, GLK_REVID_A1)) { | |
140 | u32 val = I915_READ(CHICKEN_MISC_2); | |
141 | val &= ~(GLK_CL0_PWR_DOWN | | |
142 | GLK_CL1_PWR_DOWN | | |
143 | GLK_CL2_PWR_DOWN); | |
144 | I915_WRITE(CHICKEN_MISC_2, val); | |
145 | } | |
146 | ||
9fb5026f ACO |
147 | } |
148 | ||
148ac1f3 | 149 | static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 150 | { |
c921aba8 DV |
151 | u32 tmp; |
152 | ||
153 | tmp = I915_READ(CLKCFG); | |
154 | ||
155 | switch (tmp & CLKCFG_FSB_MASK) { | |
156 | case CLKCFG_FSB_533: | |
157 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
158 | break; | |
159 | case CLKCFG_FSB_800: | |
160 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
161 | break; | |
162 | case CLKCFG_FSB_667: | |
163 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
164 | break; | |
165 | case CLKCFG_FSB_400: | |
166 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
167 | break; | |
168 | } | |
169 | ||
170 | switch (tmp & CLKCFG_MEM_MASK) { | |
171 | case CLKCFG_MEM_533: | |
172 | dev_priv->mem_freq = 533; | |
173 | break; | |
174 | case CLKCFG_MEM_667: | |
175 | dev_priv->mem_freq = 667; | |
176 | break; | |
177 | case CLKCFG_MEM_800: | |
178 | dev_priv->mem_freq = 800; | |
179 | break; | |
180 | } | |
181 | ||
182 | /* detect pineview DDR3 setting */ | |
183 | tmp = I915_READ(CSHRDDR3CTL); | |
184 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
185 | } | |
186 | ||
148ac1f3 | 187 | static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv) |
c921aba8 | 188 | { |
c921aba8 DV |
189 | u16 ddrpll, csipll; |
190 | ||
191 | ddrpll = I915_READ16(DDRMPLL1); | |
192 | csipll = I915_READ16(CSIPLL0); | |
193 | ||
194 | switch (ddrpll & 0xff) { | |
195 | case 0xc: | |
196 | dev_priv->mem_freq = 800; | |
197 | break; | |
198 | case 0x10: | |
199 | dev_priv->mem_freq = 1066; | |
200 | break; | |
201 | case 0x14: | |
202 | dev_priv->mem_freq = 1333; | |
203 | break; | |
204 | case 0x18: | |
205 | dev_priv->mem_freq = 1600; | |
206 | break; | |
207 | default: | |
208 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
209 | ddrpll & 0xff); | |
210 | dev_priv->mem_freq = 0; | |
211 | break; | |
212 | } | |
213 | ||
20e4d407 | 214 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
215 | |
216 | switch (csipll & 0x3ff) { | |
217 | case 0x00c: | |
218 | dev_priv->fsb_freq = 3200; | |
219 | break; | |
220 | case 0x00e: | |
221 | dev_priv->fsb_freq = 3733; | |
222 | break; | |
223 | case 0x010: | |
224 | dev_priv->fsb_freq = 4266; | |
225 | break; | |
226 | case 0x012: | |
227 | dev_priv->fsb_freq = 4800; | |
228 | break; | |
229 | case 0x014: | |
230 | dev_priv->fsb_freq = 5333; | |
231 | break; | |
232 | case 0x016: | |
233 | dev_priv->fsb_freq = 5866; | |
234 | break; | |
235 | case 0x018: | |
236 | dev_priv->fsb_freq = 6400; | |
237 | break; | |
238 | default: | |
239 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
240 | csipll & 0x3ff); | |
241 | dev_priv->fsb_freq = 0; | |
242 | break; | |
243 | } | |
244 | ||
245 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 246 | dev_priv->ips.c_m = 0; |
c921aba8 | 247 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 248 | dev_priv->ips.c_m = 1; |
c921aba8 | 249 | } else { |
20e4d407 | 250 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
251 | } |
252 | } | |
253 | ||
b445e3b0 ED |
254 | static const struct cxsr_latency cxsr_latency_table[] = { |
255 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
256 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
257 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
258 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
259 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
260 | ||
261 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
262 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
263 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
264 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
265 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
266 | ||
267 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
268 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
269 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
270 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
271 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
272 | ||
273 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
274 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
275 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
276 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
277 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
278 | ||
279 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
280 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
281 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
282 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
283 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
284 | ||
285 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
286 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
287 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
288 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
289 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
290 | }; | |
291 | ||
44a655ca TU |
292 | static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop, |
293 | bool is_ddr3, | |
b445e3b0 ED |
294 | int fsb, |
295 | int mem) | |
296 | { | |
297 | const struct cxsr_latency *latency; | |
298 | int i; | |
299 | ||
300 | if (fsb == 0 || mem == 0) | |
301 | return NULL; | |
302 | ||
303 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
304 | latency = &cxsr_latency_table[i]; | |
305 | if (is_desktop == latency->is_desktop && | |
306 | is_ddr3 == latency->is_ddr3 && | |
307 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
308 | return latency; | |
309 | } | |
310 | ||
311 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
312 | ||
313 | return NULL; | |
314 | } | |
315 | ||
fc1ac8de VS |
316 | static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable) |
317 | { | |
318 | u32 val; | |
319 | ||
320 | mutex_lock(&dev_priv->rps.hw_lock); | |
321 | ||
322 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
323 | if (enable) | |
324 | val &= ~FORCE_DDR_HIGH_FREQ; | |
325 | else | |
326 | val |= FORCE_DDR_HIGH_FREQ; | |
327 | val &= ~FORCE_DDR_LOW_FREQ; | |
328 | val |= FORCE_DDR_FREQ_REQ_ACK; | |
329 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
330 | ||
331 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
332 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) | |
333 | DRM_ERROR("timed out waiting for Punit DDR DVFS request\n"); | |
334 | ||
335 | mutex_unlock(&dev_priv->rps.hw_lock); | |
336 | } | |
337 | ||
cfb41411 VS |
338 | static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable) |
339 | { | |
340 | u32 val; | |
341 | ||
342 | mutex_lock(&dev_priv->rps.hw_lock); | |
343 | ||
344 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
345 | if (enable) | |
346 | val |= DSP_MAXFIFO_PM5_ENABLE; | |
347 | else | |
348 | val &= ~DSP_MAXFIFO_PM5_ENABLE; | |
349 | vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val); | |
350 | ||
351 | mutex_unlock(&dev_priv->rps.hw_lock); | |
352 | } | |
353 | ||
f4998963 VS |
354 | #define FW_WM(value, plane) \ |
355 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK) | |
356 | ||
11a85d6a | 357 | static bool _intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 358 | { |
11a85d6a | 359 | bool was_enabled; |
5209b1f4 | 360 | u32 val; |
b445e3b0 | 361 | |
920a14b2 | 362 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
11a85d6a | 363 | was_enabled = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5209b1f4 | 364 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); |
a7a6c498 | 365 | POSTING_READ(FW_BLC_SELF_VLV); |
c0f86832 | 366 | } else if (IS_G4X(dev_priv) || IS_I965GM(dev_priv)) { |
11a85d6a | 367 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 | 368 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); |
a7a6c498 | 369 | POSTING_READ(FW_BLC_SELF); |
9b1e14f4 | 370 | } else if (IS_PINEVIEW(dev_priv)) { |
11a85d6a VS |
371 | val = I915_READ(DSPFW3); |
372 | was_enabled = val & PINEVIEW_SELF_REFRESH_EN; | |
373 | if (enable) | |
374 | val |= PINEVIEW_SELF_REFRESH_EN; | |
375 | else | |
376 | val &= ~PINEVIEW_SELF_REFRESH_EN; | |
5209b1f4 | 377 | I915_WRITE(DSPFW3, val); |
a7a6c498 | 378 | POSTING_READ(DSPFW3); |
50a0bc90 | 379 | } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) { |
11a85d6a | 380 | was_enabled = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; |
5209b1f4 ID |
381 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : |
382 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
383 | I915_WRITE(FW_BLC_SELF, val); | |
a7a6c498 | 384 | POSTING_READ(FW_BLC_SELF); |
50a0bc90 | 385 | } else if (IS_I915GM(dev_priv)) { |
acb91359 VS |
386 | /* |
387 | * FIXME can't find a bit like this for 915G, and | |
388 | * and yet it does have the related watermark in | |
389 | * FW_BLC_SELF. What's going on? | |
390 | */ | |
11a85d6a | 391 | was_enabled = I915_READ(INSTPM) & INSTPM_SELF_EN; |
5209b1f4 ID |
392 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : |
393 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
394 | I915_WRITE(INSTPM, val); | |
a7a6c498 | 395 | POSTING_READ(INSTPM); |
5209b1f4 | 396 | } else { |
11a85d6a | 397 | return false; |
5209b1f4 | 398 | } |
b445e3b0 | 399 | |
1489bba8 VS |
400 | trace_intel_memory_cxsr(dev_priv, was_enabled, enable); |
401 | ||
11a85d6a VS |
402 | DRM_DEBUG_KMS("memory self-refresh is %s (was %s)\n", |
403 | enableddisabled(enable), | |
404 | enableddisabled(was_enabled)); | |
405 | ||
406 | return was_enabled; | |
b445e3b0 ED |
407 | } |
408 | ||
62571fc3 VS |
409 | /** |
410 | * intel_set_memory_cxsr - Configure CxSR state | |
411 | * @dev_priv: i915 device | |
412 | * @enable: Allow vs. disallow CxSR | |
413 | * | |
414 | * Allow or disallow the system to enter a special CxSR | |
415 | * (C-state self refresh) state. What typically happens in CxSR mode | |
416 | * is that several display FIFOs may get combined into a single larger | |
417 | * FIFO for a particular plane (so called max FIFO mode) to allow the | |
418 | * system to defer memory fetches longer, and the memory will enter | |
419 | * self refresh. | |
420 | * | |
421 | * Note that enabling CxSR does not guarantee that the system enter | |
422 | * this special mode, nor does it guarantee that the system stays | |
423 | * in that mode once entered. So this just allows/disallows the system | |
424 | * to autonomously utilize the CxSR mode. Other factors such as core | |
425 | * C-states will affect when/if the system actually enters/exits the | |
426 | * CxSR mode. | |
427 | * | |
428 | * Note that on VLV/CHV this actually only controls the max FIFO mode, | |
429 | * and the system is free to enter/exit memory self refresh at any time | |
430 | * even when the use of CxSR has been disallowed. | |
431 | * | |
432 | * While the system is actually in the CxSR/max FIFO mode, some plane | |
433 | * control registers will not get latched on vblank. Thus in order to | |
434 | * guarantee the system will respond to changes in the plane registers | |
435 | * we must always disallow CxSR prior to making changes to those registers. | |
436 | * Unfortunately the system will re-evaluate the CxSR conditions at | |
437 | * frame start which happens after vblank start (which is when the plane | |
438 | * registers would get latched), so we can't proceed with the plane update | |
439 | * during the same frame where we disallowed CxSR. | |
440 | * | |
441 | * Certain platforms also have a deeper HPLL SR mode. Fortunately the | |
442 | * HPLL SR mode depends on CxSR itself, so we don't have to hand hold | |
443 | * the hardware w.r.t. HPLL SR when writing to plane registers. | |
444 | * Disallowing just CxSR is sufficient. | |
445 | */ | |
11a85d6a | 446 | bool intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
3d90e649 | 447 | { |
11a85d6a VS |
448 | bool ret; |
449 | ||
3d90e649 | 450 | mutex_lock(&dev_priv->wm.wm_mutex); |
11a85d6a | 451 | ret = _intel_set_memory_cxsr(dev_priv, enable); |
04548cba VS |
452 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
453 | dev_priv->wm.vlv.cxsr = enable; | |
454 | else if (IS_G4X(dev_priv)) | |
455 | dev_priv->wm.g4x.cxsr = enable; | |
3d90e649 | 456 | mutex_unlock(&dev_priv->wm.wm_mutex); |
11a85d6a VS |
457 | |
458 | return ret; | |
3d90e649 | 459 | } |
fc1ac8de | 460 | |
b445e3b0 ED |
461 | /* |
462 | * Latency for FIFO fetches is dependent on several factors: | |
463 | * - memory configuration (speed, channels) | |
464 | * - chipset | |
465 | * - current MCH state | |
466 | * It can be fairly high in some situations, so here we assume a fairly | |
467 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
468 | * set this value too high, the FIFO will fetch frequently to stay full) | |
469 | * and power consumption (set it too low to save power and we might see | |
470 | * FIFO underruns and display "flicker"). | |
471 | * | |
472 | * A value of 5us seems to be a good balance; safe for very low end | |
473 | * platforms but not overly aggressive on lower latency configs. | |
474 | */ | |
5aef6003 | 475 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 476 | |
b5004720 VS |
477 | #define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \ |
478 | ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8)) | |
479 | ||
814e7f0b | 480 | static void vlv_get_fifo_size(struct intel_crtc_state *crtc_state) |
b5004720 | 481 | { |
814e7f0b | 482 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 483 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b | 484 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
f07d43d2 VS |
485 | enum pipe pipe = crtc->pipe; |
486 | int sprite0_start, sprite1_start; | |
49845a23 | 487 | |
f07d43d2 | 488 | switch (pipe) { |
b5004720 VS |
489 | uint32_t dsparb, dsparb2, dsparb3; |
490 | case PIPE_A: | |
491 | dsparb = I915_READ(DSPARB); | |
492 | dsparb2 = I915_READ(DSPARB2); | |
493 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0); | |
494 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4); | |
495 | break; | |
496 | case PIPE_B: | |
497 | dsparb = I915_READ(DSPARB); | |
498 | dsparb2 = I915_READ(DSPARB2); | |
499 | sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8); | |
500 | sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12); | |
501 | break; | |
502 | case PIPE_C: | |
503 | dsparb2 = I915_READ(DSPARB2); | |
504 | dsparb3 = I915_READ(DSPARB3); | |
505 | sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16); | |
506 | sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20); | |
507 | break; | |
508 | default: | |
f07d43d2 VS |
509 | MISSING_CASE(pipe); |
510 | return; | |
b5004720 VS |
511 | } |
512 | ||
f07d43d2 VS |
513 | fifo_state->plane[PLANE_PRIMARY] = sprite0_start; |
514 | fifo_state->plane[PLANE_SPRITE0] = sprite1_start - sprite0_start; | |
515 | fifo_state->plane[PLANE_SPRITE1] = 511 - sprite1_start; | |
516 | fifo_state->plane[PLANE_CURSOR] = 63; | |
b5004720 VS |
517 | } |
518 | ||
ef0f5e93 | 519 | static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 520 | { |
b445e3b0 ED |
521 | uint32_t dsparb = I915_READ(DSPARB); |
522 | int size; | |
523 | ||
524 | size = dsparb & 0x7f; | |
525 | if (plane) | |
526 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
527 | ||
528 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
529 | plane ? "B" : "A", size); | |
530 | ||
531 | return size; | |
532 | } | |
533 | ||
ef0f5e93 | 534 | static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 535 | { |
b445e3b0 ED |
536 | uint32_t dsparb = I915_READ(DSPARB); |
537 | int size; | |
538 | ||
539 | size = dsparb & 0x1ff; | |
540 | if (plane) | |
541 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
542 | size >>= 1; /* Convert to cachelines */ | |
543 | ||
544 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
545 | plane ? "B" : "A", size); | |
546 | ||
547 | return size; | |
548 | } | |
549 | ||
ef0f5e93 | 550 | static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane) |
b445e3b0 | 551 | { |
b445e3b0 ED |
552 | uint32_t dsparb = I915_READ(DSPARB); |
553 | int size; | |
554 | ||
555 | size = dsparb & 0x7f; | |
556 | size >>= 2; /* Convert to cachelines */ | |
557 | ||
558 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
559 | plane ? "B" : "A", | |
560 | size); | |
561 | ||
562 | return size; | |
563 | } | |
564 | ||
b445e3b0 ED |
565 | /* Pineview has different values for various configs */ |
566 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
567 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
568 | .max_wm = PINEVIEW_MAX_WM, | |
569 | .default_wm = PINEVIEW_DFT_WM, | |
570 | .guard_size = PINEVIEW_GUARD_WM, | |
571 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
572 | }; |
573 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
574 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
575 | .max_wm = PINEVIEW_MAX_WM, | |
576 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
577 | .guard_size = PINEVIEW_GUARD_WM, | |
578 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
579 | }; |
580 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
581 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
582 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
583 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
584 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
585 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
586 | }; |
587 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
588 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
589 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
590 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
591 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
592 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 | 593 | }; |
b445e3b0 | 594 | static const struct intel_watermark_params i965_cursor_wm_info = { |
e0f0273e VS |
595 | .fifo_size = I965_CURSOR_FIFO, |
596 | .max_wm = I965_CURSOR_MAX_WM, | |
597 | .default_wm = I965_CURSOR_DFT_WM, | |
598 | .guard_size = 2, | |
599 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
600 | }; |
601 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
602 | .fifo_size = I945_FIFO_SIZE, |
603 | .max_wm = I915_MAX_WM, | |
604 | .default_wm = 1, | |
605 | .guard_size = 2, | |
606 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
607 | }; |
608 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
609 | .fifo_size = I915_FIFO_SIZE, |
610 | .max_wm = I915_MAX_WM, | |
611 | .default_wm = 1, | |
612 | .guard_size = 2, | |
613 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 614 | }; |
9d539105 | 615 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
616 | .fifo_size = I855GM_FIFO_SIZE, |
617 | .max_wm = I915_MAX_WM, | |
618 | .default_wm = 1, | |
619 | .guard_size = 2, | |
620 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 621 | }; |
9d539105 VS |
622 | static const struct intel_watermark_params i830_bc_wm_info = { |
623 | .fifo_size = I855GM_FIFO_SIZE, | |
624 | .max_wm = I915_MAX_WM/2, | |
625 | .default_wm = 1, | |
626 | .guard_size = 2, | |
627 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
628 | }; | |
feb56b93 | 629 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
630 | .fifo_size = I830_FIFO_SIZE, |
631 | .max_wm = I915_MAX_WM, | |
632 | .default_wm = 1, | |
633 | .guard_size = 2, | |
634 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
635 | }; |
636 | ||
baf69ca8 VS |
637 | /** |
638 | * intel_wm_method1 - Method 1 / "small buffer" watermark formula | |
639 | * @pixel_rate: Pipe pixel rate in kHz | |
640 | * @cpp: Plane bytes per pixel | |
641 | * @latency: Memory wakeup latency in 0.1us units | |
642 | * | |
643 | * Compute the watermark using the method 1 or "small buffer" | |
644 | * formula. The caller may additonally add extra cachelines | |
645 | * to account for TLB misses and clock crossings. | |
646 | * | |
647 | * This method is concerned with the short term drain rate | |
648 | * of the FIFO, ie. it does not account for blanking periods | |
649 | * which would effectively reduce the average drain rate across | |
650 | * a longer period. The name "small" refers to the fact the | |
651 | * FIFO is relatively small compared to the amount of data | |
652 | * fetched. | |
653 | * | |
654 | * The FIFO level vs. time graph might look something like: | |
655 | * | |
656 | * |\ |\ | |
657 | * | \ | \ | |
658 | * __---__---__ (- plane active, _ blanking) | |
659 | * -> time | |
660 | * | |
661 | * or perhaps like this: | |
662 | * | |
663 | * |\|\ |\|\ | |
664 | * __----__----__ (- plane active, _ blanking) | |
665 | * -> time | |
666 | * | |
667 | * Returns: | |
668 | * The watermark in bytes | |
669 | */ | |
670 | static unsigned int intel_wm_method1(unsigned int pixel_rate, | |
671 | unsigned int cpp, | |
672 | unsigned int latency) | |
673 | { | |
674 | uint64_t ret; | |
675 | ||
676 | ret = (uint64_t) pixel_rate * cpp * latency; | |
677 | ret = DIV_ROUND_UP_ULL(ret, 10000); | |
678 | ||
679 | return ret; | |
680 | } | |
681 | ||
682 | /** | |
683 | * intel_wm_method2 - Method 2 / "large buffer" watermark formula | |
684 | * @pixel_rate: Pipe pixel rate in kHz | |
685 | * @htotal: Pipe horizontal total | |
686 | * @width: Plane width in pixels | |
687 | * @cpp: Plane bytes per pixel | |
688 | * @latency: Memory wakeup latency in 0.1us units | |
689 | * | |
690 | * Compute the watermark using the method 2 or "large buffer" | |
691 | * formula. The caller may additonally add extra cachelines | |
692 | * to account for TLB misses and clock crossings. | |
693 | * | |
694 | * This method is concerned with the long term drain rate | |
695 | * of the FIFO, ie. it does account for blanking periods | |
696 | * which effectively reduce the average drain rate across | |
697 | * a longer period. The name "large" refers to the fact the | |
698 | * FIFO is relatively large compared to the amount of data | |
699 | * fetched. | |
700 | * | |
701 | * The FIFO level vs. time graph might look something like: | |
702 | * | |
703 | * |\___ |\___ | |
704 | * | \___ | \___ | |
705 | * | \ | \ | |
706 | * __ --__--__--__--__--__--__ (- plane active, _ blanking) | |
707 | * -> time | |
708 | * | |
709 | * Returns: | |
710 | * The watermark in bytes | |
711 | */ | |
712 | static unsigned int intel_wm_method2(unsigned int pixel_rate, | |
713 | unsigned int htotal, | |
714 | unsigned int width, | |
715 | unsigned int cpp, | |
716 | unsigned int latency) | |
717 | { | |
718 | unsigned int ret; | |
719 | ||
720 | /* | |
721 | * FIXME remove once all users are computing | |
722 | * watermarks in the correct place. | |
723 | */ | |
724 | if (WARN_ON_ONCE(htotal == 0)) | |
725 | htotal = 1; | |
726 | ||
727 | ret = (latency * pixel_rate) / (htotal * 10000); | |
728 | ret = (ret + 1) * width * cpp; | |
729 | ||
730 | return ret; | |
731 | } | |
732 | ||
b445e3b0 ED |
733 | /** |
734 | * intel_calculate_wm - calculate watermark level | |
baf69ca8 | 735 | * @pixel_rate: pixel clock |
b445e3b0 | 736 | * @wm: chip FIFO params |
ac484963 | 737 | * @cpp: bytes per pixel |
b445e3b0 ED |
738 | * @latency_ns: memory latency for the platform |
739 | * | |
740 | * Calculate the watermark level (the level at which the display plane will | |
741 | * start fetching from memory again). Each chip has a different display | |
742 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
743 | * in the correct intel_watermark_params structure. | |
744 | * | |
745 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
746 | * on the pixel size. When it reaches the watermark level, it'll start | |
747 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
748 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
749 | * will occur, and a display engine hang could result. | |
750 | */ | |
baf69ca8 VS |
751 | static unsigned int intel_calculate_wm(int pixel_rate, |
752 | const struct intel_watermark_params *wm, | |
753 | int fifo_size, int cpp, | |
754 | unsigned int latency_ns) | |
b445e3b0 | 755 | { |
baf69ca8 | 756 | int entries, wm_size; |
b445e3b0 ED |
757 | |
758 | /* | |
759 | * Note: we need to make sure we don't overflow for various clock & | |
760 | * latency values. | |
761 | * clocks go from a few thousand to several hundred thousand. | |
762 | * latency is usually a few thousand | |
763 | */ | |
baf69ca8 VS |
764 | entries = intel_wm_method1(pixel_rate, cpp, |
765 | latency_ns / 100); | |
766 | entries = DIV_ROUND_UP(entries, wm->cacheline_size) + | |
767 | wm->guard_size; | |
768 | DRM_DEBUG_KMS("FIFO entries required for mode: %d\n", entries); | |
b445e3b0 | 769 | |
baf69ca8 VS |
770 | wm_size = fifo_size - entries; |
771 | DRM_DEBUG_KMS("FIFO watermark level: %d\n", wm_size); | |
b445e3b0 ED |
772 | |
773 | /* Don't promote wm_size to unsigned... */ | |
baf69ca8 | 774 | if (wm_size > wm->max_wm) |
b445e3b0 ED |
775 | wm_size = wm->max_wm; |
776 | if (wm_size <= 0) | |
777 | wm_size = wm->default_wm; | |
d6feb196 VS |
778 | |
779 | /* | |
780 | * Bspec seems to indicate that the value shouldn't be lower than | |
781 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
782 | * Lets go for 8 which is the burst size since certain platforms | |
783 | * already use a hardcoded 8 (which is what the spec says should be | |
784 | * done). | |
785 | */ | |
786 | if (wm_size <= 8) | |
787 | wm_size = 8; | |
788 | ||
b445e3b0 ED |
789 | return wm_size; |
790 | } | |
791 | ||
04548cba VS |
792 | static bool is_disabling(int old, int new, int threshold) |
793 | { | |
794 | return old >= threshold && new < threshold; | |
795 | } | |
796 | ||
797 | static bool is_enabling(int old, int new, int threshold) | |
798 | { | |
799 | return old < threshold && new >= threshold; | |
800 | } | |
801 | ||
6d5019b6 VS |
802 | static int intel_wm_num_levels(struct drm_i915_private *dev_priv) |
803 | { | |
804 | return dev_priv->wm.max_level + 1; | |
805 | } | |
806 | ||
24304d81 VS |
807 | static bool intel_wm_plane_visible(const struct intel_crtc_state *crtc_state, |
808 | const struct intel_plane_state *plane_state) | |
809 | { | |
810 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
811 | ||
812 | /* FIXME check the 'enable' instead */ | |
813 | if (!crtc_state->base.active) | |
814 | return false; | |
815 | ||
816 | /* | |
817 | * Treat cursor with fb as always visible since cursor updates | |
818 | * can happen faster than the vrefresh rate, and the current | |
819 | * watermark code doesn't handle that correctly. Cursor updates | |
820 | * which set/clear the fb or change the cursor size are going | |
821 | * to get throttled by intel_legacy_cursor_update() to work | |
822 | * around this problem with the watermark code. | |
823 | */ | |
824 | if (plane->id == PLANE_CURSOR) | |
825 | return plane_state->base.fb != NULL; | |
826 | else | |
827 | return plane_state->base.visible; | |
828 | } | |
829 | ||
ffc7a76b | 830 | static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv) |
b445e3b0 | 831 | { |
efc2611e | 832 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 833 | |
ffc7a76b | 834 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
efc2611e | 835 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
836 | if (enabled) |
837 | return NULL; | |
838 | enabled = crtc; | |
839 | } | |
840 | } | |
841 | ||
842 | return enabled; | |
843 | } | |
844 | ||
432081bc | 845 | static void pineview_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 846 | { |
ffc7a76b | 847 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 848 | struct intel_crtc *crtc; |
b445e3b0 ED |
849 | const struct cxsr_latency *latency; |
850 | u32 reg; | |
baf69ca8 | 851 | unsigned int wm; |
b445e3b0 | 852 | |
50a0bc90 TU |
853 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
854 | dev_priv->is_ddr3, | |
855 | dev_priv->fsb_freq, | |
856 | dev_priv->mem_freq); | |
b445e3b0 ED |
857 | if (!latency) { |
858 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 859 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
860 | return; |
861 | } | |
862 | ||
ffc7a76b | 863 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 | 864 | if (crtc) { |
efc2611e VS |
865 | const struct drm_display_mode *adjusted_mode = |
866 | &crtc->config->base.adjusted_mode; | |
867 | const struct drm_framebuffer *fb = | |
868 | crtc->base.primary->state->fb; | |
353c8598 | 869 | int cpp = fb->format->cpp[0]; |
7c5f93b0 | 870 | int clock = adjusted_mode->crtc_clock; |
b445e3b0 ED |
871 | |
872 | /* Display SR */ | |
873 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
874 | pineview_display_wm.fifo_size, | |
ac484963 | 875 | cpp, latency->display_sr); |
b445e3b0 ED |
876 | reg = I915_READ(DSPFW1); |
877 | reg &= ~DSPFW_SR_MASK; | |
f4998963 | 878 | reg |= FW_WM(wm, SR); |
b445e3b0 ED |
879 | I915_WRITE(DSPFW1, reg); |
880 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
881 | ||
882 | /* cursor SR */ | |
883 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
884 | pineview_display_wm.fifo_size, | |
99834b14 | 885 | 4, latency->cursor_sr); |
b445e3b0 ED |
886 | reg = I915_READ(DSPFW3); |
887 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
f4998963 | 888 | reg |= FW_WM(wm, CURSOR_SR); |
b445e3b0 ED |
889 | I915_WRITE(DSPFW3, reg); |
890 | ||
891 | /* Display HPLL off SR */ | |
892 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
893 | pineview_display_hplloff_wm.fifo_size, | |
ac484963 | 894 | cpp, latency->display_hpll_disable); |
b445e3b0 ED |
895 | reg = I915_READ(DSPFW3); |
896 | reg &= ~DSPFW_HPLL_SR_MASK; | |
f4998963 | 897 | reg |= FW_WM(wm, HPLL_SR); |
b445e3b0 ED |
898 | I915_WRITE(DSPFW3, reg); |
899 | ||
900 | /* cursor HPLL off SR */ | |
901 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
902 | pineview_display_hplloff_wm.fifo_size, | |
99834b14 | 903 | 4, latency->cursor_hpll_disable); |
b445e3b0 ED |
904 | reg = I915_READ(DSPFW3); |
905 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
f4998963 | 906 | reg |= FW_WM(wm, HPLL_CURSOR); |
b445e3b0 ED |
907 | I915_WRITE(DSPFW3, reg); |
908 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
909 | ||
5209b1f4 | 910 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 911 | } else { |
5209b1f4 | 912 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
913 | } |
914 | } | |
915 | ||
0f95ff85 VS |
916 | /* |
917 | * Documentation says: | |
918 | * "If the line size is small, the TLB fetches can get in the way of the | |
919 | * data fetches, causing some lag in the pixel data return which is not | |
920 | * accounted for in the above formulas. The following adjustment only | |
921 | * needs to be applied if eight whole lines fit in the buffer at once. | |
922 | * The WM is adjusted upwards by the difference between the FIFO size | |
923 | * and the size of 8 whole lines. This adjustment is always performed | |
924 | * in the actual pixel depth regardless of whether FBC is enabled or not." | |
925 | */ | |
926 | static int g4x_tlb_miss_wa(int fifo_size, int width, int cpp) | |
927 | { | |
928 | int tlb_miss = fifo_size * 64 - width * cpp * 8; | |
929 | ||
930 | return max(0, tlb_miss); | |
931 | } | |
932 | ||
04548cba VS |
933 | static void g4x_write_wm_values(struct drm_i915_private *dev_priv, |
934 | const struct g4x_wm_values *wm) | |
b445e3b0 | 935 | { |
e93329a5 VS |
936 | enum pipe pipe; |
937 | ||
938 | for_each_pipe(dev_priv, pipe) | |
939 | trace_g4x_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); | |
940 | ||
04548cba VS |
941 | I915_WRITE(DSPFW1, |
942 | FW_WM(wm->sr.plane, SR) | | |
943 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | | |
944 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
945 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
946 | I915_WRITE(DSPFW2, | |
947 | (wm->fbc_en ? DSPFW_FBC_SR_EN : 0) | | |
948 | FW_WM(wm->sr.fbc, FBC_SR) | | |
949 | FW_WM(wm->hpll.fbc, FBC_HPLL_SR) | | |
950 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEB) | | |
951 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
952 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
953 | I915_WRITE(DSPFW3, | |
954 | (wm->hpll_en ? DSPFW_HPLL_SR_EN : 0) | | |
955 | FW_WM(wm->sr.cursor, CURSOR_SR) | | |
956 | FW_WM(wm->hpll.cursor, HPLL_CURSOR) | | |
957 | FW_WM(wm->hpll.plane, HPLL_SR)); | |
b445e3b0 | 958 | |
04548cba | 959 | POSTING_READ(DSPFW1); |
b445e3b0 ED |
960 | } |
961 | ||
15665979 VS |
962 | #define FW_WM_VLV(value, plane) \ |
963 | (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV) | |
964 | ||
50f4caef | 965 | static void vlv_write_wm_values(struct drm_i915_private *dev_priv, |
0018fda1 VS |
966 | const struct vlv_wm_values *wm) |
967 | { | |
50f4caef VS |
968 | enum pipe pipe; |
969 | ||
970 | for_each_pipe(dev_priv, pipe) { | |
c137d660 VS |
971 | trace_vlv_wm(intel_get_crtc_for_pipe(dev_priv, pipe), wm); |
972 | ||
50f4caef VS |
973 | I915_WRITE(VLV_DDL(pipe), |
974 | (wm->ddl[pipe].plane[PLANE_CURSOR] << DDL_CURSOR_SHIFT) | | |
975 | (wm->ddl[pipe].plane[PLANE_SPRITE1] << DDL_SPRITE_SHIFT(1)) | | |
976 | (wm->ddl[pipe].plane[PLANE_SPRITE0] << DDL_SPRITE_SHIFT(0)) | | |
977 | (wm->ddl[pipe].plane[PLANE_PRIMARY] << DDL_PLANE_SHIFT)); | |
978 | } | |
0018fda1 | 979 | |
6fe6a7ff VS |
980 | /* |
981 | * Zero the (unused) WM1 watermarks, and also clear all the | |
982 | * high order bits so that there are no out of bounds values | |
983 | * present in the registers during the reprogramming. | |
984 | */ | |
985 | I915_WRITE(DSPHOWM, 0); | |
986 | I915_WRITE(DSPHOWM1, 0); | |
987 | I915_WRITE(DSPFW4, 0); | |
988 | I915_WRITE(DSPFW5, 0); | |
989 | I915_WRITE(DSPFW6, 0); | |
990 | ||
ae80152d | 991 | I915_WRITE(DSPFW1, |
15665979 | 992 | FW_WM(wm->sr.plane, SR) | |
1b31389c VS |
993 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_CURSOR], CURSORB) | |
994 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_PRIMARY], PLANEB) | | |
995 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_PRIMARY], PLANEA)); | |
ae80152d | 996 | I915_WRITE(DSPFW2, |
1b31389c VS |
997 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE1], SPRITEB) | |
998 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_CURSOR], CURSORA) | | |
999 | FW_WM_VLV(wm->pipe[PIPE_A].plane[PLANE_SPRITE0], SPRITEA)); | |
ae80152d | 1000 | I915_WRITE(DSPFW3, |
15665979 | 1001 | FW_WM(wm->sr.cursor, CURSOR_SR)); |
ae80152d VS |
1002 | |
1003 | if (IS_CHERRYVIEW(dev_priv)) { | |
1004 | I915_WRITE(DSPFW7_CHV, | |
1b31389c VS |
1005 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
1006 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 1007 | I915_WRITE(DSPFW8_CHV, |
1b31389c VS |
1008 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE1], SPRITEF) | |
1009 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_SPRITE0], SPRITEE)); | |
ae80152d | 1010 | I915_WRITE(DSPFW9_CHV, |
1b31389c VS |
1011 | FW_WM_VLV(wm->pipe[PIPE_C].plane[PLANE_PRIMARY], PLANEC) | |
1012 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_CURSOR], CURSORC)); | |
ae80152d | 1013 | I915_WRITE(DSPHOWM, |
15665979 | 1014 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
1015 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE1] >> 8, SPRITEF_HI) | |
1016 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_SPRITE0] >> 8, SPRITEE_HI) | | |
1017 | FW_WM(wm->pipe[PIPE_C].plane[PLANE_PRIMARY] >> 8, PLANEC_HI) | | |
1018 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | | |
1019 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
1020 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
1021 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
1022 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
1023 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
1024 | } else { |
1025 | I915_WRITE(DSPFW7, | |
1b31389c VS |
1026 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE1], SPRITED) | |
1027 | FW_WM_VLV(wm->pipe[PIPE_B].plane[PLANE_SPRITE0], SPRITEC)); | |
ae80152d | 1028 | I915_WRITE(DSPHOWM, |
15665979 | 1029 | FW_WM(wm->sr.plane >> 9, SR_HI) | |
1b31389c VS |
1030 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE1] >> 8, SPRITED_HI) | |
1031 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_SPRITE0] >> 8, SPRITEC_HI) | | |
1032 | FW_WM(wm->pipe[PIPE_B].plane[PLANE_PRIMARY] >> 8, PLANEB_HI) | | |
1033 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE1] >> 8, SPRITEB_HI) | | |
1034 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_SPRITE0] >> 8, SPRITEA_HI) | | |
1035 | FW_WM(wm->pipe[PIPE_A].plane[PLANE_PRIMARY] >> 8, PLANEA_HI)); | |
ae80152d VS |
1036 | } |
1037 | ||
1038 | POSTING_READ(DSPFW1); | |
0018fda1 VS |
1039 | } |
1040 | ||
15665979 VS |
1041 | #undef FW_WM_VLV |
1042 | ||
04548cba VS |
1043 | static void g4x_setup_wm_latency(struct drm_i915_private *dev_priv) |
1044 | { | |
1045 | /* all latencies in usec */ | |
1046 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_NORMAL] = 5; | |
1047 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_SR] = 12; | |
79d94306 | 1048 | dev_priv->wm.pri_latency[G4X_WM_LEVEL_HPLL] = 35; |
04548cba | 1049 | |
79d94306 | 1050 | dev_priv->wm.max_level = G4X_WM_LEVEL_HPLL; |
04548cba VS |
1051 | } |
1052 | ||
1053 | static int g4x_plane_fifo_size(enum plane_id plane_id, int level) | |
1054 | { | |
1055 | /* | |
1056 | * DSPCNTR[13] supposedly controls whether the | |
1057 | * primary plane can use the FIFO space otherwise | |
1058 | * reserved for the sprite plane. It's not 100% clear | |
1059 | * what the actual FIFO size is, but it looks like we | |
1060 | * can happily set both primary and sprite watermarks | |
1061 | * up to 127 cachelines. So that would seem to mean | |
1062 | * that either DSPCNTR[13] doesn't do anything, or that | |
1063 | * the total FIFO is >= 256 cachelines in size. Either | |
1064 | * way, we don't seem to have to worry about this | |
1065 | * repartitioning as the maximum watermark value the | |
1066 | * register can hold for each plane is lower than the | |
1067 | * minimum FIFO size. | |
1068 | */ | |
1069 | switch (plane_id) { | |
1070 | case PLANE_CURSOR: | |
1071 | return 63; | |
1072 | case PLANE_PRIMARY: | |
1073 | return level == G4X_WM_LEVEL_NORMAL ? 127 : 511; | |
1074 | case PLANE_SPRITE0: | |
1075 | return level == G4X_WM_LEVEL_NORMAL ? 127 : 0; | |
1076 | default: | |
1077 | MISSING_CASE(plane_id); | |
1078 | return 0; | |
1079 | } | |
1080 | } | |
1081 | ||
1082 | static int g4x_fbc_fifo_size(int level) | |
1083 | { | |
1084 | switch (level) { | |
1085 | case G4X_WM_LEVEL_SR: | |
1086 | return 7; | |
1087 | case G4X_WM_LEVEL_HPLL: | |
1088 | return 15; | |
1089 | default: | |
1090 | MISSING_CASE(level); | |
1091 | return 0; | |
1092 | } | |
1093 | } | |
1094 | ||
1095 | static uint16_t g4x_compute_wm(const struct intel_crtc_state *crtc_state, | |
1096 | const struct intel_plane_state *plane_state, | |
1097 | int level) | |
1098 | { | |
1099 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
1100 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); | |
1101 | const struct drm_display_mode *adjusted_mode = | |
1102 | &crtc_state->base.adjusted_mode; | |
1103 | int clock, htotal, cpp, width, wm; | |
1104 | int latency = dev_priv->wm.pri_latency[level] * 10; | |
1105 | ||
1106 | if (latency == 0) | |
1107 | return USHRT_MAX; | |
1108 | ||
1109 | if (!intel_wm_plane_visible(crtc_state, plane_state)) | |
1110 | return 0; | |
1111 | ||
1112 | /* | |
1113 | * Not 100% sure which way ELK should go here as the | |
1114 | * spec only says CL/CTG should assume 32bpp and BW | |
1115 | * doesn't need to. But as these things followed the | |
1116 | * mobile vs. desktop lines on gen3 as well, let's | |
1117 | * assume ELK doesn't need this. | |
1118 | * | |
1119 | * The spec also fails to list such a restriction for | |
1120 | * the HPLL watermark, which seems a little strange. | |
1121 | * Let's use 32bpp for the HPLL watermark as well. | |
1122 | */ | |
1123 | if (IS_GM45(dev_priv) && plane->id == PLANE_PRIMARY && | |
1124 | level != G4X_WM_LEVEL_NORMAL) | |
1125 | cpp = 4; | |
1126 | else | |
1127 | cpp = plane_state->base.fb->format->cpp[0]; | |
1128 | ||
1129 | clock = adjusted_mode->crtc_clock; | |
1130 | htotal = adjusted_mode->crtc_htotal; | |
1131 | ||
1132 | if (plane->id == PLANE_CURSOR) | |
1133 | width = plane_state->base.crtc_w; | |
1134 | else | |
1135 | width = drm_rect_width(&plane_state->base.dst); | |
1136 | ||
1137 | if (plane->id == PLANE_CURSOR) { | |
1138 | wm = intel_wm_method2(clock, htotal, width, cpp, latency); | |
1139 | } else if (plane->id == PLANE_PRIMARY && | |
1140 | level == G4X_WM_LEVEL_NORMAL) { | |
1141 | wm = intel_wm_method1(clock, cpp, latency); | |
1142 | } else { | |
1143 | int small, large; | |
1144 | ||
1145 | small = intel_wm_method1(clock, cpp, latency); | |
1146 | large = intel_wm_method2(clock, htotal, width, cpp, latency); | |
1147 | ||
1148 | wm = min(small, large); | |
1149 | } | |
1150 | ||
1151 | wm += g4x_tlb_miss_wa(g4x_plane_fifo_size(plane->id, level), | |
1152 | width, cpp); | |
1153 | ||
1154 | wm = DIV_ROUND_UP(wm, 64) + 2; | |
1155 | ||
1156 | return min_t(int, wm, USHRT_MAX); | |
1157 | } | |
1158 | ||
1159 | static bool g4x_raw_plane_wm_set(struct intel_crtc_state *crtc_state, | |
1160 | int level, enum plane_id plane_id, u16 value) | |
1161 | { | |
1162 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1163 | bool dirty = false; | |
1164 | ||
1165 | for (; level < intel_wm_num_levels(dev_priv); level++) { | |
1166 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1167 | ||
1168 | dirty |= raw->plane[plane_id] != value; | |
1169 | raw->plane[plane_id] = value; | |
1170 | } | |
1171 | ||
1172 | return dirty; | |
1173 | } | |
1174 | ||
1175 | static bool g4x_raw_fbc_wm_set(struct intel_crtc_state *crtc_state, | |
1176 | int level, u16 value) | |
1177 | { | |
1178 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1179 | bool dirty = false; | |
1180 | ||
1181 | /* NORMAL level doesn't have an FBC watermark */ | |
1182 | level = max(level, G4X_WM_LEVEL_SR); | |
1183 | ||
1184 | for (; level < intel_wm_num_levels(dev_priv); level++) { | |
1185 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1186 | ||
1187 | dirty |= raw->fbc != value; | |
1188 | raw->fbc = value; | |
1189 | } | |
1190 | ||
1191 | return dirty; | |
1192 | } | |
1193 | ||
1194 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, | |
1195 | const struct intel_plane_state *pstate, | |
1196 | uint32_t pri_val); | |
1197 | ||
1198 | static bool g4x_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, | |
1199 | const struct intel_plane_state *plane_state) | |
1200 | { | |
1201 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); | |
1202 | int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); | |
1203 | enum plane_id plane_id = plane->id; | |
1204 | bool dirty = false; | |
1205 | int level; | |
1206 | ||
1207 | if (!intel_wm_plane_visible(crtc_state, plane_state)) { | |
1208 | dirty |= g4x_raw_plane_wm_set(crtc_state, 0, plane_id, 0); | |
1209 | if (plane_id == PLANE_PRIMARY) | |
1210 | dirty |= g4x_raw_fbc_wm_set(crtc_state, 0, 0); | |
1211 | goto out; | |
1212 | } | |
1213 | ||
1214 | for (level = 0; level < num_levels; level++) { | |
1215 | struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1216 | int wm, max_wm; | |
1217 | ||
1218 | wm = g4x_compute_wm(crtc_state, plane_state, level); | |
1219 | max_wm = g4x_plane_fifo_size(plane_id, level); | |
1220 | ||
1221 | if (wm > max_wm) | |
1222 | break; | |
1223 | ||
1224 | dirty |= raw->plane[plane_id] != wm; | |
1225 | raw->plane[plane_id] = wm; | |
1226 | ||
1227 | if (plane_id != PLANE_PRIMARY || | |
1228 | level == G4X_WM_LEVEL_NORMAL) | |
1229 | continue; | |
1230 | ||
1231 | wm = ilk_compute_fbc_wm(crtc_state, plane_state, | |
1232 | raw->plane[plane_id]); | |
1233 | max_wm = g4x_fbc_fifo_size(level); | |
1234 | ||
1235 | /* | |
1236 | * FBC wm is not mandatory as we | |
1237 | * can always just disable its use. | |
1238 | */ | |
1239 | if (wm > max_wm) | |
1240 | wm = USHRT_MAX; | |
1241 | ||
1242 | dirty |= raw->fbc != wm; | |
1243 | raw->fbc = wm; | |
1244 | } | |
1245 | ||
1246 | /* mark watermarks as invalid */ | |
1247 | dirty |= g4x_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); | |
1248 | ||
1249 | if (plane_id == PLANE_PRIMARY) | |
1250 | dirty |= g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); | |
1251 | ||
1252 | out: | |
1253 | if (dirty) { | |
1254 | DRM_DEBUG_KMS("%s watermarks: normal=%d, SR=%d, HPLL=%d\n", | |
1255 | plane->base.name, | |
1256 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_NORMAL].plane[plane_id], | |
1257 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].plane[plane_id], | |
1258 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].plane[plane_id]); | |
1259 | ||
1260 | if (plane_id == PLANE_PRIMARY) | |
1261 | DRM_DEBUG_KMS("FBC watermarks: SR=%d, HPLL=%d\n", | |
1262 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_SR].fbc, | |
1263 | crtc_state->wm.g4x.raw[G4X_WM_LEVEL_HPLL].fbc); | |
1264 | } | |
1265 | ||
1266 | return dirty; | |
1267 | } | |
1268 | ||
1269 | static bool g4x_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, | |
1270 | enum plane_id plane_id, int level) | |
1271 | { | |
1272 | const struct g4x_pipe_wm *raw = &crtc_state->wm.g4x.raw[level]; | |
1273 | ||
1274 | return raw->plane[plane_id] <= g4x_plane_fifo_size(plane_id, level); | |
1275 | } | |
1276 | ||
1277 | static bool g4x_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, | |
1278 | int level) | |
1279 | { | |
1280 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1281 | ||
1282 | if (level > dev_priv->wm.max_level) | |
1283 | return false; | |
1284 | ||
1285 | return g4x_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && | |
1286 | g4x_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1287 | g4x_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
1288 | } | |
1289 | ||
1290 | /* mark all levels starting from 'level' as invalid */ | |
1291 | static void g4x_invalidate_wms(struct intel_crtc *crtc, | |
1292 | struct g4x_wm_state *wm_state, int level) | |
1293 | { | |
1294 | if (level <= G4X_WM_LEVEL_NORMAL) { | |
1295 | enum plane_id plane_id; | |
1296 | ||
1297 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1298 | wm_state->wm.plane[plane_id] = USHRT_MAX; | |
1299 | } | |
1300 | ||
1301 | if (level <= G4X_WM_LEVEL_SR) { | |
1302 | wm_state->cxsr = false; | |
1303 | wm_state->sr.cursor = USHRT_MAX; | |
1304 | wm_state->sr.plane = USHRT_MAX; | |
1305 | wm_state->sr.fbc = USHRT_MAX; | |
1306 | } | |
1307 | ||
1308 | if (level <= G4X_WM_LEVEL_HPLL) { | |
1309 | wm_state->hpll_en = false; | |
1310 | wm_state->hpll.cursor = USHRT_MAX; | |
1311 | wm_state->hpll.plane = USHRT_MAX; | |
1312 | wm_state->hpll.fbc = USHRT_MAX; | |
1313 | } | |
1314 | } | |
1315 | ||
1316 | static int g4x_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1317 | { | |
1318 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1319 | struct intel_atomic_state *state = | |
1320 | to_intel_atomic_state(crtc_state->base.state); | |
1321 | struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; | |
1322 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1323 | ~BIT(PLANE_CURSOR)); | |
1324 | const struct g4x_pipe_wm *raw; | |
1325 | struct intel_plane_state *plane_state; | |
1326 | struct intel_plane *plane; | |
1327 | enum plane_id plane_id; | |
1328 | int i, level; | |
1329 | unsigned int dirty = 0; | |
1330 | ||
1331 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1332 | const struct intel_plane_state *old_plane_state = | |
1333 | to_intel_plane_state(plane->base.state); | |
1334 | ||
1335 | if (plane_state->base.crtc != &crtc->base && | |
1336 | old_plane_state->base.crtc != &crtc->base) | |
1337 | continue; | |
1338 | ||
1339 | if (g4x_raw_plane_wm_compute(crtc_state, plane_state)) | |
1340 | dirty |= BIT(plane->id); | |
1341 | } | |
1342 | ||
1343 | if (!dirty) | |
1344 | return 0; | |
1345 | ||
1346 | level = G4X_WM_LEVEL_NORMAL; | |
1347 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1348 | goto out; | |
1349 | ||
1350 | raw = &crtc_state->wm.g4x.raw[level]; | |
1351 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1352 | wm_state->wm.plane[plane_id] = raw->plane[plane_id]; | |
1353 | ||
1354 | level = G4X_WM_LEVEL_SR; | |
1355 | ||
1356 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1357 | goto out; | |
1358 | ||
1359 | raw = &crtc_state->wm.g4x.raw[level]; | |
1360 | wm_state->sr.plane = raw->plane[PLANE_PRIMARY]; | |
1361 | wm_state->sr.cursor = raw->plane[PLANE_CURSOR]; | |
1362 | wm_state->sr.fbc = raw->fbc; | |
1363 | ||
1364 | wm_state->cxsr = num_active_planes == BIT(PLANE_PRIMARY); | |
1365 | ||
1366 | level = G4X_WM_LEVEL_HPLL; | |
1367 | ||
1368 | if (!g4x_raw_crtc_wm_is_valid(crtc_state, level)) | |
1369 | goto out; | |
1370 | ||
1371 | raw = &crtc_state->wm.g4x.raw[level]; | |
1372 | wm_state->hpll.plane = raw->plane[PLANE_PRIMARY]; | |
1373 | wm_state->hpll.cursor = raw->plane[PLANE_CURSOR]; | |
1374 | wm_state->hpll.fbc = raw->fbc; | |
1375 | ||
1376 | wm_state->hpll_en = wm_state->cxsr; | |
1377 | ||
1378 | level++; | |
1379 | ||
1380 | out: | |
1381 | if (level == G4X_WM_LEVEL_NORMAL) | |
1382 | return -EINVAL; | |
1383 | ||
1384 | /* invalidate the higher levels */ | |
1385 | g4x_invalidate_wms(crtc, wm_state, level); | |
1386 | ||
1387 | /* | |
1388 | * Determine if the FBC watermark(s) can be used. IF | |
1389 | * this isn't the case we prefer to disable the FBC | |
1390 | ( watermark(s) rather than disable the SR/HPLL | |
1391 | * level(s) entirely. | |
1392 | */ | |
1393 | wm_state->fbc_en = level > G4X_WM_LEVEL_NORMAL; | |
1394 | ||
1395 | if (level >= G4X_WM_LEVEL_SR && | |
1396 | wm_state->sr.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_SR)) | |
1397 | wm_state->fbc_en = false; | |
1398 | else if (level >= G4X_WM_LEVEL_HPLL && | |
1399 | wm_state->hpll.fbc > g4x_fbc_fifo_size(G4X_WM_LEVEL_HPLL)) | |
1400 | wm_state->fbc_en = false; | |
1401 | ||
1402 | return 0; | |
1403 | } | |
1404 | ||
1405 | static int g4x_compute_intermediate_wm(struct drm_device *dev, | |
1406 | struct intel_crtc *crtc, | |
1407 | struct intel_crtc_state *crtc_state) | |
1408 | { | |
1409 | struct g4x_wm_state *intermediate = &crtc_state->wm.g4x.intermediate; | |
1410 | const struct g4x_wm_state *optimal = &crtc_state->wm.g4x.optimal; | |
1411 | const struct g4x_wm_state *active = &crtc->wm.active.g4x; | |
1412 | enum plane_id plane_id; | |
1413 | ||
1414 | intermediate->cxsr = optimal->cxsr && active->cxsr && | |
1415 | !crtc_state->disable_cxsr; | |
1416 | intermediate->hpll_en = optimal->hpll_en && active->hpll_en && | |
1417 | !crtc_state->disable_cxsr; | |
1418 | intermediate->fbc_en = optimal->fbc_en && active->fbc_en; | |
1419 | ||
1420 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
1421 | intermediate->wm.plane[plane_id] = | |
1422 | max(optimal->wm.plane[plane_id], | |
1423 | active->wm.plane[plane_id]); | |
1424 | ||
1425 | WARN_ON(intermediate->wm.plane[plane_id] > | |
1426 | g4x_plane_fifo_size(plane_id, G4X_WM_LEVEL_NORMAL)); | |
1427 | } | |
1428 | ||
1429 | intermediate->sr.plane = max(optimal->sr.plane, | |
1430 | active->sr.plane); | |
1431 | intermediate->sr.cursor = max(optimal->sr.cursor, | |
1432 | active->sr.cursor); | |
1433 | intermediate->sr.fbc = max(optimal->sr.fbc, | |
1434 | active->sr.fbc); | |
1435 | ||
1436 | intermediate->hpll.plane = max(optimal->hpll.plane, | |
1437 | active->hpll.plane); | |
1438 | intermediate->hpll.cursor = max(optimal->hpll.cursor, | |
1439 | active->hpll.cursor); | |
1440 | intermediate->hpll.fbc = max(optimal->hpll.fbc, | |
1441 | active->hpll.fbc); | |
1442 | ||
1443 | WARN_ON((intermediate->sr.plane > | |
1444 | g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_SR) || | |
1445 | intermediate->sr.cursor > | |
1446 | g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_SR)) && | |
1447 | intermediate->cxsr); | |
1448 | WARN_ON((intermediate->sr.plane > | |
1449 | g4x_plane_fifo_size(PLANE_PRIMARY, G4X_WM_LEVEL_HPLL) || | |
1450 | intermediate->sr.cursor > | |
1451 | g4x_plane_fifo_size(PLANE_CURSOR, G4X_WM_LEVEL_HPLL)) && | |
1452 | intermediate->hpll_en); | |
1453 | ||
1454 | WARN_ON(intermediate->sr.fbc > g4x_fbc_fifo_size(1) && | |
1455 | intermediate->fbc_en && intermediate->cxsr); | |
1456 | WARN_ON(intermediate->hpll.fbc > g4x_fbc_fifo_size(2) && | |
1457 | intermediate->fbc_en && intermediate->hpll_en); | |
1458 | ||
1459 | /* | |
1460 | * If our intermediate WM are identical to the final WM, then we can | |
1461 | * omit the post-vblank programming; only update if it's different. | |
1462 | */ | |
1463 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) | |
1464 | crtc_state->wm.need_postvbl_update = true; | |
1465 | ||
1466 | return 0; | |
1467 | } | |
1468 | ||
1469 | static void g4x_merge_wm(struct drm_i915_private *dev_priv, | |
1470 | struct g4x_wm_values *wm) | |
1471 | { | |
1472 | struct intel_crtc *crtc; | |
1473 | int num_active_crtcs = 0; | |
1474 | ||
1475 | wm->cxsr = true; | |
1476 | wm->hpll_en = true; | |
1477 | wm->fbc_en = true; | |
1478 | ||
1479 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
1480 | const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; | |
1481 | ||
1482 | if (!crtc->active) | |
1483 | continue; | |
1484 | ||
1485 | if (!wm_state->cxsr) | |
1486 | wm->cxsr = false; | |
1487 | if (!wm_state->hpll_en) | |
1488 | wm->hpll_en = false; | |
1489 | if (!wm_state->fbc_en) | |
1490 | wm->fbc_en = false; | |
1491 | ||
1492 | num_active_crtcs++; | |
1493 | } | |
1494 | ||
1495 | if (num_active_crtcs != 1) { | |
1496 | wm->cxsr = false; | |
1497 | wm->hpll_en = false; | |
1498 | wm->fbc_en = false; | |
1499 | } | |
1500 | ||
1501 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
1502 | const struct g4x_wm_state *wm_state = &crtc->wm.active.g4x; | |
1503 | enum pipe pipe = crtc->pipe; | |
1504 | ||
1505 | wm->pipe[pipe] = wm_state->wm; | |
1506 | if (crtc->active && wm->cxsr) | |
1507 | wm->sr = wm_state->sr; | |
1508 | if (crtc->active && wm->hpll_en) | |
1509 | wm->hpll = wm_state->hpll; | |
1510 | } | |
1511 | } | |
1512 | ||
1513 | static void g4x_program_watermarks(struct drm_i915_private *dev_priv) | |
1514 | { | |
1515 | struct g4x_wm_values *old_wm = &dev_priv->wm.g4x; | |
1516 | struct g4x_wm_values new_wm = {}; | |
1517 | ||
1518 | g4x_merge_wm(dev_priv, &new_wm); | |
1519 | ||
1520 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) | |
1521 | return; | |
1522 | ||
1523 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) | |
1524 | _intel_set_memory_cxsr(dev_priv, false); | |
1525 | ||
1526 | g4x_write_wm_values(dev_priv, &new_wm); | |
1527 | ||
1528 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) | |
1529 | _intel_set_memory_cxsr(dev_priv, true); | |
1530 | ||
1531 | *old_wm = new_wm; | |
1532 | } | |
1533 | ||
1534 | static void g4x_initial_watermarks(struct intel_atomic_state *state, | |
1535 | struct intel_crtc_state *crtc_state) | |
1536 | { | |
1537 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1538 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1539 | ||
1540 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1541 | crtc->wm.active.g4x = crtc_state->wm.g4x.intermediate; | |
1542 | g4x_program_watermarks(dev_priv); | |
1543 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1544 | } | |
1545 | ||
1546 | static void g4x_optimize_watermarks(struct intel_atomic_state *state, | |
1547 | struct intel_crtc_state *crtc_state) | |
1548 | { | |
1549 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
1550 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
1551 | ||
1552 | if (!crtc_state->wm.need_postvbl_update) | |
1553 | return; | |
1554 | ||
1555 | mutex_lock(&dev_priv->wm.wm_mutex); | |
1556 | intel_crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; | |
1557 | g4x_program_watermarks(dev_priv); | |
1558 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
1559 | } | |
1560 | ||
262cd2e1 VS |
1561 | /* latency must be in 0.1us units. */ |
1562 | static unsigned int vlv_wm_method2(unsigned int pixel_rate, | |
baf69ca8 VS |
1563 | unsigned int htotal, |
1564 | unsigned int width, | |
ac484963 | 1565 | unsigned int cpp, |
262cd2e1 VS |
1566 | unsigned int latency) |
1567 | { | |
1568 | unsigned int ret; | |
1569 | ||
baf69ca8 VS |
1570 | ret = intel_wm_method2(pixel_rate, htotal, |
1571 | width, cpp, latency); | |
262cd2e1 VS |
1572 | ret = DIV_ROUND_UP(ret, 64); |
1573 | ||
1574 | return ret; | |
1575 | } | |
1576 | ||
bb726519 | 1577 | static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv) |
262cd2e1 | 1578 | { |
262cd2e1 VS |
1579 | /* all latencies in usec */ |
1580 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3; | |
1581 | ||
58590c14 VS |
1582 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM2; |
1583 | ||
262cd2e1 VS |
1584 | if (IS_CHERRYVIEW(dev_priv)) { |
1585 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12; | |
1586 | dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33; | |
58590c14 VS |
1587 | |
1588 | dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS; | |
262cd2e1 VS |
1589 | } |
1590 | } | |
1591 | ||
e339d67e VS |
1592 | static uint16_t vlv_compute_wm_level(const struct intel_crtc_state *crtc_state, |
1593 | const struct intel_plane_state *plane_state, | |
262cd2e1 VS |
1594 | int level) |
1595 | { | |
e339d67e | 1596 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
262cd2e1 | 1597 | struct drm_i915_private *dev_priv = to_i915(plane->base.dev); |
e339d67e VS |
1598 | const struct drm_display_mode *adjusted_mode = |
1599 | &crtc_state->base.adjusted_mode; | |
ac484963 | 1600 | int clock, htotal, cpp, width, wm; |
262cd2e1 VS |
1601 | |
1602 | if (dev_priv->wm.pri_latency[level] == 0) | |
1603 | return USHRT_MAX; | |
1604 | ||
a07102f1 | 1605 | if (!intel_wm_plane_visible(crtc_state, plane_state)) |
262cd2e1 VS |
1606 | return 0; |
1607 | ||
ef426c10 | 1608 | cpp = plane_state->base.fb->format->cpp[0]; |
e339d67e VS |
1609 | clock = adjusted_mode->crtc_clock; |
1610 | htotal = adjusted_mode->crtc_htotal; | |
1611 | width = crtc_state->pipe_src_w; | |
262cd2e1 | 1612 | |
709f3fc9 | 1613 | if (plane->id == PLANE_CURSOR) { |
262cd2e1 VS |
1614 | /* |
1615 | * FIXME the formula gives values that are | |
1616 | * too big for the cursor FIFO, and hence we | |
1617 | * would never be able to use cursors. For | |
1618 | * now just hardcode the watermark. | |
1619 | */ | |
1620 | wm = 63; | |
1621 | } else { | |
ac484963 | 1622 | wm = vlv_wm_method2(clock, htotal, width, cpp, |
262cd2e1 VS |
1623 | dev_priv->wm.pri_latency[level] * 10); |
1624 | } | |
1625 | ||
1626 | return min_t(int, wm, USHRT_MAX); | |
1627 | } | |
1628 | ||
1a10ae6b VS |
1629 | static bool vlv_need_sprite0_fifo_workaround(unsigned int active_planes) |
1630 | { | |
1631 | return (active_planes & (BIT(PLANE_SPRITE0) | | |
1632 | BIT(PLANE_SPRITE1))) == BIT(PLANE_SPRITE1); | |
1633 | } | |
1634 | ||
5012e604 | 1635 | static int vlv_compute_fifo(struct intel_crtc_state *crtc_state) |
54f1b6e1 | 1636 | { |
855c79f5 | 1637 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
114d7dc0 | 1638 | const struct g4x_pipe_wm *raw = |
5012e604 | 1639 | &crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2]; |
814e7f0b | 1640 | struct vlv_fifo_state *fifo_state = &crtc_state->wm.vlv.fifo_state; |
5012e604 VS |
1641 | unsigned int active_planes = crtc_state->active_planes & ~BIT(PLANE_CURSOR); |
1642 | int num_active_planes = hweight32(active_planes); | |
1643 | const int fifo_size = 511; | |
54f1b6e1 | 1644 | int fifo_extra, fifo_left = fifo_size; |
1a10ae6b | 1645 | int sprite0_fifo_extra = 0; |
5012e604 VS |
1646 | unsigned int total_rate; |
1647 | enum plane_id plane_id; | |
54f1b6e1 | 1648 | |
1a10ae6b VS |
1649 | /* |
1650 | * When enabling sprite0 after sprite1 has already been enabled | |
1651 | * we tend to get an underrun unless sprite0 already has some | |
1652 | * FIFO space allcoated. Hence we always allocate at least one | |
1653 | * cacheline for sprite0 whenever sprite1 is enabled. | |
1654 | * | |
1655 | * All other plane enable sequences appear immune to this problem. | |
1656 | */ | |
1657 | if (vlv_need_sprite0_fifo_workaround(active_planes)) | |
1658 | sprite0_fifo_extra = 1; | |
1659 | ||
5012e604 VS |
1660 | total_rate = raw->plane[PLANE_PRIMARY] + |
1661 | raw->plane[PLANE_SPRITE0] + | |
1a10ae6b VS |
1662 | raw->plane[PLANE_SPRITE1] + |
1663 | sprite0_fifo_extra; | |
54f1b6e1 | 1664 | |
5012e604 VS |
1665 | if (total_rate > fifo_size) |
1666 | return -EINVAL; | |
54f1b6e1 | 1667 | |
5012e604 VS |
1668 | if (total_rate == 0) |
1669 | total_rate = 1; | |
54f1b6e1 | 1670 | |
5012e604 | 1671 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1672 | unsigned int rate; |
1673 | ||
5012e604 VS |
1674 | if ((active_planes & BIT(plane_id)) == 0) { |
1675 | fifo_state->plane[plane_id] = 0; | |
54f1b6e1 VS |
1676 | continue; |
1677 | } | |
1678 | ||
5012e604 VS |
1679 | rate = raw->plane[plane_id]; |
1680 | fifo_state->plane[plane_id] = fifo_size * rate / total_rate; | |
1681 | fifo_left -= fifo_state->plane[plane_id]; | |
54f1b6e1 VS |
1682 | } |
1683 | ||
1a10ae6b VS |
1684 | fifo_state->plane[PLANE_SPRITE0] += sprite0_fifo_extra; |
1685 | fifo_left -= sprite0_fifo_extra; | |
1686 | ||
5012e604 VS |
1687 | fifo_state->plane[PLANE_CURSOR] = 63; |
1688 | ||
1689 | fifo_extra = DIV_ROUND_UP(fifo_left, num_active_planes ?: 1); | |
54f1b6e1 VS |
1690 | |
1691 | /* spread the remainder evenly */ | |
5012e604 | 1692 | for_each_plane_id_on_crtc(crtc, plane_id) { |
54f1b6e1 VS |
1693 | int plane_extra; |
1694 | ||
1695 | if (fifo_left == 0) | |
1696 | break; | |
1697 | ||
5012e604 | 1698 | if ((active_planes & BIT(plane_id)) == 0) |
54f1b6e1 VS |
1699 | continue; |
1700 | ||
1701 | plane_extra = min(fifo_extra, fifo_left); | |
5012e604 | 1702 | fifo_state->plane[plane_id] += plane_extra; |
54f1b6e1 VS |
1703 | fifo_left -= plane_extra; |
1704 | } | |
1705 | ||
5012e604 VS |
1706 | WARN_ON(active_planes != 0 && fifo_left != 0); |
1707 | ||
1708 | /* give it all to the first plane if none are active */ | |
1709 | if (active_planes == 0) { | |
1710 | WARN_ON(fifo_left != fifo_size); | |
1711 | fifo_state->plane[PLANE_PRIMARY] = fifo_left; | |
1712 | } | |
1713 | ||
1714 | return 0; | |
54f1b6e1 VS |
1715 | } |
1716 | ||
ff32c54e VS |
1717 | /* mark all levels starting from 'level' as invalid */ |
1718 | static void vlv_invalidate_wms(struct intel_crtc *crtc, | |
1719 | struct vlv_wm_state *wm_state, int level) | |
1720 | { | |
1721 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1722 | ||
6d5019b6 | 1723 | for (; level < intel_wm_num_levels(dev_priv); level++) { |
ff32c54e VS |
1724 | enum plane_id plane_id; |
1725 | ||
1726 | for_each_plane_id_on_crtc(crtc, plane_id) | |
1727 | wm_state->wm[level].plane[plane_id] = USHRT_MAX; | |
1728 | ||
1729 | wm_state->sr[level].cursor = USHRT_MAX; | |
1730 | wm_state->sr[level].plane = USHRT_MAX; | |
1731 | } | |
1732 | } | |
1733 | ||
26cca0e5 VS |
1734 | static u16 vlv_invert_wm_value(u16 wm, u16 fifo_size) |
1735 | { | |
1736 | if (wm > fifo_size) | |
1737 | return USHRT_MAX; | |
1738 | else | |
1739 | return fifo_size - wm; | |
1740 | } | |
1741 | ||
ff32c54e VS |
1742 | /* |
1743 | * Starting from 'level' set all higher | |
1744 | * levels to 'value' in the "raw" watermarks. | |
1745 | */ | |
236c48e6 | 1746 | static bool vlv_raw_plane_wm_set(struct intel_crtc_state *crtc_state, |
ff32c54e | 1747 | int level, enum plane_id plane_id, u16 value) |
262cd2e1 | 1748 | { |
ff32c54e | 1749 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); |
6d5019b6 | 1750 | int num_levels = intel_wm_num_levels(dev_priv); |
236c48e6 | 1751 | bool dirty = false; |
262cd2e1 | 1752 | |
ff32c54e | 1753 | for (; level < num_levels; level++) { |
114d7dc0 | 1754 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
262cd2e1 | 1755 | |
236c48e6 | 1756 | dirty |= raw->plane[plane_id] != value; |
ff32c54e | 1757 | raw->plane[plane_id] = value; |
262cd2e1 | 1758 | } |
236c48e6 VS |
1759 | |
1760 | return dirty; | |
262cd2e1 VS |
1761 | } |
1762 | ||
77d14ee4 VS |
1763 | static bool vlv_raw_plane_wm_compute(struct intel_crtc_state *crtc_state, |
1764 | const struct intel_plane_state *plane_state) | |
262cd2e1 | 1765 | { |
ff32c54e VS |
1766 | struct intel_plane *plane = to_intel_plane(plane_state->base.plane); |
1767 | enum plane_id plane_id = plane->id; | |
6d5019b6 | 1768 | int num_levels = intel_wm_num_levels(to_i915(plane->base.dev)); |
262cd2e1 | 1769 | int level; |
236c48e6 | 1770 | bool dirty = false; |
262cd2e1 | 1771 | |
a07102f1 | 1772 | if (!intel_wm_plane_visible(crtc_state, plane_state)) { |
236c48e6 VS |
1773 | dirty |= vlv_raw_plane_wm_set(crtc_state, 0, plane_id, 0); |
1774 | goto out; | |
ff32c54e | 1775 | } |
262cd2e1 | 1776 | |
ff32c54e | 1777 | for (level = 0; level < num_levels; level++) { |
114d7dc0 | 1778 | struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e VS |
1779 | int wm = vlv_compute_wm_level(crtc_state, plane_state, level); |
1780 | int max_wm = plane_id == PLANE_CURSOR ? 63 : 511; | |
262cd2e1 | 1781 | |
ff32c54e VS |
1782 | if (wm > max_wm) |
1783 | break; | |
262cd2e1 | 1784 | |
236c48e6 | 1785 | dirty |= raw->plane[plane_id] != wm; |
ff32c54e VS |
1786 | raw->plane[plane_id] = wm; |
1787 | } | |
262cd2e1 | 1788 | |
ff32c54e | 1789 | /* mark all higher levels as invalid */ |
236c48e6 | 1790 | dirty |= vlv_raw_plane_wm_set(crtc_state, level, plane_id, USHRT_MAX); |
262cd2e1 | 1791 | |
236c48e6 VS |
1792 | out: |
1793 | if (dirty) | |
57a6528a | 1794 | DRM_DEBUG_KMS("%s watermarks: PM2=%d, PM5=%d, DDR DVFS=%d\n", |
236c48e6 VS |
1795 | plane->base.name, |
1796 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM2].plane[plane_id], | |
1797 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_PM5].plane[plane_id], | |
1798 | crtc_state->wm.vlv.raw[VLV_WM_LEVEL_DDR_DVFS].plane[plane_id]); | |
1799 | ||
1800 | return dirty; | |
ff32c54e | 1801 | } |
262cd2e1 | 1802 | |
77d14ee4 VS |
1803 | static bool vlv_raw_plane_wm_is_valid(const struct intel_crtc_state *crtc_state, |
1804 | enum plane_id plane_id, int level) | |
ff32c54e | 1805 | { |
114d7dc0 | 1806 | const struct g4x_pipe_wm *raw = |
ff32c54e VS |
1807 | &crtc_state->wm.vlv.raw[level]; |
1808 | const struct vlv_fifo_state *fifo_state = | |
1809 | &crtc_state->wm.vlv.fifo_state; | |
262cd2e1 | 1810 | |
ff32c54e VS |
1811 | return raw->plane[plane_id] <= fifo_state->plane[plane_id]; |
1812 | } | |
262cd2e1 | 1813 | |
77d14ee4 | 1814 | static bool vlv_raw_crtc_wm_is_valid(const struct intel_crtc_state *crtc_state, int level) |
ff32c54e | 1815 | { |
77d14ee4 VS |
1816 | return vlv_raw_plane_wm_is_valid(crtc_state, PLANE_PRIMARY, level) && |
1817 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE0, level) && | |
1818 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_SPRITE1, level) && | |
1819 | vlv_raw_plane_wm_is_valid(crtc_state, PLANE_CURSOR, level); | |
ff32c54e VS |
1820 | } |
1821 | ||
1822 | static int vlv_compute_pipe_wm(struct intel_crtc_state *crtc_state) | |
1823 | { | |
1824 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
1825 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); | |
1826 | struct intel_atomic_state *state = | |
1827 | to_intel_atomic_state(crtc_state->base.state); | |
1828 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
1829 | const struct vlv_fifo_state *fifo_state = | |
1830 | &crtc_state->wm.vlv.fifo_state; | |
1831 | int num_active_planes = hweight32(crtc_state->active_planes & | |
1832 | ~BIT(PLANE_CURSOR)); | |
236c48e6 | 1833 | bool needs_modeset = drm_atomic_crtc_needs_modeset(&crtc_state->base); |
ff32c54e VS |
1834 | struct intel_plane_state *plane_state; |
1835 | struct intel_plane *plane; | |
1836 | enum plane_id plane_id; | |
1837 | int level, ret, i; | |
236c48e6 | 1838 | unsigned int dirty = 0; |
ff32c54e VS |
1839 | |
1840 | for_each_intel_plane_in_state(state, plane, plane_state, i) { | |
1841 | const struct intel_plane_state *old_plane_state = | |
1842 | to_intel_plane_state(plane->base.state); | |
1843 | ||
1844 | if (plane_state->base.crtc != &crtc->base && | |
1845 | old_plane_state->base.crtc != &crtc->base) | |
1846 | continue; | |
262cd2e1 | 1847 | |
77d14ee4 | 1848 | if (vlv_raw_plane_wm_compute(crtc_state, plane_state)) |
236c48e6 VS |
1849 | dirty |= BIT(plane->id); |
1850 | } | |
1851 | ||
1852 | /* | |
1853 | * DSPARB registers may have been reset due to the | |
1854 | * power well being turned off. Make sure we restore | |
1855 | * them to a consistent state even if no primary/sprite | |
1856 | * planes are initially active. | |
1857 | */ | |
1858 | if (needs_modeset) | |
1859 | crtc_state->fifo_changed = true; | |
1860 | ||
1861 | if (!dirty) | |
1862 | return 0; | |
1863 | ||
1864 | /* cursor changes don't warrant a FIFO recompute */ | |
1865 | if (dirty & ~BIT(PLANE_CURSOR)) { | |
1866 | const struct intel_crtc_state *old_crtc_state = | |
1867 | to_intel_crtc_state(crtc->base.state); | |
1868 | const struct vlv_fifo_state *old_fifo_state = | |
1869 | &old_crtc_state->wm.vlv.fifo_state; | |
1870 | ||
1871 | ret = vlv_compute_fifo(crtc_state); | |
1872 | if (ret) | |
1873 | return ret; | |
1874 | ||
1875 | if (needs_modeset || | |
1876 | memcmp(old_fifo_state, fifo_state, | |
1877 | sizeof(*fifo_state)) != 0) | |
1878 | crtc_state->fifo_changed = true; | |
5012e604 | 1879 | } |
262cd2e1 | 1880 | |
ff32c54e | 1881 | /* initially allow all levels */ |
6d5019b6 | 1882 | wm_state->num_levels = intel_wm_num_levels(dev_priv); |
ff32c54e VS |
1883 | /* |
1884 | * Note that enabling cxsr with no primary/sprite planes | |
1885 | * enabled can wedge the pipe. Hence we only allow cxsr | |
1886 | * with exactly one enabled primary/sprite plane. | |
1887 | */ | |
5eeb798b | 1888 | wm_state->cxsr = crtc->pipe != PIPE_C && num_active_planes == 1; |
ff32c54e | 1889 | |
5012e604 | 1890 | for (level = 0; level < wm_state->num_levels; level++) { |
114d7dc0 | 1891 | const struct g4x_pipe_wm *raw = &crtc_state->wm.vlv.raw[level]; |
ff32c54e | 1892 | const int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1; |
5012e604 | 1893 | |
77d14ee4 | 1894 | if (!vlv_raw_crtc_wm_is_valid(crtc_state, level)) |
ff32c54e | 1895 | break; |
5012e604 | 1896 | |
ff32c54e VS |
1897 | for_each_plane_id_on_crtc(crtc, plane_id) { |
1898 | wm_state->wm[level].plane[plane_id] = | |
1899 | vlv_invert_wm_value(raw->plane[plane_id], | |
1900 | fifo_state->plane[plane_id]); | |
1901 | } | |
1902 | ||
1903 | wm_state->sr[level].plane = | |
1904 | vlv_invert_wm_value(max3(raw->plane[PLANE_PRIMARY], | |
5012e604 | 1905 | raw->plane[PLANE_SPRITE0], |
ff32c54e VS |
1906 | raw->plane[PLANE_SPRITE1]), |
1907 | sr_fifo_size); | |
262cd2e1 | 1908 | |
ff32c54e VS |
1909 | wm_state->sr[level].cursor = |
1910 | vlv_invert_wm_value(raw->plane[PLANE_CURSOR], | |
1911 | 63); | |
262cd2e1 VS |
1912 | } |
1913 | ||
ff32c54e VS |
1914 | if (level == 0) |
1915 | return -EINVAL; | |
1916 | ||
1917 | /* limit to only levels we can actually handle */ | |
1918 | wm_state->num_levels = level; | |
1919 | ||
1920 | /* invalidate the higher levels */ | |
1921 | vlv_invalidate_wms(crtc, wm_state, level); | |
1922 | ||
1923 | return 0; | |
262cd2e1 VS |
1924 | } |
1925 | ||
54f1b6e1 VS |
1926 | #define VLV_FIFO(plane, value) \ |
1927 | (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV) | |
1928 | ||
ff32c54e VS |
1929 | static void vlv_atomic_update_fifo(struct intel_atomic_state *state, |
1930 | struct intel_crtc_state *crtc_state) | |
54f1b6e1 | 1931 | { |
814e7f0b | 1932 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); |
f07d43d2 | 1933 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
814e7f0b VS |
1934 | const struct vlv_fifo_state *fifo_state = |
1935 | &crtc_state->wm.vlv.fifo_state; | |
f07d43d2 | 1936 | int sprite0_start, sprite1_start, fifo_size; |
54f1b6e1 | 1937 | |
236c48e6 VS |
1938 | if (!crtc_state->fifo_changed) |
1939 | return; | |
1940 | ||
f07d43d2 VS |
1941 | sprite0_start = fifo_state->plane[PLANE_PRIMARY]; |
1942 | sprite1_start = fifo_state->plane[PLANE_SPRITE0] + sprite0_start; | |
1943 | fifo_size = fifo_state->plane[PLANE_SPRITE1] + sprite1_start; | |
54f1b6e1 | 1944 | |
f07d43d2 VS |
1945 | WARN_ON(fifo_state->plane[PLANE_CURSOR] != 63); |
1946 | WARN_ON(fifo_size != 511); | |
54f1b6e1 | 1947 | |
c137d660 VS |
1948 | trace_vlv_fifo_size(crtc, sprite0_start, sprite1_start, fifo_size); |
1949 | ||
44e921d4 VS |
1950 | /* |
1951 | * uncore.lock serves a double purpose here. It allows us to | |
1952 | * use the less expensive I915_{READ,WRITE}_FW() functions, and | |
1953 | * it protects the DSPARB registers from getting clobbered by | |
1954 | * parallel updates from multiple pipes. | |
1955 | * | |
1956 | * intel_pipe_update_start() has already disabled interrupts | |
1957 | * for us, so a plain spin_lock() is sufficient here. | |
1958 | */ | |
1959 | spin_lock(&dev_priv->uncore.lock); | |
467a14d9 | 1960 | |
54f1b6e1 VS |
1961 | switch (crtc->pipe) { |
1962 | uint32_t dsparb, dsparb2, dsparb3; | |
1963 | case PIPE_A: | |
44e921d4 VS |
1964 | dsparb = I915_READ_FW(DSPARB); |
1965 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1966 | |
1967 | dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) | | |
1968 | VLV_FIFO(SPRITEB, 0xff)); | |
1969 | dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) | | |
1970 | VLV_FIFO(SPRITEB, sprite1_start)); | |
1971 | ||
1972 | dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) | | |
1973 | VLV_FIFO(SPRITEB_HI, 0x1)); | |
1974 | dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) | | |
1975 | VLV_FIFO(SPRITEB_HI, sprite1_start >> 8)); | |
1976 | ||
44e921d4 VS |
1977 | I915_WRITE_FW(DSPARB, dsparb); |
1978 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1979 | break; |
1980 | case PIPE_B: | |
44e921d4 VS |
1981 | dsparb = I915_READ_FW(DSPARB); |
1982 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
1983 | |
1984 | dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) | | |
1985 | VLV_FIFO(SPRITED, 0xff)); | |
1986 | dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) | | |
1987 | VLV_FIFO(SPRITED, sprite1_start)); | |
1988 | ||
1989 | dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) | | |
1990 | VLV_FIFO(SPRITED_HI, 0xff)); | |
1991 | dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) | | |
1992 | VLV_FIFO(SPRITED_HI, sprite1_start >> 8)); | |
1993 | ||
44e921d4 VS |
1994 | I915_WRITE_FW(DSPARB, dsparb); |
1995 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
1996 | break; |
1997 | case PIPE_C: | |
44e921d4 VS |
1998 | dsparb3 = I915_READ_FW(DSPARB3); |
1999 | dsparb2 = I915_READ_FW(DSPARB2); | |
54f1b6e1 VS |
2000 | |
2001 | dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) | | |
2002 | VLV_FIFO(SPRITEF, 0xff)); | |
2003 | dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) | | |
2004 | VLV_FIFO(SPRITEF, sprite1_start)); | |
2005 | ||
2006 | dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) | | |
2007 | VLV_FIFO(SPRITEF_HI, 0xff)); | |
2008 | dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) | | |
2009 | VLV_FIFO(SPRITEF_HI, sprite1_start >> 8)); | |
2010 | ||
44e921d4 VS |
2011 | I915_WRITE_FW(DSPARB3, dsparb3); |
2012 | I915_WRITE_FW(DSPARB2, dsparb2); | |
54f1b6e1 VS |
2013 | break; |
2014 | default: | |
2015 | break; | |
2016 | } | |
467a14d9 | 2017 | |
44e921d4 | 2018 | POSTING_READ_FW(DSPARB); |
467a14d9 | 2019 | |
44e921d4 | 2020 | spin_unlock(&dev_priv->uncore.lock); |
54f1b6e1 VS |
2021 | } |
2022 | ||
2023 | #undef VLV_FIFO | |
2024 | ||
4841da51 VS |
2025 | static int vlv_compute_intermediate_wm(struct drm_device *dev, |
2026 | struct intel_crtc *crtc, | |
2027 | struct intel_crtc_state *crtc_state) | |
2028 | { | |
2029 | struct vlv_wm_state *intermediate = &crtc_state->wm.vlv.intermediate; | |
2030 | const struct vlv_wm_state *optimal = &crtc_state->wm.vlv.optimal; | |
2031 | const struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
2032 | int level; | |
2033 | ||
2034 | intermediate->num_levels = min(optimal->num_levels, active->num_levels); | |
5eeb798b VS |
2035 | intermediate->cxsr = optimal->cxsr && active->cxsr && |
2036 | !crtc_state->disable_cxsr; | |
4841da51 VS |
2037 | |
2038 | for (level = 0; level < intermediate->num_levels; level++) { | |
2039 | enum plane_id plane_id; | |
2040 | ||
2041 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
2042 | intermediate->wm[level].plane[plane_id] = | |
2043 | min(optimal->wm[level].plane[plane_id], | |
2044 | active->wm[level].plane[plane_id]); | |
2045 | } | |
2046 | ||
2047 | intermediate->sr[level].plane = min(optimal->sr[level].plane, | |
2048 | active->sr[level].plane); | |
2049 | intermediate->sr[level].cursor = min(optimal->sr[level].cursor, | |
2050 | active->sr[level].cursor); | |
2051 | } | |
2052 | ||
2053 | vlv_invalidate_wms(crtc, intermediate, level); | |
2054 | ||
2055 | /* | |
2056 | * If our intermediate WM are identical to the final WM, then we can | |
2057 | * omit the post-vblank programming; only update if it's different. | |
2058 | */ | |
5eeb798b VS |
2059 | if (memcmp(intermediate, optimal, sizeof(*intermediate)) != 0) |
2060 | crtc_state->wm.need_postvbl_update = true; | |
4841da51 VS |
2061 | |
2062 | return 0; | |
2063 | } | |
2064 | ||
7c951c00 | 2065 | static void vlv_merge_wm(struct drm_i915_private *dev_priv, |
262cd2e1 VS |
2066 | struct vlv_wm_values *wm) |
2067 | { | |
2068 | struct intel_crtc *crtc; | |
2069 | int num_active_crtcs = 0; | |
2070 | ||
7c951c00 | 2071 | wm->level = dev_priv->wm.max_level; |
262cd2e1 VS |
2072 | wm->cxsr = true; |
2073 | ||
7c951c00 | 2074 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 2075 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
2076 | |
2077 | if (!crtc->active) | |
2078 | continue; | |
2079 | ||
2080 | if (!wm_state->cxsr) | |
2081 | wm->cxsr = false; | |
2082 | ||
2083 | num_active_crtcs++; | |
2084 | wm->level = min_t(int, wm->level, wm_state->num_levels - 1); | |
2085 | } | |
2086 | ||
2087 | if (num_active_crtcs != 1) | |
2088 | wm->cxsr = false; | |
2089 | ||
6f9c784b VS |
2090 | if (num_active_crtcs > 1) |
2091 | wm->level = VLV_WM_LEVEL_PM2; | |
2092 | ||
7c951c00 | 2093 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
7eb4941f | 2094 | const struct vlv_wm_state *wm_state = &crtc->wm.active.vlv; |
262cd2e1 VS |
2095 | enum pipe pipe = crtc->pipe; |
2096 | ||
262cd2e1 | 2097 | wm->pipe[pipe] = wm_state->wm[wm->level]; |
ff32c54e | 2098 | if (crtc->active && wm->cxsr) |
262cd2e1 VS |
2099 | wm->sr = wm_state->sr[wm->level]; |
2100 | ||
1b31389c VS |
2101 | wm->ddl[pipe].plane[PLANE_PRIMARY] = DDL_PRECISION_HIGH | 2; |
2102 | wm->ddl[pipe].plane[PLANE_SPRITE0] = DDL_PRECISION_HIGH | 2; | |
2103 | wm->ddl[pipe].plane[PLANE_SPRITE1] = DDL_PRECISION_HIGH | 2; | |
2104 | wm->ddl[pipe].plane[PLANE_CURSOR] = DDL_PRECISION_HIGH | 2; | |
262cd2e1 VS |
2105 | } |
2106 | } | |
2107 | ||
ff32c54e | 2108 | static void vlv_program_watermarks(struct drm_i915_private *dev_priv) |
262cd2e1 | 2109 | { |
fa292a4b VS |
2110 | struct vlv_wm_values *old_wm = &dev_priv->wm.vlv; |
2111 | struct vlv_wm_values new_wm = {}; | |
262cd2e1 | 2112 | |
fa292a4b | 2113 | vlv_merge_wm(dev_priv, &new_wm); |
262cd2e1 | 2114 | |
ff32c54e | 2115 | if (memcmp(old_wm, &new_wm, sizeof(new_wm)) == 0) |
262cd2e1 VS |
2116 | return; |
2117 | ||
fa292a4b | 2118 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
2119 | chv_set_memory_dvfs(dev_priv, false); |
2120 | ||
fa292a4b | 2121 | if (is_disabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
2122 | chv_set_memory_pm5(dev_priv, false); |
2123 | ||
fa292a4b | 2124 | if (is_disabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 2125 | _intel_set_memory_cxsr(dev_priv, false); |
262cd2e1 | 2126 | |
fa292a4b | 2127 | vlv_write_wm_values(dev_priv, &new_wm); |
262cd2e1 | 2128 | |
fa292a4b | 2129 | if (is_enabling(old_wm->cxsr, new_wm.cxsr, true)) |
3d90e649 | 2130 | _intel_set_memory_cxsr(dev_priv, true); |
262cd2e1 | 2131 | |
fa292a4b | 2132 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_PM5)) |
262cd2e1 VS |
2133 | chv_set_memory_pm5(dev_priv, true); |
2134 | ||
fa292a4b | 2135 | if (is_enabling(old_wm->level, new_wm.level, VLV_WM_LEVEL_DDR_DVFS)) |
262cd2e1 VS |
2136 | chv_set_memory_dvfs(dev_priv, true); |
2137 | ||
fa292a4b | 2138 | *old_wm = new_wm; |
3c2777fd VS |
2139 | } |
2140 | ||
ff32c54e VS |
2141 | static void vlv_initial_watermarks(struct intel_atomic_state *state, |
2142 | struct intel_crtc_state *crtc_state) | |
2143 | { | |
2144 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
2145 | struct intel_crtc *crtc = to_intel_crtc(crtc_state->base.crtc); | |
2146 | ||
2147 | mutex_lock(&dev_priv->wm.wm_mutex); | |
4841da51 VS |
2148 | crtc->wm.active.vlv = crtc_state->wm.vlv.intermediate; |
2149 | vlv_program_watermarks(dev_priv); | |
2150 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2151 | } | |
2152 | ||
2153 | static void vlv_optimize_watermarks(struct intel_atomic_state *state, | |
2154 | struct intel_crtc_state *crtc_state) | |
2155 | { | |
2156 | struct drm_i915_private *dev_priv = to_i915(crtc_state->base.crtc->dev); | |
2157 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc_state->base.crtc); | |
2158 | ||
2159 | if (!crtc_state->wm.need_postvbl_update) | |
2160 | return; | |
2161 | ||
2162 | mutex_lock(&dev_priv->wm.wm_mutex); | |
2163 | intel_crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
ff32c54e VS |
2164 | vlv_program_watermarks(dev_priv); |
2165 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2166 | } | |
2167 | ||
432081bc | 2168 | static void i965_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2169 | { |
ffc7a76b | 2170 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 2171 | struct intel_crtc *crtc; |
b445e3b0 ED |
2172 | int srwm = 1; |
2173 | int cursor_sr = 16; | |
9858425c | 2174 | bool cxsr_enabled; |
b445e3b0 ED |
2175 | |
2176 | /* Calc sr entries for one plane configs */ | |
ffc7a76b | 2177 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
2178 | if (crtc) { |
2179 | /* self-refresh has much higher latency */ | |
2180 | static const int sr_latency_ns = 12000; | |
efc2611e VS |
2181 | const struct drm_display_mode *adjusted_mode = |
2182 | &crtc->config->base.adjusted_mode; | |
2183 | const struct drm_framebuffer *fb = | |
2184 | crtc->base.primary->state->fb; | |
241bfc38 | 2185 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 2186 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e | 2187 | int hdisplay = crtc->config->pipe_src_w; |
353c8598 | 2188 | int cpp = fb->format->cpp[0]; |
b445e3b0 ED |
2189 | int entries; |
2190 | ||
baf69ca8 VS |
2191 | entries = intel_wm_method2(clock, htotal, |
2192 | hdisplay, cpp, sr_latency_ns / 100); | |
b445e3b0 ED |
2193 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); |
2194 | srwm = I965_FIFO_SIZE - entries; | |
2195 | if (srwm < 0) | |
2196 | srwm = 1; | |
2197 | srwm &= 0x1ff; | |
2198 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
2199 | entries, srwm); | |
2200 | ||
baf69ca8 VS |
2201 | entries = intel_wm_method2(clock, htotal, |
2202 | crtc->base.cursor->state->crtc_w, 4, | |
2203 | sr_latency_ns / 100); | |
b445e3b0 | 2204 | entries = DIV_ROUND_UP(entries, |
baf69ca8 VS |
2205 | i965_cursor_wm_info.cacheline_size) + |
2206 | i965_cursor_wm_info.guard_size; | |
b445e3b0 | 2207 | |
baf69ca8 | 2208 | cursor_sr = i965_cursor_wm_info.fifo_size - entries; |
b445e3b0 ED |
2209 | if (cursor_sr > i965_cursor_wm_info.max_wm) |
2210 | cursor_sr = i965_cursor_wm_info.max_wm; | |
2211 | ||
2212 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
2213 | "cursor %d\n", srwm, cursor_sr); | |
2214 | ||
9858425c | 2215 | cxsr_enabled = true; |
b445e3b0 | 2216 | } else { |
9858425c | 2217 | cxsr_enabled = false; |
b445e3b0 | 2218 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 2219 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
2220 | } |
2221 | ||
2222 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
2223 | srwm); | |
2224 | ||
2225 | /* 965 has limitations... */ | |
f4998963 VS |
2226 | I915_WRITE(DSPFW1, FW_WM(srwm, SR) | |
2227 | FW_WM(8, CURSORB) | | |
2228 | FW_WM(8, PLANEB) | | |
2229 | FW_WM(8, PLANEA)); | |
2230 | I915_WRITE(DSPFW2, FW_WM(8, CURSORA) | | |
2231 | FW_WM(8, PLANEC_OLD)); | |
b445e3b0 | 2232 | /* update cursor SR watermark */ |
f4998963 | 2233 | I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR)); |
9858425c ID |
2234 | |
2235 | if (cxsr_enabled) | |
2236 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
2237 | } |
2238 | ||
f4998963 VS |
2239 | #undef FW_WM |
2240 | ||
432081bc | 2241 | static void i9xx_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2242 | { |
ffc7a76b | 2243 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
b445e3b0 ED |
2244 | const struct intel_watermark_params *wm_info; |
2245 | uint32_t fwater_lo; | |
2246 | uint32_t fwater_hi; | |
2247 | int cwm, srwm = 1; | |
2248 | int fifo_size; | |
2249 | int planea_wm, planeb_wm; | |
efc2611e | 2250 | struct intel_crtc *crtc, *enabled = NULL; |
b445e3b0 | 2251 | |
a9097be4 | 2252 | if (IS_I945GM(dev_priv)) |
b445e3b0 | 2253 | wm_info = &i945_wm_info; |
5db94019 | 2254 | else if (!IS_GEN2(dev_priv)) |
b445e3b0 ED |
2255 | wm_info = &i915_wm_info; |
2256 | else | |
9d539105 | 2257 | wm_info = &i830_a_wm_info; |
b445e3b0 | 2258 | |
ef0f5e93 | 2259 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0); |
b91eb5cc | 2260 | crtc = intel_get_crtc_for_plane(dev_priv, 0); |
efc2611e VS |
2261 | if (intel_crtc_active(crtc)) { |
2262 | const struct drm_display_mode *adjusted_mode = | |
2263 | &crtc->config->base.adjusted_mode; | |
2264 | const struct drm_framebuffer *fb = | |
2265 | crtc->base.primary->state->fb; | |
2266 | int cpp; | |
2267 | ||
5db94019 | 2268 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 2269 | cpp = 4; |
efc2611e | 2270 | else |
353c8598 | 2271 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 2272 | |
241bfc38 | 2273 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 2274 | wm_info, fifo_size, cpp, |
5aef6003 | 2275 | pessimal_latency_ns); |
b445e3b0 | 2276 | enabled = crtc; |
9d539105 | 2277 | } else { |
b445e3b0 | 2278 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
2279 | if (planea_wm > (long)wm_info->max_wm) |
2280 | planea_wm = wm_info->max_wm; | |
2281 | } | |
2282 | ||
5db94019 | 2283 | if (IS_GEN2(dev_priv)) |
9d539105 | 2284 | wm_info = &i830_bc_wm_info; |
b445e3b0 | 2285 | |
ef0f5e93 | 2286 | fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1); |
b91eb5cc | 2287 | crtc = intel_get_crtc_for_plane(dev_priv, 1); |
efc2611e VS |
2288 | if (intel_crtc_active(crtc)) { |
2289 | const struct drm_display_mode *adjusted_mode = | |
2290 | &crtc->config->base.adjusted_mode; | |
2291 | const struct drm_framebuffer *fb = | |
2292 | crtc->base.primary->state->fb; | |
2293 | int cpp; | |
2294 | ||
5db94019 | 2295 | if (IS_GEN2(dev_priv)) |
b9e0bda3 | 2296 | cpp = 4; |
efc2611e | 2297 | else |
353c8598 | 2298 | cpp = fb->format->cpp[0]; |
b9e0bda3 | 2299 | |
241bfc38 | 2300 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
b9e0bda3 | 2301 | wm_info, fifo_size, cpp, |
5aef6003 | 2302 | pessimal_latency_ns); |
b445e3b0 ED |
2303 | if (enabled == NULL) |
2304 | enabled = crtc; | |
2305 | else | |
2306 | enabled = NULL; | |
9d539105 | 2307 | } else { |
b445e3b0 | 2308 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
2309 | if (planeb_wm > (long)wm_info->max_wm) |
2310 | planeb_wm = wm_info->max_wm; | |
2311 | } | |
b445e3b0 ED |
2312 | |
2313 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
2314 | ||
50a0bc90 | 2315 | if (IS_I915GM(dev_priv) && enabled) { |
2ff8fde1 | 2316 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 2317 | |
efc2611e | 2318 | obj = intel_fb_obj(enabled->base.primary->state->fb); |
2ab1bc9d DV |
2319 | |
2320 | /* self-refresh seems busted with untiled */ | |
3e510a8e | 2321 | if (!i915_gem_object_is_tiled(obj)) |
2ab1bc9d DV |
2322 | enabled = NULL; |
2323 | } | |
2324 | ||
b445e3b0 ED |
2325 | /* |
2326 | * Overlay gets an aggressive default since video jitter is bad. | |
2327 | */ | |
2328 | cwm = 2; | |
2329 | ||
2330 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 2331 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
2332 | |
2333 | /* Calc sr entries for one plane configs */ | |
03427fcb | 2334 | if (HAS_FW_BLC(dev_priv) && enabled) { |
b445e3b0 ED |
2335 | /* self-refresh has much higher latency */ |
2336 | static const int sr_latency_ns = 6000; | |
efc2611e VS |
2337 | const struct drm_display_mode *adjusted_mode = |
2338 | &enabled->config->base.adjusted_mode; | |
2339 | const struct drm_framebuffer *fb = | |
2340 | enabled->base.primary->state->fb; | |
241bfc38 | 2341 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 2342 | int htotal = adjusted_mode->crtc_htotal; |
efc2611e VS |
2343 | int hdisplay = enabled->config->pipe_src_w; |
2344 | int cpp; | |
b445e3b0 ED |
2345 | int entries; |
2346 | ||
50a0bc90 | 2347 | if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv)) |
2d1b5056 | 2348 | cpp = 4; |
efc2611e | 2349 | else |
353c8598 | 2350 | cpp = fb->format->cpp[0]; |
2d1b5056 | 2351 | |
baf69ca8 VS |
2352 | entries = intel_wm_method2(clock, htotal, hdisplay, cpp, |
2353 | sr_latency_ns / 100); | |
b445e3b0 ED |
2354 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); |
2355 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
2356 | srwm = wm_info->fifo_size - entries; | |
2357 | if (srwm < 0) | |
2358 | srwm = 1; | |
2359 | ||
50a0bc90 | 2360 | if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) |
b445e3b0 ED |
2361 | I915_WRITE(FW_BLC_SELF, |
2362 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
acb91359 | 2363 | else |
b445e3b0 ED |
2364 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); |
2365 | } | |
2366 | ||
2367 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
2368 | planea_wm, planeb_wm, cwm, srwm); | |
2369 | ||
2370 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
2371 | fwater_hi = (cwm & 0x1f); | |
2372 | ||
2373 | /* Set request length to 8 cachelines per fetch */ | |
2374 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
2375 | fwater_hi = fwater_hi | (1 << 8); | |
2376 | ||
2377 | I915_WRITE(FW_BLC, fwater_lo); | |
2378 | I915_WRITE(FW_BLC2, fwater_hi); | |
2379 | ||
5209b1f4 ID |
2380 | if (enabled) |
2381 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
2382 | } |
2383 | ||
432081bc | 2384 | static void i845_update_wm(struct intel_crtc *unused_crtc) |
b445e3b0 | 2385 | { |
ffc7a76b | 2386 | struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev); |
efc2611e | 2387 | struct intel_crtc *crtc; |
241bfc38 | 2388 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
2389 | uint32_t fwater_lo; |
2390 | int planea_wm; | |
2391 | ||
ffc7a76b | 2392 | crtc = single_enabled_crtc(dev_priv); |
b445e3b0 ED |
2393 | if (crtc == NULL) |
2394 | return; | |
2395 | ||
efc2611e | 2396 | adjusted_mode = &crtc->config->base.adjusted_mode; |
241bfc38 | 2397 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, |
feb56b93 | 2398 | &i845_wm_info, |
ef0f5e93 | 2399 | dev_priv->display.get_fifo_size(dev_priv, 0), |
5aef6003 | 2400 | 4, pessimal_latency_ns); |
b445e3b0 ED |
2401 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
2402 | fwater_lo |= (3<<8) | planea_wm; | |
2403 | ||
2404 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
2405 | ||
2406 | I915_WRITE(FW_BLC, fwater_lo); | |
2407 | } | |
2408 | ||
37126462 | 2409 | /* latency must be in 0.1us units. */ |
baf69ca8 VS |
2410 | static unsigned int ilk_wm_method1(unsigned int pixel_rate, |
2411 | unsigned int cpp, | |
2412 | unsigned int latency) | |
801bcfff | 2413 | { |
baf69ca8 | 2414 | unsigned int ret; |
3312ba65 | 2415 | |
baf69ca8 VS |
2416 | ret = intel_wm_method1(pixel_rate, cpp, latency); |
2417 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
801bcfff PZ |
2418 | |
2419 | return ret; | |
2420 | } | |
2421 | ||
37126462 | 2422 | /* latency must be in 0.1us units. */ |
baf69ca8 VS |
2423 | static unsigned int ilk_wm_method2(unsigned int pixel_rate, |
2424 | unsigned int htotal, | |
2425 | unsigned int width, | |
2426 | unsigned int cpp, | |
2427 | unsigned int latency) | |
801bcfff | 2428 | { |
baf69ca8 | 2429 | unsigned int ret; |
3312ba65 | 2430 | |
baf69ca8 VS |
2431 | ret = intel_wm_method2(pixel_rate, htotal, |
2432 | width, cpp, latency); | |
801bcfff | 2433 | ret = DIV_ROUND_UP(ret, 64) + 2; |
baf69ca8 | 2434 | |
801bcfff PZ |
2435 | return ret; |
2436 | } | |
2437 | ||
23297044 | 2438 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
ac484963 | 2439 | uint8_t cpp) |
cca32e9a | 2440 | { |
15126882 MR |
2441 | /* |
2442 | * Neither of these should be possible since this function shouldn't be | |
2443 | * called if the CRTC is off or the plane is invisible. But let's be | |
2444 | * extra paranoid to avoid a potential divide-by-zero if we screw up | |
2445 | * elsewhere in the driver. | |
2446 | */ | |
ac484963 | 2447 | if (WARN_ON(!cpp)) |
15126882 MR |
2448 | return 0; |
2449 | if (WARN_ON(!horiz_pixels)) | |
2450 | return 0; | |
2451 | ||
ac484963 | 2452 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2; |
cca32e9a PZ |
2453 | } |
2454 | ||
820c1980 | 2455 | struct ilk_wm_maximums { |
cca32e9a PZ |
2456 | uint16_t pri; |
2457 | uint16_t spr; | |
2458 | uint16_t cur; | |
2459 | uint16_t fbc; | |
2460 | }; | |
2461 | ||
37126462 VS |
2462 | /* |
2463 | * For both WM_PIPE and WM_LP. | |
2464 | * mem_value must be in 0.1us units. | |
2465 | */ | |
7221fc33 | 2466 | static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2467 | const struct intel_plane_state *pstate, |
cca32e9a PZ |
2468 | uint32_t mem_value, |
2469 | bool is_lp) | |
801bcfff | 2470 | { |
cca32e9a | 2471 | uint32_t method1, method2; |
8305494e | 2472 | int cpp; |
cca32e9a | 2473 | |
24304d81 | 2474 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2475 | return 0; |
2476 | ||
353c8598 | 2477 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2478 | |
a7d1b3f4 | 2479 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
cca32e9a PZ |
2480 | |
2481 | if (!is_lp) | |
2482 | return method1; | |
2483 | ||
a7d1b3f4 | 2484 | method2 = ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2485 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2486 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2487 | cpp, mem_value); |
cca32e9a PZ |
2488 | |
2489 | return min(method1, method2); | |
801bcfff PZ |
2490 | } |
2491 | ||
37126462 VS |
2492 | /* |
2493 | * For both WM_PIPE and WM_LP. | |
2494 | * mem_value must be in 0.1us units. | |
2495 | */ | |
7221fc33 | 2496 | static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2497 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2498 | uint32_t mem_value) |
2499 | { | |
2500 | uint32_t method1, method2; | |
8305494e | 2501 | int cpp; |
801bcfff | 2502 | |
24304d81 | 2503 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2504 | return 0; |
2505 | ||
353c8598 | 2506 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2507 | |
a7d1b3f4 VS |
2508 | method1 = ilk_wm_method1(cstate->pixel_rate, cpp, mem_value); |
2509 | method2 = ilk_wm_method2(cstate->pixel_rate, | |
7221fc33 | 2510 | cstate->base.adjusted_mode.crtc_htotal, |
936e71e3 | 2511 | drm_rect_width(&pstate->base.dst), |
ac484963 | 2512 | cpp, mem_value); |
801bcfff PZ |
2513 | return min(method1, method2); |
2514 | } | |
2515 | ||
37126462 VS |
2516 | /* |
2517 | * For both WM_PIPE and WM_LP. | |
2518 | * mem_value must be in 0.1us units. | |
2519 | */ | |
7221fc33 | 2520 | static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2521 | const struct intel_plane_state *pstate, |
801bcfff PZ |
2522 | uint32_t mem_value) |
2523 | { | |
a5509abd VS |
2524 | int cpp; |
2525 | ||
24304d81 | 2526 | if (!intel_wm_plane_visible(cstate, pstate)) |
801bcfff PZ |
2527 | return 0; |
2528 | ||
a5509abd VS |
2529 | cpp = pstate->base.fb->format->cpp[0]; |
2530 | ||
a7d1b3f4 | 2531 | return ilk_wm_method2(cstate->pixel_rate, |
7221fc33 | 2532 | cstate->base.adjusted_mode.crtc_htotal, |
a5509abd | 2533 | pstate->base.crtc_w, cpp, mem_value); |
801bcfff PZ |
2534 | } |
2535 | ||
cca32e9a | 2536 | /* Only for WM_LP. */ |
7221fc33 | 2537 | static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate, |
43d59eda | 2538 | const struct intel_plane_state *pstate, |
1fda9882 | 2539 | uint32_t pri_val) |
cca32e9a | 2540 | { |
8305494e | 2541 | int cpp; |
43d59eda | 2542 | |
24304d81 | 2543 | if (!intel_wm_plane_visible(cstate, pstate)) |
cca32e9a PZ |
2544 | return 0; |
2545 | ||
353c8598 | 2546 | cpp = pstate->base.fb->format->cpp[0]; |
8305494e | 2547 | |
936e71e3 | 2548 | return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp); |
cca32e9a PZ |
2549 | } |
2550 | ||
175fded1 TU |
2551 | static unsigned int |
2552 | ilk_display_fifo_size(const struct drm_i915_private *dev_priv) | |
158ae64f | 2553 | { |
175fded1 | 2554 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 | 2555 | return 3072; |
175fded1 | 2556 | else if (INTEL_GEN(dev_priv) >= 7) |
158ae64f VS |
2557 | return 768; |
2558 | else | |
2559 | return 512; | |
2560 | } | |
2561 | ||
175fded1 TU |
2562 | static unsigned int |
2563 | ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv, | |
2564 | int level, bool is_sprite) | |
4e975081 | 2565 | { |
175fded1 | 2566 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2567 | /* BDW primary/sprite plane watermarks */ |
2568 | return level == 0 ? 255 : 2047; | |
175fded1 | 2569 | else if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2570 | /* IVB/HSW primary/sprite plane watermarks */ |
2571 | return level == 0 ? 127 : 1023; | |
2572 | else if (!is_sprite) | |
2573 | /* ILK/SNB primary plane watermarks */ | |
2574 | return level == 0 ? 127 : 511; | |
2575 | else | |
2576 | /* ILK/SNB sprite plane watermarks */ | |
2577 | return level == 0 ? 63 : 255; | |
2578 | } | |
2579 | ||
175fded1 TU |
2580 | static unsigned int |
2581 | ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level) | |
4e975081 | 2582 | { |
175fded1 | 2583 | if (INTEL_GEN(dev_priv) >= 7) |
4e975081 VS |
2584 | return level == 0 ? 63 : 255; |
2585 | else | |
2586 | return level == 0 ? 31 : 63; | |
2587 | } | |
2588 | ||
175fded1 | 2589 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv) |
4e975081 | 2590 | { |
175fded1 | 2591 | if (INTEL_GEN(dev_priv) >= 8) |
4e975081 VS |
2592 | return 31; |
2593 | else | |
2594 | return 15; | |
2595 | } | |
2596 | ||
158ae64f VS |
2597 | /* Calculate the maximum primary/sprite plane watermark */ |
2598 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2599 | int level, | |
240264f4 | 2600 | const struct intel_wm_config *config, |
158ae64f VS |
2601 | enum intel_ddb_partitioning ddb_partitioning, |
2602 | bool is_sprite) | |
2603 | { | |
175fded1 TU |
2604 | struct drm_i915_private *dev_priv = to_i915(dev); |
2605 | unsigned int fifo_size = ilk_display_fifo_size(dev_priv); | |
158ae64f VS |
2606 | |
2607 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2608 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2609 | return 0; |
2610 | ||
2611 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2612 | if (level == 0 || config->num_pipes_active > 1) { |
175fded1 | 2613 | fifo_size /= INTEL_INFO(dev_priv)->num_pipes; |
158ae64f VS |
2614 | |
2615 | /* | |
2616 | * For some reason the non self refresh | |
2617 | * FIFO size is only half of the self | |
2618 | * refresh FIFO size on ILK/SNB. | |
2619 | */ | |
175fded1 | 2620 | if (INTEL_GEN(dev_priv) <= 6) |
158ae64f VS |
2621 | fifo_size /= 2; |
2622 | } | |
2623 | ||
240264f4 | 2624 | if (config->sprites_enabled) { |
158ae64f VS |
2625 | /* level 0 is always calculated with 1:1 split */ |
2626 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2627 | if (is_sprite) | |
2628 | fifo_size *= 5; | |
2629 | fifo_size /= 6; | |
2630 | } else { | |
2631 | fifo_size /= 2; | |
2632 | } | |
2633 | } | |
2634 | ||
2635 | /* clamp to max that the registers can hold */ | |
175fded1 | 2636 | return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite)); |
158ae64f VS |
2637 | } |
2638 | ||
2639 | /* Calculate the maximum cursor plane watermark */ | |
2640 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2641 | int level, |
2642 | const struct intel_wm_config *config) | |
158ae64f VS |
2643 | { |
2644 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2645 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2646 | return 64; |
2647 | ||
2648 | /* otherwise just report max that registers can hold */ | |
175fded1 | 2649 | return ilk_cursor_wm_reg_max(to_i915(dev), level); |
158ae64f VS |
2650 | } |
2651 | ||
d34ff9c6 | 2652 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2653 | int level, |
2654 | const struct intel_wm_config *config, | |
2655 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2656 | struct ilk_wm_maximums *max) |
158ae64f | 2657 | { |
240264f4 VS |
2658 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2659 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2660 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
175fded1 | 2661 | max->fbc = ilk_fbc_wm_reg_max(to_i915(dev)); |
158ae64f VS |
2662 | } |
2663 | ||
175fded1 | 2664 | static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv, |
a3cb4048 VS |
2665 | int level, |
2666 | struct ilk_wm_maximums *max) | |
2667 | { | |
175fded1 TU |
2668 | max->pri = ilk_plane_wm_reg_max(dev_priv, level, false); |
2669 | max->spr = ilk_plane_wm_reg_max(dev_priv, level, true); | |
2670 | max->cur = ilk_cursor_wm_reg_max(dev_priv, level); | |
2671 | max->fbc = ilk_fbc_wm_reg_max(dev_priv); | |
a3cb4048 VS |
2672 | } |
2673 | ||
d9395655 | 2674 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2675 | const struct ilk_wm_maximums *max, |
d9395655 | 2676 | struct intel_wm_level *result) |
a9786a11 VS |
2677 | { |
2678 | bool ret; | |
2679 | ||
2680 | /* already determined to be invalid? */ | |
2681 | if (!result->enable) | |
2682 | return false; | |
2683 | ||
2684 | result->enable = result->pri_val <= max->pri && | |
2685 | result->spr_val <= max->spr && | |
2686 | result->cur_val <= max->cur; | |
2687 | ||
2688 | ret = result->enable; | |
2689 | ||
2690 | /* | |
2691 | * HACK until we can pre-compute everything, | |
2692 | * and thus fail gracefully if LP0 watermarks | |
2693 | * are exceeded... | |
2694 | */ | |
2695 | if (level == 0 && !result->enable) { | |
2696 | if (result->pri_val > max->pri) | |
2697 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2698 | level, result->pri_val, max->pri); | |
2699 | if (result->spr_val > max->spr) | |
2700 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2701 | level, result->spr_val, max->spr); | |
2702 | if (result->cur_val > max->cur) | |
2703 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2704 | level, result->cur_val, max->cur); | |
2705 | ||
2706 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2707 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2708 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2709 | result->enable = true; | |
2710 | } | |
2711 | ||
a9786a11 VS |
2712 | return ret; |
2713 | } | |
2714 | ||
d34ff9c6 | 2715 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
43d59eda | 2716 | const struct intel_crtc *intel_crtc, |
6f5ddd17 | 2717 | int level, |
7221fc33 | 2718 | struct intel_crtc_state *cstate, |
86c8bbbe MR |
2719 | struct intel_plane_state *pristate, |
2720 | struct intel_plane_state *sprstate, | |
2721 | struct intel_plane_state *curstate, | |
1fd527cc | 2722 | struct intel_wm_level *result) |
6f5ddd17 VS |
2723 | { |
2724 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2725 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2726 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2727 | ||
2728 | /* WM1+ latency values stored in 0.5us units */ | |
2729 | if (level > 0) { | |
2730 | pri_latency *= 5; | |
2731 | spr_latency *= 5; | |
2732 | cur_latency *= 5; | |
2733 | } | |
2734 | ||
e3bddded ML |
2735 | if (pristate) { |
2736 | result->pri_val = ilk_compute_pri_wm(cstate, pristate, | |
2737 | pri_latency, level); | |
2738 | result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val); | |
2739 | } | |
2740 | ||
2741 | if (sprstate) | |
2742 | result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency); | |
2743 | ||
2744 | if (curstate) | |
2745 | result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency); | |
2746 | ||
6f5ddd17 VS |
2747 | result->enable = true; |
2748 | } | |
2749 | ||
801bcfff | 2750 | static uint32_t |
532f7a7f | 2751 | hsw_compute_linetime_wm(const struct intel_crtc_state *cstate) |
1f8eeabf | 2752 | { |
532f7a7f VS |
2753 | const struct intel_atomic_state *intel_state = |
2754 | to_intel_atomic_state(cstate->base.state); | |
ee91a159 MR |
2755 | const struct drm_display_mode *adjusted_mode = |
2756 | &cstate->base.adjusted_mode; | |
85a02deb | 2757 | u32 linetime, ips_linetime; |
1f8eeabf | 2758 | |
ee91a159 MR |
2759 | if (!cstate->base.active) |
2760 | return 0; | |
2761 | if (WARN_ON(adjusted_mode->crtc_clock == 0)) | |
2762 | return 0; | |
bb0f4aab | 2763 | if (WARN_ON(intel_state->cdclk.logical.cdclk == 0)) |
801bcfff | 2764 | return 0; |
1011d8c4 | 2765 | |
1f8eeabf ED |
2766 | /* The WM are computed with base on how long it takes to fill a single |
2767 | * row at the given clock rate, multiplied by 8. | |
2768 | * */ | |
124abe07 VS |
2769 | linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, |
2770 | adjusted_mode->crtc_clock); | |
2771 | ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8, | |
bb0f4aab | 2772 | intel_state->cdclk.logical.cdclk); |
1f8eeabf | 2773 | |
801bcfff PZ |
2774 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2775 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2776 | } |
2777 | ||
bb726519 VS |
2778 | static void intel_read_wm_latency(struct drm_i915_private *dev_priv, |
2779 | uint16_t wm[8]) | |
12b134df | 2780 | { |
50682ee6 | 2781 | if (INTEL_GEN(dev_priv) >= 9) { |
2af30a5c | 2782 | uint32_t val; |
4f947386 | 2783 | int ret, i; |
5db94019 | 2784 | int level, max_level = ilk_wm_max_level(dev_priv); |
2af30a5c PB |
2785 | |
2786 | /* read the first set of memory latencies[0:3] */ | |
2787 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2788 | mutex_lock(&dev_priv->rps.hw_lock); | |
2789 | ret = sandybridge_pcode_read(dev_priv, | |
2790 | GEN9_PCODE_READ_MEM_LATENCY, | |
2791 | &val); | |
2792 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2793 | ||
2794 | if (ret) { | |
2795 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2796 | return; | |
2797 | } | |
2798 | ||
2799 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2800 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2801 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2802 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2803 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2804 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2805 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2806 | ||
2807 | /* read the second set of memory latencies[4:7] */ | |
2808 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2809 | mutex_lock(&dev_priv->rps.hw_lock); | |
2810 | ret = sandybridge_pcode_read(dev_priv, | |
2811 | GEN9_PCODE_READ_MEM_LATENCY, | |
2812 | &val); | |
2813 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2814 | if (ret) { | |
2815 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2816 | return; | |
2817 | } | |
2818 | ||
2819 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2820 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2821 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2822 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2823 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2824 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2825 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2826 | ||
0727e40a PZ |
2827 | /* |
2828 | * If a level n (n > 1) has a 0us latency, all levels m (m >= n) | |
2829 | * need to be disabled. We make sure to sanitize the values out | |
2830 | * of the punit to satisfy this requirement. | |
2831 | */ | |
2832 | for (level = 1; level <= max_level; level++) { | |
2833 | if (wm[level] == 0) { | |
2834 | for (i = level + 1; i <= max_level; i++) | |
2835 | wm[i] = 0; | |
2836 | break; | |
2837 | } | |
2838 | } | |
2839 | ||
367294be | 2840 | /* |
50682ee6 | 2841 | * WaWmMemoryReadLatency:skl+,glk |
6f97235b | 2842 | * |
367294be | 2843 | * punit doesn't take into account the read latency so we need |
0727e40a PZ |
2844 | * to add 2us to the various latency levels we retrieve from the |
2845 | * punit when level 0 response data us 0us. | |
367294be | 2846 | */ |
0727e40a PZ |
2847 | if (wm[0] == 0) { |
2848 | wm[0] += 2; | |
2849 | for (level = 1; level <= max_level; level++) { | |
2850 | if (wm[level] == 0) | |
2851 | break; | |
367294be | 2852 | wm[level] += 2; |
4f947386 | 2853 | } |
0727e40a PZ |
2854 | } |
2855 | ||
8652744b | 2856 | } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
12b134df VS |
2857 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2858 | ||
2859 | wm[0] = (sskpd >> 56) & 0xFF; | |
2860 | if (wm[0] == 0) | |
2861 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2862 | wm[1] = (sskpd >> 4) & 0xFF; |
2863 | wm[2] = (sskpd >> 12) & 0xFF; | |
2864 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2865 | wm[4] = (sskpd >> 32) & 0x1FF; | |
bb726519 | 2866 | } else if (INTEL_GEN(dev_priv) >= 6) { |
63cf9a13 VS |
2867 | uint32_t sskpd = I915_READ(MCH_SSKPD); |
2868 | ||
2869 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2870 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2871 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2872 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
bb726519 | 2873 | } else if (INTEL_GEN(dev_priv) >= 5) { |
3a88d0ac VS |
2874 | uint32_t mltr = I915_READ(MLTR_ILK); |
2875 | ||
2876 | /* ILK primary LP0 latency is 700 ns */ | |
2877 | wm[0] = 7; | |
2878 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2879 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
50682ee6 PZ |
2880 | } else { |
2881 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
12b134df VS |
2882 | } |
2883 | } | |
2884 | ||
5db94019 TU |
2885 | static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv, |
2886 | uint16_t wm[5]) | |
53615a5e VS |
2887 | { |
2888 | /* ILK sprite LP0 latency is 1300 ns */ | |
5db94019 | 2889 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2890 | wm[0] = 13; |
2891 | } | |
2892 | ||
fd6b8f43 TU |
2893 | static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv, |
2894 | uint16_t wm[5]) | |
53615a5e VS |
2895 | { |
2896 | /* ILK cursor LP0 latency is 1300 ns */ | |
fd6b8f43 | 2897 | if (IS_GEN5(dev_priv)) |
53615a5e VS |
2898 | wm[0] = 13; |
2899 | ||
2900 | /* WaDoubleCursorLP3Latency:ivb */ | |
fd6b8f43 | 2901 | if (IS_IVYBRIDGE(dev_priv)) |
53615a5e VS |
2902 | wm[3] *= 2; |
2903 | } | |
2904 | ||
5db94019 | 2905 | int ilk_wm_max_level(const struct drm_i915_private *dev_priv) |
26ec971e | 2906 | { |
26ec971e | 2907 | /* how many WM levels are we expecting */ |
8652744b | 2908 | if (INTEL_GEN(dev_priv) >= 9) |
2af30a5c | 2909 | return 7; |
8652744b | 2910 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ad0d6dc4 | 2911 | return 4; |
8652744b | 2912 | else if (INTEL_GEN(dev_priv) >= 6) |
ad0d6dc4 | 2913 | return 3; |
26ec971e | 2914 | else |
ad0d6dc4 VS |
2915 | return 2; |
2916 | } | |
7526ed79 | 2917 | |
5db94019 | 2918 | static void intel_print_wm_latency(struct drm_i915_private *dev_priv, |
ad0d6dc4 | 2919 | const char *name, |
2af30a5c | 2920 | const uint16_t wm[8]) |
ad0d6dc4 | 2921 | { |
5db94019 | 2922 | int level, max_level = ilk_wm_max_level(dev_priv); |
26ec971e VS |
2923 | |
2924 | for (level = 0; level <= max_level; level++) { | |
2925 | unsigned int latency = wm[level]; | |
2926 | ||
2927 | if (latency == 0) { | |
2928 | DRM_ERROR("%s WM%d latency not provided\n", | |
2929 | name, level); | |
2930 | continue; | |
2931 | } | |
2932 | ||
2af30a5c PB |
2933 | /* |
2934 | * - latencies are in us on gen9. | |
2935 | * - before then, WM1+ latency values are in 0.5us units | |
2936 | */ | |
dfc267ab | 2937 | if (INTEL_GEN(dev_priv) >= 9) |
2af30a5c PB |
2938 | latency *= 10; |
2939 | else if (level > 0) | |
26ec971e VS |
2940 | latency *= 5; |
2941 | ||
2942 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2943 | name, level, wm[level], | |
2944 | latency / 10, latency % 10); | |
2945 | } | |
2946 | } | |
2947 | ||
e95a2f75 VS |
2948 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2949 | uint16_t wm[5], uint16_t min) | |
2950 | { | |
5db94019 | 2951 | int level, max_level = ilk_wm_max_level(dev_priv); |
e95a2f75 VS |
2952 | |
2953 | if (wm[0] >= min) | |
2954 | return false; | |
2955 | ||
2956 | wm[0] = max(wm[0], min); | |
2957 | for (level = 1; level <= max_level; level++) | |
2958 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2959 | ||
2960 | return true; | |
2961 | } | |
2962 | ||
bb726519 | 2963 | static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv) |
e95a2f75 | 2964 | { |
e95a2f75 VS |
2965 | bool changed; |
2966 | ||
2967 | /* | |
2968 | * The BIOS provided WM memory latency values are often | |
2969 | * inadequate for high resolution displays. Adjust them. | |
2970 | */ | |
2971 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2972 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2973 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2974 | ||
2975 | if (!changed) | |
2976 | return; | |
2977 | ||
2978 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
5db94019 TU |
2979 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2980 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2981 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2982 | } |
2983 | ||
bb726519 | 2984 | static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv) |
53615a5e | 2985 | { |
bb726519 | 2986 | intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency); |
53615a5e VS |
2987 | |
2988 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2989 | sizeof(dev_priv->wm.pri_latency)); | |
2990 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2991 | sizeof(dev_priv->wm.pri_latency)); | |
2992 | ||
5db94019 | 2993 | intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency); |
fd6b8f43 | 2994 | intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency); |
26ec971e | 2995 | |
5db94019 TU |
2996 | intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency); |
2997 | intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency); | |
2998 | intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 | 2999 | |
5db94019 | 3000 | if (IS_GEN6(dev_priv)) |
bb726519 | 3001 | snb_wm_latency_quirk(dev_priv); |
53615a5e VS |
3002 | } |
3003 | ||
bb726519 | 3004 | static void skl_setup_wm_latency(struct drm_i915_private *dev_priv) |
2af30a5c | 3005 | { |
bb726519 | 3006 | intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency); |
5db94019 | 3007 | intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency); |
2af30a5c PB |
3008 | } |
3009 | ||
ed4a6a7c MR |
3010 | static bool ilk_validate_pipe_wm(struct drm_device *dev, |
3011 | struct intel_pipe_wm *pipe_wm) | |
3012 | { | |
3013 | /* LP0 watermark maximums depend on this pipe alone */ | |
3014 | const struct intel_wm_config config = { | |
3015 | .num_pipes_active = 1, | |
3016 | .sprites_enabled = pipe_wm->sprites_enabled, | |
3017 | .sprites_scaled = pipe_wm->sprites_scaled, | |
3018 | }; | |
3019 | struct ilk_wm_maximums max; | |
3020 | ||
3021 | /* LP0 watermarks always use 1/2 DDB partitioning */ | |
3022 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
3023 | ||
3024 | /* At least LP0 must be valid */ | |
3025 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) { | |
3026 | DRM_DEBUG_KMS("LP0 watermark invalid\n"); | |
3027 | return false; | |
3028 | } | |
3029 | ||
3030 | return true; | |
3031 | } | |
3032 | ||
0b2ae6d7 | 3033 | /* Compute new watermarks for the pipe */ |
e3bddded | 3034 | static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate) |
0b2ae6d7 | 3035 | { |
e3bddded ML |
3036 | struct drm_atomic_state *state = cstate->base.state; |
3037 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
86c8bbbe | 3038 | struct intel_pipe_wm *pipe_wm; |
e3bddded | 3039 | struct drm_device *dev = state->dev; |
fac5e23e | 3040 | const struct drm_i915_private *dev_priv = to_i915(dev); |
43d59eda | 3041 | struct intel_plane *intel_plane; |
86c8bbbe | 3042 | struct intel_plane_state *pristate = NULL; |
43d59eda | 3043 | struct intel_plane_state *sprstate = NULL; |
86c8bbbe | 3044 | struct intel_plane_state *curstate = NULL; |
5db94019 | 3045 | int level, max_level = ilk_wm_max_level(dev_priv), usable_level; |
820c1980 | 3046 | struct ilk_wm_maximums max; |
0b2ae6d7 | 3047 | |
e8f1f02e | 3048 | pipe_wm = &cstate->wm.ilk.optimal; |
86c8bbbe | 3049 | |
43d59eda | 3050 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
e3bddded ML |
3051 | struct intel_plane_state *ps; |
3052 | ||
3053 | ps = intel_atomic_get_existing_plane_state(state, | |
3054 | intel_plane); | |
3055 | if (!ps) | |
3056 | continue; | |
86c8bbbe MR |
3057 | |
3058 | if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY) | |
e3bddded | 3059 | pristate = ps; |
86c8bbbe | 3060 | else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY) |
e3bddded | 3061 | sprstate = ps; |
86c8bbbe | 3062 | else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR) |
e3bddded | 3063 | curstate = ps; |
43d59eda MR |
3064 | } |
3065 | ||
ed4a6a7c | 3066 | pipe_wm->pipe_enabled = cstate->base.active; |
e3bddded | 3067 | if (sprstate) { |
936e71e3 VS |
3068 | pipe_wm->sprites_enabled = sprstate->base.visible; |
3069 | pipe_wm->sprites_scaled = sprstate->base.visible && | |
3070 | (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 || | |
3071 | drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16); | |
e3bddded ML |
3072 | } |
3073 | ||
d81f04c5 ML |
3074 | usable_level = max_level; |
3075 | ||
7b39a0b7 | 3076 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
175fded1 | 3077 | if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled) |
d81f04c5 | 3078 | usable_level = 1; |
7b39a0b7 VS |
3079 | |
3080 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
ed4a6a7c | 3081 | if (pipe_wm->sprites_scaled) |
d81f04c5 | 3082 | usable_level = 0; |
7b39a0b7 | 3083 | |
86c8bbbe | 3084 | ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate, |
71f0a626 ML |
3085 | pristate, sprstate, curstate, &pipe_wm->raw_wm[0]); |
3086 | ||
3087 | memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm)); | |
3088 | pipe_wm->wm[0] = pipe_wm->raw_wm[0]; | |
0b2ae6d7 | 3089 | |
8652744b | 3090 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
532f7a7f | 3091 | pipe_wm->linetime = hsw_compute_linetime_wm(cstate); |
0b2ae6d7 | 3092 | |
ed4a6a7c | 3093 | if (!ilk_validate_pipe_wm(dev, pipe_wm)) |
1a426d61 | 3094 | return -EINVAL; |
a3cb4048 | 3095 | |
175fded1 | 3096 | ilk_compute_wm_reg_maximums(dev_priv, 1, &max); |
a3cb4048 VS |
3097 | |
3098 | for (level = 1; level <= max_level; level++) { | |
71f0a626 | 3099 | struct intel_wm_level *wm = &pipe_wm->raw_wm[level]; |
a3cb4048 | 3100 | |
86c8bbbe | 3101 | ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate, |
d81f04c5 | 3102 | pristate, sprstate, curstate, wm); |
a3cb4048 VS |
3103 | |
3104 | /* | |
3105 | * Disable any watermark level that exceeds the | |
3106 | * register maximums since such watermarks are | |
3107 | * always invalid. | |
3108 | */ | |
71f0a626 ML |
3109 | if (level > usable_level) |
3110 | continue; | |
3111 | ||
3112 | if (ilk_validate_wm_level(level, &max, wm)) | |
3113 | pipe_wm->wm[level] = *wm; | |
3114 | else | |
d81f04c5 | 3115 | usable_level = level; |
a3cb4048 VS |
3116 | } |
3117 | ||
86c8bbbe | 3118 | return 0; |
0b2ae6d7 VS |
3119 | } |
3120 | ||
ed4a6a7c MR |
3121 | /* |
3122 | * Build a set of 'intermediate' watermark values that satisfy both the old | |
3123 | * state and the new state. These can be programmed to the hardware | |
3124 | * immediately. | |
3125 | */ | |
3126 | static int ilk_compute_intermediate_wm(struct drm_device *dev, | |
3127 | struct intel_crtc *intel_crtc, | |
3128 | struct intel_crtc_state *newstate) | |
3129 | { | |
e8f1f02e | 3130 | struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate; |
ed4a6a7c | 3131 | struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk; |
5db94019 | 3132 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
ed4a6a7c MR |
3133 | |
3134 | /* | |
3135 | * Start with the final, target watermarks, then combine with the | |
3136 | * currently active watermarks to get values that are safe both before | |
3137 | * and after the vblank. | |
3138 | */ | |
e8f1f02e | 3139 | *a = newstate->wm.ilk.optimal; |
ed4a6a7c MR |
3140 | a->pipe_enabled |= b->pipe_enabled; |
3141 | a->sprites_enabled |= b->sprites_enabled; | |
3142 | a->sprites_scaled |= b->sprites_scaled; | |
3143 | ||
3144 | for (level = 0; level <= max_level; level++) { | |
3145 | struct intel_wm_level *a_wm = &a->wm[level]; | |
3146 | const struct intel_wm_level *b_wm = &b->wm[level]; | |
3147 | ||
3148 | a_wm->enable &= b_wm->enable; | |
3149 | a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val); | |
3150 | a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val); | |
3151 | a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val); | |
3152 | a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val); | |
3153 | } | |
3154 | ||
3155 | /* | |
3156 | * We need to make sure that these merged watermark values are | |
3157 | * actually a valid configuration themselves. If they're not, | |
3158 | * there's no safe way to transition from the old state to | |
3159 | * the new state, so we need to fail the atomic transaction. | |
3160 | */ | |
3161 | if (!ilk_validate_pipe_wm(dev, a)) | |
3162 | return -EINVAL; | |
3163 | ||
3164 | /* | |
3165 | * If our intermediate WM are identical to the final WM, then we can | |
3166 | * omit the post-vblank programming; only update if it's different. | |
3167 | */ | |
5eeb798b VS |
3168 | if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) != 0) |
3169 | newstate->wm.need_postvbl_update = true; | |
ed4a6a7c MR |
3170 | |
3171 | return 0; | |
3172 | } | |
3173 | ||
0b2ae6d7 VS |
3174 | /* |
3175 | * Merge the watermarks from all active pipes for a specific level. | |
3176 | */ | |
3177 | static void ilk_merge_wm_level(struct drm_device *dev, | |
3178 | int level, | |
3179 | struct intel_wm_level *ret_wm) | |
3180 | { | |
3181 | const struct intel_crtc *intel_crtc; | |
3182 | ||
d52fea5b VS |
3183 | ret_wm->enable = true; |
3184 | ||
d3fcc808 | 3185 | for_each_intel_crtc(dev, intel_crtc) { |
ed4a6a7c | 3186 | const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk; |
fe392efd VS |
3187 | const struct intel_wm_level *wm = &active->wm[level]; |
3188 | ||
3189 | if (!active->pipe_enabled) | |
3190 | continue; | |
0b2ae6d7 | 3191 | |
d52fea5b VS |
3192 | /* |
3193 | * The watermark values may have been used in the past, | |
3194 | * so we must maintain them in the registers for some | |
3195 | * time even if the level is now disabled. | |
3196 | */ | |
0b2ae6d7 | 3197 | if (!wm->enable) |
d52fea5b | 3198 | ret_wm->enable = false; |
0b2ae6d7 VS |
3199 | |
3200 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
3201 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
3202 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
3203 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
3204 | } | |
0b2ae6d7 VS |
3205 | } |
3206 | ||
3207 | /* | |
3208 | * Merge all low power watermarks for all active pipes. | |
3209 | */ | |
3210 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 3211 | const struct intel_wm_config *config, |
820c1980 | 3212 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
3213 | struct intel_pipe_wm *merged) |
3214 | { | |
fac5e23e | 3215 | struct drm_i915_private *dev_priv = to_i915(dev); |
5db94019 | 3216 | int level, max_level = ilk_wm_max_level(dev_priv); |
d52fea5b | 3217 | int last_enabled_level = max_level; |
0b2ae6d7 | 3218 | |
0ba22e26 | 3219 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
fd6b8f43 | 3220 | if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) && |
0ba22e26 | 3221 | config->num_pipes_active > 1) |
1204d5ba | 3222 | last_enabled_level = 0; |
0ba22e26 | 3223 | |
6c8b6c28 | 3224 | /* ILK: FBC WM must be disabled always */ |
175fded1 | 3225 | merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6; |
0b2ae6d7 VS |
3226 | |
3227 | /* merge each WM1+ level */ | |
3228 | for (level = 1; level <= max_level; level++) { | |
3229 | struct intel_wm_level *wm = &merged->wm[level]; | |
3230 | ||
3231 | ilk_merge_wm_level(dev, level, wm); | |
3232 | ||
d52fea5b VS |
3233 | if (level > last_enabled_level) |
3234 | wm->enable = false; | |
3235 | else if (!ilk_validate_wm_level(level, max, wm)) | |
3236 | /* make sure all following levels get disabled */ | |
3237 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
3238 | |
3239 | /* | |
3240 | * The spec says it is preferred to disable | |
3241 | * FBC WMs instead of disabling a WM level. | |
3242 | */ | |
3243 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
3244 | if (wm->enable) |
3245 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
3246 | wm->fbc_val = 0; |
3247 | } | |
3248 | } | |
6c8b6c28 VS |
3249 | |
3250 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
3251 | /* | |
3252 | * FIXME this is racy. FBC might get enabled later. | |
3253 | * What we should check here is whether FBC can be | |
3254 | * enabled sometime later. | |
3255 | */ | |
5db94019 | 3256 | if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled && |
0e631adc | 3257 | intel_fbc_is_active(dev_priv)) { |
6c8b6c28 VS |
3258 | for (level = 2; level <= max_level; level++) { |
3259 | struct intel_wm_level *wm = &merged->wm[level]; | |
3260 | ||
3261 | wm->enable = false; | |
3262 | } | |
3263 | } | |
0b2ae6d7 VS |
3264 | } |
3265 | ||
b380ca3c VS |
3266 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
3267 | { | |
3268 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
3269 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
3270 | } | |
3271 | ||
a68d68ee VS |
3272 | /* The value we need to program into the WM_LPx latency field */ |
3273 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
3274 | { | |
fac5e23e | 3275 | struct drm_i915_private *dev_priv = to_i915(dev); |
a68d68ee | 3276 | |
8652744b | 3277 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
a68d68ee VS |
3278 | return 2 * level; |
3279 | else | |
3280 | return dev_priv->wm.pri_latency[level]; | |
3281 | } | |
3282 | ||
820c1980 | 3283 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 3284 | const struct intel_pipe_wm *merged, |
609cedef | 3285 | enum intel_ddb_partitioning partitioning, |
820c1980 | 3286 | struct ilk_wm_values *results) |
801bcfff | 3287 | { |
175fded1 | 3288 | struct drm_i915_private *dev_priv = to_i915(dev); |
0b2ae6d7 VS |
3289 | struct intel_crtc *intel_crtc; |
3290 | int level, wm_lp; | |
cca32e9a | 3291 | |
0362c781 | 3292 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 3293 | results->partitioning = partitioning; |
cca32e9a | 3294 | |
0b2ae6d7 | 3295 | /* LP1+ register values */ |
cca32e9a | 3296 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 3297 | const struct intel_wm_level *r; |
801bcfff | 3298 | |
b380ca3c | 3299 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 3300 | |
0362c781 | 3301 | r = &merged->wm[level]; |
cca32e9a | 3302 | |
d52fea5b VS |
3303 | /* |
3304 | * Maintain the watermark values even if the level is | |
3305 | * disabled. Doing otherwise could cause underruns. | |
3306 | */ | |
3307 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 3308 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
3309 | (r->pri_val << WM1_LP_SR_SHIFT) | |
3310 | r->cur_val; | |
3311 | ||
d52fea5b VS |
3312 | if (r->enable) |
3313 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
3314 | ||
175fded1 | 3315 | if (INTEL_GEN(dev_priv) >= 8) |
416f4727 VS |
3316 | results->wm_lp[wm_lp - 1] |= |
3317 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
3318 | else | |
3319 | results->wm_lp[wm_lp - 1] |= | |
3320 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
3321 | ||
d52fea5b VS |
3322 | /* |
3323 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
3324 | * level is disabled. Doing otherwise could cause underruns. | |
3325 | */ | |
175fded1 | 3326 | if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) { |
6cef2b8a VS |
3327 | WARN_ON(wm_lp != 1); |
3328 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
3329 | } else | |
3330 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 3331 | } |
801bcfff | 3332 | |
0b2ae6d7 | 3333 | /* LP0 register values */ |
d3fcc808 | 3334 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 | 3335 | enum pipe pipe = intel_crtc->pipe; |
ed4a6a7c MR |
3336 | const struct intel_wm_level *r = |
3337 | &intel_crtc->wm.active.ilk.wm[0]; | |
0b2ae6d7 VS |
3338 | |
3339 | if (WARN_ON(!r->enable)) | |
3340 | continue; | |
3341 | ||
ed4a6a7c | 3342 | results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime; |
1011d8c4 | 3343 | |
0b2ae6d7 VS |
3344 | results->wm_pipe[pipe] = |
3345 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
3346 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
3347 | r->cur_val; | |
801bcfff PZ |
3348 | } |
3349 | } | |
3350 | ||
861f3389 PZ |
3351 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
3352 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 3353 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
3354 | struct intel_pipe_wm *r1, |
3355 | struct intel_pipe_wm *r2) | |
861f3389 | 3356 | { |
5db94019 | 3357 | int level, max_level = ilk_wm_max_level(to_i915(dev)); |
198a1e9b | 3358 | int level1 = 0, level2 = 0; |
861f3389 | 3359 | |
198a1e9b VS |
3360 | for (level = 1; level <= max_level; level++) { |
3361 | if (r1->wm[level].enable) | |
3362 | level1 = level; | |
3363 | if (r2->wm[level].enable) | |
3364 | level2 = level; | |
861f3389 PZ |
3365 | } |
3366 | ||
198a1e9b VS |
3367 | if (level1 == level2) { |
3368 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
3369 | return r2; |
3370 | else | |
3371 | return r1; | |
198a1e9b | 3372 | } else if (level1 > level2) { |
861f3389 PZ |
3373 | return r1; |
3374 | } else { | |
3375 | return r2; | |
3376 | } | |
3377 | } | |
3378 | ||
49a687c4 VS |
3379 | /* dirty bits used to track which watermarks need changes */ |
3380 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
3381 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
3382 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
3383 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
3384 | #define WM_DIRTY_FBC (1 << 24) | |
3385 | #define WM_DIRTY_DDB (1 << 25) | |
3386 | ||
055e393f | 3387 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
3388 | const struct ilk_wm_values *old, |
3389 | const struct ilk_wm_values *new) | |
49a687c4 VS |
3390 | { |
3391 | unsigned int dirty = 0; | |
3392 | enum pipe pipe; | |
3393 | int wm_lp; | |
3394 | ||
055e393f | 3395 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
3396 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
3397 | dirty |= WM_DIRTY_LINETIME(pipe); | |
3398 | /* Must disable LP1+ watermarks too */ | |
3399 | dirty |= WM_DIRTY_LP_ALL; | |
3400 | } | |
3401 | ||
3402 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
3403 | dirty |= WM_DIRTY_PIPE(pipe); | |
3404 | /* Must disable LP1+ watermarks too */ | |
3405 | dirty |= WM_DIRTY_LP_ALL; | |
3406 | } | |
3407 | } | |
3408 | ||
3409 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
3410 | dirty |= WM_DIRTY_FBC; | |
3411 | /* Must disable LP1+ watermarks too */ | |
3412 | dirty |= WM_DIRTY_LP_ALL; | |
3413 | } | |
3414 | ||
3415 | if (old->partitioning != new->partitioning) { | |
3416 | dirty |= WM_DIRTY_DDB; | |
3417 | /* Must disable LP1+ watermarks too */ | |
3418 | dirty |= WM_DIRTY_LP_ALL; | |
3419 | } | |
3420 | ||
3421 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
3422 | if (dirty & WM_DIRTY_LP_ALL) | |
3423 | return dirty; | |
3424 | ||
3425 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
3426 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
3427 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
3428 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
3429 | break; | |
3430 | } | |
3431 | ||
3432 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
3433 | for (; wm_lp <= 3; wm_lp++) | |
3434 | dirty |= WM_DIRTY_LP(wm_lp); | |
3435 | ||
3436 | return dirty; | |
3437 | } | |
3438 | ||
8553c18e VS |
3439 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
3440 | unsigned int dirty) | |
801bcfff | 3441 | { |
820c1980 | 3442 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 3443 | bool changed = false; |
801bcfff | 3444 | |
facd619b VS |
3445 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
3446 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
3447 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 3448 | changed = true; |
facd619b VS |
3449 | } |
3450 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
3451 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
3452 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 3453 | changed = true; |
facd619b VS |
3454 | } |
3455 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
3456 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
3457 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 3458 | changed = true; |
facd619b | 3459 | } |
801bcfff | 3460 | |
facd619b VS |
3461 | /* |
3462 | * Don't touch WM1S_LP_EN here. | |
3463 | * Doing so could cause underruns. | |
3464 | */ | |
6cef2b8a | 3465 | |
8553c18e VS |
3466 | return changed; |
3467 | } | |
3468 | ||
3469 | /* | |
3470 | * The spec says we shouldn't write when we don't need, because every write | |
3471 | * causes WMs to be re-evaluated, expending some power. | |
3472 | */ | |
820c1980 ID |
3473 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
3474 | struct ilk_wm_values *results) | |
8553c18e | 3475 | { |
820c1980 | 3476 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
3477 | unsigned int dirty; |
3478 | uint32_t val; | |
3479 | ||
055e393f | 3480 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
3481 | if (!dirty) |
3482 | return; | |
3483 | ||
3484 | _ilk_disable_lp_wm(dev_priv, dirty); | |
3485 | ||
49a687c4 | 3486 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 3487 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 3488 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 3489 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 3490 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
3491 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
3492 | ||
49a687c4 | 3493 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 3494 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 3495 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 3496 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 3497 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
3498 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
3499 | ||
49a687c4 | 3500 | if (dirty & WM_DIRTY_DDB) { |
8652744b | 3501 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) { |
ac9545fd VS |
3502 | val = I915_READ(WM_MISC); |
3503 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3504 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
3505 | else | |
3506 | val |= WM_MISC_DATA_PARTITION_5_6; | |
3507 | I915_WRITE(WM_MISC, val); | |
3508 | } else { | |
3509 | val = I915_READ(DISP_ARB_CTL2); | |
3510 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
3511 | val &= ~DISP_DATA_PARTITION_5_6; | |
3512 | else | |
3513 | val |= DISP_DATA_PARTITION_5_6; | |
3514 | I915_WRITE(DISP_ARB_CTL2, val); | |
3515 | } | |
1011d8c4 PZ |
3516 | } |
3517 | ||
49a687c4 | 3518 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
3519 | val = I915_READ(DISP_ARB_CTL); |
3520 | if (results->enable_fbc_wm) | |
3521 | val &= ~DISP_FBC_WM_DIS; | |
3522 | else | |
3523 | val |= DISP_FBC_WM_DIS; | |
3524 | I915_WRITE(DISP_ARB_CTL, val); | |
3525 | } | |
3526 | ||
954911eb ID |
3527 | if (dirty & WM_DIRTY_LP(1) && |
3528 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
3529 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
3530 | ||
175fded1 | 3531 | if (INTEL_GEN(dev_priv) >= 7) { |
6cef2b8a VS |
3532 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
3533 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
3534 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
3535 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
3536 | } | |
801bcfff | 3537 | |
facd619b | 3538 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 3539 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 3540 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 3541 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 3542 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 3543 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
3544 | |
3545 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
3546 | } |
3547 | ||
ed4a6a7c | 3548 | bool ilk_disable_lp_wm(struct drm_device *dev) |
8553c18e | 3549 | { |
fac5e23e | 3550 | struct drm_i915_private *dev_priv = to_i915(dev); |
8553c18e VS |
3551 | |
3552 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
3553 | } | |
3554 | ||
ee3d532f PZ |
3555 | /* |
3556 | * FIXME: We still don't have the proper code detect if we need to apply the WA, | |
3557 | * so assume we'll always need it in order to avoid underruns. | |
3558 | */ | |
3559 | static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state) | |
3560 | { | |
3561 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
3562 | ||
b976dc53 | 3563 | if (IS_GEN9_BC(dev_priv) || IS_BROXTON(dev_priv)) |
ee3d532f PZ |
3564 | return true; |
3565 | ||
3566 | return false; | |
3567 | } | |
3568 | ||
56feca91 PZ |
3569 | static bool |
3570 | intel_has_sagv(struct drm_i915_private *dev_priv) | |
3571 | { | |
01971819 RV |
3572 | if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv) || |
3573 | IS_CANNONLAKE(dev_priv)) | |
6e3100ec PZ |
3574 | return true; |
3575 | ||
3576 | if (IS_SKYLAKE(dev_priv) && | |
3577 | dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED) | |
3578 | return true; | |
3579 | ||
3580 | return false; | |
56feca91 PZ |
3581 | } |
3582 | ||
656d1b89 L |
3583 | /* |
3584 | * SAGV dynamically adjusts the system agent voltage and clock frequencies | |
3585 | * depending on power and performance requirements. The display engine access | |
3586 | * to system memory is blocked during the adjustment time. Because of the | |
3587 | * blocking time, having this enabled can cause full system hangs and/or pipe | |
3588 | * underruns if we don't meet all of the following requirements: | |
3589 | * | |
3590 | * - <= 1 pipe enabled | |
3591 | * - All planes can enable watermarks for latencies >= SAGV engine block time | |
3592 | * - We're not using an interlaced display configuration | |
3593 | */ | |
3594 | int | |
16dcdc4e | 3595 | intel_enable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 L |
3596 | { |
3597 | int ret; | |
3598 | ||
56feca91 PZ |
3599 | if (!intel_has_sagv(dev_priv)) |
3600 | return 0; | |
3601 | ||
3602 | if (dev_priv->sagv_status == I915_SAGV_ENABLED) | |
656d1b89 L |
3603 | return 0; |
3604 | ||
3605 | DRM_DEBUG_KMS("Enabling the SAGV\n"); | |
3606 | mutex_lock(&dev_priv->rps.hw_lock); | |
3607 | ||
3608 | ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL, | |
3609 | GEN9_SAGV_ENABLE); | |
3610 | ||
3611 | /* We don't need to wait for the SAGV when enabling */ | |
3612 | mutex_unlock(&dev_priv->rps.hw_lock); | |
3613 | ||
3614 | /* | |
3615 | * Some skl systems, pre-release machines in particular, | |
3616 | * don't actually have an SAGV. | |
3617 | */ | |
6e3100ec | 3618 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3619 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3620 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 L |
3621 | return 0; |
3622 | } else if (ret < 0) { | |
3623 | DRM_ERROR("Failed to enable the SAGV\n"); | |
3624 | return ret; | |
3625 | } | |
3626 | ||
16dcdc4e | 3627 | dev_priv->sagv_status = I915_SAGV_ENABLED; |
656d1b89 L |
3628 | return 0; |
3629 | } | |
3630 | ||
656d1b89 | 3631 | int |
16dcdc4e | 3632 | intel_disable_sagv(struct drm_i915_private *dev_priv) |
656d1b89 | 3633 | { |
b3b8e999 | 3634 | int ret; |
656d1b89 | 3635 | |
56feca91 PZ |
3636 | if (!intel_has_sagv(dev_priv)) |
3637 | return 0; | |
3638 | ||
3639 | if (dev_priv->sagv_status == I915_SAGV_DISABLED) | |
656d1b89 L |
3640 | return 0; |
3641 | ||
3642 | DRM_DEBUG_KMS("Disabling the SAGV\n"); | |
3643 | mutex_lock(&dev_priv->rps.hw_lock); | |
3644 | ||
3645 | /* bspec says to keep retrying for at least 1 ms */ | |
b3b8e999 ID |
3646 | ret = skl_pcode_request(dev_priv, GEN9_PCODE_SAGV_CONTROL, |
3647 | GEN9_SAGV_DISABLE, | |
3648 | GEN9_SAGV_IS_DISABLED, GEN9_SAGV_IS_DISABLED, | |
3649 | 1); | |
656d1b89 L |
3650 | mutex_unlock(&dev_priv->rps.hw_lock); |
3651 | ||
656d1b89 L |
3652 | /* |
3653 | * Some skl systems, pre-release machines in particular, | |
3654 | * don't actually have an SAGV. | |
3655 | */ | |
b3b8e999 | 3656 | if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) { |
656d1b89 | 3657 | DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n"); |
16dcdc4e | 3658 | dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED; |
656d1b89 | 3659 | return 0; |
b3b8e999 ID |
3660 | } else if (ret < 0) { |
3661 | DRM_ERROR("Failed to disable the SAGV (%d)\n", ret); | |
3662 | return ret; | |
656d1b89 L |
3663 | } |
3664 | ||
16dcdc4e | 3665 | dev_priv->sagv_status = I915_SAGV_DISABLED; |
656d1b89 L |
3666 | return 0; |
3667 | } | |
3668 | ||
16dcdc4e | 3669 | bool intel_can_enable_sagv(struct drm_atomic_state *state) |
656d1b89 L |
3670 | { |
3671 | struct drm_device *dev = state->dev; | |
3672 | struct drm_i915_private *dev_priv = to_i915(dev); | |
3673 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
ee3d532f PZ |
3674 | struct intel_crtc *crtc; |
3675 | struct intel_plane *plane; | |
d8c0fafc | 3676 | struct intel_crtc_state *cstate; |
656d1b89 | 3677 | enum pipe pipe; |
d8c0fafc | 3678 | int level, latency; |
fdd11c2b | 3679 | int sagv_block_time_us = IS_GEN9(dev_priv) ? 30 : 20; |
656d1b89 | 3680 | |
56feca91 PZ |
3681 | if (!intel_has_sagv(dev_priv)) |
3682 | return false; | |
3683 | ||
656d1b89 | 3684 | /* |
fdd11c2b | 3685 | * SKL+ workaround: bspec recommends we disable the SAGV when we have |
656d1b89 L |
3686 | * more then one pipe enabled |
3687 | * | |
3688 | * If there are no active CRTCs, no additional checks need be performed | |
3689 | */ | |
3690 | if (hweight32(intel_state->active_crtcs) == 0) | |
3691 | return true; | |
3692 | else if (hweight32(intel_state->active_crtcs) > 1) | |
3693 | return false; | |
3694 | ||
3695 | /* Since we're now guaranteed to only have one active CRTC... */ | |
3696 | pipe = ffs(intel_state->active_crtcs) - 1; | |
98187836 | 3697 | crtc = intel_get_crtc_for_pipe(dev_priv, pipe); |
d8c0fafc | 3698 | cstate = to_intel_crtc_state(crtc->base.state); |
656d1b89 | 3699 | |
c89cadd5 | 3700 | if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE) |
656d1b89 L |
3701 | return false; |
3702 | ||
ee3d532f | 3703 | for_each_intel_plane_on_crtc(dev, crtc, plane) { |
d5cdfdf5 VS |
3704 | struct skl_plane_wm *wm = |
3705 | &cstate->wm.skl.optimal.planes[plane->id]; | |
ee3d532f | 3706 | |
656d1b89 | 3707 | /* Skip this plane if it's not enabled */ |
d8c0fafc | 3708 | if (!wm->wm[0].plane_en) |
656d1b89 L |
3709 | continue; |
3710 | ||
3711 | /* Find the highest enabled wm level for this plane */ | |
5db94019 | 3712 | for (level = ilk_wm_max_level(dev_priv); |
d8c0fafc | 3713 | !wm->wm[level].plane_en; --level) |
656d1b89 L |
3714 | { } |
3715 | ||
ee3d532f PZ |
3716 | latency = dev_priv->wm.skl_latency[level]; |
3717 | ||
3718 | if (skl_needs_memory_bw_wa(intel_state) && | |
bae781b2 | 3719 | plane->base.state->fb->modifier == |
ee3d532f PZ |
3720 | I915_FORMAT_MOD_X_TILED) |
3721 | latency += 15; | |
3722 | ||
656d1b89 | 3723 | /* |
fdd11c2b PZ |
3724 | * If any of the planes on this pipe don't enable wm levels that |
3725 | * incur memory latencies higher than sagv_block_time_us we | |
3726 | * can't enable the SAGV. | |
656d1b89 | 3727 | */ |
fdd11c2b | 3728 | if (latency < sagv_block_time_us) |
656d1b89 L |
3729 | return false; |
3730 | } | |
3731 | ||
3732 | return true; | |
3733 | } | |
3734 | ||
b9cec075 DL |
3735 | static void |
3736 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
024c9045 | 3737 | const struct intel_crtc_state *cstate, |
c107acfe MR |
3738 | struct skl_ddb_entry *alloc, /* out */ |
3739 | int *num_active /* out */) | |
b9cec075 | 3740 | { |
c107acfe MR |
3741 | struct drm_atomic_state *state = cstate->base.state; |
3742 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
3743 | struct drm_i915_private *dev_priv = to_i915(dev); | |
024c9045 | 3744 | struct drm_crtc *for_crtc = cstate->base.crtc; |
b9cec075 DL |
3745 | unsigned int pipe_size, ddb_size; |
3746 | int nth_active_pipe; | |
c107acfe | 3747 | |
a6d3460e | 3748 | if (WARN_ON(!state) || !cstate->base.active) { |
b9cec075 DL |
3749 | alloc->start = 0; |
3750 | alloc->end = 0; | |
a6d3460e | 3751 | *num_active = hweight32(dev_priv->active_crtcs); |
b9cec075 DL |
3752 | return; |
3753 | } | |
3754 | ||
a6d3460e MR |
3755 | if (intel_state->active_pipe_changes) |
3756 | *num_active = hweight32(intel_state->active_crtcs); | |
3757 | else | |
3758 | *num_active = hweight32(dev_priv->active_crtcs); | |
3759 | ||
6f3fff60 D |
3760 | ddb_size = INTEL_INFO(dev_priv)->ddb_size; |
3761 | WARN_ON(ddb_size == 0); | |
b9cec075 DL |
3762 | |
3763 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
3764 | ||
c107acfe | 3765 | /* |
a6d3460e MR |
3766 | * If the state doesn't change the active CRTC's, then there's |
3767 | * no need to recalculate; the existing pipe allocation limits | |
3768 | * should remain unchanged. Note that we're safe from racing | |
3769 | * commits since any racing commit that changes the active CRTC | |
3770 | * list would need to grab _all_ crtc locks, including the one | |
3771 | * we currently hold. | |
c107acfe | 3772 | */ |
a6d3460e | 3773 | if (!intel_state->active_pipe_changes) { |
512b5527 ML |
3774 | /* |
3775 | * alloc may be cleared by clear_intel_crtc_state, | |
3776 | * copy from old state to be sure | |
3777 | */ | |
3778 | *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb; | |
a6d3460e | 3779 | return; |
c107acfe | 3780 | } |
a6d3460e MR |
3781 | |
3782 | nth_active_pipe = hweight32(intel_state->active_crtcs & | |
3783 | (drm_crtc_mask(for_crtc) - 1)); | |
3784 | pipe_size = ddb_size / hweight32(intel_state->active_crtcs); | |
3785 | alloc->start = nth_active_pipe * ddb_size / *num_active; | |
3786 | alloc->end = alloc->start + pipe_size; | |
b9cec075 DL |
3787 | } |
3788 | ||
c107acfe | 3789 | static unsigned int skl_cursor_allocation(int num_active) |
b9cec075 | 3790 | { |
c107acfe | 3791 | if (num_active == 1) |
b9cec075 DL |
3792 | return 32; |
3793 | ||
3794 | return 8; | |
3795 | } | |
3796 | ||
a269c583 DL |
3797 | static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg) |
3798 | { | |
3799 | entry->start = reg & 0x3ff; | |
3800 | entry->end = (reg >> 16) & 0x3ff; | |
16160e3d DL |
3801 | if (entry->end) |
3802 | entry->end += 1; | |
a269c583 DL |
3803 | } |
3804 | ||
08db6652 DL |
3805 | void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv, |
3806 | struct skl_ddb_allocation *ddb /* out */) | |
a269c583 | 3807 | { |
d5cdfdf5 | 3808 | struct intel_crtc *crtc; |
a269c583 | 3809 | |
b10f1b20 ML |
3810 | memset(ddb, 0, sizeof(*ddb)); |
3811 | ||
d5cdfdf5 | 3812 | for_each_intel_crtc(&dev_priv->drm, crtc) { |
4d800030 | 3813 | enum intel_display_power_domain power_domain; |
d5cdfdf5 VS |
3814 | enum plane_id plane_id; |
3815 | enum pipe pipe = crtc->pipe; | |
4d800030 ID |
3816 | |
3817 | power_domain = POWER_DOMAIN_PIPE(pipe); | |
3818 | if (!intel_display_power_get_if_enabled(dev_priv, power_domain)) | |
b10f1b20 ML |
3819 | continue; |
3820 | ||
d5cdfdf5 VS |
3821 | for_each_plane_id_on_crtc(crtc, plane_id) { |
3822 | u32 val; | |
3823 | ||
3824 | if (plane_id != PLANE_CURSOR) | |
3825 | val = I915_READ(PLANE_BUF_CFG(pipe, plane_id)); | |
3826 | else | |
3827 | val = I915_READ(CUR_BUF_CFG(pipe)); | |
a269c583 | 3828 | |
d5cdfdf5 VS |
3829 | skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane_id], val); |
3830 | } | |
4d800030 ID |
3831 | |
3832 | intel_display_power_put(dev_priv, power_domain); | |
a269c583 DL |
3833 | } |
3834 | } | |
3835 | ||
9c2f7a9d KM |
3836 | /* |
3837 | * Determines the downscale amount of a plane for the purposes of watermark calculations. | |
3838 | * The bspec defines downscale amount as: | |
3839 | * | |
3840 | * """ | |
3841 | * Horizontal down scale amount = maximum[1, Horizontal source size / | |
3842 | * Horizontal destination size] | |
3843 | * Vertical down scale amount = maximum[1, Vertical source size / | |
3844 | * Vertical destination size] | |
3845 | * Total down scale amount = Horizontal down scale amount * | |
3846 | * Vertical down scale amount | |
3847 | * """ | |
3848 | * | |
3849 | * Return value is provided in 16.16 fixed point form to retain fractional part. | |
3850 | * Caller should take care of dividing & rounding off the value. | |
3851 | */ | |
7084b50b | 3852 | static uint_fixed_16_16_t |
93aa2a1c VS |
3853 | skl_plane_downscale_amount(const struct intel_crtc_state *cstate, |
3854 | const struct intel_plane_state *pstate) | |
9c2f7a9d | 3855 | { |
93aa2a1c | 3856 | struct intel_plane *plane = to_intel_plane(pstate->base.plane); |
9c2f7a9d | 3857 | uint32_t src_w, src_h, dst_w, dst_h; |
7084b50b KM |
3858 | uint_fixed_16_16_t fp_w_ratio, fp_h_ratio; |
3859 | uint_fixed_16_16_t downscale_h, downscale_w; | |
9c2f7a9d | 3860 | |
93aa2a1c | 3861 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
eac2cb81 | 3862 | return u32_to_fixed16(0); |
9c2f7a9d KM |
3863 | |
3864 | /* n.b., src is 16.16 fixed point, dst is whole integer */ | |
93aa2a1c | 3865 | if (plane->id == PLANE_CURSOR) { |
fce5adf5 VS |
3866 | /* |
3867 | * Cursors only support 0/180 degree rotation, | |
3868 | * hence no need to account for rotation here. | |
3869 | */ | |
7084b50b KM |
3870 | src_w = pstate->base.src_w >> 16; |
3871 | src_h = pstate->base.src_h >> 16; | |
93aa2a1c VS |
3872 | dst_w = pstate->base.crtc_w; |
3873 | dst_h = pstate->base.crtc_h; | |
3874 | } else { | |
fce5adf5 VS |
3875 | /* |
3876 | * Src coordinates are already rotated by 270 degrees for | |
3877 | * the 90/270 degree plane rotation cases (to match the | |
3878 | * GTT mapping), hence no need to account for rotation here. | |
3879 | */ | |
7084b50b KM |
3880 | src_w = drm_rect_width(&pstate->base.src) >> 16; |
3881 | src_h = drm_rect_height(&pstate->base.src) >> 16; | |
93aa2a1c VS |
3882 | dst_w = drm_rect_width(&pstate->base.dst); |
3883 | dst_h = drm_rect_height(&pstate->base.dst); | |
3884 | } | |
3885 | ||
eac2cb81 KM |
3886 | fp_w_ratio = div_fixed16(src_w, dst_w); |
3887 | fp_h_ratio = div_fixed16(src_h, dst_h); | |
3888 | downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1)); | |
3889 | downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1)); | |
9c2f7a9d | 3890 | |
7084b50b | 3891 | return mul_fixed16(downscale_w, downscale_h); |
9c2f7a9d KM |
3892 | } |
3893 | ||
73b0ca8e MK |
3894 | static uint_fixed_16_16_t |
3895 | skl_pipe_downscale_amount(const struct intel_crtc_state *crtc_state) | |
3896 | { | |
eac2cb81 | 3897 | uint_fixed_16_16_t pipe_downscale = u32_to_fixed16(1); |
73b0ca8e MK |
3898 | |
3899 | if (!crtc_state->base.enable) | |
3900 | return pipe_downscale; | |
3901 | ||
3902 | if (crtc_state->pch_pfit.enabled) { | |
3903 | uint32_t src_w, src_h, dst_w, dst_h; | |
3904 | uint32_t pfit_size = crtc_state->pch_pfit.size; | |
3905 | uint_fixed_16_16_t fp_w_ratio, fp_h_ratio; | |
3906 | uint_fixed_16_16_t downscale_h, downscale_w; | |
3907 | ||
3908 | src_w = crtc_state->pipe_src_w; | |
3909 | src_h = crtc_state->pipe_src_h; | |
3910 | dst_w = pfit_size >> 16; | |
3911 | dst_h = pfit_size & 0xffff; | |
3912 | ||
3913 | if (!dst_w || !dst_h) | |
3914 | return pipe_downscale; | |
3915 | ||
eac2cb81 KM |
3916 | fp_w_ratio = div_fixed16(src_w, dst_w); |
3917 | fp_h_ratio = div_fixed16(src_h, dst_h); | |
3918 | downscale_w = max_fixed16(fp_w_ratio, u32_to_fixed16(1)); | |
3919 | downscale_h = max_fixed16(fp_h_ratio, u32_to_fixed16(1)); | |
73b0ca8e MK |
3920 | |
3921 | pipe_downscale = mul_fixed16(downscale_w, downscale_h); | |
3922 | } | |
3923 | ||
3924 | return pipe_downscale; | |
3925 | } | |
3926 | ||
3927 | int skl_check_pipe_max_pixel_rate(struct intel_crtc *intel_crtc, | |
3928 | struct intel_crtc_state *cstate) | |
3929 | { | |
3930 | struct drm_crtc_state *crtc_state = &cstate->base; | |
3931 | struct drm_atomic_state *state = crtc_state->state; | |
3932 | struct drm_plane *plane; | |
3933 | const struct drm_plane_state *pstate; | |
3934 | struct intel_plane_state *intel_pstate; | |
789f35d7 | 3935 | int crtc_clock, dotclk; |
73b0ca8e MK |
3936 | uint32_t pipe_max_pixel_rate; |
3937 | uint_fixed_16_16_t pipe_downscale; | |
eac2cb81 | 3938 | uint_fixed_16_16_t max_downscale = u32_to_fixed16(1); |
73b0ca8e MK |
3939 | |
3940 | if (!cstate->base.enable) | |
3941 | return 0; | |
3942 | ||
3943 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { | |
3944 | uint_fixed_16_16_t plane_downscale; | |
eac2cb81 | 3945 | uint_fixed_16_16_t fp_9_div_8 = div_fixed16(9, 8); |
73b0ca8e MK |
3946 | int bpp; |
3947 | ||
3948 | if (!intel_wm_plane_visible(cstate, | |
3949 | to_intel_plane_state(pstate))) | |
3950 | continue; | |
3951 | ||
3952 | if (WARN_ON(!pstate->fb)) | |
3953 | return -EINVAL; | |
3954 | ||
3955 | intel_pstate = to_intel_plane_state(pstate); | |
3956 | plane_downscale = skl_plane_downscale_amount(cstate, | |
3957 | intel_pstate); | |
3958 | bpp = pstate->fb->format->cpp[0] * 8; | |
3959 | if (bpp == 64) | |
3960 | plane_downscale = mul_fixed16(plane_downscale, | |
3961 | fp_9_div_8); | |
3962 | ||
eac2cb81 | 3963 | max_downscale = max_fixed16(plane_downscale, max_downscale); |
73b0ca8e MK |
3964 | } |
3965 | pipe_downscale = skl_pipe_downscale_amount(cstate); | |
3966 | ||
3967 | pipe_downscale = mul_fixed16(pipe_downscale, max_downscale); | |
3968 | ||
3969 | crtc_clock = crtc_state->adjusted_mode.crtc_clock; | |
789f35d7 ML |
3970 | dotclk = to_intel_atomic_state(state)->cdclk.logical.cdclk; |
3971 | ||
3972 | if (IS_GEMINILAKE(to_i915(intel_crtc->base.dev))) | |
3973 | dotclk *= 2; | |
3974 | ||
3975 | pipe_max_pixel_rate = div_round_up_u32_fixed16(dotclk, pipe_downscale); | |
73b0ca8e MK |
3976 | |
3977 | if (pipe_max_pixel_rate < crtc_clock) { | |
789f35d7 | 3978 | DRM_DEBUG_KMS("Max supported pixel clock with scaling exceeded\n"); |
73b0ca8e MK |
3979 | return -EINVAL; |
3980 | } | |
3981 | ||
3982 | return 0; | |
3983 | } | |
3984 | ||
b9cec075 | 3985 | static unsigned int |
024c9045 MR |
3986 | skl_plane_relative_data_rate(const struct intel_crtc_state *cstate, |
3987 | const struct drm_plane_state *pstate, | |
3988 | int y) | |
b9cec075 | 3989 | { |
93aa2a1c | 3990 | struct intel_plane *plane = to_intel_plane(pstate->plane); |
a280f7dd | 3991 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); |
7084b50b | 3992 | uint32_t data_rate; |
a280f7dd | 3993 | uint32_t width = 0, height = 0; |
8305494e VS |
3994 | struct drm_framebuffer *fb; |
3995 | u32 format; | |
7084b50b | 3996 | uint_fixed_16_16_t down_scale_amount; |
a1de91e5 | 3997 | |
936e71e3 | 3998 | if (!intel_pstate->base.visible) |
a1de91e5 | 3999 | return 0; |
8305494e VS |
4000 | |
4001 | fb = pstate->fb; | |
438b74a5 | 4002 | format = fb->format->format; |
8305494e | 4003 | |
93aa2a1c | 4004 | if (plane->id == PLANE_CURSOR) |
a1de91e5 MR |
4005 | return 0; |
4006 | if (y && format != DRM_FORMAT_NV12) | |
4007 | return 0; | |
a280f7dd | 4008 | |
fce5adf5 VS |
4009 | /* |
4010 | * Src coordinates are already rotated by 270 degrees for | |
4011 | * the 90/270 degree plane rotation cases (to match the | |
4012 | * GTT mapping), hence no need to account for rotation here. | |
4013 | */ | |
936e71e3 VS |
4014 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
4015 | height = drm_rect_height(&intel_pstate->base.src) >> 16; | |
a280f7dd | 4016 | |
2cd601c6 | 4017 | /* for planar format */ |
a1de91e5 | 4018 | if (format == DRM_FORMAT_NV12) { |
2cd601c6 | 4019 | if (y) /* y-plane data rate */ |
8d19d7d9 | 4020 | data_rate = width * height * |
353c8598 | 4021 | fb->format->cpp[0]; |
2cd601c6 | 4022 | else /* uv-plane data rate */ |
8d19d7d9 | 4023 | data_rate = (width / 2) * (height / 2) * |
353c8598 | 4024 | fb->format->cpp[1]; |
8d19d7d9 KM |
4025 | } else { |
4026 | /* for packed formats */ | |
353c8598 | 4027 | data_rate = width * height * fb->format->cpp[0]; |
2cd601c6 CK |
4028 | } |
4029 | ||
93aa2a1c | 4030 | down_scale_amount = skl_plane_downscale_amount(cstate, intel_pstate); |
8d19d7d9 | 4031 | |
7084b50b | 4032 | return mul_round_up_u32_fixed16(data_rate, down_scale_amount); |
b9cec075 DL |
4033 | } |
4034 | ||
4035 | /* | |
4036 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
4037 | * a 8192x4096@32bpp framebuffer: | |
4038 | * 3 * 4096 * 8192 * 4 < 2^32 | |
4039 | */ | |
4040 | static unsigned int | |
1e6ee542 ML |
4041 | skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate, |
4042 | unsigned *plane_data_rate, | |
4043 | unsigned *plane_y_data_rate) | |
b9cec075 | 4044 | { |
9c74d826 MR |
4045 | struct drm_crtc_state *cstate = &intel_cstate->base; |
4046 | struct drm_atomic_state *state = cstate->state; | |
c8fe32c1 | 4047 | struct drm_plane *plane; |
c8fe32c1 | 4048 | const struct drm_plane_state *pstate; |
d5cdfdf5 | 4049 | unsigned int total_data_rate = 0; |
a6d3460e MR |
4050 | |
4051 | if (WARN_ON(!state)) | |
4052 | return 0; | |
b9cec075 | 4053 | |
a1de91e5 | 4054 | /* Calculate and cache data rate for each plane */ |
c8fe32c1 | 4055 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) { |
d5cdfdf5 VS |
4056 | enum plane_id plane_id = to_intel_plane(plane)->id; |
4057 | unsigned int rate; | |
a6d3460e | 4058 | |
a6d3460e MR |
4059 | /* packed/uv */ |
4060 | rate = skl_plane_relative_data_rate(intel_cstate, | |
4061 | pstate, 0); | |
d5cdfdf5 | 4062 | plane_data_rate[plane_id] = rate; |
1e6ee542 ML |
4063 | |
4064 | total_data_rate += rate; | |
a6d3460e MR |
4065 | |
4066 | /* y-plane */ | |
4067 | rate = skl_plane_relative_data_rate(intel_cstate, | |
4068 | pstate, 1); | |
d5cdfdf5 | 4069 | plane_y_data_rate[plane_id] = rate; |
024c9045 | 4070 | |
1e6ee542 | 4071 | total_data_rate += rate; |
b9cec075 DL |
4072 | } |
4073 | ||
4074 | return total_data_rate; | |
4075 | } | |
4076 | ||
cbcfd14b KM |
4077 | static uint16_t |
4078 | skl_ddb_min_alloc(const struct drm_plane_state *pstate, | |
4079 | const int y) | |
4080 | { | |
4081 | struct drm_framebuffer *fb = pstate->fb; | |
4082 | struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate); | |
4083 | uint32_t src_w, src_h; | |
4084 | uint32_t min_scanlines = 8; | |
4085 | uint8_t plane_bpp; | |
4086 | ||
4087 | if (WARN_ON(!fb)) | |
4088 | return 0; | |
4089 | ||
4090 | /* For packed formats, no y-plane, return 0 */ | |
438b74a5 | 4091 | if (y && fb->format->format != DRM_FORMAT_NV12) |
cbcfd14b KM |
4092 | return 0; |
4093 | ||
4094 | /* For Non Y-tile return 8-blocks */ | |
bae781b2 | 4095 | if (fb->modifier != I915_FORMAT_MOD_Y_TILED && |
2e2adb05 VS |
4096 | fb->modifier != I915_FORMAT_MOD_Yf_TILED && |
4097 | fb->modifier != I915_FORMAT_MOD_Y_TILED_CCS && | |
4098 | fb->modifier != I915_FORMAT_MOD_Yf_TILED_CCS) | |
cbcfd14b KM |
4099 | return 8; |
4100 | ||
fce5adf5 VS |
4101 | /* |
4102 | * Src coordinates are already rotated by 270 degrees for | |
4103 | * the 90/270 degree plane rotation cases (to match the | |
4104 | * GTT mapping), hence no need to account for rotation here. | |
4105 | */ | |
936e71e3 VS |
4106 | src_w = drm_rect_width(&intel_pstate->base.src) >> 16; |
4107 | src_h = drm_rect_height(&intel_pstate->base.src) >> 16; | |
cbcfd14b | 4108 | |
cbcfd14b | 4109 | /* Halve UV plane width and height for NV12 */ |
438b74a5 | 4110 | if (fb->format->format == DRM_FORMAT_NV12 && !y) { |
cbcfd14b KM |
4111 | src_w /= 2; |
4112 | src_h /= 2; | |
4113 | } | |
4114 | ||
438b74a5 | 4115 | if (fb->format->format == DRM_FORMAT_NV12 && !y) |
353c8598 | 4116 | plane_bpp = fb->format->cpp[1]; |
cbcfd14b | 4117 | else |
353c8598 | 4118 | plane_bpp = fb->format->cpp[0]; |
cbcfd14b | 4119 | |
bd2ef25d | 4120 | if (drm_rotation_90_or_270(pstate->rotation)) { |
cbcfd14b KM |
4121 | switch (plane_bpp) { |
4122 | case 1: | |
4123 | min_scanlines = 32; | |
4124 | break; | |
4125 | case 2: | |
4126 | min_scanlines = 16; | |
4127 | break; | |
4128 | case 4: | |
4129 | min_scanlines = 8; | |
4130 | break; | |
4131 | case 8: | |
4132 | min_scanlines = 4; | |
4133 | break; | |
4134 | default: | |
4135 | WARN(1, "Unsupported pixel depth %u for rotation", | |
4136 | plane_bpp); | |
4137 | min_scanlines = 32; | |
4138 | } | |
4139 | } | |
4140 | ||
4141 | return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3; | |
4142 | } | |
4143 | ||
49845a7a ML |
4144 | static void |
4145 | skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active, | |
4146 | uint16_t *minimum, uint16_t *y_minimum) | |
4147 | { | |
4148 | const struct drm_plane_state *pstate; | |
4149 | struct drm_plane *plane; | |
4150 | ||
4151 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) { | |
d5cdfdf5 | 4152 | enum plane_id plane_id = to_intel_plane(plane)->id; |
49845a7a | 4153 | |
d5cdfdf5 | 4154 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
4155 | continue; |
4156 | ||
4157 | if (!pstate->visible) | |
4158 | continue; | |
4159 | ||
d5cdfdf5 VS |
4160 | minimum[plane_id] = skl_ddb_min_alloc(pstate, 0); |
4161 | y_minimum[plane_id] = skl_ddb_min_alloc(pstate, 1); | |
49845a7a ML |
4162 | } |
4163 | ||
4164 | minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active); | |
4165 | } | |
4166 | ||
c107acfe | 4167 | static int |
024c9045 | 4168 | skl_allocate_pipe_ddb(struct intel_crtc_state *cstate, |
b9cec075 DL |
4169 | struct skl_ddb_allocation *ddb /* out */) |
4170 | { | |
c107acfe | 4171 | struct drm_atomic_state *state = cstate->base.state; |
024c9045 | 4172 | struct drm_crtc *crtc = cstate->base.crtc; |
b9cec075 DL |
4173 | struct drm_device *dev = crtc->dev; |
4174 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4175 | enum pipe pipe = intel_crtc->pipe; | |
ce0ba283 | 4176 | struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb; |
49845a7a | 4177 | uint16_t alloc_size, start; |
fefdd810 ML |
4178 | uint16_t minimum[I915_MAX_PLANES] = {}; |
4179 | uint16_t y_minimum[I915_MAX_PLANES] = {}; | |
b9cec075 | 4180 | unsigned int total_data_rate; |
d5cdfdf5 | 4181 | enum plane_id plane_id; |
c107acfe | 4182 | int num_active; |
1e6ee542 ML |
4183 | unsigned plane_data_rate[I915_MAX_PLANES] = {}; |
4184 | unsigned plane_y_data_rate[I915_MAX_PLANES] = {}; | |
5ba6faaf | 4185 | uint16_t total_min_blocks = 0; |
b9cec075 | 4186 | |
5a920b85 PZ |
4187 | /* Clear the partitioning for disabled planes. */ |
4188 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
4189 | memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe])); | |
4190 | ||
a6d3460e MR |
4191 | if (WARN_ON(!state)) |
4192 | return 0; | |
4193 | ||
c107acfe | 4194 | if (!cstate->base.active) { |
ce0ba283 | 4195 | alloc->start = alloc->end = 0; |
c107acfe MR |
4196 | return 0; |
4197 | } | |
4198 | ||
a6d3460e | 4199 | skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active); |
34bb56af | 4200 | alloc_size = skl_ddb_entry_size(alloc); |
336031ea | 4201 | if (alloc_size == 0) |
c107acfe | 4202 | return 0; |
b9cec075 | 4203 | |
49845a7a | 4204 | skl_ddb_calc_min(cstate, num_active, minimum, y_minimum); |
a6d3460e | 4205 | |
49845a7a ML |
4206 | /* |
4207 | * 1. Allocate the mininum required blocks for each active plane | |
4208 | * and allocate the cursor, it doesn't require extra allocation | |
4209 | * proportional to the data rate. | |
4210 | */ | |
80958155 | 4211 | |
d5cdfdf5 | 4212 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
5ba6faaf KM |
4213 | total_min_blocks += minimum[plane_id]; |
4214 | total_min_blocks += y_minimum[plane_id]; | |
80958155 DL |
4215 | } |
4216 | ||
5ba6faaf KM |
4217 | if (total_min_blocks > alloc_size) { |
4218 | DRM_DEBUG_KMS("Requested display configuration exceeds system DDB limitations"); | |
4219 | DRM_DEBUG_KMS("minimum required %d/%d\n", total_min_blocks, | |
4220 | alloc_size); | |
4221 | return -EINVAL; | |
4222 | } | |
4223 | ||
9a30a261 RV |
4224 | alloc_size -= total_min_blocks; |
4225 | ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR]; | |
49845a7a ML |
4226 | ddb->plane[pipe][PLANE_CURSOR].end = alloc->end; |
4227 | ||
b9cec075 | 4228 | /* |
80958155 DL |
4229 | * 2. Distribute the remaining space in proportion to the amount of |
4230 | * data each plane needs to fetch from memory. | |
b9cec075 DL |
4231 | * |
4232 | * FIXME: we may not allocate every single block here. | |
4233 | */ | |
1e6ee542 ML |
4234 | total_data_rate = skl_get_total_relative_data_rate(cstate, |
4235 | plane_data_rate, | |
4236 | plane_y_data_rate); | |
a1de91e5 | 4237 | if (total_data_rate == 0) |
c107acfe | 4238 | return 0; |
b9cec075 | 4239 | |
34bb56af | 4240 | start = alloc->start; |
d5cdfdf5 | 4241 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
2cd601c6 | 4242 | unsigned int data_rate, y_data_rate; |
9a30a261 | 4243 | uint16_t plane_blocks, y_plane_blocks = 0; |
b9cec075 | 4244 | |
d5cdfdf5 | 4245 | if (plane_id == PLANE_CURSOR) |
49845a7a ML |
4246 | continue; |
4247 | ||
d5cdfdf5 | 4248 | data_rate = plane_data_rate[plane_id]; |
b9cec075 DL |
4249 | |
4250 | /* | |
2cd601c6 | 4251 | * allocation for (packed formats) or (uv-plane part of planar format): |
b9cec075 DL |
4252 | * promote the expression to 64 bits to avoid overflowing, the |
4253 | * result is < available as data_rate / total_data_rate < 1 | |
4254 | */ | |
9a30a261 RV |
4255 | plane_blocks = minimum[plane_id]; |
4256 | plane_blocks += div_u64((uint64_t)alloc_size * data_rate, | |
4257 | total_data_rate); | |
b9cec075 | 4258 | |
c107acfe MR |
4259 | /* Leave disabled planes at (0,0) */ |
4260 | if (data_rate) { | |
d5cdfdf5 VS |
4261 | ddb->plane[pipe][plane_id].start = start; |
4262 | ddb->plane[pipe][plane_id].end = start + plane_blocks; | |
c107acfe | 4263 | } |
b9cec075 | 4264 | |
9a30a261 RV |
4265 | start += plane_blocks; |
4266 | ||
2cd601c6 CK |
4267 | /* |
4268 | * allocation for y_plane part of planar format: | |
4269 | */ | |
d5cdfdf5 | 4270 | y_data_rate = plane_y_data_rate[plane_id]; |
a1de91e5 | 4271 | |
9a30a261 RV |
4272 | y_plane_blocks = y_minimum[plane_id]; |
4273 | y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate, | |
4274 | total_data_rate); | |
4275 | ||
c107acfe | 4276 | if (y_data_rate) { |
d5cdfdf5 VS |
4277 | ddb->y_plane[pipe][plane_id].start = start; |
4278 | ddb->y_plane[pipe][plane_id].end = start + y_plane_blocks; | |
c107acfe | 4279 | } |
9a30a261 RV |
4280 | |
4281 | start += y_plane_blocks; | |
b9cec075 DL |
4282 | } |
4283 | ||
c107acfe | 4284 | return 0; |
b9cec075 DL |
4285 | } |
4286 | ||
2d41c0b5 PB |
4287 | /* |
4288 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
ac484963 | 4289 | * for the read latency) and cpp should always be <= 8, so that |
2d41c0b5 PB |
4290 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max |
4291 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
4292 | */ | |
6c64dd37 PZ |
4293 | static uint_fixed_16_16_t |
4294 | skl_wm_method1(const struct drm_i915_private *dev_priv, uint32_t pixel_rate, | |
4295 | uint8_t cpp, uint32_t latency) | |
2d41c0b5 | 4296 | { |
b95320bd MK |
4297 | uint32_t wm_intermediate_val; |
4298 | uint_fixed_16_16_t ret; | |
2d41c0b5 PB |
4299 | |
4300 | if (latency == 0) | |
b95320bd | 4301 | return FP_16_16_MAX; |
2d41c0b5 | 4302 | |
b95320bd | 4303 | wm_intermediate_val = latency * pixel_rate * cpp; |
eac2cb81 | 4304 | ret = div_fixed16(wm_intermediate_val, 1000 * 512); |
6c64dd37 PZ |
4305 | |
4306 | if (INTEL_GEN(dev_priv) >= 10) | |
4307 | ret = add_fixed16_u32(ret, 1); | |
4308 | ||
2d41c0b5 PB |
4309 | return ret; |
4310 | } | |
4311 | ||
b95320bd MK |
4312 | static uint_fixed_16_16_t skl_wm_method2(uint32_t pixel_rate, |
4313 | uint32_t pipe_htotal, | |
4314 | uint32_t latency, | |
4315 | uint_fixed_16_16_t plane_blocks_per_line) | |
2d41c0b5 | 4316 | { |
d4c2aa60 | 4317 | uint32_t wm_intermediate_val; |
b95320bd | 4318 | uint_fixed_16_16_t ret; |
2d41c0b5 PB |
4319 | |
4320 | if (latency == 0) | |
b95320bd | 4321 | return FP_16_16_MAX; |
2d41c0b5 | 4322 | |
2d41c0b5 | 4323 | wm_intermediate_val = latency * pixel_rate; |
b95320bd MK |
4324 | wm_intermediate_val = DIV_ROUND_UP(wm_intermediate_val, |
4325 | pipe_htotal * 1000); | |
eac2cb81 | 4326 | ret = mul_u32_fixed16(wm_intermediate_val, plane_blocks_per_line); |
2d41c0b5 PB |
4327 | return ret; |
4328 | } | |
4329 | ||
d555cb58 KM |
4330 | static uint_fixed_16_16_t |
4331 | intel_get_linetime_us(struct intel_crtc_state *cstate) | |
4332 | { | |
4333 | uint32_t pixel_rate; | |
4334 | uint32_t crtc_htotal; | |
4335 | uint_fixed_16_16_t linetime_us; | |
4336 | ||
4337 | if (!cstate->base.active) | |
eac2cb81 | 4338 | return u32_to_fixed16(0); |
d555cb58 KM |
4339 | |
4340 | pixel_rate = cstate->pixel_rate; | |
4341 | ||
4342 | if (WARN_ON(pixel_rate == 0)) | |
eac2cb81 | 4343 | return u32_to_fixed16(0); |
d555cb58 KM |
4344 | |
4345 | crtc_htotal = cstate->base.adjusted_mode.crtc_htotal; | |
eac2cb81 | 4346 | linetime_us = div_fixed16(crtc_htotal * 1000, pixel_rate); |
d555cb58 KM |
4347 | |
4348 | return linetime_us; | |
4349 | } | |
4350 | ||
eb2fdcdf KM |
4351 | static uint32_t |
4352 | skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate, | |
4353 | const struct intel_plane_state *pstate) | |
9c2f7a9d KM |
4354 | { |
4355 | uint64_t adjusted_pixel_rate; | |
7084b50b | 4356 | uint_fixed_16_16_t downscale_amount; |
9c2f7a9d KM |
4357 | |
4358 | /* Shouldn't reach here on disabled planes... */ | |
93aa2a1c | 4359 | if (WARN_ON(!intel_wm_plane_visible(cstate, pstate))) |
9c2f7a9d KM |
4360 | return 0; |
4361 | ||
4362 | /* | |
4363 | * Adjusted plane pixel rate is just the pipe's adjusted pixel rate | |
4364 | * with additional adjustments for plane-specific scaling. | |
4365 | */ | |
a7d1b3f4 | 4366 | adjusted_pixel_rate = cstate->pixel_rate; |
93aa2a1c | 4367 | downscale_amount = skl_plane_downscale_amount(cstate, pstate); |
9c2f7a9d | 4368 | |
7084b50b KM |
4369 | return mul_round_up_u32_fixed16(adjusted_pixel_rate, |
4370 | downscale_amount); | |
9c2f7a9d KM |
4371 | } |
4372 | ||
55994c2c MR |
4373 | static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv, |
4374 | struct intel_crtc_state *cstate, | |
eb2fdcdf | 4375 | const struct intel_plane_state *intel_pstate, |
9a30a261 | 4376 | uint16_t ddb_allocation, |
55994c2c MR |
4377 | int level, |
4378 | uint16_t *out_blocks, /* out */ | |
9a30a261 RV |
4379 | uint8_t *out_lines, /* out */ |
4380 | bool *enabled /* out */) | |
2d41c0b5 | 4381 | { |
93aa2a1c | 4382 | struct intel_plane *plane = to_intel_plane(intel_pstate->base.plane); |
eb2fdcdf KM |
4383 | const struct drm_plane_state *pstate = &intel_pstate->base; |
4384 | const struct drm_framebuffer *fb = pstate->fb; | |
d4c2aa60 | 4385 | uint32_t latency = dev_priv->wm.skl_latency[level]; |
b95320bd MK |
4386 | uint_fixed_16_16_t method1, method2; |
4387 | uint_fixed_16_16_t plane_blocks_per_line; | |
4388 | uint_fixed_16_16_t selected_result; | |
4389 | uint32_t interm_pbpl; | |
4390 | uint32_t plane_bytes_per_line; | |
d4c2aa60 | 4391 | uint32_t res_blocks, res_lines; |
ac484963 | 4392 | uint8_t cpp; |
129eaa95 | 4393 | uint32_t width = 0; |
9c2f7a9d | 4394 | uint32_t plane_pixel_rate; |
b95320bd MK |
4395 | uint_fixed_16_16_t y_tile_minimum; |
4396 | uint32_t y_min_scanlines; | |
ee3d532f PZ |
4397 | struct intel_atomic_state *state = |
4398 | to_intel_atomic_state(cstate->base.state); | |
4399 | bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state); | |
ef8a4fb4 | 4400 | bool y_tiled, x_tiled; |
2d41c0b5 | 4401 | |
93aa2a1c | 4402 | if (latency == 0 || |
9a30a261 RV |
4403 | !intel_wm_plane_visible(cstate, intel_pstate)) { |
4404 | *enabled = false; | |
55994c2c | 4405 | return 0; |
9a30a261 | 4406 | } |
2d41c0b5 | 4407 | |
ef8a4fb4 | 4408 | y_tiled = fb->modifier == I915_FORMAT_MOD_Y_TILED || |
2e2adb05 VS |
4409 | fb->modifier == I915_FORMAT_MOD_Yf_TILED || |
4410 | fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
4411 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS; | |
ef8a4fb4 MK |
4412 | x_tiled = fb->modifier == I915_FORMAT_MOD_X_TILED; |
4413 | ||
82525c17 RV |
4414 | /* Display WA #1141: kbl,cfl */ |
4415 | if ((IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) && | |
4416 | dev_priv->ipc_enabled) | |
4b7b2331 MK |
4417 | latency += 4; |
4418 | ||
ef8a4fb4 | 4419 | if (apply_memory_bw_wa && x_tiled) |
ee3d532f PZ |
4420 | latency += 15; |
4421 | ||
93aa2a1c VS |
4422 | if (plane->id == PLANE_CURSOR) { |
4423 | width = intel_pstate->base.crtc_w; | |
93aa2a1c | 4424 | } else { |
fce5adf5 VS |
4425 | /* |
4426 | * Src coordinates are already rotated by 270 degrees for | |
4427 | * the 90/270 degree plane rotation cases (to match the | |
4428 | * GTT mapping), hence no need to account for rotation here. | |
4429 | */ | |
93aa2a1c | 4430 | width = drm_rect_width(&intel_pstate->base.src) >> 16; |
93aa2a1c | 4431 | } |
a280f7dd | 4432 | |
b064be07 KM |
4433 | cpp = (fb->format->format == DRM_FORMAT_NV12) ? fb->format->cpp[1] : |
4434 | fb->format->cpp[0]; | |
9c2f7a9d KM |
4435 | plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate); |
4436 | ||
61d0a04d | 4437 | if (drm_rotation_90_or_270(pstate->rotation)) { |
1186fa85 PZ |
4438 | |
4439 | switch (cpp) { | |
4440 | case 1: | |
4441 | y_min_scanlines = 16; | |
4442 | break; | |
4443 | case 2: | |
4444 | y_min_scanlines = 8; | |
4445 | break; | |
1186fa85 PZ |
4446 | case 4: |
4447 | y_min_scanlines = 4; | |
4448 | break; | |
86a462bc PZ |
4449 | default: |
4450 | MISSING_CASE(cpp); | |
4451 | return -EINVAL; | |
1186fa85 PZ |
4452 | } |
4453 | } else { | |
4454 | y_min_scanlines = 4; | |
4455 | } | |
4456 | ||
2ef32dee PZ |
4457 | if (apply_memory_bw_wa) |
4458 | y_min_scanlines *= 2; | |
4459 | ||
7a1a8aed | 4460 | plane_bytes_per_line = width * cpp; |
ef8a4fb4 | 4461 | if (y_tiled) { |
b95320bd MK |
4462 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line * |
4463 | y_min_scanlines, 512); | |
6c64dd37 PZ |
4464 | |
4465 | if (INTEL_GEN(dev_priv) >= 10) | |
4466 | interm_pbpl++; | |
4467 | ||
eac2cb81 | 4468 | plane_blocks_per_line = div_fixed16(interm_pbpl, |
afbc95cd | 4469 | y_min_scanlines); |
6c64dd37 | 4470 | } else if (x_tiled && INTEL_GEN(dev_priv) == 9) { |
b95320bd | 4471 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512); |
eac2cb81 | 4472 | plane_blocks_per_line = u32_to_fixed16(interm_pbpl); |
ef8a4fb4 | 4473 | } else { |
b95320bd | 4474 | interm_pbpl = DIV_ROUND_UP(plane_bytes_per_line, 512) + 1; |
eac2cb81 | 4475 | plane_blocks_per_line = u32_to_fixed16(interm_pbpl); |
7a1a8aed PZ |
4476 | } |
4477 | ||
6c64dd37 | 4478 | method1 = skl_wm_method1(dev_priv, plane_pixel_rate, cpp, latency); |
9c2f7a9d | 4479 | method2 = skl_wm_method2(plane_pixel_rate, |
024c9045 | 4480 | cstate->base.adjusted_mode.crtc_htotal, |
1186fa85 | 4481 | latency, |
7a1a8aed | 4482 | plane_blocks_per_line); |
2d41c0b5 | 4483 | |
eac2cb81 KM |
4484 | y_tile_minimum = mul_u32_fixed16(y_min_scanlines, |
4485 | plane_blocks_per_line); | |
75676ed4 | 4486 | |
ef8a4fb4 | 4487 | if (y_tiled) { |
eac2cb81 | 4488 | selected_result = max_fixed16(method2, y_tile_minimum); |
0fda6568 | 4489 | } else { |
d555cb58 KM |
4490 | uint32_t linetime_us; |
4491 | ||
eac2cb81 | 4492 | linetime_us = fixed16_to_u32_round_up( |
d555cb58 | 4493 | intel_get_linetime_us(cstate)); |
f1db3eaf PZ |
4494 | if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) && |
4495 | (plane_bytes_per_line / 512 < 1)) | |
4496 | selected_result = method2; | |
54d20ed1 ML |
4497 | else if (ddb_allocation >= |
4498 | fixed16_to_u32_round_up(plane_blocks_per_line)) | |
eac2cb81 | 4499 | selected_result = min_fixed16(method1, method2); |
d555cb58 | 4500 | else if (latency >= linetime_us) |
eac2cb81 | 4501 | selected_result = min_fixed16(method1, method2); |
0fda6568 TU |
4502 | else |
4503 | selected_result = method1; | |
4504 | } | |
2d41c0b5 | 4505 | |
eac2cb81 | 4506 | res_blocks = fixed16_to_u32_round_up(selected_result) + 1; |
d273ecce KM |
4507 | res_lines = div_round_up_fixed16(selected_result, |
4508 | plane_blocks_per_line); | |
e6d66171 | 4509 | |
2e2adb05 VS |
4510 | /* Display WA #1125: skl,bxt,kbl,glk */ |
4511 | if (level == 0 && | |
4512 | (fb->modifier == I915_FORMAT_MOD_Y_TILED_CCS || | |
4513 | fb->modifier == I915_FORMAT_MOD_Yf_TILED_CCS)) | |
4514 | res_blocks += fixed16_to_u32_round_up(y_tile_minimum); | |
4515 | ||
4516 | /* Display WA #1126: skl,bxt,kbl,glk */ | |
0fda6568 | 4517 | if (level >= 1 && level <= 7) { |
ef8a4fb4 | 4518 | if (y_tiled) { |
eac2cb81 | 4519 | res_blocks += fixed16_to_u32_round_up(y_tile_minimum); |
1186fa85 | 4520 | res_lines += y_min_scanlines; |
75676ed4 | 4521 | } else { |
0fda6568 | 4522 | res_blocks++; |
75676ed4 | 4523 | } |
0fda6568 | 4524 | } |
e6d66171 | 4525 | |
9a30a261 RV |
4526 | if (res_blocks >= ddb_allocation || res_lines > 31) { |
4527 | *enabled = false; | |
d5cdfdf5 | 4528 | |
9a30a261 RV |
4529 | /* |
4530 | * If there are no valid level 0 watermarks, then we can't | |
4531 | * support this display configuration. | |
4532 | */ | |
4533 | if (level) { | |
4534 | return 0; | |
4535 | } else { | |
4536 | struct drm_plane *plane = pstate->plane; | |
4537 | ||
4538 | DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n"); | |
4539 | DRM_DEBUG_KMS("[PLANE:%d:%s] blocks required = %u/%u, lines required = %u/31\n", | |
4540 | plane->base.id, plane->name, | |
4541 | res_blocks, ddb_allocation, res_lines); | |
4542 | return -EINVAL; | |
4543 | } | |
55994c2c | 4544 | } |
e6d66171 DL |
4545 | |
4546 | *out_blocks = res_blocks; | |
4547 | *out_lines = res_lines; | |
9a30a261 | 4548 | *enabled = true; |
2d41c0b5 | 4549 | |
55994c2c | 4550 | return 0; |
2d41c0b5 PB |
4551 | } |
4552 | ||
f4a96752 | 4553 | static int |
d2f5e36d | 4554 | skl_compute_wm_levels(const struct drm_i915_private *dev_priv, |
9a30a261 | 4555 | struct skl_ddb_allocation *ddb, |
d2f5e36d KM |
4556 | struct intel_crtc_state *cstate, |
4557 | const struct intel_plane_state *intel_pstate, | |
4558 | struct skl_plane_wm *wm) | |
2d41c0b5 | 4559 | { |
9a30a261 RV |
4560 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
4561 | struct drm_plane *plane = intel_pstate->base.plane; | |
4562 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
4563 | uint16_t ddb_blocks; | |
4564 | enum pipe pipe = intel_crtc->pipe; | |
d2f5e36d | 4565 | int level, max_level = ilk_wm_max_level(dev_priv); |
55994c2c | 4566 | int ret; |
a62163e9 | 4567 | |
7b75119c KM |
4568 | if (WARN_ON(!intel_pstate->base.fb)) |
4569 | return -EINVAL; | |
f4a96752 | 4570 | |
9a30a261 RV |
4571 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][intel_plane->id]); |
4572 | ||
d2f5e36d KM |
4573 | for (level = 0; level <= max_level; level++) { |
4574 | struct skl_wm_level *result = &wm->wm[level]; | |
4575 | ||
4576 | ret = skl_compute_plane_wm(dev_priv, | |
4577 | cstate, | |
4578 | intel_pstate, | |
9a30a261 | 4579 | ddb_blocks, |
d2f5e36d KM |
4580 | level, |
4581 | &result->plane_res_b, | |
9a30a261 RV |
4582 | &result->plane_res_l, |
4583 | &result->plane_en); | |
d2f5e36d KM |
4584 | if (ret) |
4585 | return ret; | |
4586 | } | |
f4a96752 MR |
4587 | |
4588 | return 0; | |
2d41c0b5 PB |
4589 | } |
4590 | ||
407b50f3 | 4591 | static uint32_t |
024c9045 | 4592 | skl_compute_linetime_wm(struct intel_crtc_state *cstate) |
407b50f3 | 4593 | { |
a3a8986c MK |
4594 | struct drm_atomic_state *state = cstate->base.state; |
4595 | struct drm_i915_private *dev_priv = to_i915(state->dev); | |
d555cb58 | 4596 | uint_fixed_16_16_t linetime_us; |
a3a8986c | 4597 | uint32_t linetime_wm; |
30d1b5fe | 4598 | |
d555cb58 | 4599 | linetime_us = intel_get_linetime_us(cstate); |
407b50f3 | 4600 | |
d555cb58 | 4601 | if (is_fixed16_zero(linetime_us)) |
661abfc0 | 4602 | return 0; |
407b50f3 | 4603 | |
eac2cb81 | 4604 | linetime_wm = fixed16_to_u32_round_up(mul_u32_fixed16(8, linetime_us)); |
a3a8986c MK |
4605 | |
4606 | /* Display WA #1135: bxt. */ | |
4607 | if (IS_BROXTON(dev_priv) && dev_priv->ipc_enabled) | |
4608 | linetime_wm = DIV_ROUND_UP(linetime_wm, 2); | |
4609 | ||
4610 | return linetime_wm; | |
407b50f3 DL |
4611 | } |
4612 | ||
024c9045 | 4613 | static void skl_compute_transition_wm(struct intel_crtc_state *cstate, |
9414f563 | 4614 | struct skl_wm_level *trans_wm /* out */) |
407b50f3 | 4615 | { |
024c9045 | 4616 | if (!cstate->base.active) |
407b50f3 | 4617 | return; |
9414f563 DL |
4618 | |
4619 | /* Until we know more, just disable transition WMs */ | |
a62163e9 | 4620 | trans_wm->plane_en = false; |
407b50f3 DL |
4621 | } |
4622 | ||
55994c2c MR |
4623 | static int skl_build_pipe_wm(struct intel_crtc_state *cstate, |
4624 | struct skl_ddb_allocation *ddb, | |
4625 | struct skl_pipe_wm *pipe_wm) | |
2d41c0b5 | 4626 | { |
024c9045 | 4627 | struct drm_device *dev = cstate->base.crtc->dev; |
eb2fdcdf | 4628 | struct drm_crtc_state *crtc_state = &cstate->base; |
fac5e23e | 4629 | const struct drm_i915_private *dev_priv = to_i915(dev); |
eb2fdcdf KM |
4630 | struct drm_plane *plane; |
4631 | const struct drm_plane_state *pstate; | |
a62163e9 | 4632 | struct skl_plane_wm *wm; |
55994c2c | 4633 | int ret; |
2d41c0b5 | 4634 | |
a62163e9 L |
4635 | /* |
4636 | * We'll only calculate watermarks for planes that are actually | |
4637 | * enabled, so make sure all other planes are set as disabled. | |
4638 | */ | |
4639 | memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes)); | |
4640 | ||
eb2fdcdf KM |
4641 | drm_atomic_crtc_state_for_each_plane_state(plane, pstate, crtc_state) { |
4642 | const struct intel_plane_state *intel_pstate = | |
4643 | to_intel_plane_state(pstate); | |
4644 | enum plane_id plane_id = to_intel_plane(plane)->id; | |
4645 | ||
4646 | wm = &pipe_wm->planes[plane_id]; | |
a62163e9 | 4647 | |
9a30a261 RV |
4648 | ret = skl_compute_wm_levels(dev_priv, ddb, cstate, |
4649 | intel_pstate, wm); | |
d2f5e36d KM |
4650 | if (ret) |
4651 | return ret; | |
a62163e9 | 4652 | skl_compute_transition_wm(cstate, &wm->trans_wm); |
2d41c0b5 | 4653 | } |
024c9045 | 4654 | pipe_wm->linetime = skl_compute_linetime_wm(cstate); |
2d41c0b5 | 4655 | |
55994c2c | 4656 | return 0; |
2d41c0b5 PB |
4657 | } |
4658 | ||
f0f59a00 VS |
4659 | static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, |
4660 | i915_reg_t reg, | |
16160e3d DL |
4661 | const struct skl_ddb_entry *entry) |
4662 | { | |
4663 | if (entry->end) | |
4664 | I915_WRITE(reg, (entry->end - 1) << 16 | entry->start); | |
4665 | else | |
4666 | I915_WRITE(reg, 0); | |
4667 | } | |
4668 | ||
d8c0fafc | 4669 | static void skl_write_wm_level(struct drm_i915_private *dev_priv, |
4670 | i915_reg_t reg, | |
4671 | const struct skl_wm_level *level) | |
4672 | { | |
4673 | uint32_t val = 0; | |
4674 | ||
4675 | if (level->plane_en) { | |
4676 | val |= PLANE_WM_EN; | |
4677 | val |= level->plane_res_b; | |
4678 | val |= level->plane_res_l << PLANE_WM_LINES_SHIFT; | |
4679 | } | |
4680 | ||
4681 | I915_WRITE(reg, val); | |
4682 | } | |
4683 | ||
d9348dec VS |
4684 | static void skl_write_plane_wm(struct intel_crtc *intel_crtc, |
4685 | const struct skl_plane_wm *wm, | |
4686 | const struct skl_ddb_allocation *ddb, | |
d5cdfdf5 | 4687 | enum plane_id plane_id) |
62e0fb88 L |
4688 | { |
4689 | struct drm_crtc *crtc = &intel_crtc->base; | |
4690 | struct drm_device *dev = crtc->dev; | |
4691 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4692 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4693 | enum pipe pipe = intel_crtc->pipe; |
4694 | ||
4695 | for (level = 0; level <= max_level; level++) { | |
d5cdfdf5 | 4696 | skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane_id, level), |
d8c0fafc | 4697 | &wm->wm[level]); |
62e0fb88 | 4698 | } |
d5cdfdf5 | 4699 | skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane_id), |
d8c0fafc | 4700 | &wm->trans_wm); |
27082493 | 4701 | |
d5cdfdf5 VS |
4702 | skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane_id), |
4703 | &ddb->plane[pipe][plane_id]); | |
4704 | skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane_id), | |
4705 | &ddb->y_plane[pipe][plane_id]); | |
62e0fb88 L |
4706 | } |
4707 | ||
d9348dec VS |
4708 | static void skl_write_cursor_wm(struct intel_crtc *intel_crtc, |
4709 | const struct skl_plane_wm *wm, | |
4710 | const struct skl_ddb_allocation *ddb) | |
62e0fb88 L |
4711 | { |
4712 | struct drm_crtc *crtc = &intel_crtc->base; | |
4713 | struct drm_device *dev = crtc->dev; | |
4714 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5db94019 | 4715 | int level, max_level = ilk_wm_max_level(dev_priv); |
62e0fb88 L |
4716 | enum pipe pipe = intel_crtc->pipe; |
4717 | ||
4718 | for (level = 0; level <= max_level; level++) { | |
d8c0fafc | 4719 | skl_write_wm_level(dev_priv, CUR_WM(pipe, level), |
4720 | &wm->wm[level]); | |
62e0fb88 | 4721 | } |
d8c0fafc | 4722 | skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm); |
5d374d96 | 4723 | |
27082493 | 4724 | skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe), |
d8c0fafc | 4725 | &ddb->plane[pipe][PLANE_CURSOR]); |
2d41c0b5 PB |
4726 | } |
4727 | ||
45ece230 | 4728 | bool skl_wm_level_equals(const struct skl_wm_level *l1, |
4729 | const struct skl_wm_level *l2) | |
4730 | { | |
4731 | if (l1->plane_en != l2->plane_en) | |
4732 | return false; | |
4733 | ||
4734 | /* If both planes aren't enabled, the rest shouldn't matter */ | |
4735 | if (!l1->plane_en) | |
4736 | return true; | |
4737 | ||
4738 | return (l1->plane_res_l == l2->plane_res_l && | |
4739 | l1->plane_res_b == l2->plane_res_b); | |
4740 | } | |
4741 | ||
27082493 L |
4742 | static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a, |
4743 | const struct skl_ddb_entry *b) | |
0e8fb7ba | 4744 | { |
27082493 | 4745 | return a->start < b->end && b->start < a->end; |
0e8fb7ba DL |
4746 | } |
4747 | ||
5eff503b ML |
4748 | bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries, |
4749 | const struct skl_ddb_entry *ddb, | |
4750 | int ignore) | |
0e8fb7ba | 4751 | { |
ce0ba283 | 4752 | int i; |
0e8fb7ba | 4753 | |
5eff503b ML |
4754 | for (i = 0; i < I915_MAX_PIPES; i++) |
4755 | if (i != ignore && entries[i] && | |
4756 | skl_ddb_entries_overlap(ddb, entries[i])) | |
27082493 | 4757 | return true; |
0e8fb7ba | 4758 | |
27082493 | 4759 | return false; |
0e8fb7ba DL |
4760 | } |
4761 | ||
55994c2c | 4762 | static int skl_update_pipe_wm(struct drm_crtc_state *cstate, |
03af79e0 | 4763 | const struct skl_pipe_wm *old_pipe_wm, |
55994c2c | 4764 | struct skl_pipe_wm *pipe_wm, /* out */ |
03af79e0 | 4765 | struct skl_ddb_allocation *ddb, /* out */ |
55994c2c | 4766 | bool *changed /* out */) |
2d41c0b5 | 4767 | { |
f4a96752 | 4768 | struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate); |
55994c2c | 4769 | int ret; |
2d41c0b5 | 4770 | |
55994c2c MR |
4771 | ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm); |
4772 | if (ret) | |
4773 | return ret; | |
2d41c0b5 | 4774 | |
03af79e0 | 4775 | if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm))) |
55994c2c MR |
4776 | *changed = false; |
4777 | else | |
4778 | *changed = true; | |
2d41c0b5 | 4779 | |
55994c2c | 4780 | return 0; |
2d41c0b5 PB |
4781 | } |
4782 | ||
9b613022 MR |
4783 | static uint32_t |
4784 | pipes_modified(struct drm_atomic_state *state) | |
4785 | { | |
4786 | struct drm_crtc *crtc; | |
4787 | struct drm_crtc_state *cstate; | |
4788 | uint32_t i, ret = 0; | |
4789 | ||
6ebdb5a0 | 4790 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
9b613022 MR |
4791 | ret |= drm_crtc_mask(crtc); |
4792 | ||
4793 | return ret; | |
4794 | } | |
4795 | ||
bb7791bd | 4796 | static int |
9a30a261 RV |
4797 | skl_ddb_add_affected_planes(struct intel_crtc_state *cstate) |
4798 | { | |
4799 | struct drm_atomic_state *state = cstate->base.state; | |
4800 | struct drm_device *dev = state->dev; | |
4801 | struct drm_crtc *crtc = cstate->base.crtc; | |
4802 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
4803 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4804 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4805 | struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
4806 | struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
4807 | struct drm_plane_state *plane_state; | |
4808 | struct drm_plane *plane; | |
4809 | enum pipe pipe = intel_crtc->pipe; | |
4810 | ||
4811 | WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc)); | |
4812 | ||
4813 | drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) { | |
4814 | enum plane_id plane_id = to_intel_plane(plane)->id; | |
4815 | ||
4816 | if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][plane_id], | |
4817 | &new_ddb->plane[pipe][plane_id]) && | |
4818 | skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][plane_id], | |
4819 | &new_ddb->y_plane[pipe][plane_id])) | |
4820 | continue; | |
4821 | ||
4822 | plane_state = drm_atomic_get_plane_state(state, plane); | |
4823 | if (IS_ERR(plane_state)) | |
4824 | return PTR_ERR(plane_state); | |
4825 | } | |
4826 | ||
4827 | return 0; | |
4828 | } | |
4829 | ||
4830 | static int | |
4831 | skl_compute_ddb(struct drm_atomic_state *state) | |
98d39494 MR |
4832 | { |
4833 | struct drm_device *dev = state->dev; | |
4834 | struct drm_i915_private *dev_priv = to_i915(dev); | |
4835 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); | |
4836 | struct intel_crtc *intel_crtc; | |
734fa01f | 4837 | struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb; |
9b613022 | 4838 | uint32_t realloc_pipes = pipes_modified(state); |
98d39494 MR |
4839 | int ret; |
4840 | ||
4841 | /* | |
4842 | * If this is our first atomic update following hardware readout, | |
4843 | * we can't trust the DDB that the BIOS programmed for us. Let's | |
4844 | * pretend that all pipes switched active status so that we'll | |
4845 | * ensure a full DDB recompute. | |
4846 | */ | |
1b54a880 MR |
4847 | if (dev_priv->wm.distrust_bios_wm) { |
4848 | ret = drm_modeset_lock(&dev->mode_config.connection_mutex, | |
4849 | state->acquire_ctx); | |
4850 | if (ret) | |
4851 | return ret; | |
4852 | ||
98d39494 MR |
4853 | intel_state->active_pipe_changes = ~0; |
4854 | ||
1b54a880 MR |
4855 | /* |
4856 | * We usually only initialize intel_state->active_crtcs if we | |
4857 | * we're doing a modeset; make sure this field is always | |
4858 | * initialized during the sanitization process that happens | |
4859 | * on the first commit too. | |
4860 | */ | |
4861 | if (!intel_state->modeset) | |
4862 | intel_state->active_crtcs = dev_priv->active_crtcs; | |
4863 | } | |
4864 | ||
98d39494 MR |
4865 | /* |
4866 | * If the modeset changes which CRTC's are active, we need to | |
4867 | * recompute the DDB allocation for *all* active pipes, even | |
4868 | * those that weren't otherwise being modified in any way by this | |
4869 | * atomic commit. Due to the shrinking of the per-pipe allocations | |
4870 | * when new active CRTC's are added, it's possible for a pipe that | |
4871 | * we were already using and aren't changing at all here to suddenly | |
4872 | * become invalid if its DDB needs exceeds its new allocation. | |
4873 | * | |
4874 | * Note that if we wind up doing a full DDB recompute, we can't let | |
4875 | * any other display updates race with this transaction, so we need | |
4876 | * to grab the lock on *all* CRTC's. | |
4877 | */ | |
734fa01f | 4878 | if (intel_state->active_pipe_changes) { |
98d39494 | 4879 | realloc_pipes = ~0; |
734fa01f MR |
4880 | intel_state->wm_results.dirty_pipes = ~0; |
4881 | } | |
98d39494 | 4882 | |
5a920b85 PZ |
4883 | /* |
4884 | * We're not recomputing for the pipes not included in the commit, so | |
4885 | * make sure we start with the current state. | |
4886 | */ | |
4887 | memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb)); | |
4888 | ||
98d39494 MR |
4889 | for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) { |
4890 | struct intel_crtc_state *cstate; | |
4891 | ||
4892 | cstate = intel_atomic_get_crtc_state(state, intel_crtc); | |
4893 | if (IS_ERR(cstate)) | |
4894 | return PTR_ERR(cstate); | |
9a30a261 RV |
4895 | |
4896 | ret = skl_allocate_pipe_ddb(cstate, ddb); | |
4897 | if (ret) | |
4898 | return ret; | |
4899 | ||
4900 | ret = skl_ddb_add_affected_planes(cstate); | |
4901 | if (ret) | |
4902 | return ret; | |
98d39494 MR |
4903 | } |
4904 | ||
4905 | return 0; | |
4906 | } | |
4907 | ||
2722efb9 MR |
4908 | static void |
4909 | skl_copy_wm_for_pipe(struct skl_wm_values *dst, | |
4910 | struct skl_wm_values *src, | |
4911 | enum pipe pipe) | |
4912 | { | |
2722efb9 MR |
4913 | memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe], |
4914 | sizeof(dst->ddb.y_plane[pipe])); | |
4915 | memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe], | |
4916 | sizeof(dst->ddb.plane[pipe])); | |
4917 | } | |
4918 | ||
413fc530 | 4919 | static void |
4920 | skl_print_wm_changes(const struct drm_atomic_state *state) | |
4921 | { | |
4922 | const struct drm_device *dev = state->dev; | |
4923 | const struct drm_i915_private *dev_priv = to_i915(dev); | |
4924 | const struct intel_atomic_state *intel_state = | |
4925 | to_intel_atomic_state(state); | |
4926 | const struct drm_crtc *crtc; | |
4927 | const struct drm_crtc_state *cstate; | |
413fc530 | 4928 | const struct intel_plane *intel_plane; |
413fc530 | 4929 | const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb; |
4930 | const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb; | |
7570498e | 4931 | int i; |
413fc530 | 4932 | |
6ebdb5a0 | 4933 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
7570498e ML |
4934 | const struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4935 | enum pipe pipe = intel_crtc->pipe; | |
413fc530 | 4936 | |
7570498e | 4937 | for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) { |
d5cdfdf5 | 4938 | enum plane_id plane_id = intel_plane->id; |
413fc530 | 4939 | const struct skl_ddb_entry *old, *new; |
4940 | ||
d5cdfdf5 VS |
4941 | old = &old_ddb->plane[pipe][plane_id]; |
4942 | new = &new_ddb->plane[pipe][plane_id]; | |
413fc530 | 4943 | |
413fc530 | 4944 | if (skl_ddb_entry_equal(old, new)) |
4945 | continue; | |
4946 | ||
7570498e ML |
4947 | DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n", |
4948 | intel_plane->base.base.id, | |
4949 | intel_plane->base.name, | |
4950 | old->start, old->end, | |
4951 | new->start, new->end); | |
413fc530 | 4952 | } |
4953 | } | |
4954 | } | |
4955 | ||
98d39494 MR |
4956 | static int |
4957 | skl_compute_wm(struct drm_atomic_state *state) | |
4958 | { | |
4959 | struct drm_crtc *crtc; | |
4960 | struct drm_crtc_state *cstate; | |
734fa01f MR |
4961 | struct intel_atomic_state *intel_state = to_intel_atomic_state(state); |
4962 | struct skl_wm_values *results = &intel_state->wm_results; | |
367d73d2 | 4963 | struct drm_device *dev = state->dev; |
734fa01f | 4964 | struct skl_pipe_wm *pipe_wm; |
98d39494 | 4965 | bool changed = false; |
734fa01f | 4966 | int ret, i; |
98d39494 | 4967 | |
367d73d2 ML |
4968 | /* |
4969 | * When we distrust bios wm we always need to recompute to set the | |
4970 | * expected DDB allocations for each CRTC. | |
4971 | */ | |
4972 | if (to_i915(dev)->wm.distrust_bios_wm) | |
4973 | changed = true; | |
4974 | ||
98d39494 MR |
4975 | /* |
4976 | * If this transaction isn't actually touching any CRTC's, don't | |
4977 | * bother with watermark calculation. Note that if we pass this | |
4978 | * test, we're guaranteed to hold at least one CRTC state mutex, | |
4979 | * which means we can safely use values like dev_priv->active_crtcs | |
4980 | * since any racing commits that want to update them would need to | |
4981 | * hold _all_ CRTC state mutexes. | |
4982 | */ | |
6ebdb5a0 | 4983 | for_each_new_crtc_in_state(state, crtc, cstate, i) |
98d39494 | 4984 | changed = true; |
367d73d2 | 4985 | |
98d39494 MR |
4986 | if (!changed) |
4987 | return 0; | |
4988 | ||
734fa01f MR |
4989 | /* Clear all dirty flags */ |
4990 | results->dirty_pipes = 0; | |
4991 | ||
9a30a261 | 4992 | ret = skl_compute_ddb(state); |
98d39494 MR |
4993 | if (ret) |
4994 | return ret; | |
4995 | ||
734fa01f MR |
4996 | /* |
4997 | * Calculate WM's for all pipes that are part of this transaction. | |
4998 | * Note that the DDB allocation above may have added more CRTC's that | |
4999 | * weren't otherwise being modified (and set bits in dirty_pipes) if | |
5000 | * pipe allocations had to change. | |
5001 | * | |
5002 | * FIXME: Now that we're doing this in the atomic check phase, we | |
5003 | * should allow skl_update_pipe_wm() to return failure in cases where | |
5004 | * no suitable watermark values can be found. | |
5005 | */ | |
6ebdb5a0 | 5006 | for_each_new_crtc_in_state(state, crtc, cstate, i) { |
734fa01f MR |
5007 | struct intel_crtc_state *intel_cstate = |
5008 | to_intel_crtc_state(cstate); | |
03af79e0 ML |
5009 | const struct skl_pipe_wm *old_pipe_wm = |
5010 | &to_intel_crtc_state(crtc->state)->wm.skl.optimal; | |
734fa01f MR |
5011 | |
5012 | pipe_wm = &intel_cstate->wm.skl.optimal; | |
03af79e0 ML |
5013 | ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm, |
5014 | &results->ddb, &changed); | |
734fa01f MR |
5015 | if (ret) |
5016 | return ret; | |
5017 | ||
5018 | if (changed) | |
5019 | results->dirty_pipes |= drm_crtc_mask(crtc); | |
5020 | ||
5021 | if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0) | |
5022 | /* This pipe's WM's did not change */ | |
5023 | continue; | |
5024 | ||
5025 | intel_cstate->update_wm_pre = true; | |
734fa01f MR |
5026 | } |
5027 | ||
413fc530 | 5028 | skl_print_wm_changes(state); |
5029 | ||
98d39494 MR |
5030 | return 0; |
5031 | } | |
5032 | ||
ccf010fb ML |
5033 | static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state, |
5034 | struct intel_crtc_state *cstate) | |
5035 | { | |
5036 | struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc); | |
5037 | struct drm_i915_private *dev_priv = to_i915(state->base.dev); | |
5038 | struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal; | |
e62929b3 | 5039 | const struct skl_ddb_allocation *ddb = &state->wm_results.ddb; |
ccf010fb | 5040 | enum pipe pipe = crtc->pipe; |
d5cdfdf5 | 5041 | enum plane_id plane_id; |
e62929b3 ML |
5042 | |
5043 | if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base))) | |
5044 | return; | |
ccf010fb ML |
5045 | |
5046 | I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime); | |
e62929b3 | 5047 | |
d5cdfdf5 VS |
5048 | for_each_plane_id_on_crtc(crtc, plane_id) { |
5049 | if (plane_id != PLANE_CURSOR) | |
5050 | skl_write_plane_wm(crtc, &pipe_wm->planes[plane_id], | |
5051 | ddb, plane_id); | |
5052 | else | |
5053 | skl_write_cursor_wm(crtc, &pipe_wm->planes[plane_id], | |
5054 | ddb); | |
5055 | } | |
ccf010fb ML |
5056 | } |
5057 | ||
e62929b3 ML |
5058 | static void skl_initial_wm(struct intel_atomic_state *state, |
5059 | struct intel_crtc_state *cstate) | |
2d41c0b5 | 5060 | { |
e62929b3 | 5061 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); |
432081bc | 5062 | struct drm_device *dev = intel_crtc->base.dev; |
fac5e23e | 5063 | struct drm_i915_private *dev_priv = to_i915(dev); |
e62929b3 | 5064 | struct skl_wm_values *results = &state->wm_results; |
2722efb9 | 5065 | struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw; |
27082493 | 5066 | enum pipe pipe = intel_crtc->pipe; |
adda50b8 | 5067 | |
432081bc | 5068 | if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0) |
2d41c0b5 PB |
5069 | return; |
5070 | ||
734fa01f | 5071 | mutex_lock(&dev_priv->wm.wm_mutex); |
2d41c0b5 | 5072 | |
e62929b3 ML |
5073 | if (cstate->base.active_changed) |
5074 | skl_atomic_update_crtc_wm(state, cstate); | |
27082493 L |
5075 | |
5076 | skl_copy_wm_for_pipe(hw_vals, results, pipe); | |
734fa01f MR |
5077 | |
5078 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
2d41c0b5 PB |
5079 | } |
5080 | ||
d890565c VS |
5081 | static void ilk_compute_wm_config(struct drm_device *dev, |
5082 | struct intel_wm_config *config) | |
5083 | { | |
5084 | struct intel_crtc *crtc; | |
5085 | ||
5086 | /* Compute the currently _active_ config */ | |
5087 | for_each_intel_crtc(dev, crtc) { | |
5088 | const struct intel_pipe_wm *wm = &crtc->wm.active.ilk; | |
5089 | ||
5090 | if (!wm->pipe_enabled) | |
5091 | continue; | |
5092 | ||
5093 | config->sprites_enabled |= wm->sprites_enabled; | |
5094 | config->sprites_scaled |= wm->sprites_scaled; | |
5095 | config->num_pipes_active++; | |
5096 | } | |
5097 | } | |
5098 | ||
ed4a6a7c | 5099 | static void ilk_program_watermarks(struct drm_i915_private *dev_priv) |
801bcfff | 5100 | { |
91c8a326 | 5101 | struct drm_device *dev = &dev_priv->drm; |
b9d5c839 | 5102 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
820c1980 | 5103 | struct ilk_wm_maximums max; |
d890565c | 5104 | struct intel_wm_config config = {}; |
820c1980 | 5105 | struct ilk_wm_values results = {}; |
77c122bc | 5106 | enum intel_ddb_partitioning partitioning; |
261a27d1 | 5107 | |
d890565c VS |
5108 | ilk_compute_wm_config(dev, &config); |
5109 | ||
5110 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); | |
5111 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); | |
a485bfb8 VS |
5112 | |
5113 | /* 5/6 split only in single pipe config on IVB+ */ | |
175fded1 | 5114 | if (INTEL_GEN(dev_priv) >= 7 && |
d890565c VS |
5115 | config.num_pipes_active == 1 && config.sprites_enabled) { |
5116 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); | |
5117 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); | |
0362c781 | 5118 | |
820c1980 | 5119 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 5120 | } else { |
198a1e9b | 5121 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
5122 | } |
5123 | ||
198a1e9b | 5124 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 5125 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 5126 | |
820c1980 | 5127 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 5128 | |
820c1980 | 5129 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
5130 | } |
5131 | ||
ccf010fb ML |
5132 | static void ilk_initial_watermarks(struct intel_atomic_state *state, |
5133 | struct intel_crtc_state *cstate) | |
b9d5c839 | 5134 | { |
ed4a6a7c MR |
5135 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); |
5136 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
b9d5c839 | 5137 | |
ed4a6a7c | 5138 | mutex_lock(&dev_priv->wm.wm_mutex); |
e8f1f02e | 5139 | intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate; |
ed4a6a7c MR |
5140 | ilk_program_watermarks(dev_priv); |
5141 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
5142 | } | |
bf220452 | 5143 | |
ccf010fb ML |
5144 | static void ilk_optimize_watermarks(struct intel_atomic_state *state, |
5145 | struct intel_crtc_state *cstate) | |
ed4a6a7c MR |
5146 | { |
5147 | struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev); | |
5148 | struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc); | |
bf220452 | 5149 | |
ed4a6a7c MR |
5150 | mutex_lock(&dev_priv->wm.wm_mutex); |
5151 | if (cstate->wm.need_postvbl_update) { | |
e8f1f02e | 5152 | intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal; |
ed4a6a7c MR |
5153 | ilk_program_watermarks(dev_priv); |
5154 | } | |
5155 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
b9d5c839 VS |
5156 | } |
5157 | ||
d8c0fafc | 5158 | static inline void skl_wm_level_from_reg_val(uint32_t val, |
5159 | struct skl_wm_level *level) | |
3078999f | 5160 | { |
d8c0fafc | 5161 | level->plane_en = val & PLANE_WM_EN; |
5162 | level->plane_res_b = val & PLANE_WM_BLOCKS_MASK; | |
5163 | level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) & | |
5164 | PLANE_WM_LINES_MASK; | |
3078999f PB |
5165 | } |
5166 | ||
bf9d99ad | 5167 | void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc, |
5168 | struct skl_pipe_wm *out) | |
3078999f | 5169 | { |
d5cdfdf5 | 5170 | struct drm_i915_private *dev_priv = to_i915(crtc->dev); |
3078999f | 5171 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3078999f | 5172 | enum pipe pipe = intel_crtc->pipe; |
d5cdfdf5 VS |
5173 | int level, max_level; |
5174 | enum plane_id plane_id; | |
d8c0fafc | 5175 | uint32_t val; |
3078999f | 5176 | |
5db94019 | 5177 | max_level = ilk_wm_max_level(dev_priv); |
3078999f | 5178 | |
d5cdfdf5 VS |
5179 | for_each_plane_id_on_crtc(intel_crtc, plane_id) { |
5180 | struct skl_plane_wm *wm = &out->planes[plane_id]; | |
3078999f | 5181 | |
d8c0fafc | 5182 | for (level = 0; level <= max_level; level++) { |
d5cdfdf5 VS |
5183 | if (plane_id != PLANE_CURSOR) |
5184 | val = I915_READ(PLANE_WM(pipe, plane_id, level)); | |
d8c0fafc | 5185 | else |
5186 | val = I915_READ(CUR_WM(pipe, level)); | |
3078999f | 5187 | |
d8c0fafc | 5188 | skl_wm_level_from_reg_val(val, &wm->wm[level]); |
3078999f | 5189 | } |
3078999f | 5190 | |
d5cdfdf5 VS |
5191 | if (plane_id != PLANE_CURSOR) |
5192 | val = I915_READ(PLANE_WM_TRANS(pipe, plane_id)); | |
d8c0fafc | 5193 | else |
5194 | val = I915_READ(CUR_WM_TRANS(pipe)); | |
5195 | ||
5196 | skl_wm_level_from_reg_val(val, &wm->trans_wm); | |
3078999f PB |
5197 | } |
5198 | ||
d8c0fafc | 5199 | if (!intel_crtc->active) |
5200 | return; | |
4e0963c7 | 5201 | |
bf9d99ad | 5202 | out->linetime = I915_READ(PIPE_WM_LINETIME(pipe)); |
3078999f PB |
5203 | } |
5204 | ||
5205 | void skl_wm_get_hw_state(struct drm_device *dev) | |
5206 | { | |
fac5e23e | 5207 | struct drm_i915_private *dev_priv = to_i915(dev); |
bf9d99ad | 5208 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; |
a269c583 | 5209 | struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb; |
3078999f | 5210 | struct drm_crtc *crtc; |
bf9d99ad | 5211 | struct intel_crtc *intel_crtc; |
5212 | struct intel_crtc_state *cstate; | |
3078999f | 5213 | |
a269c583 | 5214 | skl_ddb_get_hw_state(dev_priv, ddb); |
bf9d99ad | 5215 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) { |
5216 | intel_crtc = to_intel_crtc(crtc); | |
5217 | cstate = to_intel_crtc_state(crtc->state); | |
5218 | ||
5219 | skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal); | |
5220 | ||
03af79e0 | 5221 | if (intel_crtc->active) |
bf9d99ad | 5222 | hw->dirty_pipes |= drm_crtc_mask(crtc); |
bf9d99ad | 5223 | } |
a1de91e5 | 5224 | |
279e99d7 MR |
5225 | if (dev_priv->active_crtcs) { |
5226 | /* Fully recompute DDB on first atomic commit */ | |
5227 | dev_priv->wm.distrust_bios_wm = true; | |
5228 | } else { | |
5229 | /* Easy/common case; just sanitize DDB now if everything off */ | |
5230 | memset(ddb, 0, sizeof(*ddb)); | |
5231 | } | |
3078999f PB |
5232 | } |
5233 | ||
243e6a44 VS |
5234 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
5235 | { | |
5236 | struct drm_device *dev = crtc->dev; | |
fac5e23e | 5237 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 5238 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 | 5239 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
4e0963c7 | 5240 | struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state); |
e8f1f02e | 5241 | struct intel_pipe_wm *active = &cstate->wm.ilk.optimal; |
243e6a44 | 5242 | enum pipe pipe = intel_crtc->pipe; |
f0f59a00 | 5243 | static const i915_reg_t wm0_pipe_reg[] = { |
243e6a44 VS |
5244 | [PIPE_A] = WM0_PIPEA_ILK, |
5245 | [PIPE_B] = WM0_PIPEB_ILK, | |
5246 | [PIPE_C] = WM0_PIPEC_IVB, | |
5247 | }; | |
5248 | ||
5249 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
8652744b | 5250 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ce0e0713 | 5251 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 5252 | |
15606534 VS |
5253 | memset(active, 0, sizeof(*active)); |
5254 | ||
3ef00284 | 5255 | active->pipe_enabled = intel_crtc->active; |
2a44b76b VS |
5256 | |
5257 | if (active->pipe_enabled) { | |
243e6a44 VS |
5258 | u32 tmp = hw->wm_pipe[pipe]; |
5259 | ||
5260 | /* | |
5261 | * For active pipes LP0 watermark is marked as | |
5262 | * enabled, and LP1+ watermaks as disabled since | |
5263 | * we can't really reverse compute them in case | |
5264 | * multiple pipes are active. | |
5265 | */ | |
5266 | active->wm[0].enable = true; | |
5267 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
5268 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
5269 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
5270 | active->linetime = hw->wm_linetime[pipe]; | |
5271 | } else { | |
5db94019 | 5272 | int level, max_level = ilk_wm_max_level(dev_priv); |
243e6a44 VS |
5273 | |
5274 | /* | |
5275 | * For inactive pipes, all watermark levels | |
5276 | * should be marked as enabled but zeroed, | |
5277 | * which is what we'd compute them to. | |
5278 | */ | |
5279 | for (level = 0; level <= max_level; level++) | |
5280 | active->wm[level].enable = true; | |
5281 | } | |
4e0963c7 MR |
5282 | |
5283 | intel_crtc->wm.active.ilk = *active; | |
243e6a44 VS |
5284 | } |
5285 | ||
6eb1a681 VS |
5286 | #define _FW_WM(value, plane) \ |
5287 | (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT) | |
5288 | #define _FW_WM_VLV(value, plane) \ | |
5289 | (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT) | |
5290 | ||
04548cba VS |
5291 | static void g4x_read_wm_values(struct drm_i915_private *dev_priv, |
5292 | struct g4x_wm_values *wm) | |
5293 | { | |
5294 | uint32_t tmp; | |
5295 | ||
5296 | tmp = I915_READ(DSPFW1); | |
5297 | wm->sr.plane = _FW_WM(tmp, SR); | |
5298 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); | |
5299 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEB); | |
5300 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM(tmp, PLANEA); | |
5301 | ||
5302 | tmp = I915_READ(DSPFW2); | |
5303 | wm->fbc_en = tmp & DSPFW_FBC_SR_EN; | |
5304 | wm->sr.fbc = _FW_WM(tmp, FBC_SR); | |
5305 | wm->hpll.fbc = _FW_WM(tmp, FBC_HPLL_SR); | |
5306 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEB); | |
5307 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
5308 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM(tmp, SPRITEA); | |
5309 | ||
5310 | tmp = I915_READ(DSPFW3); | |
5311 | wm->hpll_en = tmp & DSPFW_HPLL_SR_EN; | |
5312 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
5313 | wm->hpll.cursor = _FW_WM(tmp, HPLL_CURSOR); | |
5314 | wm->hpll.plane = _FW_WM(tmp, HPLL_SR); | |
5315 | } | |
5316 | ||
6eb1a681 VS |
5317 | static void vlv_read_wm_values(struct drm_i915_private *dev_priv, |
5318 | struct vlv_wm_values *wm) | |
5319 | { | |
5320 | enum pipe pipe; | |
5321 | uint32_t tmp; | |
5322 | ||
5323 | for_each_pipe(dev_priv, pipe) { | |
5324 | tmp = I915_READ(VLV_DDL(pipe)); | |
5325 | ||
1b31389c | 5326 | wm->ddl[pipe].plane[PLANE_PRIMARY] = |
6eb1a681 | 5327 | (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5328 | wm->ddl[pipe].plane[PLANE_CURSOR] = |
6eb1a681 | 5329 | (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5330 | wm->ddl[pipe].plane[PLANE_SPRITE0] = |
6eb1a681 | 5331 | (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
1b31389c | 5332 | wm->ddl[pipe].plane[PLANE_SPRITE1] = |
6eb1a681 VS |
5333 | (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK); |
5334 | } | |
5335 | ||
5336 | tmp = I915_READ(DSPFW1); | |
5337 | wm->sr.plane = _FW_WM(tmp, SR); | |
1b31389c VS |
5338 | wm->pipe[PIPE_B].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORB); |
5339 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEB); | |
5340 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEA); | |
6eb1a681 VS |
5341 | |
5342 | tmp = I915_READ(DSPFW2); | |
1b31389c VS |
5343 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEB); |
5344 | wm->pipe[PIPE_A].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORA); | |
5345 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEA); | |
6eb1a681 VS |
5346 | |
5347 | tmp = I915_READ(DSPFW3); | |
5348 | wm->sr.cursor = _FW_WM(tmp, CURSOR_SR); | |
5349 | ||
5350 | if (IS_CHERRYVIEW(dev_priv)) { | |
5351 | tmp = I915_READ(DSPFW7_CHV); | |
1b31389c VS |
5352 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
5353 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
5354 | |
5355 | tmp = I915_READ(DSPFW8_CHV); | |
1b31389c VS |
5356 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITEF); |
5357 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEE); | |
6eb1a681 VS |
5358 | |
5359 | tmp = I915_READ(DSPFW9_CHV); | |
1b31389c VS |
5360 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] = _FW_WM_VLV(tmp, PLANEC); |
5361 | wm->pipe[PIPE_C].plane[PLANE_CURSOR] = _FW_WM(tmp, CURSORC); | |
6eb1a681 VS |
5362 | |
5363 | tmp = I915_READ(DSPHOWM); | |
5364 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
5365 | wm->pipe[PIPE_C].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEF_HI) << 8; |
5366 | wm->pipe[PIPE_C].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEE_HI) << 8; | |
5367 | wm->pipe[PIPE_C].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEC_HI) << 8; | |
5368 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; | |
5369 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
5370 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
5371 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
5372 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
5373 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
5374 | } else { |
5375 | tmp = I915_READ(DSPFW7); | |
1b31389c VS |
5376 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] = _FW_WM_VLV(tmp, SPRITED); |
5377 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] = _FW_WM_VLV(tmp, SPRITEC); | |
6eb1a681 VS |
5378 | |
5379 | tmp = I915_READ(DSPHOWM); | |
5380 | wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9; | |
1b31389c VS |
5381 | wm->pipe[PIPE_B].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITED_HI) << 8; |
5382 | wm->pipe[PIPE_B].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEC_HI) << 8; | |
5383 | wm->pipe[PIPE_B].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEB_HI) << 8; | |
5384 | wm->pipe[PIPE_A].plane[PLANE_SPRITE1] |= _FW_WM(tmp, SPRITEB_HI) << 8; | |
5385 | wm->pipe[PIPE_A].plane[PLANE_SPRITE0] |= _FW_WM(tmp, SPRITEA_HI) << 8; | |
5386 | wm->pipe[PIPE_A].plane[PLANE_PRIMARY] |= _FW_WM(tmp, PLANEA_HI) << 8; | |
6eb1a681 VS |
5387 | } |
5388 | } | |
5389 | ||
5390 | #undef _FW_WM | |
5391 | #undef _FW_WM_VLV | |
5392 | ||
04548cba VS |
5393 | void g4x_wm_get_hw_state(struct drm_device *dev) |
5394 | { | |
5395 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5396 | struct g4x_wm_values *wm = &dev_priv->wm.g4x; | |
5397 | struct intel_crtc *crtc; | |
5398 | ||
5399 | g4x_read_wm_values(dev_priv, wm); | |
5400 | ||
5401 | wm->cxsr = I915_READ(FW_BLC_SELF) & FW_BLC_SELF_EN; | |
5402 | ||
5403 | for_each_intel_crtc(dev, crtc) { | |
5404 | struct intel_crtc_state *crtc_state = | |
5405 | to_intel_crtc_state(crtc->base.state); | |
5406 | struct g4x_wm_state *active = &crtc->wm.active.g4x; | |
5407 | struct g4x_pipe_wm *raw; | |
5408 | enum pipe pipe = crtc->pipe; | |
5409 | enum plane_id plane_id; | |
5410 | int level, max_level; | |
5411 | ||
5412 | active->cxsr = wm->cxsr; | |
5413 | active->hpll_en = wm->hpll_en; | |
5414 | active->fbc_en = wm->fbc_en; | |
5415 | ||
5416 | active->sr = wm->sr; | |
5417 | active->hpll = wm->hpll; | |
5418 | ||
5419 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
5420 | active->wm.plane[plane_id] = | |
5421 | wm->pipe[pipe].plane[plane_id]; | |
5422 | } | |
5423 | ||
5424 | if (wm->cxsr && wm->hpll_en) | |
5425 | max_level = G4X_WM_LEVEL_HPLL; | |
5426 | else if (wm->cxsr) | |
5427 | max_level = G4X_WM_LEVEL_SR; | |
5428 | else | |
5429 | max_level = G4X_WM_LEVEL_NORMAL; | |
5430 | ||
5431 | level = G4X_WM_LEVEL_NORMAL; | |
5432 | raw = &crtc_state->wm.g4x.raw[level]; | |
5433 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5434 | raw->plane[plane_id] = active->wm.plane[plane_id]; | |
5435 | ||
5436 | if (++level > max_level) | |
5437 | goto out; | |
5438 | ||
5439 | raw = &crtc_state->wm.g4x.raw[level]; | |
5440 | raw->plane[PLANE_PRIMARY] = active->sr.plane; | |
5441 | raw->plane[PLANE_CURSOR] = active->sr.cursor; | |
5442 | raw->plane[PLANE_SPRITE0] = 0; | |
5443 | raw->fbc = active->sr.fbc; | |
5444 | ||
5445 | if (++level > max_level) | |
5446 | goto out; | |
5447 | ||
5448 | raw = &crtc_state->wm.g4x.raw[level]; | |
5449 | raw->plane[PLANE_PRIMARY] = active->hpll.plane; | |
5450 | raw->plane[PLANE_CURSOR] = active->hpll.cursor; | |
5451 | raw->plane[PLANE_SPRITE0] = 0; | |
5452 | raw->fbc = active->hpll.fbc; | |
5453 | ||
5454 | out: | |
5455 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5456 | g4x_raw_plane_wm_set(crtc_state, level, | |
5457 | plane_id, USHRT_MAX); | |
5458 | g4x_raw_fbc_wm_set(crtc_state, level, USHRT_MAX); | |
5459 | ||
5460 | crtc_state->wm.g4x.optimal = *active; | |
5461 | crtc_state->wm.g4x.intermediate = *active; | |
5462 | ||
5463 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite=%d\n", | |
5464 | pipe_name(pipe), | |
5465 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
5466 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
5467 | wm->pipe[pipe].plane[PLANE_SPRITE0]); | |
5468 | } | |
5469 | ||
5470 | DRM_DEBUG_KMS("Initial SR watermarks: plane=%d, cursor=%d fbc=%d\n", | |
5471 | wm->sr.plane, wm->sr.cursor, wm->sr.fbc); | |
5472 | DRM_DEBUG_KMS("Initial HPLL watermarks: plane=%d, SR cursor=%d fbc=%d\n", | |
5473 | wm->hpll.plane, wm->hpll.cursor, wm->hpll.fbc); | |
5474 | DRM_DEBUG_KMS("Initial SR=%s HPLL=%s FBC=%s\n", | |
5475 | yesno(wm->cxsr), yesno(wm->hpll_en), yesno(wm->fbc_en)); | |
5476 | } | |
5477 | ||
5478 | void g4x_wm_sanitize(struct drm_i915_private *dev_priv) | |
5479 | { | |
5480 | struct intel_plane *plane; | |
5481 | struct intel_crtc *crtc; | |
5482 | ||
5483 | mutex_lock(&dev_priv->wm.wm_mutex); | |
5484 | ||
5485 | for_each_intel_plane(&dev_priv->drm, plane) { | |
5486 | struct intel_crtc *crtc = | |
5487 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
5488 | struct intel_crtc_state *crtc_state = | |
5489 | to_intel_crtc_state(crtc->base.state); | |
5490 | struct intel_plane_state *plane_state = | |
5491 | to_intel_plane_state(plane->base.state); | |
5492 | struct g4x_wm_state *wm_state = &crtc_state->wm.g4x.optimal; | |
5493 | enum plane_id plane_id = plane->id; | |
5494 | int level; | |
5495 | ||
5496 | if (plane_state->base.visible) | |
5497 | continue; | |
5498 | ||
5499 | for (level = 0; level < 3; level++) { | |
5500 | struct g4x_pipe_wm *raw = | |
5501 | &crtc_state->wm.g4x.raw[level]; | |
5502 | ||
5503 | raw->plane[plane_id] = 0; | |
5504 | wm_state->wm.plane[plane_id] = 0; | |
5505 | } | |
5506 | ||
5507 | if (plane_id == PLANE_PRIMARY) { | |
5508 | for (level = 0; level < 3; level++) { | |
5509 | struct g4x_pipe_wm *raw = | |
5510 | &crtc_state->wm.g4x.raw[level]; | |
5511 | raw->fbc = 0; | |
5512 | } | |
5513 | ||
5514 | wm_state->sr.fbc = 0; | |
5515 | wm_state->hpll.fbc = 0; | |
5516 | wm_state->fbc_en = false; | |
5517 | } | |
5518 | } | |
5519 | ||
5520 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
5521 | struct intel_crtc_state *crtc_state = | |
5522 | to_intel_crtc_state(crtc->base.state); | |
5523 | ||
5524 | crtc_state->wm.g4x.intermediate = | |
5525 | crtc_state->wm.g4x.optimal; | |
5526 | crtc->wm.active.g4x = crtc_state->wm.g4x.optimal; | |
5527 | } | |
5528 | ||
5529 | g4x_program_watermarks(dev_priv); | |
5530 | ||
5531 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
5532 | } | |
5533 | ||
6eb1a681 VS |
5534 | void vlv_wm_get_hw_state(struct drm_device *dev) |
5535 | { | |
5536 | struct drm_i915_private *dev_priv = to_i915(dev); | |
5537 | struct vlv_wm_values *wm = &dev_priv->wm.vlv; | |
f07d43d2 | 5538 | struct intel_crtc *crtc; |
6eb1a681 VS |
5539 | u32 val; |
5540 | ||
5541 | vlv_read_wm_values(dev_priv, wm); | |
5542 | ||
6eb1a681 VS |
5543 | wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN; |
5544 | wm->level = VLV_WM_LEVEL_PM2; | |
5545 | ||
5546 | if (IS_CHERRYVIEW(dev_priv)) { | |
5547 | mutex_lock(&dev_priv->rps.hw_lock); | |
5548 | ||
5549 | val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ); | |
5550 | if (val & DSP_MAXFIFO_PM5_ENABLE) | |
5551 | wm->level = VLV_WM_LEVEL_PM5; | |
5552 | ||
58590c14 VS |
5553 | /* |
5554 | * If DDR DVFS is disabled in the BIOS, Punit | |
5555 | * will never ack the request. So if that happens | |
5556 | * assume we don't have to enable/disable DDR DVFS | |
5557 | * dynamically. To test that just set the REQ_ACK | |
5558 | * bit to poke the Punit, but don't change the | |
5559 | * HIGH/LOW bits so that we don't actually change | |
5560 | * the current state. | |
5561 | */ | |
6eb1a681 | 5562 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); |
58590c14 VS |
5563 | val |= FORCE_DDR_FREQ_REQ_ACK; |
5564 | vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val); | |
5565 | ||
5566 | if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) & | |
5567 | FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) { | |
5568 | DRM_DEBUG_KMS("Punit not acking DDR DVFS request, " | |
5569 | "assuming DDR DVFS is disabled\n"); | |
5570 | dev_priv->wm.max_level = VLV_WM_LEVEL_PM5; | |
5571 | } else { | |
5572 | val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2); | |
5573 | if ((val & FORCE_DDR_HIGH_FREQ) == 0) | |
5574 | wm->level = VLV_WM_LEVEL_DDR_DVFS; | |
5575 | } | |
6eb1a681 VS |
5576 | |
5577 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5578 | } | |
5579 | ||
ff32c54e VS |
5580 | for_each_intel_crtc(dev, crtc) { |
5581 | struct intel_crtc_state *crtc_state = | |
5582 | to_intel_crtc_state(crtc->base.state); | |
5583 | struct vlv_wm_state *active = &crtc->wm.active.vlv; | |
5584 | const struct vlv_fifo_state *fifo_state = | |
5585 | &crtc_state->wm.vlv.fifo_state; | |
5586 | enum pipe pipe = crtc->pipe; | |
5587 | enum plane_id plane_id; | |
5588 | int level; | |
5589 | ||
5590 | vlv_get_fifo_size(crtc_state); | |
5591 | ||
5592 | active->num_levels = wm->level + 1; | |
5593 | active->cxsr = wm->cxsr; | |
5594 | ||
ff32c54e | 5595 | for (level = 0; level < active->num_levels; level++) { |
114d7dc0 | 5596 | struct g4x_pipe_wm *raw = |
ff32c54e VS |
5597 | &crtc_state->wm.vlv.raw[level]; |
5598 | ||
5599 | active->sr[level].plane = wm->sr.plane; | |
5600 | active->sr[level].cursor = wm->sr.cursor; | |
5601 | ||
5602 | for_each_plane_id_on_crtc(crtc, plane_id) { | |
5603 | active->wm[level].plane[plane_id] = | |
5604 | wm->pipe[pipe].plane[plane_id]; | |
5605 | ||
5606 | raw->plane[plane_id] = | |
5607 | vlv_invert_wm_value(active->wm[level].plane[plane_id], | |
5608 | fifo_state->plane[plane_id]); | |
5609 | } | |
5610 | } | |
5611 | ||
5612 | for_each_plane_id_on_crtc(crtc, plane_id) | |
5613 | vlv_raw_plane_wm_set(crtc_state, level, | |
5614 | plane_id, USHRT_MAX); | |
5615 | vlv_invalidate_wms(crtc, active, level); | |
5616 | ||
5617 | crtc_state->wm.vlv.optimal = *active; | |
4841da51 | 5618 | crtc_state->wm.vlv.intermediate = *active; |
ff32c54e | 5619 | |
6eb1a681 | 5620 | DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n", |
1b31389c VS |
5621 | pipe_name(pipe), |
5622 | wm->pipe[pipe].plane[PLANE_PRIMARY], | |
5623 | wm->pipe[pipe].plane[PLANE_CURSOR], | |
5624 | wm->pipe[pipe].plane[PLANE_SPRITE0], | |
5625 | wm->pipe[pipe].plane[PLANE_SPRITE1]); | |
ff32c54e | 5626 | } |
6eb1a681 VS |
5627 | |
5628 | DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n", | |
5629 | wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr); | |
5630 | } | |
5631 | ||
602ae835 VS |
5632 | void vlv_wm_sanitize(struct drm_i915_private *dev_priv) |
5633 | { | |
5634 | struct intel_plane *plane; | |
5635 | struct intel_crtc *crtc; | |
5636 | ||
5637 | mutex_lock(&dev_priv->wm.wm_mutex); | |
5638 | ||
5639 | for_each_intel_plane(&dev_priv->drm, plane) { | |
5640 | struct intel_crtc *crtc = | |
5641 | intel_get_crtc_for_pipe(dev_priv, plane->pipe); | |
5642 | struct intel_crtc_state *crtc_state = | |
5643 | to_intel_crtc_state(crtc->base.state); | |
5644 | struct intel_plane_state *plane_state = | |
5645 | to_intel_plane_state(plane->base.state); | |
5646 | struct vlv_wm_state *wm_state = &crtc_state->wm.vlv.optimal; | |
5647 | const struct vlv_fifo_state *fifo_state = | |
5648 | &crtc_state->wm.vlv.fifo_state; | |
5649 | enum plane_id plane_id = plane->id; | |
5650 | int level; | |
5651 | ||
5652 | if (plane_state->base.visible) | |
5653 | continue; | |
5654 | ||
5655 | for (level = 0; level < wm_state->num_levels; level++) { | |
114d7dc0 | 5656 | struct g4x_pipe_wm *raw = |
602ae835 VS |
5657 | &crtc_state->wm.vlv.raw[level]; |
5658 | ||
5659 | raw->plane[plane_id] = 0; | |
5660 | ||
5661 | wm_state->wm[level].plane[plane_id] = | |
5662 | vlv_invert_wm_value(raw->plane[plane_id], | |
5663 | fifo_state->plane[plane_id]); | |
5664 | } | |
5665 | } | |
5666 | ||
5667 | for_each_intel_crtc(&dev_priv->drm, crtc) { | |
5668 | struct intel_crtc_state *crtc_state = | |
5669 | to_intel_crtc_state(crtc->base.state); | |
5670 | ||
5671 | crtc_state->wm.vlv.intermediate = | |
5672 | crtc_state->wm.vlv.optimal; | |
5673 | crtc->wm.active.vlv = crtc_state->wm.vlv.optimal; | |
5674 | } | |
5675 | ||
5676 | vlv_program_watermarks(dev_priv); | |
5677 | ||
5678 | mutex_unlock(&dev_priv->wm.wm_mutex); | |
5679 | } | |
5680 | ||
243e6a44 VS |
5681 | void ilk_wm_get_hw_state(struct drm_device *dev) |
5682 | { | |
fac5e23e | 5683 | struct drm_i915_private *dev_priv = to_i915(dev); |
820c1980 | 5684 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
5685 | struct drm_crtc *crtc; |
5686 | ||
70e1e0ec | 5687 | for_each_crtc(dev, crtc) |
243e6a44 VS |
5688 | ilk_pipe_wm_get_hw_state(crtc); |
5689 | ||
5690 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
5691 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
5692 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
5693 | ||
5694 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
175fded1 | 5695 | if (INTEL_GEN(dev_priv) >= 7) { |
cfa7698b VS |
5696 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); |
5697 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
5698 | } | |
243e6a44 | 5699 | |
8652744b | 5700 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
ac9545fd VS |
5701 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
5702 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
fd6b8f43 | 5703 | else if (IS_IVYBRIDGE(dev_priv)) |
ac9545fd VS |
5704 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? |
5705 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
5706 | |
5707 | hw->enable_fbc_wm = | |
5708 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
5709 | } | |
5710 | ||
b445e3b0 ED |
5711 | /** |
5712 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
5713 | * | |
5714 | * Calculate watermark values for the various WM regs based on current mode | |
5715 | * and plane configuration. | |
5716 | * | |
5717 | * There are several cases to deal with here: | |
5718 | * - normal (i.e. non-self-refresh) | |
5719 | * - self-refresh (SR) mode | |
5720 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
5721 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
5722 | * lines), so need to account for TLB latency | |
5723 | * | |
5724 | * The normal calculation is: | |
5725 | * watermark = dotclock * bytes per pixel * latency | |
5726 | * where latency is platform & configuration dependent (we assume pessimal | |
5727 | * values here). | |
5728 | * | |
5729 | * The SR calculation is: | |
5730 | * watermark = (trunc(latency/line time)+1) * surface width * | |
5731 | * bytes per pixel | |
5732 | * where | |
5733 | * line time = htotal / dotclock | |
5734 | * surface width = hdisplay for normal plane and 64 for cursor | |
5735 | * and latency is assumed to be high, as above. | |
5736 | * | |
5737 | * The final value programmed to the register should always be rounded up, | |
5738 | * and include an extra 2 entries to account for clock crossings. | |
5739 | * | |
5740 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
5741 | * to set the non-SR watermarks to 8. | |
5742 | */ | |
432081bc | 5743 | void intel_update_watermarks(struct intel_crtc *crtc) |
b445e3b0 | 5744 | { |
432081bc | 5745 | struct drm_i915_private *dev_priv = to_i915(crtc->base.dev); |
b445e3b0 ED |
5746 | |
5747 | if (dev_priv->display.update_wm) | |
46ba614c | 5748 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
5749 | } |
5750 | ||
e2828914 | 5751 | /* |
9270388e | 5752 | * Lock protecting IPS related data structures |
9270388e DV |
5753 | */ |
5754 | DEFINE_SPINLOCK(mchdev_lock); | |
5755 | ||
5756 | /* Global for IPS driver to get at the current i915 device. Protected by | |
5757 | * mchdev_lock. */ | |
5758 | static struct drm_i915_private *i915_mch_dev; | |
5759 | ||
91d14251 | 5760 | bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5761 | { |
2b4e57bd ED |
5762 | u16 rgvswctl; |
5763 | ||
67520415 | 5764 | lockdep_assert_held(&mchdev_lock); |
9270388e | 5765 | |
2b4e57bd ED |
5766 | rgvswctl = I915_READ16(MEMSWCTL); |
5767 | if (rgvswctl & MEMCTL_CMD_STS) { | |
5768 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
5769 | return false; /* still busy with another command */ | |
5770 | } | |
5771 | ||
5772 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
5773 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
5774 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5775 | POSTING_READ16(MEMSWCTL); | |
5776 | ||
5777 | rgvswctl |= MEMCTL_CMD_STS; | |
5778 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
5779 | ||
5780 | return true; | |
5781 | } | |
5782 | ||
91d14251 | 5783 | static void ironlake_enable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5784 | { |
84f1b20f | 5785 | u32 rgvmodectl; |
2b4e57bd ED |
5786 | u8 fmax, fmin, fstart, vstart; |
5787 | ||
9270388e DV |
5788 | spin_lock_irq(&mchdev_lock); |
5789 | ||
84f1b20f TU |
5790 | rgvmodectl = I915_READ(MEMMODECTL); |
5791 | ||
2b4e57bd ED |
5792 | /* Enable temp reporting */ |
5793 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
5794 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
5795 | ||
5796 | /* 100ms RC evaluation intervals */ | |
5797 | I915_WRITE(RCUPEI, 100000); | |
5798 | I915_WRITE(RCDNEI, 100000); | |
5799 | ||
5800 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
5801 | I915_WRITE(RCBMAXAVG, 90000); | |
5802 | I915_WRITE(RCBMINAVG, 80000); | |
5803 | ||
5804 | I915_WRITE(MEMIHYST, 1); | |
5805 | ||
5806 | /* Set up min, max, and cur for interrupt handling */ | |
5807 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
5808 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
5809 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
5810 | MEMMODE_FSTART_SHIFT; | |
5811 | ||
616847e7 | 5812 | vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >> |
2b4e57bd ED |
5813 | PXVFREQ_PX_SHIFT; |
5814 | ||
20e4d407 DV |
5815 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
5816 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 5817 | |
20e4d407 DV |
5818 | dev_priv->ips.max_delay = fstart; |
5819 | dev_priv->ips.min_delay = fmin; | |
5820 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
5821 | |
5822 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
5823 | fmax, fmin, fstart); | |
5824 | ||
5825 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
5826 | ||
5827 | /* | |
5828 | * Interrupts will be enabled in ironlake_irq_postinstall | |
5829 | */ | |
5830 | ||
5831 | I915_WRITE(VIDSTART, vstart); | |
5832 | POSTING_READ(VIDSTART); | |
5833 | ||
5834 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
5835 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
5836 | ||
9270388e | 5837 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 5838 | DRM_ERROR("stuck trying to change perf mode\n"); |
dd92d8de | 5839 | mdelay(1); |
2b4e57bd | 5840 | |
91d14251 | 5841 | ironlake_set_drps(dev_priv, fstart); |
2b4e57bd | 5842 | |
7d81c3e0 VS |
5843 | dev_priv->ips.last_count1 = I915_READ(DMIEC) + |
5844 | I915_READ(DDREC) + I915_READ(CSIEC); | |
20e4d407 | 5845 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
7d81c3e0 | 5846 | dev_priv->ips.last_count2 = I915_READ(GFXEC); |
5ed0bdf2 | 5847 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
5848 | |
5849 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
5850 | } |
5851 | ||
91d14251 | 5852 | static void ironlake_disable_drps(struct drm_i915_private *dev_priv) |
2b4e57bd | 5853 | { |
9270388e DV |
5854 | u16 rgvswctl; |
5855 | ||
5856 | spin_lock_irq(&mchdev_lock); | |
5857 | ||
5858 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
5859 | |
5860 | /* Ack interrupts, disable EFC interrupt */ | |
5861 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
5862 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
5863 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
5864 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
5865 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
5866 | ||
5867 | /* Go back to the starting frequency */ | |
91d14251 | 5868 | ironlake_set_drps(dev_priv, dev_priv->ips.fstart); |
dd92d8de | 5869 | mdelay(1); |
2b4e57bd ED |
5870 | rgvswctl |= MEMCTL_CMD_STS; |
5871 | I915_WRITE(MEMSWCTL, rgvswctl); | |
dd92d8de | 5872 | mdelay(1); |
2b4e57bd | 5873 | |
9270388e | 5874 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
5875 | } |
5876 | ||
acbe9475 DV |
5877 | /* There's a funny hw issue where the hw returns all 0 when reading from |
5878 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
5879 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
5880 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
5881 | */ | |
74ef1173 | 5882 | static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 5883 | { |
7b9e0ae6 | 5884 | u32 limits; |
2b4e57bd | 5885 | |
20b46e59 DV |
5886 | /* Only set the down limit when we've reached the lowest level to avoid |
5887 | * getting more interrupts, otherwise leave this clear. This prevents a | |
5888 | * race in the hw when coming out of rc6: There's a tiny window where | |
5889 | * the hw runs at the minimal clock before selecting the desired | |
5890 | * frequency, if the down threshold expires in that window we will not | |
5891 | * receive a down interrupt. */ | |
35ceabf3 | 5892 | if (INTEL_GEN(dev_priv) >= 9) { |
74ef1173 AG |
5893 | limits = (dev_priv->rps.max_freq_softlimit) << 23; |
5894 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5895 | limits |= (dev_priv->rps.min_freq_softlimit) << 14; | |
5896 | } else { | |
5897 | limits = dev_priv->rps.max_freq_softlimit << 24; | |
5898 | if (val <= dev_priv->rps.min_freq_softlimit) | |
5899 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
5900 | } | |
20b46e59 DV |
5901 | |
5902 | return limits; | |
5903 | } | |
5904 | ||
dd75fdc8 CW |
5905 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
5906 | { | |
5907 | int new_power; | |
8a586437 AG |
5908 | u32 threshold_up = 0, threshold_down = 0; /* in % */ |
5909 | u32 ei_up = 0, ei_down = 0; | |
dd75fdc8 CW |
5910 | |
5911 | new_power = dev_priv->rps.power; | |
5912 | switch (dev_priv->rps.power) { | |
5913 | case LOW_POWER: | |
a72b5623 CW |
5914 | if (val > dev_priv->rps.efficient_freq + 1 && |
5915 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5916 | new_power = BETWEEN; |
5917 | break; | |
5918 | ||
5919 | case BETWEEN: | |
a72b5623 CW |
5920 | if (val <= dev_priv->rps.efficient_freq && |
5921 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 | 5922 | new_power = LOW_POWER; |
a72b5623 CW |
5923 | else if (val >= dev_priv->rps.rp0_freq && |
5924 | val > dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5925 | new_power = HIGH_POWER; |
5926 | break; | |
5927 | ||
5928 | case HIGH_POWER: | |
a72b5623 CW |
5929 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && |
5930 | val < dev_priv->rps.cur_freq) | |
dd75fdc8 CW |
5931 | new_power = BETWEEN; |
5932 | break; | |
5933 | } | |
5934 | /* Max/min bins are special */ | |
aed242ff | 5935 | if (val <= dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 5936 | new_power = LOW_POWER; |
aed242ff | 5937 | if (val >= dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
5938 | new_power = HIGH_POWER; |
5939 | if (new_power == dev_priv->rps.power) | |
5940 | return; | |
5941 | ||
5942 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
5943 | switch (new_power) { | |
5944 | case LOW_POWER: | |
5945 | /* Upclock if more than 95% busy over 16ms */ | |
8a586437 AG |
5946 | ei_up = 16000; |
5947 | threshold_up = 95; | |
dd75fdc8 CW |
5948 | |
5949 | /* Downclock if less than 85% busy over 32ms */ | |
8a586437 AG |
5950 | ei_down = 32000; |
5951 | threshold_down = 85; | |
dd75fdc8 CW |
5952 | break; |
5953 | ||
5954 | case BETWEEN: | |
5955 | /* Upclock if more than 90% busy over 13ms */ | |
8a586437 AG |
5956 | ei_up = 13000; |
5957 | threshold_up = 90; | |
dd75fdc8 CW |
5958 | |
5959 | /* Downclock if less than 75% busy over 32ms */ | |
8a586437 AG |
5960 | ei_down = 32000; |
5961 | threshold_down = 75; | |
dd75fdc8 CW |
5962 | break; |
5963 | ||
5964 | case HIGH_POWER: | |
5965 | /* Upclock if more than 85% busy over 10ms */ | |
8a586437 AG |
5966 | ei_up = 10000; |
5967 | threshold_up = 85; | |
dd75fdc8 CW |
5968 | |
5969 | /* Downclock if less than 60% busy over 32ms */ | |
8a586437 AG |
5970 | ei_down = 32000; |
5971 | threshold_down = 60; | |
dd75fdc8 CW |
5972 | break; |
5973 | } | |
5974 | ||
6067a27d MK |
5975 | /* When byt can survive without system hang with dynamic |
5976 | * sw freq adjustments, this restriction can be lifted. | |
5977 | */ | |
5978 | if (IS_VALLEYVIEW(dev_priv)) | |
5979 | goto skip_hw_write; | |
5980 | ||
8a586437 | 5981 | I915_WRITE(GEN6_RP_UP_EI, |
a72b5623 | 5982 | GT_INTERVAL_FROM_US(dev_priv, ei_up)); |
8a586437 | 5983 | I915_WRITE(GEN6_RP_UP_THRESHOLD, |
a72b5623 CW |
5984 | GT_INTERVAL_FROM_US(dev_priv, |
5985 | ei_up * threshold_up / 100)); | |
8a586437 AG |
5986 | |
5987 | I915_WRITE(GEN6_RP_DOWN_EI, | |
a72b5623 | 5988 | GT_INTERVAL_FROM_US(dev_priv, ei_down)); |
8a586437 | 5989 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, |
a72b5623 CW |
5990 | GT_INTERVAL_FROM_US(dev_priv, |
5991 | ei_down * threshold_down / 100)); | |
5992 | ||
5993 | I915_WRITE(GEN6_RP_CONTROL, | |
5994 | GEN6_RP_MEDIA_TURBO | | |
5995 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5996 | GEN6_RP_MEDIA_IS_GFX | | |
5997 | GEN6_RP_ENABLE | | |
5998 | GEN6_RP_UP_BUSY_AVG | | |
5999 | GEN6_RP_DOWN_IDLE_AVG); | |
8a586437 | 6000 | |
6067a27d | 6001 | skip_hw_write: |
dd75fdc8 | 6002 | dev_priv->rps.power = new_power; |
8fb55197 CW |
6003 | dev_priv->rps.up_threshold = threshold_up; |
6004 | dev_priv->rps.down_threshold = threshold_down; | |
dd75fdc8 CW |
6005 | dev_priv->rps.last_adj = 0; |
6006 | } | |
6007 | ||
2876ce73 CW |
6008 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
6009 | { | |
6010 | u32 mask = 0; | |
6011 | ||
e0e8c7cb | 6012 | /* We use UP_EI_EXPIRED interupts for both up/down in manual mode */ |
2876ce73 | 6013 | if (val > dev_priv->rps.min_freq_softlimit) |
e0e8c7cb | 6014 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; |
2876ce73 | 6015 | if (val < dev_priv->rps.max_freq_softlimit) |
6f4b12f8 | 6016 | mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD; |
2876ce73 | 6017 | |
7b3c29f6 CW |
6018 | mask &= dev_priv->pm_rps_events; |
6019 | ||
59d02a1f | 6020 | return gen6_sanitize_rps_pm_mask(dev_priv, ~mask); |
2876ce73 CW |
6021 | } |
6022 | ||
b8a5ff8d JM |
6023 | /* gen6_set_rps is called to update the frequency request, but should also be |
6024 | * called when the range (min_delay and max_delay) is modified so that we can | |
6025 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
9fcee2f7 | 6026 | static int gen6_set_rps(struct drm_i915_private *dev_priv, u8 val) |
20b46e59 | 6027 | { |
eb64cad1 CW |
6028 | /* min/max delay may still have been modified so be sure to |
6029 | * write the limits value. | |
6030 | */ | |
6031 | if (val != dev_priv->rps.cur_freq) { | |
6032 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 6033 | |
35ceabf3 | 6034 | if (INTEL_GEN(dev_priv) >= 9) |
5704195c AG |
6035 | I915_WRITE(GEN6_RPNSWREQ, |
6036 | GEN9_FREQUENCY(val)); | |
dc97997a | 6037 | else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) |
eb64cad1 CW |
6038 | I915_WRITE(GEN6_RPNSWREQ, |
6039 | HSW_FREQUENCY(val)); | |
6040 | else | |
6041 | I915_WRITE(GEN6_RPNSWREQ, | |
6042 | GEN6_FREQUENCY(val) | | |
6043 | GEN6_OFFSET(0) | | |
6044 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 6045 | } |
7b9e0ae6 | 6046 | |
7b9e0ae6 CW |
6047 | /* Make sure we continue to get interrupts |
6048 | * until we hit the minimum or maximum frequencies. | |
6049 | */ | |
74ef1173 | 6050 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val)); |
2876ce73 | 6051 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 6052 | |
b39fb297 | 6053 | dev_priv->rps.cur_freq = val; |
0f94592e | 6054 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); |
9fcee2f7 CW |
6055 | |
6056 | return 0; | |
2b4e57bd ED |
6057 | } |
6058 | ||
9fcee2f7 | 6059 | static int valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val) |
ffe02b40 | 6060 | { |
9fcee2f7 CW |
6061 | int err; |
6062 | ||
dc97997a | 6063 | if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1), |
ffe02b40 VS |
6064 | "Odd GPU freq value\n")) |
6065 | val &= ~1; | |
6066 | ||
cd25dd5b D |
6067 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
6068 | ||
8fb55197 | 6069 | if (val != dev_priv->rps.cur_freq) { |
9fcee2f7 CW |
6070 | err = vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
6071 | if (err) | |
6072 | return err; | |
6073 | ||
db4c5e0b | 6074 | gen6_set_rps_thresholds(dev_priv, val); |
8fb55197 | 6075 | } |
ffe02b40 | 6076 | |
ffe02b40 VS |
6077 | dev_priv->rps.cur_freq = val; |
6078 | trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val)); | |
9fcee2f7 CW |
6079 | |
6080 | return 0; | |
ffe02b40 VS |
6081 | } |
6082 | ||
a7f6e231 | 6083 | /* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down |
76c3552f D |
6084 | * |
6085 | * * If Gfx is Idle, then | |
a7f6e231 D |
6086 | * 1. Forcewake Media well. |
6087 | * 2. Request idle freq. | |
6088 | * 3. Release Forcewake of Media well. | |
76c3552f D |
6089 | */ |
6090 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
6091 | { | |
aed242ff | 6092 | u32 val = dev_priv->rps.idle_freq; |
9fcee2f7 | 6093 | int err; |
5549d25f | 6094 | |
aed242ff | 6095 | if (dev_priv->rps.cur_freq <= val) |
76c3552f D |
6096 | return; |
6097 | ||
c9efef7b CW |
6098 | /* The punit delays the write of the frequency and voltage until it |
6099 | * determines the GPU is awake. During normal usage we don't want to | |
6100 | * waste power changing the frequency if the GPU is sleeping (rc6). | |
6101 | * However, the GPU and driver is now idle and we do not want to delay | |
6102 | * switching to minimum voltage (reducing power whilst idle) as we do | |
6103 | * not expect to be woken in the near future and so must flush the | |
6104 | * change by waking the device. | |
6105 | * | |
6106 | * We choose to take the media powerwell (either would do to trick the | |
6107 | * punit into committing the voltage change) as that takes a lot less | |
6108 | * power than the render powerwell. | |
6109 | */ | |
a7f6e231 | 6110 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 | 6111 | err = valleyview_set_rps(dev_priv, val); |
a7f6e231 | 6112 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA); |
9fcee2f7 CW |
6113 | |
6114 | if (err) | |
6115 | DRM_ERROR("Failed to set RPS for idle\n"); | |
76c3552f D |
6116 | } |
6117 | ||
43cf3bf0 CW |
6118 | void gen6_rps_busy(struct drm_i915_private *dev_priv) |
6119 | { | |
6120 | mutex_lock(&dev_priv->rps.hw_lock); | |
6121 | if (dev_priv->rps.enabled) { | |
bd64818d CW |
6122 | u8 freq; |
6123 | ||
e0e8c7cb | 6124 | if (dev_priv->pm_rps_events & GEN6_PM_RP_UP_EI_EXPIRED) |
43cf3bf0 CW |
6125 | gen6_rps_reset_ei(dev_priv); |
6126 | I915_WRITE(GEN6_PMINTRMSK, | |
6127 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
2b83c4c4 | 6128 | |
c33d247d CW |
6129 | gen6_enable_rps_interrupts(dev_priv); |
6130 | ||
bd64818d CW |
6131 | /* Use the user's desired frequency as a guide, but for better |
6132 | * performance, jump directly to RPe as our starting frequency. | |
6133 | */ | |
6134 | freq = max(dev_priv->rps.cur_freq, | |
6135 | dev_priv->rps.efficient_freq); | |
6136 | ||
9fcee2f7 | 6137 | if (intel_set_rps(dev_priv, |
bd64818d | 6138 | clamp(freq, |
9fcee2f7 CW |
6139 | dev_priv->rps.min_freq_softlimit, |
6140 | dev_priv->rps.max_freq_softlimit))) | |
6141 | DRM_DEBUG_DRIVER("Failed to set idle frequency\n"); | |
43cf3bf0 CW |
6142 | } |
6143 | mutex_unlock(&dev_priv->rps.hw_lock); | |
6144 | } | |
6145 | ||
b29c19b6 CW |
6146 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
6147 | { | |
c33d247d CW |
6148 | /* Flush our bottom-half so that it does not race with us |
6149 | * setting the idle frequency and so that it is bounded by | |
6150 | * our rpm wakeref. And then disable the interrupts to stop any | |
6151 | * futher RPS reclocking whilst we are asleep. | |
6152 | */ | |
6153 | gen6_disable_rps_interrupts(dev_priv); | |
6154 | ||
b29c19b6 | 6155 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 6156 | if (dev_priv->rps.enabled) { |
dc97997a | 6157 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
76c3552f | 6158 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 6159 | else |
dc97997a | 6160 | gen6_set_rps(dev_priv, dev_priv->rps.idle_freq); |
c0951f0c | 6161 | dev_priv->rps.last_adj = 0; |
12c100bf VS |
6162 | I915_WRITE(GEN6_PMINTRMSK, |
6163 | gen6_sanitize_rps_pm_mask(dev_priv, ~0)); | |
c0951f0c | 6164 | } |
8d3afd7d | 6165 | mutex_unlock(&dev_priv->rps.hw_lock); |
b29c19b6 CW |
6166 | } |
6167 | ||
7b92c1bd CW |
6168 | void gen6_rps_boost(struct drm_i915_gem_request *rq, |
6169 | struct intel_rps_client *rps) | |
b29c19b6 | 6170 | { |
7b92c1bd CW |
6171 | struct drm_i915_private *i915 = rq->i915; |
6172 | bool boost; | |
6173 | ||
8d3afd7d CW |
6174 | /* This is intentionally racy! We peek at the state here, then |
6175 | * validate inside the RPS worker. | |
6176 | */ | |
7b92c1bd | 6177 | if (!i915->rps.enabled) |
8d3afd7d | 6178 | return; |
43cf3bf0 | 6179 | |
7b92c1bd CW |
6180 | boost = false; |
6181 | spin_lock_irq(&rq->lock); | |
6182 | if (!rq->waitboost && !i915_gem_request_completed(rq)) { | |
6183 | atomic_inc(&i915->rps.num_waiters); | |
6184 | rq->waitboost = true; | |
6185 | boost = true; | |
c0951f0c | 6186 | } |
7b92c1bd CW |
6187 | spin_unlock_irq(&rq->lock); |
6188 | if (!boost) | |
6189 | return; | |
6190 | ||
6191 | if (READ_ONCE(i915->rps.cur_freq) < i915->rps.boost_freq) | |
6192 | schedule_work(&i915->rps.work); | |
6193 | ||
6194 | atomic_inc(rps ? &rps->boosts : &i915->rps.boosts); | |
b29c19b6 CW |
6195 | } |
6196 | ||
9fcee2f7 | 6197 | int intel_set_rps(struct drm_i915_private *dev_priv, u8 val) |
0a073b84 | 6198 | { |
9fcee2f7 CW |
6199 | int err; |
6200 | ||
cfd1c488 CW |
6201 | lockdep_assert_held(&dev_priv->rps.hw_lock); |
6202 | GEM_BUG_ON(val > dev_priv->rps.max_freq); | |
6203 | GEM_BUG_ON(val < dev_priv->rps.min_freq); | |
6204 | ||
76e4e4b5 CW |
6205 | if (!dev_priv->rps.enabled) { |
6206 | dev_priv->rps.cur_freq = val; | |
6207 | return 0; | |
6208 | } | |
6209 | ||
dc97997a | 6210 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) |
9fcee2f7 | 6211 | err = valleyview_set_rps(dev_priv, val); |
ffe02b40 | 6212 | else |
9fcee2f7 CW |
6213 | err = gen6_set_rps(dev_priv, val); |
6214 | ||
6215 | return err; | |
0a073b84 JB |
6216 | } |
6217 | ||
dc97997a | 6218 | static void gen9_disable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 6219 | { |
20e49366 | 6220 | I915_WRITE(GEN6_RC_CONTROL, 0); |
38c23527 | 6221 | I915_WRITE(GEN9_PG_ENABLE, 0); |
20e49366 ZW |
6222 | } |
6223 | ||
dc97997a | 6224 | static void gen9_disable_rps(struct drm_i915_private *dev_priv) |
2030d684 | 6225 | { |
2030d684 AG |
6226 | I915_WRITE(GEN6_RP_CONTROL, 0); |
6227 | } | |
6228 | ||
dc97997a | 6229 | static void gen6_disable_rps(struct drm_i915_private *dev_priv) |
d20d4f0c | 6230 | { |
d20d4f0c | 6231 | I915_WRITE(GEN6_RC_CONTROL, 0); |
44fc7d5c | 6232 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
2030d684 | 6233 | I915_WRITE(GEN6_RP_CONTROL, 0); |
44fc7d5c DV |
6234 | } |
6235 | ||
dc97997a | 6236 | static void cherryview_disable_rps(struct drm_i915_private *dev_priv) |
38807746 | 6237 | { |
38807746 D |
6238 | I915_WRITE(GEN6_RC_CONTROL, 0); |
6239 | } | |
6240 | ||
dc97997a | 6241 | static void valleyview_disable_rps(struct drm_i915_private *dev_priv) |
44fc7d5c | 6242 | { |
98a2e5f9 D |
6243 | /* we're doing forcewake before Disabling RC6, |
6244 | * This what the BIOS expects when going into suspend */ | |
59bad947 | 6245 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
98a2e5f9 | 6246 | |
44fc7d5c | 6247 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 6248 | |
59bad947 | 6249 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
d20d4f0c JB |
6250 | } |
6251 | ||
dc97997a | 6252 | static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode) |
dc39fff7 | 6253 | { |
dc97997a | 6254 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
91ca689a ID |
6255 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) |
6256 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
6257 | else | |
6258 | mode = 0; | |
6259 | } | |
dc97997a | 6260 | if (HAS_RC6p(dev_priv)) |
b99d49cc ID |
6261 | DRM_DEBUG_DRIVER("Enabling RC6 states: " |
6262 | "RC6 %s RC6p %s RC6pp %s\n", | |
6263 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE), | |
6264 | onoff(mode & GEN6_RC_CTL_RC6p_ENABLE), | |
6265 | onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE)); | |
58abf1da RV |
6266 | |
6267 | else | |
b99d49cc ID |
6268 | DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n", |
6269 | onoff(mode & GEN6_RC_CTL_RC6_ENABLE)); | |
dc39fff7 BW |
6270 | } |
6271 | ||
dc97997a | 6272 | static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv) |
274008e8 | 6273 | { |
72e96d64 | 6274 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
274008e8 SAK |
6275 | bool enable_rc6 = true; |
6276 | unsigned long rc6_ctx_base; | |
fc619841 ID |
6277 | u32 rc_ctl; |
6278 | int rc_sw_target; | |
6279 | ||
6280 | rc_ctl = I915_READ(GEN6_RC_CONTROL); | |
6281 | rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >> | |
6282 | RC_SW_TARGET_STATE_SHIFT; | |
6283 | DRM_DEBUG_DRIVER("BIOS enabled RC states: " | |
6284 | "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n", | |
6285 | onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE), | |
6286 | onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE), | |
6287 | rc_sw_target); | |
274008e8 SAK |
6288 | |
6289 | if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) { | |
b99d49cc | 6290 | DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n"); |
274008e8 SAK |
6291 | enable_rc6 = false; |
6292 | } | |
6293 | ||
6294 | /* | |
6295 | * The exact context size is not known for BXT, so assume a page size | |
6296 | * for this check. | |
6297 | */ | |
6298 | rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK; | |
72e96d64 JL |
6299 | if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) && |
6300 | (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base + | |
6301 | ggtt->stolen_reserved_size))) { | |
b99d49cc | 6302 | DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n"); |
274008e8 SAK |
6303 | enable_rc6 = false; |
6304 | } | |
6305 | ||
6306 | if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) && | |
6307 | ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) && | |
6308 | ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) && | |
6309 | ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) { | |
b99d49cc | 6310 | DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n"); |
274008e8 SAK |
6311 | enable_rc6 = false; |
6312 | } | |
6313 | ||
fc619841 ID |
6314 | if (!I915_READ(GEN8_PUSHBUS_CONTROL) || |
6315 | !I915_READ(GEN8_PUSHBUS_ENABLE) || | |
6316 | !I915_READ(GEN8_PUSHBUS_SHIFT)) { | |
6317 | DRM_DEBUG_DRIVER("Pushbus not setup properly.\n"); | |
6318 | enable_rc6 = false; | |
6319 | } | |
6320 | ||
6321 | if (!I915_READ(GEN6_GFXPAUSE)) { | |
6322 | DRM_DEBUG_DRIVER("GFX pause not setup properly.\n"); | |
6323 | enable_rc6 = false; | |
6324 | } | |
6325 | ||
6326 | if (!I915_READ(GEN8_MISC_CTRL0)) { | |
6327 | DRM_DEBUG_DRIVER("GPM control not setup properly.\n"); | |
274008e8 SAK |
6328 | enable_rc6 = false; |
6329 | } | |
6330 | ||
6331 | return enable_rc6; | |
6332 | } | |
6333 | ||
dc97997a | 6334 | int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6) |
2b4e57bd | 6335 | { |
e7d66d89 | 6336 | /* No RC6 before Ironlake and code is gone for ilk. */ |
dc97997a | 6337 | if (INTEL_INFO(dev_priv)->gen < 6) |
e6069ca8 ID |
6338 | return 0; |
6339 | ||
274008e8 SAK |
6340 | if (!enable_rc6) |
6341 | return 0; | |
6342 | ||
cc3f90f0 | 6343 | if (IS_GEN9_LP(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) { |
274008e8 SAK |
6344 | DRM_INFO("RC6 disabled by BIOS\n"); |
6345 | return 0; | |
6346 | } | |
6347 | ||
456470eb | 6348 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
6349 | if (enable_rc6 >= 0) { |
6350 | int mask; | |
6351 | ||
dc97997a | 6352 | if (HAS_RC6p(dev_priv)) |
e6069ca8 ID |
6353 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
6354 | INTEL_RC6pp_ENABLE; | |
6355 | else | |
6356 | mask = INTEL_RC6_ENABLE; | |
6357 | ||
6358 | if ((enable_rc6 & mask) != enable_rc6) | |
b99d49cc ID |
6359 | DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d " |
6360 | "(requested %d, valid %d)\n", | |
6361 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
6362 | |
6363 | return enable_rc6 & mask; | |
6364 | } | |
2b4e57bd | 6365 | |
dc97997a | 6366 | if (IS_IVYBRIDGE(dev_priv)) |
cca84a1f | 6367 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
6368 | |
6369 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
6370 | } |
6371 | ||
dc97997a | 6372 | static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv) |
3280e8b0 BW |
6373 | { |
6374 | /* All of these values are in units of 50MHz */ | |
773ea9a8 | 6375 | |
93ee2920 | 6376 | /* static values from HW: RP0 > RP1 > RPn (min_freq) */ |
cc3f90f0 | 6377 | if (IS_GEN9_LP(dev_priv)) { |
773ea9a8 | 6378 | u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP); |
35040562 BP |
6379 | dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff; |
6380 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
6381 | dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff; | |
6382 | } else { | |
773ea9a8 | 6383 | u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
35040562 BP |
6384 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; |
6385 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
6386 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
6387 | } | |
3280e8b0 | 6388 | /* hw_max = RP0 until we check for overclocking */ |
773ea9a8 | 6389 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; |
3280e8b0 | 6390 | |
93ee2920 | 6391 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; |
dc97997a | 6392 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) || |
35ceabf3 | 6393 | IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
773ea9a8 CW |
6394 | u32 ddcc_status = 0; |
6395 | ||
6396 | if (sandybridge_pcode_read(dev_priv, | |
6397 | HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL, | |
6398 | &ddcc_status) == 0) | |
93ee2920 | 6399 | dev_priv->rps.efficient_freq = |
46efa4ab TR |
6400 | clamp_t(u8, |
6401 | ((ddcc_status >> 8) & 0xff), | |
6402 | dev_priv->rps.min_freq, | |
6403 | dev_priv->rps.max_freq); | |
93ee2920 TR |
6404 | } |
6405 | ||
35ceabf3 | 6406 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
c5e0688c | 6407 | /* Store the frequency values in 16.66 MHZ units, which is |
773ea9a8 CW |
6408 | * the natural hardware unit for SKL |
6409 | */ | |
c5e0688c AG |
6410 | dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER; |
6411 | dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER; | |
6412 | dev_priv->rps.min_freq *= GEN9_FREQ_SCALER; | |
6413 | dev_priv->rps.max_freq *= GEN9_FREQ_SCALER; | |
6414 | dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER; | |
6415 | } | |
3280e8b0 BW |
6416 | } |
6417 | ||
3a45b05c | 6418 | static void reset_rps(struct drm_i915_private *dev_priv, |
9fcee2f7 | 6419 | int (*set)(struct drm_i915_private *, u8)) |
3a45b05c CW |
6420 | { |
6421 | u8 freq = dev_priv->rps.cur_freq; | |
6422 | ||
6423 | /* force a reset */ | |
6424 | dev_priv->rps.power = -1; | |
6425 | dev_priv->rps.cur_freq = -1; | |
6426 | ||
9fcee2f7 CW |
6427 | if (set(dev_priv, freq)) |
6428 | DRM_ERROR("Failed to reset RPS to initial values\n"); | |
3a45b05c CW |
6429 | } |
6430 | ||
b6fef0ef | 6431 | /* See the Gen9_GT_PM_Programming_Guide doc for the below */ |
dc97997a | 6432 | static void gen9_enable_rps(struct drm_i915_private *dev_priv) |
b6fef0ef | 6433 | { |
b6fef0ef JB |
6434 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6435 | ||
0beb059a AG |
6436 | /* Program defaults and thresholds for RPS*/ |
6437 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6438 | GEN9_FREQUENCY(dev_priv->rps.rp1_freq)); | |
6439 | ||
6440 | /* 1 second timeout*/ | |
6441 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, | |
6442 | GT_INTERVAL_FROM_US(dev_priv, 1000000)); | |
6443 | ||
b6fef0ef | 6444 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa); |
b6fef0ef | 6445 | |
0beb059a AG |
6446 | /* Leaning on the below call to gen6_set_rps to program/setup the |
6447 | * Up/Down EI & threshold registers, as well as the RP_CONTROL, | |
6448 | * RP_INTERRUPT_LIMITS & RPNSWREQ registers */ | |
3a45b05c | 6449 | reset_rps(dev_priv, gen6_set_rps); |
b6fef0ef JB |
6450 | |
6451 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); | |
6452 | } | |
6453 | ||
dc97997a | 6454 | static void gen9_enable_rc6(struct drm_i915_private *dev_priv) |
20e49366 | 6455 | { |
e2f80391 | 6456 | struct intel_engine_cs *engine; |
3b3f1650 | 6457 | enum intel_engine_id id; |
20e49366 | 6458 | uint32_t rc6_mask = 0; |
20e49366 ZW |
6459 | |
6460 | /* 1a: Software RC state - RC0 */ | |
6461 | I915_WRITE(GEN6_RC_STATE, 0); | |
6462 | ||
6463 | /* 1b: Get forcewake during program sequence. Although the driver | |
6464 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6465 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
6466 | |
6467 | /* 2a: Disable RC states. */ | |
6468 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6469 | ||
6470 | /* 2b: Program RC6 thresholds.*/ | |
63a4dec2 SAK |
6471 | |
6472 | /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */ | |
dc97997a | 6473 | if (IS_SKYLAKE(dev_priv)) |
63a4dec2 SAK |
6474 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16); |
6475 | else | |
6476 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16); | |
20e49366 ZW |
6477 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ |
6478 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 6479 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6480 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
97c322e7 | 6481 | |
1a3d1898 | 6482 | if (HAS_GUC(dev_priv)) |
97c322e7 SAK |
6483 | I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA); |
6484 | ||
20e49366 | 6485 | I915_WRITE(GEN6_RC_SLEEP, 0); |
20e49366 | 6486 | |
38c23527 ZW |
6487 | /* 2c: Program Coarse Power Gating Policies. */ |
6488 | I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25); | |
6489 | I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25); | |
6490 | ||
20e49366 | 6491 | /* 3a: Enable RC6 */ |
dc97997a | 6492 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
20e49366 | 6493 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
87ad3212 | 6494 | DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE)); |
1c044f9b CW |
6495 | I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */ |
6496 | I915_WRITE(GEN6_RC_CONTROL, | |
6497 | GEN6_RC_CTL_HW_ENABLE | GEN6_RC_CTL_EI_MODE(1) | rc6_mask); | |
20e49366 | 6498 | |
cb07bae0 SK |
6499 | /* |
6500 | * 3b: Enable Coarse Power Gating only when RC6 is enabled. | |
f2d2fe95 | 6501 | * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6. |
cb07bae0 | 6502 | */ |
dc97997a | 6503 | if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv)) |
f2d2fe95 SAK |
6504 | I915_WRITE(GEN9_PG_ENABLE, 0); |
6505 | else | |
6506 | I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? | |
6507 | (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0); | |
38c23527 | 6508 | |
59bad947 | 6509 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
20e49366 ZW |
6510 | } |
6511 | ||
dc97997a | 6512 | static void gen8_enable_rps(struct drm_i915_private *dev_priv) |
6edee7f3 | 6513 | { |
e2f80391 | 6514 | struct intel_engine_cs *engine; |
3b3f1650 | 6515 | enum intel_engine_id id; |
93ee2920 | 6516 | uint32_t rc6_mask = 0; |
6edee7f3 BW |
6517 | |
6518 | /* 1a: Software RC state - RC0 */ | |
6519 | I915_WRITE(GEN6_RC_STATE, 0); | |
6520 | ||
6521 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
6522 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 6523 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
6524 | |
6525 | /* 2a: Disable RC states. */ | |
6526 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6527 | ||
6edee7f3 BW |
6528 | /* 2b: Program RC6 thresholds.*/ |
6529 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
6530 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
6531 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
3b3f1650 | 6532 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6533 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
6edee7f3 | 6534 | I915_WRITE(GEN6_RC_SLEEP, 0); |
dc97997a | 6535 | if (IS_BROADWELL(dev_priv)) |
0d68b25e TR |
6536 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ |
6537 | else | |
6538 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
6539 | |
6540 | /* 3: Enable RC6 */ | |
dc97997a | 6541 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6edee7f3 | 6542 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; |
dc97997a CW |
6543 | intel_print_rc6_info(dev_priv, rc6_mask); |
6544 | if (IS_BROADWELL(dev_priv)) | |
0d68b25e TR |
6545 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | |
6546 | GEN7_RC_CTL_TO_MODE | | |
6547 | rc6_mask); | |
6548 | else | |
6549 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
6550 | GEN6_RC_CTL_EI_MODE(1) | | |
6551 | rc6_mask); | |
6edee7f3 BW |
6552 | |
6553 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
6554 | I915_WRITE(GEN6_RPNSWREQ, |
6555 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
6556 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
6557 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
6558 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
6559 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
6560 | ||
6561 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
6562 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
6563 | dev_priv->rps.max_freq_softlimit << 24 | | |
6564 | dev_priv->rps.min_freq_softlimit << 16); | |
6565 | ||
6566 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
6567 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
6568 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
6569 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
6570 | ||
6571 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
6572 | |
6573 | /* 5: Enable RPS */ | |
7526ed79 DV |
6574 | I915_WRITE(GEN6_RP_CONTROL, |
6575 | GEN6_RP_MEDIA_TURBO | | |
6576 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
6577 | GEN6_RP_MEDIA_IS_GFX | | |
6578 | GEN6_RP_ENABLE | | |
6579 | GEN6_RP_UP_BUSY_AVG | | |
6580 | GEN6_RP_DOWN_IDLE_AVG); | |
6581 | ||
6582 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
6583 | ||
3a45b05c | 6584 | reset_rps(dev_priv, gen6_set_rps); |
7526ed79 | 6585 | |
59bad947 | 6586 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
6587 | } |
6588 | ||
dc97997a | 6589 | static void gen6_enable_rps(struct drm_i915_private *dev_priv) |
2b4e57bd | 6590 | { |
e2f80391 | 6591 | struct intel_engine_cs *engine; |
3b3f1650 | 6592 | enum intel_engine_id id; |
99ac9612 | 6593 | u32 rc6vids, rc6_mask = 0; |
2b4e57bd | 6594 | u32 gtfifodbg; |
2b4e57bd | 6595 | int rc6_mode; |
b4ac5afc | 6596 | int ret; |
2b4e57bd | 6597 | |
4fc688ce | 6598 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 6599 | |
2b4e57bd ED |
6600 | /* Here begins a magic sequence of register writes to enable |
6601 | * auto-downclocking. | |
6602 | * | |
6603 | * Perhaps there might be some value in exposing these to | |
6604 | * userspace... | |
6605 | */ | |
6606 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
6607 | |
6608 | /* Clear the DBG now so we don't confuse earlier errors */ | |
297b32ec VS |
6609 | gtfifodbg = I915_READ(GTFIFODBG); |
6610 | if (gtfifodbg) { | |
2b4e57bd ED |
6611 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); |
6612 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
6613 | } | |
6614 | ||
59bad947 | 6615 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
6616 | |
6617 | /* disable the counters and set deterministic thresholds */ | |
6618 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
6619 | ||
6620 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
6621 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
6622 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
6623 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
6624 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
6625 | ||
3b3f1650 | 6626 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 6627 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
2b4e57bd ED |
6628 | |
6629 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
6630 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
dc97997a | 6631 | if (IS_IVYBRIDGE(dev_priv)) |
351aa566 SM |
6632 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
6633 | else | |
6634 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 6635 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
6636 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
6637 | ||
5a7dc92a | 6638 | /* Check if we are enabling RC6 */ |
dc97997a | 6639 | rc6_mode = intel_enable_rc6(); |
2b4e57bd ED |
6640 | if (rc6_mode & INTEL_RC6_ENABLE) |
6641 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
6642 | ||
5a7dc92a | 6643 | /* We don't use those on Haswell */ |
dc97997a | 6644 | if (!IS_HASWELL(dev_priv)) { |
5a7dc92a ED |
6645 | if (rc6_mode & INTEL_RC6p_ENABLE) |
6646 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 6647 | |
5a7dc92a ED |
6648 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
6649 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
6650 | } | |
2b4e57bd | 6651 | |
dc97997a | 6652 | intel_print_rc6_info(dev_priv, rc6_mask); |
2b4e57bd ED |
6653 | |
6654 | I915_WRITE(GEN6_RC_CONTROL, | |
6655 | rc6_mask | | |
6656 | GEN6_RC_CTL_EI_MODE(1) | | |
6657 | GEN6_RC_CTL_HW_ENABLE); | |
6658 | ||
dd75fdc8 CW |
6659 | /* Power down if completely idle for over 50ms */ |
6660 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 6661 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 6662 | |
3a45b05c | 6663 | reset_rps(dev_priv, gen6_set_rps); |
2b4e57bd | 6664 | |
31643d54 BW |
6665 | rc6vids = 0; |
6666 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
dc97997a | 6667 | if (IS_GEN6(dev_priv) && ret) { |
31643d54 | 6668 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); |
dc97997a | 6669 | } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { |
31643d54 BW |
6670 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", |
6671 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
6672 | rc6vids &= 0xffff00; | |
6673 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
6674 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
6675 | if (ret) | |
6676 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
6677 | } | |
6678 | ||
59bad947 | 6679 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
6680 | } |
6681 | ||
fb7404e8 | 6682 | static void gen6_update_ring_freq(struct drm_i915_private *dev_priv) |
2b4e57bd ED |
6683 | { |
6684 | int min_freq = 15; | |
3ebecd07 CW |
6685 | unsigned int gpu_freq; |
6686 | unsigned int max_ia_freq, min_ring_freq; | |
4c8c7743 | 6687 | unsigned int max_gpu_freq, min_gpu_freq; |
2b4e57bd | 6688 | int scaling_factor = 180; |
eda79642 | 6689 | struct cpufreq_policy *policy; |
2b4e57bd | 6690 | |
4fc688ce | 6691 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 6692 | |
eda79642 BW |
6693 | policy = cpufreq_cpu_get(0); |
6694 | if (policy) { | |
6695 | max_ia_freq = policy->cpuinfo.max_freq; | |
6696 | cpufreq_cpu_put(policy); | |
6697 | } else { | |
6698 | /* | |
6699 | * Default to measured freq if none found, PCU will ensure we | |
6700 | * don't go over | |
6701 | */ | |
2b4e57bd | 6702 | max_ia_freq = tsc_khz; |
eda79642 | 6703 | } |
2b4e57bd ED |
6704 | |
6705 | /* Convert from kHz to MHz */ | |
6706 | max_ia_freq /= 1000; | |
6707 | ||
153b4b95 | 6708 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
6709 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
6710 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 6711 | |
35ceabf3 | 6712 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
4c8c7743 AG |
6713 | /* Convert GT frequency to 50 HZ units */ |
6714 | min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER; | |
6715 | max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER; | |
6716 | } else { | |
6717 | min_gpu_freq = dev_priv->rps.min_freq; | |
6718 | max_gpu_freq = dev_priv->rps.max_freq; | |
6719 | } | |
6720 | ||
2b4e57bd ED |
6721 | /* |
6722 | * For each potential GPU frequency, load a ring frequency we'd like | |
6723 | * to use for memory access. We do this by specifying the IA frequency | |
6724 | * the PCU should use as a reference to determine the ring frequency. | |
6725 | */ | |
4c8c7743 AG |
6726 | for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) { |
6727 | int diff = max_gpu_freq - gpu_freq; | |
3ebecd07 CW |
6728 | unsigned int ia_freq = 0, ring_freq = 0; |
6729 | ||
35ceabf3 | 6730 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) { |
4c8c7743 AG |
6731 | /* |
6732 | * ring_freq = 2 * GT. ring_freq is in 100MHz units | |
6733 | * No floor required for ring frequency on SKL. | |
6734 | */ | |
6735 | ring_freq = gpu_freq; | |
dc97997a | 6736 | } else if (INTEL_INFO(dev_priv)->gen >= 8) { |
46c764d4 BW |
6737 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ |
6738 | ring_freq = max(min_ring_freq, gpu_freq); | |
dc97997a | 6739 | } else if (IS_HASWELL(dev_priv)) { |
f6aca45c | 6740 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
6741 | ring_freq = max(min_ring_freq, ring_freq); |
6742 | /* leave ia_freq as the default, chosen by cpufreq */ | |
6743 | } else { | |
6744 | /* On older processors, there is no separate ring | |
6745 | * clock domain, so in order to boost the bandwidth | |
6746 | * of the ring, we need to upclock the CPU (ia_freq). | |
6747 | * | |
6748 | * For GPU frequencies less than 750MHz, | |
6749 | * just use the lowest ring freq. | |
6750 | */ | |
6751 | if (gpu_freq < min_freq) | |
6752 | ia_freq = 800; | |
6753 | else | |
6754 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
6755 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
6756 | } | |
2b4e57bd | 6757 | |
42c0526c BW |
6758 | sandybridge_pcode_write(dev_priv, |
6759 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
6760 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
6761 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
6762 | gpu_freq); | |
2b4e57bd | 6763 | } |
2b4e57bd ED |
6764 | } |
6765 | ||
03af2045 | 6766 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
6767 | { |
6768 | u32 val, rp0; | |
6769 | ||
5b5929cb | 6770 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
2b6b3a09 | 6771 | |
43b67998 | 6772 | switch (INTEL_INFO(dev_priv)->sseu.eu_total) { |
5b5929cb JN |
6773 | case 8: |
6774 | /* (2 * 4) config */ | |
6775 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT); | |
6776 | break; | |
6777 | case 12: | |
6778 | /* (2 * 6) config */ | |
6779 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT); | |
6780 | break; | |
6781 | case 16: | |
6782 | /* (2 * 8) config */ | |
6783 | default: | |
6784 | /* Setting (2 * 8) Min RP0 for any other combination */ | |
6785 | rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT); | |
6786 | break; | |
095acd5f | 6787 | } |
5b5929cb JN |
6788 | |
6789 | rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK); | |
6790 | ||
2b6b3a09 D |
6791 | return rp0; |
6792 | } | |
6793 | ||
6794 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6795 | { | |
6796 | u32 val, rpe; | |
6797 | ||
6798 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
6799 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
6800 | ||
6801 | return rpe; | |
6802 | } | |
6803 | ||
7707df4a D |
6804 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6805 | { | |
6806 | u32 val, rp1; | |
6807 | ||
5b5929cb JN |
6808 | val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE); |
6809 | rp1 = (val & FB_GFX_FREQ_FUSE_MASK); | |
6810 | ||
7707df4a D |
6811 | return rp1; |
6812 | } | |
6813 | ||
96676fe3 D |
6814 | static u32 cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
6815 | { | |
6816 | u32 val, rpn; | |
6817 | ||
6818 | val = vlv_punit_read(dev_priv, FB_GFX_FMIN_AT_VMIN_FUSE); | |
6819 | rpn = ((val >> FB_GFX_FMIN_AT_VMIN_FUSE_SHIFT) & | |
6820 | FB_GFX_FREQ_FUSE_MASK); | |
6821 | ||
6822 | return rpn; | |
6823 | } | |
6824 | ||
f8f2b001 D |
6825 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
6826 | { | |
6827 | u32 val, rp1; | |
6828 | ||
6829 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
6830 | ||
6831 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
6832 | ||
6833 | return rp1; | |
6834 | } | |
6835 | ||
03af2045 | 6836 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
6837 | { |
6838 | u32 val, rp0; | |
6839 | ||
64936258 | 6840 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
6841 | |
6842 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
6843 | /* Clamp to max */ | |
6844 | rp0 = min_t(u32, rp0, 0xea); | |
6845 | ||
6846 | return rp0; | |
6847 | } | |
6848 | ||
6849 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
6850 | { | |
6851 | u32 val, rpe; | |
6852 | ||
64936258 | 6853 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 6854 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 6855 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
6856 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
6857 | ||
6858 | return rpe; | |
6859 | } | |
6860 | ||
03af2045 | 6861 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 6862 | { |
36146035 ID |
6863 | u32 val; |
6864 | ||
6865 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; | |
6866 | /* | |
6867 | * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value | |
6868 | * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on | |
6869 | * a BYT-M B0 the above register contains 0xbf. Moreover when setting | |
6870 | * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0 | |
6871 | * to make sure it matches what Punit accepts. | |
6872 | */ | |
6873 | return max_t(u32, val, 0xc0); | |
0a073b84 JB |
6874 | } |
6875 | ||
ae48434c ID |
6876 | /* Check that the pctx buffer wasn't move under us. */ |
6877 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
6878 | { | |
6879 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6880 | ||
6881 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
6882 | dev_priv->vlv_pctx->stolen->start); | |
6883 | } | |
6884 | ||
38807746 D |
6885 | |
6886 | /* Check that the pcbr address is not empty. */ | |
6887 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
6888 | { | |
6889 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
6890 | ||
6891 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
6892 | } | |
6893 | ||
dc97997a | 6894 | static void cherryview_setup_pctx(struct drm_i915_private *dev_priv) |
38807746 | 6895 | { |
62106b4f | 6896 | struct i915_ggtt *ggtt = &dev_priv->ggtt; |
72e96d64 | 6897 | unsigned long pctx_paddr, paddr; |
38807746 D |
6898 | u32 pcbr; |
6899 | int pctx_size = 32*1024; | |
6900 | ||
38807746 D |
6901 | pcbr = I915_READ(VLV_PCBR); |
6902 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
ce611ef8 | 6903 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
38807746 | 6904 | paddr = (dev_priv->mm.stolen_base + |
62106b4f | 6905 | (ggtt->stolen_size - pctx_size)); |
38807746 D |
6906 | |
6907 | pctx_paddr = (paddr & (~4095)); | |
6908 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6909 | } | |
ce611ef8 VS |
6910 | |
6911 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); | |
38807746 D |
6912 | } |
6913 | ||
dc97997a | 6914 | static void valleyview_setup_pctx(struct drm_i915_private *dev_priv) |
c9cddffc | 6915 | { |
c9cddffc JB |
6916 | struct drm_i915_gem_object *pctx; |
6917 | unsigned long pctx_paddr; | |
6918 | u32 pcbr; | |
6919 | int pctx_size = 24*1024; | |
6920 | ||
6921 | pcbr = I915_READ(VLV_PCBR); | |
6922 | if (pcbr) { | |
6923 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
6924 | int pcbr_offset; | |
6925 | ||
6926 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
187685cb | 6927 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv, |
c9cddffc | 6928 | pcbr_offset, |
190d6cd5 | 6929 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
6930 | pctx_size); |
6931 | goto out; | |
6932 | } | |
6933 | ||
ce611ef8 VS |
6934 | DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n"); |
6935 | ||
c9cddffc JB |
6936 | /* |
6937 | * From the Gunit register HAS: | |
6938 | * The Gfx driver is expected to program this register and ensure | |
6939 | * proper allocation within Gfx stolen memory. For example, this | |
6940 | * register should be programmed such than the PCBR range does not | |
6941 | * overlap with other ranges, such as the frame buffer, protected | |
6942 | * memory, or any other relevant ranges. | |
6943 | */ | |
187685cb | 6944 | pctx = i915_gem_object_create_stolen(dev_priv, pctx_size); |
c9cddffc JB |
6945 | if (!pctx) { |
6946 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
ee504898 | 6947 | goto out; |
c9cddffc JB |
6948 | } |
6949 | ||
6950 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
6951 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
6952 | ||
6953 | out: | |
ce611ef8 | 6954 | DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR)); |
c9cddffc JB |
6955 | dev_priv->vlv_pctx = pctx; |
6956 | } | |
6957 | ||
dc97997a | 6958 | static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv) |
ae48434c | 6959 | { |
ae48434c ID |
6960 | if (WARN_ON(!dev_priv->vlv_pctx)) |
6961 | return; | |
6962 | ||
f0cd5182 | 6963 | i915_gem_object_put(dev_priv->vlv_pctx); |
ae48434c ID |
6964 | dev_priv->vlv_pctx = NULL; |
6965 | } | |
6966 | ||
c30fec65 VS |
6967 | static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv) |
6968 | { | |
6969 | dev_priv->rps.gpll_ref_freq = | |
6970 | vlv_get_cck_clock(dev_priv, "GPLL ref", | |
6971 | CCK_GPLL_CLOCK_CONTROL, | |
6972 | dev_priv->czclk_freq); | |
6973 | ||
6974 | DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n", | |
6975 | dev_priv->rps.gpll_ref_freq); | |
6976 | } | |
6977 | ||
dc97997a | 6978 | static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 6979 | { |
2bb25c17 | 6980 | u32 val; |
4e80519e | 6981 | |
dc97997a | 6982 | valleyview_setup_pctx(dev_priv); |
4e80519e | 6983 | |
c30fec65 VS |
6984 | vlv_init_gpll_ref_freq(dev_priv); |
6985 | ||
2bb25c17 VS |
6986 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
6987 | switch ((val >> 6) & 3) { | |
6988 | case 0: | |
6989 | case 1: | |
6990 | dev_priv->mem_freq = 800; | |
6991 | break; | |
6992 | case 2: | |
6993 | dev_priv->mem_freq = 1066; | |
6994 | break; | |
6995 | case 3: | |
6996 | dev_priv->mem_freq = 1333; | |
6997 | break; | |
6998 | } | |
80b83b62 | 6999 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 7000 | |
4e80519e ID |
7001 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
7002 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
7003 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7004 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
4e80519e ID |
7005 | dev_priv->rps.max_freq); |
7006 | ||
7007 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
7008 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7009 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
4e80519e ID |
7010 | dev_priv->rps.efficient_freq); |
7011 | ||
f8f2b001 D |
7012 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
7013 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7014 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
f8f2b001 D |
7015 | dev_priv->rps.rp1_freq); |
7016 | ||
4e80519e ID |
7017 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
7018 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7019 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
4e80519e | 7020 | dev_priv->rps.min_freq); |
4e80519e ID |
7021 | } |
7022 | ||
dc97997a | 7023 | static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv) |
38807746 | 7024 | { |
2bb25c17 | 7025 | u32 val; |
2b6b3a09 | 7026 | |
dc97997a | 7027 | cherryview_setup_pctx(dev_priv); |
2b6b3a09 | 7028 | |
c30fec65 VS |
7029 | vlv_init_gpll_ref_freq(dev_priv); |
7030 | ||
a580516d | 7031 | mutex_lock(&dev_priv->sb_lock); |
c6e8f39d | 7032 | val = vlv_cck_read(dev_priv, CCK_FUSE_REG); |
a580516d | 7033 | mutex_unlock(&dev_priv->sb_lock); |
c6e8f39d | 7034 | |
2bb25c17 | 7035 | switch ((val >> 2) & 0x7) { |
2bb25c17 | 7036 | case 3: |
2bb25c17 VS |
7037 | dev_priv->mem_freq = 2000; |
7038 | break; | |
bfa7df01 | 7039 | default: |
2bb25c17 VS |
7040 | dev_priv->mem_freq = 1600; |
7041 | break; | |
7042 | } | |
80b83b62 | 7043 | DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq); |
2bb25c17 | 7044 | |
2b6b3a09 D |
7045 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
7046 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
7047 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7048 | intel_gpu_freq(dev_priv, dev_priv->rps.max_freq), |
2b6b3a09 D |
7049 | dev_priv->rps.max_freq); |
7050 | ||
7051 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
7052 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7053 | intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
2b6b3a09 D |
7054 | dev_priv->rps.efficient_freq); |
7055 | ||
7707df4a D |
7056 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
7057 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
7c59a9c1 | 7058 | intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), |
7707df4a D |
7059 | dev_priv->rps.rp1_freq); |
7060 | ||
96676fe3 | 7061 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
2b6b3a09 | 7062 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", |
7c59a9c1 | 7063 | intel_gpu_freq(dev_priv, dev_priv->rps.min_freq), |
2b6b3a09 D |
7064 | dev_priv->rps.min_freq); |
7065 | ||
1c14762d VS |
7066 | WARN_ONCE((dev_priv->rps.max_freq | |
7067 | dev_priv->rps.efficient_freq | | |
7068 | dev_priv->rps.rp1_freq | | |
7069 | dev_priv->rps.min_freq) & 1, | |
7070 | "Odd GPU freq values\n"); | |
38807746 D |
7071 | } |
7072 | ||
dc97997a | 7073 | static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
4e80519e | 7074 | { |
dc97997a | 7075 | valleyview_cleanup_pctx(dev_priv); |
4e80519e ID |
7076 | } |
7077 | ||
dc97997a | 7078 | static void cherryview_enable_rps(struct drm_i915_private *dev_priv) |
38807746 | 7079 | { |
e2f80391 | 7080 | struct intel_engine_cs *engine; |
3b3f1650 | 7081 | enum intel_engine_id id; |
2b6b3a09 | 7082 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
7083 | |
7084 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
7085 | ||
297b32ec VS |
7086 | gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV | |
7087 | GT_FIFO_FREE_ENTRIES_CHV); | |
38807746 D |
7088 | if (gtfifodbg) { |
7089 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
7090 | gtfifodbg); | |
7091 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
7092 | } | |
7093 | ||
7094 | cherryview_check_pctx(dev_priv); | |
7095 | ||
7096 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
7097 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
59bad947 | 7098 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
38807746 | 7099 | |
160614a2 VS |
7100 | /* Disable RC states. */ |
7101 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
7102 | ||
38807746 D |
7103 | /* 2a: Program RC6 thresholds.*/ |
7104 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
7105 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
7106 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
7107 | ||
3b3f1650 | 7108 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 7109 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
38807746 D |
7110 | I915_WRITE(GEN6_RC_SLEEP, 0); |
7111 | ||
f4f71c7d D |
7112 | /* TO threshold set to 500 us ( 0x186 * 1.28 us) */ |
7113 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x186); | |
38807746 D |
7114 | |
7115 | /* allows RC6 residency counter to work */ | |
7116 | I915_WRITE(VLV_COUNTER_CONTROL, | |
7117 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
7118 | VLV_MEDIA_RC6_COUNT_EN | | |
7119 | VLV_RENDER_RC6_COUNT_EN)); | |
7120 | ||
7121 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
7122 | pcbr = I915_READ(VLV_PCBR); | |
7123 | ||
38807746 | 7124 | /* 3: Enable RC6 */ |
dc97997a CW |
7125 | if ((intel_enable_rc6() & INTEL_RC6_ENABLE) && |
7126 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
af5a75a3 | 7127 | rc6_mode = GEN7_RC_CTL_TO_MODE; |
38807746 D |
7128 | |
7129 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
7130 | ||
2b6b3a09 | 7131 | /* 4 Program defaults and thresholds for RPS*/ |
3cbdb48f | 7132 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
2b6b3a09 D |
7133 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
7134 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
7135 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
7136 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
7137 | ||
7138 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
7139 | ||
7140 | /* 5: Enable RPS */ | |
7141 | I915_WRITE(GEN6_RP_CONTROL, | |
7142 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
eb973a5e | 7143 | GEN6_RP_MEDIA_IS_GFX | |
2b6b3a09 D |
7144 | GEN6_RP_ENABLE | |
7145 | GEN6_RP_UP_BUSY_AVG | | |
7146 | GEN6_RP_DOWN_IDLE_AVG); | |
7147 | ||
3ef62342 D |
7148 | /* Setting Fixed Bias */ |
7149 | val = VLV_OVERRIDE_EN | | |
7150 | VLV_SOC_TDP_EN | | |
7151 | CHV_BIAS_CPU_50_SOC_50; | |
7152 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
7153 | ||
2b6b3a09 D |
7154 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
7155 | ||
8d40c3ae VS |
7156 | /* RPS code assumes GPLL is used */ |
7157 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
7158 | ||
742f491d | 7159 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
2b6b3a09 D |
7160 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
7161 | ||
3a45b05c | 7162 | reset_rps(dev_priv, valleyview_set_rps); |
2b6b3a09 | 7163 | |
59bad947 | 7164 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
38807746 D |
7165 | } |
7166 | ||
dc97997a | 7167 | static void valleyview_enable_rps(struct drm_i915_private *dev_priv) |
0a073b84 | 7168 | { |
e2f80391 | 7169 | struct intel_engine_cs *engine; |
3b3f1650 | 7170 | enum intel_engine_id id; |
2a5913a8 | 7171 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
7172 | |
7173 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
7174 | ||
ae48434c ID |
7175 | valleyview_check_pctx(dev_priv); |
7176 | ||
297b32ec VS |
7177 | gtfifodbg = I915_READ(GTFIFODBG); |
7178 | if (gtfifodbg) { | |
f7d85c1e JB |
7179 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
7180 | gtfifodbg); | |
0a073b84 JB |
7181 | I915_WRITE(GTFIFODBG, gtfifodbg); |
7182 | } | |
7183 | ||
c8d9a590 | 7184 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
59bad947 | 7185 | intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL); |
0a073b84 | 7186 | |
160614a2 VS |
7187 | /* Disable RC states. */ |
7188 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
7189 | ||
cad725fe | 7190 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000); |
0a073b84 JB |
7191 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); |
7192 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
7193 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
7194 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
7195 | ||
7196 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
7197 | ||
7198 | I915_WRITE(GEN6_RP_CONTROL, | |
7199 | GEN6_RP_MEDIA_TURBO | | |
7200 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7201 | GEN6_RP_MEDIA_IS_GFX | | |
7202 | GEN6_RP_ENABLE | | |
7203 | GEN6_RP_UP_BUSY_AVG | | |
7204 | GEN6_RP_DOWN_IDLE_CONT); | |
7205 | ||
7206 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
7207 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
7208 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
7209 | ||
3b3f1650 | 7210 | for_each_engine(engine, dev_priv, id) |
e2f80391 | 7211 | I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10); |
0a073b84 | 7212 | |
2f0aa304 | 7213 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
7214 | |
7215 | /* allows RC6 residency counter to work */ | |
49798eb2 | 7216 | I915_WRITE(VLV_COUNTER_CONTROL, |
6b7f6aa7 MK |
7217 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | |
7218 | VLV_MEDIA_RC0_COUNT_EN | | |
31685c25 | 7219 | VLV_RENDER_RC0_COUNT_EN | |
49798eb2 JB |
7220 | VLV_MEDIA_RC6_COUNT_EN | |
7221 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 7222 | |
dc97997a | 7223 | if (intel_enable_rc6() & INTEL_RC6_ENABLE) |
6b88f295 | 7224 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 | 7225 | |
dc97997a | 7226 | intel_print_rc6_info(dev_priv, rc6_mode); |
dc39fff7 | 7227 | |
a2b23fe0 | 7228 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 7229 | |
3ef62342 D |
7230 | /* Setting Fixed Bias */ |
7231 | val = VLV_OVERRIDE_EN | | |
7232 | VLV_SOC_TDP_EN | | |
7233 | VLV_BIAS_CPU_125_SOC_875; | |
7234 | vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val); | |
7235 | ||
64936258 | 7236 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 | 7237 | |
8d40c3ae VS |
7238 | /* RPS code assumes GPLL is used */ |
7239 | WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n"); | |
7240 | ||
742f491d | 7241 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE)); |
0a073b84 JB |
7242 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); |
7243 | ||
3a45b05c | 7244 | reset_rps(dev_priv, valleyview_set_rps); |
0a073b84 | 7245 | |
59bad947 | 7246 | intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
7247 | } |
7248 | ||
dde18883 ED |
7249 | static unsigned long intel_pxfreq(u32 vidfreq) |
7250 | { | |
7251 | unsigned long freq; | |
7252 | int div = (vidfreq & 0x3f0000) >> 16; | |
7253 | int post = (vidfreq & 0x3000) >> 12; | |
7254 | int pre = (vidfreq & 0x7); | |
7255 | ||
7256 | if (!pre) | |
7257 | return 0; | |
7258 | ||
7259 | freq = ((div * 133333) / ((1<<post) * pre)); | |
7260 | ||
7261 | return freq; | |
7262 | } | |
7263 | ||
eb48eb00 DV |
7264 | static const struct cparams { |
7265 | u16 i; | |
7266 | u16 t; | |
7267 | u16 m; | |
7268 | u16 c; | |
7269 | } cparams[] = { | |
7270 | { 1, 1333, 301, 28664 }, | |
7271 | { 1, 1066, 294, 24460 }, | |
7272 | { 1, 800, 294, 25192 }, | |
7273 | { 0, 1333, 276, 27605 }, | |
7274 | { 0, 1066, 276, 27605 }, | |
7275 | { 0, 800, 231, 23784 }, | |
7276 | }; | |
7277 | ||
f531dcb2 | 7278 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
7279 | { |
7280 | u64 total_count, diff, ret; | |
7281 | u32 count1, count2, count3, m = 0, c = 0; | |
7282 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
7283 | int i; | |
7284 | ||
67520415 | 7285 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 7286 | |
20e4d407 | 7287 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
7288 | |
7289 | /* Prevent division-by-zero if we are asking too fast. | |
7290 | * Also, we don't get interesting results if we are polling | |
7291 | * faster than once in 10ms, so just return the saved value | |
7292 | * in such cases. | |
7293 | */ | |
7294 | if (diff1 <= 10) | |
20e4d407 | 7295 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
7296 | |
7297 | count1 = I915_READ(DMIEC); | |
7298 | count2 = I915_READ(DDREC); | |
7299 | count3 = I915_READ(CSIEC); | |
7300 | ||
7301 | total_count = count1 + count2 + count3; | |
7302 | ||
7303 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
7304 | if (total_count < dev_priv->ips.last_count1) { |
7305 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
7306 | diff += total_count; |
7307 | } else { | |
20e4d407 | 7308 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
7309 | } |
7310 | ||
7311 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
7312 | if (cparams[i].i == dev_priv->ips.c_m && |
7313 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
7314 | m = cparams[i].m; |
7315 | c = cparams[i].c; | |
7316 | break; | |
7317 | } | |
7318 | } | |
7319 | ||
7320 | diff = div_u64(diff, diff1); | |
7321 | ret = ((m * diff) + c); | |
7322 | ret = div_u64(ret, 10); | |
7323 | ||
20e4d407 DV |
7324 | dev_priv->ips.last_count1 = total_count; |
7325 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 7326 | |
20e4d407 | 7327 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
7328 | |
7329 | return ret; | |
7330 | } | |
7331 | ||
f531dcb2 CW |
7332 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
7333 | { | |
7334 | unsigned long val; | |
7335 | ||
dc97997a | 7336 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
7337 | return 0; |
7338 | ||
7339 | spin_lock_irq(&mchdev_lock); | |
7340 | ||
7341 | val = __i915_chipset_val(dev_priv); | |
7342 | ||
7343 | spin_unlock_irq(&mchdev_lock); | |
7344 | ||
7345 | return val; | |
7346 | } | |
7347 | ||
eb48eb00 DV |
7348 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
7349 | { | |
7350 | unsigned long m, x, b; | |
7351 | u32 tsfs; | |
7352 | ||
7353 | tsfs = I915_READ(TSFS); | |
7354 | ||
7355 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
7356 | x = I915_READ8(TR1); | |
7357 | ||
7358 | b = tsfs & TSFS_INTR_MASK; | |
7359 | ||
7360 | return ((m * x) / 127) - b; | |
7361 | } | |
7362 | ||
d972d6ee MK |
7363 | static int _pxvid_to_vd(u8 pxvid) |
7364 | { | |
7365 | if (pxvid == 0) | |
7366 | return 0; | |
7367 | ||
7368 | if (pxvid >= 8 && pxvid < 31) | |
7369 | pxvid = 31; | |
7370 | ||
7371 | return (pxvid + 2) * 125; | |
7372 | } | |
7373 | ||
7374 | static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
eb48eb00 | 7375 | { |
d972d6ee MK |
7376 | const int vd = _pxvid_to_vd(pxvid); |
7377 | const int vm = vd - 1125; | |
7378 | ||
dc97997a | 7379 | if (INTEL_INFO(dev_priv)->is_mobile) |
d972d6ee MK |
7380 | return vm > 0 ? vm : 0; |
7381 | ||
7382 | return vd; | |
eb48eb00 DV |
7383 | } |
7384 | ||
02d71956 | 7385 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 7386 | { |
5ed0bdf2 | 7387 | u64 now, diff, diffms; |
eb48eb00 DV |
7388 | u32 count; |
7389 | ||
67520415 | 7390 | lockdep_assert_held(&mchdev_lock); |
eb48eb00 | 7391 | |
5ed0bdf2 TG |
7392 | now = ktime_get_raw_ns(); |
7393 | diffms = now - dev_priv->ips.last_time2; | |
7394 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
7395 | |
7396 | /* Don't divide by 0 */ | |
eb48eb00 DV |
7397 | if (!diffms) |
7398 | return; | |
7399 | ||
7400 | count = I915_READ(GFXEC); | |
7401 | ||
20e4d407 DV |
7402 | if (count < dev_priv->ips.last_count2) { |
7403 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
7404 | diff += count; |
7405 | } else { | |
20e4d407 | 7406 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
7407 | } |
7408 | ||
20e4d407 DV |
7409 | dev_priv->ips.last_count2 = count; |
7410 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
7411 | |
7412 | /* More magic constants... */ | |
7413 | diff = diff * 1181; | |
7414 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 7415 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
7416 | } |
7417 | ||
02d71956 DV |
7418 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
7419 | { | |
dc97997a | 7420 | if (INTEL_INFO(dev_priv)->gen != 5) |
02d71956 DV |
7421 | return; |
7422 | ||
9270388e | 7423 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
7424 | |
7425 | __i915_update_gfx_val(dev_priv); | |
7426 | ||
9270388e | 7427 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
7428 | } |
7429 | ||
f531dcb2 | 7430 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
7431 | { |
7432 | unsigned long t, corr, state1, corr2, state2; | |
7433 | u32 pxvid, ext_v; | |
7434 | ||
67520415 | 7435 | lockdep_assert_held(&mchdev_lock); |
02d71956 | 7436 | |
616847e7 | 7437 | pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq)); |
eb48eb00 DV |
7438 | pxvid = (pxvid >> 24) & 0x7f; |
7439 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
7440 | ||
7441 | state1 = ext_v; | |
7442 | ||
7443 | t = i915_mch_val(dev_priv); | |
7444 | ||
7445 | /* Revel in the empirically derived constants */ | |
7446 | ||
7447 | /* Correction factor in 1/100000 units */ | |
7448 | if (t > 80) | |
7449 | corr = ((t * 2349) + 135940); | |
7450 | else if (t >= 50) | |
7451 | corr = ((t * 964) + 29317); | |
7452 | else /* < 50 */ | |
7453 | corr = ((t * 301) + 1004); | |
7454 | ||
7455 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
7456 | corr /= 100000; | |
20e4d407 | 7457 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
7458 | |
7459 | state2 = (corr2 * state1) / 10000; | |
7460 | state2 /= 100; /* convert to mW */ | |
7461 | ||
02d71956 | 7462 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 7463 | |
20e4d407 | 7464 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
7465 | } |
7466 | ||
f531dcb2 CW |
7467 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
7468 | { | |
7469 | unsigned long val; | |
7470 | ||
dc97997a | 7471 | if (INTEL_INFO(dev_priv)->gen != 5) |
f531dcb2 CW |
7472 | return 0; |
7473 | ||
7474 | spin_lock_irq(&mchdev_lock); | |
7475 | ||
7476 | val = __i915_gfx_val(dev_priv); | |
7477 | ||
7478 | spin_unlock_irq(&mchdev_lock); | |
7479 | ||
7480 | return val; | |
7481 | } | |
7482 | ||
eb48eb00 DV |
7483 | /** |
7484 | * i915_read_mch_val - return value for IPS use | |
7485 | * | |
7486 | * Calculate and return a value for the IPS driver to use when deciding whether | |
7487 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
7488 | */ | |
7489 | unsigned long i915_read_mch_val(void) | |
7490 | { | |
7491 | struct drm_i915_private *dev_priv; | |
7492 | unsigned long chipset_val, graphics_val, ret = 0; | |
7493 | ||
9270388e | 7494 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7495 | if (!i915_mch_dev) |
7496 | goto out_unlock; | |
7497 | dev_priv = i915_mch_dev; | |
7498 | ||
f531dcb2 CW |
7499 | chipset_val = __i915_chipset_val(dev_priv); |
7500 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
7501 | |
7502 | ret = chipset_val + graphics_val; | |
7503 | ||
7504 | out_unlock: | |
9270388e | 7505 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7506 | |
7507 | return ret; | |
7508 | } | |
7509 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
7510 | ||
7511 | /** | |
7512 | * i915_gpu_raise - raise GPU frequency limit | |
7513 | * | |
7514 | * Raise the limit; IPS indicates we have thermal headroom. | |
7515 | */ | |
7516 | bool i915_gpu_raise(void) | |
7517 | { | |
7518 | struct drm_i915_private *dev_priv; | |
7519 | bool ret = true; | |
7520 | ||
9270388e | 7521 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7522 | if (!i915_mch_dev) { |
7523 | ret = false; | |
7524 | goto out_unlock; | |
7525 | } | |
7526 | dev_priv = i915_mch_dev; | |
7527 | ||
20e4d407 DV |
7528 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
7529 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
7530 | |
7531 | out_unlock: | |
9270388e | 7532 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7533 | |
7534 | return ret; | |
7535 | } | |
7536 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
7537 | ||
7538 | /** | |
7539 | * i915_gpu_lower - lower GPU frequency limit | |
7540 | * | |
7541 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
7542 | * frequency maximum. | |
7543 | */ | |
7544 | bool i915_gpu_lower(void) | |
7545 | { | |
7546 | struct drm_i915_private *dev_priv; | |
7547 | bool ret = true; | |
7548 | ||
9270388e | 7549 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7550 | if (!i915_mch_dev) { |
7551 | ret = false; | |
7552 | goto out_unlock; | |
7553 | } | |
7554 | dev_priv = i915_mch_dev; | |
7555 | ||
20e4d407 DV |
7556 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
7557 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
7558 | |
7559 | out_unlock: | |
9270388e | 7560 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7561 | |
7562 | return ret; | |
7563 | } | |
7564 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
7565 | ||
7566 | /** | |
7567 | * i915_gpu_busy - indicate GPU business to IPS | |
7568 | * | |
7569 | * Tell the IPS driver whether or not the GPU is busy. | |
7570 | */ | |
7571 | bool i915_gpu_busy(void) | |
7572 | { | |
eb48eb00 DV |
7573 | bool ret = false; |
7574 | ||
9270388e | 7575 | spin_lock_irq(&mchdev_lock); |
dcff85c8 CW |
7576 | if (i915_mch_dev) |
7577 | ret = i915_mch_dev->gt.awake; | |
9270388e | 7578 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7579 | |
7580 | return ret; | |
7581 | } | |
7582 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
7583 | ||
7584 | /** | |
7585 | * i915_gpu_turbo_disable - disable graphics turbo | |
7586 | * | |
7587 | * Disable graphics turbo by resetting the max frequency and setting the | |
7588 | * current frequency to the default. | |
7589 | */ | |
7590 | bool i915_gpu_turbo_disable(void) | |
7591 | { | |
7592 | struct drm_i915_private *dev_priv; | |
7593 | bool ret = true; | |
7594 | ||
9270388e | 7595 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
7596 | if (!i915_mch_dev) { |
7597 | ret = false; | |
7598 | goto out_unlock; | |
7599 | } | |
7600 | dev_priv = i915_mch_dev; | |
7601 | ||
20e4d407 | 7602 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 7603 | |
91d14251 | 7604 | if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart)) |
eb48eb00 DV |
7605 | ret = false; |
7606 | ||
7607 | out_unlock: | |
9270388e | 7608 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7609 | |
7610 | return ret; | |
7611 | } | |
7612 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
7613 | ||
7614 | /** | |
7615 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
7616 | * IPS got loaded first. | |
7617 | * | |
7618 | * This awkward dance is so that neither module has to depend on the | |
7619 | * other in order for IPS to do the appropriate communication of | |
7620 | * GPU turbo limits to i915. | |
7621 | */ | |
7622 | static void | |
7623 | ips_ping_for_i915_load(void) | |
7624 | { | |
7625 | void (*link)(void); | |
7626 | ||
7627 | link = symbol_get(ips_link_to_i915_driver); | |
7628 | if (link) { | |
7629 | link(); | |
7630 | symbol_put(ips_link_to_i915_driver); | |
7631 | } | |
7632 | } | |
7633 | ||
7634 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
7635 | { | |
02d71956 DV |
7636 | /* We only register the i915 ips part with intel-ips once everything is |
7637 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 7638 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 7639 | i915_mch_dev = dev_priv; |
9270388e | 7640 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
7641 | |
7642 | ips_ping_for_i915_load(); | |
7643 | } | |
7644 | ||
7645 | void intel_gpu_ips_teardown(void) | |
7646 | { | |
9270388e | 7647 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 7648 | i915_mch_dev = NULL; |
9270388e | 7649 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 7650 | } |
76c3552f | 7651 | |
dc97997a | 7652 | static void intel_init_emon(struct drm_i915_private *dev_priv) |
dde18883 | 7653 | { |
dde18883 ED |
7654 | u32 lcfuse; |
7655 | u8 pxw[16]; | |
7656 | int i; | |
7657 | ||
7658 | /* Disable to program */ | |
7659 | I915_WRITE(ECR, 0); | |
7660 | POSTING_READ(ECR); | |
7661 | ||
7662 | /* Program energy weights for various events */ | |
7663 | I915_WRITE(SDEW, 0x15040d00); | |
7664 | I915_WRITE(CSIEW0, 0x007f0000); | |
7665 | I915_WRITE(CSIEW1, 0x1e220004); | |
7666 | I915_WRITE(CSIEW2, 0x04000004); | |
7667 | ||
7668 | for (i = 0; i < 5; i++) | |
616847e7 | 7669 | I915_WRITE(PEW(i), 0); |
dde18883 | 7670 | for (i = 0; i < 3; i++) |
616847e7 | 7671 | I915_WRITE(DEW(i), 0); |
dde18883 ED |
7672 | |
7673 | /* Program P-state weights to account for frequency power adjustment */ | |
7674 | for (i = 0; i < 16; i++) { | |
616847e7 | 7675 | u32 pxvidfreq = I915_READ(PXVFREQ(i)); |
dde18883 ED |
7676 | unsigned long freq = intel_pxfreq(pxvidfreq); |
7677 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
7678 | PXVFREQ_PX_SHIFT; | |
7679 | unsigned long val; | |
7680 | ||
7681 | val = vid * vid; | |
7682 | val *= (freq / 1000); | |
7683 | val *= 255; | |
7684 | val /= (127*127*900); | |
7685 | if (val > 0xff) | |
7686 | DRM_ERROR("bad pxval: %ld\n", val); | |
7687 | pxw[i] = val; | |
7688 | } | |
7689 | /* Render standby states get 0 weight */ | |
7690 | pxw[14] = 0; | |
7691 | pxw[15] = 0; | |
7692 | ||
7693 | for (i = 0; i < 4; i++) { | |
7694 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
7695 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
616847e7 | 7696 | I915_WRITE(PXW(i), val); |
dde18883 ED |
7697 | } |
7698 | ||
7699 | /* Adjust magic regs to magic values (more experimental results) */ | |
7700 | I915_WRITE(OGW0, 0); | |
7701 | I915_WRITE(OGW1, 0); | |
7702 | I915_WRITE(EG0, 0x00007f00); | |
7703 | I915_WRITE(EG1, 0x0000000e); | |
7704 | I915_WRITE(EG2, 0x000e0000); | |
7705 | I915_WRITE(EG3, 0x68000300); | |
7706 | I915_WRITE(EG4, 0x42000000); | |
7707 | I915_WRITE(EG5, 0x00140031); | |
7708 | I915_WRITE(EG6, 0); | |
7709 | I915_WRITE(EG7, 0); | |
7710 | ||
7711 | for (i = 0; i < 8; i++) | |
616847e7 | 7712 | I915_WRITE(PXWL(i), 0); |
dde18883 ED |
7713 | |
7714 | /* Enable PMON + select events */ | |
7715 | I915_WRITE(ECR, 0x80000019); | |
7716 | ||
7717 | lcfuse = I915_READ(LCFUSE02); | |
7718 | ||
20e4d407 | 7719 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
7720 | } |
7721 | ||
dc97997a | 7722 | void intel_init_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 7723 | { |
b268c699 ID |
7724 | /* |
7725 | * RPM depends on RC6 to save restore the GT HW context, so make RC6 a | |
7726 | * requirement. | |
7727 | */ | |
7728 | if (!i915.enable_rc6) { | |
7729 | DRM_INFO("RC6 disabled, disabling runtime PM support\n"); | |
7730 | intel_runtime_pm_get(dev_priv); | |
7731 | } | |
e6069ca8 | 7732 | |
b5163dbb | 7733 | mutex_lock(&dev_priv->drm.struct_mutex); |
773ea9a8 CW |
7734 | mutex_lock(&dev_priv->rps.hw_lock); |
7735 | ||
7736 | /* Initialize RPS limits (for userspace) */ | |
dc97997a CW |
7737 | if (IS_CHERRYVIEW(dev_priv)) |
7738 | cherryview_init_gt_powersave(dev_priv); | |
7739 | else if (IS_VALLEYVIEW(dev_priv)) | |
7740 | valleyview_init_gt_powersave(dev_priv); | |
2a13ae79 | 7741 | else if (INTEL_GEN(dev_priv) >= 6) |
773ea9a8 CW |
7742 | gen6_init_rps_frequencies(dev_priv); |
7743 | ||
7744 | /* Derive initial user preferences/limits from the hardware limits */ | |
7745 | dev_priv->rps.idle_freq = dev_priv->rps.min_freq; | |
7746 | dev_priv->rps.cur_freq = dev_priv->rps.idle_freq; | |
7747 | ||
7748 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
7749 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
7750 | ||
7751 | if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) | |
7752 | dev_priv->rps.min_freq_softlimit = | |
7753 | max_t(int, | |
7754 | dev_priv->rps.efficient_freq, | |
7755 | intel_freq_opcode(dev_priv, 450)); | |
7756 | ||
99ac9612 CW |
7757 | /* After setting max-softlimit, find the overclock max freq */ |
7758 | if (IS_GEN6(dev_priv) || | |
7759 | IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) { | |
7760 | u32 params = 0; | |
7761 | ||
7762 | sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, ¶ms); | |
7763 | if (params & BIT(31)) { /* OC supported */ | |
7764 | DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n", | |
7765 | (dev_priv->rps.max_freq & 0xff) * 50, | |
7766 | (params & 0xff) * 50); | |
7767 | dev_priv->rps.max_freq = params & 0xff; | |
7768 | } | |
7769 | } | |
7770 | ||
29ecd78d CW |
7771 | /* Finally allow us to boost to max by default */ |
7772 | dev_priv->rps.boost_freq = dev_priv->rps.max_freq; | |
7773 | ||
773ea9a8 | 7774 | mutex_unlock(&dev_priv->rps.hw_lock); |
b5163dbb | 7775 | mutex_unlock(&dev_priv->drm.struct_mutex); |
54b4f68f CW |
7776 | |
7777 | intel_autoenable_gt_powersave(dev_priv); | |
ae48434c ID |
7778 | } |
7779 | ||
dc97997a | 7780 | void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv) |
ae48434c | 7781 | { |
8dac1e1f | 7782 | if (IS_VALLEYVIEW(dev_priv)) |
dc97997a | 7783 | valleyview_cleanup_gt_powersave(dev_priv); |
b268c699 ID |
7784 | |
7785 | if (!i915.enable_rc6) | |
7786 | intel_runtime_pm_put(dev_priv); | |
ae48434c ID |
7787 | } |
7788 | ||
54b4f68f CW |
7789 | /** |
7790 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
7791 | * @dev_priv: i915 device | |
7792 | * | |
7793 | * We don't want to disable RC6 or other features here, we just want | |
7794 | * to make sure any work we've queued has finished and won't bother | |
7795 | * us while we're suspended. | |
7796 | */ | |
7797 | void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv) | |
7798 | { | |
7799 | if (INTEL_GEN(dev_priv) < 6) | |
7800 | return; | |
7801 | ||
7802 | if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work)) | |
7803 | intel_runtime_pm_put(dev_priv); | |
7804 | ||
7805 | /* gen6_rps_idle() will be called later to disable interrupts */ | |
7806 | } | |
7807 | ||
b7137e0c CW |
7808 | void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv) |
7809 | { | |
7810 | dev_priv->rps.enabled = true; /* force disabling */ | |
7811 | intel_disable_gt_powersave(dev_priv); | |
54b4f68f CW |
7812 | |
7813 | gen6_reset_rps_interrupts(dev_priv); | |
156c7ca0 JB |
7814 | } |
7815 | ||
dc97997a | 7816 | void intel_disable_gt_powersave(struct drm_i915_private *dev_priv) |
8090c6b9 | 7817 | { |
b7137e0c CW |
7818 | if (!READ_ONCE(dev_priv->rps.enabled)) |
7819 | return; | |
e494837a | 7820 | |
b7137e0c | 7821 | mutex_lock(&dev_priv->rps.hw_lock); |
e534770a | 7822 | |
b7137e0c CW |
7823 | if (INTEL_GEN(dev_priv) >= 9) { |
7824 | gen9_disable_rc6(dev_priv); | |
7825 | gen9_disable_rps(dev_priv); | |
7826 | } else if (IS_CHERRYVIEW(dev_priv)) { | |
7827 | cherryview_disable_rps(dev_priv); | |
7828 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7829 | valleyview_disable_rps(dev_priv); | |
7830 | } else if (INTEL_GEN(dev_priv) >= 6) { | |
7831 | gen6_disable_rps(dev_priv); | |
7832 | } else if (IS_IRONLAKE_M(dev_priv)) { | |
7833 | ironlake_disable_drps(dev_priv); | |
930ebb46 | 7834 | } |
b7137e0c CW |
7835 | |
7836 | dev_priv->rps.enabled = false; | |
7837 | mutex_unlock(&dev_priv->rps.hw_lock); | |
8090c6b9 DV |
7838 | } |
7839 | ||
b7137e0c | 7840 | void intel_enable_gt_powersave(struct drm_i915_private *dev_priv) |
1a01ab3b | 7841 | { |
54b4f68f CW |
7842 | /* We shouldn't be disabling as we submit, so this should be less |
7843 | * racy than it appears! | |
7844 | */ | |
b7137e0c CW |
7845 | if (READ_ONCE(dev_priv->rps.enabled)) |
7846 | return; | |
1a01ab3b | 7847 | |
b7137e0c CW |
7848 | /* Powersaving is controlled by the host when inside a VM */ |
7849 | if (intel_vgpu_active(dev_priv)) | |
7850 | return; | |
0a073b84 | 7851 | |
b7137e0c | 7852 | mutex_lock(&dev_priv->rps.hw_lock); |
dc97997a CW |
7853 | |
7854 | if (IS_CHERRYVIEW(dev_priv)) { | |
7855 | cherryview_enable_rps(dev_priv); | |
7856 | } else if (IS_VALLEYVIEW(dev_priv)) { | |
7857 | valleyview_enable_rps(dev_priv); | |
b7137e0c | 7858 | } else if (INTEL_GEN(dev_priv) >= 9) { |
dc97997a CW |
7859 | gen9_enable_rc6(dev_priv); |
7860 | gen9_enable_rps(dev_priv); | |
35ceabf3 | 7861 | if (IS_GEN9_BC(dev_priv) || IS_CANNONLAKE(dev_priv)) |
fb7404e8 | 7862 | gen6_update_ring_freq(dev_priv); |
dc97997a CW |
7863 | } else if (IS_BROADWELL(dev_priv)) { |
7864 | gen8_enable_rps(dev_priv); | |
fb7404e8 | 7865 | gen6_update_ring_freq(dev_priv); |
b7137e0c | 7866 | } else if (INTEL_GEN(dev_priv) >= 6) { |
dc97997a | 7867 | gen6_enable_rps(dev_priv); |
fb7404e8 | 7868 | gen6_update_ring_freq(dev_priv); |
b7137e0c CW |
7869 | } else if (IS_IRONLAKE_M(dev_priv)) { |
7870 | ironlake_enable_drps(dev_priv); | |
7871 | intel_init_emon(dev_priv); | |
0a073b84 | 7872 | } |
aed242ff CW |
7873 | |
7874 | WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq); | |
7875 | WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq); | |
7876 | ||
7877 | WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq); | |
7878 | WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq); | |
7879 | ||
54b4f68f | 7880 | dev_priv->rps.enabled = true; |
b7137e0c CW |
7881 | mutex_unlock(&dev_priv->rps.hw_lock); |
7882 | } | |
3cc134e3 | 7883 | |
54b4f68f CW |
7884 | static void __intel_autoenable_gt_powersave(struct work_struct *work) |
7885 | { | |
7886 | struct drm_i915_private *dev_priv = | |
7887 | container_of(work, typeof(*dev_priv), rps.autoenable_work.work); | |
7888 | struct intel_engine_cs *rcs; | |
7889 | struct drm_i915_gem_request *req; | |
7890 | ||
7891 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7892 | goto out; | |
7893 | ||
3b3f1650 | 7894 | rcs = dev_priv->engine[RCS]; |
e8a9c58f | 7895 | if (rcs->last_retired_context) |
54b4f68f CW |
7896 | goto out; |
7897 | ||
7898 | if (!rcs->init_context) | |
7899 | goto out; | |
7900 | ||
7901 | mutex_lock(&dev_priv->drm.struct_mutex); | |
7902 | ||
7903 | req = i915_gem_request_alloc(rcs, dev_priv->kernel_context); | |
7904 | if (IS_ERR(req)) | |
7905 | goto unlock; | |
7906 | ||
7907 | if (!i915.enable_execlists && i915_switch_context(req) == 0) | |
7908 | rcs->init_context(req); | |
7909 | ||
7910 | /* Mark the device busy, calling intel_enable_gt_powersave() */ | |
e642c85b | 7911 | i915_add_request(req); |
54b4f68f CW |
7912 | |
7913 | unlock: | |
7914 | mutex_unlock(&dev_priv->drm.struct_mutex); | |
7915 | out: | |
7916 | intel_runtime_pm_put(dev_priv); | |
7917 | } | |
7918 | ||
7919 | void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv) | |
7920 | { | |
7921 | if (READ_ONCE(dev_priv->rps.enabled)) | |
7922 | return; | |
7923 | ||
7924 | if (IS_IRONLAKE_M(dev_priv)) { | |
7925 | ironlake_enable_drps(dev_priv); | |
54b4f68f | 7926 | intel_init_emon(dev_priv); |
54b4f68f CW |
7927 | } else if (INTEL_INFO(dev_priv)->gen >= 6) { |
7928 | /* | |
7929 | * PCU communication is slow and this doesn't need to be | |
7930 | * done at any specific time, so do this out of our fast path | |
7931 | * to make resume and init faster. | |
7932 | * | |
7933 | * We depend on the HW RC6 power context save/restore | |
7934 | * mechanism when entering D3 through runtime PM suspend. So | |
7935 | * disable RPM until RPS/RC6 is properly setup. We can only | |
7936 | * get here via the driver load/system resume/runtime resume | |
7937 | * paths, so the _noresume version is enough (and in case of | |
7938 | * runtime resume it's necessary). | |
7939 | */ | |
7940 | if (queue_delayed_work(dev_priv->wq, | |
7941 | &dev_priv->rps.autoenable_work, | |
7942 | round_jiffies_up_relative(HZ))) | |
7943 | intel_runtime_pm_get_noresume(dev_priv); | |
7944 | } | |
7945 | } | |
7946 | ||
46f16e63 | 7947 | static void ibx_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 7948 | { |
3107bd48 DV |
7949 | /* |
7950 | * On Ibex Peak and Cougar Point, we need to disable clock | |
7951 | * gating for the panel power sequencer or it will fail to | |
7952 | * start up when no ports are active. | |
7953 | */ | |
7954 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
7955 | } | |
7956 | ||
46f16e63 | 7957 | static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv) |
0e088b8f | 7958 | { |
b12ce1d8 | 7959 | enum pipe pipe; |
0e088b8f | 7960 | |
055e393f | 7961 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
7962 | I915_WRITE(DSPCNTR(pipe), |
7963 | I915_READ(DSPCNTR(pipe)) | | |
7964 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
b12ce1d8 VS |
7965 | |
7966 | I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe))); | |
7967 | POSTING_READ(DSPSURF(pipe)); | |
0e088b8f VS |
7968 | } |
7969 | } | |
7970 | ||
46f16e63 | 7971 | static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv) |
017636cc | 7972 | { |
017636cc VS |
7973 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); |
7974 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
7975 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
7976 | ||
7977 | /* | |
7978 | * Don't touch WM1S_LP_EN here. | |
7979 | * Doing so could cause underruns. | |
7980 | */ | |
7981 | } | |
7982 | ||
46f16e63 | 7983 | static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 7984 | { |
231e54f6 | 7985 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 7986 | |
f1e8fa56 DL |
7987 | /* |
7988 | * Required for FBC | |
7989 | * WaFbcDisableDpfcClockGating:ilk | |
7990 | */ | |
4d47e4f5 DL |
7991 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
7992 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
7993 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
7994 | |
7995 | I915_WRITE(PCH_3DCGDIS0, | |
7996 | MARIUNIT_CLOCK_GATE_DISABLE | | |
7997 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
7998 | I915_WRITE(PCH_3DCGDIS1, | |
7999 | VFMUNIT_CLOCK_GATE_DISABLE); | |
8000 | ||
6f1d69b0 ED |
8001 | /* |
8002 | * According to the spec the following bits should be set in | |
8003 | * order to enable memory self-refresh | |
8004 | * The bit 22/21 of 0x42004 | |
8005 | * The bit 5 of 0x42020 | |
8006 | * The bit 15 of 0x45000 | |
8007 | */ | |
8008 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8009 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8010 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 8011 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
8012 | I915_WRITE(DISP_ARB_CTL, |
8013 | (I915_READ(DISP_ARB_CTL) | | |
8014 | DISP_FBC_WM_DIS)); | |
017636cc | 8015 | |
46f16e63 | 8016 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 ED |
8017 | |
8018 | /* | |
8019 | * Based on the document from hardware guys the following bits | |
8020 | * should be set unconditionally in order to enable FBC. | |
8021 | * The bit 22 of 0x42000 | |
8022 | * The bit 22 of 0x42004 | |
8023 | * The bit 7,8,9 of 0x42020. | |
8024 | */ | |
50a0bc90 | 8025 | if (IS_IRONLAKE_M(dev_priv)) { |
4bb35334 | 8026 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
8027 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
8028 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8029 | ILK_FBCQ_DIS); | |
8030 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8031 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8032 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
8033 | } |
8034 | ||
4d47e4f5 DL |
8035 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
8036 | ||
6f1d69b0 ED |
8037 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
8038 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8039 | ILK_ELPIN_409_SELECT); | |
8040 | I915_WRITE(_3D_CHICKEN2, | |
8041 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
8042 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 8043 | |
ecdb4eb7 | 8044 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
8045 | I915_WRITE(CACHE_MODE_0, |
8046 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 8047 | |
4e04632e AG |
8048 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
8049 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8050 | ||
46f16e63 | 8051 | g4x_disable_trickle_feed(dev_priv); |
bdad2b2f | 8052 | |
46f16e63 | 8053 | ibx_init_clock_gating(dev_priv); |
3107bd48 DV |
8054 | } |
8055 | ||
46f16e63 | 8056 | static void cpt_init_clock_gating(struct drm_i915_private *dev_priv) |
3107bd48 | 8057 | { |
3107bd48 | 8058 | int pipe; |
3f704fa2 | 8059 | uint32_t val; |
3107bd48 DV |
8060 | |
8061 | /* | |
8062 | * On Ibex Peak and Cougar Point, we need to disable clock | |
8063 | * gating for the panel power sequencer or it will fail to | |
8064 | * start up when no ports are active. | |
8065 | */ | |
cd664078 JB |
8066 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
8067 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
8068 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
8069 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
8070 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
8071 | /* The below fixes the weird display corruption, a few pixels shifted |
8072 | * downward, on (only) LVDS of some HP laptops with IVY. | |
8073 | */ | |
055e393f | 8074 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
8075 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
8076 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
8077 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 8078 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 8079 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
8080 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
8081 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
8082 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
8083 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
8084 | } | |
3107bd48 | 8085 | /* WADP0ClockGatingDisable */ |
055e393f | 8086 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
8087 | I915_WRITE(TRANS_CHICKEN1(pipe), |
8088 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
8089 | } | |
6f1d69b0 ED |
8090 | } |
8091 | ||
46f16e63 | 8092 | static void gen6_check_mch_setup(struct drm_i915_private *dev_priv) |
1d7aaa0c | 8093 | { |
1d7aaa0c DV |
8094 | uint32_t tmp; |
8095 | ||
8096 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
8097 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
8098 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
8099 | tmp); | |
1d7aaa0c DV |
8100 | } |
8101 | ||
46f16e63 | 8102 | static void gen6_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8103 | { |
231e54f6 | 8104 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 8105 | |
231e54f6 | 8106 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
8107 | |
8108 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8109 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8110 | ILK_ELPIN_409_SELECT); | |
8111 | ||
ecdb4eb7 | 8112 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
8113 | I915_WRITE(_3D_CHICKEN, |
8114 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
8115 | ||
4e04632e AG |
8116 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
8117 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8118 | ||
8d85d272 VS |
8119 | /* |
8120 | * BSpec recoomends 8x4 when MSAA is used, | |
8121 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
8122 | * |
8123 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8124 | * disable bit, which we don't touch here, but it's good | |
8125 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
8126 | */ |
8127 | I915_WRITE(GEN6_GT_MODE, | |
98533251 | 8128 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
8d85d272 | 8129 | |
46f16e63 | 8130 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 8131 | |
6f1d69b0 | 8132 | I915_WRITE(CACHE_MODE_0, |
50743298 | 8133 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
8134 | |
8135 | I915_WRITE(GEN6_UCGCTL1, | |
8136 | I915_READ(GEN6_UCGCTL1) | | |
8137 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
8138 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
8139 | ||
8140 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
8141 | * gating disable must be set. Failure to set it results in | |
8142 | * flickering pixels due to Z write ordering failures after | |
8143 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
8144 | * Sanctuary and Tropics, and apparently anything else with | |
8145 | * alpha test or pixel discard. | |
8146 | * | |
8147 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
8148 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 8149 | * |
ef59318c VS |
8150 | * WaDisableRCCUnitClockGating:snb |
8151 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
8152 | */ |
8153 | I915_WRITE(GEN6_UCGCTL2, | |
8154 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
8155 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
8156 | ||
5eb146dd | 8157 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
8158 | I915_WRITE(_3D_CHICKEN3, |
8159 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 8160 | |
e927ecde VS |
8161 | /* |
8162 | * Bspec says: | |
8163 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
8164 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
8165 | */ | |
8166 | I915_WRITE(_3D_CHICKEN3, | |
8167 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
8168 | ||
6f1d69b0 ED |
8169 | /* |
8170 | * According to the spec the following bits should be | |
8171 | * set in order to enable memory self-refresh and fbc: | |
8172 | * The bit21 and bit22 of 0x42000 | |
8173 | * The bit21 and bit22 of 0x42004 | |
8174 | * The bit5 and bit7 of 0x42020 | |
8175 | * The bit14 of 0x70180 | |
8176 | * The bit14 of 0x71180 | |
4bb35334 DL |
8177 | * |
8178 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
8179 | */ |
8180 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
8181 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
8182 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
8183 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
8184 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
8185 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
8186 | I915_WRITE(ILK_DSPCLK_GATE_D, |
8187 | I915_READ(ILK_DSPCLK_GATE_D) | | |
8188 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
8189 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 8190 | |
46f16e63 | 8191 | g4x_disable_trickle_feed(dev_priv); |
f8f2ac9a | 8192 | |
46f16e63 | 8193 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 8194 | |
46f16e63 | 8195 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
8196 | } |
8197 | ||
8198 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
8199 | { | |
8200 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
8201 | ||
3aad9059 | 8202 | /* |
46680e0a | 8203 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
8204 | * |
8205 | * This actually overrides the dispatch | |
8206 | * mode for all thread types. | |
8207 | */ | |
6f1d69b0 ED |
8208 | reg &= ~GEN7_FF_SCHED_MASK; |
8209 | reg |= GEN7_FF_TS_SCHED_HW; | |
8210 | reg |= GEN7_FF_VS_SCHED_HW; | |
8211 | reg |= GEN7_FF_DS_SCHED_HW; | |
8212 | ||
8213 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
8214 | } | |
8215 | ||
46f16e63 | 8216 | static void lpt_init_clock_gating(struct drm_i915_private *dev_priv) |
17a303ec | 8217 | { |
17a303ec PZ |
8218 | /* |
8219 | * TODO: this bit should only be enabled when really needed, then | |
8220 | * disabled when not needed anymore in order to save power. | |
8221 | */ | |
4f8036a2 | 8222 | if (HAS_PCH_LPT_LP(dev_priv)) |
17a303ec PZ |
8223 | I915_WRITE(SOUTH_DSPCLK_GATE_D, |
8224 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
8225 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
8226 | |
8227 | /* WADPOClockGatingDisable:hsw */ | |
36c0d0cf VS |
8228 | I915_WRITE(TRANS_CHICKEN1(PIPE_A), |
8229 | I915_READ(TRANS_CHICKEN1(PIPE_A)) | | |
0a790cdb | 8230 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); |
17a303ec PZ |
8231 | } |
8232 | ||
712bf364 | 8233 | static void lpt_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 8234 | { |
4f8036a2 | 8235 | if (HAS_PCH_LPT_LP(dev_priv)) { |
7d708ee4 ID |
8236 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); |
8237 | ||
8238 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
8239 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
8240 | } | |
8241 | } | |
8242 | ||
450174fe ID |
8243 | static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv, |
8244 | int general_prio_credits, | |
8245 | int high_prio_credits) | |
8246 | { | |
8247 | u32 misccpctl; | |
8248 | ||
8249 | /* WaTempDisableDOPClkGating:bdw */ | |
8250 | misccpctl = I915_READ(GEN7_MISCCPCTL); | |
8251 | I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE); | |
8252 | ||
8253 | I915_WRITE(GEN8_L3SQCREG1, | |
8254 | L3_GENERAL_PRIO_CREDITS(general_prio_credits) | | |
8255 | L3_HIGH_PRIO_CREDITS(high_prio_credits)); | |
8256 | ||
8257 | /* | |
8258 | * Wait at least 100 clocks before re-enabling clock gating. | |
8259 | * See the definition of L3SQCREG1 in BSpec. | |
8260 | */ | |
8261 | POSTING_READ(GEN8_L3SQCREG1); | |
8262 | udelay(1); | |
8263 | I915_WRITE(GEN7_MISCCPCTL, misccpctl); | |
8264 | } | |
8265 | ||
90007bca RV |
8266 | static void cannonlake_init_clock_gating(struct drm_i915_private *dev_priv) |
8267 | { | |
1a25db65 RV |
8268 | /* This is not an Wa. Enable for better image quality */ |
8269 | I915_WRITE(_3D_CHICKEN3, | |
8270 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_AA_LINE_QUALITY_FIX_ENABLE)); | |
8271 | ||
90007bca RV |
8272 | /* WaEnableChickenDCPR:cnl */ |
8273 | I915_WRITE(GEN8_CHICKEN_DCPR_1, | |
8274 | I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM); | |
8275 | ||
8276 | /* WaFbcWakeMemOn:cnl */ | |
8277 | I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) | | |
8278 | DISP_FBC_MEMORY_WAKE); | |
8279 | ||
8280 | /* WaSarbUnitClockGatingDisable:cnl (pre-prod) */ | |
8281 | if (IS_CNL_REVID(dev_priv, CNL_REVID_A0, CNL_REVID_B0)) | |
8282 | I915_WRITE(SLICE_UNIT_LEVEL_CLKGATE, | |
8283 | I915_READ(SLICE_UNIT_LEVEL_CLKGATE) | | |
8284 | SARBUNIT_CLKGATE_DIS); | |
8285 | } | |
8286 | ||
46f16e63 | 8287 | static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv) |
9498dba7 | 8288 | { |
46f16e63 | 8289 | gen9_init_clock_gating(dev_priv); |
9498dba7 MK |
8290 | |
8291 | /* WaDisableSDEUnitClockGating:kbl */ | |
8292 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
8293 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8294 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
8aeb7f62 MK |
8295 | |
8296 | /* WaDisableGamClockGating:kbl */ | |
8297 | if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0)) | |
8298 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
8299 | GEN6_GAMUNIT_CLOCK_GATE_DISABLE); | |
031cd8c8 | 8300 | |
82525c17 | 8301 | /* WaFbcNukeOnHostModify:kbl,cfl */ |
031cd8c8 MK |
8302 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | |
8303 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
9498dba7 MK |
8304 | } |
8305 | ||
46f16e63 | 8306 | static void skylake_init_clock_gating(struct drm_i915_private *dev_priv) |
dc00b6a0 | 8307 | { |
46f16e63 | 8308 | gen9_init_clock_gating(dev_priv); |
44fff99f MK |
8309 | |
8310 | /* WAC6entrylatency:skl */ | |
8311 | I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) | | |
8312 | FBC_LLC_FULLY_OPEN); | |
031cd8c8 MK |
8313 | |
8314 | /* WaFbcNukeOnHostModify:skl */ | |
8315 | I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) | | |
8316 | ILK_DPFC_NUKE_ON_ANY_MODIFICATION); | |
dc00b6a0 DV |
8317 | } |
8318 | ||
46f16e63 | 8319 | static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv) |
1020a5c2 | 8320 | { |
07d27e20 | 8321 | enum pipe pipe; |
1020a5c2 | 8322 | |
46f16e63 | 8323 | ilk_init_lp_watermarks(dev_priv); |
50ed5fbd | 8324 | |
ab57fff1 | 8325 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 8326 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 8327 | |
ab57fff1 | 8328 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
8329 | I915_WRITE(CHICKEN_PAR1_1, |
8330 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
8331 | ||
ab57fff1 | 8332 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 8333 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 8334 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 8335 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 8336 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 8337 | } |
63801f21 | 8338 | |
ab57fff1 BW |
8339 | /* WaVSRefCountFullforceMissDisable:bdw */ |
8340 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
8341 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8342 | I915_READ(GEN7_FF_THREAD_MODE) & | |
8343 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 8344 | |
295e8bb7 VS |
8345 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
8346 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
8347 | |
8348 | /* WaDisableSDEUnitClockGating:bdw */ | |
8349 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8350 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 8351 | |
450174fe ID |
8352 | /* WaProgramL3SqcReg1Default:bdw */ |
8353 | gen8_set_l3sqc_credits(dev_priv, 30, 2); | |
4d487cff | 8354 | |
6d50b065 VS |
8355 | /* |
8356 | * WaGttCachingOffByDefault:bdw | |
8357 | * GTT cache may not work with big pages, so if those | |
8358 | * are ever enabled GTT cache may need to be disabled. | |
8359 | */ | |
8360 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
8361 | ||
17e0adf0 MK |
8362 | /* WaKVMNotificationOnConfigChange:bdw */ |
8363 | I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1) | |
8364 | | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT); | |
8365 | ||
46f16e63 | 8366 | lpt_init_clock_gating(dev_priv); |
9cc19733 RB |
8367 | |
8368 | /* WaDisableDopClockGating:bdw | |
8369 | * | |
8370 | * Also see the CHICKEN2 write in bdw_init_workarounds() to disable DOP | |
8371 | * clock gating. | |
8372 | */ | |
8373 | I915_WRITE(GEN6_UCGCTL1, | |
8374 | I915_READ(GEN6_UCGCTL1) | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
1020a5c2 BW |
8375 | } |
8376 | ||
46f16e63 | 8377 | static void haswell_init_clock_gating(struct drm_i915_private *dev_priv) |
cad2a2d7 | 8378 | { |
46f16e63 | 8379 | ilk_init_lp_watermarks(dev_priv); |
cad2a2d7 | 8380 | |
f3fc4884 FJ |
8381 | /* L3 caching of data atomics doesn't work -- disable it. */ |
8382 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
8383 | I915_WRITE(HSW_ROW_CHICKEN3, | |
8384 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
8385 | ||
ecdb4eb7 | 8386 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
8387 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8388 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8389 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8390 | ||
e36ea7ff VS |
8391 | /* WaVSRefCountFullforceMissDisable:hsw */ |
8392 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8393 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 8394 | |
4e04632e AG |
8395 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
8396 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8397 | ||
fe27c606 CW |
8398 | /* enable HiZ Raw Stall Optimization */ |
8399 | I915_WRITE(CACHE_MODE_0_GEN7, | |
8400 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
8401 | ||
ecdb4eb7 | 8402 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
8403 | I915_WRITE(CACHE_MODE_1, |
8404 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 8405 | |
a12c4967 VS |
8406 | /* |
8407 | * BSpec recommends 8x4 when MSAA is used, | |
8408 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
8409 | * |
8410 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8411 | * disable bit, which we don't touch here, but it's good | |
8412 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
8413 | */ |
8414 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 8415 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a12c4967 | 8416 | |
94411593 KG |
8417 | /* WaSampleCChickenBitEnable:hsw */ |
8418 | I915_WRITE(HALF_SLICE_CHICKEN3, | |
8419 | _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE)); | |
8420 | ||
ecdb4eb7 | 8421 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
8422 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
8423 | ||
90a88643 PZ |
8424 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
8425 | I915_WRITE(CHICKEN_PAR1_1, | |
8426 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 8427 | |
46f16e63 | 8428 | lpt_init_clock_gating(dev_priv); |
cad2a2d7 ED |
8429 | } |
8430 | ||
46f16e63 | 8431 | static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8432 | { |
20848223 | 8433 | uint32_t snpcr; |
6f1d69b0 | 8434 | |
46f16e63 | 8435 | ilk_init_lp_watermarks(dev_priv); |
6f1d69b0 | 8436 | |
231e54f6 | 8437 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 8438 | |
ecdb4eb7 | 8439 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
8440 | I915_WRITE(_3D_CHICKEN3, |
8441 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
8442 | ||
ecdb4eb7 | 8443 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
8444 | I915_WRITE(IVB_CHICKEN3, |
8445 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8446 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8447 | ||
ecdb4eb7 | 8448 | /* WaDisablePSDDualDispatchEnable:ivb */ |
50a0bc90 | 8449 | if (IS_IVB_GT1(dev_priv)) |
12f3382b JB |
8450 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
8451 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 8452 | |
4e04632e AG |
8453 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
8454 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8455 | ||
ecdb4eb7 | 8456 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
8457 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
8458 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
8459 | ||
ecdb4eb7 | 8460 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
8461 | I915_WRITE(GEN7_L3CNTLREG1, |
8462 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
8463 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 | 8464 | GEN7_WA_L3_CHICKEN_MODE); |
50a0bc90 | 8465 | if (IS_IVB_GT1(dev_priv)) |
8ab43976 JB |
8466 | I915_WRITE(GEN7_ROW_CHICKEN2, |
8467 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
8468 | else { |
8469 | /* must write both registers */ | |
8470 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
8471 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
8472 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
8473 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 8474 | } |
6f1d69b0 | 8475 | |
ecdb4eb7 | 8476 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
8477 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
8478 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
8479 | ||
1b80a19a | 8480 | /* |
0f846f81 | 8481 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 8482 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
8483 | */ |
8484 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 8485 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 8486 | |
ecdb4eb7 | 8487 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
8488 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8489 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8490 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8491 | ||
46f16e63 | 8492 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
8493 | |
8494 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 8495 | |
22721343 CW |
8496 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
8497 | /* enable HiZ Raw Stall Optimization */ | |
8498 | I915_WRITE(CACHE_MODE_0_GEN7, | |
8499 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
8500 | } | |
116f2b6d | 8501 | |
ecdb4eb7 | 8502 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
8503 | I915_WRITE(CACHE_MODE_1, |
8504 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 8505 | |
a607c1a4 VS |
8506 | /* |
8507 | * BSpec recommends 8x4 when MSAA is used, | |
8508 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
8509 | * |
8510 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8511 | * disable bit, which we don't touch here, but it's good | |
8512 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
8513 | */ |
8514 | I915_WRITE(GEN7_GT_MODE, | |
98533251 | 8515 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); |
a607c1a4 | 8516 | |
20848223 BW |
8517 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
8518 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
8519 | snpcr |= GEN6_MBC_SNPCR_MED; | |
8520 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 8521 | |
6e266956 | 8522 | if (!HAS_PCH_NOP(dev_priv)) |
46f16e63 | 8523 | cpt_init_clock_gating(dev_priv); |
1d7aaa0c | 8524 | |
46f16e63 | 8525 | gen6_check_mch_setup(dev_priv); |
6f1d69b0 ED |
8526 | } |
8527 | ||
46f16e63 | 8528 | static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8529 | { |
ecdb4eb7 | 8530 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
8531 | I915_WRITE(_3D_CHICKEN3, |
8532 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
8533 | ||
ecdb4eb7 | 8534 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
8535 | I915_WRITE(IVB_CHICKEN3, |
8536 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
8537 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
8538 | ||
fad7d36e | 8539 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 8540 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 8541 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
8542 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
8543 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 8544 | |
4e04632e AG |
8545 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
8546 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8547 | ||
ecdb4eb7 | 8548 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
8549 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
8550 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
8551 | ||
ecdb4eb7 | 8552 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
8553 | I915_WRITE(GEN7_ROW_CHICKEN2, |
8554 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8555 | ||
ecdb4eb7 | 8556 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
8557 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
8558 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
8559 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
8560 | ||
46680e0a VS |
8561 | gen7_setup_fixed_func_scheduler(dev_priv); |
8562 | ||
3c0edaeb | 8563 | /* |
0f846f81 | 8564 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 8565 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
8566 | */ |
8567 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 8568 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 8569 | |
c98f5062 AG |
8570 | /* WaDisableL3Bank2xClockGate:vlv |
8571 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
8572 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
8573 | I915_WRITE(GEN7_UCGCTL4, | |
8574 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 8575 | |
afd58e79 VS |
8576 | /* |
8577 | * BSpec says this must be set, even though | |
8578 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
8579 | */ | |
6b26c86d DV |
8580 | I915_WRITE(CACHE_MODE_1, |
8581 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 8582 | |
da2518f9 VS |
8583 | /* |
8584 | * BSpec recommends 8x4 when MSAA is used, | |
8585 | * however in practice 16x4 seems fastest. | |
8586 | * | |
8587 | * Note that PS/WM thread counts depend on the WIZ hashing | |
8588 | * disable bit, which we don't touch here, but it's good | |
8589 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8590 | */ | |
8591 | I915_WRITE(GEN7_GT_MODE, | |
8592 | _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4)); | |
8593 | ||
031994ee VS |
8594 | /* |
8595 | * WaIncreaseL3CreditsForVLVB0:vlv | |
8596 | * This is the hardware default actually. | |
8597 | */ | |
8598 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
8599 | ||
2d809570 | 8600 | /* |
ecdb4eb7 | 8601 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
8602 | * Disable clock gating on th GCFG unit to prevent a delay |
8603 | * in the reporting of vblank events. | |
8604 | */ | |
7a0d1eed | 8605 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
8606 | } |
8607 | ||
46f16e63 | 8608 | static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv) |
a4565da8 | 8609 | { |
232ce337 VS |
8610 | /* WaVSRefCountFullforceMissDisable:chv */ |
8611 | /* WaDSRefCountFullforceMissDisable:chv */ | |
8612 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
8613 | I915_READ(GEN7_FF_THREAD_MODE) & | |
8614 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
8615 | |
8616 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
8617 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
8618 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
8619 | |
8620 | /* WaDisableCSUnitClockGating:chv */ | |
8621 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
8622 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
8623 | |
8624 | /* WaDisableSDEUnitClockGating:chv */ | |
8625 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
8626 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
6d50b065 | 8627 | |
450174fe ID |
8628 | /* |
8629 | * WaProgramL3SqcReg1Default:chv | |
8630 | * See gfxspecs/Related Documents/Performance Guide/ | |
8631 | * LSQC Setting Recommendations. | |
8632 | */ | |
8633 | gen8_set_l3sqc_credits(dev_priv, 38, 2); | |
8634 | ||
6d50b065 VS |
8635 | /* |
8636 | * GTT cache may not work with big pages, so if those | |
8637 | * are ever enabled GTT cache may need to be disabled. | |
8638 | */ | |
8639 | I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL); | |
a4565da8 VS |
8640 | } |
8641 | ||
46f16e63 | 8642 | static void g4x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8643 | { |
6f1d69b0 ED |
8644 | uint32_t dspclk_gate; |
8645 | ||
8646 | I915_WRITE(RENCLK_GATE_D1, 0); | |
8647 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
8648 | GS_UNIT_CLOCK_GATE_DISABLE | | |
8649 | CL_UNIT_CLOCK_GATE_DISABLE); | |
8650 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8651 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
8652 | OVRUNIT_CLOCK_GATE_DISABLE | | |
8653 | OVCUNIT_CLOCK_GATE_DISABLE; | |
50a0bc90 | 8654 | if (IS_GM45(dev_priv)) |
6f1d69b0 ED |
8655 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; |
8656 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
8657 | |
8658 | /* WaDisableRenderCachePipelinedFlush */ | |
8659 | I915_WRITE(CACHE_MODE_0, | |
8660 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 8661 | |
4e04632e AG |
8662 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
8663 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
8664 | ||
46f16e63 | 8665 | g4x_disable_trickle_feed(dev_priv); |
6f1d69b0 ED |
8666 | } |
8667 | ||
46f16e63 | 8668 | static void crestline_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8669 | { |
6f1d69b0 ED |
8670 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); |
8671 | I915_WRITE(RENCLK_GATE_D2, 0); | |
8672 | I915_WRITE(DSPCLK_GATE_D, 0); | |
8673 | I915_WRITE(RAMCLK_GATE_D, 0); | |
8674 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
8675 | I915_WRITE(MI_ARB_STATE, |
8676 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
8677 | |
8678 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
8679 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
8680 | } |
8681 | ||
46f16e63 | 8682 | static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8683 | { |
6f1d69b0 ED |
8684 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | |
8685 | I965_RCC_CLOCK_GATE_DISABLE | | |
8686 | I965_RCPB_CLOCK_GATE_DISABLE | | |
8687 | I965_ISC_CLOCK_GATE_DISABLE | | |
8688 | I965_FBC_CLOCK_GATE_DISABLE); | |
8689 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
8690 | I915_WRITE(MI_ARB_STATE, |
8691 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
8692 | |
8693 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
8694 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
8695 | } |
8696 | ||
46f16e63 | 8697 | static void gen3_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8698 | { |
6f1d69b0 ED |
8699 | u32 dstate = I915_READ(D_STATE); |
8700 | ||
8701 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
8702 | DSTATE_DOT_CLOCK_GATING; | |
8703 | I915_WRITE(D_STATE, dstate); | |
13a86b85 | 8704 | |
9b1e14f4 | 8705 | if (IS_PINEVIEW(dev_priv)) |
13a86b85 | 8706 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); |
974a3b0f DV |
8707 | |
8708 | /* IIR "flip pending" means done if this bit is set */ | |
8709 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
8710 | |
8711 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 8712 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
8713 | |
8714 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
8715 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
8716 | |
8717 | I915_WRITE(MI_ARB_STATE, | |
8718 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8719 | } |
8720 | ||
46f16e63 | 8721 | static void i85x_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8722 | { |
6f1d69b0 | 8723 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); |
54e472ae VS |
8724 | |
8725 | /* interrupts should cause a wake up from C3 */ | |
8726 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
8727 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
8728 | |
8729 | I915_WRITE(MEM_MODE, | |
8730 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8731 | } |
8732 | ||
46f16e63 | 8733 | static void i830_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8734 | { |
1038392b VS |
8735 | I915_WRITE(MEM_MODE, |
8736 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
8737 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
8738 | } |
8739 | ||
46f16e63 | 8740 | void intel_init_clock_gating(struct drm_i915_private *dev_priv) |
6f1d69b0 | 8741 | { |
46f16e63 | 8742 | dev_priv->display.init_clock_gating(dev_priv); |
6f1d69b0 ED |
8743 | } |
8744 | ||
712bf364 | 8745 | void intel_suspend_hw(struct drm_i915_private *dev_priv) |
7d708ee4 | 8746 | { |
712bf364 VS |
8747 | if (HAS_PCH_LPT(dev_priv)) |
8748 | lpt_suspend_hw(dev_priv); | |
7d708ee4 ID |
8749 | } |
8750 | ||
46f16e63 | 8751 | static void nop_init_clock_gating(struct drm_i915_private *dev_priv) |
bb400da9 ID |
8752 | { |
8753 | DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n"); | |
8754 | } | |
8755 | ||
8756 | /** | |
8757 | * intel_init_clock_gating_hooks - setup the clock gating hooks | |
8758 | * @dev_priv: device private | |
8759 | * | |
8760 | * Setup the hooks that configure which clocks of a given platform can be | |
8761 | * gated and also apply various GT and display specific workarounds for these | |
8762 | * platforms. Note that some GT specific workarounds are applied separately | |
8763 | * when GPU contexts or batchbuffers start their execution. | |
8764 | */ | |
8765 | void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv) | |
8766 | { | |
90007bca RV |
8767 | if (IS_CANNONLAKE(dev_priv)) |
8768 | dev_priv->display.init_clock_gating = cannonlake_init_clock_gating; | |
8769 | else if (IS_SKYLAKE(dev_priv)) | |
dc00b6a0 | 8770 | dev_priv->display.init_clock_gating = skylake_init_clock_gating; |
82525c17 | 8771 | else if (IS_KABYLAKE(dev_priv) || IS_COFFEELAKE(dev_priv)) |
9498dba7 | 8772 | dev_priv->display.init_clock_gating = kabylake_init_clock_gating; |
9fb5026f | 8773 | else if (IS_BROXTON(dev_priv)) |
bb400da9 | 8774 | dev_priv->display.init_clock_gating = bxt_init_clock_gating; |
9fb5026f ACO |
8775 | else if (IS_GEMINILAKE(dev_priv)) |
8776 | dev_priv->display.init_clock_gating = glk_init_clock_gating; | |
bb400da9 ID |
8777 | else if (IS_BROADWELL(dev_priv)) |
8778 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; | |
8779 | else if (IS_CHERRYVIEW(dev_priv)) | |
8780 | dev_priv->display.init_clock_gating = cherryview_init_clock_gating; | |
8781 | else if (IS_HASWELL(dev_priv)) | |
8782 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; | |
8783 | else if (IS_IVYBRIDGE(dev_priv)) | |
8784 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; | |
8785 | else if (IS_VALLEYVIEW(dev_priv)) | |
8786 | dev_priv->display.init_clock_gating = valleyview_init_clock_gating; | |
8787 | else if (IS_GEN6(dev_priv)) | |
8788 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; | |
8789 | else if (IS_GEN5(dev_priv)) | |
8790 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; | |
8791 | else if (IS_G4X(dev_priv)) | |
8792 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
c0f86832 | 8793 | else if (IS_I965GM(dev_priv)) |
bb400da9 | 8794 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; |
c0f86832 | 8795 | else if (IS_I965G(dev_priv)) |
bb400da9 ID |
8796 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; |
8797 | else if (IS_GEN3(dev_priv)) | |
8798 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
8799 | else if (IS_I85X(dev_priv) || IS_I865G(dev_priv)) | |
8800 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
8801 | else if (IS_GEN2(dev_priv)) | |
8802 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
8803 | else { | |
8804 | MISSING_CASE(INTEL_DEVID(dev_priv)); | |
8805 | dev_priv->display.init_clock_gating = nop_init_clock_gating; | |
8806 | } | |
8807 | } | |
8808 | ||
1fa61106 | 8809 | /* Set up chip specific power management-related functions */ |
62d75df7 | 8810 | void intel_init_pm(struct drm_i915_private *dev_priv) |
1fa61106 | 8811 | { |
7ff0ebcc | 8812 | intel_fbc_init(dev_priv); |
1fa61106 | 8813 | |
c921aba8 | 8814 | /* For cxsr */ |
9b1e14f4 | 8815 | if (IS_PINEVIEW(dev_priv)) |
148ac1f3 | 8816 | i915_pineview_get_mem_freq(dev_priv); |
5db94019 | 8817 | else if (IS_GEN5(dev_priv)) |
148ac1f3 | 8818 | i915_ironlake_get_mem_freq(dev_priv); |
c921aba8 | 8819 | |
1fa61106 | 8820 | /* For FIFO watermark updates */ |
62d75df7 | 8821 | if (INTEL_GEN(dev_priv) >= 9) { |
bb726519 | 8822 | skl_setup_wm_latency(dev_priv); |
e62929b3 | 8823 | dev_priv->display.initial_watermarks = skl_initial_wm; |
ccf010fb | 8824 | dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm; |
98d39494 | 8825 | dev_priv->display.compute_global_watermarks = skl_compute_wm; |
6e266956 | 8826 | } else if (HAS_PCH_SPLIT(dev_priv)) { |
bb726519 | 8827 | ilk_setup_wm_latency(dev_priv); |
53615a5e | 8828 | |
5db94019 | 8829 | if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] && |
bd602544 | 8830 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || |
5db94019 | 8831 | (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] && |
bd602544 | 8832 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { |
86c8bbbe | 8833 | dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm; |
ed4a6a7c MR |
8834 | dev_priv->display.compute_intermediate_wm = |
8835 | ilk_compute_intermediate_wm; | |
8836 | dev_priv->display.initial_watermarks = | |
8837 | ilk_initial_watermarks; | |
8838 | dev_priv->display.optimize_watermarks = | |
8839 | ilk_optimize_watermarks; | |
bd602544 VS |
8840 | } else { |
8841 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
8842 | "Disable CxSR\n"); | |
8843 | } | |
6b6b3eef | 8844 | } else if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { |
bb726519 | 8845 | vlv_setup_wm_latency(dev_priv); |
ff32c54e | 8846 | dev_priv->display.compute_pipe_wm = vlv_compute_pipe_wm; |
4841da51 | 8847 | dev_priv->display.compute_intermediate_wm = vlv_compute_intermediate_wm; |
ff32c54e | 8848 | dev_priv->display.initial_watermarks = vlv_initial_watermarks; |
4841da51 | 8849 | dev_priv->display.optimize_watermarks = vlv_optimize_watermarks; |
ff32c54e | 8850 | dev_priv->display.atomic_update_watermarks = vlv_atomic_update_fifo; |
04548cba VS |
8851 | } else if (IS_G4X(dev_priv)) { |
8852 | g4x_setup_wm_latency(dev_priv); | |
8853 | dev_priv->display.compute_pipe_wm = g4x_compute_pipe_wm; | |
8854 | dev_priv->display.compute_intermediate_wm = g4x_compute_intermediate_wm; | |
8855 | dev_priv->display.initial_watermarks = g4x_initial_watermarks; | |
8856 | dev_priv->display.optimize_watermarks = g4x_optimize_watermarks; | |
9b1e14f4 | 8857 | } else if (IS_PINEVIEW(dev_priv)) { |
50a0bc90 | 8858 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv), |
1fa61106 ED |
8859 | dev_priv->is_ddr3, |
8860 | dev_priv->fsb_freq, | |
8861 | dev_priv->mem_freq)) { | |
8862 | DRM_INFO("failed to find known CxSR latency " | |
8863 | "(found ddr%s fsb freq %d, mem freq %d), " | |
8864 | "disabling CxSR\n", | |
8865 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
8866 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
8867 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 8868 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
8869 | dev_priv->display.update_wm = NULL; |
8870 | } else | |
8871 | dev_priv->display.update_wm = pineview_update_wm; | |
5db94019 | 8872 | } else if (IS_GEN4(dev_priv)) { |
1fa61106 | 8873 | dev_priv->display.update_wm = i965_update_wm; |
5db94019 | 8874 | } else if (IS_GEN3(dev_priv)) { |
1fa61106 ED |
8875 | dev_priv->display.update_wm = i9xx_update_wm; |
8876 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
5db94019 | 8877 | } else if (IS_GEN2(dev_priv)) { |
62d75df7 | 8878 | if (INTEL_INFO(dev_priv)->num_pipes == 1) { |
feb56b93 | 8879 | dev_priv->display.update_wm = i845_update_wm; |
1fa61106 | 8880 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
8881 | } else { |
8882 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 8883 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 | 8884 | } |
feb56b93 DV |
8885 | } else { |
8886 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
8887 | } |
8888 | } | |
8889 | ||
87660502 L |
8890 | static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv) |
8891 | { | |
8892 | uint32_t flags = | |
8893 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8894 | ||
8895 | switch (flags) { | |
8896 | case GEN6_PCODE_SUCCESS: | |
8897 | return 0; | |
8898 | case GEN6_PCODE_UNIMPLEMENTED_CMD: | |
5a9cfff4 | 8899 | return -ENODEV; |
87660502 L |
8900 | case GEN6_PCODE_ILLEGAL_CMD: |
8901 | return -ENXIO; | |
8902 | case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
7850d1c3 | 8903 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: |
87660502 L |
8904 | return -EOVERFLOW; |
8905 | case GEN6_PCODE_TIMEOUT: | |
8906 | return -ETIMEDOUT; | |
8907 | default: | |
f0d66153 | 8908 | MISSING_CASE(flags); |
87660502 L |
8909 | return 0; |
8910 | } | |
8911 | } | |
8912 | ||
8913 | static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv) | |
8914 | { | |
8915 | uint32_t flags = | |
8916 | I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK; | |
8917 | ||
8918 | switch (flags) { | |
8919 | case GEN6_PCODE_SUCCESS: | |
8920 | return 0; | |
8921 | case GEN6_PCODE_ILLEGAL_CMD: | |
8922 | return -ENXIO; | |
8923 | case GEN7_PCODE_TIMEOUT: | |
8924 | return -ETIMEDOUT; | |
8925 | case GEN7_PCODE_ILLEGAL_DATA: | |
8926 | return -EINVAL; | |
8927 | case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE: | |
8928 | return -EOVERFLOW; | |
8929 | default: | |
8930 | MISSING_CASE(flags); | |
8931 | return 0; | |
8932 | } | |
8933 | } | |
8934 | ||
151a49d0 | 8935 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val) |
42c0526c | 8936 | { |
87660502 L |
8937 | int status; |
8938 | ||
4fc688ce | 8939 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8940 | |
3f5582dd CW |
8941 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8942 | * use te fw I915_READ variants to reduce the amount of work | |
8943 | * required when reading/writing. | |
8944 | */ | |
8945 | ||
8946 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
5a9cfff4 CW |
8947 | DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps\n", |
8948 | mbox, __builtin_return_address(0)); | |
42c0526c BW |
8949 | return -EAGAIN; |
8950 | } | |
8951 | ||
3f5582dd CW |
8952 | I915_WRITE_FW(GEN6_PCODE_DATA, *val); |
8953 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); | |
8954 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
42c0526c | 8955 | |
e09a3036 CW |
8956 | if (__intel_wait_for_register_fw(dev_priv, |
8957 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
8958 | 500, 0, NULL)) { | |
5a9cfff4 CW |
8959 | DRM_ERROR("timeout waiting for pcode read (from mbox %x) to finish for %ps\n", |
8960 | mbox, __builtin_return_address(0)); | |
42c0526c BW |
8961 | return -ETIMEDOUT; |
8962 | } | |
8963 | ||
3f5582dd CW |
8964 | *val = I915_READ_FW(GEN6_PCODE_DATA); |
8965 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); | |
42c0526c | 8966 | |
87660502 L |
8967 | if (INTEL_GEN(dev_priv) > 6) |
8968 | status = gen7_check_mailbox_status(dev_priv); | |
8969 | else | |
8970 | status = gen6_check_mailbox_status(dev_priv); | |
8971 | ||
8972 | if (status) { | |
5a9cfff4 CW |
8973 | DRM_DEBUG_DRIVER("warning: pcode (read from mbox %x) mailbox access failed for %ps: %d\n", |
8974 | mbox, __builtin_return_address(0), status); | |
87660502 L |
8975 | return status; |
8976 | } | |
8977 | ||
42c0526c BW |
8978 | return 0; |
8979 | } | |
8980 | ||
3f5582dd | 8981 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, |
87660502 | 8982 | u32 mbox, u32 val) |
42c0526c | 8983 | { |
87660502 L |
8984 | int status; |
8985 | ||
4fc688ce | 8986 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c | 8987 | |
3f5582dd CW |
8988 | /* GEN6_PCODE_* are outside of the forcewake domain, we can |
8989 | * use te fw I915_READ variants to reduce the amount of work | |
8990 | * required when reading/writing. | |
8991 | */ | |
8992 | ||
8993 | if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
5a9cfff4 CW |
8994 | DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps\n", |
8995 | val, mbox, __builtin_return_address(0)); | |
42c0526c BW |
8996 | return -EAGAIN; |
8997 | } | |
8998 | ||
3f5582dd | 8999 | I915_WRITE_FW(GEN6_PCODE_DATA, val); |
8bf41b72 | 9000 | I915_WRITE_FW(GEN6_PCODE_DATA1, 0); |
3f5582dd | 9001 | I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
42c0526c | 9002 | |
e09a3036 CW |
9003 | if (__intel_wait_for_register_fw(dev_priv, |
9004 | GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0, | |
9005 | 500, 0, NULL)) { | |
5a9cfff4 CW |
9006 | DRM_ERROR("timeout waiting for pcode write of 0x%08x to mbox %x to finish for %ps\n", |
9007 | val, mbox, __builtin_return_address(0)); | |
42c0526c BW |
9008 | return -ETIMEDOUT; |
9009 | } | |
9010 | ||
3f5582dd | 9011 | I915_WRITE_FW(GEN6_PCODE_DATA, 0); |
42c0526c | 9012 | |
87660502 L |
9013 | if (INTEL_GEN(dev_priv) > 6) |
9014 | status = gen7_check_mailbox_status(dev_priv); | |
9015 | else | |
9016 | status = gen6_check_mailbox_status(dev_priv); | |
9017 | ||
9018 | if (status) { | |
5a9cfff4 CW |
9019 | DRM_DEBUG_DRIVER("warning: pcode (write of 0x%08x to mbox %x) mailbox access failed for %ps: %d\n", |
9020 | val, mbox, __builtin_return_address(0), status); | |
87660502 L |
9021 | return status; |
9022 | } | |
9023 | ||
42c0526c BW |
9024 | return 0; |
9025 | } | |
a0e4e199 | 9026 | |
a0b8a1fe ID |
9027 | static bool skl_pcode_try_request(struct drm_i915_private *dev_priv, u32 mbox, |
9028 | u32 request, u32 reply_mask, u32 reply, | |
9029 | u32 *status) | |
9030 | { | |
9031 | u32 val = request; | |
9032 | ||
9033 | *status = sandybridge_pcode_read(dev_priv, mbox, &val); | |
9034 | ||
9035 | return *status || ((val & reply_mask) == reply); | |
9036 | } | |
9037 | ||
9038 | /** | |
9039 | * skl_pcode_request - send PCODE request until acknowledgment | |
9040 | * @dev_priv: device private | |
9041 | * @mbox: PCODE mailbox ID the request is targeted for | |
9042 | * @request: request ID | |
9043 | * @reply_mask: mask used to check for request acknowledgment | |
9044 | * @reply: value used to check for request acknowledgment | |
9045 | * @timeout_base_ms: timeout for polling with preemption enabled | |
9046 | * | |
9047 | * Keep resending the @request to @mbox until PCODE acknowledges it, PCODE | |
0129936d | 9048 | * reports an error or an overall timeout of @timeout_base_ms+50 ms expires. |
a0b8a1fe ID |
9049 | * The request is acknowledged once the PCODE reply dword equals @reply after |
9050 | * applying @reply_mask. Polling is first attempted with preemption enabled | |
0129936d | 9051 | * for @timeout_base_ms and if this times out for another 50 ms with |
a0b8a1fe ID |
9052 | * preemption disabled. |
9053 | * | |
9054 | * Returns 0 on success, %-ETIMEDOUT in case of a timeout, <0 in case of some | |
9055 | * other error as reported by PCODE. | |
9056 | */ | |
9057 | int skl_pcode_request(struct drm_i915_private *dev_priv, u32 mbox, u32 request, | |
9058 | u32 reply_mask, u32 reply, int timeout_base_ms) | |
9059 | { | |
9060 | u32 status; | |
9061 | int ret; | |
9062 | ||
9063 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
9064 | ||
9065 | #define COND skl_pcode_try_request(dev_priv, mbox, request, reply_mask, reply, \ | |
9066 | &status) | |
9067 | ||
9068 | /* | |
9069 | * Prime the PCODE by doing a request first. Normally it guarantees | |
9070 | * that a subsequent request, at most @timeout_base_ms later, succeeds. | |
9071 | * _wait_for() doesn't guarantee when its passed condition is evaluated | |
9072 | * first, so send the first request explicitly. | |
9073 | */ | |
9074 | if (COND) { | |
9075 | ret = 0; | |
9076 | goto out; | |
9077 | } | |
9078 | ret = _wait_for(COND, timeout_base_ms * 1000, 10); | |
9079 | if (!ret) | |
9080 | goto out; | |
9081 | ||
9082 | /* | |
9083 | * The above can time out if the number of requests was low (2 in the | |
9084 | * worst case) _and_ PCODE was busy for some reason even after a | |
9085 | * (queued) request and @timeout_base_ms delay. As a workaround retry | |
9086 | * the poll with preemption disabled to maximize the number of | |
0129936d | 9087 | * requests. Increase the timeout from @timeout_base_ms to 50ms to |
a0b8a1fe | 9088 | * account for interrupts that could reduce the number of these |
0129936d ID |
9089 | * requests, and for any quirks of the PCODE firmware that delays |
9090 | * the request completion. | |
a0b8a1fe ID |
9091 | */ |
9092 | DRM_DEBUG_KMS("PCODE timeout, retrying with preemption disabled\n"); | |
9093 | WARN_ON_ONCE(timeout_base_ms > 3); | |
9094 | preempt_disable(); | |
0129936d | 9095 | ret = wait_for_atomic(COND, 50); |
a0b8a1fe ID |
9096 | preempt_enable(); |
9097 | ||
9098 | out: | |
9099 | return ret ? ret : status; | |
9100 | #undef COND | |
9101 | } | |
9102 | ||
dd06f88c VS |
9103 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
9104 | { | |
c30fec65 VS |
9105 | /* |
9106 | * N = val - 0xb7 | |
9107 | * Slow = Fast = GPLL ref * N | |
9108 | */ | |
9109 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000); | |
855ba3be JB |
9110 | } |
9111 | ||
b55dd647 | 9112 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 9113 | { |
c30fec65 | 9114 | return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7; |
855ba3be JB |
9115 | } |
9116 | ||
b55dd647 | 9117 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 9118 | { |
c30fec65 VS |
9119 | /* |
9120 | * N = val / 2 | |
9121 | * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2 | |
9122 | */ | |
9123 | return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000); | |
22b1b2f8 D |
9124 | } |
9125 | ||
b55dd647 | 9126 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 9127 | { |
1c14762d | 9128 | /* CHV needs even values */ |
c30fec65 | 9129 | return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2; |
22b1b2f8 D |
9130 | } |
9131 | ||
616bc820 | 9132 | int intel_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 | 9133 | { |
35ceabf3 | 9134 | if (INTEL_GEN(dev_priv) >= 9) |
500a3d2e MK |
9135 | return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER, |
9136 | GEN9_FREQ_SCALER); | |
2d1fe073 | 9137 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 9138 | return chv_gpu_freq(dev_priv, val); |
2d1fe073 | 9139 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
9140 | return byt_gpu_freq(dev_priv, val); |
9141 | else | |
9142 | return val * GT_FREQUENCY_MULTIPLIER; | |
22b1b2f8 D |
9143 | } |
9144 | ||
616bc820 VS |
9145 | int intel_freq_opcode(struct drm_i915_private *dev_priv, int val) |
9146 | { | |
35ceabf3 | 9147 | if (INTEL_GEN(dev_priv) >= 9) |
500a3d2e MK |
9148 | return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER, |
9149 | GT_FREQUENCY_MULTIPLIER); | |
2d1fe073 | 9150 | else if (IS_CHERRYVIEW(dev_priv)) |
616bc820 | 9151 | return chv_freq_opcode(dev_priv, val); |
2d1fe073 | 9152 | else if (IS_VALLEYVIEW(dev_priv)) |
616bc820 VS |
9153 | return byt_freq_opcode(dev_priv, val); |
9154 | else | |
500a3d2e | 9155 | return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER); |
616bc820 | 9156 | } |
22b1b2f8 | 9157 | |
6ad790c0 CW |
9158 | struct request_boost { |
9159 | struct work_struct work; | |
eed29a5b | 9160 | struct drm_i915_gem_request *req; |
6ad790c0 CW |
9161 | }; |
9162 | ||
9163 | static void __intel_rps_boost_work(struct work_struct *work) | |
9164 | { | |
9165 | struct request_boost *boost = container_of(work, struct request_boost, work); | |
e61b9958 | 9166 | struct drm_i915_gem_request *req = boost->req; |
6ad790c0 | 9167 | |
f69a02c9 | 9168 | if (!i915_gem_request_completed(req)) |
7b92c1bd | 9169 | gen6_rps_boost(req, NULL); |
6ad790c0 | 9170 | |
e8a261ea | 9171 | i915_gem_request_put(req); |
6ad790c0 CW |
9172 | kfree(boost); |
9173 | } | |
9174 | ||
91d14251 | 9175 | void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req) |
6ad790c0 CW |
9176 | { |
9177 | struct request_boost *boost; | |
9178 | ||
91d14251 | 9179 | if (req == NULL || INTEL_GEN(req->i915) < 6) |
6ad790c0 CW |
9180 | return; |
9181 | ||
f69a02c9 | 9182 | if (i915_gem_request_completed(req)) |
e61b9958 CW |
9183 | return; |
9184 | ||
6ad790c0 CW |
9185 | boost = kmalloc(sizeof(*boost), GFP_ATOMIC); |
9186 | if (boost == NULL) | |
9187 | return; | |
9188 | ||
e8a261ea | 9189 | boost->req = i915_gem_request_get(req); |
6ad790c0 CW |
9190 | |
9191 | INIT_WORK(&boost->work, __intel_rps_boost_work); | |
91d14251 | 9192 | queue_work(req->i915->wq, &boost->work); |
6ad790c0 CW |
9193 | } |
9194 | ||
192aa181 | 9195 | void intel_pm_setup(struct drm_i915_private *dev_priv) |
907b28c5 | 9196 | { |
f742a552 DV |
9197 | mutex_init(&dev_priv->rps.hw_lock); |
9198 | ||
54b4f68f CW |
9199 | INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work, |
9200 | __intel_autoenable_gt_powersave); | |
7b92c1bd | 9201 | atomic_set(&dev_priv->rps.num_waiters, 0); |
5d584b2e | 9202 | |
33688d95 | 9203 | dev_priv->pm.suspended = false; |
1f814dac | 9204 | atomic_set(&dev_priv->pm.wakeref_count, 0); |
907b28c5 | 9205 | } |
135bafa5 | 9206 | |
47c21d9a MK |
9207 | static u64 vlv_residency_raw(struct drm_i915_private *dev_priv, |
9208 | const i915_reg_t reg) | |
9209 | { | |
facbecad | 9210 | u32 lower, upper, tmp; |
71cc2b18 | 9211 | int loop = 2; |
47c21d9a MK |
9212 | |
9213 | /* The register accessed do not need forcewake. We borrow | |
9214 | * uncore lock to prevent concurrent access to range reg. | |
9215 | */ | |
9216 | spin_lock_irq(&dev_priv->uncore.lock); | |
47c21d9a MK |
9217 | |
9218 | /* vlv and chv residency counters are 40 bits in width. | |
9219 | * With a control bit, we can choose between upper or lower | |
9220 | * 32bit window into this counter. | |
facbecad CW |
9221 | * |
9222 | * Although we always use the counter in high-range mode elsewhere, | |
9223 | * userspace may attempt to read the value before rc6 is initialised, | |
9224 | * before we have set the default VLV_COUNTER_CONTROL value. So always | |
9225 | * set the high bit to be safe. | |
47c21d9a | 9226 | */ |
facbecad CW |
9227 | I915_WRITE_FW(VLV_COUNTER_CONTROL, |
9228 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
47c21d9a MK |
9229 | upper = I915_READ_FW(reg); |
9230 | do { | |
9231 | tmp = upper; | |
9232 | ||
9233 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
9234 | _MASKED_BIT_DISABLE(VLV_COUNT_RANGE_HIGH)); | |
9235 | lower = I915_READ_FW(reg); | |
9236 | ||
9237 | I915_WRITE_FW(VLV_COUNTER_CONTROL, | |
9238 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH)); | |
9239 | upper = I915_READ_FW(reg); | |
71cc2b18 | 9240 | } while (upper != tmp && --loop); |
47c21d9a | 9241 | |
facbecad CW |
9242 | /* Everywhere else we always use VLV_COUNTER_CONTROL with the |
9243 | * VLV_COUNT_RANGE_HIGH bit set - so it is safe to leave it set | |
9244 | * now. | |
9245 | */ | |
9246 | ||
47c21d9a MK |
9247 | spin_unlock_irq(&dev_priv->uncore.lock); |
9248 | ||
9249 | return lower | (u64)upper << 8; | |
9250 | } | |
9251 | ||
c5a0ad11 MK |
9252 | u64 intel_rc6_residency_us(struct drm_i915_private *dev_priv, |
9253 | const i915_reg_t reg) | |
135bafa5 | 9254 | { |
47c21d9a | 9255 | u64 time_hw, units, div; |
135bafa5 MK |
9256 | |
9257 | if (!intel_enable_rc6()) | |
9258 | return 0; | |
9259 | ||
9260 | intel_runtime_pm_get(dev_priv); | |
9261 | ||
9262 | /* On VLV and CHV, residency time is in CZ units rather than 1.28us */ | |
9263 | if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) { | |
c5a0ad11 | 9264 | units = 1000; |
135bafa5 MK |
9265 | div = dev_priv->czclk_freq; |
9266 | ||
47c21d9a | 9267 | time_hw = vlv_residency_raw(dev_priv, reg); |
135bafa5 | 9268 | } else if (IS_GEN9_LP(dev_priv)) { |
c5a0ad11 | 9269 | units = 1000; |
135bafa5 | 9270 | div = 1200; /* 833.33ns */ |
135bafa5 | 9271 | |
47c21d9a MK |
9272 | time_hw = I915_READ(reg); |
9273 | } else { | |
9274 | units = 128000; /* 1.28us */ | |
9275 | div = 100000; | |
9276 | ||
9277 | time_hw = I915_READ(reg); | |
9278 | } | |
135bafa5 MK |
9279 | |
9280 | intel_runtime_pm_put(dev_priv); | |
47c21d9a | 9281 | return DIV_ROUND_UP_ULL(time_hw * units, div); |
135bafa5 | 9282 | } |