]> git.proxmox.com Git - mirror_ubuntu-bionic-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-bionic-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: Invert fastboot check
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
dc39fff7
BW		 34/**
35 * RC6 is a special power stage which allows the GPU to enter an very
36 * low-voltage mode when idle, using down to 0V while at this stage. This
37 * stage is entered automatically when the GPU is idle when RC6 support is
38 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
39 *
40 * There are different RC6 modes available in Intel GPU, which differentiate
41 * among each other with the latency required to enter and leave RC6 and
42 * voltage consumed by the GPU in different states.
43 *
44 * The combination of the following flags define which states GPU is allowed
45 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
46 * RC6pp is deepest RC6. Their support by hardware varies according to the
47 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
48 * which brings the most power savings; deeper states save more power, but
49 * require higher latency to switch to and wake up.
50 */
51#define INTEL_RC6_ENABLE (1<<0)
52#define INTEL_RC6p_ENABLE (1<<1)
53#define INTEL_RC6pp_ENABLE (1<<2)
54
da2078cd
DL		 55static void gen9_init_clock_gating(struct drm_device *dev)
56{
acd5c346
DL		 57 struct drm_i915_private *dev_priv = dev->dev_private;
58
77719d28
DL		 59 /* WaEnableLbsSlaRetryTimerDecrement:skl */
60 I915_WRITE(BDW_SCRATCH1, I915_READ(BDW_SCRATCH1) |
61 GEN9_LBS_SLA_RETRY_TIMER_DECREMENT_ENABLE);
6381b550
NH		 62
63 /* WaDisableKillLogic:bxt,skl */
64 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
65 ECOCHK_DIS_TLB);
77719d28 66}
91e41d16 67
45db2194 68static void skl_init_clock_gating(struct drm_device *dev)
da2078cd 69{
acd5c346 70 struct drm_i915_private *dev_priv = dev->dev_private;
3ca5da43 71
77719d28
DL		 72 gen9_init_clock_gating(dev);
73
669506e7 74 if (INTEL_REVID(dev) <= SKL_REVID_B0) {
3dcd020a
HN		 75 /*
76 * WaDisableSDEUnitClockGating:skl
9253c2e5 77 * WaSetGAPSunitClckGateDisable:skl
3dcd020a
HN		 78 */
79 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
9253c2e5 80 GEN8_GAPSUNIT_CLOCK_GATE_DISABLE |
3dcd020a 81 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
f9fc42f4
DL		 82
83 /* WaDisableVFUnitClockGating:skl */
84 I915_WRITE(GEN6_UCGCTL2, I915_READ(GEN6_UCGCTL2) |
85 GEN6_VFUNIT_CLOCK_GATE_DISABLE);
3dcd020a 86 }
8bc0ccf6 87
2caa3b26 88 if (INTEL_REVID(dev) <= SKL_REVID_D0) {
81e231af
DL		 89 /* WaDisableHDCInvalidation:skl */
90 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) |
91 BDW_DISABLE_HDC_INVALIDATION);
92
2caa3b26
DL		 93 /* WaDisableChickenBitTSGBarrierAckForFFSliceCS:skl */
94 I915_WRITE(FF_SLICE_CS_CHICKEN2,
f1d3d34d 95 _MASKED_BIT_ENABLE(GEN9_TSG_BARRIER_ACK_DISABLE));
2caa3b26 96 }
81e231af 97
a4106a78
AS		 98 /* GEN8_L3SQCREG4 has a dependency with WA batch so any new changes
99 * involving this register should also be added to WA batch as required.
100 */
8bc0ccf6
DL		 101 if (INTEL_REVID(dev) <= SKL_REVID_E0)
102 /* WaDisableLSQCROPERFforOCL:skl */
103 I915_WRITE(GEN8_L3SQCREG4, I915_READ(GEN8_L3SQCREG4) |
104 GEN8_LQSC_RO_PERF_DIS);
da2078cd
DL		 105}
106
a82abe43
ID		 107static void bxt_init_clock_gating(struct drm_device *dev)
108{
32608ca2
ID		 109 struct drm_i915_private *dev_priv = dev->dev_private;
110
a82abe43 111 gen9_init_clock_gating(dev);
32608ca2
ID		 112
113 /*
114 * FIXME:
115 * GEN8_SDEUNIT_CLOCK_GATE_DISABLE applies on A0 only.
868434c5 116 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2
ID		 117 */
118 /* WaDisableSDEUnitClockGating:bxt */
119 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5
BW		 120 GEN8_SDEUNIT_CLOCK_GATE_DISABLE |
121 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
32608ca2 122
e3a29055
RB		 123 /* FIXME: apply on A0 only */
124 I915_WRITE(TILECTL, I915_READ(TILECTL) | TILECTL_TLBPF);
a82abe43
ID		 125}
126
c921aba8
DV		 127static void i915_pineview_get_mem_freq(struct drm_device *dev)
128{
50227e1c 129 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 130 u32 tmp;
131
132 tmp = I915_READ(CLKCFG);
133
134 switch (tmp & CLKCFG_FSB_MASK) {
135 case CLKCFG_FSB_533:
136 dev_priv->fsb_freq = 533; /* 133*4 */
137 break;
138 case CLKCFG_FSB_800:
139 dev_priv->fsb_freq = 800; /* 200*4 */
140 break;
141 case CLKCFG_FSB_667:
142 dev_priv->fsb_freq = 667; /* 167*4 */
143 break;
144 case CLKCFG_FSB_400:
145 dev_priv->fsb_freq = 400; /* 100*4 */
146 break;
147 }
148
149 switch (tmp & CLKCFG_MEM_MASK) {
150 case CLKCFG_MEM_533:
151 dev_priv->mem_freq = 533;
152 break;
153 case CLKCFG_MEM_667:
154 dev_priv->mem_freq = 667;
155 break;
156 case CLKCFG_MEM_800:
157 dev_priv->mem_freq = 800;
158 break;
159 }
160
161 /* detect pineview DDR3 setting */
162 tmp = I915_READ(CSHRDDR3CTL);
163 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
164}
165
166static void i915_ironlake_get_mem_freq(struct drm_device *dev)
167{
50227e1c 168 struct drm_i915_private *dev_priv = dev->dev_private;
c921aba8
DV		 169 u16 ddrpll, csipll;
170
171 ddrpll = I915_READ16(DDRMPLL1);
172 csipll = I915_READ16(CSIPLL0);
173
174 switch (ddrpll & 0xff) {
175 case 0xc:
176 dev_priv->mem_freq = 800;
177 break;
178 case 0x10:
179 dev_priv->mem_freq = 1066;
180 break;
181 case 0x14:
182 dev_priv->mem_freq = 1333;
183 break;
184 case 0x18:
185 dev_priv->mem_freq = 1600;
186 break;
187 default:
188 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
189 ddrpll & 0xff);
190 dev_priv->mem_freq = 0;
191 break;
192 }
193
20e4d407 194 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 195
196 switch (csipll & 0x3ff) {
197 case 0x00c:
198 dev_priv->fsb_freq = 3200;
199 break;
200 case 0x00e:
201 dev_priv->fsb_freq = 3733;
202 break;
203 case 0x010:
204 dev_priv->fsb_freq = 4266;
205 break;
206 case 0x012:
207 dev_priv->fsb_freq = 4800;
208 break;
209 case 0x014:
210 dev_priv->fsb_freq = 5333;
211 break;
212 case 0x016:
213 dev_priv->fsb_freq = 5866;
214 break;
215 case 0x018:
216 dev_priv->fsb_freq = 6400;
217 break;
218 default:
219 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
220 csipll & 0x3ff);
221 dev_priv->fsb_freq = 0;
222 break;
223 }
224
225 if (dev_priv->fsb_freq == 3200) {
20e4d407 226 dev_priv->ips.c_m = 0;
c921aba8 227 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 228 dev_priv->ips.c_m = 1;
c921aba8 229 } else {
20e4d407 230 dev_priv->ips.c_m = 2;
c921aba8
DV		 231 }
232}
233
b445e3b0
ED		 234static const struct cxsr_latency cxsr_latency_table[] = {
235 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
236 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
237 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
238 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
239 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
240
241 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
242 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
243 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
244 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
245 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
246
247 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
248 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
249 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
250 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
251 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
252
253 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
254 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
255 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
256 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
257 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
258
259 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
260 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
261 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
262 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
263 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
264
265 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
266 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
267 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
268 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
269 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
270};
271
63c62275 272static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 273 int is_ddr3,
274 int fsb,
275 int mem)
276{
277 const struct cxsr_latency *latency;
278 int i;
279
280 if (fsb == 0 || mem == 0)
281 return NULL;
282
283 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
284 latency = &cxsr_latency_table[i];
285 if (is_desktop == latency->is_desktop &&
286 is_ddr3 == latency->is_ddr3 &&
287 fsb == latency->fsb_freq && mem == latency->mem_freq)
288 return latency;
289 }
290
291 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
292
293 return NULL;
294}
295
fc1ac8de
VS		 296static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
297{
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
303 if (enable)
304 val &= ~FORCE_DDR_HIGH_FREQ;
305 else
306 val |= FORCE_DDR_HIGH_FREQ;
307 val &= ~FORCE_DDR_LOW_FREQ;
308 val |= FORCE_DDR_FREQ_REQ_ACK;
309 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
310
311 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
312 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
313 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
314
315 mutex_unlock(&dev_priv->rps.hw_lock);
316}
317
cfb41411
VS		 318static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
319{
320 u32 val;
321
322 mutex_lock(&dev_priv->rps.hw_lock);
323
324 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
325 if (enable)
326 val |= DSP_MAXFIFO_PM5_ENABLE;
327 else
328 val &= ~DSP_MAXFIFO_PM5_ENABLE;
329 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
330
331 mutex_unlock(&dev_priv->rps.hw_lock);
332}
333
f4998963
VS		 334#define FW_WM(value, plane) \
335 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
336
5209b1f4 337void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 338{
5209b1f4
ID		 339 struct drm_device *dev = dev_priv->dev;
340 u32 val;
b445e3b0 341
5209b1f4
ID		 342 if (IS_VALLEYVIEW(dev)) {
343 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 344 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 345 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 346 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
347 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 348 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 349 } else if (IS_PINEVIEW(dev)) {
350 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
351 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
352 I915_WRITE(DSPFW3, val);
a7a6c498 353 POSTING_READ(DSPFW3);
5209b1f4
ID		 354 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
355 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
356 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
357 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 358 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 359 } else if (IS_I915GM(dev)) {
360 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
361 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
362 I915_WRITE(INSTPM, val);
a7a6c498 363 POSTING_READ(INSTPM);
5209b1f4
ID		 364 } else {
365 return;
366 }
b445e3b0 367
5209b1f4
ID		 368 DRM_DEBUG_KMS("memory self-refresh is %s\n",
369 enable ? "enabled" : "disabled");
b445e3b0
ED		 370}
371
fc1ac8de 372
b445e3b0
ED		 373/*
374 * Latency for FIFO fetches is dependent on several factors:
375 * - memory configuration (speed, channels)
376 * - chipset
377 * - current MCH state
378 * It can be fairly high in some situations, so here we assume a fairly
379 * pessimal value. It's a tradeoff between extra memory fetches (if we
380 * set this value too high, the FIFO will fetch frequently to stay full)
381 * and power consumption (set it too low to save power and we might see
382 * FIFO underruns and display "flicker").
383 *
384 * A value of 5us seems to be a good balance; safe for very low end
385 * platforms but not overly aggressive on lower latency configs.
386 */
5aef6003 387static const int pessimal_latency_ns = 5000;
b445e3b0 388
b5004720
VS		 389#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
390 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
391
392static int vlv_get_fifo_size(struct drm_device *dev,
393 enum pipe pipe, int plane)
394{
395 struct drm_i915_private *dev_priv = dev->dev_private;
396 int sprite0_start, sprite1_start, size;
397
398 switch (pipe) {
399 uint32_t dsparb, dsparb2, dsparb3;
400 case PIPE_A:
401 dsparb = I915_READ(DSPARB);
402 dsparb2 = I915_READ(DSPARB2);
403 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
404 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
405 break;
406 case PIPE_B:
407 dsparb = I915_READ(DSPARB);
408 dsparb2 = I915_READ(DSPARB2);
409 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
410 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
411 break;
412 case PIPE_C:
413 dsparb2 = I915_READ(DSPARB2);
414 dsparb3 = I915_READ(DSPARB3);
415 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
416 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
417 break;
418 default:
419 return 0;
420 }
421
422 switch (plane) {
423 case 0:
424 size = sprite0_start;
425 break;
426 case 1:
427 size = sprite1_start - sprite0_start;
428 break;
429 case 2:
430 size = 512 - 1 - sprite1_start;
431 break;
432 default:
433 return 0;
434 }
435
436 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
437 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
438 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
439 size);
440
441 return size;
442}
443
1fa61106 444static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 445{
446 struct drm_i915_private *dev_priv = dev->dev_private;
447 uint32_t dsparb = I915_READ(DSPARB);
448 int size;
449
450 size = dsparb & 0x7f;
451 if (plane)
452 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
453
454 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
455 plane ? "B" : "A", size);
456
457 return size;
458}
459
feb56b93 460static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 461{
462 struct drm_i915_private *dev_priv = dev->dev_private;
463 uint32_t dsparb = I915_READ(DSPARB);
464 int size;
465
466 size = dsparb & 0x1ff;
467 if (plane)
468 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
469 size >>= 1; /* Convert to cachelines */
470
471 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
472 plane ? "B" : "A", size);
473
474 return size;
475}
476
1fa61106 477static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 478{
479 struct drm_i915_private *dev_priv = dev->dev_private;
480 uint32_t dsparb = I915_READ(DSPARB);
481 int size;
482
483 size = dsparb & 0x7f;
484 size >>= 2; /* Convert to cachelines */
485
486 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
487 plane ? "B" : "A",
488 size);
489
490 return size;
491}
492
b445e3b0
ED		 493/* Pineview has different values for various configs */
494static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 495 .fifo_size = PINEVIEW_DISPLAY_FIFO,
496 .max_wm = PINEVIEW_MAX_WM,
497 .default_wm = PINEVIEW_DFT_WM,
498 .guard_size = PINEVIEW_GUARD_WM,
499 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 500};
501static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 502 .fifo_size = PINEVIEW_DISPLAY_FIFO,
503 .max_wm = PINEVIEW_MAX_WM,
504 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
505 .guard_size = PINEVIEW_GUARD_WM,
506 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 507};
508static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 509 .fifo_size = PINEVIEW_CURSOR_FIFO,
510 .max_wm = PINEVIEW_CURSOR_MAX_WM,
511 .default_wm = PINEVIEW_CURSOR_DFT_WM,
512 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
513 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 514};
515static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 516 .fifo_size = PINEVIEW_CURSOR_FIFO,
517 .max_wm = PINEVIEW_CURSOR_MAX_WM,
518 .default_wm = PINEVIEW_CURSOR_DFT_WM,
519 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
520 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 521};
522static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 523 .fifo_size = G4X_FIFO_SIZE,
524 .max_wm = G4X_MAX_WM,
525 .default_wm = G4X_MAX_WM,
526 .guard_size = 2,
527 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 528};
529static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 530 .fifo_size = I965_CURSOR_FIFO,
531 .max_wm = I965_CURSOR_MAX_WM,
532 .default_wm = I965_CURSOR_DFT_WM,
533 .guard_size = 2,
534 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 535};
536static const struct intel_watermark_params valleyview_wm_info = {
e0f0273e
VS		 537 .fifo_size = VALLEYVIEW_FIFO_SIZE,
538 .max_wm = VALLEYVIEW_MAX_WM,
539 .default_wm = VALLEYVIEW_MAX_WM,
540 .guard_size = 2,
541 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 542};
543static const struct intel_watermark_params valleyview_cursor_wm_info = {
e0f0273e
VS		 544 .fifo_size = I965_CURSOR_FIFO,
545 .max_wm = VALLEYVIEW_CURSOR_MAX_WM,
546 .default_wm = I965_CURSOR_DFT_WM,
547 .guard_size = 2,
548 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 549};
550static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 551 .fifo_size = I965_CURSOR_FIFO,
552 .max_wm = I965_CURSOR_MAX_WM,
553 .default_wm = I965_CURSOR_DFT_WM,
554 .guard_size = 2,
555 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 556};
557static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 558 .fifo_size = I945_FIFO_SIZE,
559 .max_wm = I915_MAX_WM,
560 .default_wm = 1,
561 .guard_size = 2,
562 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 563};
564static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 565 .fifo_size = I915_FIFO_SIZE,
566 .max_wm = I915_MAX_WM,
567 .default_wm = 1,
568 .guard_size = 2,
569 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 570};
9d539105 571static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 572 .fifo_size = I855GM_FIFO_SIZE,
573 .max_wm = I915_MAX_WM,
574 .default_wm = 1,
575 .guard_size = 2,
576 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 577};
9d539105
VS		 578static const struct intel_watermark_params i830_bc_wm_info = {
579 .fifo_size = I855GM_FIFO_SIZE,
580 .max_wm = I915_MAX_WM/2,
581 .default_wm = 1,
582 .guard_size = 2,
583 .cacheline_size = I830_FIFO_LINE_SIZE,
584};
feb56b93 585static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 586 .fifo_size = I830_FIFO_SIZE,
587 .max_wm = I915_MAX_WM,
588 .default_wm = 1,
589 .guard_size = 2,
590 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 591};
592
b445e3b0
ED		 593/**
594 * intel_calculate_wm - calculate watermark level
595 * @clock_in_khz: pixel clock
596 * @wm: chip FIFO params
597 * @pixel_size: display pixel size
598 * @latency_ns: memory latency for the platform
599 *
600 * Calculate the watermark level (the level at which the display plane will
601 * start fetching from memory again). Each chip has a different display
602 * FIFO size and allocation, so the caller needs to figure that out and pass
603 * in the correct intel_watermark_params structure.
604 *
605 * As the pixel clock runs, the FIFO will be drained at a rate that depends
606 * on the pixel size. When it reaches the watermark level, it'll start
607 * fetching FIFO line sized based chunks from memory until the FIFO fills
608 * past the watermark point. If the FIFO drains completely, a FIFO underrun
609 * will occur, and a display engine hang could result.
610 */
611static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
612 const struct intel_watermark_params *wm,
613 int fifo_size,
614 int pixel_size,
615 unsigned long latency_ns)
616{
617 long entries_required, wm_size;
618
619 /*
620 * Note: we need to make sure we don't overflow for various clock &
621 * latency values.
622 * clocks go from a few thousand to several hundred thousand.
623 * latency is usually a few thousand
624 */
625 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
626 1000;
627 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
628
629 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
630
631 wm_size = fifo_size - (entries_required + wm->guard_size);
632
633 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
634
635 /* Don't promote wm_size to unsigned... */
636 if (wm_size > (long)wm->max_wm)
637 wm_size = wm->max_wm;
638 if (wm_size <= 0)
639 wm_size = wm->default_wm;
d6feb196
VS		 640
641 /*
642 * Bspec seems to indicate that the value shouldn't be lower than
643 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
644 * Lets go for 8 which is the burst size since certain platforms
645 * already use a hardcoded 8 (which is what the spec says should be
646 * done).
647 */
648 if (wm_size <= 8)
649 wm_size = 8;
650
b445e3b0
ED		 651 return wm_size;
652}
653
654static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
655{
656 struct drm_crtc *crtc, *enabled = NULL;
657
70e1e0ec 658 for_each_crtc(dev, crtc) {
3490ea5d 659 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 660 if (enabled)
661 return NULL;
662 enabled = crtc;
663 }
664 }
665
666 return enabled;
667}
668
46ba614c 669static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 670{
46ba614c 671 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 672 struct drm_i915_private *dev_priv = dev->dev_private;
673 struct drm_crtc *crtc;
674 const struct cxsr_latency *latency;
675 u32 reg;
676 unsigned long wm;
677
678 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
679 dev_priv->fsb_freq, dev_priv->mem_freq);
680 if (!latency) {
681 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 682 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 683 return;
684 }
685
686 crtc = single_enabled_crtc(dev);
687 if (crtc) {
241bfc38 688 const struct drm_display_mode *adjusted_mode;
59bea882 689 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
241bfc38
DL		 690 int clock;
691
6e3c9717 692 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 693 clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 694
695 /* Display SR */
696 wm = intel_calculate_wm(clock, &pineview_display_wm,
697 pineview_display_wm.fifo_size,
698 pixel_size, latency->display_sr);
699 reg = I915_READ(DSPFW1);
700 reg &= ~DSPFW_SR_MASK;
f4998963 701 reg |= FW_WM(wm, SR);
b445e3b0
ED		 702 I915_WRITE(DSPFW1, reg);
703 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
704
705 /* cursor SR */
706 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
707 pineview_display_wm.fifo_size,
708 pixel_size, latency->cursor_sr);
709 reg = I915_READ(DSPFW3);
710 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 711 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 712 I915_WRITE(DSPFW3, reg);
713
714 /* Display HPLL off SR */
715 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
716 pineview_display_hplloff_wm.fifo_size,
717 pixel_size, latency->display_hpll_disable);
718 reg = I915_READ(DSPFW3);
719 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 720 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 721 I915_WRITE(DSPFW3, reg);
722
723 /* cursor HPLL off SR */
724 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
725 pineview_display_hplloff_wm.fifo_size,
726 pixel_size, latency->cursor_hpll_disable);
727 reg = I915_READ(DSPFW3);
728 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 729 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 730 I915_WRITE(DSPFW3, reg);
731 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
732
5209b1f4 733 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 734 } else {
5209b1f4 735 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 736 }
737}
738
739static bool g4x_compute_wm0(struct drm_device *dev,
740 int plane,
741 const struct intel_watermark_params *display,
742 int display_latency_ns,
743 const struct intel_watermark_params *cursor,
744 int cursor_latency_ns,
745 int *plane_wm,
746 int *cursor_wm)
747{
748 struct drm_crtc *crtc;
4fe8590a 749 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 750 int htotal, hdisplay, clock, pixel_size;
751 int line_time_us, line_count;
752 int entries, tlb_miss;
753
754 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 755 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 756 *cursor_wm = cursor->guard_size;
757 *plane_wm = display->guard_size;
758 return false;
759 }
760
6e3c9717 761 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 762 clock = adjusted_mode->crtc_clock;
fec8cba3 763 htotal = adjusted_mode->crtc_htotal;
6e3c9717 764 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 765 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 766
767 /* Use the small buffer method to calculate plane watermark */
768 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
769 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
770 if (tlb_miss > 0)
771 entries += tlb_miss;
772 entries = DIV_ROUND_UP(entries, display->cacheline_size);
773 *plane_wm = entries + display->guard_size;
774 if (*plane_wm > (int)display->max_wm)
775 *plane_wm = display->max_wm;
776
777 /* Use the large buffer method to calculate cursor watermark */
922044c9 778 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 779 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
3dd512fb 780 entries = line_count * crtc->cursor->state->crtc_w * pixel_size;
b445e3b0
ED		 781 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
782 if (tlb_miss > 0)
783 entries += tlb_miss;
784 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
785 *cursor_wm = entries + cursor->guard_size;
786 if (*cursor_wm > (int)cursor->max_wm)
787 *cursor_wm = (int)cursor->max_wm;
788
789 return true;
790}
791
792/*
793 * Check the wm result.
794 *
795 * If any calculated watermark values is larger than the maximum value that
796 * can be programmed into the associated watermark register, that watermark
797 * must be disabled.
798 */
799static bool g4x_check_srwm(struct drm_device *dev,
800 int display_wm, int cursor_wm,
801 const struct intel_watermark_params *display,
802 const struct intel_watermark_params *cursor)
803{
804 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
805 display_wm, cursor_wm);
806
807 if (display_wm > display->max_wm) {
808 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
809 display_wm, display->max_wm);
810 return false;
811 }
812
813 if (cursor_wm > cursor->max_wm) {
814 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
815 cursor_wm, cursor->max_wm);
816 return false;
817 }
818
819 if (!(display_wm || cursor_wm)) {
820 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
821 return false;
822 }
823
824 return true;
825}
826
827static bool g4x_compute_srwm(struct drm_device *dev,
828 int plane,
829 int latency_ns,
830 const struct intel_watermark_params *display,
831 const struct intel_watermark_params *cursor,
832 int *display_wm, int *cursor_wm)
833{
834 struct drm_crtc *crtc;
4fe8590a 835 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 836 int hdisplay, htotal, pixel_size, clock;
837 unsigned long line_time_us;
838 int line_count, line_size;
839 int small, large;
840 int entries;
841
842 if (!latency_ns) {
843 *display_wm = *cursor_wm = 0;
844 return false;
845 }
846
847 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 848 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 849 clock = adjusted_mode->crtc_clock;
fec8cba3 850 htotal = adjusted_mode->crtc_htotal;
6e3c9717 851 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 852 pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0 853
922044c9 854 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 855 line_count = (latency_ns / line_time_us + 1000) / 1000;
856 line_size = hdisplay * pixel_size;
857
858 /* Use the minimum of the small and large buffer method for primary */
859 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
860 large = line_count * line_size;
861
862 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
863 *display_wm = entries + display->guard_size;
864
865 /* calculate the self-refresh watermark for display cursor */
3dd512fb 866 entries = line_count * pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 867 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
868 *cursor_wm = entries + cursor->guard_size;
869
870 return g4x_check_srwm(dev,
871 *display_wm, *cursor_wm,
872 display, cursor);
873}
874
15665979
VS		 875#define FW_WM_VLV(value, plane) \
876 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
877
0018fda1
VS		 878static void vlv_write_wm_values(struct intel_crtc *crtc,
879 const struct vlv_wm_values *wm)
880{
881 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
882 enum pipe pipe = crtc->pipe;
883
884 I915_WRITE(VLV_DDL(pipe),
885 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
886 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
887 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
888 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
889
ae80152d 890 I915_WRITE(DSPFW1,
15665979
VS		 891 FW_WM(wm->sr.plane, SR) |
892 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
893 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
894 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 895 I915_WRITE(DSPFW2,
15665979
VS		 896 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
897 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
898 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 899 I915_WRITE(DSPFW3,
15665979 900 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 901
902 if (IS_CHERRYVIEW(dev_priv)) {
903 I915_WRITE(DSPFW7_CHV,
15665979
VS		 904 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
905 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 906 I915_WRITE(DSPFW8_CHV,
15665979
VS		 907 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
908 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 909 I915_WRITE(DSPFW9_CHV,
15665979
VS		 910 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
911 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 912 I915_WRITE(DSPHOWM,
15665979
VS		 913 FW_WM(wm->sr.plane >> 9, SR_HI) |
914 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
915 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
916 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
917 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
918 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
919 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
920 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
921 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
922 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 923 } else {
924 I915_WRITE(DSPFW7,
15665979
VS		 925 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
926 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 927 I915_WRITE(DSPHOWM,
15665979
VS		 928 FW_WM(wm->sr.plane >> 9, SR_HI) |
929 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
930 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
931 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
932 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
933 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
934 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 935 }
936
2cb389b7
VS		 937 /* zero (unused) WM1 watermarks */
938 I915_WRITE(DSPFW4, 0);
939 I915_WRITE(DSPFW5, 0);
940 I915_WRITE(DSPFW6, 0);
941 I915_WRITE(DSPHOWM1, 0);
942
ae80152d 943 POSTING_READ(DSPFW1);
0018fda1
VS		 944}
945
15665979
VS		 946#undef FW_WM_VLV
947
6eb1a681
VS		 948enum vlv_wm_level {
949 VLV_WM_LEVEL_PM2,
950 VLV_WM_LEVEL_PM5,
951 VLV_WM_LEVEL_DDR_DVFS,
952 CHV_WM_NUM_LEVELS,
953 VLV_WM_NUM_LEVELS = 1,
954};
955
262cd2e1
VS		 956/* latency must be in 0.1us units. */
957static unsigned int vlv_wm_method2(unsigned int pixel_rate,
958 unsigned int pipe_htotal,
959 unsigned int horiz_pixels,
960 unsigned int bytes_per_pixel,
961 unsigned int latency)
962{
963 unsigned int ret;
964
965 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
966 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
967 ret = DIV_ROUND_UP(ret, 64);
968
969 return ret;
970}
971
972static void vlv_setup_wm_latency(struct drm_device *dev)
973{
974 struct drm_i915_private *dev_priv = dev->dev_private;
975
976 /* all latencies in usec */
977 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
978
979 if (IS_CHERRYVIEW(dev_priv)) {
980 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
981 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
982 }
983}
984
985static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
986 struct intel_crtc *crtc,
987 const struct intel_plane_state *state,
988 int level)
989{
990 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
991 int clock, htotal, pixel_size, width, wm;
992
993 if (dev_priv->wm.pri_latency[level] == 0)
994 return USHRT_MAX;
995
996 if (!state->visible)
997 return 0;
998
999 pixel_size = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1000 clock = crtc->config->base.adjusted_mode.crtc_clock;
1001 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
1002 width = crtc->config->pipe_src_w;
1003 if (WARN_ON(htotal == 0))
1004 htotal = 1;
1005
1006 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1007 /*
1008 * FIXME the formula gives values that are
1009 * too big for the cursor FIFO, and hence we
1010 * would never be able to use cursors. For
1011 * now just hardcode the watermark.
1012 */
1013 wm = 63;
1014 } else {
1015 wm = vlv_wm_method2(clock, htotal, width, pixel_size,
1016 dev_priv->wm.pri_latency[level] * 10);
1017 }
1018
1019 return min_t(int, wm, USHRT_MAX);
1020}
1021
54f1b6e1
VS		 1022static void vlv_compute_fifo(struct intel_crtc *crtc)
1023{
1024 struct drm_device *dev = crtc->base.dev;
1025 struct vlv_wm_state *wm_state = &crtc->wm_state;
1026 struct intel_plane *plane;
1027 unsigned int total_rate = 0;
1028 const int fifo_size = 512 - 1;
1029 int fifo_extra, fifo_left = fifo_size;
1030
1031 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1032 struct intel_plane_state *state =
1033 to_intel_plane_state(plane->base.state);
1034
1035 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1036 continue;
1037
1038 if (state->visible) {
1039 wm_state->num_active_planes++;
1040 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1041 }
1042 }
1043
1044 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1045 struct intel_plane_state *state =
1046 to_intel_plane_state(plane->base.state);
1047 unsigned int rate;
1048
1049 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1050 plane->wm.fifo_size = 63;
1051 continue;
1052 }
1053
1054 if (!state->visible) {
1055 plane->wm.fifo_size = 0;
1056 continue;
1057 }
1058
1059 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1060 plane->wm.fifo_size = fifo_size * rate / total_rate;
1061 fifo_left -= plane->wm.fifo_size;
1062 }
1063
1064 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1065
1066 /* spread the remainder evenly */
1067 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1068 int plane_extra;
1069
1070 if (fifo_left == 0)
1071 break;
1072
1073 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1074 continue;
1075
1076 /* give it all to the first plane if none are active */
1077 if (plane->wm.fifo_size == 0 &&
1078 wm_state->num_active_planes)
1079 continue;
1080
1081 plane_extra = min(fifo_extra, fifo_left);
1082 plane->wm.fifo_size += plane_extra;
1083 fifo_left -= plane_extra;
1084 }
1085
1086 WARN_ON(fifo_left != 0);
1087}
1088
262cd2e1
VS		 1089static void vlv_invert_wms(struct intel_crtc *crtc)
1090{
1091 struct vlv_wm_state *wm_state = &crtc->wm_state;
1092 int level;
1093
1094 for (level = 0; level < wm_state->num_levels; level++) {
1095 struct drm_device *dev = crtc->base.dev;
1096 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1097 struct intel_plane *plane;
1098
1099 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1100 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1101
1102 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1103 switch (plane->base.type) {
1104 int sprite;
1105 case DRM_PLANE_TYPE_CURSOR:
1106 wm_state->wm[level].cursor = plane->wm.fifo_size -
1107 wm_state->wm[level].cursor;
1108 break;
1109 case DRM_PLANE_TYPE_PRIMARY:
1110 wm_state->wm[level].primary = plane->wm.fifo_size -
1111 wm_state->wm[level].primary;
1112 break;
1113 case DRM_PLANE_TYPE_OVERLAY:
1114 sprite = plane->plane;
1115 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1116 wm_state->wm[level].sprite[sprite];
1117 break;
1118 }
1119 }
1120 }
1121}
1122
26e1fe4f 1123static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1124{
1125 struct drm_device *dev = crtc->base.dev;
1126 struct vlv_wm_state *wm_state = &crtc->wm_state;
1127 struct intel_plane *plane;
1128 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1129 int level;
1130
1131 memset(wm_state, 0, sizeof(*wm_state));
1132
852eb00d 1133 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
262cd2e1
VS		 1134 if (IS_CHERRYVIEW(dev))
1135 wm_state->num_levels = CHV_WM_NUM_LEVELS;
1136 else
1137 wm_state->num_levels = VLV_WM_NUM_LEVELS;
1138
1139 wm_state->num_active_planes = 0;
262cd2e1 1140
54f1b6e1 1141 vlv_compute_fifo(crtc);
262cd2e1
VS		 1142
1143 if (wm_state->num_active_planes != 1)
1144 wm_state->cxsr = false;
1145
1146 if (wm_state->cxsr) {
1147 for (level = 0; level < wm_state->num_levels; level++) {
1148 wm_state->sr[level].plane = sr_fifo_size;
1149 wm_state->sr[level].cursor = 63;
1150 }
1151 }
1152
1153 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1154 struct intel_plane_state *state =
1155 to_intel_plane_state(plane->base.state);
1156
1157 if (!state->visible)
1158 continue;
1159
1160 /* normal watermarks */
1161 for (level = 0; level < wm_state->num_levels; level++) {
1162 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1163 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1164
1165 /* hack */
1166 if (WARN_ON(level == 0 && wm > max_wm))
1167 wm = max_wm;
1168
1169 if (wm > plane->wm.fifo_size)
1170 break;
1171
1172 switch (plane->base.type) {
1173 int sprite;
1174 case DRM_PLANE_TYPE_CURSOR:
1175 wm_state->wm[level].cursor = wm;
1176 break;
1177 case DRM_PLANE_TYPE_PRIMARY:
1178 wm_state->wm[level].primary = wm;
1179 break;
1180 case DRM_PLANE_TYPE_OVERLAY:
1181 sprite = plane->plane;
1182 wm_state->wm[level].sprite[sprite] = wm;
1183 break;
1184 }
1185 }
1186
1187 wm_state->num_levels = level;
1188
1189 if (!wm_state->cxsr)
1190 continue;
1191
1192 /* maxfifo watermarks */
1193 switch (plane->base.type) {
1194 int sprite, level;
1195 case DRM_PLANE_TYPE_CURSOR:
1196 for (level = 0; level < wm_state->num_levels; level++)
1197 wm_state->sr[level].cursor =
1198 wm_state->sr[level].cursor;
1199 break;
1200 case DRM_PLANE_TYPE_PRIMARY:
1201 for (level = 0; level < wm_state->num_levels; level++)
1202 wm_state->sr[level].plane =
1203 min(wm_state->sr[level].plane,
1204 wm_state->wm[level].primary);
1205 break;
1206 case DRM_PLANE_TYPE_OVERLAY:
1207 sprite = plane->plane;
1208 for (level = 0; level < wm_state->num_levels; level++)
1209 wm_state->sr[level].plane =
1210 min(wm_state->sr[level].plane,
1211 wm_state->wm[level].sprite[sprite]);
1212 break;
1213 }
1214 }
1215
1216 /* clear any (partially) filled invalid levels */
1217 for (level = wm_state->num_levels; level < CHV_WM_NUM_LEVELS; level++) {
1218 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1219 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1220 }
1221
1222 vlv_invert_wms(crtc);
1223}
1224
54f1b6e1
VS		 1225#define VLV_FIFO(plane, value) \
1226 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1227
1228static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1229{
1230 struct drm_device *dev = crtc->base.dev;
1231 struct drm_i915_private *dev_priv = to_i915(dev);
1232 struct intel_plane *plane;
1233 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1234
1235 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1236 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1237 WARN_ON(plane->wm.fifo_size != 63);
1238 continue;
1239 }
1240
1241 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1242 sprite0_start = plane->wm.fifo_size;
1243 else if (plane->plane == 0)
1244 sprite1_start = sprite0_start + plane->wm.fifo_size;
1245 else
1246 fifo_size = sprite1_start + plane->wm.fifo_size;
1247 }
1248
1249 WARN_ON(fifo_size != 512 - 1);
1250
1251 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1252 pipe_name(crtc->pipe), sprite0_start,
1253 sprite1_start, fifo_size);
1254
1255 switch (crtc->pipe) {
1256 uint32_t dsparb, dsparb2, dsparb3;
1257 case PIPE_A:
1258 dsparb = I915_READ(DSPARB);
1259 dsparb2 = I915_READ(DSPARB2);
1260
1261 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1262 VLV_FIFO(SPRITEB, 0xff));
1263 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1264 VLV_FIFO(SPRITEB, sprite1_start));
1265
1266 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1267 VLV_FIFO(SPRITEB_HI, 0x1));
1268 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1269 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1270
1271 I915_WRITE(DSPARB, dsparb);
1272 I915_WRITE(DSPARB2, dsparb2);
1273 break;
1274 case PIPE_B:
1275 dsparb = I915_READ(DSPARB);
1276 dsparb2 = I915_READ(DSPARB2);
1277
1278 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1279 VLV_FIFO(SPRITED, 0xff));
1280 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1281 VLV_FIFO(SPRITED, sprite1_start));
1282
1283 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1284 VLV_FIFO(SPRITED_HI, 0xff));
1285 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1286 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1287
1288 I915_WRITE(DSPARB, dsparb);
1289 I915_WRITE(DSPARB2, dsparb2);
1290 break;
1291 case PIPE_C:
1292 dsparb3 = I915_READ(DSPARB3);
1293 dsparb2 = I915_READ(DSPARB2);
1294
1295 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1296 VLV_FIFO(SPRITEF, 0xff));
1297 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1298 VLV_FIFO(SPRITEF, sprite1_start));
1299
1300 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1301 VLV_FIFO(SPRITEF_HI, 0xff));
1302 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1303 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1304
1305 I915_WRITE(DSPARB3, dsparb3);
1306 I915_WRITE(DSPARB2, dsparb2);
1307 break;
1308 default:
1309 break;
1310 }
1311}
1312
1313#undef VLV_FIFO
1314
262cd2e1
VS		 1315static void vlv_merge_wm(struct drm_device *dev,
1316 struct vlv_wm_values *wm)
1317{
1318 struct intel_crtc *crtc;
1319 int num_active_crtcs = 0;
1320
1321 if (IS_CHERRYVIEW(dev))
1322 wm->level = VLV_WM_LEVEL_DDR_DVFS;
1323 else
1324 wm->level = VLV_WM_LEVEL_PM2;
1325 wm->cxsr = true;
1326
1327 for_each_intel_crtc(dev, crtc) {
1328 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1329
1330 if (!crtc->active)
1331 continue;
1332
1333 if (!wm_state->cxsr)
1334 wm->cxsr = false;
1335
1336 num_active_crtcs++;
1337 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1338 }
1339
1340 if (num_active_crtcs != 1)
1341 wm->cxsr = false;
1342
6f9c784b
VS		 1343 if (num_active_crtcs > 1)
1344 wm->level = VLV_WM_LEVEL_PM2;
1345
262cd2e1
VS		 1346 for_each_intel_crtc(dev, crtc) {
1347 struct vlv_wm_state *wm_state = &crtc->wm_state;
1348 enum pipe pipe = crtc->pipe;
1349
1350 if (!crtc->active)
1351 continue;
1352
1353 wm->pipe[pipe] = wm_state->wm[wm->level];
1354 if (wm->cxsr)
1355 wm->sr = wm_state->sr[wm->level];
1356
1357 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1358 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1359 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1360 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1361 }
1362}
1363
1364static void vlv_update_wm(struct drm_crtc *crtc)
1365{
1366 struct drm_device *dev = crtc->dev;
1367 struct drm_i915_private *dev_priv = dev->dev_private;
1368 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1369 enum pipe pipe = intel_crtc->pipe;
1370 struct vlv_wm_values wm = {};
1371
26e1fe4f 1372 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1373 vlv_merge_wm(dev, &wm);
1374
54f1b6e1
VS		 1375 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1376 /* FIXME should be part of crtc atomic commit */
1377 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1378 return;
54f1b6e1 1379 }
262cd2e1
VS		 1380
1381 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1382 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1383 chv_set_memory_dvfs(dev_priv, false);
1384
1385 if (wm.level < VLV_WM_LEVEL_PM5 &&
1386 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1387 chv_set_memory_pm5(dev_priv, false);
1388
852eb00d 1389 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1390 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1391
54f1b6e1
VS		 1392 /* FIXME should be part of crtc atomic commit */
1393 vlv_pipe_set_fifo_size(intel_crtc);
1394
262cd2e1
VS		 1395 vlv_write_wm_values(intel_crtc, &wm);
1396
1397 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1398 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1399 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1400 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1401 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1402
852eb00d 1403 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1404 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1405
1406 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1407 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1408 chv_set_memory_pm5(dev_priv, true);
1409
1410 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1411 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1412 chv_set_memory_dvfs(dev_priv, true);
1413
1414 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1415}
1416
ae80152d
VS		 1417#define single_plane_enabled(mask) is_power_of_2(mask)
1418
46ba614c 1419static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1420{
46ba614c 1421 struct drm_device *dev = crtc->dev;
b445e3b0
ED		 1422 static const int sr_latency_ns = 12000;
1423 struct drm_i915_private *dev_priv = dev->dev_private;
1424 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1425 int plane_sr, cursor_sr;
1426 unsigned int enabled = 0;
9858425c 1427 bool cxsr_enabled;
b445e3b0 1428
51cea1f4 1429 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1430 &g4x_wm_info, pessimal_latency_ns,
1431 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1432 &planea_wm, &cursora_wm))
51cea1f4 1433 enabled |= 1 << PIPE_A;
b445e3b0 1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1436 &g4x_wm_info, pessimal_latency_ns,
1437 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1438 &planeb_wm, &cursorb_wm))
51cea1f4 1439 enabled |= 1 << PIPE_B;
b445e3b0 1440
b445e3b0
ED		 1441 if (single_plane_enabled(enabled) &&
1442 g4x_compute_srwm(dev, ffs(enabled) - 1,
1443 sr_latency_ns,
1444 &g4x_wm_info,
1445 &g4x_cursor_wm_info,
52bd02d8 1446 &plane_sr, &cursor_sr)) {
9858425c 1447 cxsr_enabled = true;
52bd02d8 1448 } else {
9858425c 1449 cxsr_enabled = false;
5209b1f4 1450 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1451 plane_sr = cursor_sr = 0;
1452 }
b445e3b0 1453
a5043453
VS		 1454 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1455 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1456 planea_wm, cursora_wm,
1457 planeb_wm, cursorb_wm,
1458 plane_sr, cursor_sr);
1459
1460 I915_WRITE(DSPFW1,
f4998963
VS		 1461 FW_WM(plane_sr, SR) |
1462 FW_WM(cursorb_wm, CURSORB) |
1463 FW_WM(planeb_wm, PLANEB) |
1464 FW_WM(planea_wm, PLANEA));
b445e3b0 1465 I915_WRITE(DSPFW2,
8c919b28 1466 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1467 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1468 /* HPLL off in SR has some issues on G4x... disable it */
1469 I915_WRITE(DSPFW3,
8c919b28 1470 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1471 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1472
1473 if (cxsr_enabled)
1474 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1475}
1476
46ba614c 1477static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1478{
46ba614c 1479 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1480 struct drm_i915_private *dev_priv = dev->dev_private;
1481 struct drm_crtc *crtc;
1482 int srwm = 1;
1483 int cursor_sr = 16;
9858425c 1484 bool cxsr_enabled;
b445e3b0
ED		 1485
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1488 if (crtc) {
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
4fe8590a 1491 const struct drm_display_mode *adjusted_mode =
6e3c9717 1492 &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1493 int clock = adjusted_mode->crtc_clock;
fec8cba3 1494 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1495 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
59bea882 1496 int pixel_size = crtc->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1497 unsigned long line_time_us;
1498 int entries;
1499
922044c9 1500 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1501
1502 /* Use ns/us then divide to preserve precision */
1503 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1504 pixel_size * hdisplay;
1505 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1506 srwm = I965_FIFO_SIZE - entries;
1507 if (srwm < 0)
1508 srwm = 1;
1509 srwm &= 0x1ff;
1510 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1511 entries, srwm);
1512
1513 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
3dd512fb 1514 pixel_size * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1515 entries = DIV_ROUND_UP(entries,
1516 i965_cursor_wm_info.cacheline_size);
1517 cursor_sr = i965_cursor_wm_info.fifo_size -
1518 (entries + i965_cursor_wm_info.guard_size);
1519
1520 if (cursor_sr > i965_cursor_wm_info.max_wm)
1521 cursor_sr = i965_cursor_wm_info.max_wm;
1522
1523 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1524 "cursor %d\n", srwm, cursor_sr);
1525
9858425c 1526 cxsr_enabled = true;
b445e3b0 1527 } else {
9858425c 1528 cxsr_enabled = false;
b445e3b0 1529 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1530 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1531 }
1532
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534 srwm);
1535
1536 /* 965 has limitations... */
f4998963
VS		 1537 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1538 FW_WM(8, CURSORB) |
1539 FW_WM(8, PLANEB) |
1540 FW_WM(8, PLANEA));
1541 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1542 FW_WM(8, PLANEC_OLD));
b445e3b0 1543 /* update cursor SR watermark */
f4998963 1544 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1545
1546 if (cxsr_enabled)
1547 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1548}
1549
f4998963
VS		 1550#undef FW_WM
1551
46ba614c 1552static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1553{
46ba614c 1554 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1555 struct drm_i915_private *dev_priv = dev->dev_private;
1556 const struct intel_watermark_params *wm_info;
1557 uint32_t fwater_lo;
1558 uint32_t fwater_hi;
1559 int cwm, srwm = 1;
1560 int fifo_size;
1561 int planea_wm, planeb_wm;
1562 struct drm_crtc *crtc, *enabled = NULL;
1563
1564 if (IS_I945GM(dev))
1565 wm_info = &i945_wm_info;
1566 else if (!IS_GEN2(dev))
1567 wm_info = &i915_wm_info;
1568 else
9d539105 1569 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1570
1571 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1572 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1573 if (intel_crtc_active(crtc)) {
241bfc38 1574 const struct drm_display_mode *adjusted_mode;
59bea882 1575 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1576 if (IS_GEN2(dev))
1577 cpp = 4;
1578
6e3c9717 1579 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1580 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1581 wm_info, fifo_size, cpp,
5aef6003 1582 pessimal_latency_ns);
b445e3b0 1583 enabled = crtc;
9d539105 1584 } else {
b445e3b0 1585 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1586 if (planea_wm > (long)wm_info->max_wm)
1587 planea_wm = wm_info->max_wm;
1588 }
1589
1590 if (IS_GEN2(dev))
1591 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1592
1593 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1594 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1595 if (intel_crtc_active(crtc)) {
241bfc38 1596 const struct drm_display_mode *adjusted_mode;
59bea882 1597 int cpp = crtc->primary->state->fb->bits_per_pixel / 8;
b9e0bda3
CW		 1598 if (IS_GEN2(dev))
1599 cpp = 4;
1600
6e3c9717 1601 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1602 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1603 wm_info, fifo_size, cpp,
5aef6003 1604 pessimal_latency_ns);
b445e3b0
ED		 1605 if (enabled == NULL)
1606 enabled = crtc;
1607 else
1608 enabled = NULL;
9d539105 1609 } else {
b445e3b0 1610 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1611 if (planeb_wm > (long)wm_info->max_wm)
1612 planeb_wm = wm_info->max_wm;
1613 }
b445e3b0
ED		 1614
1615 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1616
2ab1bc9d 1617 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1618 struct drm_i915_gem_object *obj;
2ab1bc9d 1619
59bea882 1620 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1621
1622 /* self-refresh seems busted with untiled */
2ff8fde1 1623 if (obj->tiling_mode == I915_TILING_NONE)
2ab1bc9d
DV		 1624 enabled = NULL;
1625 }
1626
b445e3b0
ED		 1627 /*
1628 * Overlay gets an aggressive default since video jitter is bad.
1629 */
1630 cwm = 2;
1631
1632 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1633 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1634
1635 /* Calc sr entries for one plane configs */
1636 if (HAS_FW_BLC(dev) && enabled) {
1637 /* self-refresh has much higher latency */
1638 static const int sr_latency_ns = 6000;
4fe8590a 1639 const struct drm_display_mode *adjusted_mode =
6e3c9717 1640 &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1641 int clock = adjusted_mode->crtc_clock;
fec8cba3 1642 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1643 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
59bea882 1644 int pixel_size = enabled->primary->state->fb->bits_per_pixel / 8;
b445e3b0
ED		 1645 unsigned long line_time_us;
1646 int entries;
1647
922044c9 1648 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1649
1650 /* Use ns/us then divide to preserve precision */
1651 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1652 pixel_size * hdisplay;
1653 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1654 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1655 srwm = wm_info->fifo_size - entries;
1656 if (srwm < 0)
1657 srwm = 1;
1658
1659 if (IS_I945G(dev) || IS_I945GM(dev))
1660 I915_WRITE(FW_BLC_SELF,
1661 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1662 else if (IS_I915GM(dev))
1663 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1664 }
1665
1666 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1667 planea_wm, planeb_wm, cwm, srwm);
1668
1669 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1670 fwater_hi = (cwm & 0x1f);
1671
1672 /* Set request length to 8 cachelines per fetch */
1673 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1674 fwater_hi = fwater_hi | (1 << 8);
1675
1676 I915_WRITE(FW_BLC, fwater_lo);
1677 I915_WRITE(FW_BLC2, fwater_hi);
1678
5209b1f4
ID		 1679 if (enabled)
1680 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1681}
1682
feb56b93 1683static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1684{
46ba614c 1685 struct drm_device *dev = unused_crtc->dev;
b445e3b0
ED		 1686 struct drm_i915_private *dev_priv = dev->dev_private;
1687 struct drm_crtc *crtc;
241bfc38 1688 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1689 uint32_t fwater_lo;
1690 int planea_wm;
1691
1692 crtc = single_enabled_crtc(dev);
1693 if (crtc == NULL)
1694 return;
1695
6e3c9717 1696 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1697 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1698 &i845_wm_info,
b445e3b0 1699 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1700 4, pessimal_latency_ns);
b445e3b0
ED		 1701 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1702 fwater_lo |= (3<<8) | planea_wm;
1703
1704 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1705
1706 I915_WRITE(FW_BLC, fwater_lo);
1707}
1708
8cfb3407 1709uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1710{
fd4daa9c 1711 uint32_t pixel_rate;
801bcfff 1712
8cfb3407 1713 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1714
1715 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1716 * adjust the pixel_rate here. */
1717
8cfb3407 1718 if (pipe_config->pch_pfit.enabled) {
801bcfff 1719 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1720 uint32_t pfit_size = pipe_config->pch_pfit.size;
1721
1722 pipe_w = pipe_config->pipe_src_w;
1723 pipe_h = pipe_config->pipe_src_h;
801bcfff 1724
801bcfff
PZ		 1725 pfit_w = (pfit_size >> 16) & 0xFFFF;
1726 pfit_h = pfit_size & 0xFFFF;
1727 if (pipe_w < pfit_w)
1728 pipe_w = pfit_w;
1729 if (pipe_h < pfit_h)
1730 pipe_h = pfit_h;
1731
1732 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1733 pfit_w * pfit_h);
1734 }
1735
1736 return pixel_rate;
1737}
1738
37126462 1739/* latency must be in 0.1us units. */
23297044 1740static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 1741 uint32_t latency)
1742{
1743 uint64_t ret;
1744
3312ba65
VS		 1745 if (WARN(latency == 0, "Latency value missing\n"))
1746 return UINT_MAX;
1747
801bcfff
PZ		 1748 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
1749 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1750
1751 return ret;
1752}
1753
37126462 1754/* latency must be in 0.1us units. */
23297044 1755static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 1756 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
1757 uint32_t latency)
1758{
1759 uint32_t ret;
1760
3312ba65
VS		 1761 if (WARN(latency == 0, "Latency value missing\n"))
1762 return UINT_MAX;
1763
801bcfff
PZ		 1764 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
1765 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
1766 ret = DIV_ROUND_UP(ret, 64) + 2;
1767 return ret;
1768}
1769
23297044 1770static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 1771 uint8_t bytes_per_pixel)
1772{
1773 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
1774}
1775
2ac96d2a
PB		 1776struct skl_pipe_wm_parameters {
1777 bool active;
1778 uint32_t pipe_htotal;
1779 uint32_t pixel_rate; /* in KHz */
1780 struct intel_plane_wm_parameters plane[I915_MAX_PLANES];
1781 struct intel_plane_wm_parameters cursor;
1782};
1783
820c1980 1784struct ilk_pipe_wm_parameters {
801bcfff 1785 bool active;
801bcfff
PZ		 1786 uint32_t pipe_htotal;
1787 uint32_t pixel_rate;
c35426d2
VS		 1788 struct intel_plane_wm_parameters pri;
1789 struct intel_plane_wm_parameters spr;
1790 struct intel_plane_wm_parameters cur;
801bcfff
PZ		 1791};
1792
820c1980 1793struct ilk_wm_maximums {
cca32e9a
PZ		 1794 uint16_t pri;
1795 uint16_t spr;
1796 uint16_t cur;
1797 uint16_t fbc;
1798};
1799
240264f4
VS		 1800/* used in computing the new watermarks state */
1801struct intel_wm_config {
1802 unsigned int num_pipes_active;
1803 bool sprites_enabled;
1804 bool sprites_scaled;
240264f4
VS		 1805};
1806
37126462
VS		 1807/*
1808 * For both WM_PIPE and WM_LP.
1809 * mem_value must be in 0.1us units.
1810 */
820c1980 1811static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params,
cca32e9a
PZ		 1812 uint32_t mem_value,
1813 bool is_lp)
801bcfff 1814{
cca32e9a
PZ		 1815 uint32_t method1, method2;
1816
c35426d2 1817 if (!params->active || !params->pri.enabled)
801bcfff
PZ		 1818 return 0;
1819
23297044 1820 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1821 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1822 mem_value);
1823
1824 if (!is_lp)
1825 return method1;
1826
23297044 1827 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a 1828 params->pipe_htotal,
c35426d2
VS		 1829 params->pri.horiz_pixels,
1830 params->pri.bytes_per_pixel,
cca32e9a
PZ		 1831 mem_value);
1832
1833 return min(method1, method2);
801bcfff
PZ		 1834}
1835
37126462
VS		 1836/*
1837 * For both WM_PIPE and WM_LP.
1838 * mem_value must be in 0.1us units.
1839 */
820c1980 1840static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1841 uint32_t mem_value)
1842{
1843 uint32_t method1, method2;
1844
c35426d2 1845 if (!params->active || !params->spr.enabled)
801bcfff
PZ		 1846 return 0;
1847
23297044 1848 method1 = ilk_wm_method1(params->pixel_rate,
c35426d2 1849 params->spr.bytes_per_pixel,
801bcfff 1850 mem_value);
23297044 1851 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff 1852 params->pipe_htotal,
c35426d2
VS		 1853 params->spr.horiz_pixels,
1854 params->spr.bytes_per_pixel,
801bcfff
PZ		 1855 mem_value);
1856 return min(method1, method2);
1857}
1858
37126462
VS		 1859/*
1860 * For both WM_PIPE and WM_LP.
1861 * mem_value must be in 0.1us units.
1862 */
820c1980 1863static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params,
801bcfff
PZ		 1864 uint32_t mem_value)
1865{
c35426d2 1866 if (!params->active || !params->cur.enabled)
801bcfff
PZ		 1867 return 0;
1868
23297044 1869 return ilk_wm_method2(params->pixel_rate,
801bcfff 1870 params->pipe_htotal,
c35426d2
VS		 1871 params->cur.horiz_pixels,
1872 params->cur.bytes_per_pixel,
801bcfff
PZ		 1873 mem_value);
1874}
1875
cca32e9a 1876/* Only for WM_LP. */
820c1980 1877static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params,
1fda9882 1878 uint32_t pri_val)
cca32e9a 1879{
c35426d2 1880 if (!params->active || !params->pri.enabled)
cca32e9a
PZ		 1881 return 0;
1882
23297044 1883 return ilk_wm_fbc(pri_val,
c35426d2
VS		 1884 params->pri.horiz_pixels,
1885 params->pri.bytes_per_pixel);
cca32e9a
PZ		 1886}
1887
158ae64f
VS		 1888static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1889{
416f4727
VS		 1890 if (INTEL_INFO(dev)->gen >= 8)
1891 return 3072;
1892 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1893 return 768;
1894 else
1895 return 512;
1896}
1897
4e975081
VS		 1898static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1899 int level, bool is_sprite)
1900{
1901 if (INTEL_INFO(dev)->gen >= 8)
1902 /* BDW primary/sprite plane watermarks */
1903 return level == 0 ? 255 : 2047;
1904 else if (INTEL_INFO(dev)->gen >= 7)
1905 /* IVB/HSW primary/sprite plane watermarks */
1906 return level == 0 ? 127 : 1023;
1907 else if (!is_sprite)
1908 /* ILK/SNB primary plane watermarks */
1909 return level == 0 ? 127 : 511;
1910 else
1911 /* ILK/SNB sprite plane watermarks */
1912 return level == 0 ? 63 : 255;
1913}
1914
1915static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1916 int level)
1917{
1918 if (INTEL_INFO(dev)->gen >= 7)
1919 return level == 0 ? 63 : 255;
1920 else
1921 return level == 0 ? 31 : 63;
1922}
1923
1924static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1925{
1926 if (INTEL_INFO(dev)->gen >= 8)
1927 return 31;
1928 else
1929 return 15;
1930}
1931
158ae64f
VS		 1932/* Calculate the maximum primary/sprite plane watermark */
1933static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1934 int level,
240264f4 1935 const struct intel_wm_config *config,
158ae64f
VS		 1936 enum intel_ddb_partitioning ddb_partitioning,
1937 bool is_sprite)
1938{
1939 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1940
1941 /* if sprites aren't enabled, sprites get nothing */
240264f4 1942 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1943 return 0;
1944
1945 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1946 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1947 fifo_size /= INTEL_INFO(dev)->num_pipes;
1948
1949 /*
1950 * For some reason the non self refresh
1951 * FIFO size is only half of the self
1952 * refresh FIFO size on ILK/SNB.
1953 */
1954 if (INTEL_INFO(dev)->gen <= 6)
1955 fifo_size /= 2;
1956 }
1957
240264f4 1958 if (config->sprites_enabled) {
158ae64f
VS		 1959 /* level 0 is always calculated with 1:1 split */
1960 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1961 if (is_sprite)
1962 fifo_size *= 5;
1963 fifo_size /= 6;
1964 } else {
1965 fifo_size /= 2;
1966 }
1967 }
1968
1969 /* clamp to max that the registers can hold */
4e975081 1970 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1971}
1972
1973/* Calculate the maximum cursor plane watermark */
1974static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1975 int level,
1976 const struct intel_wm_config *config)
158ae64f
VS		 1977{
1978 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1979 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1980 return 64;
1981
1982 /* otherwise just report max that registers can hold */
4e975081 1983 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1984}
1985
d34ff9c6 1986static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1987 int level,
1988 const struct intel_wm_config *config,
1989 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1990 struct ilk_wm_maximums *max)
158ae64f 1991{
240264f4
VS		 1992 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1993 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1994 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1995 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1996}
1997
a3cb4048
VS		 1998static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1999 int level,
2000 struct ilk_wm_maximums *max)
2001{
2002 max->pri = ilk_plane_wm_reg_max(dev, level, false);
2003 max->spr = ilk_plane_wm_reg_max(dev, level, true);
2004 max->cur = ilk_cursor_wm_reg_max(dev, level);
2005 max->fbc = ilk_fbc_wm_reg_max(dev);
2006}
2007
d9395655 2008static bool ilk_validate_wm_level(int level,
820c1980 2009 const struct ilk_wm_maximums *max,
d9395655 2010 struct intel_wm_level *result)
a9786a11
VS		 2011{
2012 bool ret;
2013
2014 /* already determined to be invalid? */
2015 if (!result->enable)
2016 return false;
2017
2018 result->enable = result->pri_val <= max->pri &&
2019 result->spr_val <= max->spr &&
2020 result->cur_val <= max->cur;
2021
2022 ret = result->enable;
2023
2024 /*
2025 * HACK until we can pre-compute everything,
2026 * and thus fail gracefully if LP0 watermarks
2027 * are exceeded...
2028 */
2029 if (level == 0 && !result->enable) {
2030 if (result->pri_val > max->pri)
2031 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2032 level, result->pri_val, max->pri);
2033 if (result->spr_val > max->spr)
2034 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2035 level, result->spr_val, max->spr);
2036 if (result->cur_val > max->cur)
2037 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2038 level, result->cur_val, max->cur);
2039
2040 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2041 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2042 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2043 result->enable = true;
2044 }
2045
a9786a11
VS		 2046 return ret;
2047}
2048
d34ff9c6 2049static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
6f5ddd17 2050 int level,
820c1980 2051 const struct ilk_pipe_wm_parameters *p,
1fd527cc 2052 struct intel_wm_level *result)
6f5ddd17
VS		 2053{
2054 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2055 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2056 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2057
2058 /* WM1+ latency values stored in 0.5us units */
2059 if (level > 0) {
2060 pri_latency *= 5;
2061 spr_latency *= 5;
2062 cur_latency *= 5;
2063 }
2064
2065 result->pri_val = ilk_compute_pri_wm(p, pri_latency, level);
2066 result->spr_val = ilk_compute_spr_wm(p, spr_latency);
2067 result->cur_val = ilk_compute_cur_wm(p, cur_latency);
2068 result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val);
2069 result->enable = true;
2070}
2071
801bcfff
PZ		 2072static uint32_t
2073hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2074{
2075 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2076 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
6e3c9717 2077 struct drm_display_mode *mode = &intel_crtc->config->base.adjusted_mode;
85a02deb 2078 u32 linetime, ips_linetime;
1f8eeabf 2079
3ef00284 2080 if (!intel_crtc->active)
801bcfff 2081 return 0;
1011d8c4 2082
1f8eeabf
ED		 2083 /* The WM are computed with base on how long it takes to fill a single
2084 * row at the given clock rate, multiplied by 8.
2085 * */
fec8cba3
JB		 2086 linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
2087 mode->crtc_clock);
2088 ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8,
05024da3 2089 dev_priv->cdclk_freq);
1f8eeabf 2090
801bcfff
PZ		 2091 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2092 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2093}
2094
2af30a5c 2095static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df
VS		 2096{
2097 struct drm_i915_private *dev_priv = dev->dev_private;
2098
2af30a5c
PB		 2099 if (IS_GEN9(dev)) {
2100 uint32_t val;
4f947386 2101 int ret, i;
367294be 2102 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2103
2104 /* read the first set of memory latencies[0:3] */
2105 val = 0; /* data0 to be programmed to 0 for first set */
2106 mutex_lock(&dev_priv->rps.hw_lock);
2107 ret = sandybridge_pcode_read(dev_priv,
2108 GEN9_PCODE_READ_MEM_LATENCY,
2109 &val);
2110 mutex_unlock(&dev_priv->rps.hw_lock);
2111
2112 if (ret) {
2113 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2114 return;
2115 }
2116
2117 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2118 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2119 GEN9_MEM_LATENCY_LEVEL_MASK;
2120 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2121 GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124
2125 /* read the second set of memory latencies[4:7] */
2126 val = 1; /* data0 to be programmed to 1 for second set */
2127 mutex_lock(&dev_priv->rps.hw_lock);
2128 ret = sandybridge_pcode_read(dev_priv,
2129 GEN9_PCODE_READ_MEM_LATENCY,
2130 &val);
2131 mutex_unlock(&dev_priv->rps.hw_lock);
2132 if (ret) {
2133 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2134 return;
2135 }
2136
2137 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2138 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2139 GEN9_MEM_LATENCY_LEVEL_MASK;
2140 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2141 GEN9_MEM_LATENCY_LEVEL_MASK;
2142 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2143 GEN9_MEM_LATENCY_LEVEL_MASK;
2144
367294be 2145 /*
6f97235b
DL		 2146 * WaWmMemoryReadLatency:skl
2147 *
367294be
VK		 2148 * punit doesn't take into account the read latency so we need
2149 * to add 2us to the various latency levels we retrieve from
2150 * the punit.
2151 * - W0 is a bit special in that it's the only level that
2152 * can't be disabled if we want to have display working, so
2153 * we always add 2us there.
2154 * - For levels >=1, punit returns 0us latency when they are
2155 * disabled, so we respect that and don't add 2us then
4f947386
VK		 2156 *
2157 * Additionally, if a level n (n > 1) has a 0us latency, all
2158 * levels m (m >= n) need to be disabled. We make sure to
2159 * sanitize the values out of the punit to satisfy this
2160 * requirement.
367294be
VK		 2161 */
2162 wm[0] += 2;
2163 for (level = 1; level <= max_level; level++)
2164 if (wm[level] != 0)
2165 wm[level] += 2;
4f947386
VK		 2166 else {
2167 for (i = level + 1; i <= max_level; i++)
2168 wm[i] = 0;
367294be 2169
4f947386
VK		 2170 break;
2171 }
2af30a5c 2172 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2173 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2174
2175 wm[0] = (sskpd >> 56) & 0xFF;
2176 if (wm[0] == 0)
2177 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2178 wm[1] = (sskpd >> 4) & 0xFF;
2179 wm[2] = (sskpd >> 12) & 0xFF;
2180 wm[3] = (sskpd >> 20) & 0x1FF;
2181 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2182 } else if (INTEL_INFO(dev)->gen >= 6) {
2183 uint32_t sskpd = I915_READ(MCH_SSKPD);
2184
2185 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2186 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2187 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2188 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2189 } else if (INTEL_INFO(dev)->gen >= 5) {
2190 uint32_t mltr = I915_READ(MLTR_ILK);
2191
2192 /* ILK primary LP0 latency is 700 ns */
2193 wm[0] = 7;
2194 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2195 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2196 }
2197}
2198
53615a5e
VS		 2199static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2200{
2201 /* ILK sprite LP0 latency is 1300 ns */
2202 if (INTEL_INFO(dev)->gen == 5)
2203 wm[0] = 13;
2204}
2205
2206static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2207{
2208 /* ILK cursor LP0 latency is 1300 ns */
2209 if (INTEL_INFO(dev)->gen == 5)
2210 wm[0] = 13;
2211
2212 /* WaDoubleCursorLP3Latency:ivb */
2213 if (IS_IVYBRIDGE(dev))
2214 wm[3] *= 2;
2215}
2216
546c81fd 2217int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2218{
26ec971e 2219 /* how many WM levels are we expecting */
b6e742f6 2220 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2221 return 7;
2222 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2223 return 4;
26ec971e 2224 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2225 return 3;
26ec971e 2226 else
ad0d6dc4
VS		 2227 return 2;
2228}
7526ed79 2229
ad0d6dc4
VS		 2230static void intel_print_wm_latency(struct drm_device *dev,
2231 const char *name,
2af30a5c 2232 const uint16_t wm[8])
ad0d6dc4
VS		 2233{
2234 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2235
2236 for (level = 0; level <= max_level; level++) {
2237 unsigned int latency = wm[level];
2238
2239 if (latency == 0) {
2240 DRM_ERROR("%s WM%d latency not provided\n",
2241 name, level);
2242 continue;
2243 }
2244
2af30a5c
PB		 2245 /*
2246 * - latencies are in us on gen9.
2247 * - before then, WM1+ latency values are in 0.5us units
2248 */
2249 if (IS_GEN9(dev))
2250 latency *= 10;
2251 else if (level > 0)
26ec971e
VS		 2252 latency *= 5;
2253
2254 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2255 name, level, wm[level],
2256 latency / 10, latency % 10);
2257 }
2258}
2259
e95a2f75
VS		 2260static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2261 uint16_t wm[5], uint16_t min)
2262{
2263 int level, max_level = ilk_wm_max_level(dev_priv->dev);
2264
2265 if (wm[0] >= min)
2266 return false;
2267
2268 wm[0] = max(wm[0], min);
2269 for (level = 1; level <= max_level; level++)
2270 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2271
2272 return true;
2273}
2274
2275static void snb_wm_latency_quirk(struct drm_device *dev)
2276{
2277 struct drm_i915_private *dev_priv = dev->dev_private;
2278 bool changed;
2279
2280 /*
2281 * The BIOS provided WM memory latency values are often
2282 * inadequate for high resolution displays. Adjust them.
2283 */
2284 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2285 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2286 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2287
2288 if (!changed)
2289 return;
2290
2291 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2292 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2293 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2294 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2295}
2296
fa50ad61 2297static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e
VS		 2298{
2299 struct drm_i915_private *dev_priv = dev->dev_private;
2300
2301 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2302
2303 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2304 sizeof(dev_priv->wm.pri_latency));
2305 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2306 sizeof(dev_priv->wm.pri_latency));
2307
2308 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2309 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2310
2311 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2312 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2313 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2314
2315 if (IS_GEN6(dev))
2316 snb_wm_latency_quirk(dev);
53615a5e
VS		 2317}
2318
2af30a5c
PB		 2319static void skl_setup_wm_latency(struct drm_device *dev)
2320{
2321 struct drm_i915_private *dev_priv = dev->dev_private;
2322
2323 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2324 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2325}
2326
820c1980 2327static void ilk_compute_wm_parameters(struct drm_crtc *crtc,
2a44b76b 2328 struct ilk_pipe_wm_parameters *p)
1011d8c4 2329{
7c4a395f
VS		 2330 struct drm_device *dev = crtc->dev;
2331 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2332 enum pipe pipe = intel_crtc->pipe;
7c4a395f 2333 struct drm_plane *plane;
1011d8c4 2334
3ef00284 2335 if (!intel_crtc->active)
2a44b76b 2336 return;
801bcfff 2337
2a44b76b 2338 p->active = true;
6e3c9717 2339 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
8cfb3407 2340 p->pixel_rate = ilk_pipe_pixel_rate(intel_crtc->config);
c9f038a1 2341
54da691d 2342 if (crtc->primary->state->fb)
c9f038a1
MR		 2343 p->pri.bytes_per_pixel =
2344 crtc->primary->state->fb->bits_per_pixel / 8;
54da691d
TG		 2345 else
2346 p->pri.bytes_per_pixel = 4;
2347
2348 p->cur.bytes_per_pixel = 4;
2349 /*
2350 * TODO: for now, assume primary and cursor planes are always enabled.
2351 * Setting them to false makes the screen flicker.
2352 */
2353 p->pri.enabled = true;
2354 p->cur.enabled = true;
c9f038a1 2355
6e3c9717 2356 p->pri.horiz_pixels = intel_crtc->config->pipe_src_w;
3dd512fb 2357 p->cur.horiz_pixels = intel_crtc->base.cursor->state->crtc_w;
7c4a395f 2358
af2b653b 2359 drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) {
801bcfff 2360 struct intel_plane *intel_plane = to_intel_plane(plane);
801bcfff 2361
2a44b76b 2362 if (intel_plane->pipe == pipe) {
7c4a395f 2363 p->spr = intel_plane->wm;
2a44b76b
VS		 2364 break;
2365 }
2366 }
2367}
2368
2369static void ilk_compute_wm_config(struct drm_device *dev,
2370 struct intel_wm_config *config)
2371{
2372 struct intel_crtc *intel_crtc;
2373
2374 /* Compute the currently _active_ config */
d3fcc808 2375 for_each_intel_crtc(dev, intel_crtc) {
2a44b76b 2376 const struct intel_pipe_wm *wm = &intel_crtc->wm.active;
cca32e9a 2377
2a44b76b
VS		 2378 if (!wm->pipe_enabled)
2379 continue;
cca32e9a 2380
2a44b76b
VS		 2381 config->sprites_enabled |= wm->sprites_enabled;
2382 config->sprites_scaled |= wm->sprites_scaled;
2383 config->num_pipes_active++;
cca32e9a 2384 }
801bcfff
PZ		 2385}
2386
0b2ae6d7
VS		 2387/* Compute new watermarks for the pipe */
2388static bool intel_compute_pipe_wm(struct drm_crtc *crtc,
820c1980 2389 const struct ilk_pipe_wm_parameters *params,
0b2ae6d7
VS		 2390 struct intel_pipe_wm *pipe_wm)
2391{
2392 struct drm_device *dev = crtc->dev;
d34ff9c6 2393 const struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7
VS		 2394 int level, max_level = ilk_wm_max_level(dev);
2395 /* LP0 watermark maximums depend on this pipe alone */
2396 struct intel_wm_config config = {
2397 .num_pipes_active = 1,
2398 .sprites_enabled = params->spr.enabled,
2399 .sprites_scaled = params->spr.scaled,
2400 };
820c1980 2401 struct ilk_wm_maximums max;
0b2ae6d7 2402
2a44b76b
VS		 2403 pipe_wm->pipe_enabled = params->active;
2404 pipe_wm->sprites_enabled = params->spr.enabled;
2405 pipe_wm->sprites_scaled = params->spr.scaled;
2406
7b39a0b7
VS		 2407 /* ILK/SNB: LP2+ watermarks only w/o sprites */
2408 if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled)
2409 max_level = 1;
2410
2411 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
2412 if (params->spr.scaled)
2413 max_level = 0;
2414
a3cb4048 2415 ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]);
0b2ae6d7 2416
a42a5719 2417 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 2418 pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc);
0b2ae6d7 2419
a3cb4048
VS		 2420 /* LP0 watermarks always use 1/2 DDB partitioning */
2421 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2422
0b2ae6d7 2423 /* At least LP0 must be valid */
a3cb4048
VS		 2424 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0]))
2425 return false;
2426
2427 ilk_compute_wm_reg_maximums(dev, 1, &max);
2428
2429 for (level = 1; level <= max_level; level++) {
2430 struct intel_wm_level wm = {};
2431
2432 ilk_compute_wm_level(dev_priv, level, params, &wm);
2433
2434 /*
2435 * Disable any watermark level that exceeds the
2436 * register maximums since such watermarks are
2437 * always invalid.
2438 */
2439 if (!ilk_validate_wm_level(level, &max, &wm))
2440 break;
2441
2442 pipe_wm->wm[level] = wm;
2443 }
2444
2445 return true;
0b2ae6d7
VS		 2446}
2447
2448/*
2449 * Merge the watermarks from all active pipes for a specific level.
2450 */
2451static void ilk_merge_wm_level(struct drm_device *dev,
2452 int level,
2453 struct intel_wm_level *ret_wm)
2454{
2455 const struct intel_crtc *intel_crtc;
2456
d52fea5b
VS		 2457 ret_wm->enable = true;
2458
d3fcc808 2459 for_each_intel_crtc(dev, intel_crtc) {
fe392efd
VS		 2460 const struct intel_pipe_wm *active = &intel_crtc->wm.active;
2461 const struct intel_wm_level *wm = &active->wm[level];
2462
2463 if (!active->pipe_enabled)
2464 continue;
0b2ae6d7 2465
d52fea5b
VS		 2466 /*
2467 * The watermark values may have been used in the past,
2468 * so we must maintain them in the registers for some
2469 * time even if the level is now disabled.
2470 */
0b2ae6d7 2471 if (!wm->enable)
d52fea5b 2472 ret_wm->enable = false;
0b2ae6d7
VS		 2473
2474 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2475 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2476 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2477 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2478 }
0b2ae6d7
VS		 2479}
2480
2481/*
2482 * Merge all low power watermarks for all active pipes.
2483 */
2484static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2485 const struct intel_wm_config *config,
820c1980 2486 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2487 struct intel_pipe_wm *merged)
2488{
7733b49b 2489 struct drm_i915_private *dev_priv = dev->dev_private;
0b2ae6d7 2490 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2491 int last_enabled_level = max_level;
0b2ae6d7 2492
0ba22e26
VS		 2493 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2494 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2495 config->num_pipes_active > 1)
2496 return;
2497
6c8b6c28
VS		 2498 /* ILK: FBC WM must be disabled always */
2499 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2500
2501 /* merge each WM1+ level */
2502 for (level = 1; level <= max_level; level++) {
2503 struct intel_wm_level *wm = &merged->wm[level];
2504
2505 ilk_merge_wm_level(dev, level, wm);
2506
d52fea5b
VS		 2507 if (level > last_enabled_level)
2508 wm->enable = false;
2509 else if (!ilk_validate_wm_level(level, max, wm))
2510 /* make sure all following levels get disabled */
2511 last_enabled_level = level - 1;
0b2ae6d7
VS		 2512
2513 /*
2514 * The spec says it is preferred to disable
2515 * FBC WMs instead of disabling a WM level.
2516 */
2517 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2518 if (wm->enable)
2519 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2520 wm->fbc_val = 0;
2521 }
2522 }
6c8b6c28
VS		 2523
2524 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2525 /*
2526 * FIXME this is racy. FBC might get enabled later.
2527 * What we should check here is whether FBC can be
2528 * enabled sometime later.
2529 */
7733b49b
PZ		 2530 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
2531 intel_fbc_enabled(dev_priv)) {
6c8b6c28
VS		 2532 for (level = 2; level <= max_level; level++) {
2533 struct intel_wm_level *wm = &merged->wm[level];
2534
2535 wm->enable = false;
2536 }
2537 }
0b2ae6d7
VS		 2538}
2539
b380ca3c
VS		 2540static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2541{
2542 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2543 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2544}
2545
a68d68ee
VS		 2546/* The value we need to program into the WM_LPx latency field */
2547static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2548{
2549 struct drm_i915_private *dev_priv = dev->dev_private;
2550
a42a5719 2551 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2552 return 2 * level;
2553 else
2554 return dev_priv->wm.pri_latency[level];
2555}
2556
820c1980 2557static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2558 const struct intel_pipe_wm *merged,
609cedef 2559 enum intel_ddb_partitioning partitioning,
820c1980 2560 struct ilk_wm_values *results)
801bcfff 2561{
0b2ae6d7
VS		 2562 struct intel_crtc *intel_crtc;
2563 int level, wm_lp;
cca32e9a 2564
0362c781 2565 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2566 results->partitioning = partitioning;
cca32e9a 2567
0b2ae6d7 2568 /* LP1+ register values */
cca32e9a 2569 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2570 const struct intel_wm_level *r;
801bcfff 2571
b380ca3c 2572 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2573
0362c781 2574 r = &merged->wm[level];
cca32e9a 2575
d52fea5b
VS		 2576 /*
2577 * Maintain the watermark values even if the level is
2578 * disabled. Doing otherwise could cause underruns.
2579 */
2580 results->wm_lp[wm_lp - 1] =
a68d68ee 2581 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2582 (r->pri_val << WM1_LP_SR_SHIFT) |
2583 r->cur_val;
2584
d52fea5b
VS		 2585 if (r->enable)
2586 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2587
416f4727
VS		 2588 if (INTEL_INFO(dev)->gen >= 8)
2589 results->wm_lp[wm_lp - 1] |=
2590 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2591 else
2592 results->wm_lp[wm_lp - 1] |=
2593 r->fbc_val << WM1_LP_FBC_SHIFT;
2594
d52fea5b
VS		 2595 /*
2596 * Always set WM1S_LP_EN when spr_val != 0, even if the
2597 * level is disabled. Doing otherwise could cause underruns.
2598 */
6cef2b8a
VS		 2599 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2600 WARN_ON(wm_lp != 1);
2601 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2602 } else
2603 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2604 }
801bcfff 2605
0b2ae6d7 2606 /* LP0 register values */
d3fcc808 2607 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7
VS		 2608 enum pipe pipe = intel_crtc->pipe;
2609 const struct intel_wm_level *r =
2610 &intel_crtc->wm.active.wm[0];
2611
2612 if (WARN_ON(!r->enable))
2613 continue;
2614
2615 results->wm_linetime[pipe] = intel_crtc->wm.active.linetime;
1011d8c4 2616
0b2ae6d7
VS		 2617 results->wm_pipe[pipe] =
2618 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2619 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2620 r->cur_val;
801bcfff
PZ		 2621 }
2622}
2623
861f3389
PZ		 2624/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2625 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2626static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2627 struct intel_pipe_wm *r1,
2628 struct intel_pipe_wm *r2)
861f3389 2629{
198a1e9b
VS		 2630 int level, max_level = ilk_wm_max_level(dev);
2631 int level1 = 0, level2 = 0;
861f3389 2632
198a1e9b
VS		 2633 for (level = 1; level <= max_level; level++) {
2634 if (r1->wm[level].enable)
2635 level1 = level;
2636 if (r2->wm[level].enable)
2637 level2 = level;
861f3389
PZ		 2638 }
2639
198a1e9b
VS		 2640 if (level1 == level2) {
2641 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2642 return r2;
2643 else
2644 return r1;
198a1e9b 2645 } else if (level1 > level2) {
861f3389
PZ		 2646 return r1;
2647 } else {
2648 return r2;
2649 }
2650}
2651
49a687c4
VS		 2652/* dirty bits used to track which watermarks need changes */
2653#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2654#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2655#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2656#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2657#define WM_DIRTY_FBC (1 << 24)
2658#define WM_DIRTY_DDB (1 << 25)
2659
055e393f 2660static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2661 const struct ilk_wm_values *old,
2662 const struct ilk_wm_values *new)
49a687c4
VS		 2663{
2664 unsigned int dirty = 0;
2665 enum pipe pipe;
2666 int wm_lp;
2667
055e393f 2668 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2669 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2670 dirty |= WM_DIRTY_LINETIME(pipe);
2671 /* Must disable LP1+ watermarks too */
2672 dirty |= WM_DIRTY_LP_ALL;
2673 }
2674
2675 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2676 dirty |= WM_DIRTY_PIPE(pipe);
2677 /* Must disable LP1+ watermarks too */
2678 dirty |= WM_DIRTY_LP_ALL;
2679 }
2680 }
2681
2682 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2683 dirty |= WM_DIRTY_FBC;
2684 /* Must disable LP1+ watermarks too */
2685 dirty |= WM_DIRTY_LP_ALL;
2686 }
2687
2688 if (old->partitioning != new->partitioning) {
2689 dirty |= WM_DIRTY_DDB;
2690 /* Must disable LP1+ watermarks too */
2691 dirty |= WM_DIRTY_LP_ALL;
2692 }
2693
2694 /* LP1+ watermarks already deemed dirty, no need to continue */
2695 if (dirty & WM_DIRTY_LP_ALL)
2696 return dirty;
2697
2698 /* Find the lowest numbered LP1+ watermark in need of an update... */
2699 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2700 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2701 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2702 break;
2703 }
2704
2705 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2706 for (; wm_lp <= 3; wm_lp++)
2707 dirty |= WM_DIRTY_LP(wm_lp);
2708
2709 return dirty;
2710}
2711
8553c18e
VS		 2712static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2713 unsigned int dirty)
801bcfff 2714{
820c1980 2715 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2716 bool changed = false;
801bcfff 2717
facd619b
VS		 2718 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2719 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2720 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2721 changed = true;
facd619b
VS		 2722 }
2723 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2724 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2725 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2726 changed = true;
facd619b
VS		 2727 }
2728 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2729 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2730 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2731 changed = true;
facd619b 2732 }
801bcfff 2733
facd619b
VS		 2734 /*
2735 * Don't touch WM1S_LP_EN here.
2736 * Doing so could cause underruns.
2737 */
6cef2b8a 2738
8553c18e
VS		 2739 return changed;
2740}
2741
2742/*
2743 * The spec says we shouldn't write when we don't need, because every write
2744 * causes WMs to be re-evaluated, expending some power.
2745 */
820c1980
ID		 2746static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2747 struct ilk_wm_values *results)
8553c18e
VS		 2748{
2749 struct drm_device *dev = dev_priv->dev;
820c1980 2750 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2751 unsigned int dirty;
2752 uint32_t val;
2753
055e393f 2754 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2755 if (!dirty)
2756 return;
2757
2758 _ilk_disable_lp_wm(dev_priv, dirty);
2759
49a687c4 2760 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2761 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2762 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2763 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2764 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2765 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2766
49a687c4 2767 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2768 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2769 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2770 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2771 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2772 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2773
49a687c4 2774 if (dirty & WM_DIRTY_DDB) {
a42a5719 2775 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2776 val = I915_READ(WM_MISC);
2777 if (results->partitioning == INTEL_DDB_PART_1_2)
2778 val &= ~WM_MISC_DATA_PARTITION_5_6;
2779 else
2780 val |= WM_MISC_DATA_PARTITION_5_6;
2781 I915_WRITE(WM_MISC, val);
2782 } else {
2783 val = I915_READ(DISP_ARB_CTL2);
2784 if (results->partitioning == INTEL_DDB_PART_1_2)
2785 val &= ~DISP_DATA_PARTITION_5_6;
2786 else
2787 val |= DISP_DATA_PARTITION_5_6;
2788 I915_WRITE(DISP_ARB_CTL2, val);
2789 }
1011d8c4
PZ		 2790 }
2791
49a687c4 2792 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2793 val = I915_READ(DISP_ARB_CTL);
2794 if (results->enable_fbc_wm)
2795 val &= ~DISP_FBC_WM_DIS;
2796 else
2797 val |= DISP_FBC_WM_DIS;
2798 I915_WRITE(DISP_ARB_CTL, val);
2799 }
2800
954911eb
ID		 2801 if (dirty & WM_DIRTY_LP(1) &&
2802 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2803 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2804
2805 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2806 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2807 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2808 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2809 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2810 }
801bcfff 2811
facd619b 2812 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2813 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2814 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2815 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2816 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2817 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2818
2819 dev_priv->wm.hw = *results;
801bcfff
PZ		 2820}
2821
8553c18e
VS		 2822static bool ilk_disable_lp_wm(struct drm_device *dev)
2823{
2824 struct drm_i915_private *dev_priv = dev->dev_private;
2825
2826 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2827}
2828
b9cec075
DL		 2829/*
2830 * On gen9, we need to allocate Display Data Buffer (DDB) portions to the
2831 * different active planes.
2832 */
2833
2834#define SKL_DDB_SIZE 896 /* in blocks */
43d735a6 2835#define BXT_DDB_SIZE 512
b9cec075
DL		 2836
2837static void
2838skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
2839 struct drm_crtc *for_crtc,
2840 const struct intel_wm_config *config,
2841 const struct skl_pipe_wm_parameters *params,
2842 struct skl_ddb_entry *alloc /* out */)
2843{
2844 struct drm_crtc *crtc;
2845 unsigned int pipe_size, ddb_size;
2846 int nth_active_pipe;
2847
2848 if (!params->active) {
2849 alloc->start = 0;
2850 alloc->end = 0;
2851 return;
2852 }
2853
43d735a6
DL		 2854 if (IS_BROXTON(dev))
2855 ddb_size = BXT_DDB_SIZE;
2856 else
2857 ddb_size = SKL_DDB_SIZE;
b9cec075
DL		 2858
2859 ddb_size -= 4; /* 4 blocks for bypass path allocation */
2860
2861 nth_active_pipe = 0;
2862 for_each_crtc(dev, crtc) {
3ef00284 2863 if (!to_intel_crtc(crtc)->active)
b9cec075
DL		 2864 continue;
2865
2866 if (crtc == for_crtc)
2867 break;
2868
2869 nth_active_pipe++;
2870 }
2871
2872 pipe_size = ddb_size / config->num_pipes_active;
2873 alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active;
16160e3d 2874 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 2875}
2876
2877static unsigned int skl_cursor_allocation(const struct intel_wm_config *config)
2878{
2879 if (config->num_pipes_active == 1)
2880 return 32;
2881
2882 return 8;
2883}
2884
a269c583
DL		 2885static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
2886{
2887 entry->start = reg & 0x3ff;
2888 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 2889 if (entry->end)
2890 entry->end += 1;
a269c583
DL		 2891}
2892
08db6652
DL		 2893void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
2894 struct skl_ddb_allocation *ddb /* out */)
a269c583 2895{
a269c583
DL		 2896 enum pipe pipe;
2897 int plane;
2898 u32 val;
2899
2900 for_each_pipe(dev_priv, pipe) {
dd740780 2901 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 2902 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
2903 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
2904 val);
2905 }
2906
2907 val = I915_READ(CUR_BUF_CFG(pipe));
2908 skl_ddb_entry_init_from_hw(&ddb->cursor[pipe], val);
2909 }
2910}
2911
b9cec075 2912static unsigned int
2cd601c6 2913skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p, int y)
b9cec075 2914{
2cd601c6
CK		 2915
2916 /* for planar format */
2917 if (p->y_bytes_per_pixel) {
2918 if (y) /* y-plane data rate */
2919 return p->horiz_pixels * p->vert_pixels * p->y_bytes_per_pixel;
2920 else /* uv-plane data rate */
2921 return (p->horiz_pixels/2) * (p->vert_pixels/2) * p->bytes_per_pixel;
2922 }
2923
2924 /* for packed formats */
b9cec075
DL		 2925 return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel;
2926}
2927
2928/*
2929 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
2930 * a 8192x4096@32bpp framebuffer:
2931 * 3 * 4096 * 8192 * 4 < 2^32
2932 */
2933static unsigned int
2934skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc,
2935 const struct skl_pipe_wm_parameters *params)
2936{
2937 unsigned int total_data_rate = 0;
2938 int plane;
2939
2940 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
2941 const struct intel_plane_wm_parameters *p;
2942
2943 p = &params->plane[plane];
2944 if (!p->enabled)
2945 continue;
2946
2cd601c6
CK		 2947 total_data_rate += skl_plane_relative_data_rate(p, 0); /* packed/uv */
2948 if (p->y_bytes_per_pixel) {
2949 total_data_rate += skl_plane_relative_data_rate(p, 1); /* y-plane */
2950 }
b9cec075
DL		 2951 }
2952
2953 return total_data_rate;
2954}
2955
2956static void
2957skl_allocate_pipe_ddb(struct drm_crtc *crtc,
2958 const struct intel_wm_config *config,
2959 const struct skl_pipe_wm_parameters *params,
2960 struct skl_ddb_allocation *ddb /* out */)
2961{
2962 struct drm_device *dev = crtc->dev;
dd740780 2963 struct drm_i915_private *dev_priv = dev->dev_private;
b9cec075
DL		 2964 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2965 enum pipe pipe = intel_crtc->pipe;
34bb56af 2966 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 2967 uint16_t alloc_size, start, cursor_blocks;
80958155 2968 uint16_t minimum[I915_MAX_PLANES];
2cd601c6 2969 uint16_t y_minimum[I915_MAX_PLANES];
b9cec075
DL		 2970 unsigned int total_data_rate;
2971 int plane;
2972
34bb56af
DL		 2973 skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, alloc);
2974 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 2975 if (alloc_size == 0) {
2976 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
2977 memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe]));
2978 return;
2979 }
2980
2981 cursor_blocks = skl_cursor_allocation(config);
34bb56af
DL		 2982 ddb->cursor[pipe].start = alloc->end - cursor_blocks;
2983 ddb->cursor[pipe].end = alloc->end;
b9cec075
DL		 2984
2985 alloc_size -= cursor_blocks;
34bb56af 2986 alloc->end -= cursor_blocks;
b9cec075 2987
80958155 2988 /* 1. Allocate the mininum required blocks for each active plane */
dd740780 2989 for_each_plane(dev_priv, pipe, plane) {
80958155
DL		 2990 const struct intel_plane_wm_parameters *p;
2991
2992 p = &params->plane[plane];
2993 if (!p->enabled)
2994 continue;
2995
2996 minimum[plane] = 8;
2997 alloc_size -= minimum[plane];
2cd601c6
CK		 2998 y_minimum[plane] = p->y_bytes_per_pixel ? 8 : 0;
2999 alloc_size -= y_minimum[plane];
80958155
DL		 3000 }
3001
b9cec075 3002 /*
80958155
DL		 3003 * 2. Distribute the remaining space in proportion to the amount of
3004 * data each plane needs to fetch from memory.
b9cec075
DL		 3005 *
3006 * FIXME: we may not allocate every single block here.
3007 */
3008 total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params);
3009
34bb56af 3010 start = alloc->start;
b9cec075
DL		 3011 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) {
3012 const struct intel_plane_wm_parameters *p;
2cd601c6
CK		 3013 unsigned int data_rate, y_data_rate;
3014 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075
DL		 3015
3016 p = &params->plane[plane];
3017 if (!p->enabled)
3018 continue;
3019
2cd601c6 3020 data_rate = skl_plane_relative_data_rate(p, 0);
b9cec075
DL		 3021
3022 /*
2cd601c6 3023 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3024 * promote the expression to 64 bits to avoid overflowing, the
3025 * result is < available as data_rate / total_data_rate < 1
3026 */
80958155
DL		 3027 plane_blocks = minimum[plane];
3028 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3029 total_data_rate);
b9cec075
DL		 3030
3031 ddb->plane[pipe][plane].start = start;
16160e3d 3032 ddb->plane[pipe][plane].end = start + plane_blocks;
b9cec075
DL		 3033
3034 start += plane_blocks;
2cd601c6
CK		 3035
3036 /*
3037 * allocation for y_plane part of planar format:
3038 */
3039 if (p->y_bytes_per_pixel) {
3040 y_data_rate = skl_plane_relative_data_rate(p, 1);
3041 y_plane_blocks = y_minimum[plane];
3042 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3043 total_data_rate);
3044
3045 ddb->y_plane[pipe][plane].start = start;
3046 ddb->y_plane[pipe][plane].end = start + y_plane_blocks;
3047
3048 start += y_plane_blocks;
3049 }
3050
b9cec075
DL		 3051 }
3052
3053}
3054
5cec258b 3055static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3056{
3057 /* TODO: Take into account the scalers once we support them */
2d112de7 3058 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3059}
3060
3061/*
3062 * The max latency should be 257 (max the punit can code is 255 and we add 2us
3063 * for the read latency) and bytes_per_pixel should always be <= 8, so that
3064 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3065 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3066*/
3067static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
3068 uint32_t latency)
3069{
3070 uint32_t wm_intermediate_val, ret;
3071
3072 if (latency == 0)
3073 return UINT_MAX;
3074
d4c2aa60 3075 wm_intermediate_val = latency * pixel_rate * bytes_per_pixel / 512;
2d41c0b5
PB		 3076 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3077
3078 return ret;
3079}
3080
3081static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
3082 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
0fda6568 3083 uint64_t tiling, uint32_t latency)
2d41c0b5 3084{
d4c2aa60
TU		 3085 uint32_t ret;
3086 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3087 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3088
3089 if (latency == 0)
3090 return UINT_MAX;
3091
3092 plane_bytes_per_line = horiz_pixels * bytes_per_pixel;
0fda6568
TU		 3093
3094 if (tiling == I915_FORMAT_MOD_Y_TILED ||
3095 tiling == I915_FORMAT_MOD_Yf_TILED) {
3096 plane_bytes_per_line *= 4;
3097 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3098 plane_blocks_per_line /= 4;
3099 } else {
3100 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3101 }
3102
2d41c0b5
PB		 3103 wm_intermediate_val = latency * pixel_rate;
3104 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3105 plane_blocks_per_line;
2d41c0b5
PB		 3106
3107 return ret;
3108}
3109
2d41c0b5
PB		 3110static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb,
3111 const struct intel_crtc *intel_crtc)
3112{
3113 struct drm_device *dev = intel_crtc->base.dev;
3114 struct drm_i915_private *dev_priv = dev->dev_private;
3115 const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3116 enum pipe pipe = intel_crtc->pipe;
3117
3118 if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe],
3119 sizeof(new_ddb->plane[pipe])))
3120 return true;
3121
3122 if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe],
3123 sizeof(new_ddb->cursor[pipe])))
3124 return true;
3125
3126 return false;
3127}
3128
3129static void skl_compute_wm_global_parameters(struct drm_device *dev,
3130 struct intel_wm_config *config)
3131{
3132 struct drm_crtc *crtc;
3133 struct drm_plane *plane;
3134
3135 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3ef00284 3136 config->num_pipes_active += to_intel_crtc(crtc)->active;
2d41c0b5
PB		 3137
3138 /* FIXME: I don't think we need those two global parameters on SKL */
3139 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3140 struct intel_plane *intel_plane = to_intel_plane(plane);
3141
3142 config->sprites_enabled |= intel_plane->wm.enabled;
3143 config->sprites_scaled |= intel_plane->wm.scaled;
3144 }
3145}
3146
3147static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc,
3148 struct skl_pipe_wm_parameters *p)
3149{
3150 struct drm_device *dev = crtc->dev;
3151 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3152 enum pipe pipe = intel_crtc->pipe;
3153 struct drm_plane *plane;
0fda6568 3154 struct drm_framebuffer *fb;
2d41c0b5
PB		 3155 int i = 1; /* Index for sprite planes start */
3156
3ef00284 3157 p->active = intel_crtc->active;
2d41c0b5 3158 if (p->active) {
6e3c9717
ACO		 3159 p->pipe_htotal = intel_crtc->config->base.adjusted_mode.crtc_htotal;
3160 p->pixel_rate = skl_pipe_pixel_rate(intel_crtc->config);
2d41c0b5 3161
0fda6568 3162 fb = crtc->primary->state->fb;
2cd601c6 3163 /* For planar: Bpp is for uv plane, y_Bpp is for y plane */
c9f038a1
MR		 3164 if (fb) {
3165 p->plane[0].enabled = true;
2cd601c6
CK		 3166 p->plane[0].bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3167 drm_format_plane_cpp(fb->pixel_format, 1) : fb->bits_per_pixel / 8;
3168 p->plane[0].y_bytes_per_pixel = fb->pixel_format == DRM_FORMAT_NV12 ?
3169 drm_format_plane_cpp(fb->pixel_format, 0) : 0;
0fda6568 3170 p->plane[0].tiling = fb->modifier[0];
c9f038a1
MR		 3171 } else {
3172 p->plane[0].enabled = false;
3173 p->plane[0].bytes_per_pixel = 0;
2cd601c6 3174 p->plane[0].y_bytes_per_pixel = 0;
c9f038a1
MR		 3175 p->plane[0].tiling = DRM_FORMAT_MOD_NONE;
3176 }
3177 p->plane[0].horiz_pixels = intel_crtc->config->pipe_src_w;
3178 p->plane[0].vert_pixels = intel_crtc->config->pipe_src_h;
1fc0a8f7 3179 p->plane[0].rotation = crtc->primary->state->rotation;
2d41c0b5 3180
c9f038a1 3181 fb = crtc->cursor->state->fb;
2cd601c6 3182 p->cursor.y_bytes_per_pixel = 0;
c9f038a1
MR		 3183 if (fb) {
3184 p->cursor.enabled = true;
3185 p->cursor.bytes_per_pixel = fb->bits_per_pixel / 8;
3186 p->cursor.horiz_pixels = crtc->cursor->state->crtc_w;
3187 p->cursor.vert_pixels = crtc->cursor->state->crtc_h;
3188 } else {
3189 p->cursor.enabled = false;
3190 p->cursor.bytes_per_pixel = 0;
3191 p->cursor.horiz_pixels = 64;
3192 p->cursor.vert_pixels = 64;
3193 }
2d41c0b5
PB		 3194 }
3195
3196 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
3197 struct intel_plane *intel_plane = to_intel_plane(plane);
3198
a712f8eb
SJ		 3199 if (intel_plane->pipe == pipe &&
3200 plane->type == DRM_PLANE_TYPE_OVERLAY)
2d41c0b5
PB		 3201 p->plane[i++] = intel_plane->wm;
3202 }
3203}
3204
d4c2aa60
TU		 3205static bool skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3206 struct skl_pipe_wm_parameters *p,
afb024aa
DL		 3207 struct intel_plane_wm_parameters *p_params,
3208 uint16_t ddb_allocation,
d4c2aa60 3209 int level,
afb024aa
DL		 3210 uint16_t *out_blocks, /* out */
3211 uint8_t *out_lines /* out */)
2d41c0b5 3212{
d4c2aa60
TU		 3213 uint32_t latency = dev_priv->wm.skl_latency[level];
3214 uint32_t method1, method2;
3215 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3216 uint32_t res_blocks, res_lines;
3217 uint32_t selected_result;
2cd601c6 3218 uint8_t bytes_per_pixel;
2d41c0b5 3219
d4c2aa60 3220 if (latency == 0 || !p->active || !p_params->enabled)
2d41c0b5
PB		 3221 return false;
3222
2cd601c6
CK		 3223 bytes_per_pixel = p_params->y_bytes_per_pixel ?
3224 p_params->y_bytes_per_pixel :
3225 p_params->bytes_per_pixel;
2d41c0b5 3226 method1 = skl_wm_method1(p->pixel_rate,
2cd601c6 3227 bytes_per_pixel,
d4c2aa60 3228 latency);
2d41c0b5
PB		 3229 method2 = skl_wm_method2(p->pixel_rate,
3230 p->pipe_htotal,
3231 p_params->horiz_pixels,
2cd601c6 3232 bytes_per_pixel,
0fda6568 3233 p_params->tiling,
d4c2aa60 3234 latency);
2d41c0b5 3235
2cd601c6 3236 plane_bytes_per_line = p_params->horiz_pixels * bytes_per_pixel;
d4c2aa60 3237 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
2d41c0b5 3238
0fda6568
TU		 3239 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3240 p_params->tiling == I915_FORMAT_MOD_Yf_TILED) {
1fc0a8f7
TU		 3241 uint32_t min_scanlines = 4;
3242 uint32_t y_tile_minimum;
3243 if (intel_rotation_90_or_270(p_params->rotation)) {
3244 switch (p_params->bytes_per_pixel) {
3245 case 1:
3246 min_scanlines = 16;
3247 break;
3248 case 2:
3249 min_scanlines = 8;
3250 break;
3251 case 8:
3252 WARN(1, "Unsupported pixel depth for rotation");
2f0b5790 3253 }
1fc0a8f7
TU		 3254 }
3255 y_tile_minimum = plane_blocks_per_line * min_scanlines;
0fda6568
TU		 3256 selected_result = max(method2, y_tile_minimum);
3257 } else {
3258 if ((ddb_allocation / plane_blocks_per_line) >= 1)
3259 selected_result = min(method1, method2);
3260 else
3261 selected_result = method1;
3262 }
2d41c0b5 3263
d4c2aa60
TU		 3264 res_blocks = selected_result + 1;
3265 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3266
0fda6568
TU		 3267 if (level >= 1 && level <= 7) {
3268 if (p_params->tiling == I915_FORMAT_MOD_Y_TILED ||
3269 p_params->tiling == I915_FORMAT_MOD_Yf_TILED)
3270 res_lines += 4;
3271 else
3272 res_blocks++;
3273 }
e6d66171 3274
d4c2aa60 3275 if (res_blocks >= ddb_allocation || res_lines > 31)
e6d66171
DL		 3276 return false;
3277
3278 *out_blocks = res_blocks;
3279 *out_lines = res_lines;
2d41c0b5
PB		 3280
3281 return true;
3282}
3283
3284static void skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3285 struct skl_ddb_allocation *ddb,
3286 struct skl_pipe_wm_parameters *p,
3287 enum pipe pipe,
3288 int level,
3289 int num_planes,
3290 struct skl_wm_level *result)
3291{
2d41c0b5
PB		 3292 uint16_t ddb_blocks;
3293 int i;
3294
3295 for (i = 0; i < num_planes; i++) {
3296 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3297
d4c2aa60
TU		 3298 result->plane_en[i] = skl_compute_plane_wm(dev_priv,
3299 p, &p->plane[i],
2d41c0b5 3300 ddb_blocks,
d4c2aa60 3301 level,
2d41c0b5
PB		 3302 &result->plane_res_b[i],
3303 &result->plane_res_l[i]);
3304 }
3305
3306 ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]);
d4c2aa60
TU		 3307 result->cursor_en = skl_compute_plane_wm(dev_priv, p, &p->cursor,
3308 ddb_blocks, level,
3309 &result->cursor_res_b,
2d41c0b5
PB		 3310 &result->cursor_res_l);
3311}
3312
407b50f3
DL		 3313static uint32_t
3314skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p)
3315{
3ef00284 3316 if (!to_intel_crtc(crtc)->active)
407b50f3
DL		 3317 return 0;
3318
3319 return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate);
3320
3321}
3322
3323static void skl_compute_transition_wm(struct drm_crtc *crtc,
3324 struct skl_pipe_wm_parameters *params,
9414f563 3325 struct skl_wm_level *trans_wm /* out */)
407b50f3 3326{
9414f563
DL		 3327 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3328 int i;
3329
407b50f3
DL		 3330 if (!params->active)
3331 return;
9414f563
DL		 3332
3333 /* Until we know more, just disable transition WMs */
3334 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3335 trans_wm->plane_en[i] = false;
3336 trans_wm->cursor_en = false;
407b50f3
DL		 3337}
3338
2d41c0b5
PB		 3339static void skl_compute_pipe_wm(struct drm_crtc *crtc,
3340 struct skl_ddb_allocation *ddb,
3341 struct skl_pipe_wm_parameters *params,
3342 struct skl_pipe_wm *pipe_wm)
3343{
3344 struct drm_device *dev = crtc->dev;
3345 const struct drm_i915_private *dev_priv = dev->dev_private;
3346 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3347 int level, max_level = ilk_wm_max_level(dev);
3348
3349 for (level = 0; level <= max_level; level++) {
3350 skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe,
3351 level, intel_num_planes(intel_crtc),
3352 &pipe_wm->wm[level]);
3353 }
3354 pipe_wm->linetime = skl_compute_linetime_wm(crtc, params);
3355
9414f563 3356 skl_compute_transition_wm(crtc, params, &pipe_wm->trans_wm);
2d41c0b5
PB		 3357}
3358
3359static void skl_compute_wm_results(struct drm_device *dev,
3360 struct skl_pipe_wm_parameters *p,
3361 struct skl_pipe_wm *p_wm,
3362 struct skl_wm_values *r,
3363 struct intel_crtc *intel_crtc)
3364{
3365 int level, max_level = ilk_wm_max_level(dev);
3366 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3367 uint32_t temp;
3368 int i;
2d41c0b5
PB		 3369
3370 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3371 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3372 temp = 0;
2d41c0b5
PB		 3373
3374 temp |= p_wm->wm[level].plane_res_l[i] <<
3375 PLANE_WM_LINES_SHIFT;
3376 temp |= p_wm->wm[level].plane_res_b[i];
3377 if (p_wm->wm[level].plane_en[i])
3378 temp |= PLANE_WM_EN;
3379
3380 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3381 }
3382
3383 temp = 0;
2d41c0b5
PB		 3384
3385 temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT;
3386 temp |= p_wm->wm[level].cursor_res_b;
3387
3388 if (p_wm->wm[level].cursor_en)
3389 temp |= PLANE_WM_EN;
3390
3391 r->cursor[pipe][level] = temp;
2d41c0b5
PB		 3392
3393 }
3394
9414f563
DL		 3395 /* transition WMs */
3396 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3397 temp = 0;
3398 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3399 temp |= p_wm->trans_wm.plane_res_b[i];
3400 if (p_wm->trans_wm.plane_en[i])
3401 temp |= PLANE_WM_EN;
3402
3403 r->plane_trans[pipe][i] = temp;
3404 }
3405
3406 temp = 0;
3407 temp |= p_wm->trans_wm.cursor_res_l << PLANE_WM_LINES_SHIFT;
3408 temp |= p_wm->trans_wm.cursor_res_b;
3409 if (p_wm->trans_wm.cursor_en)
3410 temp |= PLANE_WM_EN;
3411
3412 r->cursor_trans[pipe] = temp;
3413
2d41c0b5
PB		 3414 r->wm_linetime[pipe] = p_wm->linetime;
3415}
3416
16160e3d
DL		 3417static void skl_ddb_entry_write(struct drm_i915_private *dev_priv, uint32_t reg,
3418 const struct skl_ddb_entry *entry)
3419{
3420 if (entry->end)
3421 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3422 else
3423 I915_WRITE(reg, 0);
3424}
3425
2d41c0b5
PB		 3426static void skl_write_wm_values(struct drm_i915_private *dev_priv,
3427 const struct skl_wm_values *new)
3428{
3429 struct drm_device *dev = dev_priv->dev;
3430 struct intel_crtc *crtc;
3431
3432 list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) {
3433 int i, level, max_level = ilk_wm_max_level(dev);
3434 enum pipe pipe = crtc->pipe;
3435
5d374d96
DL		 3436 if (!new->dirty[pipe])
3437 continue;
8211bd5b 3438
5d374d96 3439 I915_WRITE(PIPE_WM_LINETIME(pipe), new->wm_linetime[pipe]);
8211bd5b 3440
5d374d96
DL		 3441 for (level = 0; level <= max_level; level++) {
3442 for (i = 0; i < intel_num_planes(crtc); i++)
3443 I915_WRITE(PLANE_WM(pipe, i, level),
3444 new->plane[pipe][i][level]);
3445 I915_WRITE(CUR_WM(pipe, level),
3446 new->cursor[pipe][level]);
2d41c0b5 3447 }
5d374d96
DL		 3448 for (i = 0; i < intel_num_planes(crtc); i++)
3449 I915_WRITE(PLANE_WM_TRANS(pipe, i),
3450 new->plane_trans[pipe][i]);
3451 I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]);
3452
2cd601c6 3453 for (i = 0; i < intel_num_planes(crtc); i++) {
5d374d96
DL		 3454 skl_ddb_entry_write(dev_priv,
3455 PLANE_BUF_CFG(pipe, i),
3456 &new->ddb.plane[pipe][i]);
2cd601c6
CK		 3457 skl_ddb_entry_write(dev_priv,
3458 PLANE_NV12_BUF_CFG(pipe, i),
3459 &new->ddb.y_plane[pipe][i]);
3460 }
5d374d96
DL		 3461
3462 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3463 &new->ddb.cursor[pipe]);
2d41c0b5 3464 }
2d41c0b5
PB		 3465}
3466
0e8fb7ba
DL		 3467/*
3468 * When setting up a new DDB allocation arrangement, we need to correctly
3469 * sequence the times at which the new allocations for the pipes are taken into
3470 * account or we'll have pipes fetching from space previously allocated to
3471 * another pipe.
3472 *
3473 * Roughly the sequence looks like:
3474 * 1. re-allocate the pipe(s) with the allocation being reduced and not
3475 * overlapping with a previous light-up pipe (another way to put it is:
3476 * pipes with their new allocation strickly included into their old ones).
3477 * 2. re-allocate the other pipes that get their allocation reduced
3478 * 3. allocate the pipes having their allocation increased
3479 *
3480 * Steps 1. and 2. are here to take care of the following case:
3481 * - Initially DDB looks like this:
3482 * | B | C |
3483 * - enable pipe A.
3484 * - pipe B has a reduced DDB allocation that overlaps with the old pipe C
3485 * allocation
3486 * | A | B | C |
3487 *
3488 * We need to sequence the re-allocation: C, B, A (and not B, C, A).
3489 */
3490
d21b795c
DL		 3491static void
3492skl_wm_flush_pipe(struct drm_i915_private *dev_priv, enum pipe pipe, int pass)
0e8fb7ba 3493{
0e8fb7ba
DL		 3494 int plane;
3495
d21b795c
DL		 3496 DRM_DEBUG_KMS("flush pipe %c (pass %d)\n", pipe_name(pipe), pass);
3497
dd740780 3498 for_each_plane(dev_priv, pipe, plane) {
0e8fb7ba
DL		 3499 I915_WRITE(PLANE_SURF(pipe, plane),
3500 I915_READ(PLANE_SURF(pipe, plane)));
3501 }
3502 I915_WRITE(CURBASE(pipe), I915_READ(CURBASE(pipe)));
3503}
3504
3505static bool
3506skl_ddb_allocation_included(const struct skl_ddb_allocation *old,
3507 const struct skl_ddb_allocation *new,
3508 enum pipe pipe)
3509{
3510 uint16_t old_size, new_size;
3511
3512 old_size = skl_ddb_entry_size(&old->pipe[pipe]);
3513 new_size = skl_ddb_entry_size(&new->pipe[pipe]);
3514
3515 return old_size != new_size &&
3516 new->pipe[pipe].start >= old->pipe[pipe].start &&
3517 new->pipe[pipe].end <= old->pipe[pipe].end;
3518}
3519
3520static void skl_flush_wm_values(struct drm_i915_private *dev_priv,
3521 struct skl_wm_values *new_values)
3522{
3523 struct drm_device *dev = dev_priv->dev;
3524 struct skl_ddb_allocation *cur_ddb, *new_ddb;
c929cb45 3525 bool reallocated[I915_MAX_PIPES] = {};
0e8fb7ba
DL		 3526 struct intel_crtc *crtc;
3527 enum pipe pipe;
3528
3529 new_ddb = &new_values->ddb;
3530 cur_ddb = &dev_priv->wm.skl_hw.ddb;
3531
3532 /*
3533 * First pass: flush the pipes with the new allocation contained into
3534 * the old space.
3535 *
3536 * We'll wait for the vblank on those pipes to ensure we can safely
3537 * re-allocate the freed space without this pipe fetching from it.
3538 */
3539 for_each_intel_crtc(dev, crtc) {
3540 if (!crtc->active)
3541 continue;
3542
3543 pipe = crtc->pipe;
3544
3545 if (!skl_ddb_allocation_included(cur_ddb, new_ddb, pipe))
3546 continue;
3547
d21b795c 3548 skl_wm_flush_pipe(dev_priv, pipe, 1);
0e8fb7ba
DL		 3549 intel_wait_for_vblank(dev, pipe);
3550
3551 reallocated[pipe] = true;
3552 }
3553
3554
3555 /*
3556 * Second pass: flush the pipes that are having their allocation
3557 * reduced, but overlapping with a previous allocation.
3558 *
3559 * Here as well we need to wait for the vblank to make sure the freed
3560 * space is not used anymore.
3561 */
3562 for_each_intel_crtc(dev, crtc) {
3563 if (!crtc->active)
3564 continue;
3565
3566 pipe = crtc->pipe;
3567
3568 if (reallocated[pipe])
3569 continue;
3570
3571 if (skl_ddb_entry_size(&new_ddb->pipe[pipe]) <
3572 skl_ddb_entry_size(&cur_ddb->pipe[pipe])) {
d21b795c 3573 skl_wm_flush_pipe(dev_priv, pipe, 2);
0e8fb7ba 3574 intel_wait_for_vblank(dev, pipe);
d9d8e6b3 3575 reallocated[pipe] = true;
0e8fb7ba 3576 }
0e8fb7ba
DL		 3577 }
3578
3579 /*
3580 * Third pass: flush the pipes that got more space allocated.
3581 *
3582 * We don't need to actively wait for the update here, next vblank
3583 * will just get more DDB space with the correct WM values.
3584 */
3585 for_each_intel_crtc(dev, crtc) {
3586 if (!crtc->active)
3587 continue;
3588
3589 pipe = crtc->pipe;
3590
3591 /*
3592 * At this point, only the pipes more space than before are
3593 * left to re-allocate.
3594 */
3595 if (reallocated[pipe])
3596 continue;
3597
d21b795c 3598 skl_wm_flush_pipe(dev_priv, pipe, 3);
0e8fb7ba
DL		 3599 }
3600}
3601
2d41c0b5
PB		 3602static bool skl_update_pipe_wm(struct drm_crtc *crtc,
3603 struct skl_pipe_wm_parameters *params,
3604 struct intel_wm_config *config,
3605 struct skl_ddb_allocation *ddb, /* out */
3606 struct skl_pipe_wm *pipe_wm /* out */)
3607{
3608 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3609
3610 skl_compute_wm_pipe_parameters(crtc, params);
b9cec075 3611 skl_allocate_pipe_ddb(crtc, config, params, ddb);
2d41c0b5
PB		 3612 skl_compute_pipe_wm(crtc, ddb, params, pipe_wm);
3613
3614 if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm)))
3615 return false;
3616
3617 intel_crtc->wm.skl_active = *pipe_wm;
2cd601c6 3618
2d41c0b5
PB		 3619 return true;
3620}
3621
3622static void skl_update_other_pipe_wm(struct drm_device *dev,
3623 struct drm_crtc *crtc,
3624 struct intel_wm_config *config,
3625 struct skl_wm_values *r)
3626{
3627 struct intel_crtc *intel_crtc;
3628 struct intel_crtc *this_crtc = to_intel_crtc(crtc);
3629
3630 /*
3631 * If the WM update hasn't changed the allocation for this_crtc (the
3632 * crtc we are currently computing the new WM values for), other
3633 * enabled crtcs will keep the same allocation and we don't need to
3634 * recompute anything for them.
3635 */
3636 if (!skl_ddb_allocation_changed(&r->ddb, this_crtc))
3637 return;
3638
3639 /*
3640 * Otherwise, because of this_crtc being freshly enabled/disabled, the
3641 * other active pipes need new DDB allocation and WM values.
3642 */
3643 list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list,
3644 base.head) {
3645 struct skl_pipe_wm_parameters params = {};
3646 struct skl_pipe_wm pipe_wm = {};
3647 bool wm_changed;
3648
3649 if (this_crtc->pipe == intel_crtc->pipe)
3650 continue;
3651
3652 if (!intel_crtc->active)
3653 continue;
3654
3655 wm_changed = skl_update_pipe_wm(&intel_crtc->base,
3656 &params, config,
3657 &r->ddb, &pipe_wm);
3658
3659 /*
3660 * If we end up re-computing the other pipe WM values, it's
3661 * because it was really needed, so we expect the WM values to
3662 * be different.
3663 */
3664 WARN_ON(!wm_changed);
3665
3666 skl_compute_wm_results(dev, &params, &pipe_wm, r, intel_crtc);
3667 r->dirty[intel_crtc->pipe] = true;
3668 }
3669}
3670
3671static void skl_update_wm(struct drm_crtc *crtc)
3672{
3673 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3674 struct drm_device *dev = crtc->dev;
3675 struct drm_i915_private *dev_priv = dev->dev_private;
3676 struct skl_pipe_wm_parameters params = {};
3677 struct skl_wm_values *results = &dev_priv->wm.skl_results;
3678 struct skl_pipe_wm pipe_wm = {};
3679 struct intel_wm_config config = {};
3680
3681 memset(results, 0, sizeof(*results));
3682
3683 skl_compute_wm_global_parameters(dev, &config);
3684
3685 if (!skl_update_pipe_wm(crtc, &params, &config,
3686 &results->ddb, &pipe_wm))
3687 return;
3688
3689 skl_compute_wm_results(dev, &params, &pipe_wm, results, intel_crtc);
3690 results->dirty[intel_crtc->pipe] = true;
3691
3692 skl_update_other_pipe_wm(dev, crtc, &config, results);
3693 skl_write_wm_values(dev_priv, results);
0e8fb7ba 3694 skl_flush_wm_values(dev_priv, results);
53b0deb4
DL		 3695
3696 /* store the new configuration */
3697 dev_priv->wm.skl_hw = *results;
2d41c0b5
PB		 3698}
3699
3700static void
3701skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc,
3702 uint32_t sprite_width, uint32_t sprite_height,
3703 int pixel_size, bool enabled, bool scaled)
3704{
3705 struct intel_plane *intel_plane = to_intel_plane(plane);
0fda6568 3706 struct drm_framebuffer *fb = plane->state->fb;
2d41c0b5
PB		 3707
3708 intel_plane->wm.enabled = enabled;
3709 intel_plane->wm.scaled = scaled;
3710 intel_plane->wm.horiz_pixels = sprite_width;
3711 intel_plane->wm.vert_pixels = sprite_height;
0fda6568 3712 intel_plane->wm.tiling = DRM_FORMAT_MOD_NONE;
2cd601c6
CK		 3713
3714 /* For planar: Bpp is for UV plane, y_Bpp is for Y plane */
3715 intel_plane->wm.bytes_per_pixel =
3716 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3717 drm_format_plane_cpp(plane->state->fb->pixel_format, 1) : pixel_size;
3718 intel_plane->wm.y_bytes_per_pixel =
3719 (fb && fb->pixel_format == DRM_FORMAT_NV12) ?
3720 drm_format_plane_cpp(plane->state->fb->pixel_format, 0) : 0;
3721
0fda6568
TU		 3722 /*
3723 * Framebuffer can be NULL on plane disable, but it does not
3724 * matter for watermarks if we assume no tiling in that case.
3725 */
3726 if (fb)
3727 intel_plane->wm.tiling = fb->modifier[0];
1fc0a8f7 3728 intel_plane->wm.rotation = plane->state->rotation;
2d41c0b5
PB		 3729
3730 skl_update_wm(crtc);
3731}
3732
820c1980 3733static void ilk_update_wm(struct drm_crtc *crtc)
801bcfff 3734{
7c4a395f 3735 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
46ba614c 3736 struct drm_device *dev = crtc->dev;
801bcfff 3737 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980
ID		 3738 struct ilk_wm_maximums max;
3739 struct ilk_pipe_wm_parameters params = {};
3740 struct ilk_wm_values results = {};
77c122bc 3741 enum intel_ddb_partitioning partitioning;
7c4a395f 3742 struct intel_pipe_wm pipe_wm = {};
198a1e9b 3743 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
a485bfb8 3744 struct intel_wm_config config = {};
7c4a395f 3745
2a44b76b 3746 ilk_compute_wm_parameters(crtc, &params);
7c4a395f
VS		 3747
3748 intel_compute_pipe_wm(crtc, &params, &pipe_wm);
3749
3750 if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm)))
3751 return;
861f3389 3752
7c4a395f 3753 intel_crtc->wm.active = pipe_wm;
861f3389 3754
2a44b76b
VS		 3755 ilk_compute_wm_config(dev, &config);
3756
34982fe1 3757 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
0ba22e26 3758 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 3759
3760 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1
VS		 3761 if (INTEL_INFO(dev)->gen >= 7 &&
3762 config.num_pipes_active == 1 && config.sprites_enabled) {
34982fe1 3763 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
0ba22e26 3764 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 3765
820c1980 3766 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 3767 } else {
198a1e9b 3768 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 3769 }
3770
198a1e9b 3771 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 3772 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 3773
820c1980 3774 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 3775
820c1980 3776 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 3777}
3778
ed57cb8a
DL		 3779static void
3780ilk_update_sprite_wm(struct drm_plane *plane,
3781 struct drm_crtc *crtc,
3782 uint32_t sprite_width, uint32_t sprite_height,
3783 int pixel_size, bool enabled, bool scaled)
526682e9 3784{
8553c18e 3785 struct drm_device *dev = plane->dev;
adf3d35e 3786 struct intel_plane *intel_plane = to_intel_plane(plane);
526682e9 3787
adf3d35e
VS		 3788 intel_plane->wm.enabled = enabled;
3789 intel_plane->wm.scaled = scaled;
3790 intel_plane->wm.horiz_pixels = sprite_width;
ed57cb8a 3791 intel_plane->wm.vert_pixels = sprite_width;
adf3d35e 3792 intel_plane->wm.bytes_per_pixel = pixel_size;
526682e9 3793
8553c18e
VS		 3794 /*
3795 * IVB workaround: must disable low power watermarks for at least
3796 * one frame before enabling scaling. LP watermarks can be re-enabled
3797 * when scaling is disabled.
3798 *
3799 * WaCxSRDisabledForSpriteScaling:ivb
3800 */
3801 if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev))
3802 intel_wait_for_vblank(dev, intel_plane->pipe);
3803
820c1980 3804 ilk_update_wm(crtc);
526682e9
PZ		 3805}
3806
3078999f
PB		 3807static void skl_pipe_wm_active_state(uint32_t val,
3808 struct skl_pipe_wm *active,
3809 bool is_transwm,
3810 bool is_cursor,
3811 int i,
3812 int level)
3813{
3814 bool is_enabled = (val & PLANE_WM_EN) != 0;
3815
3816 if (!is_transwm) {
3817 if (!is_cursor) {
3818 active->wm[level].plane_en[i] = is_enabled;
3819 active->wm[level].plane_res_b[i] =
3820 val & PLANE_WM_BLOCKS_MASK;
3821 active->wm[level].plane_res_l[i] =
3822 (val >> PLANE_WM_LINES_SHIFT) &
3823 PLANE_WM_LINES_MASK;
3824 } else {
3825 active->wm[level].cursor_en = is_enabled;
3826 active->wm[level].cursor_res_b =
3827 val & PLANE_WM_BLOCKS_MASK;
3828 active->wm[level].cursor_res_l =
3829 (val >> PLANE_WM_LINES_SHIFT) &
3830 PLANE_WM_LINES_MASK;
3831 }
3832 } else {
3833 if (!is_cursor) {
3834 active->trans_wm.plane_en[i] = is_enabled;
3835 active->trans_wm.plane_res_b[i] =
3836 val & PLANE_WM_BLOCKS_MASK;
3837 active->trans_wm.plane_res_l[i] =
3838 (val >> PLANE_WM_LINES_SHIFT) &
3839 PLANE_WM_LINES_MASK;
3840 } else {
3841 active->trans_wm.cursor_en = is_enabled;
3842 active->trans_wm.cursor_res_b =
3843 val & PLANE_WM_BLOCKS_MASK;
3844 active->trans_wm.cursor_res_l =
3845 (val >> PLANE_WM_LINES_SHIFT) &
3846 PLANE_WM_LINES_MASK;
3847 }
3848 }
3849}
3850
3851static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3852{
3853 struct drm_device *dev = crtc->dev;
3854 struct drm_i915_private *dev_priv = dev->dev_private;
3855 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
3856 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3857 struct skl_pipe_wm *active = &intel_crtc->wm.skl_active;
3858 enum pipe pipe = intel_crtc->pipe;
3859 int level, i, max_level;
3860 uint32_t temp;
3861
3862 max_level = ilk_wm_max_level(dev);
3863
3864 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
3865
3866 for (level = 0; level <= max_level; level++) {
3867 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3868 hw->plane[pipe][i][level] =
3869 I915_READ(PLANE_WM(pipe, i, level));
3870 hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level));
3871 }
3872
3873 for (i = 0; i < intel_num_planes(intel_crtc); i++)
3874 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
3875 hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe));
3876
3ef00284 3877 if (!intel_crtc->active)
3078999f
PB		 3878 return;
3879
3880 hw->dirty[pipe] = true;
3881
3882 active->linetime = hw->wm_linetime[pipe];
3883
3884 for (level = 0; level <= max_level; level++) {
3885 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3886 temp = hw->plane[pipe][i][level];
3887 skl_pipe_wm_active_state(temp, active, false,
3888 false, i, level);
3889 }
3890 temp = hw->cursor[pipe][level];
3891 skl_pipe_wm_active_state(temp, active, false, true, i, level);
3892 }
3893
3894 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3895 temp = hw->plane_trans[pipe][i];
3896 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
3897 }
3898
3899 temp = hw->cursor_trans[pipe];
3900 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
3901}
3902
3903void skl_wm_get_hw_state(struct drm_device *dev)
3904{
a269c583
DL		 3905 struct drm_i915_private *dev_priv = dev->dev_private;
3906 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 3907 struct drm_crtc *crtc;
3908
a269c583 3909 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 3910 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
3911 skl_pipe_wm_get_hw_state(crtc);
3912}
3913
243e6a44
VS		 3914static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
3915{
3916 struct drm_device *dev = crtc->dev;
3917 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 3918 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 3919 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3920 struct intel_pipe_wm *active = &intel_crtc->wm.active;
3921 enum pipe pipe = intel_crtc->pipe;
3922 static const unsigned int wm0_pipe_reg[] = {
3923 [PIPE_A] = WM0_PIPEA_ILK,
3924 [PIPE_B] = WM0_PIPEB_ILK,
3925 [PIPE_C] = WM0_PIPEC_IVB,
3926 };
3927
3928 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 3929 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 3930 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 3931
3ef00284 3932 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 3933
3934 if (active->pipe_enabled) {
243e6a44
VS		 3935 u32 tmp = hw->wm_pipe[pipe];
3936
3937 /*
3938 * For active pipes LP0 watermark is marked as
3939 * enabled, and LP1+ watermaks as disabled since
3940 * we can't really reverse compute them in case
3941 * multiple pipes are active.
3942 */
3943 active->wm[0].enable = true;
3944 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
3945 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
3946 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
3947 active->linetime = hw->wm_linetime[pipe];
3948 } else {
3949 int level, max_level = ilk_wm_max_level(dev);
3950
3951 /*
3952 * For inactive pipes, all watermark levels
3953 * should be marked as enabled but zeroed,
3954 * which is what we'd compute them to.
3955 */
3956 for (level = 0; level <= max_level; level++)
3957 active->wm[level].enable = true;
3958 }
3959}
3960
6eb1a681
VS		 3961#define _FW_WM(value, plane) \
3962 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
3963#define _FW_WM_VLV(value, plane) \
3964 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
3965
3966static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
3967 struct vlv_wm_values *wm)
3968{
3969 enum pipe pipe;
3970 uint32_t tmp;
3971
3972 for_each_pipe(dev_priv, pipe) {
3973 tmp = I915_READ(VLV_DDL(pipe));
3974
3975 wm->ddl[pipe].primary =
3976 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3977 wm->ddl[pipe].cursor =
3978 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3979 wm->ddl[pipe].sprite[0] =
3980 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3981 wm->ddl[pipe].sprite[1] =
3982 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
3983 }
3984
3985 tmp = I915_READ(DSPFW1);
3986 wm->sr.plane = _FW_WM(tmp, SR);
3987 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
3988 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
3989 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
3990
3991 tmp = I915_READ(DSPFW2);
3992 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
3993 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
3994 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
3995
3996 tmp = I915_READ(DSPFW3);
3997 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
3998
3999 if (IS_CHERRYVIEW(dev_priv)) {
4000 tmp = I915_READ(DSPFW7_CHV);
4001 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4002 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4003
4004 tmp = I915_READ(DSPFW8_CHV);
4005 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4006 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4007
4008 tmp = I915_READ(DSPFW9_CHV);
4009 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4010 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4011
4012 tmp = I915_READ(DSPHOWM);
4013 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4014 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4015 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4016 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4017 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4018 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4019 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4020 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4021 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4022 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4023 } else {
4024 tmp = I915_READ(DSPFW7);
4025 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4026 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4027
4028 tmp = I915_READ(DSPHOWM);
4029 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4030 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4031 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4032 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4033 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4034 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4035 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4036 }
4037}
4038
4039#undef _FW_WM
4040#undef _FW_WM_VLV
4041
4042void vlv_wm_get_hw_state(struct drm_device *dev)
4043{
4044 struct drm_i915_private *dev_priv = to_i915(dev);
4045 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4046 struct intel_plane *plane;
4047 enum pipe pipe;
4048 u32 val;
4049
4050 vlv_read_wm_values(dev_priv, wm);
4051
4052 for_each_intel_plane(dev, plane) {
4053 switch (plane->base.type) {
4054 int sprite;
4055 case DRM_PLANE_TYPE_CURSOR:
4056 plane->wm.fifo_size = 63;
4057 break;
4058 case DRM_PLANE_TYPE_PRIMARY:
4059 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4060 break;
4061 case DRM_PLANE_TYPE_OVERLAY:
4062 sprite = plane->plane;
4063 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4064 break;
4065 }
4066 }
4067
4068 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4069 wm->level = VLV_WM_LEVEL_PM2;
4070
4071 if (IS_CHERRYVIEW(dev_priv)) {
4072 mutex_lock(&dev_priv->rps.hw_lock);
4073
4074 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4075 if (val & DSP_MAXFIFO_PM5_ENABLE)
4076 wm->level = VLV_WM_LEVEL_PM5;
4077
4078 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4079 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4080 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4081
4082 mutex_unlock(&dev_priv->rps.hw_lock);
4083 }
4084
4085 for_each_pipe(dev_priv, pipe)
4086 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4087 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4088 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4089
4090 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4091 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4092}
4093
243e6a44
VS		 4094void ilk_wm_get_hw_state(struct drm_device *dev)
4095{
4096 struct drm_i915_private *dev_priv = dev->dev_private;
820c1980 4097 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4098 struct drm_crtc *crtc;
4099
70e1e0ec 4100 for_each_crtc(dev, crtc)
243e6a44
VS		 4101 ilk_pipe_wm_get_hw_state(crtc);
4102
4103 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4104 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4105 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4106
4107 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4108 if (INTEL_INFO(dev)->gen >= 7) {
4109 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4110 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4111 }
243e6a44 4112
a42a5719 4113 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4114 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4115 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4116 else if (IS_IVYBRIDGE(dev))
4117 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4118 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4119
4120 hw->enable_fbc_wm =
4121 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4122}
4123
b445e3b0
ED		 4124/**
4125 * intel_update_watermarks - update FIFO watermark values based on current modes
4126 *
4127 * Calculate watermark values for the various WM regs based on current mode
4128 * and plane configuration.
4129 *
4130 * There are several cases to deal with here:
4131 * - normal (i.e. non-self-refresh)
4132 * - self-refresh (SR) mode
4133 * - lines are large relative to FIFO size (buffer can hold up to 2)
4134 * - lines are small relative to FIFO size (buffer can hold more than 2
4135 * lines), so need to account for TLB latency
4136 *
4137 * The normal calculation is:
4138 * watermark = dotclock * bytes per pixel * latency
4139 * where latency is platform & configuration dependent (we assume pessimal
4140 * values here).
4141 *
4142 * The SR calculation is:
4143 * watermark = (trunc(latency/line time)+1) * surface width *
4144 * bytes per pixel
4145 * where
4146 * line time = htotal / dotclock
4147 * surface width = hdisplay for normal plane and 64 for cursor
4148 * and latency is assumed to be high, as above.
4149 *
4150 * The final value programmed to the register should always be rounded up,
4151 * and include an extra 2 entries to account for clock crossings.
4152 *
4153 * We don't use the sprite, so we can ignore that. And on Crestline we have
4154 * to set the non-SR watermarks to 8.
4155 */
46ba614c 4156void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4157{
46ba614c 4158 struct drm_i915_private *dev_priv = crtc->dev->dev_private;
b445e3b0
ED		 4159
4160 if (dev_priv->display.update_wm)
46ba614c 4161 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4162}
4163
adf3d35e
VS		 4164void intel_update_sprite_watermarks(struct drm_plane *plane,
4165 struct drm_crtc *crtc,
ed57cb8a
DL		 4166 uint32_t sprite_width,
4167 uint32_t sprite_height,
4168 int pixel_size,
39db4a4d 4169 bool enabled, bool scaled)
b445e3b0 4170{
adf3d35e 4171 struct drm_i915_private *dev_priv = plane->dev->dev_private;
b445e3b0
ED		 4172
4173 if (dev_priv->display.update_sprite_wm)
ed57cb8a
DL		 4174 dev_priv->display.update_sprite_wm(plane, crtc,
4175 sprite_width, sprite_height,
39db4a4d 4176 pixel_size, enabled, scaled);
b445e3b0
ED		 4177}
4178
9270388e
DV		 4179/**
4180 * Lock protecting IPS related data structures
9270388e
DV		 4181 */
4182DEFINE_SPINLOCK(mchdev_lock);
4183
4184/* Global for IPS driver to get at the current i915 device. Protected by
4185 * mchdev_lock. */
4186static struct drm_i915_private *i915_mch_dev;
4187
2b4e57bd
ED		 4188bool ironlake_set_drps(struct drm_device *dev, u8 val)
4189{
4190 struct drm_i915_private *dev_priv = dev->dev_private;
4191 u16 rgvswctl;
4192
9270388e
DV		 4193 assert_spin_locked(&mchdev_lock);
4194
2b4e57bd
ED		 4195 rgvswctl = I915_READ16(MEMSWCTL);
4196 if (rgvswctl & MEMCTL_CMD_STS) {
4197 DRM_DEBUG("gpu busy, RCS change rejected\n");
4198 return false; /* still busy with another command */
4199 }
4200
4201 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4202 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4203 I915_WRITE16(MEMSWCTL, rgvswctl);
4204 POSTING_READ16(MEMSWCTL);
4205
4206 rgvswctl |= MEMCTL_CMD_STS;
4207 I915_WRITE16(MEMSWCTL, rgvswctl);
4208
4209 return true;
4210}
4211
8090c6b9 4212static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 4213{
4214 struct drm_i915_private *dev_priv = dev->dev_private;
4215 u32 rgvmodectl = I915_READ(MEMMODECTL);
4216 u8 fmax, fmin, fstart, vstart;
4217
9270388e
DV		 4218 spin_lock_irq(&mchdev_lock);
4219
2b4e57bd
ED		 4220 /* Enable temp reporting */
4221 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4222 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4223
4224 /* 100ms RC evaluation intervals */
4225 I915_WRITE(RCUPEI, 100000);
4226 I915_WRITE(RCDNEI, 100000);
4227
4228 /* Set max/min thresholds to 90ms and 80ms respectively */
4229 I915_WRITE(RCBMAXAVG, 90000);
4230 I915_WRITE(RCBMINAVG, 80000);
4231
4232 I915_WRITE(MEMIHYST, 1);
4233
4234 /* Set up min, max, and cur for interrupt handling */
4235 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4236 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4237 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4238 MEMMODE_FSTART_SHIFT;
4239
4240 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
4241 PXVFREQ_PX_SHIFT;
4242
20e4d407
DV		 4243 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4244 dev_priv->ips.fstart = fstart;
2b4e57bd 4245
20e4d407
DV		 4246 dev_priv->ips.max_delay = fstart;
4247 dev_priv->ips.min_delay = fmin;
4248 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4249
4250 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4251 fmax, fmin, fstart);
4252
4253 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4254
4255 /*
4256 * Interrupts will be enabled in ironlake_irq_postinstall
4257 */
4258
4259 I915_WRITE(VIDSTART, vstart);
4260 POSTING_READ(VIDSTART);
4261
4262 rgvmodectl |= MEMMODE_SWMODE_EN;
4263 I915_WRITE(MEMMODECTL, rgvmodectl);
4264
9270388e 4265 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4266 DRM_ERROR("stuck trying to change perf mode\n");
6adfb1ef 4267 msleep(1);
2b4e57bd
ED		 4268
4269 ironlake_set_drps(dev, fstart);
4270
20e4d407 4271 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 4272 I915_READ(0x112e0);
20e4d407
DV		 4273 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
4274 dev_priv->ips.last_count2 = I915_READ(0x112f4);
5ed0bdf2 4275 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4276
4277 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4278}
4279
8090c6b9 4280static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 4281{
4282 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 4283 u16 rgvswctl;
4284
4285 spin_lock_irq(&mchdev_lock);
4286
4287 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4288
4289 /* Ack interrupts, disable EFC interrupt */
4290 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4291 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4292 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4293 I915_WRITE(DEIIR, DE_PCU_EVENT);
4294 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4295
4296 /* Go back to the starting frequency */
20e4d407 4297 ironlake_set_drps(dev, dev_priv->ips.fstart);
6adfb1ef 4298 msleep(1);
2b4e57bd
ED		 4299 rgvswctl |= MEMCTL_CMD_STS;
4300 I915_WRITE(MEMSWCTL, rgvswctl);
6adfb1ef 4301 msleep(1);
2b4e57bd 4302
9270388e 4303 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4304}
4305
acbe9475
DV		 4306/* There's a funny hw issue where the hw returns all 0 when reading from
4307 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4308 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4309 * all limits and the gpu stuck at whatever frequency it is at atm).
4310 */
74ef1173 4311static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4312{
7b9e0ae6 4313 u32 limits;
2b4e57bd 4314
20b46e59
DV		 4315 /* Only set the down limit when we've reached the lowest level to avoid
4316 * getting more interrupts, otherwise leave this clear. This prevents a
4317 * race in the hw when coming out of rc6: There's a tiny window where
4318 * the hw runs at the minimal clock before selecting the desired
4319 * frequency, if the down threshold expires in that window we will not
4320 * receive a down interrupt. */
74ef1173
AG		 4321 if (IS_GEN9(dev_priv->dev)) {
4322 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4323 if (val <= dev_priv->rps.min_freq_softlimit)
4324 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4325 } else {
4326 limits = dev_priv->rps.max_freq_softlimit << 24;
4327 if (val <= dev_priv->rps.min_freq_softlimit)
4328 limits |= dev_priv->rps.min_freq_softlimit << 16;
4329 }
20b46e59
DV		 4330
4331 return limits;
4332}
4333
dd75fdc8
CW		 4334static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4335{
4336 int new_power;
8a586437
AG		 4337 u32 threshold_up = 0, threshold_down = 0; /* in % */
4338 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4339
4340 new_power = dev_priv->rps.power;
4341 switch (dev_priv->rps.power) {
4342 case LOW_POWER:
b39fb297 4343 if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4344 new_power = BETWEEN;
4345 break;
4346
4347 case BETWEEN:
b39fb297 4348 if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq)
dd75fdc8 4349 new_power = LOW_POWER;
b39fb297 4350 else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4351 new_power = HIGH_POWER;
4352 break;
4353
4354 case HIGH_POWER:
b39fb297 4355 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4356 new_power = BETWEEN;
4357 break;
4358 }
4359 /* Max/min bins are special */
aed242ff 4360 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4361 new_power = LOW_POWER;
aed242ff 4362 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4363 new_power = HIGH_POWER;
4364 if (new_power == dev_priv->rps.power)
4365 return;
4366
4367 /* Note the units here are not exactly 1us, but 1280ns. */
4368 switch (new_power) {
4369 case LOW_POWER:
4370 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4371 ei_up = 16000;
4372 threshold_up = 95;
dd75fdc8
CW		 4373
4374 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4375 ei_down = 32000;
4376 threshold_down = 85;
dd75fdc8
CW		 4377 break;
4378
4379 case BETWEEN:
4380 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4381 ei_up = 13000;
4382 threshold_up = 90;
dd75fdc8
CW		 4383
4384 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4385 ei_down = 32000;
4386 threshold_down = 75;
dd75fdc8
CW		 4387 break;
4388
4389 case HIGH_POWER:
4390 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4391 ei_up = 10000;
4392 threshold_up = 85;
dd75fdc8
CW		 4393
4394 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4395 ei_down = 32000;
4396 threshold_down = 60;
dd75fdc8
CW		 4397 break;
4398 }
4399
8a586437
AG		 4400 I915_WRITE(GEN6_RP_UP_EI,
4401 GT_INTERVAL_FROM_US(dev_priv, ei_up));
4402 I915_WRITE(GEN6_RP_UP_THRESHOLD,
4403 GT_INTERVAL_FROM_US(dev_priv, (ei_up * threshold_up / 100)));
4404
4405 I915_WRITE(GEN6_RP_DOWN_EI,
4406 GT_INTERVAL_FROM_US(dev_priv, ei_down));
4407 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
4408 GT_INTERVAL_FROM_US(dev_priv, (ei_down * threshold_down / 100)));
4409
4410 I915_WRITE(GEN6_RP_CONTROL,
4411 GEN6_RP_MEDIA_TURBO |
4412 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4413 GEN6_RP_MEDIA_IS_GFX |
4414 GEN6_RP_ENABLE |
4415 GEN6_RP_UP_BUSY_AVG |
4416 GEN6_RP_DOWN_IDLE_AVG);
4417
dd75fdc8 4418 dev_priv->rps.power = new_power;
8fb55197
CW		 4419 dev_priv->rps.up_threshold = threshold_up;
4420 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4421 dev_priv->rps.last_adj = 0;
4422}
4423
2876ce73
CW		 4424static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4425{
4426 u32 mask = 0;
4427
4428 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4429 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4430 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4431 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4432
7b3c29f6
CW		 4433 mask &= dev_priv->pm_rps_events;
4434
59d02a1f 4435 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4436}
4437
b8a5ff8d
JM		 4438/* gen6_set_rps is called to update the frequency request, but should also be
4439 * called when the range (min_delay and max_delay) is modified so that we can
4440 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
ffe02b40 4441static void gen6_set_rps(struct drm_device *dev, u8 val)
20b46e59
DV		 4442{
4443 struct drm_i915_private *dev_priv = dev->dev_private;
7b9e0ae6 4444
4fc688ce 4445 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4446 WARN_ON(val > dev_priv->rps.max_freq);
4447 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4448
eb64cad1
CW		 4449 /* min/max delay may still have been modified so be sure to
4450 * write the limits value.
4451 */
4452 if (val != dev_priv->rps.cur_freq) {
4453 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4454
5704195c
AG		 4455 if (IS_GEN9(dev))
4456 I915_WRITE(GEN6_RPNSWREQ,
4457 GEN9_FREQUENCY(val));
4458 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
eb64cad1
CW		 4459 I915_WRITE(GEN6_RPNSWREQ,
4460 HSW_FREQUENCY(val));
4461 else
4462 I915_WRITE(GEN6_RPNSWREQ,
4463 GEN6_FREQUENCY(val) |
4464 GEN6_OFFSET(0) |
4465 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4466 }
7b9e0ae6 4467
7b9e0ae6
CW		 4468 /* Make sure we continue to get interrupts
4469 * until we hit the minimum or maximum frequencies.
4470 */
74ef1173 4471 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4472 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4473
d5570a72
BW		 4474 POSTING_READ(GEN6_RPNSWREQ);
4475
b39fb297 4476 dev_priv->rps.cur_freq = val;
be2cde9a 4477 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 4478}
4479
ffe02b40
VS		 4480static void valleyview_set_rps(struct drm_device *dev, u8 val)
4481{
4482 struct drm_i915_private *dev_priv = dev->dev_private;
4483
4484 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4485 WARN_ON(val > dev_priv->rps.max_freq);
4486 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40
VS		 4487
4488 if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1),
4489 "Odd GPU freq value\n"))
4490 val &= ~1;
4491
cd25dd5b
D		 4492 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4493
8fb55197 4494 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4495 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4496 if (!IS_CHERRYVIEW(dev_priv))
4497 gen6_set_rps_thresholds(dev_priv, val);
4498 }
ffe02b40 4499
ffe02b40
VS		 4500 dev_priv->rps.cur_freq = val;
4501 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
4502}
4503
a7f6e231 4504/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 4505 *
4506 * * If Gfx is Idle, then
a7f6e231
D		 4507 * 1. Forcewake Media well.
4508 * 2. Request idle freq.
4509 * 3. Release Forcewake of Media well.
76c3552f
D		 4510*/
4511static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
4512{
aed242ff 4513 u32 val = dev_priv->rps.idle_freq;
5549d25f 4514
aed242ff 4515 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 4516 return;
4517
a7f6e231
D		 4518 /* Wake up the media well, as that takes a lot less
4519 * power than the Render well. */
4520 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
4521 valleyview_set_rps(dev_priv->dev, val);
4522 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 4523}
4524
43cf3bf0
CW		 4525void gen6_rps_busy(struct drm_i915_private *dev_priv)
4526{
4527 mutex_lock(&dev_priv->rps.hw_lock);
4528 if (dev_priv->rps.enabled) {
4529 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
4530 gen6_rps_reset_ei(dev_priv);
4531 I915_WRITE(GEN6_PMINTRMSK,
4532 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
4533 }
4534 mutex_unlock(&dev_priv->rps.hw_lock);
4535}
4536
b29c19b6
CW		 4537void gen6_rps_idle(struct drm_i915_private *dev_priv)
4538{
691bb717
DL		 4539 struct drm_device *dev = dev_priv->dev;
4540
b29c19b6 4541 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 4542 if (dev_priv->rps.enabled) {
21a11fff 4543 if (IS_VALLEYVIEW(dev))
76c3552f 4544 vlv_set_rps_idle(dev_priv);
7526ed79 4545 else
aed242ff 4546 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
c0951f0c 4547 dev_priv->rps.last_adj = 0;
43cf3bf0 4548 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
c0951f0c 4549 }
8d3afd7d 4550 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 4551
8d3afd7d 4552 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 4553 while (!list_empty(&dev_priv->rps.clients))
4554 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 4555 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4556}
4557
1854d5ca 4558void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 4559 struct intel_rps_client *rps,
4560 unsigned long submitted)
b29c19b6 4561{
8d3afd7d
CW		 4562 /* This is intentionally racy! We peek at the state here, then
4563 * validate inside the RPS worker.
4564 */
4565 if (!(dev_priv->mm.busy &&
4566 dev_priv->rps.enabled &&
4567 dev_priv->rps.cur_freq < dev_priv->rps.max_freq_softlimit))
4568 return;
43cf3bf0 4569
e61b9958
CW		 4570 /* Force a RPS boost (and don't count it against the client) if
4571 * the GPU is severely congested.
4572 */
d0bc54f2 4573 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 4574 rps = NULL;
4575
8d3afd7d
CW		 4576 spin_lock(&dev_priv->rps.client_lock);
4577 if (rps == NULL || list_empty(&rps->link)) {
4578 spin_lock_irq(&dev_priv->irq_lock);
4579 if (dev_priv->rps.interrupts_enabled) {
4580 dev_priv->rps.client_boost = true;
4581 queue_work(dev_priv->wq, &dev_priv->rps.work);
4582 }
4583 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 4584
2e1b8730
CW		 4585 if (rps != NULL) {
4586 list_add(&rps->link, &dev_priv->rps.clients);
4587 rps->boosts++;
1854d5ca
CW		 4588 } else
4589 dev_priv->rps.boosts++;
c0951f0c 4590 }
8d3afd7d 4591 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 4592}
4593
ffe02b40 4594void intel_set_rps(struct drm_device *dev, u8 val)
0a073b84 4595{
ffe02b40
VS		 4596 if (IS_VALLEYVIEW(dev))
4597 valleyview_set_rps(dev, val);
4598 else
4599 gen6_set_rps(dev, val);
0a073b84
JB		 4600}
4601
20e49366
ZW		 4602static void gen9_disable_rps(struct drm_device *dev)
4603{
4604 struct drm_i915_private *dev_priv = dev->dev_private;
4605
4606 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 4607 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 4608}
4609
44fc7d5c 4610static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 4611{
4612 struct drm_i915_private *dev_priv = dev->dev_private;
4613
4614 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 4615 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
44fc7d5c
DV		 4616}
4617
38807746
D		 4618static void cherryview_disable_rps(struct drm_device *dev)
4619{
4620 struct drm_i915_private *dev_priv = dev->dev_private;
4621
4622 I915_WRITE(GEN6_RC_CONTROL, 0);
4623}
4624
44fc7d5c
DV		 4625static void valleyview_disable_rps(struct drm_device *dev)
4626{
4627 struct drm_i915_private *dev_priv = dev->dev_private;
4628
98a2e5f9
D		 4629 /* we're doing forcewake before Disabling RC6,
4630 * This what the BIOS expects when going into suspend */
59bad947 4631 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 4632
44fc7d5c 4633 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 4634
59bad947 4635 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 4636}
4637
dc39fff7
BW		 4638static void intel_print_rc6_info(struct drm_device *dev, u32 mode)
4639{
91ca689a
ID		 4640 if (IS_VALLEYVIEW(dev)) {
4641 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
4642 mode = GEN6_RC_CTL_RC6_ENABLE;
4643 else
4644 mode = 0;
4645 }
58abf1da
RV		 4646 if (HAS_RC6p(dev))
4647 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n",
4648 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
4649 (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
4650 (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
4651
4652 else
4653 DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n",
4654 (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off");
dc39fff7
BW		 4655}
4656
e6069ca8 4657static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6)
2b4e57bd 4658{
e7d66d89
DV		 4659 /* No RC6 before Ironlake and code is gone for ilk. */
4660 if (INTEL_INFO(dev)->gen < 6)
e6069ca8
ID		 4661 return 0;
4662
456470eb 4663 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 4664 if (enable_rc6 >= 0) {
4665 int mask;
4666
58abf1da 4667 if (HAS_RC6p(dev))
e6069ca8
ID		 4668 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
4669 INTEL_RC6pp_ENABLE;
4670 else
4671 mask = INTEL_RC6_ENABLE;
4672
4673 if ((enable_rc6 & mask) != enable_rc6)
8dfd1f04
DV		 4674 DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n",
4675 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 4676
4677 return enable_rc6 & mask;
4678 }
2b4e57bd 4679
8bade1ad 4680 if (IS_IVYBRIDGE(dev))
cca84a1f 4681 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 4682
4683 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 4684}
4685
e6069ca8
ID		 4686int intel_enable_rc6(const struct drm_device *dev)
4687{
4688 return i915.enable_rc6;
4689}
4690
93ee2920 4691static void gen6_init_rps_frequencies(struct drm_device *dev)
3280e8b0 4692{
93ee2920
TR		 4693 struct drm_i915_private *dev_priv = dev->dev_private;
4694 uint32_t rp_state_cap;
4695 u32 ddcc_status = 0;
4696 int ret;
4697
3280e8b0
BW		 4698 /* All of these values are in units of 50MHz */
4699 dev_priv->rps.cur_freq = 0;
93ee2920 4700 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
35040562
BP		 4701 if (IS_BROXTON(dev)) {
4702 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
4703 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
4704 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4705 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
4706 } else {
4707 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
4708 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
4709 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
4710 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
4711 }
4712
3280e8b0
BW		 4713 /* hw_max = RP0 until we check for overclocking */
4714 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
4715
93ee2920 4716 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
c5e0688c 4717 if (IS_HASWELL(dev) || IS_BROADWELL(dev) || IS_SKYLAKE(dev)) {
93ee2920
TR		 4718 ret = sandybridge_pcode_read(dev_priv,
4719 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
4720 &ddcc_status);
4721 if (0 == ret)
4722 dev_priv->rps.efficient_freq =
46efa4ab
TR		 4723 clamp_t(u8,
4724 ((ddcc_status >> 8) & 0xff),
4725 dev_priv->rps.min_freq,
4726 dev_priv->rps.max_freq);
93ee2920
TR		 4727 }
4728
c5e0688c
AG		 4729 if (IS_SKYLAKE(dev)) {
4730 /* Store the frequency values in 16.66 MHZ units, which is
4731 the natural hardware unit for SKL */
4732 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
4733 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
4734 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
4735 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
4736 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
4737 }
4738
aed242ff
CW		 4739 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
4740
3280e8b0
BW		 4741 /* Preserve min/max settings in case of re-init */
4742 if (dev_priv->rps.max_freq_softlimit == 0)
4743 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
4744
93ee2920
TR		 4745 if (dev_priv->rps.min_freq_softlimit == 0) {
4746 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
4747 dev_priv->rps.min_freq_softlimit =
813b5e69
VS		 4748 max_t(int, dev_priv->rps.efficient_freq,
4749 intel_freq_opcode(dev_priv, 450));
93ee2920
TR		 4750 else
4751 dev_priv->rps.min_freq_softlimit =
4752 dev_priv->rps.min_freq;
4753 }
3280e8b0
BW		 4754}
4755
b6fef0ef 4756/* See the Gen9_GT_PM_Programming_Guide doc for the below */
20e49366 4757static void gen9_enable_rps(struct drm_device *dev)
b6fef0ef
JB		 4758{
4759 struct drm_i915_private *dev_priv = dev->dev_private;
4760
4761 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
4762
ba1c554c
DL		 4763 gen6_init_rps_frequencies(dev);
4764
0beb059a
AG		 4765 /* Program defaults and thresholds for RPS*/
4766 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4767 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
4768
4769 /* 1 second timeout*/
4770 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
4771 GT_INTERVAL_FROM_US(dev_priv, 1000000));
4772
b6fef0ef 4773 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 4774
0beb059a
AG		 4775 /* Leaning on the below call to gen6_set_rps to program/setup the
4776 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
4777 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
4778 dev_priv->rps.power = HIGH_POWER; /* force a reset */
4779 gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit);
b6fef0ef
JB		 4780
4781 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
4782}
4783
4784static void gen9_enable_rc6(struct drm_device *dev)
20e49366
ZW		 4785{
4786 struct drm_i915_private *dev_priv = dev->dev_private;
4787 struct intel_engine_cs *ring;
4788 uint32_t rc6_mask = 0;
4789 int unused;
4790
4791 /* 1a: Software RC state - RC0 */
4792 I915_WRITE(GEN6_RC_STATE, 0);
4793
4794 /* 1b: Get forcewake during program sequence. Although the driver
4795 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4796 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4797
4798 /* 2a: Disable RC states. */
4799 I915_WRITE(GEN6_RC_CONTROL, 0);
4800
4801 /* 2b: Program RC6 thresholds.*/
4802 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
4803 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4804 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4805 for_each_ring(ring, dev_priv, unused)
4806 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4807 I915_WRITE(GEN6_RC_SLEEP, 0);
4808 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
4809
38c23527
ZW		 4810 /* 2c: Program Coarse Power Gating Policies. */
4811 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
4812 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
4813
20e49366
ZW		 4814 /* 3a: Enable RC6 */
4815 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4816 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
4817 DRM_INFO("RC6 %s\n", (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
4818 "on" : "off");
4819 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4820 GEN6_RC_CTL_EI_MODE(1) |
4821 rc6_mask);
4822
cb07bae0
SK		 4823 /*
4824 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
4825 * WaDisableRenderPowerGating:skl,bxt - Render PG need to be disabled with RC6.
4826 */
a4104c55 4827 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
cb07bae0 4828 GEN9_MEDIA_PG_ENABLE : 0);
a4104c55 4829
38c23527 4830
59bad947 4831 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 4832
4833}
4834
6edee7f3
BW		 4835static void gen8_enable_rps(struct drm_device *dev)
4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4838 struct intel_engine_cs *ring;
93ee2920 4839 uint32_t rc6_mask = 0;
6edee7f3
BW		 4840 int unused;
4841
4842 /* 1a: Software RC state - RC0 */
4843 I915_WRITE(GEN6_RC_STATE, 0);
4844
4845 /* 1c & 1d: Get forcewake during program sequence. Although the driver
4846 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 4847 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4848
4849 /* 2a: Disable RC states. */
4850 I915_WRITE(GEN6_RC_CONTROL, 0);
4851
93ee2920
TR		 4852 /* Initialize rps frequencies */
4853 gen6_init_rps_frequencies(dev);
6edee7f3
BW		 4854
4855 /* 2b: Program RC6 thresholds.*/
4856 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
4857 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
4858 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
4859 for_each_ring(ring, dev_priv, unused)
4860 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
4861 I915_WRITE(GEN6_RC_SLEEP, 0);
0d68b25e
TR		 4862 if (IS_BROADWELL(dev))
4863 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
4864 else
4865 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 4866
4867 /* 3: Enable RC6 */
4868 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
4869 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
abbf9d2c 4870 intel_print_rc6_info(dev, rc6_mask);
0d68b25e
TR		 4871 if (IS_BROADWELL(dev))
4872 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4873 GEN7_RC_CTL_TO_MODE |
4874 rc6_mask);
4875 else
4876 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
4877 GEN6_RC_CTL_EI_MODE(1) |
4878 rc6_mask);
6edee7f3
BW		 4879
4880 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 4881 I915_WRITE(GEN6_RPNSWREQ,
4882 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
4883 I915_WRITE(GEN6_RC_VIDEO_FREQ,
4884 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 4885 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
4886 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
4887
4888 /* Docs recommend 900MHz, and 300 MHz respectively */
4889 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
4890 dev_priv->rps.max_freq_softlimit << 24 |
4891 dev_priv->rps.min_freq_softlimit << 16);
4892
4893 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
4894 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
4895 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
4896 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
4897
4898 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 4899
4900 /* 5: Enable RPS */
7526ed79
DV		 4901 I915_WRITE(GEN6_RP_CONTROL,
4902 GEN6_RP_MEDIA_TURBO |
4903 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4904 GEN6_RP_MEDIA_IS_GFX |
4905 GEN6_RP_ENABLE |
4906 GEN6_RP_UP_BUSY_AVG |
4907 GEN6_RP_DOWN_IDLE_AVG);
4908
4909 /* 6: Ring frequency + overclocking (our driver does this later */
4910
c7f3153a 4911 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 4912 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
7526ed79 4913
59bad947 4914 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 4915}
4916
79f5b2c7 4917static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 4918{
79f5b2c7 4919 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 4920 struct intel_engine_cs *ring;
d060c169 4921 u32 rc6vids, pcu_mbox = 0, rc6_mask = 0;
2b4e57bd 4922 u32 gtfifodbg;
2b4e57bd 4923 int rc6_mode;
42c0526c 4924 int i, ret;
2b4e57bd 4925
4fc688ce 4926 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 4927
2b4e57bd
ED		 4928 /* Here begins a magic sequence of register writes to enable
4929 * auto-downclocking.
4930 *
4931 * Perhaps there might be some value in exposing these to
4932 * userspace...
4933 */
4934 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 4935
4936 /* Clear the DBG now so we don't confuse earlier errors */
4937 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
4938 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
4939 I915_WRITE(GTFIFODBG, gtfifodbg);
4940 }
4941
59bad947 4942 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd 4943
93ee2920
TR		 4944 /* Initialize rps frequencies */
4945 gen6_init_rps_frequencies(dev);
dd0a1aa1 4946
2b4e57bd
ED		 4947 /* disable the counters and set deterministic thresholds */
4948 I915_WRITE(GEN6_RC_CONTROL, 0);
4949
4950 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
4951 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
4952 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
4953 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
4954 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
4955
b4519513
CW		 4956 for_each_ring(ring, dev_priv, i)
4957 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 4958
4959 I915_WRITE(GEN6_RC_SLEEP, 0);
4960 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
29c78f60 4961 if (IS_IVYBRIDGE(dev))
351aa566
SM		 4962 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
4963 else
4964 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 4965 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 4966 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
4967
5a7dc92a 4968 /* Check if we are enabling RC6 */
2b4e57bd
ED		 4969 rc6_mode = intel_enable_rc6(dev_priv->dev);
4970 if (rc6_mode & INTEL_RC6_ENABLE)
4971 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
4972
5a7dc92a
ED		 4973 /* We don't use those on Haswell */
4974 if (!IS_HASWELL(dev)) {
4975 if (rc6_mode & INTEL_RC6p_ENABLE)
4976 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 4977
5a7dc92a
ED		 4978 if (rc6_mode & INTEL_RC6pp_ENABLE)
4979 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
4980 }
2b4e57bd 4981
dc39fff7 4982 intel_print_rc6_info(dev, rc6_mask);
2b4e57bd
ED		 4983
4984 I915_WRITE(GEN6_RC_CONTROL,
4985 rc6_mask |
4986 GEN6_RC_CTL_EI_MODE(1) |
4987 GEN6_RC_CTL_HW_ENABLE);
4988
dd75fdc8
CW		 4989 /* Power down if completely idle for over 50ms */
4990 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 4991 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 4992
42c0526c 4993 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 4994 if (ret)
42c0526c 4995 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169
BW		 4996
4997 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
4998 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
4999 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
b39fb297 5000 (dev_priv->rps.max_freq_softlimit & 0xff) * 50,
d060c169 5001 (pcu_mbox & 0xff) * 50);
b39fb297 5002 dev_priv->rps.max_freq = pcu_mbox & 0xff;
2b4e57bd
ED		 5003 }
5004
dd75fdc8 5005 dev_priv->rps.power = HIGH_POWER; /* force a reset */
aed242ff 5006 gen6_set_rps(dev_priv->dev, dev_priv->rps.idle_freq);
2b4e57bd 5007
31643d54
BW		 5008 rc6vids = 0;
5009 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
5010 if (IS_GEN6(dev) && ret) {
5011 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
5012 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
5013 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5014 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5015 rc6vids &= 0xffff00;
5016 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5017 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5018 if (ret)
5019 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5020 }
5021
59bad947 5022 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5023}
5024
c2bc2fc5 5025static void __gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 5026{
79f5b2c7 5027 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 5028 int min_freq = 15;
3ebecd07
CW		 5029 unsigned int gpu_freq;
5030 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5031 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5032 int scaling_factor = 180;
eda79642 5033 struct cpufreq_policy *policy;
2b4e57bd 5034
4fc688ce 5035 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5036
eda79642
BW		 5037 policy = cpufreq_cpu_get(0);
5038 if (policy) {
5039 max_ia_freq = policy->cpuinfo.max_freq;
5040 cpufreq_cpu_put(policy);
5041 } else {
5042 /*
5043 * Default to measured freq if none found, PCU will ensure we
5044 * don't go over
5045 */
2b4e57bd 5046 max_ia_freq = tsc_khz;
eda79642 5047 }
2b4e57bd
ED		 5048
5049 /* Convert from kHz to MHz */
5050 max_ia_freq /= 1000;
5051
153b4b95 5052 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5053 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5054 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5055
4c8c7743
AG		 5056 if (IS_SKYLAKE(dev)) {
5057 /* Convert GT frequency to 50 HZ units */
5058 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5059 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5060 } else {
5061 min_gpu_freq = dev_priv->rps.min_freq;
5062 max_gpu_freq = dev_priv->rps.max_freq;
5063 }
5064
2b4e57bd
ED		 5065 /*
5066 * For each potential GPU frequency, load a ring frequency we'd like
5067 * to use for memory access. We do this by specifying the IA frequency
5068 * the PCU should use as a reference to determine the ring frequency.
5069 */
4c8c7743
AG		 5070 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5071 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5072 unsigned int ia_freq = 0, ring_freq = 0;
5073
4c8c7743
AG		 5074 if (IS_SKYLAKE(dev)) {
5075 /*
5076 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5077 * No floor required for ring frequency on SKL.
5078 */
5079 ring_freq = gpu_freq;
5080 } else if (INTEL_INFO(dev)->gen >= 8) {
46c764d4
BW		 5081 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5082 ring_freq = max(min_ring_freq, gpu_freq);
5083 } else if (IS_HASWELL(dev)) {
f6aca45c 5084 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5085 ring_freq = max(min_ring_freq, ring_freq);
5086 /* leave ia_freq as the default, chosen by cpufreq */
5087 } else {
5088 /* On older processors, there is no separate ring
5089 * clock domain, so in order to boost the bandwidth
5090 * of the ring, we need to upclock the CPU (ia_freq).
5091 *
5092 * For GPU frequencies less than 750MHz,
5093 * just use the lowest ring freq.
5094 */
5095 if (gpu_freq < min_freq)
5096 ia_freq = 800;
5097 else
5098 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5099 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5100 }
2b4e57bd 5101
42c0526c
BW		 5102 sandybridge_pcode_write(dev_priv,
5103 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5104 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5105 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5106 gpu_freq);
2b4e57bd 5107 }
2b4e57bd
ED		 5108}
5109
c2bc2fc5
ID		 5110void gen6_update_ring_freq(struct drm_device *dev)
5111{
5112 struct drm_i915_private *dev_priv = dev->dev_private;
5113
97d3308a 5114 if (!HAS_CORE_RING_FREQ(dev))
c2bc2fc5
ID		 5115 return;
5116
5117 mutex_lock(&dev_priv->rps.hw_lock);
5118 __gen6_update_ring_freq(dev);
5119 mutex_unlock(&dev_priv->rps.hw_lock);
5120}
5121
03af2045 5122static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09 5123{
095acd5f 5124 struct drm_device *dev = dev_priv->dev;
2b6b3a09
D		 5125 u32 val, rp0;
5126
095acd5f
D		 5127 if (dev->pdev->revision >= 0x20) {
5128 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5129
095acd5f
D		 5130 switch (INTEL_INFO(dev)->eu_total) {
5131 case 8:
5132 /* (2 * 4) config */
5133 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5134 break;
5135 case 12:
5136 /* (2 * 6) config */
5137 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5138 break;
5139 case 16:
5140 /* (2 * 8) config */
5141 default:
5142 /* Setting (2 * 8) Min RP0 for any other combination */
5143 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5144 break;
5145 }
5146 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5147 } else {
5148 /* For pre-production hardware */
5149 val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG);
5150 rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5151 PUNIT_GPU_STATUS_MAX_FREQ_MASK;
5152 }
2b6b3a09
D		 5153 return rp0;
5154}
5155
5156static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5157{
5158 u32 val, rpe;
5159
5160 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5161 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5162
5163 return rpe;
5164}
5165
7707df4a
D		 5166static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5167{
095acd5f 5168 struct drm_device *dev = dev_priv->dev;
7707df4a
D		 5169 u32 val, rp1;
5170
095acd5f
D		 5171 if (dev->pdev->revision >= 0x20) {
5172 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5173 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5174 } else {
5175 /* For pre-production hardware */
5176 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5177 rp1 = ((val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) &
5178 PUNIT_GPU_STATUS_MAX_FREQ_MASK);
5179 }
7707df4a
D		 5180 return rp1;
5181}
5182
f8f2b001
D		 5183static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5184{
5185 u32 val, rp1;
5186
5187 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5188
5189 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5190
5191 return rp1;
5192}
5193
03af2045 5194static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5195{
5196 u32 val, rp0;
5197
64936258 5198 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5199
5200 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5201 /* Clamp to max */
5202 rp0 = min_t(u32, rp0, 0xea);
5203
5204 return rp0;
5205}
5206
5207static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5208{
5209 u32 val, rpe;
5210
64936258 5211 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5212 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5213 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5214 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5215
5216 return rpe;
5217}
5218
03af2045 5219static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5220{
64936258 5221 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 5222}
5223
ae48434c
ID		 5224/* Check that the pctx buffer wasn't move under us. */
5225static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5226{
5227 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5228
5229 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5230 dev_priv->vlv_pctx->stolen->start);
5231}
5232
38807746
D		 5233
5234/* Check that the pcbr address is not empty. */
5235static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5236{
5237 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5238
5239 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5240}
5241
5242static void cherryview_setup_pctx(struct drm_device *dev)
5243{
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245 unsigned long pctx_paddr, paddr;
5246 struct i915_gtt *gtt = &dev_priv->gtt;
5247 u32 pcbr;
5248 int pctx_size = 32*1024;
5249
5250 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5251
5252 pcbr = I915_READ(VLV_PCBR);
5253 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5254 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746
D		 5255 paddr = (dev_priv->mm.stolen_base +
5256 (gtt->stolen_size - pctx_size));
5257
5258 pctx_paddr = (paddr & (~4095));
5259 I915_WRITE(VLV_PCBR, pctx_paddr);
5260 }
ce611ef8
VS		 5261
5262 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5263}
5264
c9cddffc
JB		 5265static void valleyview_setup_pctx(struct drm_device *dev)
5266{
5267 struct drm_i915_private *dev_priv = dev->dev_private;
5268 struct drm_i915_gem_object *pctx;
5269 unsigned long pctx_paddr;
5270 u32 pcbr;
5271 int pctx_size = 24*1024;
5272
17b0c1f7
ID		 5273 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
5274
c9cddffc
JB		 5275 pcbr = I915_READ(VLV_PCBR);
5276 if (pcbr) {
5277 /* BIOS set it up already, grab the pre-alloc'd space */
5278 int pcbr_offset;
5279
5280 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
5281 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
5282 pcbr_offset,
190d6cd5 5283 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5284 pctx_size);
5285 goto out;
5286 }
5287
ce611ef8
VS		 5288 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5289
c9cddffc
JB		 5290 /*
5291 * From the Gunit register HAS:
5292 * The Gfx driver is expected to program this register and ensure
5293 * proper allocation within Gfx stolen memory. For example, this
5294 * register should be programmed such than the PCBR range does not
5295 * overlap with other ranges, such as the frame buffer, protected
5296 * memory, or any other relevant ranges.
5297 */
5298 pctx = i915_gem_object_create_stolen(dev, pctx_size);
5299 if (!pctx) {
5300 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
5301 return;
5302 }
5303
5304 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5305 I915_WRITE(VLV_PCBR, pctx_paddr);
5306
5307out:
ce611ef8 5308 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5309 dev_priv->vlv_pctx = pctx;
5310}
5311
ae48434c
ID		 5312static void valleyview_cleanup_pctx(struct drm_device *dev)
5313{
5314 struct drm_i915_private *dev_priv = dev->dev_private;
5315
5316 if (WARN_ON(!dev_priv->vlv_pctx))
5317 return;
5318
5319 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
5320 dev_priv->vlv_pctx = NULL;
5321}
5322
4e80519e
ID		 5323static void valleyview_init_gt_powersave(struct drm_device *dev)
5324{
5325 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5326 u32 val;
4e80519e
ID		 5327
5328 valleyview_setup_pctx(dev);
5329
5330 mutex_lock(&dev_priv->rps.hw_lock);
5331
2bb25c17
VS		 5332 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5333 switch ((val >> 6) & 3) {
5334 case 0:
5335 case 1:
5336 dev_priv->mem_freq = 800;
5337 break;
5338 case 2:
5339 dev_priv->mem_freq = 1066;
5340 break;
5341 case 3:
5342 dev_priv->mem_freq = 1333;
5343 break;
5344 }
80b83b62 5345 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5346
4e80519e
ID		 5347 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5348 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5349 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5350 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5351 dev_priv->rps.max_freq);
5352
5353 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5354 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5355 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5356 dev_priv->rps.efficient_freq);
5357
f8f2b001
D		 5358 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5359 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5360 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5361 dev_priv->rps.rp1_freq);
5362
4e80519e
ID		 5363 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5364 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5365 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e
ID		 5366 dev_priv->rps.min_freq);
5367
aed242ff
CW		 5368 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5369
4e80519e
ID		 5370 /* Preserve min/max settings in case of re-init */
5371 if (dev_priv->rps.max_freq_softlimit == 0)
5372 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5373
5374 if (dev_priv->rps.min_freq_softlimit == 0)
5375 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5376
5377 mutex_unlock(&dev_priv->rps.hw_lock);
5378}
5379
38807746
D		 5380static void cherryview_init_gt_powersave(struct drm_device *dev)
5381{
2b6b3a09 5382 struct drm_i915_private *dev_priv = dev->dev_private;
2bb25c17 5383 u32 val;
2b6b3a09 5384
38807746 5385 cherryview_setup_pctx(dev);
2b6b3a09
D		 5386
5387 mutex_lock(&dev_priv->rps.hw_lock);
5388
a580516d 5389 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5390 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5391 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5392
2bb25c17
VS		 5393 switch ((val >> 2) & 0x7) {
5394 case 0:
5395 case 1:
5396 dev_priv->rps.cz_freq = 200;
5397 dev_priv->mem_freq = 1600;
5398 break;
5399 case 2:
5400 dev_priv->rps.cz_freq = 267;
5401 dev_priv->mem_freq = 1600;
5402 break;
5403 case 3:
5404 dev_priv->rps.cz_freq = 333;
5405 dev_priv->mem_freq = 2000;
5406 break;
5407 case 4:
5408 dev_priv->rps.cz_freq = 320;
5409 dev_priv->mem_freq = 1600;
5410 break;
5411 case 5:
5412 dev_priv->rps.cz_freq = 400;
5413 dev_priv->mem_freq = 1600;
5414 break;
5415 }
80b83b62 5416 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5417
2b6b3a09
D		 5418 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5419 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5420 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5421 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5422 dev_priv->rps.max_freq);
5423
5424 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5425 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5426 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5427 dev_priv->rps.efficient_freq);
5428
7707df4a
D		 5429 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5430 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5431 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5432 dev_priv->rps.rp1_freq);
5433
5b7c91b7
D		 5434 /* PUnit validated range is only [RPe, RP0] */
5435 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5436 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5437 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5438 dev_priv->rps.min_freq);
5439
1c14762d
VS		 5440 WARN_ONCE((dev_priv->rps.max_freq |
5441 dev_priv->rps.efficient_freq |
5442 dev_priv->rps.rp1_freq |
5443 dev_priv->rps.min_freq) & 1,
5444 "Odd GPU freq values\n");
5445
aed242ff
CW		 5446 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
5447
2b6b3a09
D		 5448 /* Preserve min/max settings in case of re-init */
5449 if (dev_priv->rps.max_freq_softlimit == 0)
5450 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
5451
5452 if (dev_priv->rps.min_freq_softlimit == 0)
5453 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
5454
5455 mutex_unlock(&dev_priv->rps.hw_lock);
38807746
D		 5456}
5457
4e80519e
ID		 5458static void valleyview_cleanup_gt_powersave(struct drm_device *dev)
5459{
5460 valleyview_cleanup_pctx(dev);
5461}
5462
38807746
D		 5463static void cherryview_enable_rps(struct drm_device *dev)
5464{
5465 struct drm_i915_private *dev_priv = dev->dev_private;
5466 struct intel_engine_cs *ring;
2b6b3a09 5467 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5468 int i;
5469
5470 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5471
5472 gtfifodbg = I915_READ(GTFIFODBG);
5473 if (gtfifodbg) {
5474 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5475 gtfifodbg);
5476 I915_WRITE(GTFIFODBG, gtfifodbg);
5477 }
5478
5479 cherryview_check_pctx(dev_priv);
5480
5481 /* 1a & 1b: Get forcewake during program sequence. Although the driver
5482 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5483 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 5484
160614a2
VS		 5485 /* Disable RC states. */
5486 I915_WRITE(GEN6_RC_CONTROL, 0);
5487
38807746
D		 5488 /* 2a: Program RC6 thresholds.*/
5489 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5490 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5491 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
5492
5493 for_each_ring(ring, dev_priv, i)
5494 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5495 I915_WRITE(GEN6_RC_SLEEP, 0);
5496
f4f71c7d
D		 5497 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
5498 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 5499
5500 /* allows RC6 residency counter to work */
5501 I915_WRITE(VLV_COUNTER_CONTROL,
5502 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
5503 VLV_MEDIA_RC6_COUNT_EN |
5504 VLV_RENDER_RC6_COUNT_EN));
5505
5506 /* For now we assume BIOS is allocating and populating the PCBR */
5507 pcbr = I915_READ(VLV_PCBR);
5508
38807746
D		 5509 /* 3: Enable RC6 */
5510 if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) &&
5511 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 5512 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 5513
5514 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
5515
2b6b3a09 5516 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 5517 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 5518 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5519 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5520 I915_WRITE(GEN6_RP_UP_EI, 66000);
5521 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5522
5523 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5524
5525 /* 5: Enable RPS */
5526 I915_WRITE(GEN6_RP_CONTROL,
5527 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 5528 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 5529 GEN6_RP_ENABLE |
5530 GEN6_RP_UP_BUSY_AVG |
5531 GEN6_RP_DOWN_IDLE_AVG);
5532
3ef62342
D		 5533 /* Setting Fixed Bias */
5534 val = VLV_OVERRIDE_EN |
5535 VLV_SOC_TDP_EN |
5536 CHV_BIAS_CPU_50_SOC_50;
5537 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5538
2b6b3a09
D		 5539 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5540
8d40c3ae
VS		 5541 /* RPS code assumes GPLL is used */
5542 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5543
c8e9627d 5544 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
2b6b3a09
D		 5545 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5546
5547 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
5548 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5549 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
2b6b3a09
D		 5550 dev_priv->rps.cur_freq);
5551
5552 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5553 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5554 dev_priv->rps.efficient_freq);
5555
5556 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
5557
59bad947 5558 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 5559}
5560
0a073b84
JB		 5561static void valleyview_enable_rps(struct drm_device *dev)
5562{
5563 struct drm_i915_private *dev_priv = dev->dev_private;
a4872ba6 5564 struct intel_engine_cs *ring;
2a5913a8 5565 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 5566 int i;
5567
5568 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
5569
ae48434c
ID		 5570 valleyview_check_pctx(dev_priv);
5571
0a073b84 5572 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
f7d85c1e
JB		 5573 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
5574 gtfifodbg);
0a073b84
JB		 5575 I915_WRITE(GTFIFODBG, gtfifodbg);
5576 }
5577
c8d9a590 5578 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 5579 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 5580
160614a2
VS		 5581 /* Disable RC states. */
5582 I915_WRITE(GEN6_RC_CONTROL, 0);
5583
cad725fe 5584 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 5585 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
5586 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
5587 I915_WRITE(GEN6_RP_UP_EI, 66000);
5588 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5589
5590 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
5591
5592 I915_WRITE(GEN6_RP_CONTROL,
5593 GEN6_RP_MEDIA_TURBO |
5594 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5595 GEN6_RP_MEDIA_IS_GFX |
5596 GEN6_RP_ENABLE |
5597 GEN6_RP_UP_BUSY_AVG |
5598 GEN6_RP_DOWN_IDLE_CONT);
5599
5600 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
5601 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5602 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5603
5604 for_each_ring(ring, dev_priv, i)
5605 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
5606
2f0aa304 5607 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 5608
5609 /* allows RC6 residency counter to work */
49798eb2 5610 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 5611 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
5612 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 5613 VLV_MEDIA_RC6_COUNT_EN |
5614 VLV_RENDER_RC6_COUNT_EN));
31685c25 5615
a2b23fe0 5616 if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE)
6b88f295 5617 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7
BW		 5618
5619 intel_print_rc6_info(dev, rc6_mode);
5620
a2b23fe0 5621 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 5622
3ef62342
D		 5623 /* Setting Fixed Bias */
5624 val = VLV_OVERRIDE_EN |
5625 VLV_SOC_TDP_EN |
5626 VLV_BIAS_CPU_125_SOC_875;
5627 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
5628
64936258 5629 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 5630
8d40c3ae
VS		 5631 /* RPS code assumes GPLL is used */
5632 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
5633
c8e9627d 5634 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & GPLLENABLE ? "yes" : "no");
0a073b84
JB		 5635 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
5636
b39fb297 5637 dev_priv->rps.cur_freq = (val >> 8) & 0xff;
73008b98 5638 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
7c59a9c1 5639 intel_gpu_freq(dev_priv, dev_priv->rps.cur_freq),
b39fb297 5640 dev_priv->rps.cur_freq);
0a073b84 5641
73008b98 5642 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
7c59a9c1 5643 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
b39fb297 5644 dev_priv->rps.efficient_freq);
0a073b84 5645
b39fb297 5646 valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq);
0a073b84 5647
59bad947 5648 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 5649}
5650
dde18883
ED		 5651static unsigned long intel_pxfreq(u32 vidfreq)
5652{
5653 unsigned long freq;
5654 int div = (vidfreq & 0x3f0000) >> 16;
5655 int post = (vidfreq & 0x3000) >> 12;
5656 int pre = (vidfreq & 0x7);
5657
5658 if (!pre)
5659 return 0;
5660
5661 freq = ((div * 133333) / ((1<<post) * pre));
5662
5663 return freq;
5664}
5665
eb48eb00
DV		 5666static const struct cparams {
5667 u16 i;
5668 u16 t;
5669 u16 m;
5670 u16 c;
5671} cparams[] = {
5672 { 1, 1333, 301, 28664 },
5673 { 1, 1066, 294, 24460 },
5674 { 1, 800, 294, 25192 },
5675 { 0, 1333, 276, 27605 },
5676 { 0, 1066, 276, 27605 },
5677 { 0, 800, 231, 23784 },
5678};
5679
f531dcb2 5680static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5681{
5682 u64 total_count, diff, ret;
5683 u32 count1, count2, count3, m = 0, c = 0;
5684 unsigned long now = jiffies_to_msecs(jiffies), diff1;
5685 int i;
5686
02d71956
DV		 5687 assert_spin_locked(&mchdev_lock);
5688
20e4d407 5689 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 5690
5691 /* Prevent division-by-zero if we are asking too fast.
5692 * Also, we don't get interesting results if we are polling
5693 * faster than once in 10ms, so just return the saved value
5694 * in such cases.
5695 */
5696 if (diff1 <= 10)
20e4d407 5697 return dev_priv->ips.chipset_power;
eb48eb00
DV		 5698
5699 count1 = I915_READ(DMIEC);
5700 count2 = I915_READ(DDREC);
5701 count3 = I915_READ(CSIEC);
5702
5703 total_count = count1 + count2 + count3;
5704
5705 /* FIXME: handle per-counter overflow */
20e4d407
DV		 5706 if (total_count < dev_priv->ips.last_count1) {
5707 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 5708 diff += total_count;
5709 } else {
20e4d407 5710 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 5711 }
5712
5713 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 5714 if (cparams[i].i == dev_priv->ips.c_m &&
5715 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 5716 m = cparams[i].m;
5717 c = cparams[i].c;
5718 break;
5719 }
5720 }
5721
5722 diff = div_u64(diff, diff1);
5723 ret = ((m * diff) + c);
5724 ret = div_u64(ret, 10);
5725
20e4d407
DV		 5726 dev_priv->ips.last_count1 = total_count;
5727 dev_priv->ips.last_time1 = now;
eb48eb00 5728
20e4d407 5729 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 5730
5731 return ret;
5732}
5733
f531dcb2
CW		 5734unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
5735{
3d13ef2e 5736 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5737 unsigned long val;
5738
3d13ef2e 5739 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5740 return 0;
5741
5742 spin_lock_irq(&mchdev_lock);
5743
5744 val = __i915_chipset_val(dev_priv);
5745
5746 spin_unlock_irq(&mchdev_lock);
5747
5748 return val;
5749}
5750
eb48eb00
DV		 5751unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
5752{
5753 unsigned long m, x, b;
5754 u32 tsfs;
5755
5756 tsfs = I915_READ(TSFS);
5757
5758 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
5759 x = I915_READ8(TR1);
5760
5761 b = tsfs & TSFS_INTR_MASK;
5762
5763 return ((m * x) / 127) - b;
5764}
5765
d972d6ee
MK		 5766static int _pxvid_to_vd(u8 pxvid)
5767{
5768 if (pxvid == 0)
5769 return 0;
5770
5771 if (pxvid >= 8 && pxvid < 31)
5772 pxvid = 31;
5773
5774 return (pxvid + 2) * 125;
5775}
5776
5777static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 5778{
3d13ef2e 5779 struct drm_device *dev = dev_priv->dev;
d972d6ee
MK		 5780 const int vd = _pxvid_to_vd(pxvid);
5781 const int vm = vd - 1125;
5782
3d13ef2e 5783 if (INTEL_INFO(dev)->is_mobile)
d972d6ee
MK		 5784 return vm > 0 ? vm : 0;
5785
5786 return vd;
eb48eb00
DV		 5787}
5788
02d71956 5789static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 5790{
5ed0bdf2 5791 u64 now, diff, diffms;
eb48eb00
DV		 5792 u32 count;
5793
02d71956 5794 assert_spin_locked(&mchdev_lock);
eb48eb00 5795
5ed0bdf2
TG		 5796 now = ktime_get_raw_ns();
5797 diffms = now - dev_priv->ips.last_time2;
5798 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 5799
5800 /* Don't divide by 0 */
eb48eb00
DV		 5801 if (!diffms)
5802 return;
5803
5804 count = I915_READ(GFXEC);
5805
20e4d407
DV		 5806 if (count < dev_priv->ips.last_count2) {
5807 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 5808 diff += count;
5809 } else {
20e4d407 5810 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 5811 }
5812
20e4d407
DV		 5813 dev_priv->ips.last_count2 = count;
5814 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 5815
5816 /* More magic constants... */
5817 diff = diff * 1181;
5818 diff = div_u64(diff, diffms * 10);
20e4d407 5819 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 5820}
5821
02d71956
DV		 5822void i915_update_gfx_val(struct drm_i915_private *dev_priv)
5823{
3d13ef2e
DL		 5824 struct drm_device *dev = dev_priv->dev;
5825
5826 if (INTEL_INFO(dev)->gen != 5)
02d71956
DV		 5827 return;
5828
9270388e 5829 spin_lock_irq(&mchdev_lock);
02d71956
DV		 5830
5831 __i915_update_gfx_val(dev_priv);
5832
9270388e 5833 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 5834}
5835
f531dcb2 5836static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 5837{
5838 unsigned long t, corr, state1, corr2, state2;
5839 u32 pxvid, ext_v;
5840
02d71956
DV		 5841 assert_spin_locked(&mchdev_lock);
5842
b39fb297 5843 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4));
eb48eb00
DV		 5844 pxvid = (pxvid >> 24) & 0x7f;
5845 ext_v = pvid_to_extvid(dev_priv, pxvid);
5846
5847 state1 = ext_v;
5848
5849 t = i915_mch_val(dev_priv);
5850
5851 /* Revel in the empirically derived constants */
5852
5853 /* Correction factor in 1/100000 units */
5854 if (t > 80)
5855 corr = ((t * 2349) + 135940);
5856 else if (t >= 50)
5857 corr = ((t * 964) + 29317);
5858 else /* < 50 */
5859 corr = ((t * 301) + 1004);
5860
5861 corr = corr * ((150142 * state1) / 10000 - 78642);
5862 corr /= 100000;
20e4d407 5863 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 5864
5865 state2 = (corr2 * state1) / 10000;
5866 state2 /= 100; /* convert to mW */
5867
02d71956 5868 __i915_update_gfx_val(dev_priv);
eb48eb00 5869
20e4d407 5870 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 5871}
5872
f531dcb2
CW		 5873unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
5874{
3d13ef2e 5875 struct drm_device *dev = dev_priv->dev;
f531dcb2
CW		 5876 unsigned long val;
5877
3d13ef2e 5878 if (INTEL_INFO(dev)->gen != 5)
f531dcb2
CW		 5879 return 0;
5880
5881 spin_lock_irq(&mchdev_lock);
5882
5883 val = __i915_gfx_val(dev_priv);
5884
5885 spin_unlock_irq(&mchdev_lock);
5886
5887 return val;
5888}
5889
eb48eb00
DV		 5890/**
5891 * i915_read_mch_val - return value for IPS use
5892 *
5893 * Calculate and return a value for the IPS driver to use when deciding whether
5894 * we have thermal and power headroom to increase CPU or GPU power budget.
5895 */
5896unsigned long i915_read_mch_val(void)
5897{
5898 struct drm_i915_private *dev_priv;
5899 unsigned long chipset_val, graphics_val, ret = 0;
5900
9270388e 5901 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5902 if (!i915_mch_dev)
5903 goto out_unlock;
5904 dev_priv = i915_mch_dev;
5905
f531dcb2
CW		 5906 chipset_val = __i915_chipset_val(dev_priv);
5907 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 5908
5909 ret = chipset_val + graphics_val;
5910
5911out_unlock:
9270388e 5912 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5913
5914 return ret;
5915}
5916EXPORT_SYMBOL_GPL(i915_read_mch_val);
5917
5918/**
5919 * i915_gpu_raise - raise GPU frequency limit
5920 *
5921 * Raise the limit; IPS indicates we have thermal headroom.
5922 */
5923bool i915_gpu_raise(void)
5924{
5925 struct drm_i915_private *dev_priv;
5926 bool ret = true;
5927
9270388e 5928 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5929 if (!i915_mch_dev) {
5930 ret = false;
5931 goto out_unlock;
5932 }
5933 dev_priv = i915_mch_dev;
5934
20e4d407
DV		 5935 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
5936 dev_priv->ips.max_delay--;
eb48eb00
DV		 5937
5938out_unlock:
9270388e 5939 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5940
5941 return ret;
5942}
5943EXPORT_SYMBOL_GPL(i915_gpu_raise);
5944
5945/**
5946 * i915_gpu_lower - lower GPU frequency limit
5947 *
5948 * IPS indicates we're close to a thermal limit, so throttle back the GPU
5949 * frequency maximum.
5950 */
5951bool i915_gpu_lower(void)
5952{
5953 struct drm_i915_private *dev_priv;
5954 bool ret = true;
5955
9270388e 5956 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5957 if (!i915_mch_dev) {
5958 ret = false;
5959 goto out_unlock;
5960 }
5961 dev_priv = i915_mch_dev;
5962
20e4d407
DV		 5963 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
5964 dev_priv->ips.max_delay++;
eb48eb00
DV		 5965
5966out_unlock:
9270388e 5967 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5968
5969 return ret;
5970}
5971EXPORT_SYMBOL_GPL(i915_gpu_lower);
5972
5973/**
5974 * i915_gpu_busy - indicate GPU business to IPS
5975 *
5976 * Tell the IPS driver whether or not the GPU is busy.
5977 */
5978bool i915_gpu_busy(void)
5979{
5980 struct drm_i915_private *dev_priv;
a4872ba6 5981 struct intel_engine_cs *ring;
eb48eb00 5982 bool ret = false;
f047e395 5983 int i;
eb48eb00 5984
9270388e 5985 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 5986 if (!i915_mch_dev)
5987 goto out_unlock;
5988 dev_priv = i915_mch_dev;
5989
f047e395
CW		 5990 for_each_ring(ring, dev_priv, i)
5991 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 5992
5993out_unlock:
9270388e 5994 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 5995
5996 return ret;
5997}
5998EXPORT_SYMBOL_GPL(i915_gpu_busy);
5999
6000/**
6001 * i915_gpu_turbo_disable - disable graphics turbo
6002 *
6003 * Disable graphics turbo by resetting the max frequency and setting the
6004 * current frequency to the default.
6005 */
6006bool i915_gpu_turbo_disable(void)
6007{
6008 struct drm_i915_private *dev_priv;
6009 bool ret = true;
6010
9270388e 6011 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6012 if (!i915_mch_dev) {
6013 ret = false;
6014 goto out_unlock;
6015 }
6016 dev_priv = i915_mch_dev;
6017
20e4d407 6018 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6019
20e4d407 6020 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 6021 ret = false;
6022
6023out_unlock:
9270388e 6024 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6025
6026 return ret;
6027}
6028EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6029
6030/**
6031 * Tells the intel_ips driver that the i915 driver is now loaded, if
6032 * IPS got loaded first.
6033 *
6034 * This awkward dance is so that neither module has to depend on the
6035 * other in order for IPS to do the appropriate communication of
6036 * GPU turbo limits to i915.
6037 */
6038static void
6039ips_ping_for_i915_load(void)
6040{
6041 void (*link)(void);
6042
6043 link = symbol_get(ips_link_to_i915_driver);
6044 if (link) {
6045 link();
6046 symbol_put(ips_link_to_i915_driver);
6047 }
6048}
6049
6050void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6051{
02d71956
DV		 6052 /* We only register the i915 ips part with intel-ips once everything is
6053 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6054 spin_lock_irq(&mchdev_lock);
eb48eb00 6055 i915_mch_dev = dev_priv;
9270388e 6056 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6057
6058 ips_ping_for_i915_load();
6059}
6060
6061void intel_gpu_ips_teardown(void)
6062{
9270388e 6063 spin_lock_irq(&mchdev_lock);
eb48eb00 6064 i915_mch_dev = NULL;
9270388e 6065 spin_unlock_irq(&mchdev_lock);
eb48eb00 6066}
76c3552f 6067
8090c6b9 6068static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 6069{
6070 struct drm_i915_private *dev_priv = dev->dev_private;
6071 u32 lcfuse;
6072 u8 pxw[16];
6073 int i;
6074
6075 /* Disable to program */
6076 I915_WRITE(ECR, 0);
6077 POSTING_READ(ECR);
6078
6079 /* Program energy weights for various events */
6080 I915_WRITE(SDEW, 0x15040d00);
6081 I915_WRITE(CSIEW0, 0x007f0000);
6082 I915_WRITE(CSIEW1, 0x1e220004);
6083 I915_WRITE(CSIEW2, 0x04000004);
6084
6085 for (i = 0; i < 5; i++)
6086 I915_WRITE(PEW + (i * 4), 0);
6087 for (i = 0; i < 3; i++)
6088 I915_WRITE(DEW + (i * 4), 0);
6089
6090 /* Program P-state weights to account for frequency power adjustment */
6091 for (i = 0; i < 16; i++) {
6092 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
6093 unsigned long freq = intel_pxfreq(pxvidfreq);
6094 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6095 PXVFREQ_PX_SHIFT;
6096 unsigned long val;
6097
6098 val = vid * vid;
6099 val *= (freq / 1000);
6100 val *= 255;
6101 val /= (127*127*900);
6102 if (val > 0xff)
6103 DRM_ERROR("bad pxval: %ld\n", val);
6104 pxw[i] = val;
6105 }
6106 /* Render standby states get 0 weight */
6107 pxw[14] = 0;
6108 pxw[15] = 0;
6109
6110 for (i = 0; i < 4; i++) {
6111 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6112 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
6113 I915_WRITE(PXW + (i * 4), val);
6114 }
6115
6116 /* Adjust magic regs to magic values (more experimental results) */
6117 I915_WRITE(OGW0, 0);
6118 I915_WRITE(OGW1, 0);
6119 I915_WRITE(EG0, 0x00007f00);
6120 I915_WRITE(EG1, 0x0000000e);
6121 I915_WRITE(EG2, 0x000e0000);
6122 I915_WRITE(EG3, 0x68000300);
6123 I915_WRITE(EG4, 0x42000000);
6124 I915_WRITE(EG5, 0x00140031);
6125 I915_WRITE(EG6, 0);
6126 I915_WRITE(EG7, 0);
6127
6128 for (i = 0; i < 8; i++)
6129 I915_WRITE(PXWL + (i * 4), 0);
6130
6131 /* Enable PMON + select events */
6132 I915_WRITE(ECR, 0x80000019);
6133
6134 lcfuse = I915_READ(LCFUSE02);
6135
20e4d407 6136 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6137}
6138
ae48434c
ID		 6139void intel_init_gt_powersave(struct drm_device *dev)
6140{
e6069ca8
ID		 6141 i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6);
6142
38807746
D		 6143 if (IS_CHERRYVIEW(dev))
6144 cherryview_init_gt_powersave(dev);
6145 else if (IS_VALLEYVIEW(dev))
4e80519e 6146 valleyview_init_gt_powersave(dev);
ae48434c
ID		 6147}
6148
6149void intel_cleanup_gt_powersave(struct drm_device *dev)
6150{
38807746
D		 6151 if (IS_CHERRYVIEW(dev))
6152 return;
6153 else if (IS_VALLEYVIEW(dev))
4e80519e 6154 valleyview_cleanup_gt_powersave(dev);
ae48434c
ID		 6155}
6156
dbea3cea
ID		 6157static void gen6_suspend_rps(struct drm_device *dev)
6158{
6159 struct drm_i915_private *dev_priv = dev->dev_private;
6160
6161 flush_delayed_work(&dev_priv->rps.delayed_resume_work);
6162
4c2a8897 6163 gen6_disable_rps_interrupts(dev);
dbea3cea
ID		 6164}
6165
156c7ca0
JB		 6166/**
6167 * intel_suspend_gt_powersave - suspend PM work and helper threads
6168 * @dev: drm device
6169 *
6170 * We don't want to disable RC6 or other features here, we just want
6171 * to make sure any work we've queued has finished and won't bother
6172 * us while we're suspended.
6173 */
6174void intel_suspend_gt_powersave(struct drm_device *dev)
6175{
6176 struct drm_i915_private *dev_priv = dev->dev_private;
6177
d4d70aa5
ID		 6178 if (INTEL_INFO(dev)->gen < 6)
6179 return;
6180
dbea3cea 6181 gen6_suspend_rps(dev);
b47adc17
D		 6182
6183 /* Force GPU to min freq during suspend */
6184 gen6_rps_idle(dev_priv);
156c7ca0
JB		 6185}
6186
8090c6b9
DV		 6187void intel_disable_gt_powersave(struct drm_device *dev)
6188{
1a01ab3b
JB		 6189 struct drm_i915_private *dev_priv = dev->dev_private;
6190
930ebb46 6191 if (IS_IRONLAKE_M(dev)) {
8090c6b9 6192 ironlake_disable_drps(dev);
38807746 6193 } else if (INTEL_INFO(dev)->gen >= 6) {
10d8d366 6194 intel_suspend_gt_powersave(dev);
e494837a 6195
4fc688ce 6196 mutex_lock(&dev_priv->rps.hw_lock);
20e49366
ZW		 6197 if (INTEL_INFO(dev)->gen >= 9)
6198 gen9_disable_rps(dev);
6199 else if (IS_CHERRYVIEW(dev))
38807746
D		 6200 cherryview_disable_rps(dev);
6201 else if (IS_VALLEYVIEW(dev))
d20d4f0c
JB		 6202 valleyview_disable_rps(dev);
6203 else
6204 gen6_disable_rps(dev);
e534770a 6205
c0951f0c 6206 dev_priv->rps.enabled = false;
4fc688ce 6207 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 6208 }
8090c6b9
DV		 6209}
6210
1a01ab3b
JB		 6211static void intel_gen6_powersave_work(struct work_struct *work)
6212{
6213 struct drm_i915_private *dev_priv =
6214 container_of(work, struct drm_i915_private,
6215 rps.delayed_resume_work.work);
6216 struct drm_device *dev = dev_priv->dev;
6217
4fc688ce 6218 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84 6219
4c2a8897 6220 gen6_reset_rps_interrupts(dev);
3cc134e3 6221
38807746
D		 6222 if (IS_CHERRYVIEW(dev)) {
6223 cherryview_enable_rps(dev);
6224 } else if (IS_VALLEYVIEW(dev)) {
0a073b84 6225 valleyview_enable_rps(dev);
20e49366 6226 } else if (INTEL_INFO(dev)->gen >= 9) {
b6fef0ef 6227 gen9_enable_rc6(dev);
20e49366 6228 gen9_enable_rps(dev);
cc017fb4
AG		 6229 if (IS_SKYLAKE(dev))
6230 __gen6_update_ring_freq(dev);
6edee7f3
BW		 6231 } else if (IS_BROADWELL(dev)) {
6232 gen8_enable_rps(dev);
c2bc2fc5 6233 __gen6_update_ring_freq(dev);
0a073b84
JB		 6234 } else {
6235 gen6_enable_rps(dev);
c2bc2fc5 6236 __gen6_update_ring_freq(dev);
0a073b84 6237 }
aed242ff
CW		 6238
6239 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6240 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6241
6242 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6243 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6244
c0951f0c 6245 dev_priv->rps.enabled = true;
3cc134e3 6246
4c2a8897 6247 gen6_enable_rps_interrupts(dev);
3cc134e3 6248
4fc688ce 6249 mutex_unlock(&dev_priv->rps.hw_lock);
c6df39b5
ID		 6250
6251 intel_runtime_pm_put(dev_priv);
1a01ab3b
JB		 6252}
6253
8090c6b9
DV		 6254void intel_enable_gt_powersave(struct drm_device *dev)
6255{
1a01ab3b
JB		 6256 struct drm_i915_private *dev_priv = dev->dev_private;
6257
f61018b1
YZ		 6258 /* Powersaving is controlled by the host when inside a VM */
6259 if (intel_vgpu_active(dev))
6260 return;
6261
8090c6b9 6262 if (IS_IRONLAKE_M(dev)) {
dc1d0136 6263 mutex_lock(&dev->struct_mutex);
8090c6b9 6264 ironlake_enable_drps(dev);
8090c6b9 6265 intel_init_emon(dev);
dc1d0136 6266 mutex_unlock(&dev->struct_mutex);
38807746 6267 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b
JB		 6268 /*
6269 * PCU communication is slow and this doesn't need to be
6270 * done at any specific time, so do this out of our fast path
6271 * to make resume and init faster.
c6df39b5
ID		 6272 *
6273 * We depend on the HW RC6 power context save/restore
6274 * mechanism when entering D3 through runtime PM suspend. So
6275 * disable RPM until RPS/RC6 is properly setup. We can only
6276 * get here via the driver load/system resume/runtime resume
6277 * paths, so the _noresume version is enough (and in case of
6278 * runtime resume it's necessary).
1a01ab3b 6279 */
c6df39b5
ID		 6280 if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
6281 round_jiffies_up_relative(HZ)))
6282 intel_runtime_pm_get_noresume(dev_priv);
8090c6b9
DV		 6283 }
6284}
6285
c6df39b5
ID		 6286void intel_reset_gt_powersave(struct drm_device *dev)
6287{
6288 struct drm_i915_private *dev_priv = dev->dev_private;
6289
dbea3cea
ID		 6290 if (INTEL_INFO(dev)->gen < 6)
6291 return;
6292
6293 gen6_suspend_rps(dev);
c6df39b5 6294 dev_priv->rps.enabled = false;
c6df39b5
ID		 6295}
6296
3107bd48
DV		 6297static void ibx_init_clock_gating(struct drm_device *dev)
6298{
6299 struct drm_i915_private *dev_priv = dev->dev_private;
6300
6301 /*
6302 * On Ibex Peak and Cougar Point, we need to disable clock
6303 * gating for the panel power sequencer or it will fail to
6304 * start up when no ports are active.
6305 */
6306 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6307}
6308
0e088b8f
VS		 6309static void g4x_disable_trickle_feed(struct drm_device *dev)
6310{
6311 struct drm_i915_private *dev_priv = dev->dev_private;
b12ce1d8 6312 enum pipe pipe;
0e088b8f 6313
055e393f 6314 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6315 I915_WRITE(DSPCNTR(pipe),
6316 I915_READ(DSPCNTR(pipe)) |
6317 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6318
6319 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6320 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6321 }
6322}
6323
017636cc
VS		 6324static void ilk_init_lp_watermarks(struct drm_device *dev)
6325{
6326 struct drm_i915_private *dev_priv = dev->dev_private;
6327
6328 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6329 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6330 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6331
6332 /*
6333 * Don't touch WM1S_LP_EN here.
6334 * Doing so could cause underruns.
6335 */
6336}
6337
1fa61106 6338static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6339{
6340 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6341 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6342
f1e8fa56
DL		 6343 /*
6344 * Required for FBC
6345 * WaFbcDisableDpfcClockGating:ilk
6346 */
4d47e4f5
DL		 6347 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6348 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6349 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6350
6351 I915_WRITE(PCH_3DCGDIS0,
6352 MARIUNIT_CLOCK_GATE_DISABLE |
6353 SVSMUNIT_CLOCK_GATE_DISABLE);
6354 I915_WRITE(PCH_3DCGDIS1,
6355 VFMUNIT_CLOCK_GATE_DISABLE);
6356
6f1d69b0
ED		 6357 /*
6358 * According to the spec the following bits should be set in
6359 * order to enable memory self-refresh
6360 * The bit 22/21 of 0x42004
6361 * The bit 5 of 0x42020
6362 * The bit 15 of 0x45000
6363 */
6364 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6365 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6366 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6367 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6368 I915_WRITE(DISP_ARB_CTL,
6369 (I915_READ(DISP_ARB_CTL) |
6370 DISP_FBC_WM_DIS));
017636cc
VS		 6371
6372 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6373
6374 /*
6375 * Based on the document from hardware guys the following bits
6376 * should be set unconditionally in order to enable FBC.
6377 * The bit 22 of 0x42000
6378 * The bit 22 of 0x42004
6379 * The bit 7,8,9 of 0x42020.
6380 */
6381 if (IS_IRONLAKE_M(dev)) {
4bb35334 6382 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6383 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6384 I915_READ(ILK_DISPLAY_CHICKEN1) |
6385 ILK_FBCQ_DIS);
6386 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6387 I915_READ(ILK_DISPLAY_CHICKEN2) |
6388 ILK_DPARB_GATE);
6f1d69b0
ED		 6389 }
6390
4d47e4f5
DL		 6391 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6392
6f1d69b0
ED		 6393 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6394 I915_READ(ILK_DISPLAY_CHICKEN2) |
6395 ILK_ELPIN_409_SELECT);
6396 I915_WRITE(_3D_CHICKEN2,
6397 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6398 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6399
ecdb4eb7 6400 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6401 I915_WRITE(CACHE_MODE_0,
6402 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6403
4e04632e
AG		 6404 /* WaDisable_RenderCache_OperationalFlush:ilk */
6405 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6406
0e088b8f 6407 g4x_disable_trickle_feed(dev);
bdad2b2f 6408
3107bd48
DV		 6409 ibx_init_clock_gating(dev);
6410}
6411
6412static void cpt_init_clock_gating(struct drm_device *dev)
6413{
6414 struct drm_i915_private *dev_priv = dev->dev_private;
6415 int pipe;
3f704fa2 6416 uint32_t val;
3107bd48
DV		 6417
6418 /*
6419 * On Ibex Peak and Cougar Point, we need to disable clock
6420 * gating for the panel power sequencer or it will fail to
6421 * start up when no ports are active.
6422 */
cd664078
JB		 6423 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6424 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6425 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6426 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6427 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6428 /* The below fixes the weird display corruption, a few pixels shifted
6429 * downward, on (only) LVDS of some HP laptops with IVY.
6430 */
055e393f 6431 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6432 val = I915_READ(TRANS_CHICKEN2(pipe));
6433 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6434 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6435 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6436 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6437 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6438 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6439 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6440 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6441 }
3107bd48 6442 /* WADP0ClockGatingDisable */
055e393f 6443 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 6444 I915_WRITE(TRANS_CHICKEN1(pipe),
6445 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
6446 }
6f1d69b0
ED		 6447}
6448
1d7aaa0c
DV		 6449static void gen6_check_mch_setup(struct drm_device *dev)
6450{
6451 struct drm_i915_private *dev_priv = dev->dev_private;
6452 uint32_t tmp;
6453
6454 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 6455 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
6456 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
6457 tmp);
1d7aaa0c
DV		 6458}
6459
1fa61106 6460static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6461{
6462 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 6463 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6464
231e54f6 6465 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 6466
6467 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6468 I915_READ(ILK_DISPLAY_CHICKEN2) |
6469 ILK_ELPIN_409_SELECT);
6470
ecdb4eb7 6471 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 6472 I915_WRITE(_3D_CHICKEN,
6473 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
6474
4e04632e
AG		 6475 /* WaDisable_RenderCache_OperationalFlush:snb */
6476 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6477
8d85d272
VS		 6478 /*
6479 * BSpec recoomends 8x4 when MSAA is used,
6480 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6481 *
6482 * Note that PS/WM thread counts depend on the WIZ hashing
6483 * disable bit, which we don't touch here, but it's good
6484 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 6485 */
6486 I915_WRITE(GEN6_GT_MODE,
98533251 6487 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 6488
017636cc 6489 ilk_init_lp_watermarks(dev);
6f1d69b0 6490
6f1d69b0 6491 I915_WRITE(CACHE_MODE_0,
50743298 6492 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 6493
6494 I915_WRITE(GEN6_UCGCTL1,
6495 I915_READ(GEN6_UCGCTL1) |
6496 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
6497 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
6498
6499 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
6500 * gating disable must be set. Failure to set it results in
6501 * flickering pixels due to Z write ordering failures after
6502 * some amount of runtime in the Mesa "fire" demo, and Unigine
6503 * Sanctuary and Tropics, and apparently anything else with
6504 * alpha test or pixel discard.
6505 *
6506 * According to the spec, bit 11 (RCCUNIT) must also be set,
6507 * but we didn't debug actual testcases to find it out.
0f846f81 6508 *
ef59318c
VS		 6509 * WaDisableRCCUnitClockGating:snb
6510 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 6511 */
6512 I915_WRITE(GEN6_UCGCTL2,
6513 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
6514 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
6515
5eb146dd 6516 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 6517 I915_WRITE(_3D_CHICKEN3,
6518 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 6519
e927ecde
VS		 6520 /*
6521 * Bspec says:
6522 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
6523 * 3DSTATE_SF number of SF output attributes is more than 16."
6524 */
6525 I915_WRITE(_3D_CHICKEN3,
6526 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
6527
6f1d69b0
ED		 6528 /*
6529 * According to the spec the following bits should be
6530 * set in order to enable memory self-refresh and fbc:
6531 * The bit21 and bit22 of 0x42000
6532 * The bit21 and bit22 of 0x42004
6533 * The bit5 and bit7 of 0x42020
6534 * The bit14 of 0x70180
6535 * The bit14 of 0x71180
4bb35334
DL		 6536 *
6537 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 6538 */
6539 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6540 I915_READ(ILK_DISPLAY_CHICKEN1) |
6541 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
6542 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6543 I915_READ(ILK_DISPLAY_CHICKEN2) |
6544 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 6545 I915_WRITE(ILK_DSPCLK_GATE_D,
6546 I915_READ(ILK_DSPCLK_GATE_D) |
6547 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
6548 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 6549
0e088b8f 6550 g4x_disable_trickle_feed(dev);
f8f2ac9a 6551
3107bd48 6552 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6553
6554 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6555}
6556
6557static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
6558{
6559 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
6560
3aad9059 6561 /*
46680e0a 6562 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 6563 *
6564 * This actually overrides the dispatch
6565 * mode for all thread types.
6566 */
6f1d69b0
ED		 6567 reg &= ~GEN7_FF_SCHED_MASK;
6568 reg |= GEN7_FF_TS_SCHED_HW;
6569 reg |= GEN7_FF_VS_SCHED_HW;
6570 reg |= GEN7_FF_DS_SCHED_HW;
6571
6572 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
6573}
6574
17a303ec
PZ		 6575static void lpt_init_clock_gating(struct drm_device *dev)
6576{
6577 struct drm_i915_private *dev_priv = dev->dev_private;
6578
6579 /*
6580 * TODO: this bit should only be enabled when really needed, then
6581 * disabled when not needed anymore in order to save power.
6582 */
6583 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
6584 I915_WRITE(SOUTH_DSPCLK_GATE_D,
6585 I915_READ(SOUTH_DSPCLK_GATE_D) |
6586 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 6587
6588 /* WADPOClockGatingDisable:hsw */
6589 I915_WRITE(_TRANSA_CHICKEN1,
6590 I915_READ(_TRANSA_CHICKEN1) |
6591 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 6592}
6593
7d708ee4
ID		 6594static void lpt_suspend_hw(struct drm_device *dev)
6595{
6596 struct drm_i915_private *dev_priv = dev->dev_private;
6597
6598 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
6599 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
6600
6601 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
6602 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
6603 }
6604}
6605
47c2bd97 6606static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2
BW		 6607{
6608 struct drm_i915_private *dev_priv = dev->dev_private;
07d27e20 6609 enum pipe pipe;
4d487cff 6610 uint32_t misccpctl;
1020a5c2 6611
7ad0dbab 6612 ilk_init_lp_watermarks(dev);
50ed5fbd 6613
ab57fff1 6614 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 6615 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 6616
ab57fff1 6617 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 6618 I915_WRITE(CHICKEN_PAR1_1,
6619 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
6620
ab57fff1 6621 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 6622 for_each_pipe(dev_priv, pipe) {
07d27e20 6623 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 6624 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 6625 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 6626 }
63801f21 6627
ab57fff1
BW		 6628 /* WaVSRefCountFullforceMissDisable:bdw */
6629 /* WaDSRefCountFullforceMissDisable:bdw */
6630 I915_WRITE(GEN7_FF_THREAD_MODE,
6631 I915_READ(GEN7_FF_THREAD_MODE) &
6632 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 6633
295e8bb7
VS		 6634 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6635 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 6636
6637 /* WaDisableSDEUnitClockGating:bdw */
6638 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6639 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 6640
4d487cff
VS		 6641 /*
6642 * WaProgramL3SqcReg1Default:bdw
6643 * WaTempDisableDOPClkGating:bdw
6644 */
6645 misccpctl = I915_READ(GEN7_MISCCPCTL);
6646 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
6647 I915_WRITE(GEN8_L3SQCREG1, BDW_WA_L3SQCREG1_DEFAULT);
6648 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
6649
6d50b065
VS		 6650 /*
6651 * WaGttCachingOffByDefault:bdw
6652 * GTT cache may not work with big pages, so if those
6653 * are ever enabled GTT cache may need to be disabled.
6654 */
6655 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
6656
89d6b2b8 6657 lpt_init_clock_gating(dev);
1020a5c2
BW		 6658}
6659
cad2a2d7
ED		 6660static void haswell_init_clock_gating(struct drm_device *dev)
6661{
6662 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7 6663
017636cc 6664 ilk_init_lp_watermarks(dev);
cad2a2d7 6665
f3fc4884
FJ		 6666 /* L3 caching of data atomics doesn't work -- disable it. */
6667 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
6668 I915_WRITE(HSW_ROW_CHICKEN3,
6669 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
6670
ecdb4eb7 6671 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 6672 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6673 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6674 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6675
e36ea7ff
VS		 6676 /* WaVSRefCountFullforceMissDisable:hsw */
6677 I915_WRITE(GEN7_FF_THREAD_MODE,
6678 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 6679
4e04632e
AG		 6680 /* WaDisable_RenderCache_OperationalFlush:hsw */
6681 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6682
fe27c606
CW		 6683 /* enable HiZ Raw Stall Optimization */
6684 I915_WRITE(CACHE_MODE_0_GEN7,
6685 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6686
ecdb4eb7 6687 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 6688 I915_WRITE(CACHE_MODE_1,
6689 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 6690
a12c4967
VS		 6691 /*
6692 * BSpec recommends 8x4 when MSAA is used,
6693 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6694 *
6695 * Note that PS/WM thread counts depend on the WIZ hashing
6696 * disable bit, which we don't touch here, but it's good
6697 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 6698 */
6699 I915_WRITE(GEN7_GT_MODE,
98533251 6700 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 6701
94411593
KG		 6702 /* WaSampleCChickenBitEnable:hsw */
6703 I915_WRITE(HALF_SLICE_CHICKEN3,
6704 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
6705
ecdb4eb7 6706 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 6707 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
6708
90a88643
PZ		 6709 /* WaRsPkgCStateDisplayPMReq:hsw */
6710 I915_WRITE(CHICKEN_PAR1_1,
6711 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 6712
17a303ec 6713 lpt_init_clock_gating(dev);
cad2a2d7
ED		 6714}
6715
1fa61106 6716static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6717{
6718 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 6719 uint32_t snpcr;
6f1d69b0 6720
017636cc 6721 ilk_init_lp_watermarks(dev);
6f1d69b0 6722
231e54f6 6723 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 6724
ecdb4eb7 6725 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 6726 I915_WRITE(_3D_CHICKEN3,
6727 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6728
ecdb4eb7 6729 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 6730 I915_WRITE(IVB_CHICKEN3,
6731 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6732 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6733
ecdb4eb7 6734 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 6735 if (IS_IVB_GT1(dev))
6736 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
6737 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6738
4e04632e
AG		 6739 /* WaDisable_RenderCache_OperationalFlush:ivb */
6740 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6741
ecdb4eb7 6742 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 6743 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
6744 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
6745
ecdb4eb7 6746 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 6747 I915_WRITE(GEN7_L3CNTLREG1,
6748 GEN7_WA_FOR_GEN7_L3_CONTROL);
6749 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 6750 GEN7_WA_L3_CHICKEN_MODE);
6751 if (IS_IVB_GT1(dev))
6752 I915_WRITE(GEN7_ROW_CHICKEN2,
6753 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 6754 else {
6755 /* must write both registers */
6756 I915_WRITE(GEN7_ROW_CHICKEN2,
6757 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 6758 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
6759 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 6760 }
6f1d69b0 6761
ecdb4eb7 6762 /* WaForceL3Serialization:ivb */
61939d97
JB		 6763 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6764 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6765
1b80a19a 6766 /*
0f846f81 6767 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6768 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 6769 */
6770 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 6771 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6772
ecdb4eb7 6773 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 6774 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6775 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6776 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6777
0e088b8f 6778 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6779
6780 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 6781
22721343
CW		 6782 if (0) { /* causes HiZ corruption on ivb:gt1 */
6783 /* enable HiZ Raw Stall Optimization */
6784 I915_WRITE(CACHE_MODE_0_GEN7,
6785 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
6786 }
116f2b6d 6787
ecdb4eb7 6788 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 6789 I915_WRITE(CACHE_MODE_1,
6790 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 6791
a607c1a4
VS		 6792 /*
6793 * BSpec recommends 8x4 when MSAA is used,
6794 * however in practice 16x4 seems fastest.
c5c98a58
VS		 6795 *
6796 * Note that PS/WM thread counts depend on the WIZ hashing
6797 * disable bit, which we don't touch here, but it's good
6798 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 6799 */
6800 I915_WRITE(GEN7_GT_MODE,
98533251 6801 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 6802
20848223
BW		 6803 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
6804 snpcr &= ~GEN6_MBC_SNPCR_MASK;
6805 snpcr |= GEN6_MBC_SNPCR_MED;
6806 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 6807
ab5c608b
BW		 6808 if (!HAS_PCH_NOP(dev))
6809 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 6810
6811 gen6_check_mch_setup(dev);
6f1d69b0
ED		 6812}
6813
c6beb13e
VS		 6814static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
6815{
6816 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6817
6818 /*
6819 * Disable trickle feed and enable pnd deadline calculation
6820 */
6821 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6822 I915_WRITE(CBR1_VLV, 0);
6823}
6824
1fa61106 6825static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6826{
6827 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 6828
c6beb13e 6829 vlv_init_display_clock_gating(dev_priv);
6f1d69b0 6830
ecdb4eb7 6831 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 6832 I915_WRITE(_3D_CHICKEN3,
6833 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
6834
ecdb4eb7 6835 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 6836 I915_WRITE(IVB_CHICKEN3,
6837 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
6838 CHICKEN3_DGMG_DONE_FIX_DISABLE);
6839
fad7d36e 6840 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 6841 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 6842 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 6843 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
6844 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 6845
4e04632e
AG		 6846 /* WaDisable_RenderCache_OperationalFlush:vlv */
6847 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6848
ecdb4eb7 6849 /* WaForceL3Serialization:vlv */
61939d97
JB		 6850 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
6851 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
6852
ecdb4eb7 6853 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 6854 I915_WRITE(GEN7_ROW_CHICKEN2,
6855 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
6856
ecdb4eb7 6857 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 6858 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
6859 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
6860 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
6861
46680e0a
VS		 6862 gen7_setup_fixed_func_scheduler(dev_priv);
6863
3c0edaeb 6864 /*
0f846f81 6865 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 6866 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 6867 */
6868 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 6869 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 6870
c98f5062
AG		 6871 /* WaDisableL3Bank2xClockGate:vlv
6872 * Disabling L3 clock gating- MMIO 940c[25] = 1
6873 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
6874 I915_WRITE(GEN7_UCGCTL4,
6875 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 6876
afd58e79
VS		 6877 /*
6878 * BSpec says this must be set, even though
6879 * WaDisable4x2SubspanOptimization isn't listed for VLV.
6880 */
6b26c86d
DV		 6881 I915_WRITE(CACHE_MODE_1,
6882 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 6883
da2518f9
VS		 6884 /*
6885 * BSpec recommends 8x4 when MSAA is used,
6886 * however in practice 16x4 seems fastest.
6887 *
6888 * Note that PS/WM thread counts depend on the WIZ hashing
6889 * disable bit, which we don't touch here, but it's good
6890 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
6891 */
6892 I915_WRITE(GEN7_GT_MODE,
6893 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
6894
031994ee
VS		 6895 /*
6896 * WaIncreaseL3CreditsForVLVB0:vlv
6897 * This is the hardware default actually.
6898 */
6899 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
6900
2d809570 6901 /*
ecdb4eb7 6902 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 6903 * Disable clock gating on th GCFG unit to prevent a delay
6904 * in the reporting of vblank events.
6905 */
7a0d1eed 6906 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 6907}
6908
a4565da8
VS		 6909static void cherryview_init_clock_gating(struct drm_device *dev)
6910{
6911 struct drm_i915_private *dev_priv = dev->dev_private;
6912
c6beb13e 6913 vlv_init_display_clock_gating(dev_priv);
dd811e70 6914
232ce337
VS		 6915 /* WaVSRefCountFullforceMissDisable:chv */
6916 /* WaDSRefCountFullforceMissDisable:chv */
6917 I915_WRITE(GEN7_FF_THREAD_MODE,
6918 I915_READ(GEN7_FF_THREAD_MODE) &
6919 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 6920
6921 /* WaDisableSemaphoreAndSyncFlipWait:chv */
6922 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
6923 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 6924
6925 /* WaDisableCSUnitClockGating:chv */
6926 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
6927 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 6928
6929 /* WaDisableSDEUnitClockGating:chv */
6930 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
6931 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065
VS		 6932
6933 /*
6934 * GTT cache may not work with big pages, so if those
6935 * are ever enabled GTT cache may need to be disabled.
6936 */
6937 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 6938}
6939
1fa61106 6940static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6941{
6942 struct drm_i915_private *dev_priv = dev->dev_private;
6943 uint32_t dspclk_gate;
6944
6945 I915_WRITE(RENCLK_GATE_D1, 0);
6946 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
6947 GS_UNIT_CLOCK_GATE_DISABLE |
6948 CL_UNIT_CLOCK_GATE_DISABLE);
6949 I915_WRITE(RAMCLK_GATE_D, 0);
6950 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
6951 OVRUNIT_CLOCK_GATE_DISABLE |
6952 OVCUNIT_CLOCK_GATE_DISABLE;
6953 if (IS_GM45(dev))
6954 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
6955 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 6956
6957 /* WaDisableRenderCachePipelinedFlush */
6958 I915_WRITE(CACHE_MODE_0,
6959 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 6960
4e04632e
AG		 6961 /* WaDisable_RenderCache_OperationalFlush:g4x */
6962 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6963
0e088b8f 6964 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 6965}
6966
1fa61106 6967static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6968{
6969 struct drm_i915_private *dev_priv = dev->dev_private;
6970
6971 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
6972 I915_WRITE(RENCLK_GATE_D2, 0);
6973 I915_WRITE(DSPCLK_GATE_D, 0);
6974 I915_WRITE(RAMCLK_GATE_D, 0);
6975 I915_WRITE16(DEUC, 0);
20f94967
VS		 6976 I915_WRITE(MI_ARB_STATE,
6977 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6978
6979 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6980 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6981}
6982
1fa61106 6983static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 6984{
6985 struct drm_i915_private *dev_priv = dev->dev_private;
6986
6987 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
6988 I965_RCC_CLOCK_GATE_DISABLE |
6989 I965_RCPB_CLOCK_GATE_DISABLE |
6990 I965_ISC_CLOCK_GATE_DISABLE |
6991 I965_FBC_CLOCK_GATE_DISABLE);
6992 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 6993 I915_WRITE(MI_ARB_STATE,
6994 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 6995
6996 /* WaDisable_RenderCache_OperationalFlush:gen4 */
6997 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 6998}
6999
1fa61106 7000static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7001{
7002 struct drm_i915_private *dev_priv = dev->dev_private;
7003 u32 dstate = I915_READ(D_STATE);
7004
7005 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7006 DSTATE_DOT_CLOCK_GATING;
7007 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7008
7009 if (IS_PINEVIEW(dev))
7010 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7011
7012 /* IIR "flip pending" means done if this bit is set */
7013 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7014
7015 /* interrupts should cause a wake up from C3 */
3299254f 7016 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7017
7018 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7019 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7020
7021 I915_WRITE(MI_ARB_STATE,
7022 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7023}
7024
1fa61106 7025static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7026{
7027 struct drm_i915_private *dev_priv = dev->dev_private;
7028
7029 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7030
7031 /* interrupts should cause a wake up from C3 */
7032 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7033 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7034
7035 I915_WRITE(MEM_MODE,
7036 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7037}
7038
1fa61106 7039static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 7040{
7041 struct drm_i915_private *dev_priv = dev->dev_private;
7042
7043 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7044
7045 I915_WRITE(MEM_MODE,
7046 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7047 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7048}
7049
6f1d69b0
ED		 7050void intel_init_clock_gating(struct drm_device *dev)
7051{
7052 struct drm_i915_private *dev_priv = dev->dev_private;
7053
c57e3551
DL		 7054 if (dev_priv->display.init_clock_gating)
7055 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7056}
7057
7d708ee4
ID		 7058void intel_suspend_hw(struct drm_device *dev)
7059{
7060 if (HAS_PCH_LPT(dev))
7061 lpt_suspend_hw(dev);
7062}
7063
1fa61106
ED		 7064/* Set up chip specific power management-related functions */
7065void intel_init_pm(struct drm_device *dev)
7066{
7067 struct drm_i915_private *dev_priv = dev->dev_private;
7068
7ff0ebcc 7069 intel_fbc_init(dev_priv);
1fa61106 7070
c921aba8
DV		 7071 /* For cxsr */
7072 if (IS_PINEVIEW(dev))
7073 i915_pineview_get_mem_freq(dev);
7074 else if (IS_GEN5(dev))
7075 i915_ironlake_get_mem_freq(dev);
7076
1fa61106 7077 /* For FIFO watermark updates */
f5ed50cb 7078 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c
PB		 7079 skl_setup_wm_latency(dev);
7080
a82abe43
ID		 7081 if (IS_BROXTON(dev))
7082 dev_priv->display.init_clock_gating =
7083 bxt_init_clock_gating;
7084 else if (IS_SKYLAKE(dev))
7085 dev_priv->display.init_clock_gating =
7086 skl_init_clock_gating;
2d41c0b5
PB		 7087 dev_priv->display.update_wm = skl_update_wm;
7088 dev_priv->display.update_sprite_wm = skl_update_sprite_wm;
c83155a6 7089 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7090 ilk_setup_wm_latency(dev);
53615a5e 7091
bd602544
VS		 7092 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7093 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7094 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7095 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
7096 dev_priv->display.update_wm = ilk_update_wm;
7097 dev_priv->display.update_sprite_wm = ilk_update_sprite_wm;
7098 } else {
7099 DRM_DEBUG_KMS("Failed to read display plane latency. "
7100 "Disable CxSR\n");
7101 }
7102
7103 if (IS_GEN5(dev))
1fa61106 7104 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
bd602544 7105 else if (IS_GEN6(dev))
1fa61106 7106 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
bd602544 7107 else if (IS_IVYBRIDGE(dev))
1fa61106 7108 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
bd602544 7109 else if (IS_HASWELL(dev))
cad2a2d7 7110 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
bd602544 7111 else if (INTEL_INFO(dev)->gen == 8)
47c2bd97 7112 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
a4565da8 7113 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1
VS		 7114 vlv_setup_wm_latency(dev);
7115
7116 dev_priv->display.update_wm = vlv_update_wm;
a4565da8
VS		 7117 dev_priv->display.init_clock_gating =
7118 cherryview_init_clock_gating;
1fa61106 7119 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f
VS		 7120 vlv_setup_wm_latency(dev);
7121
7122 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7123 dev_priv->display.init_clock_gating =
7124 valleyview_init_clock_gating;
1fa61106
ED		 7125 } else if (IS_PINEVIEW(dev)) {
7126 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7127 dev_priv->is_ddr3,
7128 dev_priv->fsb_freq,
7129 dev_priv->mem_freq)) {
7130 DRM_INFO("failed to find known CxSR latency "
7131 "(found ddr%s fsb freq %d, mem freq %d), "
7132 "disabling CxSR\n",
7133 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7134 dev_priv->fsb_freq, dev_priv->mem_freq);
7135 /* Disable CxSR and never update its watermark again */
5209b1f4 7136 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7137 dev_priv->display.update_wm = NULL;
7138 } else
7139 dev_priv->display.update_wm = pineview_update_wm;
7140 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7141 } else if (IS_G4X(dev)) {
7142 dev_priv->display.update_wm = g4x_update_wm;
7143 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7144 } else if (IS_GEN4(dev)) {
7145 dev_priv->display.update_wm = i965_update_wm;
7146 if (IS_CRESTLINE(dev))
7147 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7148 else if (IS_BROADWATER(dev))
7149 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7150 } else if (IS_GEN3(dev)) {
7151 dev_priv->display.update_wm = i9xx_update_wm;
7152 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
7153 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
feb56b93
DV		 7154 } else if (IS_GEN2(dev)) {
7155 if (INTEL_INFO(dev)->num_pipes == 1) {
7156 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7157 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7158 } else {
7159 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7160 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93
DV		 7161 }
7162
7163 if (IS_I85X(dev) || IS_I865G(dev))
7164 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7165 else
7166 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7167 } else {
7168 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7169 }
7170}
7171
151a49d0 7172int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7173{
4fc688ce 7174 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7175
7176 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7177 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7178 return -EAGAIN;
7179 }
7180
7181 I915_WRITE(GEN6_PCODE_DATA, *val);
dddab346 7182 I915_WRITE(GEN6_PCODE_DATA1, 0);
42c0526c
BW		 7183 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7184
7185 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7186 500)) {
7187 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7188 return -ETIMEDOUT;
7189 }
7190
7191 *val = I915_READ(GEN6_PCODE_DATA);
7192 I915_WRITE(GEN6_PCODE_DATA, 0);
7193
7194 return 0;
7195}
7196
151a49d0 7197int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u32 mbox, u32 val)
42c0526c 7198{
4fc688ce 7199 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 7200
7201 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
7202 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7203 return -EAGAIN;
7204 }
7205
7206 I915_WRITE(GEN6_PCODE_DATA, val);
7207 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
7208
7209 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
7210 500)) {
7211 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7212 return -ETIMEDOUT;
7213 }
7214
7215 I915_WRITE(GEN6_PCODE_DATA, 0);
7216
7217 return 0;
7218}
a0e4e199 7219
dd06f88c 7220static int vlv_gpu_freq_div(unsigned int czclk_freq)
855ba3be 7221{
dd06f88c
VS		 7222 switch (czclk_freq) {
7223 case 200:
7224 return 10;
7225 case 267:
7226 return 12;
7227 case 320:
7228 case 333:
dd06f88c 7229 return 16;
ab3fb157
VS		 7230 case 400:
7231 return 20;
855ba3be
JB		 7232 default:
7233 return -1;
7234 }
dd06f88c 7235}
855ba3be 7236
dd06f88c
VS		 7237static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7238{
7239 int div, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
7240
7241 div = vlv_gpu_freq_div(czclk_freq);
7242 if (div < 0)
7243 return div;
7244
7245 return DIV_ROUND_CLOSEST(czclk_freq * (val + 6 - 0xbd), div);
855ba3be
JB		 7246}
7247
b55dd647 7248static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7249{
dd06f88c 7250 int mul, czclk_freq = DIV_ROUND_CLOSEST(dev_priv->mem_freq, 4);
855ba3be 7251
dd06f88c
VS		 7252 mul = vlv_gpu_freq_div(czclk_freq);
7253 if (mul < 0)
7254 return mul;
855ba3be 7255
dd06f88c 7256 return DIV_ROUND_CLOSEST(mul * val, czclk_freq) + 0xbd - 6;
855ba3be
JB		 7257}
7258
b55dd647 7259static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7260{
dd06f88c 7261 int div, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7262
dd06f88c
VS		 7263 div = vlv_gpu_freq_div(czclk_freq) / 2;
7264 if (div < 0)
7265 return div;
22b1b2f8 7266
dd06f88c 7267 return DIV_ROUND_CLOSEST(czclk_freq * val, 2 * div) / 2;
22b1b2f8
D		 7268}
7269
b55dd647 7270static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7271{
dd06f88c 7272 int mul, czclk_freq = dev_priv->rps.cz_freq;
22b1b2f8 7273
dd06f88c
VS		 7274 mul = vlv_gpu_freq_div(czclk_freq) / 2;
7275 if (mul < 0)
7276 return mul;
22b1b2f8 7277
1c14762d 7278 /* CHV needs even values */
dd06f88c 7279 return DIV_ROUND_CLOSEST(val * 2 * mul, czclk_freq) * 2;
22b1b2f8
D		 7280}
7281
616bc820 7282int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7283{
80b6dda4
AG		 7284 if (IS_GEN9(dev_priv->dev))
7285 return (val * GT_FREQUENCY_MULTIPLIER) / GEN9_FREQ_SCALER;
7286 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7287 return chv_gpu_freq(dev_priv, val);
22b1b2f8 7288 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7289 return byt_gpu_freq(dev_priv, val);
7290 else
7291 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7292}
7293
616bc820
VS		 7294int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7295{
80b6dda4
AG		 7296 if (IS_GEN9(dev_priv->dev))
7297 return (val * GEN9_FREQ_SCALER) / GT_FREQUENCY_MULTIPLIER;
7298 else if (IS_CHERRYVIEW(dev_priv->dev))
616bc820 7299 return chv_freq_opcode(dev_priv, val);
22b1b2f8 7300 else if (IS_VALLEYVIEW(dev_priv->dev))
616bc820
VS		 7301 return byt_freq_opcode(dev_priv, val);
7302 else
7303 return val / GT_FREQUENCY_MULTIPLIER;
7304}
22b1b2f8 7305
6ad790c0
CW		 7306struct request_boost {
7307 struct work_struct work;
eed29a5b 7308 struct drm_i915_gem_request *req;
6ad790c0
CW		 7309};
7310
7311static void __intel_rps_boost_work(struct work_struct *work)
7312{
7313 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7314 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7315
e61b9958
CW		 7316 if (!i915_gem_request_completed(req, true))
7317 gen6_rps_boost(to_i915(req->ring->dev), NULL,
7318 req->emitted_jiffies);
6ad790c0 7319
e61b9958 7320 i915_gem_request_unreference__unlocked(req);
6ad790c0
CW		 7321 kfree(boost);
7322}
7323
7324void intel_queue_rps_boost_for_request(struct drm_device *dev,
eed29a5b 7325 struct drm_i915_gem_request *req)
6ad790c0
CW		 7326{
7327 struct request_boost *boost;
7328
eed29a5b 7329 if (req == NULL || INTEL_INFO(dev)->gen < 6)
6ad790c0
CW		 7330 return;
7331
e61b9958
CW		 7332 if (i915_gem_request_completed(req, true))
7333 return;
7334
6ad790c0
CW		 7335 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7336 if (boost == NULL)
7337 return;
7338
eed29a5b
DV		 7339 i915_gem_request_reference(req);
7340 boost->req = req;
6ad790c0
CW		 7341
7342 INIT_WORK(&boost->work, __intel_rps_boost_work);
7343 queue_work(to_i915(dev)->wq, &boost->work);
7344}
7345
f742a552 7346void intel_pm_setup(struct drm_device *dev)
907b28c5
CW		 7347{
7348 struct drm_i915_private *dev_priv = dev->dev_private;
7349
f742a552 7350 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7351 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7352
907b28c5
CW		 7353 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
7354 intel_gen6_powersave_work);
1854d5ca 7355 INIT_LIST_HEAD(&dev_priv->rps.clients);
2e1b8730
CW		 7356 INIT_LIST_HEAD(&dev_priv->rps.semaphores.link);
7357 INIT_LIST_HEAD(&dev_priv->rps.mmioflips.link);
5d584b2e 7358
33688d95 7359 dev_priv->pm.suspended = false;
907b28c5 7360}
ubuntu-bionic-kernel mirror