]> git.proxmox.com Git - mirror_ubuntu-artful-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-artful-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm: Nuke fb->bits_per_pixel
[mirror_ubuntu-artful-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
c8fe32c1 34#include <drm/drm_atomic_helper.h>
85208be0 35
dc39fff7 36/**
18afd443
JN		 37 * DOC: RC6
38 *
dc39fff7
BW		 39 * RC6 is a special power stage which allows the GPU to enter an very
40 * low-voltage mode when idle, using down to 0V while at this stage. This
41 * stage is entered automatically when the GPU is idle when RC6 support is
42 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
43 *
44 * There are different RC6 modes available in Intel GPU, which differentiate
45 * among each other with the latency required to enter and leave RC6 and
46 * voltage consumed by the GPU in different states.
47 *
48 * The combination of the following flags define which states GPU is allowed
49 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
50 * RC6pp is deepest RC6. Their support by hardware varies according to the
51 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
52 * which brings the most power savings; deeper states save more power, but
53 * require higher latency to switch to and wake up.
54 */
55#define INTEL_RC6_ENABLE (1<<0)
56#define INTEL_RC6p_ENABLE (1<<1)
57#define INTEL_RC6pp_ENABLE (1<<2)
58
46f16e63 59static void gen9_init_clock_gating(struct drm_i915_private *dev_priv)
a82abe43 60{
b033bb6d 61 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 62 I915_WRITE(CHICKEN_PAR1_1,
63 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
64
b033bb6d
MK		 65 I915_WRITE(GEN8_CONFIG0,
66 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 67
68 /* WaEnableChickenDCPR:skl,bxt,kbl */
69 I915_WRITE(GEN8_CHICKEN_DCPR_1,
70 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 71
72 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 73 /* WaFbcWakeMemOn:skl,bxt,kbl */
74 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
75 DISP_FBC_WM_DIS |
76 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 77
78 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
79 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
80 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 81}
82
46f16e63 83static void bxt_init_clock_gating(struct drm_i915_private *dev_priv)
b033bb6d 84{
46f16e63 85 gen9_init_clock_gating(dev_priv);
b033bb6d 86
a7546159
NH		 87 /* WaDisableSDEUnitClockGating:bxt */
88 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
89 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
90
32608ca2
ID		 91 /*
92 * FIXME:
868434c5 93 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 94 */
32608ca2 95 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 96 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 97
98 /*
99 * Wa: Backlight PWM may stop in the asserted state, causing backlight
100 * to stay fully on.
101 */
102 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
103 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
104 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 105}
106
148ac1f3 107static void i915_pineview_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 108{
c921aba8
DV		 109 u32 tmp;
110
111 tmp = I915_READ(CLKCFG);
112
113 switch (tmp & CLKCFG_FSB_MASK) {
114 case CLKCFG_FSB_533:
115 dev_priv->fsb_freq = 533; /* 133*4 */
116 break;
117 case CLKCFG_FSB_800:
118 dev_priv->fsb_freq = 800; /* 200*4 */
119 break;
120 case CLKCFG_FSB_667:
121 dev_priv->fsb_freq = 667; /* 167*4 */
122 break;
123 case CLKCFG_FSB_400:
124 dev_priv->fsb_freq = 400; /* 100*4 */
125 break;
126 }
127
128 switch (tmp & CLKCFG_MEM_MASK) {
129 case CLKCFG_MEM_533:
130 dev_priv->mem_freq = 533;
131 break;
132 case CLKCFG_MEM_667:
133 dev_priv->mem_freq = 667;
134 break;
135 case CLKCFG_MEM_800:
136 dev_priv->mem_freq = 800;
137 break;
138 }
139
140 /* detect pineview DDR3 setting */
141 tmp = I915_READ(CSHRDDR3CTL);
142 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
143}
144
148ac1f3 145static void i915_ironlake_get_mem_freq(struct drm_i915_private *dev_priv)
c921aba8 146{
c921aba8
DV		 147 u16 ddrpll, csipll;
148
149 ddrpll = I915_READ16(DDRMPLL1);
150 csipll = I915_READ16(CSIPLL0);
151
152 switch (ddrpll & 0xff) {
153 case 0xc:
154 dev_priv->mem_freq = 800;
155 break;
156 case 0x10:
157 dev_priv->mem_freq = 1066;
158 break;
159 case 0x14:
160 dev_priv->mem_freq = 1333;
161 break;
162 case 0x18:
163 dev_priv->mem_freq = 1600;
164 break;
165 default:
166 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
167 ddrpll & 0xff);
168 dev_priv->mem_freq = 0;
169 break;
170 }
171
20e4d407 172 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 173
174 switch (csipll & 0x3ff) {
175 case 0x00c:
176 dev_priv->fsb_freq = 3200;
177 break;
178 case 0x00e:
179 dev_priv->fsb_freq = 3733;
180 break;
181 case 0x010:
182 dev_priv->fsb_freq = 4266;
183 break;
184 case 0x012:
185 dev_priv->fsb_freq = 4800;
186 break;
187 case 0x014:
188 dev_priv->fsb_freq = 5333;
189 break;
190 case 0x016:
191 dev_priv->fsb_freq = 5866;
192 break;
193 case 0x018:
194 dev_priv->fsb_freq = 6400;
195 break;
196 default:
197 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
198 csipll & 0x3ff);
199 dev_priv->fsb_freq = 0;
200 break;
201 }
202
203 if (dev_priv->fsb_freq == 3200) {
20e4d407 204 dev_priv->ips.c_m = 0;
c921aba8 205 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 206 dev_priv->ips.c_m = 1;
c921aba8 207 } else {
20e4d407 208 dev_priv->ips.c_m = 2;
c921aba8
DV		 209 }
210}
211
b445e3b0
ED		 212static const struct cxsr_latency cxsr_latency_table[] = {
213 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
214 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
215 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
216 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
217 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
218
219 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
220 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
221 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
222 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
223 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
224
225 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
226 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
227 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
228 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
229 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
230
231 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
232 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
233 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
234 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
235 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
236
237 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
238 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
239 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
240 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
241 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
242
243 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
244 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
245 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
246 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
247 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
248};
249
44a655ca
TU		 250static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
251 bool is_ddr3,
b445e3b0
ED		 252 int fsb,
253 int mem)
254{
255 const struct cxsr_latency *latency;
256 int i;
257
258 if (fsb == 0 || mem == 0)
259 return NULL;
260
261 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
262 latency = &cxsr_latency_table[i];
263 if (is_desktop == latency->is_desktop &&
264 is_ddr3 == latency->is_ddr3 &&
265 fsb == latency->fsb_freq && mem == latency->mem_freq)
266 return latency;
267 }
268
269 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
270
271 return NULL;
272}
273
fc1ac8de
VS		 274static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
275{
276 u32 val;
277
278 mutex_lock(&dev_priv->rps.hw_lock);
279
280 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
281 if (enable)
282 val &= ~FORCE_DDR_HIGH_FREQ;
283 else
284 val |= FORCE_DDR_HIGH_FREQ;
285 val &= ~FORCE_DDR_LOW_FREQ;
286 val |= FORCE_DDR_FREQ_REQ_ACK;
287 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
288
289 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
290 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
291 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
292
293 mutex_unlock(&dev_priv->rps.hw_lock);
294}
295
cfb41411
VS		 296static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
297{
298 u32 val;
299
300 mutex_lock(&dev_priv->rps.hw_lock);
301
302 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
303 if (enable)
304 val |= DSP_MAXFIFO_PM5_ENABLE;
305 else
306 val &= ~DSP_MAXFIFO_PM5_ENABLE;
307 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
308
309 mutex_unlock(&dev_priv->rps.hw_lock);
310}
311
f4998963
VS		 312#define FW_WM(value, plane) \
313 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
314
5209b1f4 315void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 316{
5209b1f4 317 u32 val;
b445e3b0 318
920a14b2 319 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
5209b1f4 320 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 321 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 322 dev_priv->wm.vlv.cxsr = enable;
9beb5fea 323 } else if (IS_G4X(dev_priv) || IS_CRESTLINE(dev_priv)) {
5209b1f4 324 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 325 POSTING_READ(FW_BLC_SELF);
9b1e14f4 326 } else if (IS_PINEVIEW(dev_priv)) {
5209b1f4
ID		 327 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
328 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
329 I915_WRITE(DSPFW3, val);
a7a6c498 330 POSTING_READ(DSPFW3);
50a0bc90 331 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 332 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
333 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
334 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 335 POSTING_READ(FW_BLC_SELF);
50a0bc90 336 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 337 /*
338 * FIXME can't find a bit like this for 915G, and
339 * and yet it does have the related watermark in
340 * FW_BLC_SELF. What's going on?
341 */
5209b1f4
ID		 342 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
343 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
344 I915_WRITE(INSTPM, val);
a7a6c498 345 POSTING_READ(INSTPM);
5209b1f4
ID		 346 } else {
347 return;
348 }
b445e3b0 349
08c4d7fc 350 DRM_DEBUG_KMS("memory self-refresh is %s\n", enableddisabled(enable));
b445e3b0
ED		 351}
352
fc1ac8de 353
b445e3b0
ED		 354/*
355 * Latency for FIFO fetches is dependent on several factors:
356 * - memory configuration (speed, channels)
357 * - chipset
358 * - current MCH state
359 * It can be fairly high in some situations, so here we assume a fairly
360 * pessimal value. It's a tradeoff between extra memory fetches (if we
361 * set this value too high, the FIFO will fetch frequently to stay full)
362 * and power consumption (set it too low to save power and we might see
363 * FIFO underruns and display "flicker").
364 *
365 * A value of 5us seems to be a good balance; safe for very low end
366 * platforms but not overly aggressive on lower latency configs.
367 */
5aef6003 368static const int pessimal_latency_ns = 5000;
b445e3b0 369
b5004720
VS		 370#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
371 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
372
ef0f5e93 373static int vlv_get_fifo_size(struct drm_i915_private *dev_priv,
b5004720
VS		 374 enum pipe pipe, int plane)
375{
b5004720
VS		 376 int sprite0_start, sprite1_start, size;
377
378 switch (pipe) {
379 uint32_t dsparb, dsparb2, dsparb3;
380 case PIPE_A:
381 dsparb = I915_READ(DSPARB);
382 dsparb2 = I915_READ(DSPARB2);
383 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
384 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
385 break;
386 case PIPE_B:
387 dsparb = I915_READ(DSPARB);
388 dsparb2 = I915_READ(DSPARB2);
389 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
390 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
391 break;
392 case PIPE_C:
393 dsparb2 = I915_READ(DSPARB2);
394 dsparb3 = I915_READ(DSPARB3);
395 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
396 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
397 break;
398 default:
399 return 0;
400 }
401
402 switch (plane) {
403 case 0:
404 size = sprite0_start;
405 break;
406 case 1:
407 size = sprite1_start - sprite0_start;
408 break;
409 case 2:
410 size = 512 - 1 - sprite1_start;
411 break;
412 default:
413 return 0;
414 }
415
416 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
417 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
418 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
419 size);
420
421 return size;
422}
423
ef0f5e93 424static int i9xx_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 425{
b445e3b0
ED		 426 uint32_t dsparb = I915_READ(DSPARB);
427 int size;
428
429 size = dsparb & 0x7f;
430 if (plane)
431 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
432
433 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
434 plane ? "B" : "A", size);
435
436 return size;
437}
438
ef0f5e93 439static int i830_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 440{
b445e3b0
ED		 441 uint32_t dsparb = I915_READ(DSPARB);
442 int size;
443
444 size = dsparb & 0x1ff;
445 if (plane)
446 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
447 size >>= 1; /* Convert to cachelines */
448
449 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
450 plane ? "B" : "A", size);
451
452 return size;
453}
454
ef0f5e93 455static int i845_get_fifo_size(struct drm_i915_private *dev_priv, int plane)
b445e3b0 456{
b445e3b0
ED		 457 uint32_t dsparb = I915_READ(DSPARB);
458 int size;
459
460 size = dsparb & 0x7f;
461 size >>= 2; /* Convert to cachelines */
462
463 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
464 plane ? "B" : "A",
465 size);
466
467 return size;
468}
469
b445e3b0
ED		 470/* Pineview has different values for various configs */
471static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 472 .fifo_size = PINEVIEW_DISPLAY_FIFO,
473 .max_wm = PINEVIEW_MAX_WM,
474 .default_wm = PINEVIEW_DFT_WM,
475 .guard_size = PINEVIEW_GUARD_WM,
476 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 477};
478static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 479 .fifo_size = PINEVIEW_DISPLAY_FIFO,
480 .max_wm = PINEVIEW_MAX_WM,
481 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
482 .guard_size = PINEVIEW_GUARD_WM,
483 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 484};
485static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 486 .fifo_size = PINEVIEW_CURSOR_FIFO,
487 .max_wm = PINEVIEW_CURSOR_MAX_WM,
488 .default_wm = PINEVIEW_CURSOR_DFT_WM,
489 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
490 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 491};
492static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 493 .fifo_size = PINEVIEW_CURSOR_FIFO,
494 .max_wm = PINEVIEW_CURSOR_MAX_WM,
495 .default_wm = PINEVIEW_CURSOR_DFT_WM,
496 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
497 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 498};
499static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 500 .fifo_size = G4X_FIFO_SIZE,
501 .max_wm = G4X_MAX_WM,
502 .default_wm = G4X_MAX_WM,
503 .guard_size = 2,
504 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 505};
506static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 507 .fifo_size = I965_CURSOR_FIFO,
508 .max_wm = I965_CURSOR_MAX_WM,
509 .default_wm = I965_CURSOR_DFT_WM,
510 .guard_size = 2,
511 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 512};
b445e3b0 513static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 514 .fifo_size = I965_CURSOR_FIFO,
515 .max_wm = I965_CURSOR_MAX_WM,
516 .default_wm = I965_CURSOR_DFT_WM,
517 .guard_size = 2,
518 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 519};
520static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 521 .fifo_size = I945_FIFO_SIZE,
522 .max_wm = I915_MAX_WM,
523 .default_wm = 1,
524 .guard_size = 2,
525 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 526};
527static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 528 .fifo_size = I915_FIFO_SIZE,
529 .max_wm = I915_MAX_WM,
530 .default_wm = 1,
531 .guard_size = 2,
532 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 533};
9d539105 534static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 535 .fifo_size = I855GM_FIFO_SIZE,
536 .max_wm = I915_MAX_WM,
537 .default_wm = 1,
538 .guard_size = 2,
539 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 540};
9d539105
VS		 541static const struct intel_watermark_params i830_bc_wm_info = {
542 .fifo_size = I855GM_FIFO_SIZE,
543 .max_wm = I915_MAX_WM/2,
544 .default_wm = 1,
545 .guard_size = 2,
546 .cacheline_size = I830_FIFO_LINE_SIZE,
547};
feb56b93 548static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 549 .fifo_size = I830_FIFO_SIZE,
550 .max_wm = I915_MAX_WM,
551 .default_wm = 1,
552 .guard_size = 2,
553 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 554};
555
b445e3b0
ED		 556/**
557 * intel_calculate_wm - calculate watermark level
558 * @clock_in_khz: pixel clock
559 * @wm: chip FIFO params
ac484963 560 * @cpp: bytes per pixel
b445e3b0
ED		 561 * @latency_ns: memory latency for the platform
562 *
563 * Calculate the watermark level (the level at which the display plane will
564 * start fetching from memory again). Each chip has a different display
565 * FIFO size and allocation, so the caller needs to figure that out and pass
566 * in the correct intel_watermark_params structure.
567 *
568 * As the pixel clock runs, the FIFO will be drained at a rate that depends
569 * on the pixel size. When it reaches the watermark level, it'll start
570 * fetching FIFO line sized based chunks from memory until the FIFO fills
571 * past the watermark point. If the FIFO drains completely, a FIFO underrun
572 * will occur, and a display engine hang could result.
573 */
574static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
575 const struct intel_watermark_params *wm,
ac484963 576 int fifo_size, int cpp,
b445e3b0
ED		 577 unsigned long latency_ns)
578{
579 long entries_required, wm_size;
580
581 /*
582 * Note: we need to make sure we don't overflow for various clock &
583 * latency values.
584 * clocks go from a few thousand to several hundred thousand.
585 * latency is usually a few thousand
586 */
ac484963 587 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 588 1000;
589 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
590
591 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
592
593 wm_size = fifo_size - (entries_required + wm->guard_size);
594
595 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
596
597 /* Don't promote wm_size to unsigned... */
598 if (wm_size > (long)wm->max_wm)
599 wm_size = wm->max_wm;
600 if (wm_size <= 0)
601 wm_size = wm->default_wm;
d6feb196
VS		 602
603 /*
604 * Bspec seems to indicate that the value shouldn't be lower than
605 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
606 * Lets go for 8 which is the burst size since certain platforms
607 * already use a hardcoded 8 (which is what the spec says should be
608 * done).
609 */
610 if (wm_size <= 8)
611 wm_size = 8;
612
b445e3b0
ED		 613 return wm_size;
614}
615
ffc7a76b 616static struct intel_crtc *single_enabled_crtc(struct drm_i915_private *dev_priv)
b445e3b0 617{
efc2611e 618 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 619
ffc7a76b 620 for_each_intel_crtc(&dev_priv->drm, crtc) {
efc2611e 621 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 622 if (enabled)
623 return NULL;
624 enabled = crtc;
625 }
626 }
627
628 return enabled;
629}
630
432081bc 631static void pineview_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 632{
ffc7a76b 633 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 634 struct intel_crtc *crtc;
b445e3b0
ED		 635 const struct cxsr_latency *latency;
636 u32 reg;
637 unsigned long wm;
638
50a0bc90
TU		 639 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
640 dev_priv->is_ddr3,
641 dev_priv->fsb_freq,
642 dev_priv->mem_freq);
b445e3b0
ED		 643 if (!latency) {
644 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 645 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 646 return;
647 }
648
ffc7a76b 649 crtc = single_enabled_crtc(dev_priv);
b445e3b0 650 if (crtc) {
efc2611e
VS		 651 const struct drm_display_mode *adjusted_mode =
652 &crtc->config->base.adjusted_mode;
653 const struct drm_framebuffer *fb =
654 crtc->base.primary->state->fb;
353c8598 655 int cpp = fb->format->cpp[0];
7c5f93b0 656 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 657
658 /* Display SR */
659 wm = intel_calculate_wm(clock, &pineview_display_wm,
660 pineview_display_wm.fifo_size,
ac484963 661 cpp, latency->display_sr);
b445e3b0
ED		 662 reg = I915_READ(DSPFW1);
663 reg &= ~DSPFW_SR_MASK;
f4998963 664 reg |= FW_WM(wm, SR);
b445e3b0
ED		 665 I915_WRITE(DSPFW1, reg);
666 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
667
668 /* cursor SR */
669 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
670 pineview_display_wm.fifo_size,
ac484963 671 cpp, latency->cursor_sr);
b445e3b0
ED		 672 reg = I915_READ(DSPFW3);
673 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 674 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 675 I915_WRITE(DSPFW3, reg);
676
677 /* Display HPLL off SR */
678 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
679 pineview_display_hplloff_wm.fifo_size,
ac484963 680 cpp, latency->display_hpll_disable);
b445e3b0
ED		 681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 683 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 684 I915_WRITE(DSPFW3, reg);
685
686 /* cursor HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
ac484963 689 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 692 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 693 I915_WRITE(DSPFW3, reg);
694 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
695
5209b1f4 696 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 697 } else {
5209b1f4 698 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 699 }
700}
701
f0ce2310 702static bool g4x_compute_wm0(struct drm_i915_private *dev_priv,
b445e3b0
ED		 703 int plane,
704 const struct intel_watermark_params *display,
705 int display_latency_ns,
706 const struct intel_watermark_params *cursor,
707 int cursor_latency_ns,
708 int *plane_wm,
709 int *cursor_wm)
710{
efc2611e 711 struct intel_crtc *crtc;
4fe8590a 712 const struct drm_display_mode *adjusted_mode;
efc2611e 713 const struct drm_framebuffer *fb;
ac484963 714 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 715 int line_time_us, line_count;
716 int entries, tlb_miss;
717
b91eb5cc 718 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e 719 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 720 *cursor_wm = cursor->guard_size;
721 *plane_wm = display->guard_size;
722 return false;
723 }
724
efc2611e
VS		 725 adjusted_mode = &crtc->config->base.adjusted_mode;
726 fb = crtc->base.primary->state->fb;
241bfc38 727 clock = adjusted_mode->crtc_clock;
fec8cba3 728 htotal = adjusted_mode->crtc_htotal;
efc2611e 729 hdisplay = crtc->config->pipe_src_w;
353c8598 730 cpp = fb->format->cpp[0];
b445e3b0
ED		 731
732 /* Use the small buffer method to calculate plane watermark */
ac484963 733 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 734 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
735 if (tlb_miss > 0)
736 entries += tlb_miss;
737 entries = DIV_ROUND_UP(entries, display->cacheline_size);
738 *plane_wm = entries + display->guard_size;
739 if (*plane_wm > (int)display->max_wm)
740 *plane_wm = display->max_wm;
741
742 /* Use the large buffer method to calculate cursor watermark */
922044c9 743 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 744 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
efc2611e 745 entries = line_count * crtc->base.cursor->state->crtc_w * cpp;
b445e3b0
ED		 746 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
747 if (tlb_miss > 0)
748 entries += tlb_miss;
749 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
750 *cursor_wm = entries + cursor->guard_size;
751 if (*cursor_wm > (int)cursor->max_wm)
752 *cursor_wm = (int)cursor->max_wm;
753
754 return true;
755}
756
757/*
758 * Check the wm result.
759 *
760 * If any calculated watermark values is larger than the maximum value that
761 * can be programmed into the associated watermark register, that watermark
762 * must be disabled.
763 */
f0ce2310 764static bool g4x_check_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 765 int display_wm, int cursor_wm,
766 const struct intel_watermark_params *display,
767 const struct intel_watermark_params *cursor)
768{
769 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
770 display_wm, cursor_wm);
771
772 if (display_wm > display->max_wm) {
ae9400ca 773 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 774 display_wm, display->max_wm);
775 return false;
776 }
777
778 if (cursor_wm > cursor->max_wm) {
ae9400ca 779 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 780 cursor_wm, cursor->max_wm);
781 return false;
782 }
783
784 if (!(display_wm || cursor_wm)) {
785 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
786 return false;
787 }
788
789 return true;
790}
791
f0ce2310 792static bool g4x_compute_srwm(struct drm_i915_private *dev_priv,
b445e3b0
ED		 793 int plane,
794 int latency_ns,
795 const struct intel_watermark_params *display,
796 const struct intel_watermark_params *cursor,
797 int *display_wm, int *cursor_wm)
798{
efc2611e 799 struct intel_crtc *crtc;
4fe8590a 800 const struct drm_display_mode *adjusted_mode;
efc2611e 801 const struct drm_framebuffer *fb;
ac484963 802 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 803 unsigned long line_time_us;
804 int line_count, line_size;
805 int small, large;
806 int entries;
807
808 if (!latency_ns) {
809 *display_wm = *cursor_wm = 0;
810 return false;
811 }
812
b91eb5cc 813 crtc = intel_get_crtc_for_plane(dev_priv, plane);
efc2611e
VS		 814 adjusted_mode = &crtc->config->base.adjusted_mode;
815 fb = crtc->base.primary->state->fb;
241bfc38 816 clock = adjusted_mode->crtc_clock;
fec8cba3 817 htotal = adjusted_mode->crtc_htotal;
efc2611e 818 hdisplay = crtc->config->pipe_src_w;
353c8598 819 cpp = fb->format->cpp[0];
b445e3b0 820
922044c9 821 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 822 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 823 line_size = hdisplay * cpp;
b445e3b0
ED		 824
825 /* Use the minimum of the small and large buffer method for primary */
ac484963 826 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 827 large = line_count * line_size;
828
829 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
830 *display_wm = entries + display->guard_size;
831
832 /* calculate the self-refresh watermark for display cursor */
efc2611e 833 entries = line_count * cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 834 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
835 *cursor_wm = entries + cursor->guard_size;
836
f0ce2310 837 return g4x_check_srwm(dev_priv,
b445e3b0
ED		 838 *display_wm, *cursor_wm,
839 display, cursor);
840}
841
15665979
VS		 842#define FW_WM_VLV(value, plane) \
843 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
844
0018fda1
VS		 845static void vlv_write_wm_values(struct intel_crtc *crtc,
846 const struct vlv_wm_values *wm)
847{
848 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
849 enum pipe pipe = crtc->pipe;
850
851 I915_WRITE(VLV_DDL(pipe),
852 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
853 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
854 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
855 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
856
ae80152d 857 I915_WRITE(DSPFW1,
15665979
VS		 858 FW_WM(wm->sr.plane, SR) |
859 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
860 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
861 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 862 I915_WRITE(DSPFW2,
15665979
VS		 863 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
864 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
865 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 866 I915_WRITE(DSPFW3,
15665979 867 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 868
869 if (IS_CHERRYVIEW(dev_priv)) {
870 I915_WRITE(DSPFW7_CHV,
15665979
VS		 871 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
872 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 873 I915_WRITE(DSPFW8_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
875 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 876 I915_WRITE(DSPFW9_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
878 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 879 I915_WRITE(DSPHOWM,
15665979
VS		 880 FW_WM(wm->sr.plane >> 9, SR_HI) |
881 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
882 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
883 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
884 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
885 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
886 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
887 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
888 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
889 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 890 } else {
891 I915_WRITE(DSPFW7,
15665979
VS		 892 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
893 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 894 I915_WRITE(DSPHOWM,
15665979
VS		 895 FW_WM(wm->sr.plane >> 9, SR_HI) |
896 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
897 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
898 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
899 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
900 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
901 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 902 }
903
2cb389b7
VS		 904 /* zero (unused) WM1 watermarks */
905 I915_WRITE(DSPFW4, 0);
906 I915_WRITE(DSPFW5, 0);
907 I915_WRITE(DSPFW6, 0);
908 I915_WRITE(DSPHOWM1, 0);
909
ae80152d 910 POSTING_READ(DSPFW1);
0018fda1
VS		 911}
912
15665979
VS		 913#undef FW_WM_VLV
914
6eb1a681
VS		 915enum vlv_wm_level {
916 VLV_WM_LEVEL_PM2,
917 VLV_WM_LEVEL_PM5,
918 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 919};
920
262cd2e1
VS		 921/* latency must be in 0.1us units. */
922static unsigned int vlv_wm_method2(unsigned int pixel_rate,
923 unsigned int pipe_htotal,
924 unsigned int horiz_pixels,
ac484963 925 unsigned int cpp,
262cd2e1
VS		 926 unsigned int latency)
927{
928 unsigned int ret;
929
930 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 931 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 932 ret = DIV_ROUND_UP(ret, 64);
933
934 return ret;
935}
936
bb726519 937static void vlv_setup_wm_latency(struct drm_i915_private *dev_priv)
262cd2e1 938{
262cd2e1
VS		 939 /* all latencies in usec */
940 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
941
58590c14
VS		 942 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
943
262cd2e1
VS		 944 if (IS_CHERRYVIEW(dev_priv)) {
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
946 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 947
948 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 949 }
950}
951
952static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
953 struct intel_crtc *crtc,
954 const struct intel_plane_state *state,
955 int level)
956{
957 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 958 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 959
960 if (dev_priv->wm.pri_latency[level] == 0)
961 return USHRT_MAX;
962
936e71e3 963 if (!state->base.visible)
262cd2e1
VS		 964 return 0;
965
353c8598 966 cpp = state->base.fb->format->cpp[0];
262cd2e1
VS		 967 clock = crtc->config->base.adjusted_mode.crtc_clock;
968 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
969 width = crtc->config->pipe_src_w;
970 if (WARN_ON(htotal == 0))
971 htotal = 1;
972
973 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
974 /*
975 * FIXME the formula gives values that are
976 * too big for the cursor FIFO, and hence we
977 * would never be able to use cursors. For
978 * now just hardcode the watermark.
979 */
980 wm = 63;
981 } else {
ac484963 982 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 983 dev_priv->wm.pri_latency[level] * 10);
984 }
985
986 return min_t(int, wm, USHRT_MAX);
987}
988
54f1b6e1
VS		 989static void vlv_compute_fifo(struct intel_crtc *crtc)
990{
991 struct drm_device *dev = crtc->base.dev;
992 struct vlv_wm_state *wm_state = &crtc->wm_state;
993 struct intel_plane *plane;
994 unsigned int total_rate = 0;
995 const int fifo_size = 512 - 1;
996 int fifo_extra, fifo_left = fifo_size;
997
998 for_each_intel_plane_on_crtc(dev, crtc, plane) {
999 struct intel_plane_state *state =
1000 to_intel_plane_state(plane->base.state);
1001
1002 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1003 continue;
1004
936e71e3 1005 if (state->base.visible) {
54f1b6e1 1006 wm_state->num_active_planes++;
353c8598 1007 total_rate += state->base.fb->format->cpp[0];
54f1b6e1
VS		 1008 }
1009 }
1010
1011 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1012 struct intel_plane_state *state =
1013 to_intel_plane_state(plane->base.state);
1014 unsigned int rate;
1015
1016 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1017 plane->wm.fifo_size = 63;
1018 continue;
1019 }
1020
936e71e3 1021 if (!state->base.visible) {
54f1b6e1
VS		 1022 plane->wm.fifo_size = 0;
1023 continue;
1024 }
1025
353c8598 1026 rate = state->base.fb->format->cpp[0];
54f1b6e1
VS		 1027 plane->wm.fifo_size = fifo_size * rate / total_rate;
1028 fifo_left -= plane->wm.fifo_size;
1029 }
1030
1031 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1032
1033 /* spread the remainder evenly */
1034 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1035 int plane_extra;
1036
1037 if (fifo_left == 0)
1038 break;
1039
1040 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1041 continue;
1042
1043 /* give it all to the first plane if none are active */
1044 if (plane->wm.fifo_size == 0 &&
1045 wm_state->num_active_planes)
1046 continue;
1047
1048 plane_extra = min(fifo_extra, fifo_left);
1049 plane->wm.fifo_size += plane_extra;
1050 fifo_left -= plane_extra;
1051 }
1052
1053 WARN_ON(fifo_left != 0);
1054}
1055
262cd2e1
VS		 1056static void vlv_invert_wms(struct intel_crtc *crtc)
1057{
1058 struct vlv_wm_state *wm_state = &crtc->wm_state;
1059 int level;
1060
1061 for (level = 0; level < wm_state->num_levels; level++) {
1062 struct drm_device *dev = crtc->base.dev;
b7f05d4a
TU		 1063 const int sr_fifo_size =
1064 INTEL_INFO(to_i915(dev))->num_pipes * 512 - 1;
262cd2e1
VS		 1065 struct intel_plane *plane;
1066
1067 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1068 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1069
1070 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1071 switch (plane->base.type) {
1072 int sprite;
1073 case DRM_PLANE_TYPE_CURSOR:
1074 wm_state->wm[level].cursor = plane->wm.fifo_size -
1075 wm_state->wm[level].cursor;
1076 break;
1077 case DRM_PLANE_TYPE_PRIMARY:
1078 wm_state->wm[level].primary = plane->wm.fifo_size -
1079 wm_state->wm[level].primary;
1080 break;
1081 case DRM_PLANE_TYPE_OVERLAY:
1082 sprite = plane->plane;
1083 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1084 wm_state->wm[level].sprite[sprite];
1085 break;
1086 }
1087 }
1088 }
1089}
1090
26e1fe4f 1091static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1092{
1093 struct drm_device *dev = crtc->base.dev;
b7f05d4a 1094 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1095 struct vlv_wm_state *wm_state = &crtc->wm_state;
1096 struct intel_plane *plane;
b7f05d4a 1097 int sr_fifo_size = INTEL_INFO(dev_priv)->num_pipes * 512 - 1;
262cd2e1
VS		 1098 int level;
1099
1100 memset(wm_state, 0, sizeof(*wm_state));
1101
852eb00d 1102 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
b7f05d4a 1103 wm_state->num_levels = dev_priv->wm.max_level + 1;
262cd2e1
VS		 1104
1105 wm_state->num_active_planes = 0;
262cd2e1 1106
54f1b6e1 1107 vlv_compute_fifo(crtc);
262cd2e1
VS		 1108
1109 if (wm_state->num_active_planes != 1)
1110 wm_state->cxsr = false;
1111
1112 if (wm_state->cxsr) {
1113 for (level = 0; level < wm_state->num_levels; level++) {
1114 wm_state->sr[level].plane = sr_fifo_size;
1115 wm_state->sr[level].cursor = 63;
1116 }
1117 }
1118
1119 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1120 struct intel_plane_state *state =
1121 to_intel_plane_state(plane->base.state);
1122
936e71e3 1123 if (!state->base.visible)
262cd2e1
VS		 1124 continue;
1125
1126 /* normal watermarks */
1127 for (level = 0; level < wm_state->num_levels; level++) {
1128 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1129 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1130
1131 /* hack */
1132 if (WARN_ON(level == 0 && wm > max_wm))
1133 wm = max_wm;
1134
1135 if (wm > plane->wm.fifo_size)
1136 break;
1137
1138 switch (plane->base.type) {
1139 int sprite;
1140 case DRM_PLANE_TYPE_CURSOR:
1141 wm_state->wm[level].cursor = wm;
1142 break;
1143 case DRM_PLANE_TYPE_PRIMARY:
1144 wm_state->wm[level].primary = wm;
1145 break;
1146 case DRM_PLANE_TYPE_OVERLAY:
1147 sprite = plane->plane;
1148 wm_state->wm[level].sprite[sprite] = wm;
1149 break;
1150 }
1151 }
1152
1153 wm_state->num_levels = level;
1154
1155 if (!wm_state->cxsr)
1156 continue;
1157
1158 /* maxfifo watermarks */
1159 switch (plane->base.type) {
1160 int sprite, level;
1161 case DRM_PLANE_TYPE_CURSOR:
1162 for (level = 0; level < wm_state->num_levels; level++)
1163 wm_state->sr[level].cursor =
5a37ed0a 1164 wm_state->wm[level].cursor;
262cd2e1
VS		 1165 break;
1166 case DRM_PLANE_TYPE_PRIMARY:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].plane =
1169 min(wm_state->sr[level].plane,
1170 wm_state->wm[level].primary);
1171 break;
1172 case DRM_PLANE_TYPE_OVERLAY:
1173 sprite = plane->plane;
1174 for (level = 0; level < wm_state->num_levels; level++)
1175 wm_state->sr[level].plane =
1176 min(wm_state->sr[level].plane,
1177 wm_state->wm[level].sprite[sprite]);
1178 break;
1179 }
1180 }
1181
1182 /* clear any (partially) filled invalid levels */
b7f05d4a 1183 for (level = wm_state->num_levels; level < dev_priv->wm.max_level + 1; level++) {
262cd2e1
VS		 1184 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1185 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1186 }
1187
1188 vlv_invert_wms(crtc);
1189}
1190
54f1b6e1
VS		 1191#define VLV_FIFO(plane, value) \
1192 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1193
1194static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1195{
1196 struct drm_device *dev = crtc->base.dev;
1197 struct drm_i915_private *dev_priv = to_i915(dev);
1198 struct intel_plane *plane;
1199 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1200
1201 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1202 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1203 WARN_ON(plane->wm.fifo_size != 63);
1204 continue;
1205 }
1206
1207 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1208 sprite0_start = plane->wm.fifo_size;
1209 else if (plane->plane == 0)
1210 sprite1_start = sprite0_start + plane->wm.fifo_size;
1211 else
1212 fifo_size = sprite1_start + plane->wm.fifo_size;
1213 }
1214
1215 WARN_ON(fifo_size != 512 - 1);
1216
1217 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1218 pipe_name(crtc->pipe), sprite0_start,
1219 sprite1_start, fifo_size);
1220
1221 switch (crtc->pipe) {
1222 uint32_t dsparb, dsparb2, dsparb3;
1223 case PIPE_A:
1224 dsparb = I915_READ(DSPARB);
1225 dsparb2 = I915_READ(DSPARB2);
1226
1227 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1228 VLV_FIFO(SPRITEB, 0xff));
1229 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1230 VLV_FIFO(SPRITEB, sprite1_start));
1231
1232 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1233 VLV_FIFO(SPRITEB_HI, 0x1));
1234 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1235 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1236
1237 I915_WRITE(DSPARB, dsparb);
1238 I915_WRITE(DSPARB2, dsparb2);
1239 break;
1240 case PIPE_B:
1241 dsparb = I915_READ(DSPARB);
1242 dsparb2 = I915_READ(DSPARB2);
1243
1244 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1245 VLV_FIFO(SPRITED, 0xff));
1246 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1247 VLV_FIFO(SPRITED, sprite1_start));
1248
1249 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1250 VLV_FIFO(SPRITED_HI, 0xff));
1251 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1252 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1253
1254 I915_WRITE(DSPARB, dsparb);
1255 I915_WRITE(DSPARB2, dsparb2);
1256 break;
1257 case PIPE_C:
1258 dsparb3 = I915_READ(DSPARB3);
1259 dsparb2 = I915_READ(DSPARB2);
1260
1261 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1262 VLV_FIFO(SPRITEF, 0xff));
1263 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1264 VLV_FIFO(SPRITEF, sprite1_start));
1265
1266 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1267 VLV_FIFO(SPRITEF_HI, 0xff));
1268 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1269 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1270
1271 I915_WRITE(DSPARB3, dsparb3);
1272 I915_WRITE(DSPARB2, dsparb2);
1273 break;
1274 default:
1275 break;
1276 }
1277}
1278
1279#undef VLV_FIFO
1280
262cd2e1
VS		 1281static void vlv_merge_wm(struct drm_device *dev,
1282 struct vlv_wm_values *wm)
1283{
1284 struct intel_crtc *crtc;
1285 int num_active_crtcs = 0;
1286
58590c14 1287 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1288 wm->cxsr = true;
1289
1290 for_each_intel_crtc(dev, crtc) {
1291 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1292
1293 if (!crtc->active)
1294 continue;
1295
1296 if (!wm_state->cxsr)
1297 wm->cxsr = false;
1298
1299 num_active_crtcs++;
1300 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1301 }
1302
1303 if (num_active_crtcs != 1)
1304 wm->cxsr = false;
1305
6f9c784b
VS		 1306 if (num_active_crtcs > 1)
1307 wm->level = VLV_WM_LEVEL_PM2;
1308
262cd2e1
VS		 1309 for_each_intel_crtc(dev, crtc) {
1310 struct vlv_wm_state *wm_state = &crtc->wm_state;
1311 enum pipe pipe = crtc->pipe;
1312
1313 if (!crtc->active)
1314 continue;
1315
1316 wm->pipe[pipe] = wm_state->wm[wm->level];
1317 if (wm->cxsr)
1318 wm->sr = wm_state->sr[wm->level];
1319
1320 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1321 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1322 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1323 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1324 }
1325}
1326
432081bc 1327static void vlv_update_wm(struct intel_crtc *crtc)
262cd2e1 1328{
432081bc 1329 struct drm_device *dev = crtc->base.dev;
fac5e23e 1330 struct drm_i915_private *dev_priv = to_i915(dev);
432081bc 1331 enum pipe pipe = crtc->pipe;
262cd2e1
VS		 1332 struct vlv_wm_values wm = {};
1333
432081bc 1334 vlv_compute_wm(crtc);
262cd2e1
VS		 1335 vlv_merge_wm(dev, &wm);
1336
54f1b6e1
VS		 1337 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1338 /* FIXME should be part of crtc atomic commit */
432081bc 1339 vlv_pipe_set_fifo_size(crtc);
262cd2e1 1340 return;
54f1b6e1 1341 }
262cd2e1
VS		 1342
1343 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1344 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1345 chv_set_memory_dvfs(dev_priv, false);
1346
1347 if (wm.level < VLV_WM_LEVEL_PM5 &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1349 chv_set_memory_pm5(dev_priv, false);
1350
852eb00d 1351 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1352 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1353
54f1b6e1 1354 /* FIXME should be part of crtc atomic commit */
432081bc 1355 vlv_pipe_set_fifo_size(crtc);
54f1b6e1 1356
432081bc 1357 vlv_write_wm_values(crtc, &wm);
262cd2e1
VS		 1358
1359 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1360 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1361 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1362 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1363 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1364
852eb00d 1365 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1366 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1367
1368 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1369 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1370 chv_set_memory_pm5(dev_priv, true);
1371
1372 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1374 chv_set_memory_dvfs(dev_priv, true);
1375
1376 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1377}
1378
ae80152d
VS		 1379#define single_plane_enabled(mask) is_power_of_2(mask)
1380
432081bc 1381static void g4x_update_wm(struct intel_crtc *crtc)
b445e3b0 1382{
b91eb5cc 1383 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0 1384 static const int sr_latency_ns = 12000;
b445e3b0
ED		 1385 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1386 int plane_sr, cursor_sr;
1387 unsigned int enabled = 0;
9858425c 1388 bool cxsr_enabled;
b445e3b0 1389
f0ce2310 1390 if (g4x_compute_wm0(dev_priv, PIPE_A,
5aef6003
CW		 1391 &g4x_wm_info, pessimal_latency_ns,
1392 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1393 &planea_wm, &cursora_wm))
51cea1f4 1394 enabled |= 1 << PIPE_A;
b445e3b0 1395
f0ce2310 1396 if (g4x_compute_wm0(dev_priv, PIPE_B,
5aef6003
CW		 1397 &g4x_wm_info, pessimal_latency_ns,
1398 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1399 &planeb_wm, &cursorb_wm))
51cea1f4 1400 enabled |= 1 << PIPE_B;
b445e3b0 1401
b445e3b0 1402 if (single_plane_enabled(enabled) &&
f0ce2310 1403 g4x_compute_srwm(dev_priv, ffs(enabled) - 1,
b445e3b0
ED		 1404 sr_latency_ns,
1405 &g4x_wm_info,
1406 &g4x_cursor_wm_info,
52bd02d8 1407 &plane_sr, &cursor_sr)) {
9858425c 1408 cxsr_enabled = true;
52bd02d8 1409 } else {
9858425c 1410 cxsr_enabled = false;
5209b1f4 1411 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1412 plane_sr = cursor_sr = 0;
1413 }
b445e3b0 1414
a5043453
VS		 1415 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1416 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1417 planea_wm, cursora_wm,
1418 planeb_wm, cursorb_wm,
1419 plane_sr, cursor_sr);
1420
1421 I915_WRITE(DSPFW1,
f4998963
VS		 1422 FW_WM(plane_sr, SR) |
1423 FW_WM(cursorb_wm, CURSORB) |
1424 FW_WM(planeb_wm, PLANEB) |
1425 FW_WM(planea_wm, PLANEA));
b445e3b0 1426 I915_WRITE(DSPFW2,
8c919b28 1427 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1428 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1429 /* HPLL off in SR has some issues on G4x... disable it */
1430 I915_WRITE(DSPFW3,
8c919b28 1431 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1432 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1433
1434 if (cxsr_enabled)
1435 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1436}
1437
432081bc 1438static void i965_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1439{
ffc7a76b 1440 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1441 struct intel_crtc *crtc;
b445e3b0
ED		 1442 int srwm = 1;
1443 int cursor_sr = 16;
9858425c 1444 bool cxsr_enabled;
b445e3b0
ED		 1445
1446 /* Calc sr entries for one plane configs */
ffc7a76b 1447 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1448 if (crtc) {
1449 /* self-refresh has much higher latency */
1450 static const int sr_latency_ns = 12000;
efc2611e
VS		 1451 const struct drm_display_mode *adjusted_mode =
1452 &crtc->config->base.adjusted_mode;
1453 const struct drm_framebuffer *fb =
1454 crtc->base.primary->state->fb;
241bfc38 1455 int clock = adjusted_mode->crtc_clock;
fec8cba3 1456 int htotal = adjusted_mode->crtc_htotal;
efc2611e 1457 int hdisplay = crtc->config->pipe_src_w;
353c8598 1458 int cpp = fb->format->cpp[0];
b445e3b0
ED		 1459 unsigned long line_time_us;
1460 int entries;
1461
922044c9 1462 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1463
1464 /* Use ns/us then divide to preserve precision */
1465 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1466 cpp * hdisplay;
b445e3b0
ED		 1467 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1468 srwm = I965_FIFO_SIZE - entries;
1469 if (srwm < 0)
1470 srwm = 1;
1471 srwm &= 0x1ff;
1472 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1473 entries, srwm);
1474
1475 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
efc2611e 1476 cpp * crtc->base.cursor->state->crtc_w;
b445e3b0
ED		 1477 entries = DIV_ROUND_UP(entries,
1478 i965_cursor_wm_info.cacheline_size);
1479 cursor_sr = i965_cursor_wm_info.fifo_size -
1480 (entries + i965_cursor_wm_info.guard_size);
1481
1482 if (cursor_sr > i965_cursor_wm_info.max_wm)
1483 cursor_sr = i965_cursor_wm_info.max_wm;
1484
1485 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1486 "cursor %d\n", srwm, cursor_sr);
1487
9858425c 1488 cxsr_enabled = true;
b445e3b0 1489 } else {
9858425c 1490 cxsr_enabled = false;
b445e3b0 1491 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1492 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1493 }
1494
1495 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1496 srwm);
1497
1498 /* 965 has limitations... */
f4998963
VS		 1499 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1500 FW_WM(8, CURSORB) |
1501 FW_WM(8, PLANEB) |
1502 FW_WM(8, PLANEA));
1503 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1504 FW_WM(8, PLANEC_OLD));
b445e3b0 1505 /* update cursor SR watermark */
f4998963 1506 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1507
1508 if (cxsr_enabled)
1509 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1510}
1511
f4998963
VS		 1512#undef FW_WM
1513
432081bc 1514static void i9xx_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1515{
ffc7a76b 1516 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
b445e3b0
ED		 1517 const struct intel_watermark_params *wm_info;
1518 uint32_t fwater_lo;
1519 uint32_t fwater_hi;
1520 int cwm, srwm = 1;
1521 int fifo_size;
1522 int planea_wm, planeb_wm;
efc2611e 1523 struct intel_crtc *crtc, *enabled = NULL;
b445e3b0 1524
a9097be4 1525 if (IS_I945GM(dev_priv))
b445e3b0 1526 wm_info = &i945_wm_info;
5db94019 1527 else if (!IS_GEN2(dev_priv))
b445e3b0
ED		 1528 wm_info = &i915_wm_info;
1529 else
9d539105 1530 wm_info = &i830_a_wm_info;
b445e3b0 1531
ef0f5e93 1532 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 0);
b91eb5cc 1533 crtc = intel_get_crtc_for_plane(dev_priv, 0);
efc2611e
VS		 1534 if (intel_crtc_active(crtc)) {
1535 const struct drm_display_mode *adjusted_mode =
1536 &crtc->config->base.adjusted_mode;
1537 const struct drm_framebuffer *fb =
1538 crtc->base.primary->state->fb;
1539 int cpp;
1540
5db94019 1541 if (IS_GEN2(dev_priv))
b9e0bda3 1542 cpp = 4;
efc2611e 1543 else
353c8598 1544 cpp = fb->format->cpp[0];
b9e0bda3 1545
241bfc38 1546 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1547 wm_info, fifo_size, cpp,
5aef6003 1548 pessimal_latency_ns);
b445e3b0 1549 enabled = crtc;
9d539105 1550 } else {
b445e3b0 1551 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1552 if (planea_wm > (long)wm_info->max_wm)
1553 planea_wm = wm_info->max_wm;
1554 }
1555
5db94019 1556 if (IS_GEN2(dev_priv))
9d539105 1557 wm_info = &i830_bc_wm_info;
b445e3b0 1558
ef0f5e93 1559 fifo_size = dev_priv->display.get_fifo_size(dev_priv, 1);
b91eb5cc 1560 crtc = intel_get_crtc_for_plane(dev_priv, 1);
efc2611e
VS		 1561 if (intel_crtc_active(crtc)) {
1562 const struct drm_display_mode *adjusted_mode =
1563 &crtc->config->base.adjusted_mode;
1564 const struct drm_framebuffer *fb =
1565 crtc->base.primary->state->fb;
1566 int cpp;
1567
5db94019 1568 if (IS_GEN2(dev_priv))
b9e0bda3 1569 cpp = 4;
efc2611e 1570 else
353c8598 1571 cpp = fb->format->cpp[0];
b9e0bda3 1572
241bfc38 1573 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1574 wm_info, fifo_size, cpp,
5aef6003 1575 pessimal_latency_ns);
b445e3b0
ED		 1576 if (enabled == NULL)
1577 enabled = crtc;
1578 else
1579 enabled = NULL;
9d539105 1580 } else {
b445e3b0 1581 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1582 if (planeb_wm > (long)wm_info->max_wm)
1583 planeb_wm = wm_info->max_wm;
1584 }
b445e3b0
ED		 1585
1586 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1587
50a0bc90 1588 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1589 struct drm_i915_gem_object *obj;
2ab1bc9d 1590
efc2611e 1591 obj = intel_fb_obj(enabled->base.primary->state->fb);
2ab1bc9d
DV		 1592
1593 /* self-refresh seems busted with untiled */
3e510a8e 1594 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1595 enabled = NULL;
1596 }
1597
b445e3b0
ED		 1598 /*
1599 * Overlay gets an aggressive default since video jitter is bad.
1600 */
1601 cwm = 2;
1602
1603 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1604 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1605
1606 /* Calc sr entries for one plane configs */
03427fcb 1607 if (HAS_FW_BLC(dev_priv) && enabled) {
b445e3b0
ED		 1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
efc2611e
VS		 1610 const struct drm_display_mode *adjusted_mode =
1611 &enabled->config->base.adjusted_mode;
1612 const struct drm_framebuffer *fb =
1613 enabled->base.primary->state->fb;
241bfc38 1614 int clock = adjusted_mode->crtc_clock;
fec8cba3 1615 int htotal = adjusted_mode->crtc_htotal;
efc2611e
VS		 1616 int hdisplay = enabled->config->pipe_src_w;
1617 int cpp;
b445e3b0
ED		 1618 unsigned long line_time_us;
1619 int entries;
1620
50a0bc90 1621 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056 1622 cpp = 4;
efc2611e 1623 else
353c8598 1624 cpp = fb->format->cpp[0];
2d1b5056 1625
922044c9 1626 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1627
1628 /* Use ns/us then divide to preserve precision */
1629 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1630 cpp * hdisplay;
b445e3b0
ED		 1631 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1632 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1633 srwm = wm_info->fifo_size - entries;
1634 if (srwm < 0)
1635 srwm = 1;
1636
50a0bc90 1637 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1638 I915_WRITE(FW_BLC_SELF,
1639 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1640 else
b445e3b0
ED		 1641 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1642 }
1643
1644 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1645 planea_wm, planeb_wm, cwm, srwm);
1646
1647 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1648 fwater_hi = (cwm & 0x1f);
1649
1650 /* Set request length to 8 cachelines per fetch */
1651 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1652 fwater_hi = fwater_hi | (1 << 8);
1653
1654 I915_WRITE(FW_BLC, fwater_lo);
1655 I915_WRITE(FW_BLC2, fwater_hi);
1656
5209b1f4
ID		 1657 if (enabled)
1658 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1659}
1660
432081bc 1661static void i845_update_wm(struct intel_crtc *unused_crtc)
b445e3b0 1662{
ffc7a76b 1663 struct drm_i915_private *dev_priv = to_i915(unused_crtc->base.dev);
efc2611e 1664 struct intel_crtc *crtc;
241bfc38 1665 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1666 uint32_t fwater_lo;
1667 int planea_wm;
1668
ffc7a76b 1669 crtc = single_enabled_crtc(dev_priv);
b445e3b0
ED		 1670 if (crtc == NULL)
1671 return;
1672
efc2611e 1673 adjusted_mode = &crtc->config->base.adjusted_mode;
241bfc38 1674 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1675 &i845_wm_info,
ef0f5e93 1676 dev_priv->display.get_fifo_size(dev_priv, 0),
5aef6003 1677 4, pessimal_latency_ns);
b445e3b0
ED		 1678 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1679 fwater_lo |= (3<<8) | planea_wm;
1680
1681 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1682
1683 I915_WRITE(FW_BLC, fwater_lo);
1684}
1685
8cfb3407 1686uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1687{
fd4daa9c 1688 uint32_t pixel_rate;
801bcfff 1689
8cfb3407 1690 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1691
1692 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1693 * adjust the pixel_rate here. */
1694
8cfb3407 1695 if (pipe_config->pch_pfit.enabled) {
801bcfff 1696 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1697 uint32_t pfit_size = pipe_config->pch_pfit.size;
1698
1699 pipe_w = pipe_config->pipe_src_w;
1700 pipe_h = pipe_config->pipe_src_h;
801bcfff 1701
801bcfff
PZ		 1702 pfit_w = (pfit_size >> 16) & 0xFFFF;
1703 pfit_h = pfit_size & 0xFFFF;
1704 if (pipe_w < pfit_w)
1705 pipe_w = pfit_w;
1706 if (pipe_h < pfit_h)
1707 pipe_h = pfit_h;
1708
15126882
MR		 1709 if (WARN_ON(!pfit_w || !pfit_h))
1710 return pixel_rate;
1711
801bcfff
PZ		 1712 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1713 pfit_w * pfit_h);
1714 }
1715
1716 return pixel_rate;
1717}
1718
37126462 1719/* latency must be in 0.1us units. */
ac484963 1720static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1721{
1722 uint64_t ret;
1723
3312ba65
VS		 1724 if (WARN(latency == 0, "Latency value missing\n"))
1725 return UINT_MAX;
1726
ac484963 1727 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1728 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1729
1730 return ret;
1731}
1732
37126462 1733/* latency must be in 0.1us units. */
23297044 1734static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1735 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1736 uint32_t latency)
1737{
1738 uint32_t ret;
1739
3312ba65
VS		 1740 if (WARN(latency == 0, "Latency value missing\n"))
1741 return UINT_MAX;
15126882
MR		 1742 if (WARN_ON(!pipe_htotal))
1743 return UINT_MAX;
3312ba65 1744
801bcfff 1745 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1746 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1747 ret = DIV_ROUND_UP(ret, 64) + 2;
1748 return ret;
1749}
1750
23297044 1751static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1752 uint8_t cpp)
cca32e9a 1753{
15126882
MR		 1754 /*
1755 * Neither of these should be possible since this function shouldn't be
1756 * called if the CRTC is off or the plane is invisible. But let's be
1757 * extra paranoid to avoid a potential divide-by-zero if we screw up
1758 * elsewhere in the driver.
1759 */
ac484963 1760 if (WARN_ON(!cpp))
15126882
MR		 1761 return 0;
1762 if (WARN_ON(!horiz_pixels))
1763 return 0;
1764
ac484963 1765 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1766}
1767
820c1980 1768struct ilk_wm_maximums {
cca32e9a
PZ		 1769 uint16_t pri;
1770 uint16_t spr;
1771 uint16_t cur;
1772 uint16_t fbc;
1773};
1774
37126462
VS		 1775/*
1776 * For both WM_PIPE and WM_LP.
1777 * mem_value must be in 0.1us units.
1778 */
7221fc33 1779static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1780 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1781 uint32_t mem_value,
1782 bool is_lp)
801bcfff 1783{
cca32e9a 1784 uint32_t method1, method2;
8305494e 1785 int cpp;
cca32e9a 1786
936e71e3 1787 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1788 return 0;
1789
353c8598 1790 cpp = pstate->base.fb->format->cpp[0];
8305494e 1791
ac484963 1792 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1793
1794 if (!is_lp)
1795 return method1;
1796
7221fc33
MR		 1797 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1798 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1799 drm_rect_width(&pstate->base.dst),
ac484963 1800 cpp, mem_value);
cca32e9a
PZ		 1801
1802 return min(method1, method2);
801bcfff
PZ		 1803}
1804
37126462
VS		 1805/*
1806 * For both WM_PIPE and WM_LP.
1807 * mem_value must be in 0.1us units.
1808 */
7221fc33 1809static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1810 const struct intel_plane_state *pstate,
801bcfff
PZ		 1811 uint32_t mem_value)
1812{
1813 uint32_t method1, method2;
8305494e 1814 int cpp;
801bcfff 1815
936e71e3 1816 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1817 return 0;
1818
353c8598 1819 cpp = pstate->base.fb->format->cpp[0];
8305494e 1820
ac484963 1821 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1822 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1823 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1824 drm_rect_width(&pstate->base.dst),
ac484963 1825 cpp, mem_value);
801bcfff
PZ		 1826 return min(method1, method2);
1827}
1828
37126462
VS		 1829/*
1830 * For both WM_PIPE and WM_LP.
1831 * mem_value must be in 0.1us units.
1832 */
7221fc33 1833static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1834 const struct intel_plane_state *pstate,
801bcfff
PZ		 1835 uint32_t mem_value)
1836{
b2435692
MR		 1837 /*
1838 * We treat the cursor plane as always-on for the purposes of watermark
1839 * calculation. Until we have two-stage watermark programming merged,
1840 * this is necessary to avoid flickering.
1841 */
1842 int cpp = 4;
936e71e3 1843 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1844
b2435692 1845 if (!cstate->base.active)
801bcfff
PZ		 1846 return 0;
1847
7221fc33
MR		 1848 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1849 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1850 width, cpp, mem_value);
801bcfff
PZ		 1851}
1852
cca32e9a 1853/* Only for WM_LP. */
7221fc33 1854static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1855 const struct intel_plane_state *pstate,
1fda9882 1856 uint32_t pri_val)
cca32e9a 1857{
8305494e 1858 int cpp;
43d59eda 1859
936e71e3 1860 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1861 return 0;
1862
353c8598 1863 cpp = pstate->base.fb->format->cpp[0];
8305494e 1864
936e71e3 1865 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1866}
1867
175fded1
TU		 1868static unsigned int
1869ilk_display_fifo_size(const struct drm_i915_private *dev_priv)
158ae64f 1870{
175fded1 1871 if (INTEL_GEN(dev_priv) >= 8)
416f4727 1872 return 3072;
175fded1 1873 else if (INTEL_GEN(dev_priv) >= 7)
158ae64f
VS		 1874 return 768;
1875 else
1876 return 512;
1877}
1878
175fded1
TU		 1879static unsigned int
1880ilk_plane_wm_reg_max(const struct drm_i915_private *dev_priv,
1881 int level, bool is_sprite)
4e975081 1882{
175fded1 1883 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1884 /* BDW primary/sprite plane watermarks */
1885 return level == 0 ? 255 : 2047;
175fded1 1886 else if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1887 /* IVB/HSW primary/sprite plane watermarks */
1888 return level == 0 ? 127 : 1023;
1889 else if (!is_sprite)
1890 /* ILK/SNB primary plane watermarks */
1891 return level == 0 ? 127 : 511;
1892 else
1893 /* ILK/SNB sprite plane watermarks */
1894 return level == 0 ? 63 : 255;
1895}
1896
175fded1
TU		 1897static unsigned int
1898ilk_cursor_wm_reg_max(const struct drm_i915_private *dev_priv, int level)
4e975081 1899{
175fded1 1900 if (INTEL_GEN(dev_priv) >= 7)
4e975081
VS		 1901 return level == 0 ? 63 : 255;
1902 else
1903 return level == 0 ? 31 : 63;
1904}
1905
175fded1 1906static unsigned int ilk_fbc_wm_reg_max(const struct drm_i915_private *dev_priv)
4e975081 1907{
175fded1 1908 if (INTEL_GEN(dev_priv) >= 8)
4e975081
VS		 1909 return 31;
1910 else
1911 return 15;
1912}
1913
158ae64f
VS		 1914/* Calculate the maximum primary/sprite plane watermark */
1915static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1916 int level,
240264f4 1917 const struct intel_wm_config *config,
158ae64f
VS		 1918 enum intel_ddb_partitioning ddb_partitioning,
1919 bool is_sprite)
1920{
175fded1
TU		 1921 struct drm_i915_private *dev_priv = to_i915(dev);
1922 unsigned int fifo_size = ilk_display_fifo_size(dev_priv);
158ae64f
VS		 1923
1924 /* if sprites aren't enabled, sprites get nothing */
240264f4 1925 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1926 return 0;
1927
1928 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1929 if (level == 0 || config->num_pipes_active > 1) {
175fded1 1930 fifo_size /= INTEL_INFO(dev_priv)->num_pipes;
158ae64f
VS		 1931
1932 /*
1933 * For some reason the non self refresh
1934 * FIFO size is only half of the self
1935 * refresh FIFO size on ILK/SNB.
1936 */
175fded1 1937 if (INTEL_GEN(dev_priv) <= 6)
158ae64f
VS		 1938 fifo_size /= 2;
1939 }
1940
240264f4 1941 if (config->sprites_enabled) {
158ae64f
VS		 1942 /* level 0 is always calculated with 1:1 split */
1943 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1944 if (is_sprite)
1945 fifo_size *= 5;
1946 fifo_size /= 6;
1947 } else {
1948 fifo_size /= 2;
1949 }
1950 }
1951
1952 /* clamp to max that the registers can hold */
175fded1 1953 return min(fifo_size, ilk_plane_wm_reg_max(dev_priv, level, is_sprite));
158ae64f
VS		 1954}
1955
1956/* Calculate the maximum cursor plane watermark */
1957static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1958 int level,
1959 const struct intel_wm_config *config)
158ae64f
VS		 1960{
1961 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1962 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1963 return 64;
1964
1965 /* otherwise just report max that registers can hold */
175fded1 1966 return ilk_cursor_wm_reg_max(to_i915(dev), level);
158ae64f
VS		 1967}
1968
d34ff9c6 1969static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1970 int level,
1971 const struct intel_wm_config *config,
1972 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1973 struct ilk_wm_maximums *max)
158ae64f 1974{
240264f4
VS		 1975 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1976 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1977 max->cur = ilk_cursor_wm_max(dev, level, config);
175fded1 1978 max->fbc = ilk_fbc_wm_reg_max(to_i915(dev));
158ae64f
VS		 1979}
1980
175fded1 1981static void ilk_compute_wm_reg_maximums(const struct drm_i915_private *dev_priv,
a3cb4048
VS		 1982 int level,
1983 struct ilk_wm_maximums *max)
1984{
175fded1
TU		 1985 max->pri = ilk_plane_wm_reg_max(dev_priv, level, false);
1986 max->spr = ilk_plane_wm_reg_max(dev_priv, level, true);
1987 max->cur = ilk_cursor_wm_reg_max(dev_priv, level);
1988 max->fbc = ilk_fbc_wm_reg_max(dev_priv);
a3cb4048
VS		 1989}
1990
d9395655 1991static bool ilk_validate_wm_level(int level,
820c1980 1992 const struct ilk_wm_maximums *max,
d9395655 1993 struct intel_wm_level *result)
a9786a11
VS		 1994{
1995 bool ret;
1996
1997 /* already determined to be invalid? */
1998 if (!result->enable)
1999 return false;
2000
2001 result->enable = result->pri_val <= max->pri &&
2002 result->spr_val <= max->spr &&
2003 result->cur_val <= max->cur;
2004
2005 ret = result->enable;
2006
2007 /*
2008 * HACK until we can pre-compute everything,
2009 * and thus fail gracefully if LP0 watermarks
2010 * are exceeded...
2011 */
2012 if (level == 0 && !result->enable) {
2013 if (result->pri_val > max->pri)
2014 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2015 level, result->pri_val, max->pri);
2016 if (result->spr_val > max->spr)
2017 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2018 level, result->spr_val, max->spr);
2019 if (result->cur_val > max->cur)
2020 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2021 level, result->cur_val, max->cur);
2022
2023 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2024 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2025 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2026 result->enable = true;
2027 }
2028
a9786a11
VS		 2029 return ret;
2030}
2031
d34ff9c6 2032static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2033 const struct intel_crtc *intel_crtc,
6f5ddd17 2034 int level,
7221fc33 2035 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2036 struct intel_plane_state *pristate,
2037 struct intel_plane_state *sprstate,
2038 struct intel_plane_state *curstate,
1fd527cc 2039 struct intel_wm_level *result)
6f5ddd17
VS		 2040{
2041 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2042 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2043 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2044
2045 /* WM1+ latency values stored in 0.5us units */
2046 if (level > 0) {
2047 pri_latency *= 5;
2048 spr_latency *= 5;
2049 cur_latency *= 5;
2050 }
2051
e3bddded
ML		 2052 if (pristate) {
2053 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2054 pri_latency, level);
2055 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2056 }
2057
2058 if (sprstate)
2059 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2060
2061 if (curstate)
2062 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2063
6f5ddd17
VS		 2064 result->enable = true;
2065}
2066
801bcfff 2067static uint32_t
532f7a7f 2068hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2069{
532f7a7f
VS		 2070 const struct intel_atomic_state *intel_state =
2071 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2072 const struct drm_display_mode *adjusted_mode =
2073 &cstate->base.adjusted_mode;
85a02deb 2074 u32 linetime, ips_linetime;
1f8eeabf 2075
ee91a159
MR		 2076 if (!cstate->base.active)
2077 return 0;
2078 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2079 return 0;
532f7a7f 2080 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2081 return 0;
1011d8c4 2082
1f8eeabf
ED		 2083 /* The WM are computed with base on how long it takes to fill a single
2084 * row at the given clock rate, multiplied by 8.
2085 * */
124abe07
VS		 2086 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2087 adjusted_mode->crtc_clock);
2088 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2089 intel_state->cdclk);
1f8eeabf 2090
801bcfff
PZ		 2091 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2092 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2093}
2094
bb726519
VS		 2095static void intel_read_wm_latency(struct drm_i915_private *dev_priv,
2096 uint16_t wm[8])
12b134df 2097{
5db94019 2098 if (IS_GEN9(dev_priv)) {
2af30a5c 2099 uint32_t val;
4f947386 2100 int ret, i;
5db94019 2101 int level, max_level = ilk_wm_max_level(dev_priv);
2af30a5c
PB		 2102
2103 /* read the first set of memory latencies[0:3] */
2104 val = 0; /* data0 to be programmed to 0 for first set */
2105 mutex_lock(&dev_priv->rps.hw_lock);
2106 ret = sandybridge_pcode_read(dev_priv,
2107 GEN9_PCODE_READ_MEM_LATENCY,
2108 &val);
2109 mutex_unlock(&dev_priv->rps.hw_lock);
2110
2111 if (ret) {
2112 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2113 return;
2114 }
2115
2116 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2117 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2118 GEN9_MEM_LATENCY_LEVEL_MASK;
2119 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2120 GEN9_MEM_LATENCY_LEVEL_MASK;
2121 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2122 GEN9_MEM_LATENCY_LEVEL_MASK;
2123
2124 /* read the second set of memory latencies[4:7] */
2125 val = 1; /* data0 to be programmed to 1 for second set */
2126 mutex_lock(&dev_priv->rps.hw_lock);
2127 ret = sandybridge_pcode_read(dev_priv,
2128 GEN9_PCODE_READ_MEM_LATENCY,
2129 &val);
2130 mutex_unlock(&dev_priv->rps.hw_lock);
2131 if (ret) {
2132 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2133 return;
2134 }
2135
2136 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2137 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2138 GEN9_MEM_LATENCY_LEVEL_MASK;
2139 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2140 GEN9_MEM_LATENCY_LEVEL_MASK;
2141 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2142 GEN9_MEM_LATENCY_LEVEL_MASK;
2143
0727e40a
PZ		 2144 /*
2145 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2146 * need to be disabled. We make sure to sanitize the values out
2147 * of the punit to satisfy this requirement.
2148 */
2149 for (level = 1; level <= max_level; level++) {
2150 if (wm[level] == 0) {
2151 for (i = level + 1; i <= max_level; i++)
2152 wm[i] = 0;
2153 break;
2154 }
2155 }
2156
367294be 2157 /*
6f97235b
DL		 2158 * WaWmMemoryReadLatency:skl
2159 *
367294be 2160 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2161 * to add 2us to the various latency levels we retrieve from the
2162 * punit when level 0 response data us 0us.
367294be 2163 */
0727e40a
PZ		 2164 if (wm[0] == 0) {
2165 wm[0] += 2;
2166 for (level = 1; level <= max_level; level++) {
2167 if (wm[level] == 0)
2168 break;
367294be 2169 wm[level] += 2;
4f947386 2170 }
0727e40a
PZ		 2171 }
2172
8652744b 2173 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2174 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2175
2176 wm[0] = (sskpd >> 56) & 0xFF;
2177 if (wm[0] == 0)
2178 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2179 wm[1] = (sskpd >> 4) & 0xFF;
2180 wm[2] = (sskpd >> 12) & 0xFF;
2181 wm[3] = (sskpd >> 20) & 0x1FF;
2182 wm[4] = (sskpd >> 32) & 0x1FF;
bb726519 2183 } else if (INTEL_GEN(dev_priv) >= 6) {
63cf9a13
VS		 2184 uint32_t sskpd = I915_READ(MCH_SSKPD);
2185
2186 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2187 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2188 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2189 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
bb726519 2190 } else if (INTEL_GEN(dev_priv) >= 5) {
3a88d0ac
VS		 2191 uint32_t mltr = I915_READ(MLTR_ILK);
2192
2193 /* ILK primary LP0 latency is 700 ns */
2194 wm[0] = 7;
2195 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2196 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2197 }
2198}
2199
5db94019
TU		 2200static void intel_fixup_spr_wm_latency(struct drm_i915_private *dev_priv,
2201 uint16_t wm[5])
53615a5e
VS		 2202{
2203 /* ILK sprite LP0 latency is 1300 ns */
5db94019 2204 if (IS_GEN5(dev_priv))
53615a5e
VS		 2205 wm[0] = 13;
2206}
2207
fd6b8f43
TU		 2208static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2209 uint16_t wm[5])
53615a5e
VS		 2210{
2211 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2212 if (IS_GEN5(dev_priv))
53615a5e
VS		 2213 wm[0] = 13;
2214
2215 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2216 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2217 wm[3] *= 2;
2218}
2219
5db94019 2220int ilk_wm_max_level(const struct drm_i915_private *dev_priv)
26ec971e 2221{
26ec971e 2222 /* how many WM levels are we expecting */
8652744b 2223 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2224 return 7;
8652744b 2225 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2226 return 4;
8652744b 2227 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2228 return 3;
26ec971e 2229 else
ad0d6dc4
VS		 2230 return 2;
2231}
7526ed79 2232
5db94019 2233static void intel_print_wm_latency(struct drm_i915_private *dev_priv,
ad0d6dc4 2234 const char *name,
2af30a5c 2235 const uint16_t wm[8])
ad0d6dc4 2236{
5db94019 2237 int level, max_level = ilk_wm_max_level(dev_priv);
26ec971e
VS		 2238
2239 for (level = 0; level <= max_level; level++) {
2240 unsigned int latency = wm[level];
2241
2242 if (latency == 0) {
2243 DRM_ERROR("%s WM%d latency not provided\n",
2244 name, level);
2245 continue;
2246 }
2247
2af30a5c
PB		 2248 /*
2249 * - latencies are in us on gen9.
2250 * - before then, WM1+ latency values are in 0.5us units
2251 */
5db94019 2252 if (IS_GEN9(dev_priv))
2af30a5c
PB		 2253 latency *= 10;
2254 else if (level > 0)
26ec971e
VS		 2255 latency *= 5;
2256
2257 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2258 name, level, wm[level],
2259 latency / 10, latency % 10);
2260 }
2261}
2262
e95a2f75
VS		 2263static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2264 uint16_t wm[5], uint16_t min)
2265{
5db94019 2266 int level, max_level = ilk_wm_max_level(dev_priv);
e95a2f75
VS		 2267
2268 if (wm[0] >= min)
2269 return false;
2270
2271 wm[0] = max(wm[0], min);
2272 for (level = 1; level <= max_level; level++)
2273 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2274
2275 return true;
2276}
2277
bb726519 2278static void snb_wm_latency_quirk(struct drm_i915_private *dev_priv)
e95a2f75 2279{
e95a2f75
VS		 2280 bool changed;
2281
2282 /*
2283 * The BIOS provided WM memory latency values are often
2284 * inadequate for high resolution displays. Adjust them.
2285 */
2286 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2287 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2288 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2289
2290 if (!changed)
2291 return;
2292
2293 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
5db94019
TU		 2294 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2295 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2296 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2297}
2298
bb726519 2299static void ilk_setup_wm_latency(struct drm_i915_private *dev_priv)
53615a5e 2300{
bb726519 2301 intel_read_wm_latency(dev_priv, dev_priv->wm.pri_latency);
53615a5e
VS		 2302
2303 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2304 sizeof(dev_priv->wm.pri_latency));
2305 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2306 sizeof(dev_priv->wm.pri_latency));
2307
5db94019 2308 intel_fixup_spr_wm_latency(dev_priv, dev_priv->wm.spr_latency);
fd6b8f43 2309 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e 2310
5db94019
TU		 2311 intel_print_wm_latency(dev_priv, "Primary", dev_priv->wm.pri_latency);
2312 intel_print_wm_latency(dev_priv, "Sprite", dev_priv->wm.spr_latency);
2313 intel_print_wm_latency(dev_priv, "Cursor", dev_priv->wm.cur_latency);
e95a2f75 2314
5db94019 2315 if (IS_GEN6(dev_priv))
bb726519 2316 snb_wm_latency_quirk(dev_priv);
53615a5e
VS		 2317}
2318
bb726519 2319static void skl_setup_wm_latency(struct drm_i915_private *dev_priv)
2af30a5c 2320{
bb726519 2321 intel_read_wm_latency(dev_priv, dev_priv->wm.skl_latency);
5db94019 2322 intel_print_wm_latency(dev_priv, "Gen9 Plane", dev_priv->wm.skl_latency);
2af30a5c
PB		 2323}
2324
ed4a6a7c
MR		 2325static bool ilk_validate_pipe_wm(struct drm_device *dev,
2326 struct intel_pipe_wm *pipe_wm)
2327{
2328 /* LP0 watermark maximums depend on this pipe alone */
2329 const struct intel_wm_config config = {
2330 .num_pipes_active = 1,
2331 .sprites_enabled = pipe_wm->sprites_enabled,
2332 .sprites_scaled = pipe_wm->sprites_scaled,
2333 };
2334 struct ilk_wm_maximums max;
2335
2336 /* LP0 watermarks always use 1/2 DDB partitioning */
2337 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2338
2339 /* At least LP0 must be valid */
2340 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2341 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2342 return false;
2343 }
2344
2345 return true;
2346}
2347
0b2ae6d7 2348/* Compute new watermarks for the pipe */
e3bddded 2349static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2350{
e3bddded
ML		 2351 struct drm_atomic_state *state = cstate->base.state;
2352 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2353 struct intel_pipe_wm *pipe_wm;
e3bddded 2354 struct drm_device *dev = state->dev;
fac5e23e 2355 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2356 struct intel_plane *intel_plane;
86c8bbbe 2357 struct intel_plane_state *pristate = NULL;
43d59eda 2358 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2359 struct intel_plane_state *curstate = NULL;
5db94019 2360 int level, max_level = ilk_wm_max_level(dev_priv), usable_level;
820c1980 2361 struct ilk_wm_maximums max;
0b2ae6d7 2362
e8f1f02e 2363 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2364
43d59eda 2365 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2366 struct intel_plane_state *ps;
2367
2368 ps = intel_atomic_get_existing_plane_state(state,
2369 intel_plane);
2370 if (!ps)
2371 continue;
86c8bbbe
MR		 2372
2373 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2374 pristate = ps;
86c8bbbe 2375 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2376 sprstate = ps;
86c8bbbe 2377 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2378 curstate = ps;
43d59eda
MR		 2379 }
2380
ed4a6a7c 2381 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2382 if (sprstate) {
936e71e3
VS		 2383 pipe_wm->sprites_enabled = sprstate->base.visible;
2384 pipe_wm->sprites_scaled = sprstate->base.visible &&
2385 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2386 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2387 }
2388
d81f04c5
ML		 2389 usable_level = max_level;
2390
7b39a0b7 2391 /* ILK/SNB: LP2+ watermarks only w/o sprites */
175fded1 2392 if (INTEL_GEN(dev_priv) <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2393 usable_level = 1;
7b39a0b7
VS		 2394
2395 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2396 if (pipe_wm->sprites_scaled)
d81f04c5 2397 usable_level = 0;
7b39a0b7 2398
86c8bbbe 2399 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2400 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2401
2402 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2403 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2404
8652744b 2405 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2406 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2407
ed4a6a7c 2408 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2409 return -EINVAL;
a3cb4048 2410
175fded1 2411 ilk_compute_wm_reg_maximums(dev_priv, 1, &max);
a3cb4048
VS		 2412
2413 for (level = 1; level <= max_level; level++) {
71f0a626 2414 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2415
86c8bbbe 2416 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2417 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2418
2419 /*
2420 * Disable any watermark level that exceeds the
2421 * register maximums since such watermarks are
2422 * always invalid.
2423 */
71f0a626
ML		 2424 if (level > usable_level)
2425 continue;
2426
2427 if (ilk_validate_wm_level(level, &max, wm))
2428 pipe_wm->wm[level] = *wm;
2429 else
d81f04c5 2430 usable_level = level;
a3cb4048
VS		 2431 }
2432
86c8bbbe 2433 return 0;
0b2ae6d7
VS		 2434}
2435
ed4a6a7c
MR		 2436/*
2437 * Build a set of 'intermediate' watermark values that satisfy both the old
2438 * state and the new state. These can be programmed to the hardware
2439 * immediately.
2440 */
2441static int ilk_compute_intermediate_wm(struct drm_device *dev,
2442 struct intel_crtc *intel_crtc,
2443 struct intel_crtc_state *newstate)
2444{
e8f1f02e 2445 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c 2446 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
5db94019 2447 int level, max_level = ilk_wm_max_level(to_i915(dev));
ed4a6a7c
MR		 2448
2449 /*
2450 * Start with the final, target watermarks, then combine with the
2451 * currently active watermarks to get values that are safe both before
2452 * and after the vblank.
2453 */
e8f1f02e 2454 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2455 a->pipe_enabled |= b->pipe_enabled;
2456 a->sprites_enabled |= b->sprites_enabled;
2457 a->sprites_scaled |= b->sprites_scaled;
2458
2459 for (level = 0; level <= max_level; level++) {
2460 struct intel_wm_level *a_wm = &a->wm[level];
2461 const struct intel_wm_level *b_wm = &b->wm[level];
2462
2463 a_wm->enable &= b_wm->enable;
2464 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2465 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2466 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2467 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2468 }
2469
2470 /*
2471 * We need to make sure that these merged watermark values are
2472 * actually a valid configuration themselves. If they're not,
2473 * there's no safe way to transition from the old state to
2474 * the new state, so we need to fail the atomic transaction.
2475 */
2476 if (!ilk_validate_pipe_wm(dev, a))
2477 return -EINVAL;
2478
2479 /*
2480 * If our intermediate WM are identical to the final WM, then we can
2481 * omit the post-vblank programming; only update if it's different.
2482 */
e8f1f02e 2483 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2484 newstate->wm.need_postvbl_update = false;
2485
2486 return 0;
2487}
2488
0b2ae6d7
VS		 2489/*
2490 * Merge the watermarks from all active pipes for a specific level.
2491 */
2492static void ilk_merge_wm_level(struct drm_device *dev,
2493 int level,
2494 struct intel_wm_level *ret_wm)
2495{
2496 const struct intel_crtc *intel_crtc;
2497
d52fea5b
VS		 2498 ret_wm->enable = true;
2499
d3fcc808 2500 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2501 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2502 const struct intel_wm_level *wm = &active->wm[level];
2503
2504 if (!active->pipe_enabled)
2505 continue;
0b2ae6d7 2506
d52fea5b
VS		 2507 /*
2508 * The watermark values may have been used in the past,
2509 * so we must maintain them in the registers for some
2510 * time even if the level is now disabled.
2511 */
0b2ae6d7 2512 if (!wm->enable)
d52fea5b 2513 ret_wm->enable = false;
0b2ae6d7
VS		 2514
2515 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2516 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2517 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2518 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2519 }
0b2ae6d7
VS		 2520}
2521
2522/*
2523 * Merge all low power watermarks for all active pipes.
2524 */
2525static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2526 const struct intel_wm_config *config,
820c1980 2527 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2528 struct intel_pipe_wm *merged)
2529{
fac5e23e 2530 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 2531 int level, max_level = ilk_wm_max_level(dev_priv);
d52fea5b 2532 int last_enabled_level = max_level;
0b2ae6d7 2533
0ba22e26 2534 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2535 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2536 config->num_pipes_active > 1)
1204d5ba 2537 last_enabled_level = 0;
0ba22e26 2538
6c8b6c28 2539 /* ILK: FBC WM must be disabled always */
175fded1 2540 merged->fbc_wm_enabled = INTEL_GEN(dev_priv) >= 6;
0b2ae6d7
VS		 2541
2542 /* merge each WM1+ level */
2543 for (level = 1; level <= max_level; level++) {
2544 struct intel_wm_level *wm = &merged->wm[level];
2545
2546 ilk_merge_wm_level(dev, level, wm);
2547
d52fea5b
VS		 2548 if (level > last_enabled_level)
2549 wm->enable = false;
2550 else if (!ilk_validate_wm_level(level, max, wm))
2551 /* make sure all following levels get disabled */
2552 last_enabled_level = level - 1;
0b2ae6d7
VS		 2553
2554 /*
2555 * The spec says it is preferred to disable
2556 * FBC WMs instead of disabling a WM level.
2557 */
2558 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2559 if (wm->enable)
2560 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2561 wm->fbc_val = 0;
2562 }
2563 }
6c8b6c28
VS		 2564
2565 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2566 /*
2567 * FIXME this is racy. FBC might get enabled later.
2568 * What we should check here is whether FBC can be
2569 * enabled sometime later.
2570 */
5db94019 2571 if (IS_GEN5(dev_priv) && !merged->fbc_wm_enabled &&
0e631adc 2572 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2573 for (level = 2; level <= max_level; level++) {
2574 struct intel_wm_level *wm = &merged->wm[level];
2575
2576 wm->enable = false;
2577 }
2578 }
0b2ae6d7
VS		 2579}
2580
b380ca3c
VS		 2581static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2582{
2583 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2584 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2585}
2586
a68d68ee
VS		 2587/* The value we need to program into the WM_LPx latency field */
2588static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2589{
fac5e23e 2590 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2591
8652744b 2592 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2593 return 2 * level;
2594 else
2595 return dev_priv->wm.pri_latency[level];
2596}
2597
820c1980 2598static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2599 const struct intel_pipe_wm *merged,
609cedef 2600 enum intel_ddb_partitioning partitioning,
820c1980 2601 struct ilk_wm_values *results)
801bcfff 2602{
175fded1 2603 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7
VS		 2604 struct intel_crtc *intel_crtc;
2605 int level, wm_lp;
cca32e9a 2606
0362c781 2607 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2608 results->partitioning = partitioning;
cca32e9a 2609
0b2ae6d7 2610 /* LP1+ register values */
cca32e9a 2611 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2612 const struct intel_wm_level *r;
801bcfff 2613
b380ca3c 2614 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2615
0362c781 2616 r = &merged->wm[level];
cca32e9a 2617
d52fea5b
VS		 2618 /*
2619 * Maintain the watermark values even if the level is
2620 * disabled. Doing otherwise could cause underruns.
2621 */
2622 results->wm_lp[wm_lp - 1] =
a68d68ee 2623 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2624 (r->pri_val << WM1_LP_SR_SHIFT) |
2625 r->cur_val;
2626
d52fea5b
VS		 2627 if (r->enable)
2628 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2629
175fded1 2630 if (INTEL_GEN(dev_priv) >= 8)
416f4727
VS		 2631 results->wm_lp[wm_lp - 1] |=
2632 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2633 else
2634 results->wm_lp[wm_lp - 1] |=
2635 r->fbc_val << WM1_LP_FBC_SHIFT;
2636
d52fea5b
VS		 2637 /*
2638 * Always set WM1S_LP_EN when spr_val != 0, even if the
2639 * level is disabled. Doing otherwise could cause underruns.
2640 */
175fded1 2641 if (INTEL_GEN(dev_priv) <= 6 && r->spr_val) {
6cef2b8a
VS		 2642 WARN_ON(wm_lp != 1);
2643 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2644 } else
2645 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2646 }
801bcfff 2647
0b2ae6d7 2648 /* LP0 register values */
d3fcc808 2649 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2650 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2651 const struct intel_wm_level *r =
2652 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2653
2654 if (WARN_ON(!r->enable))
2655 continue;
2656
ed4a6a7c 2657 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2658
0b2ae6d7
VS		 2659 results->wm_pipe[pipe] =
2660 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2661 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2662 r->cur_val;
801bcfff
PZ		 2663 }
2664}
2665
861f3389
PZ		 2666/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2667 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2668static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2669 struct intel_pipe_wm *r1,
2670 struct intel_pipe_wm *r2)
861f3389 2671{
5db94019 2672 int level, max_level = ilk_wm_max_level(to_i915(dev));
198a1e9b 2673 int level1 = 0, level2 = 0;
861f3389 2674
198a1e9b
VS		 2675 for (level = 1; level <= max_level; level++) {
2676 if (r1->wm[level].enable)
2677 level1 = level;
2678 if (r2->wm[level].enable)
2679 level2 = level;
861f3389
PZ		 2680 }
2681
198a1e9b
VS		 2682 if (level1 == level2) {
2683 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2684 return r2;
2685 else
2686 return r1;
198a1e9b 2687 } else if (level1 > level2) {
861f3389
PZ		 2688 return r1;
2689 } else {
2690 return r2;
2691 }
2692}
2693
49a687c4
VS		 2694/* dirty bits used to track which watermarks need changes */
2695#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2696#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2697#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2698#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2699#define WM_DIRTY_FBC (1 << 24)
2700#define WM_DIRTY_DDB (1 << 25)
2701
055e393f 2702static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2703 const struct ilk_wm_values *old,
2704 const struct ilk_wm_values *new)
49a687c4
VS		 2705{
2706 unsigned int dirty = 0;
2707 enum pipe pipe;
2708 int wm_lp;
2709
055e393f 2710 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2711 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2712 dirty |= WM_DIRTY_LINETIME(pipe);
2713 /* Must disable LP1+ watermarks too */
2714 dirty |= WM_DIRTY_LP_ALL;
2715 }
2716
2717 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2718 dirty |= WM_DIRTY_PIPE(pipe);
2719 /* Must disable LP1+ watermarks too */
2720 dirty |= WM_DIRTY_LP_ALL;
2721 }
2722 }
2723
2724 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2725 dirty |= WM_DIRTY_FBC;
2726 /* Must disable LP1+ watermarks too */
2727 dirty |= WM_DIRTY_LP_ALL;
2728 }
2729
2730 if (old->partitioning != new->partitioning) {
2731 dirty |= WM_DIRTY_DDB;
2732 /* Must disable LP1+ watermarks too */
2733 dirty |= WM_DIRTY_LP_ALL;
2734 }
2735
2736 /* LP1+ watermarks already deemed dirty, no need to continue */
2737 if (dirty & WM_DIRTY_LP_ALL)
2738 return dirty;
2739
2740 /* Find the lowest numbered LP1+ watermark in need of an update... */
2741 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2742 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2743 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2744 break;
2745 }
2746
2747 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2748 for (; wm_lp <= 3; wm_lp++)
2749 dirty |= WM_DIRTY_LP(wm_lp);
2750
2751 return dirty;
2752}
2753
8553c18e
VS		 2754static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2755 unsigned int dirty)
801bcfff 2756{
820c1980 2757 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2758 bool changed = false;
801bcfff 2759
facd619b
VS		 2760 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2761 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2762 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2763 changed = true;
facd619b
VS		 2764 }
2765 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2766 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2767 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2768 changed = true;
facd619b
VS		 2769 }
2770 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2771 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2772 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2773 changed = true;
facd619b 2774 }
801bcfff 2775
facd619b
VS		 2776 /*
2777 * Don't touch WM1S_LP_EN here.
2778 * Doing so could cause underruns.
2779 */
6cef2b8a 2780
8553c18e
VS		 2781 return changed;
2782}
2783
2784/*
2785 * The spec says we shouldn't write when we don't need, because every write
2786 * causes WMs to be re-evaluated, expending some power.
2787 */
820c1980
ID		 2788static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2789 struct ilk_wm_values *results)
8553c18e 2790{
820c1980 2791 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2792 unsigned int dirty;
2793 uint32_t val;
2794
055e393f 2795 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2796 if (!dirty)
2797 return;
2798
2799 _ilk_disable_lp_wm(dev_priv, dirty);
2800
49a687c4 2801 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2802 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2803 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2804 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2805 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2806 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2807
49a687c4 2808 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2809 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2810 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2811 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2812 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2813 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2814
49a687c4 2815 if (dirty & WM_DIRTY_DDB) {
8652744b 2816 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2817 val = I915_READ(WM_MISC);
2818 if (results->partitioning == INTEL_DDB_PART_1_2)
2819 val &= ~WM_MISC_DATA_PARTITION_5_6;
2820 else
2821 val |= WM_MISC_DATA_PARTITION_5_6;
2822 I915_WRITE(WM_MISC, val);
2823 } else {
2824 val = I915_READ(DISP_ARB_CTL2);
2825 if (results->partitioning == INTEL_DDB_PART_1_2)
2826 val &= ~DISP_DATA_PARTITION_5_6;
2827 else
2828 val |= DISP_DATA_PARTITION_5_6;
2829 I915_WRITE(DISP_ARB_CTL2, val);
2830 }
1011d8c4
PZ		 2831 }
2832
49a687c4 2833 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2834 val = I915_READ(DISP_ARB_CTL);
2835 if (results->enable_fbc_wm)
2836 val &= ~DISP_FBC_WM_DIS;
2837 else
2838 val |= DISP_FBC_WM_DIS;
2839 I915_WRITE(DISP_ARB_CTL, val);
2840 }
2841
954911eb
ID		 2842 if (dirty & WM_DIRTY_LP(1) &&
2843 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2844 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2845
175fded1 2846 if (INTEL_GEN(dev_priv) >= 7) {
6cef2b8a
VS		 2847 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2848 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2849 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2850 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2851 }
801bcfff 2852
facd619b 2853 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2854 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2855 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2856 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2857 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2858 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2859
2860 dev_priv->wm.hw = *results;
801bcfff
PZ		 2861}
2862
ed4a6a7c 2863bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2864{
fac5e23e 2865 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2866
2867 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2868}
2869
656d1b89 2870#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2871
024c9045
MR		 2872/*
2873 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2874 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2875 * other universal planes are in indices 1..n. Note that this may leave unused
2876 * indices between the top "sprite" plane and the cursor.
2877 */
2878static int
2879skl_wm_plane_id(const struct intel_plane *plane)
2880{
2881 switch (plane->base.type) {
2882 case DRM_PLANE_TYPE_PRIMARY:
2883 return 0;
2884 case DRM_PLANE_TYPE_CURSOR:
2885 return PLANE_CURSOR;
2886 case DRM_PLANE_TYPE_OVERLAY:
2887 return plane->plane + 1;
2888 default:
2889 MISSING_CASE(plane->base.type);
2890 return plane->plane;
2891 }
2892}
2893
ee3d532f
PZ		 2894/*
2895 * FIXME: We still don't have the proper code detect if we need to apply the WA,
2896 * so assume we'll always need it in order to avoid underruns.
2897 */
2898static bool skl_needs_memory_bw_wa(struct intel_atomic_state *state)
2899{
2900 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
2901
2902 if (IS_SKYLAKE(dev_priv) || IS_BROXTON(dev_priv) ||
2903 IS_KABYLAKE(dev_priv))
2904 return true;
2905
2906 return false;
2907}
2908
56feca91
PZ		 2909static bool
2910intel_has_sagv(struct drm_i915_private *dev_priv)
2911{
6e3100ec
PZ		 2912 if (IS_KABYLAKE(dev_priv))
2913 return true;
2914
2915 if (IS_SKYLAKE(dev_priv) &&
2916 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2917 return true;
2918
2919 return false;
56feca91
PZ		 2920}
2921
656d1b89
L		 2922/*
2923 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2924 * depending on power and performance requirements. The display engine access
2925 * to system memory is blocked during the adjustment time. Because of the
2926 * blocking time, having this enabled can cause full system hangs and/or pipe
2927 * underruns if we don't meet all of the following requirements:
2928 *
2929 * - <= 1 pipe enabled
2930 * - All planes can enable watermarks for latencies >= SAGV engine block time
2931 * - We're not using an interlaced display configuration
2932 */
2933int
16dcdc4e 2934intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2935{
2936 int ret;
2937
56feca91
PZ		 2938 if (!intel_has_sagv(dev_priv))
2939 return 0;
2940
2941 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2942 return 0;
2943
2944 DRM_DEBUG_KMS("Enabling the SAGV\n");
2945 mutex_lock(&dev_priv->rps.hw_lock);
2946
2947 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2948 GEN9_SAGV_ENABLE);
2949
2950 /* We don't need to wait for the SAGV when enabling */
2951 mutex_unlock(&dev_priv->rps.hw_lock);
2952
2953 /*
2954 * Some skl systems, pre-release machines in particular,
2955 * don't actually have an SAGV.
2956 */
6e3100ec 2957 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2958 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2959 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2960 return 0;
2961 } else if (ret < 0) {
2962 DRM_ERROR("Failed to enable the SAGV\n");
2963 return ret;
2964 }
2965
16dcdc4e 2966 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2967 return 0;
2968}
2969
2970static int
16dcdc4e 2971intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2972{
2973 int ret;
2974 uint32_t temp = GEN9_SAGV_DISABLE;
2975
2976 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2977 &temp);
2978 if (ret)
2979 return ret;
2980 else
2981 return temp & GEN9_SAGV_IS_DISABLED;
2982}
2983
2984int
16dcdc4e 2985intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2986{
2987 int ret, result;
2988
56feca91
PZ		 2989 if (!intel_has_sagv(dev_priv))
2990 return 0;
2991
2992 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2993 return 0;
2994
2995 DRM_DEBUG_KMS("Disabling the SAGV\n");
2996 mutex_lock(&dev_priv->rps.hw_lock);
2997
2998 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2999 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 3000 mutex_unlock(&dev_priv->rps.hw_lock);
3001
3002 if (ret == -ETIMEDOUT) {
3003 DRM_ERROR("Request to disable SAGV timed out\n");
3004 return -ETIMEDOUT;
3005 }
3006
3007 /*
3008 * Some skl systems, pre-release machines in particular,
3009 * don't actually have an SAGV.
3010 */
6e3100ec 3011 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 3012 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 3013 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 3014 return 0;
3015 } else if (result < 0) {
3016 DRM_ERROR("Failed to disable the SAGV\n");
3017 return result;
3018 }
3019
16dcdc4e 3020 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 3021 return 0;
3022}
3023
16dcdc4e 3024bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3025{
3026 struct drm_device *dev = state->dev;
3027 struct drm_i915_private *dev_priv = to_i915(dev);
3028 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
ee3d532f
PZ		 3029 struct intel_crtc *crtc;
3030 struct intel_plane *plane;
d8c0fafc 3031 struct intel_crtc_state *cstate;
3032 struct skl_plane_wm *wm;
656d1b89 3033 enum pipe pipe;
d8c0fafc 3034 int level, latency;
656d1b89 3035
56feca91
PZ		 3036 if (!intel_has_sagv(dev_priv))
3037 return false;
3038
656d1b89
L		 3039 /*
3040 * SKL workaround: bspec recommends we disable the SAGV when we have
3041 * more then one pipe enabled
3042 *
3043 * If there are no active CRTCs, no additional checks need be performed
3044 */
3045 if (hweight32(intel_state->active_crtcs) == 0)
3046 return true;
3047 else if (hweight32(intel_state->active_crtcs) > 1)
3048 return false;
3049
3050 /* Since we're now guaranteed to only have one active CRTC... */
3051 pipe = ffs(intel_state->active_crtcs) - 1;
98187836 3052 crtc = intel_get_crtc_for_pipe(dev_priv, pipe);
d8c0fafc 3053 cstate = to_intel_crtc_state(crtc->base.state);
656d1b89 3054
c89cadd5 3055 if (crtc->base.state->adjusted_mode.flags & DRM_MODE_FLAG_INTERLACE)
656d1b89
L		 3056 return false;
3057
ee3d532f 3058 for_each_intel_plane_on_crtc(dev, crtc, plane) {
d8c0fafc 3059 wm = &cstate->wm.skl.optimal.planes[skl_wm_plane_id(plane)];
ee3d532f 3060
656d1b89 3061 /* Skip this plane if it's not enabled */
d8c0fafc 3062 if (!wm->wm[0].plane_en)
656d1b89
L		 3063 continue;
3064
3065 /* Find the highest enabled wm level for this plane */
5db94019 3066 for (level = ilk_wm_max_level(dev_priv);
d8c0fafc 3067 !wm->wm[level].plane_en; --level)
656d1b89
L		 3068 { }
3069
ee3d532f
PZ		 3070 latency = dev_priv->wm.skl_latency[level];
3071
3072 if (skl_needs_memory_bw_wa(intel_state) &&
bae781b2 3073 plane->base.state->fb->modifier ==
ee3d532f
PZ		 3074 I915_FORMAT_MOD_X_TILED)
3075 latency += 15;
3076
656d1b89
L		 3077 /*
3078 * If any of the planes on this pipe don't enable wm levels
3079 * that incur memory latencies higher then 30µs we can't enable
3080 * the SAGV
3081 */
ee3d532f 3082 if (latency < SKL_SAGV_BLOCK_TIME)
656d1b89
L		 3083 return false;
3084 }
3085
3086 return true;
3087}
3088
b9cec075
DL		 3089static void
3090skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3091 const struct intel_crtc_state *cstate,
c107acfe
MR		 3092 struct skl_ddb_entry *alloc, /* out */
3093 int *num_active /* out */)
b9cec075 3094{
c107acfe
MR		 3095 struct drm_atomic_state *state = cstate->base.state;
3096 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3097 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3098 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3099 unsigned int pipe_size, ddb_size;
3100 int nth_active_pipe;
c107acfe 3101
a6d3460e 3102 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3103 alloc->start = 0;
3104 alloc->end = 0;
a6d3460e 3105 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3106 return;
3107 }
3108
a6d3460e
MR		 3109 if (intel_state->active_pipe_changes)
3110 *num_active = hweight32(intel_state->active_crtcs);
3111 else
3112 *num_active = hweight32(dev_priv->active_crtcs);
3113
6f3fff60
D		 3114 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3115 WARN_ON(ddb_size == 0);
b9cec075
DL		 3116
3117 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3118
c107acfe 3119 /*
a6d3460e
MR		 3120 * If the state doesn't change the active CRTC's, then there's
3121 * no need to recalculate; the existing pipe allocation limits
3122 * should remain unchanged. Note that we're safe from racing
3123 * commits since any racing commit that changes the active CRTC
3124 * list would need to grab _all_ crtc locks, including the one
3125 * we currently hold.
c107acfe 3126 */
a6d3460e 3127 if (!intel_state->active_pipe_changes) {
512b5527
ML		 3128 /*
3129 * alloc may be cleared by clear_intel_crtc_state,
3130 * copy from old state to be sure
3131 */
3132 *alloc = to_intel_crtc_state(for_crtc->state)->wm.skl.ddb;
a6d3460e 3133 return;
c107acfe 3134 }
a6d3460e
MR		 3135
3136 nth_active_pipe = hweight32(intel_state->active_crtcs &
3137 (drm_crtc_mask(for_crtc) - 1));
3138 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3139 alloc->start = nth_active_pipe * ddb_size / *num_active;
3140 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3141}
3142
c107acfe 3143static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3144{
c107acfe 3145 if (num_active == 1)
b9cec075
DL		 3146 return 32;
3147
3148 return 8;
3149}
3150
a269c583
DL		 3151static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3152{
3153 entry->start = reg & 0x3ff;
3154 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3155 if (entry->end)
3156 entry->end += 1;
a269c583
DL		 3157}
3158
08db6652
DL		 3159void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3160 struct skl_ddb_allocation *ddb /* out */)
a269c583 3161{
a269c583
DL		 3162 enum pipe pipe;
3163 int plane;
3164 u32 val;
3165
b10f1b20
ML		 3166 memset(ddb, 0, sizeof(*ddb));
3167
a269c583 3168 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3169 enum intel_display_power_domain power_domain;
3170
3171 power_domain = POWER_DOMAIN_PIPE(pipe);
3172 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3173 continue;
3174
8b364b41 3175 for_each_universal_plane(dev_priv, pipe, plane) {
a269c583
DL		 3176 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3177 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3178 val);
3179 }
3180
3181 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3182 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3183 val);
4d800030
ID		 3184
3185 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3186 }
3187}
3188
9c2f7a9d
KM		 3189/*
3190 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3191 * The bspec defines downscale amount as:
3192 *
3193 * """
3194 * Horizontal down scale amount = maximum[1, Horizontal source size /
3195 * Horizontal destination size]
3196 * Vertical down scale amount = maximum[1, Vertical source size /
3197 * Vertical destination size]
3198 * Total down scale amount = Horizontal down scale amount *
3199 * Vertical down scale amount
3200 * """
3201 *
3202 * Return value is provided in 16.16 fixed point form to retain fractional part.
3203 * Caller should take care of dividing & rounding off the value.
3204 */
3205static uint32_t
3206skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3207{
3208 uint32_t downscale_h, downscale_w;
3209 uint32_t src_w, src_h, dst_w, dst_h;
3210
936e71e3 3211 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3212 return DRM_PLANE_HELPER_NO_SCALING;
3213
3214 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3215 src_w = drm_rect_width(&pstate->base.src);
3216 src_h = drm_rect_height(&pstate->base.src);
3217 dst_w = drm_rect_width(&pstate->base.dst);
3218 dst_h = drm_rect_height(&pstate->base.dst);
bd2ef25d 3219 if (drm_rotation_90_or_270(pstate->base.rotation))
9c2f7a9d
KM		 3220 swap(dst_w, dst_h);
3221
3222 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3223 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3224
3225 /* Provide result in 16.16 fixed point */
3226 return (uint64_t)downscale_w * downscale_h >> 16;
3227}
3228
b9cec075 3229static unsigned int
024c9045
MR		 3230skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3231 const struct drm_plane_state *pstate,
3232 int y)
b9cec075 3233{
a280f7dd 3234 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
8d19d7d9 3235 uint32_t down_scale_amount, data_rate;
a280f7dd 3236 uint32_t width = 0, height = 0;
8305494e
VS		 3237 struct drm_framebuffer *fb;
3238 u32 format;
a1de91e5 3239
936e71e3 3240 if (!intel_pstate->base.visible)
a1de91e5 3241 return 0;
8305494e
VS		 3242
3243 fb = pstate->fb;
3244 format = fb->pixel_format;
3245
a1de91e5
MR		 3246 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3247 return 0;
3248 if (y && format != DRM_FORMAT_NV12)
3249 return 0;
a280f7dd 3250
936e71e3
VS		 3251 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3252 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3253
bd2ef25d 3254 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd 3255 swap(width, height);
2cd601c6
CK		 3256
3257 /* for planar format */
a1de91e5 3258 if (format == DRM_FORMAT_NV12) {
2cd601c6 3259 if (y) /* y-plane data rate */
8d19d7d9 3260 data_rate = width * height *
353c8598 3261 fb->format->cpp[0];
2cd601c6 3262 else /* uv-plane data rate */
8d19d7d9 3263 data_rate = (width / 2) * (height / 2) *
353c8598 3264 fb->format->cpp[1];
8d19d7d9
KM		 3265 } else {
3266 /* for packed formats */
353c8598 3267 data_rate = width * height * fb->format->cpp[0];
2cd601c6
CK		 3268 }
3269
8d19d7d9
KM		 3270 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3271
3272 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3273}
3274
3275/*
3276 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3277 * a 8192x4096@32bpp framebuffer:
3278 * 3 * 4096 * 8192 * 4 < 2^32
3279 */
3280static unsigned int
1e6ee542
ML		 3281skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate,
3282 unsigned *plane_data_rate,
3283 unsigned *plane_y_data_rate)
b9cec075 3284{
9c74d826
MR		 3285 struct drm_crtc_state *cstate = &intel_cstate->base;
3286 struct drm_atomic_state *state = cstate->state;
c8fe32c1 3287 struct drm_plane *plane;
024c9045 3288 const struct intel_plane *intel_plane;
c8fe32c1 3289 const struct drm_plane_state *pstate;
a1de91e5 3290 unsigned int rate, total_data_rate = 0;
9c74d826 3291 int id;
a6d3460e
MR		 3292
3293 if (WARN_ON(!state))
3294 return 0;
b9cec075 3295
a1de91e5 3296 /* Calculate and cache data rate for each plane */
c8fe32c1 3297 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, cstate) {
a6d3460e
MR		 3298 id = skl_wm_plane_id(to_intel_plane(plane));
3299 intel_plane = to_intel_plane(plane);
3300
a6d3460e
MR		 3301 /* packed/uv */
3302 rate = skl_plane_relative_data_rate(intel_cstate,
3303 pstate, 0);
1e6ee542
ML		 3304 plane_data_rate[id] = rate;
3305
3306 total_data_rate += rate;
a6d3460e
MR		 3307
3308 /* y-plane */
3309 rate = skl_plane_relative_data_rate(intel_cstate,
3310 pstate, 1);
1e6ee542 3311 plane_y_data_rate[id] = rate;
024c9045 3312
1e6ee542 3313 total_data_rate += rate;
b9cec075
DL		 3314 }
3315
3316 return total_data_rate;
3317}
3318
cbcfd14b
KM		 3319static uint16_t
3320skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3321 const int y)
3322{
3323 struct drm_framebuffer *fb = pstate->fb;
3324 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3325 uint32_t src_w, src_h;
3326 uint32_t min_scanlines = 8;
3327 uint8_t plane_bpp;
3328
3329 if (WARN_ON(!fb))
3330 return 0;
3331
3332 /* For packed formats, no y-plane, return 0 */
3333 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3334 return 0;
3335
3336 /* For Non Y-tile return 8-blocks */
bae781b2
VS		 3337 if (fb->modifier != I915_FORMAT_MOD_Y_TILED &&
3338 fb->modifier != I915_FORMAT_MOD_Yf_TILED)
cbcfd14b
KM		 3339 return 8;
3340
936e71e3
VS		 3341 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3342 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b 3343
bd2ef25d 3344 if (drm_rotation_90_or_270(pstate->rotation))
cbcfd14b
KM		 3345 swap(src_w, src_h);
3346
3347 /* Halve UV plane width and height for NV12 */
3348 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3349 src_w /= 2;
3350 src_h /= 2;
3351 }
3352
3353 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
353c8598 3354 plane_bpp = fb->format->cpp[1];
cbcfd14b 3355 else
353c8598 3356 plane_bpp = fb->format->cpp[0];
cbcfd14b 3357
bd2ef25d 3358 if (drm_rotation_90_or_270(pstate->rotation)) {
cbcfd14b
KM		 3359 switch (plane_bpp) {
3360 case 1:
3361 min_scanlines = 32;
3362 break;
3363 case 2:
3364 min_scanlines = 16;
3365 break;
3366 case 4:
3367 min_scanlines = 8;
3368 break;
3369 case 8:
3370 min_scanlines = 4;
3371 break;
3372 default:
3373 WARN(1, "Unsupported pixel depth %u for rotation",
3374 plane_bpp);
3375 min_scanlines = 32;
3376 }
3377 }
3378
3379 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3380}
3381
49845a7a
ML		 3382static void
3383skl_ddb_calc_min(const struct intel_crtc_state *cstate, int num_active,
3384 uint16_t *minimum, uint16_t *y_minimum)
3385{
3386 const struct drm_plane_state *pstate;
3387 struct drm_plane *plane;
3388
3389 drm_atomic_crtc_state_for_each_plane_state(plane, pstate, &cstate->base) {
3390 struct intel_plane *intel_plane = to_intel_plane(plane);
3391 int id = skl_wm_plane_id(intel_plane);
3392
3393 if (id == PLANE_CURSOR)
3394 continue;
3395
3396 if (!pstate->visible)
3397 continue;
3398
3399 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3400 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
3401 }
3402
3403 minimum[PLANE_CURSOR] = skl_cursor_allocation(num_active);
3404}
3405
c107acfe 3406static int
024c9045 3407skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3408 struct skl_ddb_allocation *ddb /* out */)
3409{
c107acfe 3410 struct drm_atomic_state *state = cstate->base.state;
024c9045 3411 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3412 struct drm_device *dev = crtc->dev;
3413 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3414 enum pipe pipe = intel_crtc->pipe;
ce0ba283 3415 struct skl_ddb_entry *alloc = &cstate->wm.skl.ddb;
49845a7a 3416 uint16_t alloc_size, start;
fefdd810
ML		 3417 uint16_t minimum[I915_MAX_PLANES] = {};
3418 uint16_t y_minimum[I915_MAX_PLANES] = {};
b9cec075 3419 unsigned int total_data_rate;
c107acfe
MR		 3420 int num_active;
3421 int id, i;
1e6ee542
ML		 3422 unsigned plane_data_rate[I915_MAX_PLANES] = {};
3423 unsigned plane_y_data_rate[I915_MAX_PLANES] = {};
b9cec075 3424
5a920b85
PZ		 3425 /* Clear the partitioning for disabled planes. */
3426 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3427 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3428
a6d3460e
MR		 3429 if (WARN_ON(!state))
3430 return 0;
3431
c107acfe 3432 if (!cstate->base.active) {
ce0ba283 3433 alloc->start = alloc->end = 0;
c107acfe
MR		 3434 return 0;
3435 }
3436
a6d3460e 3437 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3438 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3439 if (alloc_size == 0) {
3440 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3441 return 0;
b9cec075
DL		 3442 }
3443
49845a7a 3444 skl_ddb_calc_min(cstate, num_active, minimum, y_minimum);
a6d3460e 3445
49845a7a
ML		 3446 /*
3447 * 1. Allocate the mininum required blocks for each active plane
3448 * and allocate the cursor, it doesn't require extra allocation
3449 * proportional to the data rate.
3450 */
80958155 3451
49845a7a 3452 for (i = 0; i < I915_MAX_PLANES; i++) {
c107acfe
MR		 3453 alloc_size -= minimum[i];
3454 alloc_size -= y_minimum[i];
80958155
DL		 3455 }
3456
49845a7a
ML		 3457 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - minimum[PLANE_CURSOR];
3458 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
3459
b9cec075 3460 /*
80958155
DL		 3461 * 2. Distribute the remaining space in proportion to the amount of
3462 * data each plane needs to fetch from memory.
b9cec075
DL		 3463 *
3464 * FIXME: we may not allocate every single block here.
3465 */
1e6ee542
ML		 3466 total_data_rate = skl_get_total_relative_data_rate(cstate,
3467 plane_data_rate,
3468 plane_y_data_rate);
a1de91e5 3469 if (total_data_rate == 0)
c107acfe 3470 return 0;
b9cec075 3471
34bb56af 3472 start = alloc->start;
1e6ee542 3473 for (id = 0; id < I915_MAX_PLANES; id++) {
2cd601c6
CK		 3474 unsigned int data_rate, y_data_rate;
3475 uint16_t plane_blocks, y_plane_blocks = 0;
b9cec075 3476
49845a7a
ML		 3477 if (id == PLANE_CURSOR)
3478 continue;
3479
1e6ee542 3480 data_rate = plane_data_rate[id];
b9cec075
DL		 3481
3482 /*
2cd601c6 3483 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3484 * promote the expression to 64 bits to avoid overflowing, the
3485 * result is < available as data_rate / total_data_rate < 1
3486 */
024c9045 3487 plane_blocks = minimum[id];
80958155
DL		 3488 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3489 total_data_rate);
b9cec075 3490
c107acfe
MR		 3491 /* Leave disabled planes at (0,0) */
3492 if (data_rate) {
3493 ddb->plane[pipe][id].start = start;
3494 ddb->plane[pipe][id].end = start + plane_blocks;
3495 }
b9cec075
DL		 3496
3497 start += plane_blocks;
2cd601c6
CK		 3498
3499 /*
3500 * allocation for y_plane part of planar format:
3501 */
1e6ee542 3502 y_data_rate = plane_y_data_rate[id];
a1de91e5
MR		 3503
3504 y_plane_blocks = y_minimum[id];
3505 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3506 total_data_rate);
2cd601c6 3507
c107acfe
MR		 3508 if (y_data_rate) {
3509 ddb->y_plane[pipe][id].start = start;
3510 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3511 }
a1de91e5
MR		 3512
3513 start += y_plane_blocks;
b9cec075
DL		 3514 }
3515
c107acfe 3516 return 0;
b9cec075
DL		 3517}
3518
2d41c0b5
PB		 3519/*
3520 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3521 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3522 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3523 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3524*/
ac484963 3525static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3526{
3527 uint32_t wm_intermediate_val, ret;
3528
3529 if (latency == 0)
3530 return UINT_MAX;
3531
ac484963 3532 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3533 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3534
3535 return ret;
3536}
3537
3538static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3539 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3540{
d4c2aa60 3541 uint32_t ret;
d4c2aa60 3542 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3543
3544 if (latency == 0)
3545 return UINT_MAX;
3546
2d41c0b5
PB		 3547 wm_intermediate_val = latency * pixel_rate;
3548 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3549 plane_blocks_per_line;
2d41c0b5
PB		 3550
3551 return ret;
3552}
3553
9c2f7a9d
KM		 3554static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3555 struct intel_plane_state *pstate)
3556{
3557 uint64_t adjusted_pixel_rate;
3558 uint64_t downscale_amount;
3559 uint64_t pixel_rate;
3560
3561 /* Shouldn't reach here on disabled planes... */
936e71e3 3562 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3563 return 0;
3564
3565 /*
3566 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3567 * with additional adjustments for plane-specific scaling.
3568 */
cfd7e3a2 3569 adjusted_pixel_rate = ilk_pipe_pixel_rate(cstate);
9c2f7a9d
KM		 3570 downscale_amount = skl_plane_downscale_amount(pstate);
3571
3572 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3573 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3574
3575 return pixel_rate;
3576}
3577
55994c2c
MR		 3578static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3579 struct intel_crtc_state *cstate,
3580 struct intel_plane_state *intel_pstate,
3581 uint16_t ddb_allocation,
3582 int level,
3583 uint16_t *out_blocks, /* out */
3584 uint8_t *out_lines, /* out */
3585 bool *enabled /* out */)
2d41c0b5 3586{
33815fa5
MR		 3587 struct drm_plane_state *pstate = &intel_pstate->base;
3588 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3589 uint32_t latency = dev_priv->wm.skl_latency[level];
3590 uint32_t method1, method2;
3591 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3592 uint32_t res_blocks, res_lines;
3593 uint32_t selected_result;
ac484963 3594 uint8_t cpp;
a280f7dd 3595 uint32_t width = 0, height = 0;
9c2f7a9d 3596 uint32_t plane_pixel_rate;
75676ed4 3597 uint32_t y_tile_minimum, y_min_scanlines;
ee3d532f
PZ		 3598 struct intel_atomic_state *state =
3599 to_intel_atomic_state(cstate->base.state);
3600 bool apply_memory_bw_wa = skl_needs_memory_bw_wa(state);
2d41c0b5 3601
936e71e3 3602 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3603 *enabled = false;
3604 return 0;
3605 }
2d41c0b5 3606
bae781b2 3607 if (apply_memory_bw_wa && fb->modifier == I915_FORMAT_MOD_X_TILED)
ee3d532f
PZ		 3608 latency += 15;
3609
936e71e3
VS		 3610 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3611 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3612
bd2ef25d 3613 if (drm_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3614 swap(width, height);
3615
353c8598 3616 cpp = fb->format->cpp[0];
9c2f7a9d
KM		 3617 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3618
61d0a04d 3619 if (drm_rotation_90_or_270(pstate->rotation)) {
1186fa85 3620 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
353c8598
VS		 3621 fb->format->cpp[1] :
3622 fb->format->cpp[0];
1186fa85
PZ		 3623
3624 switch (cpp) {
3625 case 1:
3626 y_min_scanlines = 16;
3627 break;
3628 case 2:
3629 y_min_scanlines = 8;
3630 break;
1186fa85
PZ		 3631 case 4:
3632 y_min_scanlines = 4;
3633 break;
86a462bc
PZ		 3634 default:
3635 MISSING_CASE(cpp);
3636 return -EINVAL;
1186fa85
PZ		 3637 }
3638 } else {
3639 y_min_scanlines = 4;
3640 }
3641
2ef32dee
PZ		 3642 if (apply_memory_bw_wa)
3643 y_min_scanlines *= 2;
3644
7a1a8aed 3645 plane_bytes_per_line = width * cpp;
bae781b2
VS		 3646 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3647 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
7a1a8aed
PZ		 3648 plane_blocks_per_line =
3649 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3650 plane_blocks_per_line /= y_min_scanlines;
bae781b2 3651 } else if (fb->modifier == DRM_FORMAT_MOD_NONE) {
7a1a8aed
PZ		 3652 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3653 + 1;
3654 } else {
3655 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3656 }
3657
9c2f7a9d
KM		 3658 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3659 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3660 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3661 latency,
7a1a8aed 3662 plane_blocks_per_line);
2d41c0b5 3663
75676ed4
PZ		 3664 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3665
bae781b2
VS		 3666 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3667 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3668 selected_result = max(method2, y_tile_minimum);
3669 } else {
f1db3eaf
PZ		 3670 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3671 (plane_bytes_per_line / 512 < 1))
3672 selected_result = method2;
3673 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3674 selected_result = min(method1, method2);
3675 else
3676 selected_result = method1;
3677 }
2d41c0b5 3678
d4c2aa60
TU		 3679 res_blocks = selected_result + 1;
3680 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3681
0fda6568 3682 if (level >= 1 && level <= 7) {
bae781b2
VS		 3683 if (fb->modifier == I915_FORMAT_MOD_Y_TILED ||
3684 fb->modifier == I915_FORMAT_MOD_Yf_TILED) {
75676ed4 3685 res_blocks += y_tile_minimum;
1186fa85 3686 res_lines += y_min_scanlines;
75676ed4 3687 } else {
0fda6568 3688 res_blocks++;
75676ed4 3689 }
0fda6568 3690 }
e6d66171 3691
55994c2c
MR		 3692 if (res_blocks >= ddb_allocation || res_lines > 31) {
3693 *enabled = false;
6b6bada7
MR		 3694
3695 /*
3696 * If there are no valid level 0 watermarks, then we can't
3697 * support this display configuration.
3698 */
3699 if (level) {
3700 return 0;
3701 } else {
3702 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3703 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3704 to_intel_crtc(cstate->base.crtc)->pipe,
3705 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3706 res_blocks, ddb_allocation, res_lines);
3707
3708 return -EINVAL;
3709 }
55994c2c 3710 }
e6d66171
DL		 3711
3712 *out_blocks = res_blocks;
3713 *out_lines = res_lines;
55994c2c 3714 *enabled = true;
2d41c0b5 3715
55994c2c 3716 return 0;
2d41c0b5
PB		 3717}
3718
f4a96752
MR		 3719static int
3720skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3721 struct skl_ddb_allocation *ddb,
3722 struct intel_crtc_state *cstate,
a62163e9 3723 struct intel_plane *intel_plane,
f4a96752
MR		 3724 int level,
3725 struct skl_wm_level *result)
2d41c0b5 3726{
f4a96752 3727 struct drm_atomic_state *state = cstate->base.state;
024c9045 3728 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
a62163e9
L		 3729 struct drm_plane *plane = &intel_plane->base;
3730 struct intel_plane_state *intel_pstate = NULL;
2d41c0b5 3731 uint16_t ddb_blocks;
024c9045 3732 enum pipe pipe = intel_crtc->pipe;
55994c2c 3733 int ret;
a62163e9
L		 3734 int i = skl_wm_plane_id(intel_plane);
3735
3736 if (state)
3737 intel_pstate =
3738 intel_atomic_get_existing_plane_state(state,
3739 intel_plane);
024c9045 3740
f4a96752 3741 /*
a62163e9
L		 3742 * Note: If we start supporting multiple pending atomic commits against
3743 * the same planes/CRTC's in the future, plane->state will no longer be
3744 * the correct pre-state to use for the calculations here and we'll
3745 * need to change where we get the 'unchanged' plane data from.
3746 *
3747 * For now this is fine because we only allow one queued commit against
3748 * a CRTC. Even if the plane isn't modified by this transaction and we
3749 * don't have a plane lock, we still have the CRTC's lock, so we know
3750 * that no other transactions are racing with us to update it.
f4a96752 3751 */
a62163e9
L		 3752 if (!intel_pstate)
3753 intel_pstate = to_intel_plane_state(plane->state);
f4a96752 3754
a62163e9 3755 WARN_ON(!intel_pstate->base.fb);
f4a96752 3756
a62163e9 3757 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
2d41c0b5 3758
a62163e9
L		 3759 ret = skl_compute_plane_wm(dev_priv,
3760 cstate,
3761 intel_pstate,
3762 ddb_blocks,
3763 level,
3764 &result->plane_res_b,
3765 &result->plane_res_l,
3766 &result->plane_en);
3767 if (ret)
3768 return ret;
f4a96752
MR		 3769
3770 return 0;
2d41c0b5
PB		 3771}
3772
407b50f3 3773static uint32_t
024c9045 3774skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3775{
30d1b5fe
PZ		 3776 uint32_t pixel_rate;
3777
024c9045 3778 if (!cstate->base.active)
407b50f3
DL		 3779 return 0;
3780
30d1b5fe
PZ		 3781 pixel_rate = ilk_pipe_pixel_rate(cstate);
3782
3783 if (WARN_ON(pixel_rate == 0))
661abfc0 3784 return 0;
407b50f3 3785
024c9045 3786 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
30d1b5fe 3787 pixel_rate);
407b50f3
DL		 3788}
3789
024c9045 3790static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3791 struct skl_wm_level *trans_wm /* out */)
407b50f3 3792{
024c9045 3793 if (!cstate->base.active)
407b50f3 3794 return;
9414f563
DL		 3795
3796 /* Until we know more, just disable transition WMs */
a62163e9 3797 trans_wm->plane_en = false;
407b50f3
DL		 3798}
3799
55994c2c
MR		 3800static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3801 struct skl_ddb_allocation *ddb,
3802 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3803{
024c9045 3804 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3805 const struct drm_i915_private *dev_priv = to_i915(dev);
a62163e9
L		 3806 struct intel_plane *intel_plane;
3807 struct skl_plane_wm *wm;
5db94019 3808 int level, max_level = ilk_wm_max_level(dev_priv);
55994c2c 3809 int ret;
2d41c0b5 3810
a62163e9
L		 3811 /*
3812 * We'll only calculate watermarks for planes that are actually
3813 * enabled, so make sure all other planes are set as disabled.
3814 */
3815 memset(pipe_wm->planes, 0, sizeof(pipe_wm->planes));
3816
3817 for_each_intel_plane_mask(&dev_priv->drm,
3818 intel_plane,
3819 cstate->base.plane_mask) {
3820 wm = &pipe_wm->planes[skl_wm_plane_id(intel_plane)];
3821
3822 for (level = 0; level <= max_level; level++) {
3823 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3824 intel_plane, level,
3825 &wm->wm[level]);
3826 if (ret)
3827 return ret;
3828 }
3829 skl_compute_transition_wm(cstate, &wm->trans_wm);
2d41c0b5 3830 }
024c9045 3831 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3832
55994c2c 3833 return 0;
2d41c0b5
PB		 3834}
3835
f0f59a00
VS		 3836static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3837 i915_reg_t reg,
16160e3d
DL		 3838 const struct skl_ddb_entry *entry)
3839{
3840 if (entry->end)
3841 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3842 else
3843 I915_WRITE(reg, 0);
3844}
3845
d8c0fafc 3846static void skl_write_wm_level(struct drm_i915_private *dev_priv,
3847 i915_reg_t reg,
3848 const struct skl_wm_level *level)
3849{
3850 uint32_t val = 0;
3851
3852 if (level->plane_en) {
3853 val |= PLANE_WM_EN;
3854 val |= level->plane_res_b;
3855 val |= level->plane_res_l << PLANE_WM_LINES_SHIFT;
3856 }
3857
3858 I915_WRITE(reg, val);
3859}
3860
99101574
VS		 3861static void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3862 const struct skl_plane_wm *wm,
3863 const struct skl_ddb_allocation *ddb,
3864 int plane)
62e0fb88
L		 3865{
3866 struct drm_crtc *crtc = &intel_crtc->base;
3867 struct drm_device *dev = crtc->dev;
3868 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3869 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3870 enum pipe pipe = intel_crtc->pipe;
3871
3872 for (level = 0; level <= max_level; level++) {
d8c0fafc 3873 skl_write_wm_level(dev_priv, PLANE_WM(pipe, plane, level),
3874 &wm->wm[level]);
62e0fb88 3875 }
d8c0fafc 3876 skl_write_wm_level(dev_priv, PLANE_WM_TRANS(pipe, plane),
3877 &wm->trans_wm);
27082493
L		 3878
3879 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
d8c0fafc 3880 &ddb->plane[pipe][plane]);
27082493 3881 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
d8c0fafc 3882 &ddb->y_plane[pipe][plane]);
62e0fb88
L		 3883}
3884
99101574
VS		 3885static void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3886 const struct skl_plane_wm *wm,
3887 const struct skl_ddb_allocation *ddb)
62e0fb88
L		 3888{
3889 struct drm_crtc *crtc = &intel_crtc->base;
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = to_i915(dev);
5db94019 3892 int level, max_level = ilk_wm_max_level(dev_priv);
62e0fb88
L		 3893 enum pipe pipe = intel_crtc->pipe;
3894
3895 for (level = 0; level <= max_level; level++) {
d8c0fafc 3896 skl_write_wm_level(dev_priv, CUR_WM(pipe, level),
3897 &wm->wm[level]);
62e0fb88 3898 }
d8c0fafc 3899 skl_write_wm_level(dev_priv, CUR_WM_TRANS(pipe), &wm->trans_wm);
5d374d96 3900
27082493 3901 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
d8c0fafc 3902 &ddb->plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3903}
3904
45ece230 3905bool skl_wm_level_equals(const struct skl_wm_level *l1,
3906 const struct skl_wm_level *l2)
3907{
3908 if (l1->plane_en != l2->plane_en)
3909 return false;
3910
3911 /* If both planes aren't enabled, the rest shouldn't matter */
3912 if (!l1->plane_en)
3913 return true;
3914
3915 return (l1->plane_res_l == l2->plane_res_l &&
3916 l1->plane_res_b == l2->plane_res_b);
3917}
3918
27082493
L		 3919static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3920 const struct skl_ddb_entry *b)
0e8fb7ba 3921{
27082493 3922 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3923}
3924
5eff503b
ML		 3925bool skl_ddb_allocation_overlaps(const struct skl_ddb_entry **entries,
3926 const struct skl_ddb_entry *ddb,
3927 int ignore)
0e8fb7ba 3928{
ce0ba283 3929 int i;
0e8fb7ba 3930
5eff503b
ML		 3931 for (i = 0; i < I915_MAX_PIPES; i++)
3932 if (i != ignore && entries[i] &&
3933 skl_ddb_entries_overlap(ddb, entries[i]))
27082493 3934 return true;
0e8fb7ba 3935
27082493 3936 return false;
0e8fb7ba
DL		 3937}
3938
55994c2c 3939static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
03af79e0 3940 const struct skl_pipe_wm *old_pipe_wm,
55994c2c 3941 struct skl_pipe_wm *pipe_wm, /* out */
03af79e0 3942 struct skl_ddb_allocation *ddb, /* out */
55994c2c 3943 bool *changed /* out */)
2d41c0b5 3944{
f4a96752 3945 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3946 int ret;
2d41c0b5 3947
55994c2c
MR		 3948 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3949 if (ret)
3950 return ret;
2d41c0b5 3951
03af79e0 3952 if (!memcmp(old_pipe_wm, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3953 *changed = false;
3954 else
3955 *changed = true;
2d41c0b5 3956
55994c2c 3957 return 0;
2d41c0b5
PB		 3958}
3959
9b613022
MR		 3960static uint32_t
3961pipes_modified(struct drm_atomic_state *state)
3962{
3963 struct drm_crtc *crtc;
3964 struct drm_crtc_state *cstate;
3965 uint32_t i, ret = 0;
3966
3967 for_each_crtc_in_state(state, crtc, cstate, i)
3968 ret |= drm_crtc_mask(crtc);
3969
3970 return ret;
3971}
3972
bb7791bd 3973static int
7f60e200
PZ		 3974skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3975{
3976 struct drm_atomic_state *state = cstate->base.state;
3977 struct drm_device *dev = state->dev;
3978 struct drm_crtc *crtc = cstate->base.crtc;
3979 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3980 struct drm_i915_private *dev_priv = to_i915(dev);
3981 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3982 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3983 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3984 struct drm_plane_state *plane_state;
3985 struct drm_plane *plane;
3986 enum pipe pipe = intel_crtc->pipe;
3987 int id;
3988
3989 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3990
220b0965 3991 drm_for_each_plane_mask(plane, dev, cstate->base.plane_mask) {
7f60e200
PZ		 3992 id = skl_wm_plane_id(to_intel_plane(plane));
3993
3994 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3995 &new_ddb->plane[pipe][id]) &&
3996 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3997 &new_ddb->y_plane[pipe][id]))
3998 continue;
3999
4000 plane_state = drm_atomic_get_plane_state(state, plane);
4001 if (IS_ERR(plane_state))
4002 return PTR_ERR(plane_state);
4003 }
4004
4005 return 0;
4006}
4007
98d39494
MR		 4008static int
4009skl_compute_ddb(struct drm_atomic_state *state)
4010{
4011 struct drm_device *dev = state->dev;
4012 struct drm_i915_private *dev_priv = to_i915(dev);
4013 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4014 struct intel_crtc *intel_crtc;
734fa01f 4015 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4016 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4017 int ret;
4018
4019 /*
4020 * If this is our first atomic update following hardware readout,
4021 * we can't trust the DDB that the BIOS programmed for us. Let's
4022 * pretend that all pipes switched active status so that we'll
4023 * ensure a full DDB recompute.
4024 */
1b54a880
MR		 4025 if (dev_priv->wm.distrust_bios_wm) {
4026 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4027 state->acquire_ctx);
4028 if (ret)
4029 return ret;
4030
98d39494
MR		 4031 intel_state->active_pipe_changes = ~0;
4032
1b54a880
MR		 4033 /*
4034 * We usually only initialize intel_state->active_crtcs if we
4035 * we're doing a modeset; make sure this field is always
4036 * initialized during the sanitization process that happens
4037 * on the first commit too.
4038 */
4039 if (!intel_state->modeset)
4040 intel_state->active_crtcs = dev_priv->active_crtcs;
4041 }
4042
98d39494
MR		 4043 /*
4044 * If the modeset changes which CRTC's are active, we need to
4045 * recompute the DDB allocation for *all* active pipes, even
4046 * those that weren't otherwise being modified in any way by this
4047 * atomic commit. Due to the shrinking of the per-pipe allocations
4048 * when new active CRTC's are added, it's possible for a pipe that
4049 * we were already using and aren't changing at all here to suddenly
4050 * become invalid if its DDB needs exceeds its new allocation.
4051 *
4052 * Note that if we wind up doing a full DDB recompute, we can't let
4053 * any other display updates race with this transaction, so we need
4054 * to grab the lock on *all* CRTC's.
4055 */
734fa01f 4056 if (intel_state->active_pipe_changes) {
98d39494 4057 realloc_pipes = ~0;
734fa01f
MR		 4058 intel_state->wm_results.dirty_pipes = ~0;
4059 }
98d39494 4060
5a920b85
PZ		 4061 /*
4062 * We're not recomputing for the pipes not included in the commit, so
4063 * make sure we start with the current state.
4064 */
4065 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4066
98d39494
MR		 4067 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4068 struct intel_crtc_state *cstate;
4069
4070 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4071 if (IS_ERR(cstate))
4072 return PTR_ERR(cstate);
4073
734fa01f 4074 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4075 if (ret)
4076 return ret;
05a76d3d 4077
7f60e200 4078 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4079 if (ret)
4080 return ret;
98d39494
MR		 4081 }
4082
4083 return 0;
4084}
4085
2722efb9
MR		 4086static void
4087skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4088 struct skl_wm_values *src,
4089 enum pipe pipe)
4090{
2722efb9
MR		 4091 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4092 sizeof(dst->ddb.y_plane[pipe]));
4093 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4094 sizeof(dst->ddb.plane[pipe]));
4095}
4096
413fc530 4097static void
4098skl_print_wm_changes(const struct drm_atomic_state *state)
4099{
4100 const struct drm_device *dev = state->dev;
4101 const struct drm_i915_private *dev_priv = to_i915(dev);
4102 const struct intel_atomic_state *intel_state =
4103 to_intel_atomic_state(state);
4104 const struct drm_crtc *crtc;
4105 const struct drm_crtc_state *cstate;
413fc530 4106 const struct intel_plane *intel_plane;
413fc530 4107 const struct skl_ddb_allocation *old_ddb = &dev_priv->wm.skl_hw.ddb;
4108 const struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
413fc530 4109 int id;
7570498e 4110 int i;
413fc530 4111
4112 for_each_crtc_in_state(state, crtc, cstate, i) {
7570498e
ML		 4113 const struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4114 enum pipe pipe = intel_crtc->pipe;
413fc530 4115
7570498e 4116 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
413fc530 4117 const struct skl_ddb_entry *old, *new;
4118
413fc530 4119 id = skl_wm_plane_id(intel_plane);
4120 old = &old_ddb->plane[pipe][id];
4121 new = &new_ddb->plane[pipe][id];
4122
413fc530 4123 if (skl_ddb_entry_equal(old, new))
4124 continue;
4125
7570498e
ML		 4126 DRM_DEBUG_ATOMIC("[PLANE:%d:%s] ddb (%d - %d) -> (%d - %d)\n",
4127 intel_plane->base.base.id,
4128 intel_plane->base.name,
4129 old->start, old->end,
4130 new->start, new->end);
413fc530 4131 }
4132 }
4133}
4134
98d39494
MR		 4135static int
4136skl_compute_wm(struct drm_atomic_state *state)
4137{
4138 struct drm_crtc *crtc;
4139 struct drm_crtc_state *cstate;
734fa01f
MR		 4140 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4141 struct skl_wm_values *results = &intel_state->wm_results;
4142 struct skl_pipe_wm *pipe_wm;
98d39494 4143 bool changed = false;
734fa01f 4144 int ret, i;
98d39494
MR		 4145
4146 /*
4147 * If this transaction isn't actually touching any CRTC's, don't
4148 * bother with watermark calculation. Note that if we pass this
4149 * test, we're guaranteed to hold at least one CRTC state mutex,
4150 * which means we can safely use values like dev_priv->active_crtcs
4151 * since any racing commits that want to update them would need to
4152 * hold _all_ CRTC state mutexes.
4153 */
4154 for_each_crtc_in_state(state, crtc, cstate, i)
4155 changed = true;
4156 if (!changed)
4157 return 0;
4158
734fa01f
MR		 4159 /* Clear all dirty flags */
4160 results->dirty_pipes = 0;
4161
98d39494
MR		 4162 ret = skl_compute_ddb(state);
4163 if (ret)
4164 return ret;
4165
734fa01f
MR		 4166 /*
4167 * Calculate WM's for all pipes that are part of this transaction.
4168 * Note that the DDB allocation above may have added more CRTC's that
4169 * weren't otherwise being modified (and set bits in dirty_pipes) if
4170 * pipe allocations had to change.
4171 *
4172 * FIXME: Now that we're doing this in the atomic check phase, we
4173 * should allow skl_update_pipe_wm() to return failure in cases where
4174 * no suitable watermark values can be found.
4175 */
4176 for_each_crtc_in_state(state, crtc, cstate, i) {
734fa01f
MR		 4177 struct intel_crtc_state *intel_cstate =
4178 to_intel_crtc_state(cstate);
03af79e0
ML		 4179 const struct skl_pipe_wm *old_pipe_wm =
4180 &to_intel_crtc_state(crtc->state)->wm.skl.optimal;
734fa01f
MR		 4181
4182 pipe_wm = &intel_cstate->wm.skl.optimal;
03af79e0
ML		 4183 ret = skl_update_pipe_wm(cstate, old_pipe_wm, pipe_wm,
4184 &results->ddb, &changed);
734fa01f
MR		 4185 if (ret)
4186 return ret;
4187
4188 if (changed)
4189 results->dirty_pipes |= drm_crtc_mask(crtc);
4190
4191 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4192 /* This pipe's WM's did not change */
4193 continue;
4194
4195 intel_cstate->update_wm_pre = true;
734fa01f
MR		 4196 }
4197
413fc530 4198 skl_print_wm_changes(state);
4199
98d39494
MR		 4200 return 0;
4201}
4202
ccf010fb
ML		 4203static void skl_atomic_update_crtc_wm(struct intel_atomic_state *state,
4204 struct intel_crtc_state *cstate)
4205{
4206 struct intel_crtc *crtc = to_intel_crtc(cstate->base.crtc);
4207 struct drm_i915_private *dev_priv = to_i915(state->base.dev);
4208 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
e62929b3 4209 const struct skl_ddb_allocation *ddb = &state->wm_results.ddb;
ccf010fb 4210 enum pipe pipe = crtc->pipe;
e62929b3
ML		 4211 int plane;
4212
4213 if (!(state->wm_results.dirty_pipes & drm_crtc_mask(&crtc->base)))
4214 return;
ccf010fb
ML		 4215
4216 I915_WRITE(PIPE_WM_LINETIME(pipe), pipe_wm->linetime);
e62929b3
ML		 4217
4218 for_each_universal_plane(dev_priv, pipe, plane)
4219 skl_write_plane_wm(crtc, &pipe_wm->planes[plane], ddb, plane);
4220
4221 skl_write_cursor_wm(crtc, &pipe_wm->planes[PLANE_CURSOR], ddb);
ccf010fb
ML		 4222}
4223
e62929b3
ML		 4224static void skl_initial_wm(struct intel_atomic_state *state,
4225 struct intel_crtc_state *cstate)
2d41c0b5 4226{
e62929b3 4227 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
432081bc 4228 struct drm_device *dev = intel_crtc->base.dev;
fac5e23e 4229 struct drm_i915_private *dev_priv = to_i915(dev);
e62929b3 4230 struct skl_wm_values *results = &state->wm_results;
2722efb9 4231 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
27082493 4232 enum pipe pipe = intel_crtc->pipe;
adda50b8 4233
432081bc 4234 if ((results->dirty_pipes & drm_crtc_mask(&intel_crtc->base)) == 0)
2d41c0b5
PB		 4235 return;
4236
734fa01f 4237 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4238
e62929b3
ML		 4239 if (cstate->base.active_changed)
4240 skl_atomic_update_crtc_wm(state, cstate);
27082493
L		 4241
4242 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4243
4244 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4245}
4246
d890565c
VS		 4247static void ilk_compute_wm_config(struct drm_device *dev,
4248 struct intel_wm_config *config)
4249{
4250 struct intel_crtc *crtc;
4251
4252 /* Compute the currently _active_ config */
4253 for_each_intel_crtc(dev, crtc) {
4254 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4255
4256 if (!wm->pipe_enabled)
4257 continue;
4258
4259 config->sprites_enabled |= wm->sprites_enabled;
4260 config->sprites_scaled |= wm->sprites_scaled;
4261 config->num_pipes_active++;
4262 }
4263}
4264
ed4a6a7c 4265static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4266{
91c8a326 4267 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4268 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4269 struct ilk_wm_maximums max;
d890565c 4270 struct intel_wm_config config = {};
820c1980 4271 struct ilk_wm_values results = {};
77c122bc 4272 enum intel_ddb_partitioning partitioning;
261a27d1 4273
d890565c
VS		 4274 ilk_compute_wm_config(dev, &config);
4275
4276 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4277 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4278
4279 /* 5/6 split only in single pipe config on IVB+ */
175fded1 4280 if (INTEL_GEN(dev_priv) >= 7 &&
d890565c
VS		 4281 config.num_pipes_active == 1 && config.sprites_enabled) {
4282 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4283 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4284
820c1980 4285 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4286 } else {
198a1e9b 4287 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4288 }
4289
198a1e9b 4290 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4291 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4292
820c1980 4293 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4294
820c1980 4295 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4296}
4297
ccf010fb
ML		 4298static void ilk_initial_watermarks(struct intel_atomic_state *state,
4299 struct intel_crtc_state *cstate)
b9d5c839 4300{
ed4a6a7c
MR		 4301 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4302 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4303
ed4a6a7c 4304 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4305 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4306 ilk_program_watermarks(dev_priv);
4307 mutex_unlock(&dev_priv->wm.wm_mutex);
4308}
bf220452 4309
ccf010fb
ML		 4310static void ilk_optimize_watermarks(struct intel_atomic_state *state,
4311 struct intel_crtc_state *cstate)
ed4a6a7c
MR		 4312{
4313 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4314 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4315
ed4a6a7c
MR		 4316 mutex_lock(&dev_priv->wm.wm_mutex);
4317 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4318 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4319 ilk_program_watermarks(dev_priv);
4320 }
4321 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4322}
4323
d8c0fafc 4324static inline void skl_wm_level_from_reg_val(uint32_t val,
4325 struct skl_wm_level *level)
3078999f 4326{
d8c0fafc 4327 level->plane_en = val & PLANE_WM_EN;
4328 level->plane_res_b = val & PLANE_WM_BLOCKS_MASK;
4329 level->plane_res_l = (val >> PLANE_WM_LINES_SHIFT) &
4330 PLANE_WM_LINES_MASK;
3078999f
PB		 4331}
4332
bf9d99ad 4333void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc,
4334 struct skl_pipe_wm *out)
3078999f
PB		 4335{
4336 struct drm_device *dev = crtc->dev;
fac5e23e 4337 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f 4338 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
d8c0fafc 4339 struct intel_plane *intel_plane;
d8c0fafc 4340 struct skl_plane_wm *wm;
3078999f 4341 enum pipe pipe = intel_crtc->pipe;
d8c0fafc 4342 int level, id, max_level;
4343 uint32_t val;
3078999f 4344
5db94019 4345 max_level = ilk_wm_max_level(dev_priv);
3078999f 4346
d8c0fafc 4347 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
4348 id = skl_wm_plane_id(intel_plane);
bf9d99ad 4349 wm = &out->planes[id];
3078999f 4350
d8c0fafc 4351 for (level = 0; level <= max_level; level++) {
4352 if (id != PLANE_CURSOR)
4353 val = I915_READ(PLANE_WM(pipe, id, level));
4354 else
4355 val = I915_READ(CUR_WM(pipe, level));
3078999f 4356
d8c0fafc 4357 skl_wm_level_from_reg_val(val, &wm->wm[level]);
3078999f 4358 }
3078999f 4359
d8c0fafc 4360 if (id != PLANE_CURSOR)
4361 val = I915_READ(PLANE_WM_TRANS(pipe, id));
4362 else
4363 val = I915_READ(CUR_WM_TRANS(pipe));
4364
4365 skl_wm_level_from_reg_val(val, &wm->trans_wm);
3078999f
PB		 4366 }
4367
d8c0fafc 4368 if (!intel_crtc->active)
4369 return;
4e0963c7 4370
bf9d99ad 4371 out->linetime = I915_READ(PIPE_WM_LINETIME(pipe));
3078999f
PB		 4372}
4373
4374void skl_wm_get_hw_state(struct drm_device *dev)
4375{
fac5e23e 4376 struct drm_i915_private *dev_priv = to_i915(dev);
bf9d99ad 4377 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
a269c583 4378 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f 4379 struct drm_crtc *crtc;
bf9d99ad 4380 struct intel_crtc *intel_crtc;
4381 struct intel_crtc_state *cstate;
3078999f 4382
a269c583 4383 skl_ddb_get_hw_state(dev_priv, ddb);
bf9d99ad 4384 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
4385 intel_crtc = to_intel_crtc(crtc);
4386 cstate = to_intel_crtc_state(crtc->state);
4387
4388 skl_pipe_wm_get_hw_state(crtc, &cstate->wm.skl.optimal);
4389
03af79e0 4390 if (intel_crtc->active)
bf9d99ad 4391 hw->dirty_pipes |= drm_crtc_mask(crtc);
bf9d99ad 4392 }
a1de91e5 4393
279e99d7
MR		 4394 if (dev_priv->active_crtcs) {
4395 /* Fully recompute DDB on first atomic commit */
4396 dev_priv->wm.distrust_bios_wm = true;
4397 } else {
4398 /* Easy/common case; just sanitize DDB now if everything off */
4399 memset(ddb, 0, sizeof(*ddb));
4400 }
3078999f
PB		 4401}
4402
243e6a44
VS		 4403static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4404{
4405 struct drm_device *dev = crtc->dev;
fac5e23e 4406 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4407 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4408 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4409 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4410 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4411 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4412 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4413 [PIPE_A] = WM0_PIPEA_ILK,
4414 [PIPE_B] = WM0_PIPEB_ILK,
4415 [PIPE_C] = WM0_PIPEC_IVB,
4416 };
4417
4418 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4419 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4420 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4421
15606534
VS		 4422 memset(active, 0, sizeof(*active));
4423
3ef00284 4424 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4425
4426 if (active->pipe_enabled) {
243e6a44
VS		 4427 u32 tmp = hw->wm_pipe[pipe];
4428
4429 /*
4430 * For active pipes LP0 watermark is marked as
4431 * enabled, and LP1+ watermaks as disabled since
4432 * we can't really reverse compute them in case
4433 * multiple pipes are active.
4434 */
4435 active->wm[0].enable = true;
4436 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4437 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4438 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4439 active->linetime = hw->wm_linetime[pipe];
4440 } else {
5db94019 4441 int level, max_level = ilk_wm_max_level(dev_priv);
243e6a44
VS		 4442
4443 /*
4444 * For inactive pipes, all watermark levels
4445 * should be marked as enabled but zeroed,
4446 * which is what we'd compute them to.
4447 */
4448 for (level = 0; level <= max_level; level++)
4449 active->wm[level].enable = true;
4450 }
4e0963c7
MR		 4451
4452 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4453}
4454
6eb1a681
VS		 4455#define _FW_WM(value, plane) \
4456 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4457#define _FW_WM_VLV(value, plane) \
4458 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4459
4460static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4461 struct vlv_wm_values *wm)
4462{
4463 enum pipe pipe;
4464 uint32_t tmp;
4465
4466 for_each_pipe(dev_priv, pipe) {
4467 tmp = I915_READ(VLV_DDL(pipe));
4468
4469 wm->ddl[pipe].primary =
4470 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4471 wm->ddl[pipe].cursor =
4472 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4473 wm->ddl[pipe].sprite[0] =
4474 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4475 wm->ddl[pipe].sprite[1] =
4476 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4477 }
4478
4479 tmp = I915_READ(DSPFW1);
4480 wm->sr.plane = _FW_WM(tmp, SR);
4481 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4482 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4483 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4484
4485 tmp = I915_READ(DSPFW2);
4486 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4487 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4488 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4489
4490 tmp = I915_READ(DSPFW3);
4491 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4492
4493 if (IS_CHERRYVIEW(dev_priv)) {
4494 tmp = I915_READ(DSPFW7_CHV);
4495 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4496 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4497
4498 tmp = I915_READ(DSPFW8_CHV);
4499 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4500 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4501
4502 tmp = I915_READ(DSPFW9_CHV);
4503 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4504 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4505
4506 tmp = I915_READ(DSPHOWM);
4507 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4508 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4509 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4510 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4511 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4512 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4513 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4514 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4515 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4516 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4517 } else {
4518 tmp = I915_READ(DSPFW7);
4519 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4520 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4521
4522 tmp = I915_READ(DSPHOWM);
4523 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4524 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4525 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4526 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4527 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4528 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4529 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4530 }
4531}
4532
4533#undef _FW_WM
4534#undef _FW_WM_VLV
4535
4536void vlv_wm_get_hw_state(struct drm_device *dev)
4537{
4538 struct drm_i915_private *dev_priv = to_i915(dev);
4539 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4540 struct intel_plane *plane;
4541 enum pipe pipe;
4542 u32 val;
4543
4544 vlv_read_wm_values(dev_priv, wm);
4545
4546 for_each_intel_plane(dev, plane) {
4547 switch (plane->base.type) {
4548 int sprite;
4549 case DRM_PLANE_TYPE_CURSOR:
4550 plane->wm.fifo_size = 63;
4551 break;
4552 case DRM_PLANE_TYPE_PRIMARY:
ef0f5e93 4553 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, 0);
6eb1a681
VS		 4554 break;
4555 case DRM_PLANE_TYPE_OVERLAY:
4556 sprite = plane->plane;
ef0f5e93 4557 plane->wm.fifo_size = vlv_get_fifo_size(dev_priv, plane->pipe, sprite + 1);
6eb1a681
VS		 4558 break;
4559 }
4560 }
4561
4562 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4563 wm->level = VLV_WM_LEVEL_PM2;
4564
4565 if (IS_CHERRYVIEW(dev_priv)) {
4566 mutex_lock(&dev_priv->rps.hw_lock);
4567
4568 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4569 if (val & DSP_MAXFIFO_PM5_ENABLE)
4570 wm->level = VLV_WM_LEVEL_PM5;
4571
58590c14
VS		 4572 /*
4573 * If DDR DVFS is disabled in the BIOS, Punit
4574 * will never ack the request. So if that happens
4575 * assume we don't have to enable/disable DDR DVFS
4576 * dynamically. To test that just set the REQ_ACK
4577 * bit to poke the Punit, but don't change the
4578 * HIGH/LOW bits so that we don't actually change
4579 * the current state.
4580 */
6eb1a681 4581 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4582 val |= FORCE_DDR_FREQ_REQ_ACK;
4583 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4584
4585 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4586 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4587 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4588 "assuming DDR DVFS is disabled\n");
4589 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4590 } else {
4591 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4592 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4593 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4594 }
6eb1a681
VS		 4595
4596 mutex_unlock(&dev_priv->rps.hw_lock);
4597 }
4598
4599 for_each_pipe(dev_priv, pipe)
4600 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4601 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4602 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4603
4604 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4605 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4606}
4607
243e6a44
VS		 4608void ilk_wm_get_hw_state(struct drm_device *dev)
4609{
fac5e23e 4610 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4611 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4612 struct drm_crtc *crtc;
4613
70e1e0ec 4614 for_each_crtc(dev, crtc)
243e6a44
VS		 4615 ilk_pipe_wm_get_hw_state(crtc);
4616
4617 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4618 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4619 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4620
4621 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
175fded1 4622 if (INTEL_GEN(dev_priv) >= 7) {
cfa7698b
VS		 4623 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4624 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4625 }
243e6a44 4626
8652744b 4627 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4628 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4629 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4630 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4631 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4632 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4633
4634 hw->enable_fbc_wm =
4635 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4636}
4637
b445e3b0
ED		 4638/**
4639 * intel_update_watermarks - update FIFO watermark values based on current modes
4640 *
4641 * Calculate watermark values for the various WM regs based on current mode
4642 * and plane configuration.
4643 *
4644 * There are several cases to deal with here:
4645 * - normal (i.e. non-self-refresh)
4646 * - self-refresh (SR) mode
4647 * - lines are large relative to FIFO size (buffer can hold up to 2)
4648 * - lines are small relative to FIFO size (buffer can hold more than 2
4649 * lines), so need to account for TLB latency
4650 *
4651 * The normal calculation is:
4652 * watermark = dotclock * bytes per pixel * latency
4653 * where latency is platform & configuration dependent (we assume pessimal
4654 * values here).
4655 *
4656 * The SR calculation is:
4657 * watermark = (trunc(latency/line time)+1) * surface width *
4658 * bytes per pixel
4659 * where
4660 * line time = htotal / dotclock
4661 * surface width = hdisplay for normal plane and 64 for cursor
4662 * and latency is assumed to be high, as above.
4663 *
4664 * The final value programmed to the register should always be rounded up,
4665 * and include an extra 2 entries to account for clock crossings.
4666 *
4667 * We don't use the sprite, so we can ignore that. And on Crestline we have
4668 * to set the non-SR watermarks to 8.
4669 */
432081bc 4670void intel_update_watermarks(struct intel_crtc *crtc)
b445e3b0 4671{
432081bc 4672 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
b445e3b0
ED		 4673
4674 if (dev_priv->display.update_wm)
46ba614c 4675 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4676}
4677
e2828914 4678/*
9270388e 4679 * Lock protecting IPS related data structures
9270388e
DV		 4680 */
4681DEFINE_SPINLOCK(mchdev_lock);
4682
4683/* Global for IPS driver to get at the current i915 device. Protected by
4684 * mchdev_lock. */
4685static struct drm_i915_private *i915_mch_dev;
4686
91d14251 4687bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4688{
2b4e57bd
ED		 4689 u16 rgvswctl;
4690
9270388e
DV		 4691 assert_spin_locked(&mchdev_lock);
4692
2b4e57bd
ED		 4693 rgvswctl = I915_READ16(MEMSWCTL);
4694 if (rgvswctl & MEMCTL_CMD_STS) {
4695 DRM_DEBUG("gpu busy, RCS change rejected\n");
4696 return false; /* still busy with another command */
4697 }
4698
4699 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4700 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4701 I915_WRITE16(MEMSWCTL, rgvswctl);
4702 POSTING_READ16(MEMSWCTL);
4703
4704 rgvswctl |= MEMCTL_CMD_STS;
4705 I915_WRITE16(MEMSWCTL, rgvswctl);
4706
4707 return true;
4708}
4709
91d14251 4710static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4711{
84f1b20f 4712 u32 rgvmodectl;
2b4e57bd
ED		 4713 u8 fmax, fmin, fstart, vstart;
4714
9270388e
DV		 4715 spin_lock_irq(&mchdev_lock);
4716
84f1b20f
TU		 4717 rgvmodectl = I915_READ(MEMMODECTL);
4718
2b4e57bd
ED		 4719 /* Enable temp reporting */
4720 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4721 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4722
4723 /* 100ms RC evaluation intervals */
4724 I915_WRITE(RCUPEI, 100000);
4725 I915_WRITE(RCDNEI, 100000);
4726
4727 /* Set max/min thresholds to 90ms and 80ms respectively */
4728 I915_WRITE(RCBMAXAVG, 90000);
4729 I915_WRITE(RCBMINAVG, 80000);
4730
4731 I915_WRITE(MEMIHYST, 1);
4732
4733 /* Set up min, max, and cur for interrupt handling */
4734 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4735 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4736 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4737 MEMMODE_FSTART_SHIFT;
4738
616847e7 4739 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4740 PXVFREQ_PX_SHIFT;
4741
20e4d407
DV		 4742 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4743 dev_priv->ips.fstart = fstart;
2b4e57bd 4744
20e4d407
DV		 4745 dev_priv->ips.max_delay = fstart;
4746 dev_priv->ips.min_delay = fmin;
4747 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4748
4749 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4750 fmax, fmin, fstart);
4751
4752 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4753
4754 /*
4755 * Interrupts will be enabled in ironlake_irq_postinstall
4756 */
4757
4758 I915_WRITE(VIDSTART, vstart);
4759 POSTING_READ(VIDSTART);
4760
4761 rgvmodectl |= MEMMODE_SWMODE_EN;
4762 I915_WRITE(MEMMODECTL, rgvmodectl);
4763
9270388e 4764 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4765 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4766 mdelay(1);
2b4e57bd 4767
91d14251 4768 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4769
7d81c3e0
VS		 4770 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4771 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4772 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4773 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4774 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4775
4776 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4777}
4778
91d14251 4779static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4780{
9270388e
DV		 4781 u16 rgvswctl;
4782
4783 spin_lock_irq(&mchdev_lock);
4784
4785 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4786
4787 /* Ack interrupts, disable EFC interrupt */
4788 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4789 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4790 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4791 I915_WRITE(DEIIR, DE_PCU_EVENT);
4792 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4793
4794 /* Go back to the starting frequency */
91d14251 4795 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4796 mdelay(1);
2b4e57bd
ED		 4797 rgvswctl |= MEMCTL_CMD_STS;
4798 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4799 mdelay(1);
2b4e57bd 4800
9270388e 4801 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4802}
4803
acbe9475
DV		 4804/* There's a funny hw issue where the hw returns all 0 when reading from
4805 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4806 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4807 * all limits and the gpu stuck at whatever frequency it is at atm).
4808 */
74ef1173 4809static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4810{
7b9e0ae6 4811 u32 limits;
2b4e57bd 4812
20b46e59
DV		 4813 /* Only set the down limit when we've reached the lowest level to avoid
4814 * getting more interrupts, otherwise leave this clear. This prevents a
4815 * race in the hw when coming out of rc6: There's a tiny window where
4816 * the hw runs at the minimal clock before selecting the desired
4817 * frequency, if the down threshold expires in that window we will not
4818 * receive a down interrupt. */
2d1fe073 4819 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4820 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4821 if (val <= dev_priv->rps.min_freq_softlimit)
4822 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4823 } else {
4824 limits = dev_priv->rps.max_freq_softlimit << 24;
4825 if (val <= dev_priv->rps.min_freq_softlimit)
4826 limits |= dev_priv->rps.min_freq_softlimit << 16;
4827 }
20b46e59
DV		 4828
4829 return limits;
4830}
4831
dd75fdc8
CW		 4832static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4833{
4834 int new_power;
8a586437
AG		 4835 u32 threshold_up = 0, threshold_down = 0; /* in % */
4836 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4837
4838 new_power = dev_priv->rps.power;
4839 switch (dev_priv->rps.power) {
4840 case LOW_POWER:
a72b5623
CW		 4841 if (val > dev_priv->rps.efficient_freq + 1 &&
4842 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4843 new_power = BETWEEN;
4844 break;
4845
4846 case BETWEEN:
a72b5623
CW		 4847 if (val <= dev_priv->rps.efficient_freq &&
4848 val < dev_priv->rps.cur_freq)
dd75fdc8 4849 new_power = LOW_POWER;
a72b5623
CW		 4850 else if (val >= dev_priv->rps.rp0_freq &&
4851 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4852 new_power = HIGH_POWER;
4853 break;
4854
4855 case HIGH_POWER:
a72b5623
CW		 4856 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4857 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4858 new_power = BETWEEN;
4859 break;
4860 }
4861 /* Max/min bins are special */
aed242ff 4862 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4863 new_power = LOW_POWER;
aed242ff 4864 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4865 new_power = HIGH_POWER;
4866 if (new_power == dev_priv->rps.power)
4867 return;
4868
4869 /* Note the units here are not exactly 1us, but 1280ns. */
4870 switch (new_power) {
4871 case LOW_POWER:
4872 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4873 ei_up = 16000;
4874 threshold_up = 95;
dd75fdc8
CW		 4875
4876 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4877 ei_down = 32000;
4878 threshold_down = 85;
dd75fdc8
CW		 4879 break;
4880
4881 case BETWEEN:
4882 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4883 ei_up = 13000;
4884 threshold_up = 90;
dd75fdc8
CW		 4885
4886 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4887 ei_down = 32000;
4888 threshold_down = 75;
dd75fdc8
CW		 4889 break;
4890
4891 case HIGH_POWER:
4892 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4893 ei_up = 10000;
4894 threshold_up = 85;
dd75fdc8
CW		 4895
4896 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4897 ei_down = 32000;
4898 threshold_down = 60;
dd75fdc8
CW		 4899 break;
4900 }
4901
8a586437 4902 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4903 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4904 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4905 GT_INTERVAL_FROM_US(dev_priv,
4906 ei_up * threshold_up / 100));
8a586437
AG		 4907
4908 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4909 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4910 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4911 GT_INTERVAL_FROM_US(dev_priv,
4912 ei_down * threshold_down / 100));
4913
4914 I915_WRITE(GEN6_RP_CONTROL,
4915 GEN6_RP_MEDIA_TURBO |
4916 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4917 GEN6_RP_MEDIA_IS_GFX |
4918 GEN6_RP_ENABLE |
4919 GEN6_RP_UP_BUSY_AVG |
4920 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4921
dd75fdc8 4922 dev_priv->rps.power = new_power;
8fb55197
CW		 4923 dev_priv->rps.up_threshold = threshold_up;
4924 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4925 dev_priv->rps.last_adj = 0;
4926}
4927
2876ce73
CW		 4928static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4929{
4930 u32 mask = 0;
4931
4932 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4933 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4934 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4935 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4936
7b3c29f6
CW		 4937 mask &= dev_priv->pm_rps_events;
4938
59d02a1f 4939 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4940}
4941
b8a5ff8d
JM		 4942/* gen6_set_rps is called to update the frequency request, but should also be
4943 * called when the range (min_delay and max_delay) is modified so that we can
4944 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4945static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4946{
23eafea6 4947 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4948 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4949 return;
4950
4fc688ce 4951 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4952 WARN_ON(val > dev_priv->rps.max_freq);
4953 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4954
eb64cad1
CW		 4955 /* min/max delay may still have been modified so be sure to
4956 * write the limits value.
4957 */
4958 if (val != dev_priv->rps.cur_freq) {
4959 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4960
dc97997a 4961 if (IS_GEN9(dev_priv))
5704195c
AG		 4962 I915_WRITE(GEN6_RPNSWREQ,
4963 GEN9_FREQUENCY(val));
dc97997a 4964 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4965 I915_WRITE(GEN6_RPNSWREQ,
4966 HSW_FREQUENCY(val));
4967 else
4968 I915_WRITE(GEN6_RPNSWREQ,
4969 GEN6_FREQUENCY(val) |
4970 GEN6_OFFSET(0) |
4971 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4972 }
7b9e0ae6 4973
7b9e0ae6
CW		 4974 /* Make sure we continue to get interrupts
4975 * until we hit the minimum or maximum frequencies.
4976 */
74ef1173 4977 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4978 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4979
d5570a72
BW		 4980 POSTING_READ(GEN6_RPNSWREQ);
4981
b39fb297 4982 dev_priv->rps.cur_freq = val;
0f94592e 4983 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4984}
4985
dc97997a 4986static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4987{
ffe02b40 4988 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4989 WARN_ON(val > dev_priv->rps.max_freq);
4990 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4991
dc97997a 4992 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4993 "Odd GPU freq value\n"))
4994 val &= ~1;
4995
cd25dd5b
D		 4996 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4997
8fb55197 4998 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4999 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 5000 if (!IS_CHERRYVIEW(dev_priv))
5001 gen6_set_rps_thresholds(dev_priv, val);
5002 }
ffe02b40 5003
ffe02b40
VS		 5004 dev_priv->rps.cur_freq = val;
5005 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5006}
5007
a7f6e231 5008/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5009 *
5010 * * If Gfx is Idle, then
a7f6e231
D		 5011 * 1. Forcewake Media well.
5012 * 2. Request idle freq.
5013 * 3. Release Forcewake of Media well.
76c3552f
D		 5014*/
5015static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5016{
aed242ff 5017 u32 val = dev_priv->rps.idle_freq;
5549d25f 5018
aed242ff 5019 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5020 return;
5021
a7f6e231
D		 5022 /* Wake up the media well, as that takes a lot less
5023 * power than the Render well. */
5024 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5025 valleyview_set_rps(dev_priv, val);
a7f6e231 5026 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5027}
5028
43cf3bf0
CW		 5029void gen6_rps_busy(struct drm_i915_private *dev_priv)
5030{
5031 mutex_lock(&dev_priv->rps.hw_lock);
5032 if (dev_priv->rps.enabled) {
5033 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5034 gen6_rps_reset_ei(dev_priv);
5035 I915_WRITE(GEN6_PMINTRMSK,
5036 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5037
c33d247d
CW		 5038 gen6_enable_rps_interrupts(dev_priv);
5039
2b83c4c4
MW		 5040 /* Ensure we start at the user's desired frequency */
5041 intel_set_rps(dev_priv,
5042 clamp(dev_priv->rps.cur_freq,
5043 dev_priv->rps.min_freq_softlimit,
5044 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5045 }
5046 mutex_unlock(&dev_priv->rps.hw_lock);
5047}
5048
b29c19b6
CW		 5049void gen6_rps_idle(struct drm_i915_private *dev_priv)
5050{
c33d247d
CW		 5051 /* Flush our bottom-half so that it does not race with us
5052 * setting the idle frequency and so that it is bounded by
5053 * our rpm wakeref. And then disable the interrupts to stop any
5054 * futher RPS reclocking whilst we are asleep.
5055 */
5056 gen6_disable_rps_interrupts(dev_priv);
5057
b29c19b6 5058 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5059 if (dev_priv->rps.enabled) {
dc97997a 5060 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5061 vlv_set_rps_idle(dev_priv);
7526ed79 5062 else
dc97997a 5063 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5064 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5065 I915_WRITE(GEN6_PMINTRMSK,
5066 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5067 }
8d3afd7d 5068 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5069
8d3afd7d 5070 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5071 while (!list_empty(&dev_priv->rps.clients))
5072 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5073 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5074}
5075
1854d5ca 5076void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5077 struct intel_rps_client *rps,
5078 unsigned long submitted)
b29c19b6 5079{
8d3afd7d
CW		 5080 /* This is intentionally racy! We peek at the state here, then
5081 * validate inside the RPS worker.
5082 */
67d97da3 5083 if (!(dev_priv->gt.awake &&
8d3afd7d 5084 dev_priv->rps.enabled &&
29ecd78d 5085 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5086 return;
43cf3bf0 5087
e61b9958
CW		 5088 /* Force a RPS boost (and don't count it against the client) if
5089 * the GPU is severely congested.
5090 */
d0bc54f2 5091 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5092 rps = NULL;
5093
8d3afd7d
CW		 5094 spin_lock(&dev_priv->rps.client_lock);
5095 if (rps == NULL || list_empty(&rps->link)) {
5096 spin_lock_irq(&dev_priv->irq_lock);
5097 if (dev_priv->rps.interrupts_enabled) {
5098 dev_priv->rps.client_boost = true;
c33d247d 5099 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5100 }
5101 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5102
2e1b8730
CW		 5103 if (rps != NULL) {
5104 list_add(&rps->link, &dev_priv->rps.clients);
5105 rps->boosts++;
1854d5ca
CW		 5106 } else
5107 dev_priv->rps.boosts++;
c0951f0c 5108 }
8d3afd7d 5109 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5110}
5111
dc97997a 5112void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5113{
dc97997a
CW		 5114 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5115 valleyview_set_rps(dev_priv, val);
ffe02b40 5116 else
dc97997a 5117 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5118}
5119
dc97997a 5120static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5121{
20e49366 5122 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5123 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5124}
5125
dc97997a 5126static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5127{
2030d684
AG		 5128 I915_WRITE(GEN6_RP_CONTROL, 0);
5129}
5130
dc97997a 5131static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5132{
d20d4f0c 5133 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5134 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5135 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5136}
5137
dc97997a 5138static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5139{
38807746
D		 5140 I915_WRITE(GEN6_RC_CONTROL, 0);
5141}
5142
dc97997a 5143static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5144{
98a2e5f9
D		 5145 /* we're doing forcewake before Disabling RC6,
5146 * This what the BIOS expects when going into suspend */
59bad947 5147 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5148
44fc7d5c 5149 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5150
59bad947 5151 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5152}
5153
dc97997a 5154static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5155{
dc97997a 5156 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5157 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5158 mode = GEN6_RC_CTL_RC6_ENABLE;
5159 else
5160 mode = 0;
5161 }
dc97997a 5162 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5163 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5164 "RC6 %s RC6p %s RC6pp %s\n",
5165 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5166 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5167 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5168
5169 else
b99d49cc
ID		 5170 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5171 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5172}
5173
dc97997a 5174static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5175{
72e96d64 5176 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5177 bool enable_rc6 = true;
5178 unsigned long rc6_ctx_base;
fc619841
ID		 5179 u32 rc_ctl;
5180 int rc_sw_target;
5181
5182 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5183 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5184 RC_SW_TARGET_STATE_SHIFT;
5185 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5186 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5187 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5188 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5189 rc_sw_target);
274008e8
SAK		 5190
5191 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5192 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5193 enable_rc6 = false;
5194 }
5195
5196 /*
5197 * The exact context size is not known for BXT, so assume a page size
5198 * for this check.
5199 */
5200 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5201 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5202 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5203 ggtt->stolen_reserved_size))) {
b99d49cc 5204 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5205 enable_rc6 = false;
5206 }
5207
5208 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5209 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5210 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5211 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5212 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5213 enable_rc6 = false;
5214 }
5215
fc619841
ID		 5216 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5217 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5218 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5219 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5220 enable_rc6 = false;
5221 }
5222
5223 if (!I915_READ(GEN6_GFXPAUSE)) {
5224 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5225 enable_rc6 = false;
5226 }
5227
5228 if (!I915_READ(GEN8_MISC_CTRL0)) {
5229 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5230 enable_rc6 = false;
5231 }
5232
5233 return enable_rc6;
5234}
5235
dc97997a 5236int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5237{
e7d66d89 5238 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5239 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5240 return 0;
5241
274008e8
SAK		 5242 if (!enable_rc6)
5243 return 0;
5244
dc97997a 5245 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5246 DRM_INFO("RC6 disabled by BIOS\n");
5247 return 0;
5248 }
5249
456470eb 5250 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5251 if (enable_rc6 >= 0) {
5252 int mask;
5253
dc97997a 5254 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5255 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5256 INTEL_RC6pp_ENABLE;
5257 else
5258 mask = INTEL_RC6_ENABLE;
5259
5260 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5261 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5262 "(requested %d, valid %d)\n",
5263 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5264
5265 return enable_rc6 & mask;
5266 }
2b4e57bd 5267
dc97997a 5268 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5269 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5270
5271 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5272}
5273
dc97997a 5274static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5275{
5276 /* All of these values are in units of 50MHz */
773ea9a8 5277
93ee2920 5278 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5279 if (IS_BROXTON(dev_priv)) {
773ea9a8 5280 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5281 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5282 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5283 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5284 } else {
773ea9a8 5285 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5286 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5287 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5288 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5289 }
3280e8b0 5290 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5291 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5292
93ee2920 5293 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5294 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5295 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5296 u32 ddcc_status = 0;
5297
5298 if (sandybridge_pcode_read(dev_priv,
5299 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5300 &ddcc_status) == 0)
93ee2920 5301 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5302 clamp_t(u8,
5303 ((ddcc_status >> 8) & 0xff),
5304 dev_priv->rps.min_freq,
5305 dev_priv->rps.max_freq);
93ee2920
TR		 5306 }
5307
dc97997a 5308 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5309 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5310 * the natural hardware unit for SKL
5311 */
c5e0688c
AG		 5312 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5313 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5314 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5315 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5316 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5317 }
3280e8b0
BW		 5318}
5319
3a45b05c
CW		 5320static void reset_rps(struct drm_i915_private *dev_priv,
5321 void (*set)(struct drm_i915_private *, u8))
5322{
5323 u8 freq = dev_priv->rps.cur_freq;
5324
5325 /* force a reset */
5326 dev_priv->rps.power = -1;
5327 dev_priv->rps.cur_freq = -1;
5328
5329 set(dev_priv, freq);
5330}
5331
b6fef0ef 5332/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5333static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5334{
b6fef0ef
JB		 5335 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5336
23eafea6 5337 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5338 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5339 /*
5340 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5341 * clear out the Control register just to avoid inconsitency
5342 * with debugfs interface, which will show Turbo as enabled
5343 * only and that is not expected by the User after adding the
5344 * WaGsvDisableTurbo. Apart from this there is no problem even
5345 * if the Turbo is left enabled in the Control register, as the
5346 * Up/Down interrupts would remain masked.
5347 */
dc97997a 5348 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5349 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5350 return;
5351 }
5352
0beb059a
AG		 5353 /* Program defaults and thresholds for RPS*/
5354 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5355 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5356
5357 /* 1 second timeout*/
5358 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5359 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5360
b6fef0ef 5361 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5362
0beb059a
AG		 5363 /* Leaning on the below call to gen6_set_rps to program/setup the
5364 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5365 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5366 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5367
5368 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5369}
5370
dc97997a 5371static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5372{
e2f80391 5373 struct intel_engine_cs *engine;
3b3f1650 5374 enum intel_engine_id id;
20e49366 5375 uint32_t rc6_mask = 0;
20e49366
ZW		 5376
5377 /* 1a: Software RC state - RC0 */
5378 I915_WRITE(GEN6_RC_STATE, 0);
5379
5380 /* 1b: Get forcewake during program sequence. Although the driver
5381 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5382 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5383
5384 /* 2a: Disable RC states. */
5385 I915_WRITE(GEN6_RC_CONTROL, 0);
5386
5387 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5388
5389 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5390 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5391 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5392 else
5393 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5394 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5395 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5396 for_each_engine(engine, dev_priv, id)
e2f80391 5397 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5398
1a3d1898 5399 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5400 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5401
20e49366 5402 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5403
38c23527
ZW		 5404 /* 2c: Program Coarse Power Gating Policies. */
5405 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5406 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5407
20e49366 5408 /* 3a: Enable RC6 */
dc97997a 5409 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5410 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5411 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5412 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5413 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5414 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5415 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5416 GEN7_RC_CTL_TO_MODE |
5417 rc6_mask);
3e7732a0
SAK		 5418 } else {
5419 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5420 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5421 GEN6_RC_CTL_EI_MODE(1) |
5422 rc6_mask);
3e7732a0 5423 }
20e49366 5424
cb07bae0
SK		 5425 /*
5426 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5427 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5428 */
dc97997a 5429 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5430 I915_WRITE(GEN9_PG_ENABLE, 0);
5431 else
5432 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5433 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5434
59bad947 5435 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5436}
5437
dc97997a 5438static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5439{
e2f80391 5440 struct intel_engine_cs *engine;
3b3f1650 5441 enum intel_engine_id id;
93ee2920 5442 uint32_t rc6_mask = 0;
6edee7f3
BW		 5443
5444 /* 1a: Software RC state - RC0 */
5445 I915_WRITE(GEN6_RC_STATE, 0);
5446
5447 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5448 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5449 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5450
5451 /* 2a: Disable RC states. */
5452 I915_WRITE(GEN6_RC_CONTROL, 0);
5453
6edee7f3
BW		 5454 /* 2b: Program RC6 thresholds.*/
5455 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5456 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5457 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5458 for_each_engine(engine, dev_priv, id)
e2f80391 5459 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5460 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5461 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5462 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5463 else
5464 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5465
5466 /* 3: Enable RC6 */
dc97997a 5467 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5468 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5469 intel_print_rc6_info(dev_priv, rc6_mask);
5470 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5471 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5472 GEN7_RC_CTL_TO_MODE |
5473 rc6_mask);
5474 else
5475 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5476 GEN6_RC_CTL_EI_MODE(1) |
5477 rc6_mask);
6edee7f3
BW		 5478
5479 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5480 I915_WRITE(GEN6_RPNSWREQ,
5481 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5482 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5483 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5484 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5485 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5486
5487 /* Docs recommend 900MHz, and 300 MHz respectively */
5488 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5489 dev_priv->rps.max_freq_softlimit << 24 |
5490 dev_priv->rps.min_freq_softlimit << 16);
5491
5492 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5493 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5494 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5495 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5496
5497 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5498
5499 /* 5: Enable RPS */
7526ed79
DV		 5500 I915_WRITE(GEN6_RP_CONTROL,
5501 GEN6_RP_MEDIA_TURBO |
5502 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5503 GEN6_RP_MEDIA_IS_GFX |
5504 GEN6_RP_ENABLE |
5505 GEN6_RP_UP_BUSY_AVG |
5506 GEN6_RP_DOWN_IDLE_AVG);
5507
5508 /* 6: Ring frequency + overclocking (our driver does this later */
5509
3a45b05c 5510 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5511
59bad947 5512 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5513}
5514
dc97997a 5515static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5516{
e2f80391 5517 struct intel_engine_cs *engine;
3b3f1650 5518 enum intel_engine_id id;
99ac9612 5519 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5520 u32 gtfifodbg;
2b4e57bd 5521 int rc6_mode;
b4ac5afc 5522 int ret;
2b4e57bd 5523
4fc688ce 5524 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5525
2b4e57bd
ED		 5526 /* Here begins a magic sequence of register writes to enable
5527 * auto-downclocking.
5528 *
5529 * Perhaps there might be some value in exposing these to
5530 * userspace...
5531 */
5532 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5533
5534 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5535 gtfifodbg = I915_READ(GTFIFODBG);
5536 if (gtfifodbg) {
2b4e57bd
ED		 5537 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5538 I915_WRITE(GTFIFODBG, gtfifodbg);
5539 }
5540
59bad947 5541 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5542
5543 /* disable the counters and set deterministic thresholds */
5544 I915_WRITE(GEN6_RC_CONTROL, 0);
5545
5546 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5547 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5548 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5549 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5550 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5551
3b3f1650 5552 for_each_engine(engine, dev_priv, id)
e2f80391 5553 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5554
5555 I915_WRITE(GEN6_RC_SLEEP, 0);
5556 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5557 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5558 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5559 else
5560 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5561 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5562 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5563
5a7dc92a 5564 /* Check if we are enabling RC6 */
dc97997a 5565 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5566 if (rc6_mode & INTEL_RC6_ENABLE)
5567 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5568
5a7dc92a 5569 /* We don't use those on Haswell */
dc97997a 5570 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5571 if (rc6_mode & INTEL_RC6p_ENABLE)
5572 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5573
5a7dc92a
ED		 5574 if (rc6_mode & INTEL_RC6pp_ENABLE)
5575 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5576 }
2b4e57bd 5577
dc97997a 5578 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5579
5580 I915_WRITE(GEN6_RC_CONTROL,
5581 rc6_mask |
5582 GEN6_RC_CTL_EI_MODE(1) |
5583 GEN6_RC_CTL_HW_ENABLE);
5584
dd75fdc8
CW		 5585 /* Power down if completely idle for over 50ms */
5586 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5587 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5588
3a45b05c 5589 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5590
31643d54
BW		 5591 rc6vids = 0;
5592 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5593 if (IS_GEN6(dev_priv) && ret) {
31643d54 5594 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5595 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5596 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5597 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5598 rc6vids &= 0xffff00;
5599 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5600 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5601 if (ret)
5602 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5603 }
5604
59bad947 5605 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5606}
5607
fb7404e8 5608static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5609{
5610 int min_freq = 15;
3ebecd07
CW		 5611 unsigned int gpu_freq;
5612 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5613 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5614 int scaling_factor = 180;
eda79642 5615 struct cpufreq_policy *policy;
2b4e57bd 5616
4fc688ce 5617 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5618
eda79642
BW		 5619 policy = cpufreq_cpu_get(0);
5620 if (policy) {
5621 max_ia_freq = policy->cpuinfo.max_freq;
5622 cpufreq_cpu_put(policy);
5623 } else {
5624 /*
5625 * Default to measured freq if none found, PCU will ensure we
5626 * don't go over
5627 */
2b4e57bd 5628 max_ia_freq = tsc_khz;
eda79642 5629 }
2b4e57bd
ED		 5630
5631 /* Convert from kHz to MHz */
5632 max_ia_freq /= 1000;
5633
153b4b95 5634 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5635 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5636 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5637
dc97997a 5638 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5639 /* Convert GT frequency to 50 HZ units */
5640 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5641 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5642 } else {
5643 min_gpu_freq = dev_priv->rps.min_freq;
5644 max_gpu_freq = dev_priv->rps.max_freq;
5645 }
5646
2b4e57bd
ED		 5647 /*
5648 * For each potential GPU frequency, load a ring frequency we'd like
5649 * to use for memory access. We do this by specifying the IA frequency
5650 * the PCU should use as a reference to determine the ring frequency.
5651 */
4c8c7743
AG		 5652 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5653 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5654 unsigned int ia_freq = 0, ring_freq = 0;
5655
dc97997a 5656 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5657 /*
5658 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5659 * No floor required for ring frequency on SKL.
5660 */
5661 ring_freq = gpu_freq;
dc97997a 5662 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5663 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5664 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5665 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5666 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5667 ring_freq = max(min_ring_freq, ring_freq);
5668 /* leave ia_freq as the default, chosen by cpufreq */
5669 } else {
5670 /* On older processors, there is no separate ring
5671 * clock domain, so in order to boost the bandwidth
5672 * of the ring, we need to upclock the CPU (ia_freq).
5673 *
5674 * For GPU frequencies less than 750MHz,
5675 * just use the lowest ring freq.
5676 */
5677 if (gpu_freq < min_freq)
5678 ia_freq = 800;
5679 else
5680 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5681 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5682 }
2b4e57bd 5683
42c0526c
BW		 5684 sandybridge_pcode_write(dev_priv,
5685 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5686 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5687 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5688 gpu_freq);
2b4e57bd 5689 }
2b4e57bd
ED		 5690}
5691
03af2045 5692static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5693{
5694 u32 val, rp0;
5695
5b5929cb 5696 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5697
43b67998 5698 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5699 case 8:
5700 /* (2 * 4) config */
5701 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5702 break;
5703 case 12:
5704 /* (2 * 6) config */
5705 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5706 break;
5707 case 16:
5708 /* (2 * 8) config */
5709 default:
5710 /* Setting (2 * 8) Min RP0 for any other combination */
5711 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5712 break;
095acd5f 5713 }
5b5929cb
JN		 5714
5715 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5716
2b6b3a09
D		 5717 return rp0;
5718}
5719
5720static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5721{
5722 u32 val, rpe;
5723
5724 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5725 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5726
5727 return rpe;
5728}
5729
7707df4a
D		 5730static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5731{
5732 u32 val, rp1;
5733
5b5929cb
JN		 5734 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5735 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5736
7707df4a
D		 5737 return rp1;
5738}
5739
f8f2b001
D		 5740static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5741{
5742 u32 val, rp1;
5743
5744 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5745
5746 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5747
5748 return rp1;
5749}
5750
03af2045 5751static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5752{
5753 u32 val, rp0;
5754
64936258 5755 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5756
5757 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5758 /* Clamp to max */
5759 rp0 = min_t(u32, rp0, 0xea);
5760
5761 return rp0;
5762}
5763
5764static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5765{
5766 u32 val, rpe;
5767
64936258 5768 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5769 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5770 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5771 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5772
5773 return rpe;
5774}
5775
03af2045 5776static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5777{
36146035
ID		 5778 u32 val;
5779
5780 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5781 /*
5782 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5783 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5784 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5785 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5786 * to make sure it matches what Punit accepts.
5787 */
5788 return max_t(u32, val, 0xc0);
0a073b84
JB		 5789}
5790
ae48434c
ID		 5791/* Check that the pctx buffer wasn't move under us. */
5792static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5793{
5794 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5795
5796 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5797 dev_priv->vlv_pctx->stolen->start);
5798}
5799
38807746
D		 5800
5801/* Check that the pcbr address is not empty. */
5802static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5803{
5804 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5805
5806 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5807}
5808
dc97997a 5809static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5810{
62106b4f 5811 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5812 unsigned long pctx_paddr, paddr;
38807746
D		 5813 u32 pcbr;
5814 int pctx_size = 32*1024;
5815
38807746
D		 5816 pcbr = I915_READ(VLV_PCBR);
5817 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5818 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5819 paddr = (dev_priv->mm.stolen_base +
62106b4f 5820 (ggtt->stolen_size - pctx_size));
38807746
D		 5821
5822 pctx_paddr = (paddr & (~4095));
5823 I915_WRITE(VLV_PCBR, pctx_paddr);
5824 }
ce611ef8
VS		 5825
5826 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5827}
5828
dc97997a 5829static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5830{
c9cddffc
JB		 5831 struct drm_i915_gem_object *pctx;
5832 unsigned long pctx_paddr;
5833 u32 pcbr;
5834 int pctx_size = 24*1024;
5835
5836 pcbr = I915_READ(VLV_PCBR);
5837 if (pcbr) {
5838 /* BIOS set it up already, grab the pre-alloc'd space */
5839 int pcbr_offset;
5840
5841 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5842 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5843 pcbr_offset,
190d6cd5 5844 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5845 pctx_size);
5846 goto out;
5847 }
5848
ce611ef8
VS		 5849 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5850
c9cddffc
JB		 5851 /*
5852 * From the Gunit register HAS:
5853 * The Gfx driver is expected to program this register and ensure
5854 * proper allocation within Gfx stolen memory. For example, this
5855 * register should be programmed such than the PCBR range does not
5856 * overlap with other ranges, such as the frame buffer, protected
5857 * memory, or any other relevant ranges.
5858 */
91c8a326 5859 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5860 if (!pctx) {
5861 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5862 goto out;
c9cddffc
JB		 5863 }
5864
5865 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5866 I915_WRITE(VLV_PCBR, pctx_paddr);
5867
5868out:
ce611ef8 5869 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5870 dev_priv->vlv_pctx = pctx;
5871}
5872
dc97997a 5873static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5874{
ae48434c
ID		 5875 if (WARN_ON(!dev_priv->vlv_pctx))
5876 return;
5877
f0cd5182 5878 i915_gem_object_put(dev_priv->vlv_pctx);
ae48434c
ID		 5879 dev_priv->vlv_pctx = NULL;
5880}
5881
c30fec65
VS		 5882static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5883{
5884 dev_priv->rps.gpll_ref_freq =
5885 vlv_get_cck_clock(dev_priv, "GPLL ref",
5886 CCK_GPLL_CLOCK_CONTROL,
5887 dev_priv->czclk_freq);
5888
5889 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5890 dev_priv->rps.gpll_ref_freq);
5891}
5892
dc97997a 5893static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5894{
2bb25c17 5895 u32 val;
4e80519e 5896
dc97997a 5897 valleyview_setup_pctx(dev_priv);
4e80519e 5898
c30fec65
VS		 5899 vlv_init_gpll_ref_freq(dev_priv);
5900
2bb25c17
VS		 5901 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5902 switch ((val >> 6) & 3) {
5903 case 0:
5904 case 1:
5905 dev_priv->mem_freq = 800;
5906 break;
5907 case 2:
5908 dev_priv->mem_freq = 1066;
5909 break;
5910 case 3:
5911 dev_priv->mem_freq = 1333;
5912 break;
5913 }
80b83b62 5914 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5915
4e80519e
ID		 5916 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5917 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5918 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5919 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5920 dev_priv->rps.max_freq);
5921
5922 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5923 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5924 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5925 dev_priv->rps.efficient_freq);
5926
f8f2b001
D		 5927 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5928 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5929 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5930 dev_priv->rps.rp1_freq);
5931
4e80519e
ID		 5932 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5933 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5934 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5935 dev_priv->rps.min_freq);
4e80519e
ID		 5936}
5937
dc97997a 5938static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5939{
2bb25c17 5940 u32 val;
2b6b3a09 5941
dc97997a 5942 cherryview_setup_pctx(dev_priv);
2b6b3a09 5943
c30fec65
VS		 5944 vlv_init_gpll_ref_freq(dev_priv);
5945
a580516d 5946 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5947 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5948 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5949
2bb25c17 5950 switch ((val >> 2) & 0x7) {
2bb25c17 5951 case 3:
2bb25c17
VS		 5952 dev_priv->mem_freq = 2000;
5953 break;
bfa7df01 5954 default:
2bb25c17
VS		 5955 dev_priv->mem_freq = 1600;
5956 break;
5957 }
80b83b62 5958 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5959
2b6b3a09
D		 5960 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5961 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5962 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5963 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5964 dev_priv->rps.max_freq);
5965
5966 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5967 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5968 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5969 dev_priv->rps.efficient_freq);
5970
7707df4a
D		 5971 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5972 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5973 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5974 dev_priv->rps.rp1_freq);
5975
5b7c91b7
D		 5976 /* PUnit validated range is only [RPe, RP0] */
5977 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5978 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5979 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5980 dev_priv->rps.min_freq);
5981
1c14762d
VS		 5982 WARN_ONCE((dev_priv->rps.max_freq |
5983 dev_priv->rps.efficient_freq |
5984 dev_priv->rps.rp1_freq |
5985 dev_priv->rps.min_freq) & 1,
5986 "Odd GPU freq values\n");
38807746
D		 5987}
5988
dc97997a 5989static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5990{
dc97997a 5991 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5992}
5993
dc97997a 5994static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5995{
e2f80391 5996 struct intel_engine_cs *engine;
3b3f1650 5997 enum intel_engine_id id;
2b6b3a09 5998 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5999
6000 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6001
297b32ec
VS		 6002 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6003 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6004 if (gtfifodbg) {
6005 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6006 gtfifodbg);
6007 I915_WRITE(GTFIFODBG, gtfifodbg);
6008 }
6009
6010 cherryview_check_pctx(dev_priv);
6011
6012 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6013 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6014 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6015
160614a2
VS		 6016 /* Disable RC states. */
6017 I915_WRITE(GEN6_RC_CONTROL, 0);
6018
38807746
D		 6019 /* 2a: Program RC6 thresholds.*/
6020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6021 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6022 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6023
3b3f1650 6024 for_each_engine(engine, dev_priv, id)
e2f80391 6025 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6026 I915_WRITE(GEN6_RC_SLEEP, 0);
6027
f4f71c7d
D		 6028 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6029 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6030
6031 /* allows RC6 residency counter to work */
6032 I915_WRITE(VLV_COUNTER_CONTROL,
6033 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6034 VLV_MEDIA_RC6_COUNT_EN |
6035 VLV_RENDER_RC6_COUNT_EN));
6036
6037 /* For now we assume BIOS is allocating and populating the PCBR */
6038 pcbr = I915_READ(VLV_PCBR);
6039
38807746 6040 /* 3: Enable RC6 */
dc97997a
CW		 6041 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6042 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6043 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6044
6045 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6046
2b6b3a09 6047 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6048 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6049 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6051 I915_WRITE(GEN6_RP_UP_EI, 66000);
6052 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6053
6054 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6055
6056 /* 5: Enable RPS */
6057 I915_WRITE(GEN6_RP_CONTROL,
6058 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6059 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6060 GEN6_RP_ENABLE |
6061 GEN6_RP_UP_BUSY_AVG |
6062 GEN6_RP_DOWN_IDLE_AVG);
6063
3ef62342
D		 6064 /* Setting Fixed Bias */
6065 val = VLV_OVERRIDE_EN |
6066 VLV_SOC_TDP_EN |
6067 CHV_BIAS_CPU_50_SOC_50;
6068 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6069
2b6b3a09
D		 6070 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6071
8d40c3ae
VS		 6072 /* RPS code assumes GPLL is used */
6073 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6074
742f491d 6075 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6076 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6077
3a45b05c 6078 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6079
59bad947 6080 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6081}
6082
dc97997a 6083static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6084{
e2f80391 6085 struct intel_engine_cs *engine;
3b3f1650 6086 enum intel_engine_id id;
2a5913a8 6087 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6088
6089 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6090
ae48434c
ID		 6091 valleyview_check_pctx(dev_priv);
6092
297b32ec
VS		 6093 gtfifodbg = I915_READ(GTFIFODBG);
6094 if (gtfifodbg) {
f7d85c1e
JB		 6095 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6096 gtfifodbg);
0a073b84
JB		 6097 I915_WRITE(GTFIFODBG, gtfifodbg);
6098 }
6099
c8d9a590 6100 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6101 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6102
160614a2
VS		 6103 /* Disable RC states. */
6104 I915_WRITE(GEN6_RC_CONTROL, 0);
6105
cad725fe 6106 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6107 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6109 I915_WRITE(GEN6_RP_UP_EI, 66000);
6110 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6111
6112 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6113
6114 I915_WRITE(GEN6_RP_CONTROL,
6115 GEN6_RP_MEDIA_TURBO |
6116 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6117 GEN6_RP_MEDIA_IS_GFX |
6118 GEN6_RP_ENABLE |
6119 GEN6_RP_UP_BUSY_AVG |
6120 GEN6_RP_DOWN_IDLE_CONT);
6121
6122 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6123 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6124 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6125
3b3f1650 6126 for_each_engine(engine, dev_priv, id)
e2f80391 6127 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6128
2f0aa304 6129 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6130
6131 /* allows RC6 residency counter to work */
49798eb2 6132 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6133 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6134 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6135 VLV_MEDIA_RC6_COUNT_EN |
6136 VLV_RENDER_RC6_COUNT_EN));
31685c25 6137
dc97997a 6138 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6139 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6140
dc97997a 6141 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6142
a2b23fe0 6143 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6144
3ef62342
D		 6145 /* Setting Fixed Bias */
6146 val = VLV_OVERRIDE_EN |
6147 VLV_SOC_TDP_EN |
6148 VLV_BIAS_CPU_125_SOC_875;
6149 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6150
64936258 6151 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6152
8d40c3ae
VS		 6153 /* RPS code assumes GPLL is used */
6154 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6155
742f491d 6156 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6157 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6158
3a45b05c 6159 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6160
59bad947 6161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6162}
6163
dde18883
ED		 6164static unsigned long intel_pxfreq(u32 vidfreq)
6165{
6166 unsigned long freq;
6167 int div = (vidfreq & 0x3f0000) >> 16;
6168 int post = (vidfreq & 0x3000) >> 12;
6169 int pre = (vidfreq & 0x7);
6170
6171 if (!pre)
6172 return 0;
6173
6174 freq = ((div * 133333) / ((1<<post) * pre));
6175
6176 return freq;
6177}
6178
eb48eb00
DV		 6179static const struct cparams {
6180 u16 i;
6181 u16 t;
6182 u16 m;
6183 u16 c;
6184} cparams[] = {
6185 { 1, 1333, 301, 28664 },
6186 { 1, 1066, 294, 24460 },
6187 { 1, 800, 294, 25192 },
6188 { 0, 1333, 276, 27605 },
6189 { 0, 1066, 276, 27605 },
6190 { 0, 800, 231, 23784 },
6191};
6192
f531dcb2 6193static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6194{
6195 u64 total_count, diff, ret;
6196 u32 count1, count2, count3, m = 0, c = 0;
6197 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6198 int i;
6199
02d71956
DV		 6200 assert_spin_locked(&mchdev_lock);
6201
20e4d407 6202 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6203
6204 /* Prevent division-by-zero if we are asking too fast.
6205 * Also, we don't get interesting results if we are polling
6206 * faster than once in 10ms, so just return the saved value
6207 * in such cases.
6208 */
6209 if (diff1 <= 10)
20e4d407 6210 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6211
6212 count1 = I915_READ(DMIEC);
6213 count2 = I915_READ(DDREC);
6214 count3 = I915_READ(CSIEC);
6215
6216 total_count = count1 + count2 + count3;
6217
6218 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6219 if (total_count < dev_priv->ips.last_count1) {
6220 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6221 diff += total_count;
6222 } else {
20e4d407 6223 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6224 }
6225
6226 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6227 if (cparams[i].i == dev_priv->ips.c_m &&
6228 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6229 m = cparams[i].m;
6230 c = cparams[i].c;
6231 break;
6232 }
6233 }
6234
6235 diff = div_u64(diff, diff1);
6236 ret = ((m * diff) + c);
6237 ret = div_u64(ret, 10);
6238
20e4d407
DV		 6239 dev_priv->ips.last_count1 = total_count;
6240 dev_priv->ips.last_time1 = now;
eb48eb00 6241
20e4d407 6242 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6243
6244 return ret;
6245}
6246
f531dcb2
CW		 6247unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6248{
6249 unsigned long val;
6250
dc97997a 6251 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6252 return 0;
6253
6254 spin_lock_irq(&mchdev_lock);
6255
6256 val = __i915_chipset_val(dev_priv);
6257
6258 spin_unlock_irq(&mchdev_lock);
6259
6260 return val;
6261}
6262
eb48eb00
DV		 6263unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6264{
6265 unsigned long m, x, b;
6266 u32 tsfs;
6267
6268 tsfs = I915_READ(TSFS);
6269
6270 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6271 x = I915_READ8(TR1);
6272
6273 b = tsfs & TSFS_INTR_MASK;
6274
6275 return ((m * x) / 127) - b;
6276}
6277
d972d6ee
MK		 6278static int _pxvid_to_vd(u8 pxvid)
6279{
6280 if (pxvid == 0)
6281 return 0;
6282
6283 if (pxvid >= 8 && pxvid < 31)
6284 pxvid = 31;
6285
6286 return (pxvid + 2) * 125;
6287}
6288
6289static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6290{
d972d6ee
MK		 6291 const int vd = _pxvid_to_vd(pxvid);
6292 const int vm = vd - 1125;
6293
dc97997a 6294 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6295 return vm > 0 ? vm : 0;
6296
6297 return vd;
eb48eb00
DV		 6298}
6299
02d71956 6300static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6301{
5ed0bdf2 6302 u64 now, diff, diffms;
eb48eb00
DV		 6303 u32 count;
6304
02d71956 6305 assert_spin_locked(&mchdev_lock);
eb48eb00 6306
5ed0bdf2
TG		 6307 now = ktime_get_raw_ns();
6308 diffms = now - dev_priv->ips.last_time2;
6309 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6310
6311 /* Don't divide by 0 */
eb48eb00
DV		 6312 if (!diffms)
6313 return;
6314
6315 count = I915_READ(GFXEC);
6316
20e4d407
DV		 6317 if (count < dev_priv->ips.last_count2) {
6318 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6319 diff += count;
6320 } else {
20e4d407 6321 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6322 }
6323
20e4d407
DV		 6324 dev_priv->ips.last_count2 = count;
6325 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6326
6327 /* More magic constants... */
6328 diff = diff * 1181;
6329 diff = div_u64(diff, diffms * 10);
20e4d407 6330 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6331}
6332
02d71956
DV		 6333void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6334{
dc97997a 6335 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6336 return;
6337
9270388e 6338 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6339
6340 __i915_update_gfx_val(dev_priv);
6341
9270388e 6342 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6343}
6344
f531dcb2 6345static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6346{
6347 unsigned long t, corr, state1, corr2, state2;
6348 u32 pxvid, ext_v;
6349
02d71956
DV		 6350 assert_spin_locked(&mchdev_lock);
6351
616847e7 6352 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6353 pxvid = (pxvid >> 24) & 0x7f;
6354 ext_v = pvid_to_extvid(dev_priv, pxvid);
6355
6356 state1 = ext_v;
6357
6358 t = i915_mch_val(dev_priv);
6359
6360 /* Revel in the empirically derived constants */
6361
6362 /* Correction factor in 1/100000 units */
6363 if (t > 80)
6364 corr = ((t * 2349) + 135940);
6365 else if (t >= 50)
6366 corr = ((t * 964) + 29317);
6367 else /* < 50 */
6368 corr = ((t * 301) + 1004);
6369
6370 corr = corr * ((150142 * state1) / 10000 - 78642);
6371 corr /= 100000;
20e4d407 6372 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6373
6374 state2 = (corr2 * state1) / 10000;
6375 state2 /= 100; /* convert to mW */
6376
02d71956 6377 __i915_update_gfx_val(dev_priv);
eb48eb00 6378
20e4d407 6379 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6380}
6381
f531dcb2
CW		 6382unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6383{
6384 unsigned long val;
6385
dc97997a 6386 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6387 return 0;
6388
6389 spin_lock_irq(&mchdev_lock);
6390
6391 val = __i915_gfx_val(dev_priv);
6392
6393 spin_unlock_irq(&mchdev_lock);
6394
6395 return val;
6396}
6397
eb48eb00
DV		 6398/**
6399 * i915_read_mch_val - return value for IPS use
6400 *
6401 * Calculate and return a value for the IPS driver to use when deciding whether
6402 * we have thermal and power headroom to increase CPU or GPU power budget.
6403 */
6404unsigned long i915_read_mch_val(void)
6405{
6406 struct drm_i915_private *dev_priv;
6407 unsigned long chipset_val, graphics_val, ret = 0;
6408
9270388e 6409 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6410 if (!i915_mch_dev)
6411 goto out_unlock;
6412 dev_priv = i915_mch_dev;
6413
f531dcb2
CW		 6414 chipset_val = __i915_chipset_val(dev_priv);
6415 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6416
6417 ret = chipset_val + graphics_val;
6418
6419out_unlock:
9270388e 6420 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6421
6422 return ret;
6423}
6424EXPORT_SYMBOL_GPL(i915_read_mch_val);
6425
6426/**
6427 * i915_gpu_raise - raise GPU frequency limit
6428 *
6429 * Raise the limit; IPS indicates we have thermal headroom.
6430 */
6431bool i915_gpu_raise(void)
6432{
6433 struct drm_i915_private *dev_priv;
6434 bool ret = true;
6435
9270388e 6436 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6437 if (!i915_mch_dev) {
6438 ret = false;
6439 goto out_unlock;
6440 }
6441 dev_priv = i915_mch_dev;
6442
20e4d407
DV		 6443 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6444 dev_priv->ips.max_delay--;
eb48eb00
DV		 6445
6446out_unlock:
9270388e 6447 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6448
6449 return ret;
6450}
6451EXPORT_SYMBOL_GPL(i915_gpu_raise);
6452
6453/**
6454 * i915_gpu_lower - lower GPU frequency limit
6455 *
6456 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6457 * frequency maximum.
6458 */
6459bool i915_gpu_lower(void)
6460{
6461 struct drm_i915_private *dev_priv;
6462 bool ret = true;
6463
9270388e 6464 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6465 if (!i915_mch_dev) {
6466 ret = false;
6467 goto out_unlock;
6468 }
6469 dev_priv = i915_mch_dev;
6470
20e4d407
DV		 6471 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6472 dev_priv->ips.max_delay++;
eb48eb00
DV		 6473
6474out_unlock:
9270388e 6475 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6476
6477 return ret;
6478}
6479EXPORT_SYMBOL_GPL(i915_gpu_lower);
6480
6481/**
6482 * i915_gpu_busy - indicate GPU business to IPS
6483 *
6484 * Tell the IPS driver whether or not the GPU is busy.
6485 */
6486bool i915_gpu_busy(void)
6487{
eb48eb00
DV		 6488 bool ret = false;
6489
9270388e 6490 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6491 if (i915_mch_dev)
6492 ret = i915_mch_dev->gt.awake;
9270388e 6493 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6494
6495 return ret;
6496}
6497EXPORT_SYMBOL_GPL(i915_gpu_busy);
6498
6499/**
6500 * i915_gpu_turbo_disable - disable graphics turbo
6501 *
6502 * Disable graphics turbo by resetting the max frequency and setting the
6503 * current frequency to the default.
6504 */
6505bool i915_gpu_turbo_disable(void)
6506{
6507 struct drm_i915_private *dev_priv;
6508 bool ret = true;
6509
9270388e 6510 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6511 if (!i915_mch_dev) {
6512 ret = false;
6513 goto out_unlock;
6514 }
6515 dev_priv = i915_mch_dev;
6516
20e4d407 6517 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6518
91d14251 6519 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6520 ret = false;
6521
6522out_unlock:
9270388e 6523 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6524
6525 return ret;
6526}
6527EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6528
6529/**
6530 * Tells the intel_ips driver that the i915 driver is now loaded, if
6531 * IPS got loaded first.
6532 *
6533 * This awkward dance is so that neither module has to depend on the
6534 * other in order for IPS to do the appropriate communication of
6535 * GPU turbo limits to i915.
6536 */
6537static void
6538ips_ping_for_i915_load(void)
6539{
6540 void (*link)(void);
6541
6542 link = symbol_get(ips_link_to_i915_driver);
6543 if (link) {
6544 link();
6545 symbol_put(ips_link_to_i915_driver);
6546 }
6547}
6548
6549void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6550{
02d71956
DV		 6551 /* We only register the i915 ips part with intel-ips once everything is
6552 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6553 spin_lock_irq(&mchdev_lock);
eb48eb00 6554 i915_mch_dev = dev_priv;
9270388e 6555 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6556
6557 ips_ping_for_i915_load();
6558}
6559
6560void intel_gpu_ips_teardown(void)
6561{
9270388e 6562 spin_lock_irq(&mchdev_lock);
eb48eb00 6563 i915_mch_dev = NULL;
9270388e 6564 spin_unlock_irq(&mchdev_lock);
eb48eb00 6565}
76c3552f 6566
dc97997a 6567static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6568{
dde18883
ED		 6569 u32 lcfuse;
6570 u8 pxw[16];
6571 int i;
6572
6573 /* Disable to program */
6574 I915_WRITE(ECR, 0);
6575 POSTING_READ(ECR);
6576
6577 /* Program energy weights for various events */
6578 I915_WRITE(SDEW, 0x15040d00);
6579 I915_WRITE(CSIEW0, 0x007f0000);
6580 I915_WRITE(CSIEW1, 0x1e220004);
6581 I915_WRITE(CSIEW2, 0x04000004);
6582
6583 for (i = 0; i < 5; i++)
616847e7 6584 I915_WRITE(PEW(i), 0);
dde18883 6585 for (i = 0; i < 3; i++)
616847e7 6586 I915_WRITE(DEW(i), 0);
dde18883
ED		 6587
6588 /* Program P-state weights to account for frequency power adjustment */
6589 for (i = 0; i < 16; i++) {
616847e7 6590 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6591 unsigned long freq = intel_pxfreq(pxvidfreq);
6592 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6593 PXVFREQ_PX_SHIFT;
6594 unsigned long val;
6595
6596 val = vid * vid;
6597 val *= (freq / 1000);
6598 val *= 255;
6599 val /= (127*127*900);
6600 if (val > 0xff)
6601 DRM_ERROR("bad pxval: %ld\n", val);
6602 pxw[i] = val;
6603 }
6604 /* Render standby states get 0 weight */
6605 pxw[14] = 0;
6606 pxw[15] = 0;
6607
6608 for (i = 0; i < 4; i++) {
6609 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6610 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6611 I915_WRITE(PXW(i), val);
dde18883
ED		 6612 }
6613
6614 /* Adjust magic regs to magic values (more experimental results) */
6615 I915_WRITE(OGW0, 0);
6616 I915_WRITE(OGW1, 0);
6617 I915_WRITE(EG0, 0x00007f00);
6618 I915_WRITE(EG1, 0x0000000e);
6619 I915_WRITE(EG2, 0x000e0000);
6620 I915_WRITE(EG3, 0x68000300);
6621 I915_WRITE(EG4, 0x42000000);
6622 I915_WRITE(EG5, 0x00140031);
6623 I915_WRITE(EG6, 0);
6624 I915_WRITE(EG7, 0);
6625
6626 for (i = 0; i < 8; i++)
616847e7 6627 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6628
6629 /* Enable PMON + select events */
6630 I915_WRITE(ECR, 0x80000019);
6631
6632 lcfuse = I915_READ(LCFUSE02);
6633
20e4d407 6634 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6635}
6636
dc97997a 6637void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6638{
b268c699
ID		 6639 /*
6640 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6641 * requirement.
6642 */
6643 if (!i915.enable_rc6) {
6644 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6645 intel_runtime_pm_get(dev_priv);
6646 }
e6069ca8 6647
b5163dbb 6648 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6649 mutex_lock(&dev_priv->rps.hw_lock);
6650
6651 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6652 if (IS_CHERRYVIEW(dev_priv))
6653 cherryview_init_gt_powersave(dev_priv);
6654 else if (IS_VALLEYVIEW(dev_priv))
6655 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6656 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6657 gen6_init_rps_frequencies(dev_priv);
6658
6659 /* Derive initial user preferences/limits from the hardware limits */
6660 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6661 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6662
6663 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6664 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6665
6666 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6667 dev_priv->rps.min_freq_softlimit =
6668 max_t(int,
6669 dev_priv->rps.efficient_freq,
6670 intel_freq_opcode(dev_priv, 450));
6671
99ac9612
CW		 6672 /* After setting max-softlimit, find the overclock max freq */
6673 if (IS_GEN6(dev_priv) ||
6674 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6675 u32 params = 0;
6676
6677 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6678 if (params & BIT(31)) { /* OC supported */
6679 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6680 (dev_priv->rps.max_freq & 0xff) * 50,
6681 (params & 0xff) * 50);
6682 dev_priv->rps.max_freq = params & 0xff;
6683 }
6684 }
6685
29ecd78d
CW		 6686 /* Finally allow us to boost to max by default */
6687 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6688
773ea9a8 6689 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6690 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6691
6692 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6693}
6694
dc97997a 6695void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6696{
8dac1e1f 6697 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6698 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6699
6700 if (!i915.enable_rc6)
6701 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6702}
6703
54b4f68f
CW		 6704/**
6705 * intel_suspend_gt_powersave - suspend PM work and helper threads
6706 * @dev_priv: i915 device
6707 *
6708 * We don't want to disable RC6 or other features here, we just want
6709 * to make sure any work we've queued has finished and won't bother
6710 * us while we're suspended.
6711 */
6712void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6713{
6714 if (INTEL_GEN(dev_priv) < 6)
6715 return;
6716
6717 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6718 intel_runtime_pm_put(dev_priv);
6719
6720 /* gen6_rps_idle() will be called later to disable interrupts */
6721}
6722
b7137e0c
CW		 6723void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6724{
6725 dev_priv->rps.enabled = true; /* force disabling */
6726 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6727
6728 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6729}
6730
dc97997a 6731void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6732{
b7137e0c
CW		 6733 if (!READ_ONCE(dev_priv->rps.enabled))
6734 return;
e494837a 6735
b7137e0c 6736 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6737
b7137e0c
CW		 6738 if (INTEL_GEN(dev_priv) >= 9) {
6739 gen9_disable_rc6(dev_priv);
6740 gen9_disable_rps(dev_priv);
6741 } else if (IS_CHERRYVIEW(dev_priv)) {
6742 cherryview_disable_rps(dev_priv);
6743 } else if (IS_VALLEYVIEW(dev_priv)) {
6744 valleyview_disable_rps(dev_priv);
6745 } else if (INTEL_GEN(dev_priv) >= 6) {
6746 gen6_disable_rps(dev_priv);
6747 } else if (IS_IRONLAKE_M(dev_priv)) {
6748 ironlake_disable_drps(dev_priv);
930ebb46 6749 }
b7137e0c
CW		 6750
6751 dev_priv->rps.enabled = false;
6752 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6753}
6754
b7137e0c 6755void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6756{
54b4f68f
CW		 6757 /* We shouldn't be disabling as we submit, so this should be less
6758 * racy than it appears!
6759 */
b7137e0c
CW		 6760 if (READ_ONCE(dev_priv->rps.enabled))
6761 return;
1a01ab3b 6762
b7137e0c
CW		 6763 /* Powersaving is controlled by the host when inside a VM */
6764 if (intel_vgpu_active(dev_priv))
6765 return;
0a073b84 6766
b7137e0c 6767 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6768
6769 if (IS_CHERRYVIEW(dev_priv)) {
6770 cherryview_enable_rps(dev_priv);
6771 } else if (IS_VALLEYVIEW(dev_priv)) {
6772 valleyview_enable_rps(dev_priv);
b7137e0c 6773 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6774 gen9_enable_rc6(dev_priv);
6775 gen9_enable_rps(dev_priv);
6776 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6777 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6778 } else if (IS_BROADWELL(dev_priv)) {
6779 gen8_enable_rps(dev_priv);
fb7404e8 6780 gen6_update_ring_freq(dev_priv);
b7137e0c 6781 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6782 gen6_enable_rps(dev_priv);
fb7404e8 6783 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6784 } else if (IS_IRONLAKE_M(dev_priv)) {
6785 ironlake_enable_drps(dev_priv);
6786 intel_init_emon(dev_priv);
0a073b84 6787 }
aed242ff
CW		 6788
6789 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6790 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6791
6792 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6793 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6794
54b4f68f 6795 dev_priv->rps.enabled = true;
b7137e0c
CW		 6796 mutex_unlock(&dev_priv->rps.hw_lock);
6797}
3cc134e3 6798
54b4f68f
CW		 6799static void __intel_autoenable_gt_powersave(struct work_struct *work)
6800{
6801 struct drm_i915_private *dev_priv =
6802 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6803 struct intel_engine_cs *rcs;
6804 struct drm_i915_gem_request *req;
6805
6806 if (READ_ONCE(dev_priv->rps.enabled))
6807 goto out;
6808
3b3f1650 6809 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6810 if (rcs->last_context)
6811 goto out;
6812
6813 if (!rcs->init_context)
6814 goto out;
6815
6816 mutex_lock(&dev_priv->drm.struct_mutex);
6817
6818 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6819 if (IS_ERR(req))
6820 goto unlock;
6821
6822 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6823 rcs->init_context(req);
6824
6825 /* Mark the device busy, calling intel_enable_gt_powersave() */
6826 i915_add_request_no_flush(req);
6827
6828unlock:
6829 mutex_unlock(&dev_priv->drm.struct_mutex);
6830out:
6831 intel_runtime_pm_put(dev_priv);
6832}
6833
6834void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6835{
6836 if (READ_ONCE(dev_priv->rps.enabled))
6837 return;
6838
6839 if (IS_IRONLAKE_M(dev_priv)) {
6840 ironlake_enable_drps(dev_priv);
54b4f68f 6841 intel_init_emon(dev_priv);
54b4f68f
CW		 6842 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6843 /*
6844 * PCU communication is slow and this doesn't need to be
6845 * done at any specific time, so do this out of our fast path
6846 * to make resume and init faster.
6847 *
6848 * We depend on the HW RC6 power context save/restore
6849 * mechanism when entering D3 through runtime PM suspend. So
6850 * disable RPM until RPS/RC6 is properly setup. We can only
6851 * get here via the driver load/system resume/runtime resume
6852 * paths, so the _noresume version is enough (and in case of
6853 * runtime resume it's necessary).
6854 */
6855 if (queue_delayed_work(dev_priv->wq,
6856 &dev_priv->rps.autoenable_work,
6857 round_jiffies_up_relative(HZ)))
6858 intel_runtime_pm_get_noresume(dev_priv);
6859 }
6860}
6861
46f16e63 6862static void ibx_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6863{
3107bd48
DV		 6864 /*
6865 * On Ibex Peak and Cougar Point, we need to disable clock
6866 * gating for the panel power sequencer or it will fail to
6867 * start up when no ports are active.
6868 */
6869 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6870}
6871
46f16e63 6872static void g4x_disable_trickle_feed(struct drm_i915_private *dev_priv)
0e088b8f 6873{
b12ce1d8 6874 enum pipe pipe;
0e088b8f 6875
055e393f 6876 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6877 I915_WRITE(DSPCNTR(pipe),
6878 I915_READ(DSPCNTR(pipe)) |
6879 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6880
6881 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6882 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6883 }
6884}
6885
46f16e63 6886static void ilk_init_lp_watermarks(struct drm_i915_private *dev_priv)
017636cc 6887{
017636cc
VS		 6888 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6889 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6890 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6891
6892 /*
6893 * Don't touch WM1S_LP_EN here.
6894 * Doing so could cause underruns.
6895 */
6896}
6897
46f16e63 6898static void ironlake_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 6899{
231e54f6 6900 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6901
f1e8fa56
DL		 6902 /*
6903 * Required for FBC
6904 * WaFbcDisableDpfcClockGating:ilk
6905 */
4d47e4f5
DL		 6906 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6907 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6908 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6909
6910 I915_WRITE(PCH_3DCGDIS0,
6911 MARIUNIT_CLOCK_GATE_DISABLE |
6912 SVSMUNIT_CLOCK_GATE_DISABLE);
6913 I915_WRITE(PCH_3DCGDIS1,
6914 VFMUNIT_CLOCK_GATE_DISABLE);
6915
6f1d69b0
ED		 6916 /*
6917 * According to the spec the following bits should be set in
6918 * order to enable memory self-refresh
6919 * The bit 22/21 of 0x42004
6920 * The bit 5 of 0x42020
6921 * The bit 15 of 0x45000
6922 */
6923 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6924 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6925 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6926 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6927 I915_WRITE(DISP_ARB_CTL,
6928 (I915_READ(DISP_ARB_CTL) |
6929 DISP_FBC_WM_DIS));
017636cc 6930
46f16e63 6931 ilk_init_lp_watermarks(dev_priv);
6f1d69b0
ED		 6932
6933 /*
6934 * Based on the document from hardware guys the following bits
6935 * should be set unconditionally in order to enable FBC.
6936 * The bit 22 of 0x42000
6937 * The bit 22 of 0x42004
6938 * The bit 7,8,9 of 0x42020.
6939 */
50a0bc90 6940 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6941 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6942 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6943 I915_READ(ILK_DISPLAY_CHICKEN1) |
6944 ILK_FBCQ_DIS);
6945 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6946 I915_READ(ILK_DISPLAY_CHICKEN2) |
6947 ILK_DPARB_GATE);
6f1d69b0
ED		 6948 }
6949
4d47e4f5
DL		 6950 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6951
6f1d69b0
ED		 6952 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6953 I915_READ(ILK_DISPLAY_CHICKEN2) |
6954 ILK_ELPIN_409_SELECT);
6955 I915_WRITE(_3D_CHICKEN2,
6956 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6957 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6958
ecdb4eb7 6959 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6960 I915_WRITE(CACHE_MODE_0,
6961 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6962
4e04632e
AG		 6963 /* WaDisable_RenderCache_OperationalFlush:ilk */
6964 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6965
46f16e63 6966 g4x_disable_trickle_feed(dev_priv);
bdad2b2f 6967
46f16e63 6968 ibx_init_clock_gating(dev_priv);
3107bd48
DV		 6969}
6970
46f16e63 6971static void cpt_init_clock_gating(struct drm_i915_private *dev_priv)
3107bd48 6972{
3107bd48 6973 int pipe;
3f704fa2 6974 uint32_t val;
3107bd48
DV		 6975
6976 /*
6977 * On Ibex Peak and Cougar Point, we need to disable clock
6978 * gating for the panel power sequencer or it will fail to
6979 * start up when no ports are active.
6980 */
cd664078
JB		 6981 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6982 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6983 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6984 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6985 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6986 /* The below fixes the weird display corruption, a few pixels shifted
6987 * downward, on (only) LVDS of some HP laptops with IVY.
6988 */
055e393f 6989 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6990 val = I915_READ(TRANS_CHICKEN2(pipe));
6991 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6992 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 6993 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 6994 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 6995 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
6996 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
6997 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 6998 I915_WRITE(TRANS_CHICKEN2(pipe), val);
6999 }
3107bd48 7000 /* WADP0ClockGatingDisable */
055e393f 7001 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7002 I915_WRITE(TRANS_CHICKEN1(pipe),
7003 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7004 }
6f1d69b0
ED		 7005}
7006
46f16e63 7007static void gen6_check_mch_setup(struct drm_i915_private *dev_priv)
1d7aaa0c 7008{
1d7aaa0c
DV		 7009 uint32_t tmp;
7010
7011 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7012 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7013 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7014 tmp);
1d7aaa0c
DV		 7015}
7016
46f16e63 7017static void gen6_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7018{
231e54f6 7019 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7020
231e54f6 7021 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7022
7023 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7024 I915_READ(ILK_DISPLAY_CHICKEN2) |
7025 ILK_ELPIN_409_SELECT);
7026
ecdb4eb7 7027 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7028 I915_WRITE(_3D_CHICKEN,
7029 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7030
4e04632e
AG		 7031 /* WaDisable_RenderCache_OperationalFlush:snb */
7032 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7033
8d85d272
VS		 7034 /*
7035 * BSpec recoomends 8x4 when MSAA is used,
7036 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7037 *
7038 * Note that PS/WM thread counts depend on the WIZ hashing
7039 * disable bit, which we don't touch here, but it's good
7040 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7041 */
7042 I915_WRITE(GEN6_GT_MODE,
98533251 7043 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7044
46f16e63 7045 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7046
6f1d69b0 7047 I915_WRITE(CACHE_MODE_0,
50743298 7048 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7049
7050 I915_WRITE(GEN6_UCGCTL1,
7051 I915_READ(GEN6_UCGCTL1) |
7052 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7053 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7054
7055 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7056 * gating disable must be set. Failure to set it results in
7057 * flickering pixels due to Z write ordering failures after
7058 * some amount of runtime in the Mesa "fire" demo, and Unigine
7059 * Sanctuary and Tropics, and apparently anything else with
7060 * alpha test or pixel discard.
7061 *
7062 * According to the spec, bit 11 (RCCUNIT) must also be set,
7063 * but we didn't debug actual testcases to find it out.
0f846f81 7064 *
ef59318c
VS		 7065 * WaDisableRCCUnitClockGating:snb
7066 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7067 */
7068 I915_WRITE(GEN6_UCGCTL2,
7069 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7070 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7071
5eb146dd 7072 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7073 I915_WRITE(_3D_CHICKEN3,
7074 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7075
e927ecde
VS		 7076 /*
7077 * Bspec says:
7078 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7079 * 3DSTATE_SF number of SF output attributes is more than 16."
7080 */
7081 I915_WRITE(_3D_CHICKEN3,
7082 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7083
6f1d69b0
ED		 7084 /*
7085 * According to the spec the following bits should be
7086 * set in order to enable memory self-refresh and fbc:
7087 * The bit21 and bit22 of 0x42000
7088 * The bit21 and bit22 of 0x42004
7089 * The bit5 and bit7 of 0x42020
7090 * The bit14 of 0x70180
7091 * The bit14 of 0x71180
4bb35334
DL		 7092 *
7093 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7094 */
7095 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7096 I915_READ(ILK_DISPLAY_CHICKEN1) |
7097 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7098 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7099 I915_READ(ILK_DISPLAY_CHICKEN2) |
7100 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7101 I915_WRITE(ILK_DSPCLK_GATE_D,
7102 I915_READ(ILK_DSPCLK_GATE_D) |
7103 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7104 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7105
46f16e63 7106 g4x_disable_trickle_feed(dev_priv);
f8f2ac9a 7107
46f16e63 7108 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7109
46f16e63 7110 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7111}
7112
7113static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7114{
7115 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7116
3aad9059 7117 /*
46680e0a 7118 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7119 *
7120 * This actually overrides the dispatch
7121 * mode for all thread types.
7122 */
6f1d69b0
ED		 7123 reg &= ~GEN7_FF_SCHED_MASK;
7124 reg |= GEN7_FF_TS_SCHED_HW;
7125 reg |= GEN7_FF_VS_SCHED_HW;
7126 reg |= GEN7_FF_DS_SCHED_HW;
7127
7128 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7129}
7130
46f16e63 7131static void lpt_init_clock_gating(struct drm_i915_private *dev_priv)
17a303ec 7132{
17a303ec
PZ		 7133 /*
7134 * TODO: this bit should only be enabled when really needed, then
7135 * disabled when not needed anymore in order to save power.
7136 */
4f8036a2 7137 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7138 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7139 I915_READ(SOUTH_DSPCLK_GATE_D) |
7140 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7141
7142 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7143 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7144 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7145 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7146}
7147
712bf364 7148static void lpt_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7149{
4f8036a2 7150 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7151 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7152
7153 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7154 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7155 }
7156}
7157
450174fe
ID		 7158static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7159 int general_prio_credits,
7160 int high_prio_credits)
7161{
7162 u32 misccpctl;
7163
7164 /* WaTempDisableDOPClkGating:bdw */
7165 misccpctl = I915_READ(GEN7_MISCCPCTL);
7166 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7167
7168 I915_WRITE(GEN8_L3SQCREG1,
7169 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7170 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7171
7172 /*
7173 * Wait at least 100 clocks before re-enabling clock gating.
7174 * See the definition of L3SQCREG1 in BSpec.
7175 */
7176 POSTING_READ(GEN8_L3SQCREG1);
7177 udelay(1);
7178 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7179}
7180
46f16e63 7181static void kabylake_init_clock_gating(struct drm_i915_private *dev_priv)
9498dba7 7182{
46f16e63 7183 gen9_init_clock_gating(dev_priv);
9498dba7
MK		 7184
7185 /* WaDisableSDEUnitClockGating:kbl */
7186 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7187 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7188 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7189
7190 /* WaDisableGamClockGating:kbl */
7191 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7192 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7193 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7194
7195 /* WaFbcNukeOnHostModify:kbl */
7196 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7197 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7198}
7199
46f16e63 7200static void skylake_init_clock_gating(struct drm_i915_private *dev_priv)
dc00b6a0 7201{
46f16e63 7202 gen9_init_clock_gating(dev_priv);
44fff99f
MK		 7203
7204 /* WAC6entrylatency:skl */
7205 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7206 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7207
7208 /* WaFbcNukeOnHostModify:skl */
7209 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7210 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7211}
7212
46f16e63 7213static void broadwell_init_clock_gating(struct drm_i915_private *dev_priv)
1020a5c2 7214{
07d27e20 7215 enum pipe pipe;
1020a5c2 7216
46f16e63 7217 ilk_init_lp_watermarks(dev_priv);
50ed5fbd 7218
ab57fff1 7219 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7220 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7221
ab57fff1 7222 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7223 I915_WRITE(CHICKEN_PAR1_1,
7224 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7225
ab57fff1 7226 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7227 for_each_pipe(dev_priv, pipe) {
07d27e20 7228 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7229 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7230 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7231 }
63801f21 7232
ab57fff1
BW		 7233 /* WaVSRefCountFullforceMissDisable:bdw */
7234 /* WaDSRefCountFullforceMissDisable:bdw */
7235 I915_WRITE(GEN7_FF_THREAD_MODE,
7236 I915_READ(GEN7_FF_THREAD_MODE) &
7237 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7238
295e8bb7
VS		 7239 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7240 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7241
7242 /* WaDisableSDEUnitClockGating:bdw */
7243 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7244 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7245
450174fe
ID		 7246 /* WaProgramL3SqcReg1Default:bdw */
7247 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7248
6d50b065
VS		 7249 /*
7250 * WaGttCachingOffByDefault:bdw
7251 * GTT cache may not work with big pages, so if those
7252 * are ever enabled GTT cache may need to be disabled.
7253 */
7254 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7255
17e0adf0
MK		 7256 /* WaKVMNotificationOnConfigChange:bdw */
7257 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7258 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7259
46f16e63 7260 lpt_init_clock_gating(dev_priv);
1020a5c2
BW		 7261}
7262
46f16e63 7263static void haswell_init_clock_gating(struct drm_i915_private *dev_priv)
cad2a2d7 7264{
46f16e63 7265 ilk_init_lp_watermarks(dev_priv);
cad2a2d7 7266
f3fc4884
FJ		 7267 /* L3 caching of data atomics doesn't work -- disable it. */
7268 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7269 I915_WRITE(HSW_ROW_CHICKEN3,
7270 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7271
ecdb4eb7 7272 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7273 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7274 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7275 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7276
e36ea7ff
VS		 7277 /* WaVSRefCountFullforceMissDisable:hsw */
7278 I915_WRITE(GEN7_FF_THREAD_MODE,
7279 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7280
4e04632e
AG		 7281 /* WaDisable_RenderCache_OperationalFlush:hsw */
7282 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7283
fe27c606
CW		 7284 /* enable HiZ Raw Stall Optimization */
7285 I915_WRITE(CACHE_MODE_0_GEN7,
7286 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7287
ecdb4eb7 7288 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7289 I915_WRITE(CACHE_MODE_1,
7290 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7291
a12c4967
VS		 7292 /*
7293 * BSpec recommends 8x4 when MSAA is used,
7294 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7295 *
7296 * Note that PS/WM thread counts depend on the WIZ hashing
7297 * disable bit, which we don't touch here, but it's good
7298 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7299 */
7300 I915_WRITE(GEN7_GT_MODE,
98533251 7301 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7302
94411593
KG		 7303 /* WaSampleCChickenBitEnable:hsw */
7304 I915_WRITE(HALF_SLICE_CHICKEN3,
7305 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7306
ecdb4eb7 7307 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7308 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7309
90a88643
PZ		 7310 /* WaRsPkgCStateDisplayPMReq:hsw */
7311 I915_WRITE(CHICKEN_PAR1_1,
7312 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7313
46f16e63 7314 lpt_init_clock_gating(dev_priv);
cad2a2d7
ED		 7315}
7316
46f16e63 7317static void ivybridge_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7318{
20848223 7319 uint32_t snpcr;
6f1d69b0 7320
46f16e63 7321 ilk_init_lp_watermarks(dev_priv);
6f1d69b0 7322
231e54f6 7323 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7324
ecdb4eb7 7325 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7326 I915_WRITE(_3D_CHICKEN3,
7327 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7328
ecdb4eb7 7329 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7330 I915_WRITE(IVB_CHICKEN3,
7331 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7332 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7333
ecdb4eb7 7334 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7335 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7336 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7337 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7338
4e04632e
AG		 7339 /* WaDisable_RenderCache_OperationalFlush:ivb */
7340 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7341
ecdb4eb7 7342 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7343 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7344 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7345
ecdb4eb7 7346 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7347 I915_WRITE(GEN7_L3CNTLREG1,
7348 GEN7_WA_FOR_GEN7_L3_CONTROL);
7349 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7350 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7351 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7352 I915_WRITE(GEN7_ROW_CHICKEN2,
7353 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7354 else {
7355 /* must write both registers */
7356 I915_WRITE(GEN7_ROW_CHICKEN2,
7357 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7358 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7359 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7360 }
6f1d69b0 7361
ecdb4eb7 7362 /* WaForceL3Serialization:ivb */
61939d97
JB		 7363 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7364 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7365
1b80a19a 7366 /*
0f846f81 7367 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7368 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7369 */
7370 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7371 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7372
ecdb4eb7 7373 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7374 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7375 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7376 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7377
46f16e63 7378 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7379
7380 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7381
22721343
CW		 7382 if (0) { /* causes HiZ corruption on ivb:gt1 */
7383 /* enable HiZ Raw Stall Optimization */
7384 I915_WRITE(CACHE_MODE_0_GEN7,
7385 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7386 }
116f2b6d 7387
ecdb4eb7 7388 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7389 I915_WRITE(CACHE_MODE_1,
7390 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7391
a607c1a4
VS		 7392 /*
7393 * BSpec recommends 8x4 when MSAA is used,
7394 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7395 *
7396 * Note that PS/WM thread counts depend on the WIZ hashing
7397 * disable bit, which we don't touch here, but it's good
7398 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7399 */
7400 I915_WRITE(GEN7_GT_MODE,
98533251 7401 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7402
20848223
BW		 7403 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7404 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7405 snpcr |= GEN6_MBC_SNPCR_MED;
7406 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7407
6e266956 7408 if (!HAS_PCH_NOP(dev_priv))
46f16e63 7409 cpt_init_clock_gating(dev_priv);
1d7aaa0c 7410
46f16e63 7411 gen6_check_mch_setup(dev_priv);
6f1d69b0
ED		 7412}
7413
46f16e63 7414static void valleyview_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7415{
ecdb4eb7 7416 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7417 I915_WRITE(_3D_CHICKEN3,
7418 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7419
ecdb4eb7 7420 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7421 I915_WRITE(IVB_CHICKEN3,
7422 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7423 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7424
fad7d36e 7425 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7426 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7427 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7428 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7429 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7430
4e04632e
AG		 7431 /* WaDisable_RenderCache_OperationalFlush:vlv */
7432 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7433
ecdb4eb7 7434 /* WaForceL3Serialization:vlv */
61939d97
JB		 7435 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7436 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7437
ecdb4eb7 7438 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7439 I915_WRITE(GEN7_ROW_CHICKEN2,
7440 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7441
ecdb4eb7 7442 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7443 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7444 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7445 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7446
46680e0a
VS		 7447 gen7_setup_fixed_func_scheduler(dev_priv);
7448
3c0edaeb 7449 /*
0f846f81 7450 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7451 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7452 */
7453 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7454 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7455
c98f5062
AG		 7456 /* WaDisableL3Bank2xClockGate:vlv
7457 * Disabling L3 clock gating- MMIO 940c[25] = 1
7458 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7459 I915_WRITE(GEN7_UCGCTL4,
7460 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7461
afd58e79
VS		 7462 /*
7463 * BSpec says this must be set, even though
7464 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7465 */
6b26c86d
DV		 7466 I915_WRITE(CACHE_MODE_1,
7467 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7468
da2518f9
VS		 7469 /*
7470 * BSpec recommends 8x4 when MSAA is used,
7471 * however in practice 16x4 seems fastest.
7472 *
7473 * Note that PS/WM thread counts depend on the WIZ hashing
7474 * disable bit, which we don't touch here, but it's good
7475 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7476 */
7477 I915_WRITE(GEN7_GT_MODE,
7478 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7479
031994ee
VS		 7480 /*
7481 * WaIncreaseL3CreditsForVLVB0:vlv
7482 * This is the hardware default actually.
7483 */
7484 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7485
2d809570 7486 /*
ecdb4eb7 7487 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7488 * Disable clock gating on th GCFG unit to prevent a delay
7489 * in the reporting of vblank events.
7490 */
7a0d1eed 7491 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7492}
7493
46f16e63 7494static void cherryview_init_clock_gating(struct drm_i915_private *dev_priv)
a4565da8 7495{
232ce337
VS		 7496 /* WaVSRefCountFullforceMissDisable:chv */
7497 /* WaDSRefCountFullforceMissDisable:chv */
7498 I915_WRITE(GEN7_FF_THREAD_MODE,
7499 I915_READ(GEN7_FF_THREAD_MODE) &
7500 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7501
7502 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7503 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7504 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7505
7506 /* WaDisableCSUnitClockGating:chv */
7507 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7508 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7509
7510 /* WaDisableSDEUnitClockGating:chv */
7511 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7512 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7513
450174fe
ID		 7514 /*
7515 * WaProgramL3SqcReg1Default:chv
7516 * See gfxspecs/Related Documents/Performance Guide/
7517 * LSQC Setting Recommendations.
7518 */
7519 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7520
6d50b065
VS		 7521 /*
7522 * GTT cache may not work with big pages, so if those
7523 * are ever enabled GTT cache may need to be disabled.
7524 */
7525 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7526}
7527
46f16e63 7528static void g4x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7529{
6f1d69b0
ED		 7530 uint32_t dspclk_gate;
7531
7532 I915_WRITE(RENCLK_GATE_D1, 0);
7533 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7534 GS_UNIT_CLOCK_GATE_DISABLE |
7535 CL_UNIT_CLOCK_GATE_DISABLE);
7536 I915_WRITE(RAMCLK_GATE_D, 0);
7537 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7538 OVRUNIT_CLOCK_GATE_DISABLE |
7539 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7540 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7541 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7542 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7543
7544 /* WaDisableRenderCachePipelinedFlush */
7545 I915_WRITE(CACHE_MODE_0,
7546 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7547
4e04632e
AG		 7548 /* WaDisable_RenderCache_OperationalFlush:g4x */
7549 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7550
46f16e63 7551 g4x_disable_trickle_feed(dev_priv);
6f1d69b0
ED		 7552}
7553
46f16e63 7554static void crestline_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7555{
6f1d69b0
ED		 7556 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7557 I915_WRITE(RENCLK_GATE_D2, 0);
7558 I915_WRITE(DSPCLK_GATE_D, 0);
7559 I915_WRITE(RAMCLK_GATE_D, 0);
7560 I915_WRITE16(DEUC, 0);
20f94967
VS		 7561 I915_WRITE(MI_ARB_STATE,
7562 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7563
7564 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7565 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7566}
7567
46f16e63 7568static void broadwater_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7569{
6f1d69b0
ED		 7570 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7571 I965_RCC_CLOCK_GATE_DISABLE |
7572 I965_RCPB_CLOCK_GATE_DISABLE |
7573 I965_ISC_CLOCK_GATE_DISABLE |
7574 I965_FBC_CLOCK_GATE_DISABLE);
7575 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7576 I915_WRITE(MI_ARB_STATE,
7577 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7578
7579 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7580 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7581}
7582
46f16e63 7583static void gen3_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7584{
6f1d69b0
ED		 7585 u32 dstate = I915_READ(D_STATE);
7586
7587 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7588 DSTATE_DOT_CLOCK_GATING;
7589 I915_WRITE(D_STATE, dstate);
13a86b85 7590
9b1e14f4 7591 if (IS_PINEVIEW(dev_priv))
13a86b85 7592 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7593
7594 /* IIR "flip pending" means done if this bit is set */
7595 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7596
7597 /* interrupts should cause a wake up from C3 */
3299254f 7598 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7599
7600 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7601 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7602
7603 I915_WRITE(MI_ARB_STATE,
7604 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7605}
7606
46f16e63 7607static void i85x_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7608{
6f1d69b0 7609 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7610
7611 /* interrupts should cause a wake up from C3 */
7612 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7613 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7614
7615 I915_WRITE(MEM_MODE,
7616 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7617}
7618
46f16e63 7619static void i830_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7620{
6f1d69b0 7621 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7622
7623 I915_WRITE(MEM_MODE,
7624 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7625 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7626}
7627
46f16e63 7628void intel_init_clock_gating(struct drm_i915_private *dev_priv)
6f1d69b0 7629{
46f16e63 7630 dev_priv->display.init_clock_gating(dev_priv);
6f1d69b0
ED		 7631}
7632
712bf364 7633void intel_suspend_hw(struct drm_i915_private *dev_priv)
7d708ee4 7634{
712bf364
VS		 7635 if (HAS_PCH_LPT(dev_priv))
7636 lpt_suspend_hw(dev_priv);
7d708ee4
ID		 7637}
7638
46f16e63 7639static void nop_init_clock_gating(struct drm_i915_private *dev_priv)
bb400da9
ID		 7640{
7641 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7642}
7643
7644/**
7645 * intel_init_clock_gating_hooks - setup the clock gating hooks
7646 * @dev_priv: device private
7647 *
7648 * Setup the hooks that configure which clocks of a given platform can be
7649 * gated and also apply various GT and display specific workarounds for these
7650 * platforms. Note that some GT specific workarounds are applied separately
7651 * when GPU contexts or batchbuffers start their execution.
7652 */
7653void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7654{
7655 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7656 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7657 else if (IS_KABYLAKE(dev_priv))
9498dba7 7658 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7659 else if (IS_BROXTON(dev_priv))
7660 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7661 else if (IS_BROADWELL(dev_priv))
7662 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7663 else if (IS_CHERRYVIEW(dev_priv))
7664 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7665 else if (IS_HASWELL(dev_priv))
7666 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7667 else if (IS_IVYBRIDGE(dev_priv))
7668 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7669 else if (IS_VALLEYVIEW(dev_priv))
7670 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7671 else if (IS_GEN6(dev_priv))
7672 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7673 else if (IS_GEN5(dev_priv))
7674 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7675 else if (IS_G4X(dev_priv))
7676 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7677 else if (IS_CRESTLINE(dev_priv))
7678 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7679 else if (IS_BROADWATER(dev_priv))
7680 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7681 else if (IS_GEN3(dev_priv))
7682 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7683 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7684 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7685 else if (IS_GEN2(dev_priv))
7686 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7687 else {
7688 MISSING_CASE(INTEL_DEVID(dev_priv));
7689 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7690 }
7691}
7692
1fa61106 7693/* Set up chip specific power management-related functions */
62d75df7 7694void intel_init_pm(struct drm_i915_private *dev_priv)
1fa61106 7695{
7ff0ebcc 7696 intel_fbc_init(dev_priv);
1fa61106 7697
c921aba8 7698 /* For cxsr */
9b1e14f4 7699 if (IS_PINEVIEW(dev_priv))
148ac1f3 7700 i915_pineview_get_mem_freq(dev_priv);
5db94019 7701 else if (IS_GEN5(dev_priv))
148ac1f3 7702 i915_ironlake_get_mem_freq(dev_priv);
c921aba8 7703
1fa61106 7704 /* For FIFO watermark updates */
62d75df7 7705 if (INTEL_GEN(dev_priv) >= 9) {
bb726519 7706 skl_setup_wm_latency(dev_priv);
e62929b3 7707 dev_priv->display.initial_watermarks = skl_initial_wm;
ccf010fb 7708 dev_priv->display.atomic_update_watermarks = skl_atomic_update_crtc_wm;
98d39494 7709 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7710 } else if (HAS_PCH_SPLIT(dev_priv)) {
bb726519 7711 ilk_setup_wm_latency(dev_priv);
53615a5e 7712
5db94019 7713 if ((IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[1] &&
bd602544 7714 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
5db94019 7715 (!IS_GEN5(dev_priv) && dev_priv->wm.pri_latency[0] &&
bd602544 7716 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7717 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7718 dev_priv->display.compute_intermediate_wm =
7719 ilk_compute_intermediate_wm;
7720 dev_priv->display.initial_watermarks =
7721 ilk_initial_watermarks;
7722 dev_priv->display.optimize_watermarks =
7723 ilk_optimize_watermarks;
bd602544
VS		 7724 } else {
7725 DRM_DEBUG_KMS("Failed to read display plane latency. "
7726 "Disable CxSR\n");
7727 }
920a14b2 7728 } else if (IS_CHERRYVIEW(dev_priv)) {
bb726519 7729 vlv_setup_wm_latency(dev_priv);
262cd2e1 7730 dev_priv->display.update_wm = vlv_update_wm;
11a914c2 7731 } else if (IS_VALLEYVIEW(dev_priv)) {
bb726519 7732 vlv_setup_wm_latency(dev_priv);
26e1fe4f 7733 dev_priv->display.update_wm = vlv_update_wm;
9b1e14f4 7734 } else if (IS_PINEVIEW(dev_priv)) {
50a0bc90 7735 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7736 dev_priv->is_ddr3,
7737 dev_priv->fsb_freq,
7738 dev_priv->mem_freq)) {
7739 DRM_INFO("failed to find known CxSR latency "
7740 "(found ddr%s fsb freq %d, mem freq %d), "
7741 "disabling CxSR\n",
7742 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7743 dev_priv->fsb_freq, dev_priv->mem_freq);
7744 /* Disable CxSR and never update its watermark again */
5209b1f4 7745 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7746 dev_priv->display.update_wm = NULL;
7747 } else
7748 dev_priv->display.update_wm = pineview_update_wm;
9beb5fea 7749 } else if (IS_G4X(dev_priv)) {
1fa61106 7750 dev_priv->display.update_wm = g4x_update_wm;
5db94019 7751 } else if (IS_GEN4(dev_priv)) {
1fa61106 7752 dev_priv->display.update_wm = i965_update_wm;
5db94019 7753 } else if (IS_GEN3(dev_priv)) {
1fa61106
ED		 7754 dev_priv->display.update_wm = i9xx_update_wm;
7755 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5db94019 7756 } else if (IS_GEN2(dev_priv)) {
62d75df7 7757 if (INTEL_INFO(dev_priv)->num_pipes == 1) {
feb56b93 7758 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7759 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7760 } else {
7761 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7762 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7763 }
feb56b93
DV		 7764 } else {
7765 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7766 }
7767}
7768
87660502
L		 7769static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7770{
7771 uint32_t flags =
7772 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7773
7774 switch (flags) {
7775 case GEN6_PCODE_SUCCESS:
7776 return 0;
7777 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7778 case GEN6_PCODE_ILLEGAL_CMD:
7779 return -ENXIO;
7780 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7781 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7782 return -EOVERFLOW;
7783 case GEN6_PCODE_TIMEOUT:
7784 return -ETIMEDOUT;
7785 default:
7786 MISSING_CASE(flags)
7787 return 0;
7788 }
7789}
7790
7791static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7792{
7793 uint32_t flags =
7794 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7795
7796 switch (flags) {
7797 case GEN6_PCODE_SUCCESS:
7798 return 0;
7799 case GEN6_PCODE_ILLEGAL_CMD:
7800 return -ENXIO;
7801 case GEN7_PCODE_TIMEOUT:
7802 return -ETIMEDOUT;
7803 case GEN7_PCODE_ILLEGAL_DATA:
7804 return -EINVAL;
7805 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7806 return -EOVERFLOW;
7807 default:
7808 MISSING_CASE(flags);
7809 return 0;
7810 }
7811}
7812
151a49d0 7813int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7814{
87660502
L		 7815 int status;
7816
4fc688ce 7817 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7818
3f5582dd
CW		 7819 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7820 * use te fw I915_READ variants to reduce the amount of work
7821 * required when reading/writing.
7822 */
7823
7824 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7825 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7826 return -EAGAIN;
7827 }
7828
3f5582dd
CW		 7829 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7830 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7831 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7832
3f5582dd
CW		 7833 if (intel_wait_for_register_fw(dev_priv,
7834 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7835 500)) {
42c0526c
BW		 7836 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7837 return -ETIMEDOUT;
7838 }
7839
3f5582dd
CW		 7840 *val = I915_READ_FW(GEN6_PCODE_DATA);
7841 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7842
87660502
L		 7843 if (INTEL_GEN(dev_priv) > 6)
7844 status = gen7_check_mailbox_status(dev_priv);
7845 else
7846 status = gen6_check_mailbox_status(dev_priv);
7847
7848 if (status) {
7849 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7850 status);
7851 return status;
7852 }
7853
42c0526c
BW		 7854 return 0;
7855}
7856
3f5582dd 7857int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7858 u32 mbox, u32 val)
42c0526c 7859{
87660502
L		 7860 int status;
7861
4fc688ce 7862 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7863
3f5582dd
CW		 7864 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7865 * use te fw I915_READ variants to reduce the amount of work
7866 * required when reading/writing.
7867 */
7868
7869 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7870 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7871 return -EAGAIN;
7872 }
7873
3f5582dd
CW		 7874 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7875 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7876
3f5582dd
CW		 7877 if (intel_wait_for_register_fw(dev_priv,
7878 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7879 500)) {
42c0526c
BW		 7880 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7881 return -ETIMEDOUT;
7882 }
7883
3f5582dd 7884 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7885
87660502
L		 7886 if (INTEL_GEN(dev_priv) > 6)
7887 status = gen7_check_mailbox_status(dev_priv);
7888 else
7889 status = gen6_check_mailbox_status(dev_priv);
7890
7891 if (status) {
7892 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7893 status);
7894 return status;
7895 }
7896
42c0526c
BW		 7897 return 0;
7898}
a0e4e199 7899
dd06f88c
VS		 7900static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7901{
c30fec65
VS		 7902 /*
7903 * N = val - 0xb7
7904 * Slow = Fast = GPLL ref * N
7905 */
7906 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7907}
7908
b55dd647 7909static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7910{
c30fec65 7911 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7912}
7913
b55dd647 7914static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7915{
c30fec65
VS		 7916 /*
7917 * N = val / 2
7918 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7919 */
7920 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7921}
7922
b55dd647 7923static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7924{
1c14762d 7925 /* CHV needs even values */
c30fec65 7926 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7927}
7928
616bc820 7929int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7930{
2d1fe073 7931 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7932 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7933 GEN9_FREQ_SCALER);
2d1fe073 7934 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7935 return chv_gpu_freq(dev_priv, val);
2d1fe073 7936 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7937 return byt_gpu_freq(dev_priv, val);
7938 else
7939 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7940}
7941
616bc820
VS		 7942int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7943{
2d1fe073 7944 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7945 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7946 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7947 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7948 return chv_freq_opcode(dev_priv, val);
2d1fe073 7949 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7950 return byt_freq_opcode(dev_priv, val);
7951 else
500a3d2e 7952 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7953}
22b1b2f8 7954
6ad790c0
CW		 7955struct request_boost {
7956 struct work_struct work;
eed29a5b 7957 struct drm_i915_gem_request *req;
6ad790c0
CW		 7958};
7959
7960static void __intel_rps_boost_work(struct work_struct *work)
7961{
7962 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 7963 struct drm_i915_gem_request *req = boost->req;
6ad790c0 7964
f69a02c9 7965 if (!i915_gem_request_completed(req))
c033666a 7966 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 7967
e8a261ea 7968 i915_gem_request_put(req);
6ad790c0
CW		 7969 kfree(boost);
7970}
7971
91d14251 7972void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 7973{
7974 struct request_boost *boost;
7975
91d14251 7976 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 7977 return;
7978
f69a02c9 7979 if (i915_gem_request_completed(req))
e61b9958
CW		 7980 return;
7981
6ad790c0
CW		 7982 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
7983 if (boost == NULL)
7984 return;
7985
e8a261ea 7986 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 7987
7988 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 7989 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 7990}
7991
f742a552 7992void intel_pm_setup(struct drm_device *dev)
907b28c5 7993{
fac5e23e 7994 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 7995
f742a552 7996 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 7997 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 7998
54b4f68f
CW		 7999 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8000 __intel_autoenable_gt_powersave);
1854d5ca 8001 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8002
33688d95 8003 dev_priv->pm.suspended = false;
1f814dac 8004 atomic_set(&dev_priv->pm.wakeref_count, 0);
907b28c5 8005}
Ubuntu Artful kernel mirror