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drm/i915: Tidy the macro casting by using an inline function
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
f85da868 461 unsigned int max_hdisplay, max_vdisplay;
85208be0 462
29ebf90f
CW		 463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 465 return;
29ebf90f 466 }
85208be0 467
29ebf90f
CW		 468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 471 return;
29ebf90f 472 }
85208be0
ED		 473
474 /*
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
482 */
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 486 if (crtc) {
29ebf90f
CW		 487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 489 goto out_disable;
490 }
491 crtc = tmp_crtc;
492 }
493 }
494
495 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 498 goto out_disable;
499 }
500
501 intel_crtc = to_intel_crtc(crtc);
502 fb = crtc->fb;
503 intel_fb = to_intel_framebuffer(fb);
504 obj = intel_fb->obj;
505
8a5729a3
DL		 506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 510 goto out_disable;
85208be0 511 }
8a5729a3 512 if (!i915_enable_fbc) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 515 goto out_disable;
516 }
85208be0
ED		 517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
521 "disabling\n");
85208be0
ED		 522 goto out_disable;
523 }
f85da868
PZ		 524
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 max_hdisplay = 4096;
527 max_vdisplay = 2048;
528 } else {
529 max_hdisplay = 2048;
530 max_vdisplay = 1536;
531 }
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
891348b2
RV		 538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 542 goto out_disable;
543 }
544
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
547 */
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 552 goto out_disable;
553 }
554
555 /* If the kernel debugger is active, always disable compression */
556 if (in_dbg_master())
557 goto out_disable;
558
11be49eb 559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 562 goto out_disable;
563 }
564
85208be0
ED		 565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
569 */
5c3fe8b0
BW		 570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
85208be0
ED		 573 return;
574
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
581 *
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
590 * callback.
591 *
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
598 */
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
601 }
602
603 intel_enable_fbc(crtc, 500);
29ebf90f 604 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 605 return;
606
607out_disable:
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
612 }
11be49eb 613 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 614}
615
c921aba8
DV		 616static void i915_pineview_get_mem_freq(struct drm_device *dev)
617{
618 drm_i915_private_t *dev_priv = dev->dev_private;
619 u32 tmp;
620
621 tmp = I915_READ(CLKCFG);
622
623 switch (tmp & CLKCFG_FSB_MASK) {
624 case CLKCFG_FSB_533:
625 dev_priv->fsb_freq = 533; /* 133*4 */
626 break;
627 case CLKCFG_FSB_800:
628 dev_priv->fsb_freq = 800; /* 200*4 */
629 break;
630 case CLKCFG_FSB_667:
631 dev_priv->fsb_freq = 667; /* 167*4 */
632 break;
633 case CLKCFG_FSB_400:
634 dev_priv->fsb_freq = 400; /* 100*4 */
635 break;
636 }
637
638 switch (tmp & CLKCFG_MEM_MASK) {
639 case CLKCFG_MEM_533:
640 dev_priv->mem_freq = 533;
641 break;
642 case CLKCFG_MEM_667:
643 dev_priv->mem_freq = 667;
644 break;
645 case CLKCFG_MEM_800:
646 dev_priv->mem_freq = 800;
647 break;
648 }
649
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
653}
654
655static void i915_ironlake_get_mem_freq(struct drm_device *dev)
656{
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 u16 ddrpll, csipll;
659
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
662
663 switch (ddrpll & 0xff) {
664 case 0xc:
665 dev_priv->mem_freq = 800;
666 break;
667 case 0x10:
668 dev_priv->mem_freq = 1066;
669 break;
670 case 0x14:
671 dev_priv->mem_freq = 1333;
672 break;
673 case 0x18:
674 dev_priv->mem_freq = 1600;
675 break;
676 default:
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
678 ddrpll & 0xff);
679 dev_priv->mem_freq = 0;
680 break;
681 }
682
20e4d407 683 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 684
685 switch (csipll & 0x3ff) {
686 case 0x00c:
687 dev_priv->fsb_freq = 3200;
688 break;
689 case 0x00e:
690 dev_priv->fsb_freq = 3733;
691 break;
692 case 0x010:
693 dev_priv->fsb_freq = 4266;
694 break;
695 case 0x012:
696 dev_priv->fsb_freq = 4800;
697 break;
698 case 0x014:
699 dev_priv->fsb_freq = 5333;
700 break;
701 case 0x016:
702 dev_priv->fsb_freq = 5866;
703 break;
704 case 0x018:
705 dev_priv->fsb_freq = 6400;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
709 csipll & 0x3ff);
710 dev_priv->fsb_freq = 0;
711 break;
712 }
713
714 if (dev_priv->fsb_freq == 3200) {
20e4d407 715 dev_priv->ips.c_m = 0;
c921aba8 716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 717 dev_priv->ips.c_m = 1;
c921aba8 718 } else {
20e4d407 719 dev_priv->ips.c_m = 2;
c921aba8
DV		 720 }
721}
722
b445e3b0
ED		 723static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
729
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
735
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
741
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
747
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
753
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
759};
760
63c62275 761static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 762 int is_ddr3,
763 int fsb,
764 int mem)
765{
766 const struct cxsr_latency *latency;
767 int i;
768
769 if (fsb == 0 || mem == 0)
770 return NULL;
771
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
777 return latency;
778 }
779
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
781
782 return NULL;
783}
784
1fa61106 785static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
791}
792
793/*
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
796 * - chipset
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
803 *
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
806 */
807static const int latency_ns = 5000;
808
1fa61106 809static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
813 int size;
814
815 size = dsparb & 0x7f;
816 if (plane)
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x1ff;
832 if (plane)
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
838
839 return size;
840}
841
1fa61106 842static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 843{
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
846 int size;
847
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
850
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 plane ? "B" : "A",
853 size);
854
855 return size;
856}
857
1fa61106 858static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
866
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
869
870 return size;
871}
872
873/* Pineview has different values for various configs */
874static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
883 PINEVIEW_MAX_WM,
884 PINEVIEW_DFT_HPLLOFF_WM,
885 PINEVIEW_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
894};
895static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params g4x_wm_info = {
903 G4X_FIFO_SIZE,
904 G4X_MAX_WM,
905 G4X_MAX_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params g4x_cursor_wm_info = {
910 I965_CURSOR_FIFO,
911 I965_CURSOR_MAX_WM,
912 I965_CURSOR_DFT_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
918 VALLEYVIEW_MAX_WM,
919 VALLEYVIEW_MAX_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params valleyview_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 VALLEYVIEW_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 G4X_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i965_cursor_wm_info = {
931 I965_CURSOR_FIFO,
932 I965_CURSOR_MAX_WM,
933 I965_CURSOR_DFT_WM,
934 2,
935 I915_FIFO_LINE_SIZE,
936};
937static const struct intel_watermark_params i945_wm_info = {
938 I945_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
944static const struct intel_watermark_params i915_wm_info = {
945 I915_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I915_FIFO_LINE_SIZE
950};
951static const struct intel_watermark_params i855_wm_info = {
952 I855GM_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params i830_wm_info = {
959 I830_FIFO_SIZE,
960 I915_MAX_WM,
961 1,
962 2,
963 I830_FIFO_LINE_SIZE
964};
965
966static const struct intel_watermark_params ironlake_display_wm_info = {
967 ILK_DISPLAY_FIFO,
968 ILK_DISPLAY_MAXWM,
969 ILK_DISPLAY_DFTWM,
970 2,
971 ILK_FIFO_LINE_SIZE
972};
973static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 ILK_CURSOR_FIFO,
975 ILK_CURSOR_MAXWM,
976 ILK_CURSOR_DFTWM,
977 2,
978 ILK_FIFO_LINE_SIZE
979};
980static const struct intel_watermark_params ironlake_display_srwm_info = {
981 ILK_DISPLAY_SR_FIFO,
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
984 2,
985 ILK_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params ironlake_cursor_srwm_info = {
988 ILK_CURSOR_SR_FIFO,
989 ILK_CURSOR_MAX_SRWM,
990 ILK_CURSOR_DFT_SRWM,
991 2,
992 ILK_FIFO_LINE_SIZE
993};
994
995static const struct intel_watermark_params sandybridge_display_wm_info = {
996 SNB_DISPLAY_FIFO,
997 SNB_DISPLAY_MAXWM,
998 SNB_DISPLAY_DFTWM,
999 2,
1000 SNB_FIFO_LINE_SIZE
1001};
1002static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 SNB_CURSOR_FIFO,
1004 SNB_CURSOR_MAXWM,
1005 SNB_CURSOR_DFTWM,
1006 2,
1007 SNB_FIFO_LINE_SIZE
1008};
1009static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1013 2,
1014 SNB_FIFO_LINE_SIZE
1015};
1016static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017 SNB_CURSOR_SR_FIFO,
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1020 2,
1021 SNB_FIFO_LINE_SIZE
1022};
1023
1024
1025/**
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1031 *
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1036 *
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1042 */
1043static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1045 int fifo_size,
1046 int pixel_size,
1047 unsigned long latency_ns)
1048{
1049 long entries_required, wm_size;
1050
1051 /*
1052 * Note: we need to make sure we don't overflow for various clock &
1053 * latency values.
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1056 */
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058 1000;
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1070 if (wm_size <= 0)
1071 wm_size = wm->default_wm;
1072 return wm_size;
1073}
1074
1075static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076{
1077 struct drm_crtc *crtc, *enabled = NULL;
1078
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1080 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1081 if (enabled)
1082 return NULL;
1083 enabled = crtc;
1084 }
1085 }
1086
1087 return enabled;
1088}
1089
1fa61106 1090static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1091{
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc;
1094 const struct cxsr_latency *latency;
1095 u32 reg;
1096 unsigned long wm;
1097
1098 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099 dev_priv->fsb_freq, dev_priv->mem_freq);
1100 if (!latency) {
1101 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102 pineview_disable_cxsr(dev);
1103 return;
1104 }
1105
1106 crtc = single_enabled_crtc(dev);
1107 if (crtc) {
1108 int clock = crtc->mode.clock;
1109 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
1180 htotal = crtc->mode.htotal;
1181 hdisplay = crtc->mode.hdisplay;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 /* Use the small buffer method to calculate plane watermark */
1186 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1188 if (tlb_miss > 0)
1189 entries += tlb_miss;
1190 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191 *plane_wm = entries + display->guard_size;
1192 if (*plane_wm > (int)display->max_wm)
1193 *plane_wm = display->max_wm;
1194
1195 /* Use the large buffer method to calculate cursor watermark */
1196 line_time_us = ((htotal * 1000) / clock);
1197 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198 entries = line_count * 64 * pixel_size;
1199 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1200 if (tlb_miss > 0)
1201 entries += tlb_miss;
1202 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203 *cursor_wm = entries + cursor->guard_size;
1204 if (*cursor_wm > (int)cursor->max_wm)
1205 *cursor_wm = (int)cursor->max_wm;
1206
1207 return true;
1208}
1209
1210/*
1211 * Check the wm result.
1212 *
1213 * If any calculated watermark values is larger than the maximum value that
1214 * can be programmed into the associated watermark register, that watermark
1215 * must be disabled.
1216 */
1217static bool g4x_check_srwm(struct drm_device *dev,
1218 int display_wm, int cursor_wm,
1219 const struct intel_watermark_params *display,
1220 const struct intel_watermark_params *cursor)
1221{
1222 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223 display_wm, cursor_wm);
1224
1225 if (display_wm > display->max_wm) {
1226 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227 display_wm, display->max_wm);
1228 return false;
1229 }
1230
1231 if (cursor_wm > cursor->max_wm) {
1232 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233 cursor_wm, cursor->max_wm);
1234 return false;
1235 }
1236
1237 if (!(display_wm || cursor_wm)) {
1238 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1239 return false;
1240 }
1241
1242 return true;
1243}
1244
1245static bool g4x_compute_srwm(struct drm_device *dev,
1246 int plane,
1247 int latency_ns,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor,
1250 int *display_wm, int *cursor_wm)
1251{
1252 struct drm_crtc *crtc;
1253 int hdisplay, htotal, pixel_size, clock;
1254 unsigned long line_time_us;
1255 int line_count, line_size;
1256 int small, large;
1257 int entries;
1258
1259 if (!latency_ns) {
1260 *display_wm = *cursor_wm = 0;
1261 return false;
1262 }
1263
1264 crtc = intel_get_crtc_for_plane(dev, plane);
1265 hdisplay = crtc->mode.hdisplay;
1266 htotal = crtc->mode.htotal;
1267 clock = crtc->mode.clock;
1268 pixel_size = crtc->fb->bits_per_pixel / 8;
1269
1270 line_time_us = (htotal * 1000) / clock;
1271 line_count = (latency_ns / line_time_us + 1000) / 1000;
1272 line_size = hdisplay * pixel_size;
1273
1274 /* Use the minimum of the small and large buffer method for primary */
1275 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276 large = line_count * line_size;
1277
1278 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279 *display_wm = entries + display->guard_size;
1280
1281 /* calculate the self-refresh watermark for display cursor */
1282 entries = line_count * pixel_size * 64;
1283 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284 *cursor_wm = entries + cursor->guard_size;
1285
1286 return g4x_check_srwm(dev,
1287 *display_wm, *cursor_wm,
1288 display, cursor);
1289}
1290
1291static bool vlv_compute_drain_latency(struct drm_device *dev,
1292 int plane,
1293 int *plane_prec_mult,
1294 int *plane_dl,
1295 int *cursor_prec_mult,
1296 int *cursor_dl)
1297{
1298 struct drm_crtc *crtc;
1299 int clock, pixel_size;
1300 int entries;
1301
1302 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1303 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1304 return false;
1305
1306 clock = crtc->mode.clock; /* VESA DOT Clock */
1307 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1308
1309 entries = (clock / 1000) * pixel_size;
1310 *plane_prec_mult = (entries > 256) ?
1311 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1313 pixel_size);
1314
1315 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1316 *cursor_prec_mult = (entries > 256) ?
1317 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1319
1320 return true;
1321}
1322
1323/*
1324 * Update drain latency registers of memory arbiter
1325 *
1326 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327 * to be programmed. Each plane has a drain latency multiplier and a drain
1328 * latency value.
1329 */
1330
1331static void vlv_update_drain_latency(struct drm_device *dev)
1332{
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1337 either 16 or 32 */
1338
1339 /* For plane A, Cursor A */
1340 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341 &cursor_prec_mult, &cursora_dl)) {
1342 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1346
1347 I915_WRITE(VLV_DDL1, cursora_prec |
1348 (cursora_dl << DDL_CURSORA_SHIFT) |
1349 planea_prec | planea_dl);
1350 }
1351
1352 /* For plane B, Cursor B */
1353 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354 &cursor_prec_mult, &cursorb_dl)) {
1355 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1359
1360 I915_WRITE(VLV_DDL2, cursorb_prec |
1361 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362 planeb_prec | planeb_dl);
1363 }
1364}
1365
1366#define single_plane_enabled(mask) is_power_of_2(mask)
1367
1fa61106 1368static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1369{
1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
af6c4575 1374 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1375 unsigned int enabled = 0;
1376
1377 vlv_update_drain_latency(dev);
1378
51cea1f4 1379 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
51cea1f4 1383 enabled |= 1 << PIPE_A;
b445e3b0 1384
51cea1f4 1385 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
51cea1f4 1389 enabled |= 1 << PIPE_B;
b445e3b0 1390
b445e3b0
ED		 1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1393 sr_latency_ns,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
af6c4575
CW		 1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 2*sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
52bd02d8 1401 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1403 } else {
b445e3b0
ED		 1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1406 plane_sr = cursor_sr = 0;
1407 }
b445e3b0
ED		 1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
8c919b28 1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 I915_WRITE(DSPFW3,
8c919b28
CW		 1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1425}
1426
1fa61106 1427static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1428{
1429 static const int sr_latency_ns = 12000;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432 int plane_sr, cursor_sr;
1433 unsigned int enabled = 0;
1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1436 &g4x_wm_info, latency_ns,
1437 &g4x_cursor_wm_info, latency_ns,
1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &g4x_wm_info,
1451 &g4x_cursor_wm_info,
52bd02d8 1452 &plane_sr, &cursor_sr)) {
b445e3b0 1453 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1454 } else {
b445e3b0
ED		 1455 I915_WRITE(FW_BLC_SELF,
1456 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1457 plane_sr = cursor_sr = 0;
1458 }
b445e3b0
ED		 1459
1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461 planea_wm, cursora_wm,
1462 planeb_wm, cursorb_wm,
1463 plane_sr, cursor_sr);
1464
1465 I915_WRITE(DSPFW1,
1466 (plane_sr << DSPFW_SR_SHIFT) |
1467 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1469 planea_wm);
1470 I915_WRITE(DSPFW2,
8c919b28 1471 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1472 (cursora_wm << DSPFW_CURSORA_SHIFT));
1473 /* HPLL off in SR has some issues on G4x... disable it */
1474 I915_WRITE(DSPFW3,
8c919b28 1475 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1476 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1477}
1478
1fa61106 1479static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct drm_crtc *crtc;
1483 int srwm = 1;
1484 int cursor_sr = 16;
1485
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1488 if (crtc) {
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
1491 int clock = crtc->mode.clock;
1492 int htotal = crtc->mode.htotal;
1493 int hdisplay = crtc->mode.hdisplay;
1494 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495 unsigned long line_time_us;
1496 int entries;
1497
1498 line_time_us = ((htotal * 1000) / clock);
1499
1500 /* Use ns/us then divide to preserve precision */
1501 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502 pixel_size * hdisplay;
1503 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504 srwm = I965_FIFO_SIZE - entries;
1505 if (srwm < 0)
1506 srwm = 1;
1507 srwm &= 0x1ff;
1508 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1509 entries, srwm);
1510
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512 pixel_size * 64;
1513 entries = DIV_ROUND_UP(entries,
1514 i965_cursor_wm_info.cacheline_size);
1515 cursor_sr = i965_cursor_wm_info.fifo_size -
1516 (entries + i965_cursor_wm_info.guard_size);
1517
1518 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519 cursor_sr = i965_cursor_wm_info.max_wm;
1520
1521 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522 "cursor %d\n", srwm, cursor_sr);
1523
1524 if (IS_CRESTLINE(dev))
1525 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1526 } else {
1527 /* Turn off self refresh if both pipes are enabled */
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1530 & ~FW_BLC_SELF_EN);
1531 }
1532
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534 srwm);
1535
1536 /* 965 has limitations... */
1537 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538 (8 << 16) | (8 << 8) | (8 << 0));
1539 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540 /* update cursor SR watermark */
1541 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1542}
1543
1fa61106 1544static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1545{
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
1553 struct drm_crtc *crtc, *enabled = NULL;
1554
1555 if (IS_I945GM(dev))
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev))
1558 wm_info = &i915_wm_info;
1559 else
1560 wm_info = &i855_wm_info;
1561
1562 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1564 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1565 int cpp = crtc->fb->bits_per_pixel / 8;
1566 if (IS_GEN2(dev))
1567 cpp = 4;
1568
b445e3b0 1569 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
b445e3b0
ED		 1571 latency_ns);
1572 enabled = crtc;
1573 } else
1574 planea_wm = fifo_size - wm_info->guard_size;
1575
1576 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1578 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1579 int cpp = crtc->fb->bits_per_pixel / 8;
1580 if (IS_GEN2(dev))
1581 cpp = 4;
1582
b445e3b0 1583 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1584 wm_info, fifo_size, cpp,
b445e3b0
ED		 1585 latency_ns);
1586 if (enabled == NULL)
1587 enabled = crtc;
1588 else
1589 enabled = NULL;
1590 } else
1591 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
1595 /*
1596 * Overlay gets an aggressive default since video jitter is bad.
1597 */
1598 cwm = 2;
1599
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
1601 if (IS_I945G(dev) || IS_I945GM(dev))
1602 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603 else if (IS_I915GM(dev))
1604 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 int clock = enabled->mode.clock;
1611 int htotal = enabled->mode.htotal;
1612 int hdisplay = enabled->mode.hdisplay;
1613 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614 unsigned long line_time_us;
1615 int entries;
1616
1617 line_time_us = (htotal * 1000) / clock;
1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621 pixel_size * hdisplay;
1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
1628 if (IS_I945G(dev) || IS_I945GM(dev))
1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631 else if (IS_I915GM(dev))
1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
1648 if (HAS_FW_BLC(dev)) {
1649 if (enabled) {
1650 if (IS_I945G(dev) || IS_I945GM(dev))
1651 I915_WRITE(FW_BLC_SELF,
1652 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653 else if (IS_I915GM(dev))
1654 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655 DRM_DEBUG_KMS("memory self refresh enabled\n");
1656 } else
1657 DRM_DEBUG_KMS("memory self refresh disabled\n");
1658 }
1659}
1660
1fa61106 1661static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
1665 uint32_t fwater_lo;
1666 int planea_wm;
1667
1668 crtc = single_enabled_crtc(dev);
1669 if (crtc == NULL)
1670 return;
1671
1672 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1674 4, latency_ns);
b445e3b0
ED		 1675 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676 fwater_lo |= (3<<8) | planea_wm;
1677
1678 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1679
1680 I915_WRITE(FW_BLC, fwater_lo);
1681}
1682
1683#define ILK_LP0_PLANE_LATENCY 700
1684#define ILK_LP0_CURSOR_LATENCY 1300
1685
1686/*
1687 * Check the wm result.
1688 *
1689 * If any calculated watermark values is larger than the maximum value that
1690 * can be programmed into the associated watermark register, that watermark
1691 * must be disabled.
1692 */
1693static bool ironlake_check_srwm(struct drm_device *dev, int level,
1694 int fbc_wm, int display_wm, int cursor_wm,
1695 const struct intel_watermark_params *display,
1696 const struct intel_watermark_params *cursor)
1697{
1698 struct drm_i915_private *dev_priv = dev->dev_private;
1699
1700 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1701 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1702
1703 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1704 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1705 fbc_wm, SNB_FBC_MAX_SRWM, level);
1706
1707 /* fbc has it's own way to disable FBC WM */
1708 I915_WRITE(DISP_ARB_CTL,
1709 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1710 return false;
615aaa5f
VS		 1711 } else if (INTEL_INFO(dev)->gen >= 6) {
1712 /* enable FBC WM (except on ILK, where it must remain off) */
1713 I915_WRITE(DISP_ARB_CTL,
1714 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1715 }
1716
1717 if (display_wm > display->max_wm) {
1718 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1719 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1720 return false;
1721 }
1722
1723 if (cursor_wm > cursor->max_wm) {
1724 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1725 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1726 return false;
1727 }
1728
1729 if (!(fbc_wm || display_wm || cursor_wm)) {
1730 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1731 return false;
1732 }
1733
1734 return true;
1735}
1736
1737/*
1738 * Compute watermark values of WM[1-3],
1739 */
1740static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1741 int latency_ns,
1742 const struct intel_watermark_params *display,
1743 const struct intel_watermark_params *cursor,
1744 int *fbc_wm, int *display_wm, int *cursor_wm)
1745{
1746 struct drm_crtc *crtc;
1747 unsigned long line_time_us;
1748 int hdisplay, htotal, pixel_size, clock;
1749 int line_count, line_size;
1750 int small, large;
1751 int entries;
1752
1753 if (!latency_ns) {
1754 *fbc_wm = *display_wm = *cursor_wm = 0;
1755 return false;
1756 }
1757
1758 crtc = intel_get_crtc_for_plane(dev, plane);
1759 hdisplay = crtc->mode.hdisplay;
1760 htotal = crtc->mode.htotal;
1761 clock = crtc->mode.clock;
1762 pixel_size = crtc->fb->bits_per_pixel / 8;
1763
1764 line_time_us = (htotal * 1000) / clock;
1765 line_count = (latency_ns / line_time_us + 1000) / 1000;
1766 line_size = hdisplay * pixel_size;
1767
1768 /* Use the minimum of the small and large buffer method for primary */
1769 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1770 large = line_count * line_size;
1771
1772 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1773 *display_wm = entries + display->guard_size;
1774
1775 /*
1776 * Spec says:
1777 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1778 */
1779 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1780
1781 /* calculate the self-refresh watermark for display cursor */
1782 entries = line_count * pixel_size * 64;
1783 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1784 *cursor_wm = entries + cursor->guard_size;
1785
1786 return ironlake_check_srwm(dev, level,
1787 *fbc_wm, *display_wm, *cursor_wm,
1788 display, cursor);
1789}
1790
1fa61106 1791static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1792{
1793 struct drm_i915_private *dev_priv = dev->dev_private;
1794 int fbc_wm, plane_wm, cursor_wm;
1795 unsigned int enabled;
1796
1797 enabled = 0;
51cea1f4 1798 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1799 &ironlake_display_wm_info,
1800 ILK_LP0_PLANE_LATENCY,
1801 &ironlake_cursor_wm_info,
1802 ILK_LP0_CURSOR_LATENCY,
1803 &plane_wm, &cursor_wm)) {
1804 I915_WRITE(WM0_PIPEA_ILK,
1805 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1806 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1807 " plane %d, " "cursor: %d\n",
1808 plane_wm, cursor_wm);
51cea1f4 1809 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1810 }
1811
51cea1f4 1812 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1813 &ironlake_display_wm_info,
1814 ILK_LP0_PLANE_LATENCY,
1815 &ironlake_cursor_wm_info,
1816 ILK_LP0_CURSOR_LATENCY,
1817 &plane_wm, &cursor_wm)) {
1818 I915_WRITE(WM0_PIPEB_ILK,
1819 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1820 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1821 " plane %d, cursor: %d\n",
1822 plane_wm, cursor_wm);
51cea1f4 1823 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1824 }
1825
1826 /*
1827 * Calculate and update the self-refresh watermark only when one
1828 * display plane is used.
1829 */
1830 I915_WRITE(WM3_LP_ILK, 0);
1831 I915_WRITE(WM2_LP_ILK, 0);
1832 I915_WRITE(WM1_LP_ILK, 0);
1833
1834 if (!single_plane_enabled(enabled))
1835 return;
1836 enabled = ffs(enabled) - 1;
1837
1838 /* WM1 */
1839 if (!ironlake_compute_srwm(dev, 1, enabled,
1840 ILK_READ_WM1_LATENCY() * 500,
1841 &ironlake_display_srwm_info,
1842 &ironlake_cursor_srwm_info,
1843 &fbc_wm, &plane_wm, &cursor_wm))
1844 return;
1845
1846 I915_WRITE(WM1_LP_ILK,
1847 WM1_LP_SR_EN |
1848 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1849 (fbc_wm << WM1_LP_FBC_SHIFT) |
1850 (plane_wm << WM1_LP_SR_SHIFT) |
1851 cursor_wm);
1852
1853 /* WM2 */
1854 if (!ironlake_compute_srwm(dev, 2, enabled,
1855 ILK_READ_WM2_LATENCY() * 500,
1856 &ironlake_display_srwm_info,
1857 &ironlake_cursor_srwm_info,
1858 &fbc_wm, &plane_wm, &cursor_wm))
1859 return;
1860
1861 I915_WRITE(WM2_LP_ILK,
1862 WM2_LP_EN |
1863 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1864 (fbc_wm << WM1_LP_FBC_SHIFT) |
1865 (plane_wm << WM1_LP_SR_SHIFT) |
1866 cursor_wm);
1867
1868 /*
1869 * WM3 is unsupported on ILK, probably because we don't have latency
1870 * data for that power state
1871 */
1872}
1873
1fa61106 1874static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1875{
1876 struct drm_i915_private *dev_priv = dev->dev_private;
1877 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1878 u32 val;
1879 int fbc_wm, plane_wm, cursor_wm;
1880 unsigned int enabled;
1881
1882 enabled = 0;
51cea1f4 1883 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1884 &sandybridge_display_wm_info, latency,
1885 &sandybridge_cursor_wm_info, latency,
1886 &plane_wm, &cursor_wm)) {
1887 val = I915_READ(WM0_PIPEA_ILK);
1888 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1889 I915_WRITE(WM0_PIPEA_ILK, val |
1890 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1891 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1892 " plane %d, " "cursor: %d\n",
1893 plane_wm, cursor_wm);
51cea1f4 1894 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1895 }
1896
51cea1f4 1897 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1898 &sandybridge_display_wm_info, latency,
1899 &sandybridge_cursor_wm_info, latency,
1900 &plane_wm, &cursor_wm)) {
1901 val = I915_READ(WM0_PIPEB_ILK);
1902 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1903 I915_WRITE(WM0_PIPEB_ILK, val |
1904 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1905 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1906 " plane %d, cursor: %d\n",
1907 plane_wm, cursor_wm);
51cea1f4 1908 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1909 }
1910
c43d0188
CW		 1911 /*
1912 * Calculate and update the self-refresh watermark only when one
1913 * display plane is used.
1914 *
1915 * SNB support 3 levels of watermark.
1916 *
1917 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1918 * and disabled in the descending order
1919 *
1920 */
1921 I915_WRITE(WM3_LP_ILK, 0);
1922 I915_WRITE(WM2_LP_ILK, 0);
1923 I915_WRITE(WM1_LP_ILK, 0);
1924
1925 if (!single_plane_enabled(enabled) ||
1926 dev_priv->sprite_scaling_enabled)
1927 return;
1928 enabled = ffs(enabled) - 1;
1929
1930 /* WM1 */
1931 if (!ironlake_compute_srwm(dev, 1, enabled,
1932 SNB_READ_WM1_LATENCY() * 500,
1933 &sandybridge_display_srwm_info,
1934 &sandybridge_cursor_srwm_info,
1935 &fbc_wm, &plane_wm, &cursor_wm))
1936 return;
1937
1938 I915_WRITE(WM1_LP_ILK,
1939 WM1_LP_SR_EN |
1940 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1941 (fbc_wm << WM1_LP_FBC_SHIFT) |
1942 (plane_wm << WM1_LP_SR_SHIFT) |
1943 cursor_wm);
1944
1945 /* WM2 */
1946 if (!ironlake_compute_srwm(dev, 2, enabled,
1947 SNB_READ_WM2_LATENCY() * 500,
1948 &sandybridge_display_srwm_info,
1949 &sandybridge_cursor_srwm_info,
1950 &fbc_wm, &plane_wm, &cursor_wm))
1951 return;
1952
1953 I915_WRITE(WM2_LP_ILK,
1954 WM2_LP_EN |
1955 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1956 (fbc_wm << WM1_LP_FBC_SHIFT) |
1957 (plane_wm << WM1_LP_SR_SHIFT) |
1958 cursor_wm);
1959
1960 /* WM3 */
1961 if (!ironlake_compute_srwm(dev, 3, enabled,
1962 SNB_READ_WM3_LATENCY() * 500,
1963 &sandybridge_display_srwm_info,
1964 &sandybridge_cursor_srwm_info,
1965 &fbc_wm, &plane_wm, &cursor_wm))
1966 return;
1967
1968 I915_WRITE(WM3_LP_ILK,
1969 WM3_LP_EN |
1970 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1971 (fbc_wm << WM1_LP_FBC_SHIFT) |
1972 (plane_wm << WM1_LP_SR_SHIFT) |
1973 cursor_wm);
1974}
1975
1976static void ivybridge_update_wm(struct drm_device *dev)
1977{
1978 struct drm_i915_private *dev_priv = dev->dev_private;
1979 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1980 u32 val;
1981 int fbc_wm, plane_wm, cursor_wm;
1982 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1983 unsigned int enabled;
1984
1985 enabled = 0;
51cea1f4 1986 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1987 &sandybridge_display_wm_info, latency,
1988 &sandybridge_cursor_wm_info, latency,
1989 &plane_wm, &cursor_wm)) {
1990 val = I915_READ(WM0_PIPEA_ILK);
1991 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1992 I915_WRITE(WM0_PIPEA_ILK, val |
1993 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1994 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1995 " plane %d, " "cursor: %d\n",
1996 plane_wm, cursor_wm);
51cea1f4 1997 enabled |= 1 << PIPE_A;
c43d0188
CW		 1998 }
1999
51cea1f4 2000 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 2001 &sandybridge_display_wm_info, latency,
2002 &sandybridge_cursor_wm_info, latency,
2003 &plane_wm, &cursor_wm)) {
2004 val = I915_READ(WM0_PIPEB_ILK);
2005 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2006 I915_WRITE(WM0_PIPEB_ILK, val |
2007 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2008 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2009 " plane %d, cursor: %d\n",
2010 plane_wm, cursor_wm);
51cea1f4 2011 enabled |= 1 << PIPE_B;
c43d0188
CW		 2012 }
2013
51cea1f4 2014 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2015 &sandybridge_display_wm_info, latency,
2016 &sandybridge_cursor_wm_info, latency,
2017 &plane_wm, &cursor_wm)) {
2018 val = I915_READ(WM0_PIPEC_IVB);
2019 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2020 I915_WRITE(WM0_PIPEC_IVB, val |
2021 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2022 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2023 " plane %d, cursor: %d\n",
2024 plane_wm, cursor_wm);
51cea1f4 2025 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2026 }
2027
2028 /*
2029 * Calculate and update the self-refresh watermark only when one
2030 * display plane is used.
2031 *
2032 * SNB support 3 levels of watermark.
2033 *
2034 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2035 * and disabled in the descending order
2036 *
2037 */
2038 I915_WRITE(WM3_LP_ILK, 0);
2039 I915_WRITE(WM2_LP_ILK, 0);
2040 I915_WRITE(WM1_LP_ILK, 0);
2041
2042 if (!single_plane_enabled(enabled) ||
2043 dev_priv->sprite_scaling_enabled)
2044 return;
2045 enabled = ffs(enabled) - 1;
2046
2047 /* WM1 */
2048 if (!ironlake_compute_srwm(dev, 1, enabled,
2049 SNB_READ_WM1_LATENCY() * 500,
2050 &sandybridge_display_srwm_info,
2051 &sandybridge_cursor_srwm_info,
2052 &fbc_wm, &plane_wm, &cursor_wm))
2053 return;
2054
2055 I915_WRITE(WM1_LP_ILK,
2056 WM1_LP_SR_EN |
2057 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2058 (fbc_wm << WM1_LP_FBC_SHIFT) |
2059 (plane_wm << WM1_LP_SR_SHIFT) |
2060 cursor_wm);
2061
2062 /* WM2 */
2063 if (!ironlake_compute_srwm(dev, 2, enabled,
2064 SNB_READ_WM2_LATENCY() * 500,
2065 &sandybridge_display_srwm_info,
2066 &sandybridge_cursor_srwm_info,
2067 &fbc_wm, &plane_wm, &cursor_wm))
2068 return;
2069
2070 I915_WRITE(WM2_LP_ILK,
2071 WM2_LP_EN |
2072 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2073 (fbc_wm << WM1_LP_FBC_SHIFT) |
2074 (plane_wm << WM1_LP_SR_SHIFT) |
2075 cursor_wm);
2076
c43d0188 2077 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 2078 if (!ironlake_compute_srwm(dev, 3, enabled,
2079 SNB_READ_WM3_LATENCY() * 500,
2080 &sandybridge_display_srwm_info,
2081 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2082 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2083 !ironlake_compute_srwm(dev, 3, enabled,
2084 2 * SNB_READ_WM3_LATENCY() * 500,
2085 &sandybridge_display_srwm_info,
2086 &sandybridge_cursor_srwm_info,
2087 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2088 return;
2089
2090 I915_WRITE(WM3_LP_ILK,
2091 WM3_LP_EN |
2092 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2093 (fbc_wm << WM1_LP_FBC_SHIFT) |
2094 (plane_wm << WM1_LP_SR_SHIFT) |
2095 cursor_wm);
2096}
2097
801bcfff
PZ		 2098static uint32_t hsw_wm_get_pixel_rate(struct drm_device *dev,
2099 struct drm_crtc *crtc)
2100{
2101 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2102 uint32_t pixel_rate, pfit_size;
2103
ff9a6750 2104 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2105
2106 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2107 * adjust the pixel_rate here. */
2108
2109 pfit_size = intel_crtc->config.pch_pfit.size;
2110 if (pfit_size) {
2111 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2112
2113 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2114 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2115 pfit_w = (pfit_size >> 16) & 0xFFFF;
2116 pfit_h = pfit_size & 0xFFFF;
2117 if (pipe_w < pfit_w)
2118 pipe_w = pfit_w;
2119 if (pipe_h < pfit_h)
2120 pipe_h = pfit_h;
2121
2122 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2123 pfit_w * pfit_h);
2124 }
2125
2126 return pixel_rate;
2127}
2128
2129static uint32_t hsw_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
2130 uint32_t latency)
2131{
2132 uint64_t ret;
2133
2134 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2135 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2136
2137 return ret;
2138}
2139
2140static uint32_t hsw_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
2141 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2142 uint32_t latency)
2143{
2144 uint32_t ret;
2145
2146 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2147 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2148 ret = DIV_ROUND_UP(ret, 64) + 2;
2149 return ret;
2150}
2151
cca32e9a
PZ		 2152static uint32_t hsw_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
2153 uint8_t bytes_per_pixel)
2154{
2155 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2156}
2157
801bcfff
PZ		 2158struct hsw_pipe_wm_parameters {
2159 bool active;
2160 bool sprite_enabled;
2161 uint8_t pri_bytes_per_pixel;
2162 uint8_t spr_bytes_per_pixel;
2163 uint8_t cur_bytes_per_pixel;
2164 uint32_t pri_horiz_pixels;
2165 uint32_t spr_horiz_pixels;
2166 uint32_t cur_horiz_pixels;
2167 uint32_t pipe_htotal;
2168 uint32_t pixel_rate;
2169};
2170
cca32e9a
PZ		 2171struct hsw_wm_maximums {
2172 uint16_t pri;
2173 uint16_t spr;
2174 uint16_t cur;
2175 uint16_t fbc;
2176};
2177
2178struct hsw_lp_wm_result {
2179 bool enable;
2180 bool fbc_enable;
2181 uint32_t pri_val;
2182 uint32_t spr_val;
2183 uint32_t cur_val;
2184 uint32_t fbc_val;
2185};
2186
801bcfff
PZ		 2187struct hsw_wm_values {
2188 uint32_t wm_pipe[3];
2189 uint32_t wm_lp[3];
2190 uint32_t wm_lp_spr[3];
2191 uint32_t wm_linetime[3];
cca32e9a 2192 bool enable_fbc_wm;
801bcfff
PZ		 2193};
2194
2195enum hsw_data_buf_partitioning {
2196 HSW_DATA_BUF_PART_1_2,
2197 HSW_DATA_BUF_PART_5_6,
2198};
2199
cca32e9a
PZ		 2200/* For both WM_PIPE and WM_LP. */
2201static uint32_t hsw_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
2202 uint32_t mem_value,
2203 bool is_lp)
801bcfff 2204{
cca32e9a
PZ		 2205 uint32_t method1, method2;
2206
801bcfff
PZ		 2207 /* TODO: for now, assume the primary plane is always enabled. */
2208 if (!params->active)
2209 return 0;
2210
cca32e9a
PZ		 2211 method1 = hsw_wm_method1(params->pixel_rate,
2212 params->pri_bytes_per_pixel,
2213 mem_value);
2214
2215 if (!is_lp)
2216 return method1;
2217
2218 method2 = hsw_wm_method2(params->pixel_rate,
2219 params->pipe_htotal,
2220 params->pri_horiz_pixels,
2221 params->pri_bytes_per_pixel,
2222 mem_value);
2223
2224 return min(method1, method2);
801bcfff
PZ		 2225}
2226
2227/* For both WM_PIPE and WM_LP. */
2228static uint32_t hsw_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
2229 uint32_t mem_value)
2230{
2231 uint32_t method1, method2;
2232
2233 if (!params->active || !params->sprite_enabled)
2234 return 0;
2235
2236 method1 = hsw_wm_method1(params->pixel_rate,
2237 params->spr_bytes_per_pixel,
2238 mem_value);
2239 method2 = hsw_wm_method2(params->pixel_rate,
2240 params->pipe_htotal,
2241 params->spr_horiz_pixels,
2242 params->spr_bytes_per_pixel,
2243 mem_value);
2244 return min(method1, method2);
2245}
2246
2247/* For both WM_PIPE and WM_LP. */
2248static uint32_t hsw_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
2249 uint32_t mem_value)
2250{
2251 if (!params->active)
2252 return 0;
2253
2254 return hsw_wm_method2(params->pixel_rate,
2255 params->pipe_htotal,
2256 params->cur_horiz_pixels,
2257 params->cur_bytes_per_pixel,
2258 mem_value);
2259}
2260
cca32e9a
PZ		 2261/* Only for WM_LP. */
2262static uint32_t hsw_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
2263 uint32_t pri_val,
2264 uint32_t mem_value)
2265{
2266 if (!params->active)
2267 return 0;
2268
2269 return hsw_wm_fbc(pri_val,
2270 params->pri_horiz_pixels,
2271 params->pri_bytes_per_pixel);
2272}
2273
2274static bool hsw_compute_lp_wm(uint32_t mem_value, struct hsw_wm_maximums *max,
2275 struct hsw_pipe_wm_parameters *params,
2276 struct hsw_lp_wm_result *result)
2277{
2278 enum pipe pipe;
2279 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2280
2281 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2282 struct hsw_pipe_wm_parameters *p = &params[pipe];
2283
2284 pri_val[pipe] = hsw_compute_pri_wm(p, mem_value, true);
2285 spr_val[pipe] = hsw_compute_spr_wm(p, mem_value);
2286 cur_val[pipe] = hsw_compute_cur_wm(p, mem_value);
2287 fbc_val[pipe] = hsw_compute_fbc_wm(p, pri_val[pipe], mem_value);
2288 }
2289
2290 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2291 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2292 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2293 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2294
2295 if (result->fbc_val > max->fbc) {
2296 result->fbc_enable = false;
2297 result->fbc_val = 0;
2298 } else {
2299 result->fbc_enable = true;
2300 }
2301
2302 result->enable = result->pri_val <= max->pri &&
2303 result->spr_val <= max->spr &&
2304 result->cur_val <= max->cur;
2305 return result->enable;
2306}
2307
801bcfff
PZ		 2308static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
2309 uint32_t mem_value, enum pipe pipe,
2310 struct hsw_pipe_wm_parameters *params)
2311{
2312 uint32_t pri_val, cur_val, spr_val;
2313
cca32e9a 2314 pri_val = hsw_compute_pri_wm(params, mem_value, false);
801bcfff
PZ		 2315 spr_val = hsw_compute_spr_wm(params, mem_value);
2316 cur_val = hsw_compute_cur_wm(params, mem_value);
2317
2318 WARN(pri_val > 127,
2319 "Primary WM error, mode not supported for pipe %c\n",
2320 pipe_name(pipe));
2321 WARN(spr_val > 127,
2322 "Sprite WM error, mode not supported for pipe %c\n",
2323 pipe_name(pipe));
2324 WARN(cur_val > 63,
2325 "Cursor WM error, mode not supported for pipe %c\n",
2326 pipe_name(pipe));
2327
2328 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2329 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2330 cur_val;
2331}
2332
2333static uint32_t
2334hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2335{
2336 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2337 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2338 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2339 u32 linetime, ips_linetime;
1f8eeabf 2340
801bcfff
PZ		 2341 if (!intel_crtc_active(crtc))
2342 return 0;
1011d8c4 2343
1f8eeabf
ED		 2344 /* The WM are computed with base on how long it takes to fill a single
2345 * row at the given clock rate, multiplied by 8.
2346 * */
85a02deb
PZ		 2347 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2348 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2349 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2350
801bcfff
PZ		 2351 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2352 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2353}
2354
801bcfff
PZ		 2355static void hsw_compute_wm_parameters(struct drm_device *dev,
2356 struct hsw_pipe_wm_parameters *params,
cca32e9a 2357 uint32_t *wm,
861f3389
PZ		 2358 struct hsw_wm_maximums *lp_max_1_2,
2359 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4
PZ		 2360{
2361 struct drm_i915_private *dev_priv = dev->dev_private;
2362 struct drm_crtc *crtc;
801bcfff
PZ		 2363 struct drm_plane *plane;
2364 uint64_t sskpd = I915_READ64(MCH_SSKPD);
1011d8c4 2365 enum pipe pipe;
cca32e9a 2366 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2367
801bcfff
PZ		 2368 if ((sskpd >> 56) & 0xFF)
2369 wm[0] = (sskpd >> 56) & 0xFF;
2370 else
2371 wm[0] = sskpd & 0xF;
2372 wm[1] = ((sskpd >> 4) & 0xFF) * 5;
2373 wm[2] = ((sskpd >> 12) & 0xFF) * 5;
2374 wm[3] = ((sskpd >> 20) & 0x1FF) * 5;
2375 wm[4] = ((sskpd >> 32) & 0x1FF) * 5;
2376
2377 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2378 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2379 struct hsw_pipe_wm_parameters *p;
2380
2381 pipe = intel_crtc->pipe;
2382 p = &params[pipe];
2383
2384 p->active = intel_crtc_active(crtc);
2385 if (!p->active)
2386 continue;
2387
cca32e9a
PZ		 2388 pipes_active++;
2389
801bcfff
PZ		 2390 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
2391 p->pixel_rate = hsw_wm_get_pixel_rate(dev, crtc);
2392 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2393 p->cur_bytes_per_pixel = 4;
2394 p->pri_horiz_pixels =
2395 intel_crtc->config.requested_mode.hdisplay;
2396 p->cur_horiz_pixels = 64;
2397 }
2398
2399 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2400 struct intel_plane *intel_plane = to_intel_plane(plane);
2401 struct hsw_pipe_wm_parameters *p;
2402
2403 pipe = intel_plane->pipe;
2404 p = &params[pipe];
2405
2406 p->sprite_enabled = intel_plane->wm.enable;
2407 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2408 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2409
2410 if (p->sprite_enabled)
2411 sprites_enabled++;
2412 }
2413
2414 if (pipes_active > 1) {
861f3389
PZ		 2415 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2416 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2417 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2418 } else {
2419 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2420 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2421 lp_max_1_2->spr = 384;
861f3389
PZ		 2422 lp_max_5_6->spr = 640;
2423 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2424 }
861f3389 2425 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2426}
2427
2428static void hsw_compute_wm_results(struct drm_device *dev,
2429 struct hsw_pipe_wm_parameters *params,
2430 uint32_t *wm,
cca32e9a 2431 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2432 struct hsw_wm_values *results)
2433{
2434 struct drm_i915_private *dev_priv = dev->dev_private;
2435 struct drm_crtc *crtc;
cca32e9a 2436 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2437 enum pipe pipe;
cca32e9a
PZ		 2438 int level, max_level, wm_lp;
2439
2440 for (level = 1; level <= 4; level++)
2441 if (!hsw_compute_lp_wm(wm[level], lp_maximums, params,
2442 &lp_results[level - 1]))
2443 break;
2444 max_level = level - 1;
2445
2446 /* The spec says it is preferred to disable FBC WMs instead of disabling
2447 * a WM level. */
2448 results->enable_fbc_wm = true;
2449 for (level = 1; level <= max_level; level++) {
2450 if (!lp_results[level - 1].fbc_enable) {
2451 results->enable_fbc_wm = false;
2452 break;
2453 }
2454 }
2455
2456 memset(results, 0, sizeof(*results));
2457 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2458 const struct hsw_lp_wm_result *r;
801bcfff 2459
cca32e9a
PZ		 2460 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2461 if (level > max_level)
2462 break;
2463
2464 r = &lp_results[level - 1];
2465 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2466 r->fbc_val,
2467 r->pri_val,
2468 r->cur_val);
2469 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2470 }
801bcfff
PZ		 2471
2472 for_each_pipe(pipe)
2473 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, wm[0],
2474 pipe,
2475 &params[pipe]);
1011d8c4
PZ		 2476
2477 for_each_pipe(pipe) {
2478 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2479 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2480 }
2481}
2482
861f3389
PZ		 2483/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2484 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2485static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2486 struct hsw_wm_values *r2)
861f3389
PZ		 2487{
2488 int i, val_r1 = 0, val_r2 = 0;
2489
2490 for (i = 0; i < 3; i++) {
2491 if (r1->wm_lp[i] & WM3_LP_EN)
2492 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2493 if (r2->wm_lp[i] & WM3_LP_EN)
2494 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2495 }
2496
2497 if (val_r1 == val_r2) {
2498 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2499 return r2;
2500 else
2501 return r1;
2502 } else if (val_r1 > val_r2) {
2503 return r1;
2504 } else {
2505 return r2;
2506 }
2507}
2508
801bcfff
PZ		 2509/*
2510 * The spec says we shouldn't write when we don't need, because every write
2511 * causes WMs to be re-evaluated, expending some power.
2512 */
2513static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2514 struct hsw_wm_values *results,
2515 enum hsw_data_buf_partitioning partitioning)
2516{
2517 struct hsw_wm_values previous;
2518 uint32_t val;
2519 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2520 bool prev_enable_fbc_wm;
801bcfff
PZ		 2521
2522 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2523 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2524 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2525 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2526 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2527 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2528 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2529 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2530 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2531 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2532 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2533 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2534
2535 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2536 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2537
cca32e9a
PZ		 2538 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2539
801bcfff
PZ		 2540 if (memcmp(results->wm_pipe, previous.wm_pipe,
2541 sizeof(results->wm_pipe)) == 0 &&
2542 memcmp(results->wm_lp, previous.wm_lp,
2543 sizeof(results->wm_lp)) == 0 &&
2544 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2545 sizeof(results->wm_lp_spr)) == 0 &&
2546 memcmp(results->wm_linetime, previous.wm_linetime,
2547 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2548 partitioning == prev_partitioning &&
2549 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2550 return;
2551
2552 if (previous.wm_lp[2] != 0)
2553 I915_WRITE(WM3_LP_ILK, 0);
2554 if (previous.wm_lp[1] != 0)
2555 I915_WRITE(WM2_LP_ILK, 0);
2556 if (previous.wm_lp[0] != 0)
2557 I915_WRITE(WM1_LP_ILK, 0);
2558
2559 if (previous.wm_pipe[0] != results->wm_pipe[0])
2560 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2561 if (previous.wm_pipe[1] != results->wm_pipe[1])
2562 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2563 if (previous.wm_pipe[2] != results->wm_pipe[2])
2564 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2565
2566 if (previous.wm_linetime[0] != results->wm_linetime[0])
2567 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2568 if (previous.wm_linetime[1] != results->wm_linetime[1])
2569 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2570 if (previous.wm_linetime[2] != results->wm_linetime[2])
2571 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2572
2573 if (prev_partitioning != partitioning) {
2574 val = I915_READ(WM_MISC);
2575 if (partitioning == HSW_DATA_BUF_PART_1_2)
2576 val &= ~WM_MISC_DATA_PARTITION_5_6;
2577 else
2578 val |= WM_MISC_DATA_PARTITION_5_6;
2579 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2580 }
2581
cca32e9a
PZ		 2582 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2583 val = I915_READ(DISP_ARB_CTL);
2584 if (results->enable_fbc_wm)
2585 val &= ~DISP_FBC_WM_DIS;
2586 else
2587 val |= DISP_FBC_WM_DIS;
2588 I915_WRITE(DISP_ARB_CTL, val);
2589 }
2590
801bcfff
PZ		 2591 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2592 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2593 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2594 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2595 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2596 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2597
2598 if (results->wm_lp[0] != 0)
2599 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2600 if (results->wm_lp[1] != 0)
2601 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2602 if (results->wm_lp[2] != 0)
2603 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2604}
2605
2606static void haswell_update_wm(struct drm_device *dev)
2607{
2608 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2609 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2610 struct hsw_pipe_wm_parameters params[3];
861f3389 2611 struct hsw_wm_values results_1_2, results_5_6, *best_results;
801bcfff 2612 uint32_t wm[5];
861f3389
PZ		 2613 enum hsw_data_buf_partitioning partitioning;
2614
2615 hsw_compute_wm_parameters(dev, params, wm, &lp_max_1_2, &lp_max_5_6);
2616
2617 hsw_compute_wm_results(dev, params, wm, &lp_max_1_2, &results_1_2);
2618 if (lp_max_1_2.pri != lp_max_5_6.pri) {
2619 hsw_compute_wm_results(dev, params, wm, &lp_max_5_6,
2620 &results_5_6);
2621 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2622 } else {
2623 best_results = &results_1_2;
2624 }
2625
2626 partitioning = (best_results == &results_1_2) ?
2627 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2628
861f3389 2629 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2630}
2631
526682e9
PZ		 2632static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2633 uint32_t sprite_width, int pixel_size,
2634 bool enable)
2635{
2636 struct drm_plane *plane;
2637
2638 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2639 struct intel_plane *intel_plane = to_intel_plane(plane);
2640
2641 if (intel_plane->pipe == pipe) {
2642 intel_plane->wm.enable = enable;
2643 intel_plane->wm.horiz_pixels = sprite_width + 1;
2644 intel_plane->wm.bytes_per_pixel = pixel_size;
2645 break;
2646 }
2647 }
2648
2649 haswell_update_wm(dev);
2650}
2651
b445e3b0
ED		 2652static bool
2653sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2654 uint32_t sprite_width, int pixel_size,
2655 const struct intel_watermark_params *display,
2656 int display_latency_ns, int *sprite_wm)
2657{
2658 struct drm_crtc *crtc;
2659 int clock;
2660 int entries, tlb_miss;
2661
2662 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2663 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2664 *sprite_wm = display->guard_size;
2665 return false;
2666 }
2667
2668 clock = crtc->mode.clock;
2669
2670 /* Use the small buffer method to calculate the sprite watermark */
2671 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2672 tlb_miss = display->fifo_size*display->cacheline_size -
2673 sprite_width * 8;
2674 if (tlb_miss > 0)
2675 entries += tlb_miss;
2676 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2677 *sprite_wm = entries + display->guard_size;
2678 if (*sprite_wm > (int)display->max_wm)
2679 *sprite_wm = display->max_wm;
2680
2681 return true;
2682}
2683
2684static bool
2685sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2686 uint32_t sprite_width, int pixel_size,
2687 const struct intel_watermark_params *display,
2688 int latency_ns, int *sprite_wm)
2689{
2690 struct drm_crtc *crtc;
2691 unsigned long line_time_us;
2692 int clock;
2693 int line_count, line_size;
2694 int small, large;
2695 int entries;
2696
2697 if (!latency_ns) {
2698 *sprite_wm = 0;
2699 return false;
2700 }
2701
2702 crtc = intel_get_crtc_for_plane(dev, plane);
2703 clock = crtc->mode.clock;
2704 if (!clock) {
2705 *sprite_wm = 0;
2706 return false;
2707 }
2708
2709 line_time_us = (sprite_width * 1000) / clock;
2710 if (!line_time_us) {
2711 *sprite_wm = 0;
2712 return false;
2713 }
2714
2715 line_count = (latency_ns / line_time_us + 1000) / 1000;
2716 line_size = sprite_width * pixel_size;
2717
2718 /* Use the minimum of the small and large buffer method for primary */
2719 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2720 large = line_count * line_size;
2721
2722 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2723 *sprite_wm = entries + display->guard_size;
2724
2725 return *sprite_wm > 0x3ff ? false : true;
2726}
2727
1fa61106 2728static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2729 uint32_t sprite_width, int pixel_size,
2730 bool enable)
b445e3b0
ED		 2731{
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2734 u32 val;
2735 int sprite_wm, reg;
2736 int ret;
2737
4c4ff43a
PZ		 2738 if (!enable)
2739 return;
2740
b445e3b0
ED		 2741 switch (pipe) {
2742 case 0:
2743 reg = WM0_PIPEA_ILK;
2744 break;
2745 case 1:
2746 reg = WM0_PIPEB_ILK;
2747 break;
2748 case 2:
2749 reg = WM0_PIPEC_IVB;
2750 break;
2751 default:
2752 return; /* bad pipe */
2753 }
2754
2755 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2756 &sandybridge_display_wm_info,
2757 latency, &sprite_wm);
2758 if (!ret) {
84f44ce7
VS		 2759 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2760 pipe_name(pipe));
b445e3b0
ED		 2761 return;
2762 }
2763
2764 val = I915_READ(reg);
2765 val &= ~WM0_PIPE_SPRITE_MASK;
2766 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2767 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2768
2769
2770 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2771 pixel_size,
2772 &sandybridge_display_srwm_info,
2773 SNB_READ_WM1_LATENCY() * 500,
2774 &sprite_wm);
2775 if (!ret) {
84f44ce7
VS		 2776 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2777 pipe_name(pipe));
b445e3b0
ED		 2778 return;
2779 }
2780 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2781
2782 /* Only IVB has two more LP watermarks for sprite */
2783 if (!IS_IVYBRIDGE(dev))
2784 return;
2785
2786 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2787 pixel_size,
2788 &sandybridge_display_srwm_info,
2789 SNB_READ_WM2_LATENCY() * 500,
2790 &sprite_wm);
2791 if (!ret) {
84f44ce7
VS		 2792 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2793 pipe_name(pipe));
b445e3b0
ED		 2794 return;
2795 }
2796 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2797
2798 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2799 pixel_size,
2800 &sandybridge_display_srwm_info,
2801 SNB_READ_WM3_LATENCY() * 500,
2802 &sprite_wm);
2803 if (!ret) {
84f44ce7
VS		 2804 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2805 pipe_name(pipe));
b445e3b0
ED		 2806 return;
2807 }
2808 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2809}
2810
2811/**
2812 * intel_update_watermarks - update FIFO watermark values based on current modes
2813 *
2814 * Calculate watermark values for the various WM regs based on current mode
2815 * and plane configuration.
2816 *
2817 * There are several cases to deal with here:
2818 * - normal (i.e. non-self-refresh)
2819 * - self-refresh (SR) mode
2820 * - lines are large relative to FIFO size (buffer can hold up to 2)
2821 * - lines are small relative to FIFO size (buffer can hold more than 2
2822 * lines), so need to account for TLB latency
2823 *
2824 * The normal calculation is:
2825 * watermark = dotclock * bytes per pixel * latency
2826 * where latency is platform & configuration dependent (we assume pessimal
2827 * values here).
2828 *
2829 * The SR calculation is:
2830 * watermark = (trunc(latency/line time)+1) * surface width *
2831 * bytes per pixel
2832 * where
2833 * line time = htotal / dotclock
2834 * surface width = hdisplay for normal plane and 64 for cursor
2835 * and latency is assumed to be high, as above.
2836 *
2837 * The final value programmed to the register should always be rounded up,
2838 * and include an extra 2 entries to account for clock crossings.
2839 *
2840 * We don't use the sprite, so we can ignore that. And on Crestline we have
2841 * to set the non-SR watermarks to 8.
2842 */
2843void intel_update_watermarks(struct drm_device *dev)
2844{
2845 struct drm_i915_private *dev_priv = dev->dev_private;
2846
2847 if (dev_priv->display.update_wm)
2848 dev_priv->display.update_wm(dev);
2849}
2850
2851void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a
PZ		 2852 uint32_t sprite_width, int pixel_size,
2853 bool enable)
b445e3b0
ED		 2854{
2855 struct drm_i915_private *dev_priv = dev->dev_private;
2856
2857 if (dev_priv->display.update_sprite_wm)
2858 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
4c4ff43a 2859 pixel_size, enable);
b445e3b0
ED		 2860}
2861
2b4e57bd
ED		 2862static struct drm_i915_gem_object *
2863intel_alloc_context_page(struct drm_device *dev)
2864{
2865 struct drm_i915_gem_object *ctx;
2866 int ret;
2867
2868 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2869
2870 ctx = i915_gem_alloc_object(dev, 4096);
2871 if (!ctx) {
2872 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2873 return NULL;
2874 }
2875
86a1ee26 2876 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2877 if (ret) {
2878 DRM_ERROR("failed to pin power context: %d\n", ret);
2879 goto err_unref;
2880 }
2881
2882 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2883 if (ret) {
2884 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2885 goto err_unpin;
2886 }
2887
2888 return ctx;
2889
2890err_unpin:
2891 i915_gem_object_unpin(ctx);
2892err_unref:
2893 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2894 return NULL;
2895}
2896
9270388e
DV		 2897/**
2898 * Lock protecting IPS related data structures
9270388e
DV		 2899 */
2900DEFINE_SPINLOCK(mchdev_lock);
2901
2902/* Global for IPS driver to get at the current i915 device. Protected by
2903 * mchdev_lock. */
2904static struct drm_i915_private *i915_mch_dev;
2905
2b4e57bd
ED		 2906bool ironlake_set_drps(struct drm_device *dev, u8 val)
2907{
2908 struct drm_i915_private *dev_priv = dev->dev_private;
2909 u16 rgvswctl;
2910
9270388e
DV		 2911 assert_spin_locked(&mchdev_lock);
2912
2b4e57bd
ED		 2913 rgvswctl = I915_READ16(MEMSWCTL);
2914 if (rgvswctl & MEMCTL_CMD_STS) {
2915 DRM_DEBUG("gpu busy, RCS change rejected\n");
2916 return false; /* still busy with another command */
2917 }
2918
2919 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2920 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2921 I915_WRITE16(MEMSWCTL, rgvswctl);
2922 POSTING_READ16(MEMSWCTL);
2923
2924 rgvswctl |= MEMCTL_CMD_STS;
2925 I915_WRITE16(MEMSWCTL, rgvswctl);
2926
2927 return true;
2928}
2929
8090c6b9 2930static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2931{
2932 struct drm_i915_private *dev_priv = dev->dev_private;
2933 u32 rgvmodectl = I915_READ(MEMMODECTL);
2934 u8 fmax, fmin, fstart, vstart;
2935
9270388e
DV		 2936 spin_lock_irq(&mchdev_lock);
2937
2b4e57bd
ED		 2938 /* Enable temp reporting */
2939 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2940 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2941
2942 /* 100ms RC evaluation intervals */
2943 I915_WRITE(RCUPEI, 100000);
2944 I915_WRITE(RCDNEI, 100000);
2945
2946 /* Set max/min thresholds to 90ms and 80ms respectively */
2947 I915_WRITE(RCBMAXAVG, 90000);
2948 I915_WRITE(RCBMINAVG, 80000);
2949
2950 I915_WRITE(MEMIHYST, 1);
2951
2952 /* Set up min, max, and cur for interrupt handling */
2953 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2954 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2955 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2956 MEMMODE_FSTART_SHIFT;
2957
2958 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2959 PXVFREQ_PX_SHIFT;
2960
20e4d407
DV		 2961 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2962 dev_priv->ips.fstart = fstart;
2b4e57bd 2963
20e4d407
DV		 2964 dev_priv->ips.max_delay = fstart;
2965 dev_priv->ips.min_delay = fmin;
2966 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2967
2968 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2969 fmax, fmin, fstart);
2970
2971 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2972
2973 /*
2974 * Interrupts will be enabled in ironlake_irq_postinstall
2975 */
2976
2977 I915_WRITE(VIDSTART, vstart);
2978 POSTING_READ(VIDSTART);
2979
2980 rgvmodectl |= MEMMODE_SWMODE_EN;
2981 I915_WRITE(MEMMODECTL, rgvmodectl);
2982
9270388e 2983 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2984 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2985 mdelay(1);
2b4e57bd
ED		 2986
2987 ironlake_set_drps(dev, fstart);
2988
20e4d407 2989 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2990 I915_READ(0x112e0);
20e4d407
DV		 2991 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2992 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2993 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2994
2995 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2996}
2997
8090c6b9 2998static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2999{
3000 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3001 u16 rgvswctl;
3002
3003 spin_lock_irq(&mchdev_lock);
3004
3005 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3006
3007 /* Ack interrupts, disable EFC interrupt */
3008 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3009 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3010 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3011 I915_WRITE(DEIIR, DE_PCU_EVENT);
3012 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3013
3014 /* Go back to the starting frequency */
20e4d407 3015 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3016 mdelay(1);
2b4e57bd
ED		 3017 rgvswctl |= MEMCTL_CMD_STS;
3018 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3019 mdelay(1);
2b4e57bd 3020
9270388e 3021 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3022}
3023
acbe9475
DV		 3024/* There's a funny hw issue where the hw returns all 0 when reading from
3025 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3026 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3027 * all limits and the gpu stuck at whatever frequency it is at atm).
3028 */
65bccb5c 3029static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3030{
7b9e0ae6 3031 u32 limits;
2b4e57bd 3032
7b9e0ae6 3033 limits = 0;
c6a828d3
DV		 3034
3035 if (*val >= dev_priv->rps.max_delay)
3036 *val = dev_priv->rps.max_delay;
3037 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3038
3039 /* Only set the down limit when we've reached the lowest level to avoid
3040 * getting more interrupts, otherwise leave this clear. This prevents a
3041 * race in the hw when coming out of rc6: There's a tiny window where
3042 * the hw runs at the minimal clock before selecting the desired
3043 * frequency, if the down threshold expires in that window we will not
3044 * receive a down interrupt. */
c6a828d3
DV		 3045 if (*val <= dev_priv->rps.min_delay) {
3046 *val = dev_priv->rps.min_delay;
3047 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3048 }
3049
3050 return limits;
3051}
3052
3053void gen6_set_rps(struct drm_device *dev, u8 val)
3054{
3055 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3056 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3057
4fc688ce 3058 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3059 WARN_ON(val > dev_priv->rps.max_delay);
3060 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3061
c6a828d3 3062 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3063 return;
3064
92bd1bf0
RV		 3065 if (IS_HASWELL(dev))
3066 I915_WRITE(GEN6_RPNSWREQ,
3067 HSW_FREQUENCY(val));
3068 else
3069 I915_WRITE(GEN6_RPNSWREQ,
3070 GEN6_FREQUENCY(val) |
3071 GEN6_OFFSET(0) |
3072 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3073
3074 /* Make sure we continue to get interrupts
3075 * until we hit the minimum or maximum frequencies.
3076 */
3077 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3078
d5570a72
BW		 3079 POSTING_READ(GEN6_RPNSWREQ);
3080
c6a828d3 3081 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3082
3083 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3084}
3085
80814ae4
VS		 3086/*
3087 * Wait until the previous freq change has completed,
3088 * or the timeout elapsed, and then update our notion
3089 * of the current GPU frequency.
3090 */
3091static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3092{
80814ae4
VS		 3093 u32 pval;
3094
3095 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3096
e8474409
VS		 3097 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3098 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3099
3100 pval >>= 8;
3101
3102 if (pval != dev_priv->rps.cur_delay)
3103 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3104 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3105 dev_priv->rps.cur_delay,
3106 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3107
3108 dev_priv->rps.cur_delay = pval;
3109}
3110
0a073b84
JB		 3111void valleyview_set_rps(struct drm_device *dev, u8 val)
3112{
3113 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3114
3115 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3116
3117 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3118 WARN_ON(val > dev_priv->rps.max_delay);
3119 WARN_ON(val < dev_priv->rps.min_delay);
3120
80814ae4
VS		 3121 vlv_update_rps_cur_delay(dev_priv);
3122
73008b98 3123 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3124 vlv_gpu_freq(dev_priv->mem_freq,
3125 dev_priv->rps.cur_delay),
73008b98
VS		 3126 dev_priv->rps.cur_delay,
3127 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3128
3129 if (val == dev_priv->rps.cur_delay)
3130 return;
3131
ae99258f 3132 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3133
80814ae4 3134 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3135
3136 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3137}
3138
44fc7d5c 3139static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3140{
3141 struct drm_i915_private *dev_priv = dev->dev_private;
3142
2b4e57bd 3143 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3144 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3145 /* Complete PM interrupt masking here doesn't race with the rps work
3146 * item again unmasking PM interrupts because that is using a different
3147 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3148 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3149
59cdb63d 3150 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3151 dev_priv->rps.pm_iir = 0;
59cdb63d 3152 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3153
4848405c 3154 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3155}
3156
44fc7d5c 3157static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3158{
3159 struct drm_i915_private *dev_priv = dev->dev_private;
3160
3161 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3162 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3163
44fc7d5c
DV		 3164 gen6_disable_rps_interrupts(dev);
3165}
3166
3167static void valleyview_disable_rps(struct drm_device *dev)
3168{
3169 struct drm_i915_private *dev_priv = dev->dev_private;
3170
3171 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3172
44fc7d5c 3173 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3174
3175 if (dev_priv->vlv_pctx) {
3176 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3177 dev_priv->vlv_pctx = NULL;
3178 }
d20d4f0c
JB		 3179}
3180
2b4e57bd
ED		 3181int intel_enable_rc6(const struct drm_device *dev)
3182{
eb4926e4
DL		 3183 /* No RC6 before Ironlake */
3184 if (INTEL_INFO(dev)->gen < 5)
3185 return 0;
3186
456470eb 3187 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3188 if (i915_enable_rc6 >= 0)
3189 return i915_enable_rc6;
3190
6567d748
CW		 3191 /* Disable RC6 on Ironlake */
3192 if (INTEL_INFO(dev)->gen == 5)
3193 return 0;
2b4e57bd 3194
456470eb
DV		 3195 if (IS_HASWELL(dev)) {
3196 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3197 return INTEL_RC6_ENABLE;
456470eb 3198 }
2b4e57bd 3199
456470eb 3200 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3201 if (INTEL_INFO(dev)->gen == 6) {
3202 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3203 return INTEL_RC6_ENABLE;
3204 }
456470eb 3205
2b4e57bd
ED		 3206 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3207 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3208}
3209
44fc7d5c
DV		 3210static void gen6_enable_rps_interrupts(struct drm_device *dev)
3211{
3212 struct drm_i915_private *dev_priv = dev->dev_private;
3213
3214 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3215 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3216 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3217 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3218 spin_unlock_irq(&dev_priv->irq_lock);
3219 /* unmask all PM interrupts */
3220 I915_WRITE(GEN6_PMINTRMSK, 0);
3221}
3222
79f5b2c7 3223static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3224{
79f5b2c7 3225 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3226 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3227 u32 rp_state_cap;
3228 u32 gt_perf_status;
31643d54 3229 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3230 u32 gtfifodbg;
2b4e57bd 3231 int rc6_mode;
42c0526c 3232 int i, ret;
2b4e57bd 3233
4fc688ce 3234 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3235
2b4e57bd
ED		 3236 /* Here begins a magic sequence of register writes to enable
3237 * auto-downclocking.
3238 *
3239 * Perhaps there might be some value in exposing these to
3240 * userspace...
3241 */
3242 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3243
3244 /* Clear the DBG now so we don't confuse earlier errors */
3245 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3246 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3247 I915_WRITE(GTFIFODBG, gtfifodbg);
3248 }
3249
3250 gen6_gt_force_wake_get(dev_priv);
3251
7b9e0ae6
CW		 3252 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3253 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3254
31c77388
BW		 3255 /* In units of 50MHz */
3256 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3257 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3258 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3259
2b4e57bd
ED		 3260 /* disable the counters and set deterministic thresholds */
3261 I915_WRITE(GEN6_RC_CONTROL, 0);
3262
3263 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3264 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3265 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3266 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3267 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3268
b4519513
CW		 3269 for_each_ring(ring, dev_priv, i)
3270 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3271
3272 I915_WRITE(GEN6_RC_SLEEP, 0);
3273 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3274 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3275 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3276 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3277
5a7dc92a 3278 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3279 rc6_mode = intel_enable_rc6(dev_priv->dev);
3280 if (rc6_mode & INTEL_RC6_ENABLE)
3281 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3282
5a7dc92a
ED		 3283 /* We don't use those on Haswell */
3284 if (!IS_HASWELL(dev)) {
3285 if (rc6_mode & INTEL_RC6p_ENABLE)
3286 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3287
5a7dc92a
ED		 3288 if (rc6_mode & INTEL_RC6pp_ENABLE)
3289 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3290 }
2b4e57bd
ED		 3291
3292 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3293 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3294 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3295 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3296
3297 I915_WRITE(GEN6_RC_CONTROL,
3298 rc6_mask |
3299 GEN6_RC_CTL_EI_MODE(1) |
3300 GEN6_RC_CTL_HW_ENABLE);
3301
92bd1bf0
RV		 3302 if (IS_HASWELL(dev)) {
3303 I915_WRITE(GEN6_RPNSWREQ,
3304 HSW_FREQUENCY(10));
3305 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3306 HSW_FREQUENCY(12));
3307 } else {
3308 I915_WRITE(GEN6_RPNSWREQ,
3309 GEN6_FREQUENCY(10) |
3310 GEN6_OFFSET(0) |
3311 GEN6_AGGRESSIVE_TURBO);
3312 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3313 GEN6_FREQUENCY(12));
3314 }
2b4e57bd
ED		 3315
3316 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3317 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3318 dev_priv->rps.max_delay << 24 |
3319 dev_priv->rps.min_delay << 16);
5a7dc92a 3320
1ee9ae32
DV		 3321 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3322 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3323 I915_WRITE(GEN6_RP_UP_EI, 66000);
3324 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3325
2b4e57bd
ED		 3326 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3327 I915_WRITE(GEN6_RP_CONTROL,
3328 GEN6_RP_MEDIA_TURBO |
89ba829e 3329 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3330 GEN6_RP_MEDIA_IS_GFX |
3331 GEN6_RP_ENABLE |
3332 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3333 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3334
42c0526c 3335 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3336 if (!ret) {
42c0526c
BW		 3337 pcu_mbox = 0;
3338 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3339 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3340 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3341 (dev_priv->rps.max_delay & 0xff) * 50,
3342 (pcu_mbox & 0xff) * 50);
31c77388 3343 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3344 }
3345 } else {
3346 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3347 }
3348
7b9e0ae6 3349 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3350
44fc7d5c 3351 gen6_enable_rps_interrupts(dev);
2b4e57bd 3352
31643d54
BW		 3353 rc6vids = 0;
3354 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3355 if (IS_GEN6(dev) && ret) {
3356 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3357 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3358 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3359 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3360 rc6vids &= 0xffff00;
3361 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3362 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3363 if (ret)
3364 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3365 }
3366
2b4e57bd 3367 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3368}
3369
79f5b2c7 3370static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3371{
79f5b2c7 3372 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3373 int min_freq = 15;
3ebecd07
CW		 3374 unsigned int gpu_freq;
3375 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3376 int scaling_factor = 180;
3377
4fc688ce 3378 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3379
2b4e57bd
ED		 3380 max_ia_freq = cpufreq_quick_get_max(0);
3381 /*
3382 * Default to measured freq if none found, PCU will ensure we don't go
3383 * over
3384 */
3385 if (!max_ia_freq)
3386 max_ia_freq = tsc_khz;
3387
3388 /* Convert from kHz to MHz */
3389 max_ia_freq /= 1000;
3390
3ebecd07
CW		 3391 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3392 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3393 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3394
2b4e57bd
ED		 3395 /*
3396 * For each potential GPU frequency, load a ring frequency we'd like
3397 * to use for memory access. We do this by specifying the IA frequency
3398 * the PCU should use as a reference to determine the ring frequency.
3399 */
c6a828d3 3400 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3401 gpu_freq--) {
c6a828d3 3402 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3403 unsigned int ia_freq = 0, ring_freq = 0;
3404
3405 if (IS_HASWELL(dev)) {
3406 ring_freq = (gpu_freq * 5 + 3) / 4;
3407 ring_freq = max(min_ring_freq, ring_freq);
3408 /* leave ia_freq as the default, chosen by cpufreq */
3409 } else {
3410 /* On older processors, there is no separate ring
3411 * clock domain, so in order to boost the bandwidth
3412 * of the ring, we need to upclock the CPU (ia_freq).
3413 *
3414 * For GPU frequencies less than 750MHz,
3415 * just use the lowest ring freq.
3416 */
3417 if (gpu_freq < min_freq)
3418 ia_freq = 800;
3419 else
3420 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3421 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3422 }
2b4e57bd 3423
42c0526c
BW		 3424 sandybridge_pcode_write(dev_priv,
3425 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3426 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3427 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3428 gpu_freq);
2b4e57bd 3429 }
2b4e57bd
ED		 3430}
3431
0a073b84
JB		 3432int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3433{
3434 u32 val, rp0;
3435
64936258 3436 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3437
3438 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3439 /* Clamp to max */
3440 rp0 = min_t(u32, rp0, 0xea);
3441
3442 return rp0;
3443}
3444
3445static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3446{
3447 u32 val, rpe;
3448
64936258 3449 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3450 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3451 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3452 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3453
3454 return rpe;
3455}
3456
3457int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3458{
64936258 3459 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3460}
3461
52ceb908
JB		 3462static void vlv_rps_timer_work(struct work_struct *work)
3463{
3464 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3465 rps.vlv_work.work);
3466
3467 /*
3468 * Timer fired, we must be idle. Drop to min voltage state.
3469 * Note: we use RPe here since it should match the
3470 * Vmin we were shooting for. That should give us better
3471 * perf when we come back out of RC6 than if we used the
3472 * min freq available.
3473 */
3474 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3475 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3476 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3477 mutex_unlock(&dev_priv->rps.hw_lock);
3478}
3479
c9cddffc
JB		 3480static void valleyview_setup_pctx(struct drm_device *dev)
3481{
3482 struct drm_i915_private *dev_priv = dev->dev_private;
3483 struct drm_i915_gem_object *pctx;
3484 unsigned long pctx_paddr;
3485 u32 pcbr;
3486 int pctx_size = 24*1024;
3487
3488 pcbr = I915_READ(VLV_PCBR);
3489 if (pcbr) {
3490 /* BIOS set it up already, grab the pre-alloc'd space */
3491 int pcbr_offset;
3492
3493 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3494 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3495 pcbr_offset,
190d6cd5 3496 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3497 pctx_size);
3498 goto out;
3499 }
3500
3501 /*
3502 * From the Gunit register HAS:
3503 * The Gfx driver is expected to program this register and ensure
3504 * proper allocation within Gfx stolen memory. For example, this
3505 * register should be programmed such than the PCBR range does not
3506 * overlap with other ranges, such as the frame buffer, protected
3507 * memory, or any other relevant ranges.
3508 */
3509 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3510 if (!pctx) {
3511 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3512 return;
3513 }
3514
3515 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3516 I915_WRITE(VLV_PCBR, pctx_paddr);
3517
3518out:
3519 dev_priv->vlv_pctx = pctx;
3520}
3521
0a073b84
JB		 3522static void valleyview_enable_rps(struct drm_device *dev)
3523{
3524 struct drm_i915_private *dev_priv = dev->dev_private;
3525 struct intel_ring_buffer *ring;
73008b98 3526 u32 gtfifodbg, val;
0a073b84
JB		 3527 int i;
3528
3529 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3530
3531 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3532 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3533 I915_WRITE(GTFIFODBG, gtfifodbg);
3534 }
3535
c9cddffc
JB		 3536 valleyview_setup_pctx(dev);
3537
0a073b84
JB		 3538 gen6_gt_force_wake_get(dev_priv);
3539
3540 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3541 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3542 I915_WRITE(GEN6_RP_UP_EI, 66000);
3543 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3544
3545 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3546
3547 I915_WRITE(GEN6_RP_CONTROL,
3548 GEN6_RP_MEDIA_TURBO |
3549 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3550 GEN6_RP_MEDIA_IS_GFX |
3551 GEN6_RP_ENABLE |
3552 GEN6_RP_UP_BUSY_AVG |
3553 GEN6_RP_DOWN_IDLE_CONT);
3554
3555 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3556 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3557 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3558
3559 for_each_ring(ring, dev_priv, i)
3560 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3561
3562 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3563
3564 /* allows RC6 residency counter to work */
3565 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3566 I915_WRITE(GEN6_RC_CONTROL,
3567 GEN7_RC_CTL_TO_MODE);
3568
64936258 3569 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3570 switch ((val >> 6) & 3) {
3571 case 0:
3572 case 1:
3573 dev_priv->mem_freq = 800;
3574 break;
3575 case 2:
3576 dev_priv->mem_freq = 1066;
3577 break;
3578 case 3:
3579 dev_priv->mem_freq = 1333;
3580 break;
3581 }
0a073b84
JB		 3582 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3583
3584 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3585 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3586
0a073b84 3587 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3588 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3589 vlv_gpu_freq(dev_priv->mem_freq,
3590 dev_priv->rps.cur_delay),
3591 dev_priv->rps.cur_delay);
0a073b84
JB		 3592
3593 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3594 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3595 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3596 vlv_gpu_freq(dev_priv->mem_freq,
3597 dev_priv->rps.max_delay),
3598 dev_priv->rps.max_delay);
0a073b84 3599
73008b98
VS		 3600 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3601 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3602 vlv_gpu_freq(dev_priv->mem_freq,
3603 dev_priv->rps.rpe_delay),
3604 dev_priv->rps.rpe_delay);
0a073b84 3605
73008b98
VS		 3606 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3607 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3608 vlv_gpu_freq(dev_priv->mem_freq,
3609 dev_priv->rps.min_delay),
3610 dev_priv->rps.min_delay);
0a073b84 3611
73008b98
VS		 3612 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3613 vlv_gpu_freq(dev_priv->mem_freq,
3614 dev_priv->rps.rpe_delay),
3615 dev_priv->rps.rpe_delay);
0a073b84 3616
52ceb908
JB		 3617 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3618
73008b98 3619 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3620
44fc7d5c 3621 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3622
3623 gen6_gt_force_wake_put(dev_priv);
3624}
3625
930ebb46 3626void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3627{
3628 struct drm_i915_private *dev_priv = dev->dev_private;
3629
3e373948
DV		 3630 if (dev_priv->ips.renderctx) {
3631 i915_gem_object_unpin(dev_priv->ips.renderctx);
3632 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3633 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3634 }
3635
3e373948
DV		 3636 if (dev_priv->ips.pwrctx) {
3637 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3638 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3639 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3640 }
3641}
3642
930ebb46 3643static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3644{
3645 struct drm_i915_private *dev_priv = dev->dev_private;
3646
3647 if (I915_READ(PWRCTXA)) {
3648 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3649 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3650 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3651 50);
3652
3653 I915_WRITE(PWRCTXA, 0);
3654 POSTING_READ(PWRCTXA);
3655
3656 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3657 POSTING_READ(RSTDBYCTL);
3658 }
2b4e57bd
ED		 3659}
3660
3661static int ironlake_setup_rc6(struct drm_device *dev)
3662{
3663 struct drm_i915_private *dev_priv = dev->dev_private;
3664
3e373948
DV		 3665 if (dev_priv->ips.renderctx == NULL)
3666 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3667 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3668 return -ENOMEM;
3669
3e373948
DV		 3670 if (dev_priv->ips.pwrctx == NULL)
3671 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3672 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3673 ironlake_teardown_rc6(dev);
3674 return -ENOMEM;
3675 }
3676
3677 return 0;
3678}
3679
930ebb46 3680static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3681{
3682 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3683 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3684 bool was_interruptible;
2b4e57bd
ED		 3685 int ret;
3686
3687 /* rc6 disabled by default due to repeated reports of hanging during
3688 * boot and resume.
3689 */
3690 if (!intel_enable_rc6(dev))
3691 return;
3692
79f5b2c7
DV		 3693 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3694
2b4e57bd 3695 ret = ironlake_setup_rc6(dev);
79f5b2c7 3696 if (ret)
2b4e57bd 3697 return;
2b4e57bd 3698
3e960501
CW		 3699 was_interruptible = dev_priv->mm.interruptible;
3700 dev_priv->mm.interruptible = false;
3701
2b4e57bd
ED		 3702 /*
3703 * GPU can automatically power down the render unit if given a page
3704 * to save state.
3705 */
6d90c952 3706 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3707 if (ret) {
3708 ironlake_teardown_rc6(dev);
3e960501 3709 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3710 return;
3711 }
3712
6d90c952
DV		 3713 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3714 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3715 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3716 MI_MM_SPACE_GTT |
3717 MI_SAVE_EXT_STATE_EN |
3718 MI_RESTORE_EXT_STATE_EN |
3719 MI_RESTORE_INHIBIT);
3720 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3721 intel_ring_emit(ring, MI_NOOP);
3722 intel_ring_emit(ring, MI_FLUSH);
3723 intel_ring_advance(ring);
2b4e57bd
ED		 3724
3725 /*
3726 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3727 * does an implicit flush, combined with MI_FLUSH above, it should be
3728 * safe to assume that renderctx is valid
3729 */
3e960501
CW		 3730 ret = intel_ring_idle(ring);
3731 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3732 if (ret) {
def27a58 3733 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3734 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3735 return;
3736 }
3737
f343c5f6 3738 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3739 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3740}
3741
dde18883
ED		 3742static unsigned long intel_pxfreq(u32 vidfreq)
3743{
3744 unsigned long freq;
3745 int div = (vidfreq & 0x3f0000) >> 16;
3746 int post = (vidfreq & 0x3000) >> 12;
3747 int pre = (vidfreq & 0x7);
3748
3749 if (!pre)
3750 return 0;
3751
3752 freq = ((div * 133333) / ((1<<post) * pre));
3753
3754 return freq;
3755}
3756
eb48eb00
DV		 3757static const struct cparams {
3758 u16 i;
3759 u16 t;
3760 u16 m;
3761 u16 c;
3762} cparams[] = {
3763 { 1, 1333, 301, 28664 },
3764 { 1, 1066, 294, 24460 },
3765 { 1, 800, 294, 25192 },
3766 { 0, 1333, 276, 27605 },
3767 { 0, 1066, 276, 27605 },
3768 { 0, 800, 231, 23784 },
3769};
3770
f531dcb2 3771static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3772{
3773 u64 total_count, diff, ret;
3774 u32 count1, count2, count3, m = 0, c = 0;
3775 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3776 int i;
3777
02d71956
DV		 3778 assert_spin_locked(&mchdev_lock);
3779
20e4d407 3780 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3781
3782 /* Prevent division-by-zero if we are asking too fast.
3783 * Also, we don't get interesting results if we are polling
3784 * faster than once in 10ms, so just return the saved value
3785 * in such cases.
3786 */
3787 if (diff1 <= 10)
20e4d407 3788 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3789
3790 count1 = I915_READ(DMIEC);
3791 count2 = I915_READ(DDREC);
3792 count3 = I915_READ(CSIEC);
3793
3794 total_count = count1 + count2 + count3;
3795
3796 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3797 if (total_count < dev_priv->ips.last_count1) {
3798 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3799 diff += total_count;
3800 } else {
20e4d407 3801 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3802 }
3803
3804 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3805 if (cparams[i].i == dev_priv->ips.c_m &&
3806 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3807 m = cparams[i].m;
3808 c = cparams[i].c;
3809 break;
3810 }
3811 }
3812
3813 diff = div_u64(diff, diff1);
3814 ret = ((m * diff) + c);
3815 ret = div_u64(ret, 10);
3816
20e4d407
DV		 3817 dev_priv->ips.last_count1 = total_count;
3818 dev_priv->ips.last_time1 = now;
eb48eb00 3819
20e4d407 3820 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3821
3822 return ret;
3823}
3824
f531dcb2
CW		 3825unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3826{
3827 unsigned long val;
3828
3829 if (dev_priv->info->gen != 5)
3830 return 0;
3831
3832 spin_lock_irq(&mchdev_lock);
3833
3834 val = __i915_chipset_val(dev_priv);
3835
3836 spin_unlock_irq(&mchdev_lock);
3837
3838 return val;
3839}
3840
eb48eb00
DV		 3841unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3842{
3843 unsigned long m, x, b;
3844 u32 tsfs;
3845
3846 tsfs = I915_READ(TSFS);
3847
3848 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3849 x = I915_READ8(TR1);
3850
3851 b = tsfs & TSFS_INTR_MASK;
3852
3853 return ((m * x) / 127) - b;
3854}
3855
3856static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3857{
3858 static const struct v_table {
3859 u16 vd; /* in .1 mil */
3860 u16 vm; /* in .1 mil */
3861 } v_table[] = {
3862 { 0, 0, },
3863 { 375, 0, },
3864 { 500, 0, },
3865 { 625, 0, },
3866 { 750, 0, },
3867 { 875, 0, },
3868 { 1000, 0, },
3869 { 1125, 0, },
3870 { 4125, 3000, },
3871 { 4125, 3000, },
3872 { 4125, 3000, },
3873 { 4125, 3000, },
3874 { 4125, 3000, },
3875 { 4125, 3000, },
3876 { 4125, 3000, },
3877 { 4125, 3000, },
3878 { 4125, 3000, },
3879 { 4125, 3000, },
3880 { 4125, 3000, },
3881 { 4125, 3000, },
3882 { 4125, 3000, },
3883 { 4125, 3000, },
3884 { 4125, 3000, },
3885 { 4125, 3000, },
3886 { 4125, 3000, },
3887 { 4125, 3000, },
3888 { 4125, 3000, },
3889 { 4125, 3000, },
3890 { 4125, 3000, },
3891 { 4125, 3000, },
3892 { 4125, 3000, },
3893 { 4125, 3000, },
3894 { 4250, 3125, },
3895 { 4375, 3250, },
3896 { 4500, 3375, },
3897 { 4625, 3500, },
3898 { 4750, 3625, },
3899 { 4875, 3750, },
3900 { 5000, 3875, },
3901 { 5125, 4000, },
3902 { 5250, 4125, },
3903 { 5375, 4250, },
3904 { 5500, 4375, },
3905 { 5625, 4500, },
3906 { 5750, 4625, },
3907 { 5875, 4750, },
3908 { 6000, 4875, },
3909 { 6125, 5000, },
3910 { 6250, 5125, },
3911 { 6375, 5250, },
3912 { 6500, 5375, },
3913 { 6625, 5500, },
3914 { 6750, 5625, },
3915 { 6875, 5750, },
3916 { 7000, 5875, },
3917 { 7125, 6000, },
3918 { 7250, 6125, },
3919 { 7375, 6250, },
3920 { 7500, 6375, },
3921 { 7625, 6500, },
3922 { 7750, 6625, },
3923 { 7875, 6750, },
3924 { 8000, 6875, },
3925 { 8125, 7000, },
3926 { 8250, 7125, },
3927 { 8375, 7250, },
3928 { 8500, 7375, },
3929 { 8625, 7500, },
3930 { 8750, 7625, },
3931 { 8875, 7750, },
3932 { 9000, 7875, },
3933 { 9125, 8000, },
3934 { 9250, 8125, },
3935 { 9375, 8250, },
3936 { 9500, 8375, },
3937 { 9625, 8500, },
3938 { 9750, 8625, },
3939 { 9875, 8750, },
3940 { 10000, 8875, },
3941 { 10125, 9000, },
3942 { 10250, 9125, },
3943 { 10375, 9250, },
3944 { 10500, 9375, },
3945 { 10625, 9500, },
3946 { 10750, 9625, },
3947 { 10875, 9750, },
3948 { 11000, 9875, },
3949 { 11125, 10000, },
3950 { 11250, 10125, },
3951 { 11375, 10250, },
3952 { 11500, 10375, },
3953 { 11625, 10500, },
3954 { 11750, 10625, },
3955 { 11875, 10750, },
3956 { 12000, 10875, },
3957 { 12125, 11000, },
3958 { 12250, 11125, },
3959 { 12375, 11250, },
3960 { 12500, 11375, },
3961 { 12625, 11500, },
3962 { 12750, 11625, },
3963 { 12875, 11750, },
3964 { 13000, 11875, },
3965 { 13125, 12000, },
3966 { 13250, 12125, },
3967 { 13375, 12250, },
3968 { 13500, 12375, },
3969 { 13625, 12500, },
3970 { 13750, 12625, },
3971 { 13875, 12750, },
3972 { 14000, 12875, },
3973 { 14125, 13000, },
3974 { 14250, 13125, },
3975 { 14375, 13250, },
3976 { 14500, 13375, },
3977 { 14625, 13500, },
3978 { 14750, 13625, },
3979 { 14875, 13750, },
3980 { 15000, 13875, },
3981 { 15125, 14000, },
3982 { 15250, 14125, },
3983 { 15375, 14250, },
3984 { 15500, 14375, },
3985 { 15625, 14500, },
3986 { 15750, 14625, },
3987 { 15875, 14750, },
3988 { 16000, 14875, },
3989 { 16125, 15000, },
3990 };
3991 if (dev_priv->info->is_mobile)
3992 return v_table[pxvid].vm;
3993 else
3994 return v_table[pxvid].vd;
3995}
3996
02d71956 3997static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3998{
3999 struct timespec now, diff1;
4000 u64 diff;
4001 unsigned long diffms;
4002 u32 count;
4003
02d71956 4004 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4005
4006 getrawmonotonic(&now);
20e4d407 4007 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4008
4009 /* Don't divide by 0 */
4010 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4011 if (!diffms)
4012 return;
4013
4014 count = I915_READ(GFXEC);
4015
20e4d407
DV		 4016 if (count < dev_priv->ips.last_count2) {
4017 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4018 diff += count;
4019 } else {
20e4d407 4020 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4021 }
4022
20e4d407
DV		 4023 dev_priv->ips.last_count2 = count;
4024 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4025
4026 /* More magic constants... */
4027 diff = diff * 1181;
4028 diff = div_u64(diff, diffms * 10);
20e4d407 4029 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4030}
4031
02d71956
DV		 4032void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4033{
4034 if (dev_priv->info->gen != 5)
4035 return;
4036
9270388e 4037 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4038
4039 __i915_update_gfx_val(dev_priv);
4040
9270388e 4041 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4042}
4043
f531dcb2 4044static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4045{
4046 unsigned long t, corr, state1, corr2, state2;
4047 u32 pxvid, ext_v;
4048
02d71956
DV		 4049 assert_spin_locked(&mchdev_lock);
4050
c6a828d3 4051 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4052 pxvid = (pxvid >> 24) & 0x7f;
4053 ext_v = pvid_to_extvid(dev_priv, pxvid);
4054
4055 state1 = ext_v;
4056
4057 t = i915_mch_val(dev_priv);
4058
4059 /* Revel in the empirically derived constants */
4060
4061 /* Correction factor in 1/100000 units */
4062 if (t > 80)
4063 corr = ((t * 2349) + 135940);
4064 else if (t >= 50)
4065 corr = ((t * 964) + 29317);
4066 else /* < 50 */
4067 corr = ((t * 301) + 1004);
4068
4069 corr = corr * ((150142 * state1) / 10000 - 78642);
4070 corr /= 100000;
20e4d407 4071 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4072
4073 state2 = (corr2 * state1) / 10000;
4074 state2 /= 100; /* convert to mW */
4075
02d71956 4076 __i915_update_gfx_val(dev_priv);
eb48eb00 4077
20e4d407 4078 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4079}
4080
f531dcb2
CW		 4081unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4082{
4083 unsigned long val;
4084
4085 if (dev_priv->info->gen != 5)
4086 return 0;
4087
4088 spin_lock_irq(&mchdev_lock);
4089
4090 val = __i915_gfx_val(dev_priv);
4091
4092 spin_unlock_irq(&mchdev_lock);
4093
4094 return val;
4095}
4096
eb48eb00
DV		 4097/**
4098 * i915_read_mch_val - return value for IPS use
4099 *
4100 * Calculate and return a value for the IPS driver to use when deciding whether
4101 * we have thermal and power headroom to increase CPU or GPU power budget.
4102 */
4103unsigned long i915_read_mch_val(void)
4104{
4105 struct drm_i915_private *dev_priv;
4106 unsigned long chipset_val, graphics_val, ret = 0;
4107
9270388e 4108 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4109 if (!i915_mch_dev)
4110 goto out_unlock;
4111 dev_priv = i915_mch_dev;
4112
f531dcb2
CW		 4113 chipset_val = __i915_chipset_val(dev_priv);
4114 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4115
4116 ret = chipset_val + graphics_val;
4117
4118out_unlock:
9270388e 4119 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4120
4121 return ret;
4122}
4123EXPORT_SYMBOL_GPL(i915_read_mch_val);
4124
4125/**
4126 * i915_gpu_raise - raise GPU frequency limit
4127 *
4128 * Raise the limit; IPS indicates we have thermal headroom.
4129 */
4130bool i915_gpu_raise(void)
4131{
4132 struct drm_i915_private *dev_priv;
4133 bool ret = true;
4134
9270388e 4135 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4136 if (!i915_mch_dev) {
4137 ret = false;
4138 goto out_unlock;
4139 }
4140 dev_priv = i915_mch_dev;
4141
20e4d407
DV		 4142 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4143 dev_priv->ips.max_delay--;
eb48eb00
DV		 4144
4145out_unlock:
9270388e 4146 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4147
4148 return ret;
4149}
4150EXPORT_SYMBOL_GPL(i915_gpu_raise);
4151
4152/**
4153 * i915_gpu_lower - lower GPU frequency limit
4154 *
4155 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4156 * frequency maximum.
4157 */
4158bool i915_gpu_lower(void)
4159{
4160 struct drm_i915_private *dev_priv;
4161 bool ret = true;
4162
9270388e 4163 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4164 if (!i915_mch_dev) {
4165 ret = false;
4166 goto out_unlock;
4167 }
4168 dev_priv = i915_mch_dev;
4169
20e4d407
DV		 4170 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4171 dev_priv->ips.max_delay++;
eb48eb00
DV		 4172
4173out_unlock:
9270388e 4174 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4175
4176 return ret;
4177}
4178EXPORT_SYMBOL_GPL(i915_gpu_lower);
4179
4180/**
4181 * i915_gpu_busy - indicate GPU business to IPS
4182 *
4183 * Tell the IPS driver whether or not the GPU is busy.
4184 */
4185bool i915_gpu_busy(void)
4186{
4187 struct drm_i915_private *dev_priv;
f047e395 4188 struct intel_ring_buffer *ring;
eb48eb00 4189 bool ret = false;
f047e395 4190 int i;
eb48eb00 4191
9270388e 4192 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4193 if (!i915_mch_dev)
4194 goto out_unlock;
4195 dev_priv = i915_mch_dev;
4196
f047e395
CW		 4197 for_each_ring(ring, dev_priv, i)
4198 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4199
4200out_unlock:
9270388e 4201 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4202
4203 return ret;
4204}
4205EXPORT_SYMBOL_GPL(i915_gpu_busy);
4206
4207/**
4208 * i915_gpu_turbo_disable - disable graphics turbo
4209 *
4210 * Disable graphics turbo by resetting the max frequency and setting the
4211 * current frequency to the default.
4212 */
4213bool i915_gpu_turbo_disable(void)
4214{
4215 struct drm_i915_private *dev_priv;
4216 bool ret = true;
4217
9270388e 4218 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4219 if (!i915_mch_dev) {
4220 ret = false;
4221 goto out_unlock;
4222 }
4223 dev_priv = i915_mch_dev;
4224
20e4d407 4225 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4226
20e4d407 4227 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4228 ret = false;
4229
4230out_unlock:
9270388e 4231 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4232
4233 return ret;
4234}
4235EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4236
4237/**
4238 * Tells the intel_ips driver that the i915 driver is now loaded, if
4239 * IPS got loaded first.
4240 *
4241 * This awkward dance is so that neither module has to depend on the
4242 * other in order for IPS to do the appropriate communication of
4243 * GPU turbo limits to i915.
4244 */
4245static void
4246ips_ping_for_i915_load(void)
4247{
4248 void (*link)(void);
4249
4250 link = symbol_get(ips_link_to_i915_driver);
4251 if (link) {
4252 link();
4253 symbol_put(ips_link_to_i915_driver);
4254 }
4255}
4256
4257void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4258{
02d71956
DV		 4259 /* We only register the i915 ips part with intel-ips once everything is
4260 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4261 spin_lock_irq(&mchdev_lock);
eb48eb00 4262 i915_mch_dev = dev_priv;
9270388e 4263 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4264
4265 ips_ping_for_i915_load();
4266}
4267
4268void intel_gpu_ips_teardown(void)
4269{
9270388e 4270 spin_lock_irq(&mchdev_lock);
eb48eb00 4271 i915_mch_dev = NULL;
9270388e 4272 spin_unlock_irq(&mchdev_lock);
eb48eb00 4273}
8090c6b9 4274static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4275{
4276 struct drm_i915_private *dev_priv = dev->dev_private;
4277 u32 lcfuse;
4278 u8 pxw[16];
4279 int i;
4280
4281 /* Disable to program */
4282 I915_WRITE(ECR, 0);
4283 POSTING_READ(ECR);
4284
4285 /* Program energy weights for various events */
4286 I915_WRITE(SDEW, 0x15040d00);
4287 I915_WRITE(CSIEW0, 0x007f0000);
4288 I915_WRITE(CSIEW1, 0x1e220004);
4289 I915_WRITE(CSIEW2, 0x04000004);
4290
4291 for (i = 0; i < 5; i++)
4292 I915_WRITE(PEW + (i * 4), 0);
4293 for (i = 0; i < 3; i++)
4294 I915_WRITE(DEW + (i * 4), 0);
4295
4296 /* Program P-state weights to account for frequency power adjustment */
4297 for (i = 0; i < 16; i++) {
4298 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4299 unsigned long freq = intel_pxfreq(pxvidfreq);
4300 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4301 PXVFREQ_PX_SHIFT;
4302 unsigned long val;
4303
4304 val = vid * vid;
4305 val *= (freq / 1000);
4306 val *= 255;
4307 val /= (127*127*900);
4308 if (val > 0xff)
4309 DRM_ERROR("bad pxval: %ld\n", val);
4310 pxw[i] = val;
4311 }
4312 /* Render standby states get 0 weight */
4313 pxw[14] = 0;
4314 pxw[15] = 0;
4315
4316 for (i = 0; i < 4; i++) {
4317 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4318 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4319 I915_WRITE(PXW + (i * 4), val);
4320 }
4321
4322 /* Adjust magic regs to magic values (more experimental results) */
4323 I915_WRITE(OGW0, 0);
4324 I915_WRITE(OGW1, 0);
4325 I915_WRITE(EG0, 0x00007f00);
4326 I915_WRITE(EG1, 0x0000000e);
4327 I915_WRITE(EG2, 0x000e0000);
4328 I915_WRITE(EG3, 0x68000300);
4329 I915_WRITE(EG4, 0x42000000);
4330 I915_WRITE(EG5, 0x00140031);
4331 I915_WRITE(EG6, 0);
4332 I915_WRITE(EG7, 0);
4333
4334 for (i = 0; i < 8; i++)
4335 I915_WRITE(PXWL + (i * 4), 0);
4336
4337 /* Enable PMON + select events */
4338 I915_WRITE(ECR, 0x80000019);
4339
4340 lcfuse = I915_READ(LCFUSE02);
4341
20e4d407 4342 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4343}
4344
8090c6b9
DV		 4345void intel_disable_gt_powersave(struct drm_device *dev)
4346{
1a01ab3b
JB		 4347 struct drm_i915_private *dev_priv = dev->dev_private;
4348
fd0c0642
DV		 4349 /* Interrupts should be disabled already to avoid re-arming. */
4350 WARN_ON(dev->irq_enabled);
4351
930ebb46 4352 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4353 ironlake_disable_drps(dev);
930ebb46 4354 ironlake_disable_rc6(dev);
0a073b84 4355 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4356 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4357 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4358 if (IS_VALLEYVIEW(dev))
4359 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4360 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4361 if (IS_VALLEYVIEW(dev))
4362 valleyview_disable_rps(dev);
4363 else
4364 gen6_disable_rps(dev);
4fc688ce 4365 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4366 }
8090c6b9
DV		 4367}
4368
1a01ab3b
JB		 4369static void intel_gen6_powersave_work(struct work_struct *work)
4370{
4371 struct drm_i915_private *dev_priv =
4372 container_of(work, struct drm_i915_private,
4373 rps.delayed_resume_work.work);
4374 struct drm_device *dev = dev_priv->dev;
4375
4fc688ce 4376 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4377
4378 if (IS_VALLEYVIEW(dev)) {
4379 valleyview_enable_rps(dev);
4380 } else {
4381 gen6_enable_rps(dev);
4382 gen6_update_ring_freq(dev);
4383 }
4fc688ce 4384 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4385}
4386
8090c6b9
DV		 4387void intel_enable_gt_powersave(struct drm_device *dev)
4388{
1a01ab3b
JB		 4389 struct drm_i915_private *dev_priv = dev->dev_private;
4390
8090c6b9
DV		 4391 if (IS_IRONLAKE_M(dev)) {
4392 ironlake_enable_drps(dev);
4393 ironlake_enable_rc6(dev);
4394 intel_init_emon(dev);
0a073b84 4395 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4396 /*
4397 * PCU communication is slow and this doesn't need to be
4398 * done at any specific time, so do this out of our fast path
4399 * to make resume and init faster.
4400 */
4401 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4402 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4403 }
4404}
4405
3107bd48
DV		 4406static void ibx_init_clock_gating(struct drm_device *dev)
4407{
4408 struct drm_i915_private *dev_priv = dev->dev_private;
4409
4410 /*
4411 * On Ibex Peak and Cougar Point, we need to disable clock
4412 * gating for the panel power sequencer or it will fail to
4413 * start up when no ports are active.
4414 */
4415 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4416}
4417
0e088b8f
VS		 4418static void g4x_disable_trickle_feed(struct drm_device *dev)
4419{
4420 struct drm_i915_private *dev_priv = dev->dev_private;
4421 int pipe;
4422
4423 for_each_pipe(pipe) {
4424 I915_WRITE(DSPCNTR(pipe),
4425 I915_READ(DSPCNTR(pipe)) |
4426 DISPPLANE_TRICKLE_FEED_DISABLE);
4427 intel_flush_display_plane(dev_priv, pipe);
4428 }
4429}
4430
1fa61106 4431static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4432{
4433 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4434 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4435
f1e8fa56
DL		 4436 /*
4437 * Required for FBC
4438 * WaFbcDisableDpfcClockGating:ilk
4439 */
4d47e4f5
DL		 4440 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4441 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4442 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4443
4444 I915_WRITE(PCH_3DCGDIS0,
4445 MARIUNIT_CLOCK_GATE_DISABLE |
4446 SVSMUNIT_CLOCK_GATE_DISABLE);
4447 I915_WRITE(PCH_3DCGDIS1,
4448 VFMUNIT_CLOCK_GATE_DISABLE);
4449
6f1d69b0
ED		 4450 /*
4451 * According to the spec the following bits should be set in
4452 * order to enable memory self-refresh
4453 * The bit 22/21 of 0x42004
4454 * The bit 5 of 0x42020
4455 * The bit 15 of 0x45000
4456 */
4457 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4458 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4459 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4460 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4461 I915_WRITE(DISP_ARB_CTL,
4462 (I915_READ(DISP_ARB_CTL) |
4463 DISP_FBC_WM_DIS));
4464 I915_WRITE(WM3_LP_ILK, 0);
4465 I915_WRITE(WM2_LP_ILK, 0);
4466 I915_WRITE(WM1_LP_ILK, 0);
4467
4468 /*
4469 * Based on the document from hardware guys the following bits
4470 * should be set unconditionally in order to enable FBC.
4471 * The bit 22 of 0x42000
4472 * The bit 22 of 0x42004
4473 * The bit 7,8,9 of 0x42020.
4474 */
4475 if (IS_IRONLAKE_M(dev)) {
4bb35334 4476 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4477 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4478 I915_READ(ILK_DISPLAY_CHICKEN1) |
4479 ILK_FBCQ_DIS);
4480 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4481 I915_READ(ILK_DISPLAY_CHICKEN2) |
4482 ILK_DPARB_GATE);
6f1d69b0
ED		 4483 }
4484
4d47e4f5
DL		 4485 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4486
6f1d69b0
ED		 4487 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4488 I915_READ(ILK_DISPLAY_CHICKEN2) |
4489 ILK_ELPIN_409_SELECT);
4490 I915_WRITE(_3D_CHICKEN2,
4491 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4492 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4493
ecdb4eb7 4494 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4495 I915_WRITE(CACHE_MODE_0,
4496 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4497
0e088b8f 4498 g4x_disable_trickle_feed(dev);
bdad2b2f 4499
3107bd48
DV		 4500 ibx_init_clock_gating(dev);
4501}
4502
4503static void cpt_init_clock_gating(struct drm_device *dev)
4504{
4505 struct drm_i915_private *dev_priv = dev->dev_private;
4506 int pipe;
3f704fa2 4507 uint32_t val;
3107bd48
DV		 4508
4509 /*
4510 * On Ibex Peak and Cougar Point, we need to disable clock
4511 * gating for the panel power sequencer or it will fail to
4512 * start up when no ports are active.
4513 */
4514 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4515 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4516 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4517 /* The below fixes the weird display corruption, a few pixels shifted
4518 * downward, on (only) LVDS of some HP laptops with IVY.
4519 */
3f704fa2 4520 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4521 val = I915_READ(TRANS_CHICKEN2(pipe));
4522 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4523 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4524 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4525 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4526 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4527 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4528 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4529 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4530 }
3107bd48
DV		 4531 /* WADP0ClockGatingDisable */
4532 for_each_pipe(pipe) {
4533 I915_WRITE(TRANS_CHICKEN1(pipe),
4534 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4535 }
6f1d69b0
ED		 4536}
4537
1d7aaa0c
DV		 4538static void gen6_check_mch_setup(struct drm_device *dev)
4539{
4540 struct drm_i915_private *dev_priv = dev->dev_private;
4541 uint32_t tmp;
4542
4543 tmp = I915_READ(MCH_SSKPD);
4544 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4545 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4546 DRM_INFO("This can cause pipe underruns and display issues.\n");
4547 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4548 }
4549}
4550
1fa61106 4551static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4552{
4553 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4554 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4555
231e54f6 4556 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4557
4558 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4559 I915_READ(ILK_DISPLAY_CHICKEN2) |
4560 ILK_ELPIN_409_SELECT);
4561
ecdb4eb7 4562 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4563 I915_WRITE(_3D_CHICKEN,
4564 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4565
ecdb4eb7 4566 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4567 if (IS_SNB_GT1(dev))
4568 I915_WRITE(GEN6_GT_MODE,
4569 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4570
6f1d69b0
ED		 4571 I915_WRITE(WM3_LP_ILK, 0);
4572 I915_WRITE(WM2_LP_ILK, 0);
4573 I915_WRITE(WM1_LP_ILK, 0);
4574
6f1d69b0 4575 I915_WRITE(CACHE_MODE_0,
50743298 4576 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4577
4578 I915_WRITE(GEN6_UCGCTL1,
4579 I915_READ(GEN6_UCGCTL1) |
4580 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4581 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4582
4583 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4584 * gating disable must be set. Failure to set it results in
4585 * flickering pixels due to Z write ordering failures after
4586 * some amount of runtime in the Mesa "fire" demo, and Unigine
4587 * Sanctuary and Tropics, and apparently anything else with
4588 * alpha test or pixel discard.
4589 *
4590 * According to the spec, bit 11 (RCCUNIT) must also be set,
4591 * but we didn't debug actual testcases to find it out.
0f846f81 4592 *
ecdb4eb7
DL		 4593 * Also apply WaDisableVDSUnitClockGating:snb and
4594 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4595 */
4596 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4597 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4598 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4599 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4600
4601 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4602 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4603 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4604
4605 /*
4606 * According to the spec the following bits should be
4607 * set in order to enable memory self-refresh and fbc:
4608 * The bit21 and bit22 of 0x42000
4609 * The bit21 and bit22 of 0x42004
4610 * The bit5 and bit7 of 0x42020
4611 * The bit14 of 0x70180
4612 * The bit14 of 0x71180
4bb35334
DL		 4613 *
4614 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4615 */
4616 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4617 I915_READ(ILK_DISPLAY_CHICKEN1) |
4618 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4619 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4620 I915_READ(ILK_DISPLAY_CHICKEN2) |
4621 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4622 I915_WRITE(ILK_DSPCLK_GATE_D,
4623 I915_READ(ILK_DSPCLK_GATE_D) |
4624 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4625 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4626
ecdb4eb7 4627 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4628 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4629 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4630
0e088b8f 4631 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4632
4633 /* The default value should be 0x200 according to docs, but the two
4634 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4635 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4636 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4637
4638 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4639
4640 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4641}
4642
4643static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4644{
4645 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4646
4647 reg &= ~GEN7_FF_SCHED_MASK;
4648 reg |= GEN7_FF_TS_SCHED_HW;
4649 reg |= GEN7_FF_VS_SCHED_HW;
4650 reg |= GEN7_FF_DS_SCHED_HW;
4651
41c0b3a8
BW		 4652 if (IS_HASWELL(dev_priv->dev))
4653 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4654
6f1d69b0
ED		 4655 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4656}
4657
17a303ec
PZ		 4658static void lpt_init_clock_gating(struct drm_device *dev)
4659{
4660 struct drm_i915_private *dev_priv = dev->dev_private;
4661
4662 /*
4663 * TODO: this bit should only be enabled when really needed, then
4664 * disabled when not needed anymore in order to save power.
4665 */
4666 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4667 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4668 I915_READ(SOUTH_DSPCLK_GATE_D) |
4669 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4670
4671 /* WADPOClockGatingDisable:hsw */
4672 I915_WRITE(_TRANSA_CHICKEN1,
4673 I915_READ(_TRANSA_CHICKEN1) |
4674 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4675}
4676
7d708ee4
ID		 4677static void lpt_suspend_hw(struct drm_device *dev)
4678{
4679 struct drm_i915_private *dev_priv = dev->dev_private;
4680
4681 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4682 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4683
4684 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4685 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4686 }
4687}
4688
cad2a2d7
ED		 4689static void haswell_init_clock_gating(struct drm_device *dev)
4690{
4691 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4692
4693 I915_WRITE(WM3_LP_ILK, 0);
4694 I915_WRITE(WM2_LP_ILK, 0);
4695 I915_WRITE(WM1_LP_ILK, 0);
4696
4697 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4698 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4699 */
4700 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4701
ecdb4eb7 4702 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4703 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4704 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4705
ecdb4eb7 4706 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4707 I915_WRITE(GEN7_L3CNTLREG1,
4708 GEN7_WA_FOR_GEN7_L3_CONTROL);
4709 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4710 GEN7_WA_L3_CHICKEN_MODE);
4711
ecdb4eb7 4712 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4713 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4714 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4715 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4716
0e088b8f 4717 g4x_disable_trickle_feed(dev);
cad2a2d7 4718
ecdb4eb7 4719 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4720 gen7_setup_fixed_func_scheduler(dev_priv);
4721
ecdb4eb7 4722 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4723 I915_WRITE(CACHE_MODE_1,
4724 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4725
ecdb4eb7 4726 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4727 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4728 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4729
ecdb4eb7 4730 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4731 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4732
90a88643
PZ		 4733 /* WaRsPkgCStateDisplayPMReq:hsw */
4734 I915_WRITE(CHICKEN_PAR1_1,
4735 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4736
17a303ec 4737 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4738}
4739
1fa61106 4740static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4741{
4742 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4743 uint32_t snpcr;
6f1d69b0 4744
6f1d69b0
ED		 4745 I915_WRITE(WM3_LP_ILK, 0);
4746 I915_WRITE(WM2_LP_ILK, 0);
4747 I915_WRITE(WM1_LP_ILK, 0);
4748
231e54f6 4749 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4750
ecdb4eb7 4751 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4752 I915_WRITE(_3D_CHICKEN3,
4753 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4754
ecdb4eb7 4755 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4756 I915_WRITE(IVB_CHICKEN3,
4757 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4758 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4759
ecdb4eb7 4760 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4761 if (IS_IVB_GT1(dev))
4762 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4763 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4764 else
4765 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4766 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4767
ecdb4eb7 4768 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4769 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4770 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4771
ecdb4eb7 4772 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4773 I915_WRITE(GEN7_L3CNTLREG1,
4774 GEN7_WA_FOR_GEN7_L3_CONTROL);
4775 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4776 GEN7_WA_L3_CHICKEN_MODE);
4777 if (IS_IVB_GT1(dev))
4778 I915_WRITE(GEN7_ROW_CHICKEN2,
4779 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4780 else
4781 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4782 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4783
6f1d69b0 4784
ecdb4eb7 4785 /* WaForceL3Serialization:ivb */
61939d97
JB		 4786 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4787 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4788
0f846f81
JB		 4789 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4790 * gating disable must be set. Failure to set it results in
4791 * flickering pixels due to Z write ordering failures after
4792 * some amount of runtime in the Mesa "fire" demo, and Unigine
4793 * Sanctuary and Tropics, and apparently anything else with
4794 * alpha test or pixel discard.
4795 *
4796 * According to the spec, bit 11 (RCCUNIT) must also be set,
4797 * but we didn't debug actual testcases to find it out.
4798 *
4799 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4800 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4801 */
4802 I915_WRITE(GEN6_UCGCTL2,
4803 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4804 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4805
ecdb4eb7 4806 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4807 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4808 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4809 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4810
0e088b8f 4811 g4x_disable_trickle_feed(dev);
6f1d69b0 4812
ecdb4eb7 4813 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4814 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4815 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4816
ecdb4eb7 4817 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4818 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4819
ecdb4eb7 4820 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4821 I915_WRITE(CACHE_MODE_1,
4822 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4823
4824 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4825 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4826 snpcr |= GEN6_MBC_SNPCR_MED;
4827 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4828
ab5c608b
BW		 4829 if (!HAS_PCH_NOP(dev))
4830 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4831
4832 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4833}
4834
1fa61106 4835static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4836{
4837 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4838
d7fe0cc0 4839 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4840
ecdb4eb7 4841 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4842 I915_WRITE(_3D_CHICKEN3,
4843 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4844
ecdb4eb7 4845 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4846 I915_WRITE(IVB_CHICKEN3,
4847 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4848 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4849
ecdb4eb7 4850 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4851 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4852 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4853 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4854
ecdb4eb7 4855 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4856 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4857 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4858
ecdb4eb7 4859 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4860 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4861 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4862
ecdb4eb7 4863 /* WaForceL3Serialization:vlv */
61939d97
JB		 4864 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4865 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4866
ecdb4eb7 4867 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4868 I915_WRITE(GEN7_ROW_CHICKEN2,
4869 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4870
ecdb4eb7 4871 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4872 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4873 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4874 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4875
ecdb4eb7 4876 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4877 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4878 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4879
0f846f81
JB		 4880
4881 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4882 * gating disable must be set. Failure to set it results in
4883 * flickering pixels due to Z write ordering failures after
4884 * some amount of runtime in the Mesa "fire" demo, and Unigine
4885 * Sanctuary and Tropics, and apparently anything else with
4886 * alpha test or pixel discard.
4887 *
4888 * According to the spec, bit 11 (RCCUNIT) must also be set,
4889 * but we didn't debug actual testcases to find it out.
4890 *
4891 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4892 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 4893 *
ecdb4eb7
DL		 4894 * Also apply WaDisableVDSUnitClockGating:vlv and
4895 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 4896 */
4897 I915_WRITE(GEN6_UCGCTL2,
4898 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 4899 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 4900 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4901 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4902 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4903
e3f33d46
JB		 4904 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
4905
e0d8d59b 4906 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 4907
6b26c86d
DV		 4908 I915_WRITE(CACHE_MODE_1,
4909 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 4910
2d809570 4911 /*
ecdb4eb7 4912 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 4913 * Disable clock gating on th GCFG unit to prevent a delay
4914 * in the reporting of vblank events.
4915 */
4e8c84a5
JB		 4916 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
4917
4918 /* Conservative clock gating settings for now */
4919 I915_WRITE(0x9400, 0xffffffff);
4920 I915_WRITE(0x9404, 0xffffffff);
4921 I915_WRITE(0x9408, 0xffffffff);
4922 I915_WRITE(0x940c, 0xffffffff);
4923 I915_WRITE(0x9410, 0xffffffff);
4924 I915_WRITE(0x9414, 0xffffffff);
4925 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4926}
4927
1fa61106 4928static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4929{
4930 struct drm_i915_private *dev_priv = dev->dev_private;
4931 uint32_t dspclk_gate;
4932
4933 I915_WRITE(RENCLK_GATE_D1, 0);
4934 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4935 GS_UNIT_CLOCK_GATE_DISABLE |
4936 CL_UNIT_CLOCK_GATE_DISABLE);
4937 I915_WRITE(RAMCLK_GATE_D, 0);
4938 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4939 OVRUNIT_CLOCK_GATE_DISABLE |
4940 OVCUNIT_CLOCK_GATE_DISABLE;
4941 if (IS_GM45(dev))
4942 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4943 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4944
4945 /* WaDisableRenderCachePipelinedFlush */
4946 I915_WRITE(CACHE_MODE_0,
4947 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 4948
0e088b8f 4949 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 4950}
4951
1fa61106 4952static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4953{
4954 struct drm_i915_private *dev_priv = dev->dev_private;
4955
4956 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4957 I915_WRITE(RENCLK_GATE_D2, 0);
4958 I915_WRITE(DSPCLK_GATE_D, 0);
4959 I915_WRITE(RAMCLK_GATE_D, 0);
4960 I915_WRITE16(DEUC, 0);
20f94967
VS		 4961 I915_WRITE(MI_ARB_STATE,
4962 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4963}
4964
1fa61106 4965static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4966{
4967 struct drm_i915_private *dev_priv = dev->dev_private;
4968
4969 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4970 I965_RCC_CLOCK_GATE_DISABLE |
4971 I965_RCPB_CLOCK_GATE_DISABLE |
4972 I965_ISC_CLOCK_GATE_DISABLE |
4973 I965_FBC_CLOCK_GATE_DISABLE);
4974 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 4975 I915_WRITE(MI_ARB_STATE,
4976 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 4977}
4978
1fa61106 4979static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4980{
4981 struct drm_i915_private *dev_priv = dev->dev_private;
4982 u32 dstate = I915_READ(D_STATE);
4983
4984 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4985 DSTATE_DOT_CLOCK_GATING;
4986 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4987
4988 if (IS_PINEVIEW(dev))
4989 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4990
4991 /* IIR "flip pending" means done if this bit is set */
4992 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4993}
4994
1fa61106 4995static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4996{
4997 struct drm_i915_private *dev_priv = dev->dev_private;
4998
4999 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5000}
5001
1fa61106 5002static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5003{
5004 struct drm_i915_private *dev_priv = dev->dev_private;
5005
5006 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5007}
5008
6f1d69b0
ED		 5009void intel_init_clock_gating(struct drm_device *dev)
5010{
5011 struct drm_i915_private *dev_priv = dev->dev_private;
5012
5013 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5014}
5015
7d708ee4
ID		 5016void intel_suspend_hw(struct drm_device *dev)
5017{
5018 if (HAS_PCH_LPT(dev))
5019 lpt_suspend_hw(dev);
5020}
5021
15d199ea
PZ		 5022/**
5023 * We should only use the power well if we explicitly asked the hardware to
5024 * enable it, so check if it's enabled and also check if we've requested it to
5025 * be enabled.
5026 */
b97186f0
PZ		 5027bool intel_display_power_enabled(struct drm_device *dev,
5028 enum intel_display_power_domain domain)
15d199ea
PZ		 5029{
5030 struct drm_i915_private *dev_priv = dev->dev_private;
5031
b97186f0
PZ		 5032 if (!HAS_POWER_WELL(dev))
5033 return true;
5034
5035 switch (domain) {
5036 case POWER_DOMAIN_PIPE_A:
5037 case POWER_DOMAIN_TRANSCODER_EDP:
5038 return true;
5039 case POWER_DOMAIN_PIPE_B:
5040 case POWER_DOMAIN_PIPE_C:
5041 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5042 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5043 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5044 case POWER_DOMAIN_TRANSCODER_A:
5045 case POWER_DOMAIN_TRANSCODER_B:
5046 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5047 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5048 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5049 default:
5050 BUG();
5051 }
15d199ea
PZ		 5052}
5053
a38911a3 5054static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5055{
5056 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5057 bool is_enabled, enable_requested;
5058 uint32_t tmp;
d0d3e513 5059
fa42e23c
PZ		 5060 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5061 is_enabled = tmp & HSW_PWR_WELL_STATE;
5062 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5063
fa42e23c
PZ		 5064 if (enable) {
5065 if (!enable_requested)
5066 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5067
fa42e23c
PZ		 5068 if (!is_enabled) {
5069 DRM_DEBUG_KMS("Enabling power well\n");
5070 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5071 HSW_PWR_WELL_STATE), 20))
5072 DRM_ERROR("Timeout enabling power well\n");
5073 }
5074 } else {
5075 if (enable_requested) {
5076 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5077 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5078 }
5079 }
fa42e23c 5080}
d0d3e513 5081
a38911a3
WX		 5082static struct i915_power_well *hsw_pwr;
5083
5084/* Display audio driver power well request */
5085void i915_request_power_well(void)
5086{
5087 if (WARN_ON(!hsw_pwr))
5088 return;
5089
5090 spin_lock_irq(&hsw_pwr->lock);
5091 if (!hsw_pwr->count++ &&
5092 !hsw_pwr->i915_request)
5093 __intel_set_power_well(hsw_pwr->device, true);
5094 spin_unlock_irq(&hsw_pwr->lock);
5095}
5096EXPORT_SYMBOL_GPL(i915_request_power_well);
5097
5098/* Display audio driver power well release */
5099void i915_release_power_well(void)
5100{
5101 if (WARN_ON(!hsw_pwr))
5102 return;
5103
5104 spin_lock_irq(&hsw_pwr->lock);
5105 WARN_ON(!hsw_pwr->count);
5106 if (!--hsw_pwr->count &&
5107 !hsw_pwr->i915_request)
5108 __intel_set_power_well(hsw_pwr->device, false);
5109 spin_unlock_irq(&hsw_pwr->lock);
5110}
5111EXPORT_SYMBOL_GPL(i915_release_power_well);
5112
5113int i915_init_power_well(struct drm_device *dev)
5114{
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116
5117 hsw_pwr = &dev_priv->power_well;
5118
5119 hsw_pwr->device = dev;
5120 spin_lock_init(&hsw_pwr->lock);
5121 hsw_pwr->count = 0;
5122
5123 return 0;
5124}
5125
5126void i915_remove_power_well(struct drm_device *dev)
5127{
5128 hsw_pwr = NULL;
5129}
5130
5131void intel_set_power_well(struct drm_device *dev, bool enable)
5132{
5133 struct drm_i915_private *dev_priv = dev->dev_private;
5134 struct i915_power_well *power_well = &dev_priv->power_well;
5135
5136 if (!HAS_POWER_WELL(dev))
5137 return;
5138
5139 if (!i915_disable_power_well && !enable)
5140 return;
5141
5142 spin_lock_irq(&power_well->lock);
5143 power_well->i915_request = enable;
5144
5145 /* only reject "disable" power well request */
5146 if (power_well->count && !enable) {
5147 spin_unlock_irq(&power_well->lock);
5148 return;
5149 }
5150
5151 __intel_set_power_well(dev, enable);
5152 spin_unlock_irq(&power_well->lock);
5153}
5154
fa42e23c
PZ		 5155/*
5156 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5157 * when not needed anymore. We have 4 registers that can request the power well
5158 * to be enabled, and it will only be disabled if none of the registers is
5159 * requesting it to be enabled.
d0d3e513 5160 */
fa42e23c 5161void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5162{
5163 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5164
86d52df6 5165 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5166 return;
5167
fa42e23c
PZ		 5168 /* For now, we need the power well to be always enabled. */
5169 intel_set_power_well(dev, true);
d0d3e513 5170
fa42e23c
PZ		 5171 /* We're taking over the BIOS, so clear any requests made by it since
5172 * the driver is in charge now. */
5173 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5174 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5175}
5176
1fa61106
ED		 5177/* Set up chip specific power management-related functions */
5178void intel_init_pm(struct drm_device *dev)
5179{
5180 struct drm_i915_private *dev_priv = dev->dev_private;
5181
5182 if (I915_HAS_FBC(dev)) {
5183 if (HAS_PCH_SPLIT(dev)) {
5184 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5185 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5186 dev_priv->display.enable_fbc =
5187 gen7_enable_fbc;
5188 else
5189 dev_priv->display.enable_fbc =
5190 ironlake_enable_fbc;
1fa61106
ED		 5191 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5192 } else if (IS_GM45(dev)) {
5193 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5194 dev_priv->display.enable_fbc = g4x_enable_fbc;
5195 dev_priv->display.disable_fbc = g4x_disable_fbc;
5196 } else if (IS_CRESTLINE(dev)) {
5197 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5198 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5199 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5200 }
5201 /* 855GM needs testing */
5202 }
5203
c921aba8
DV		 5204 /* For cxsr */
5205 if (IS_PINEVIEW(dev))
5206 i915_pineview_get_mem_freq(dev);
5207 else if (IS_GEN5(dev))
5208 i915_ironlake_get_mem_freq(dev);
5209
1fa61106
ED		 5210 /* For FIFO watermark updates */
5211 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 5212 if (IS_GEN5(dev)) {
5213 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
5214 dev_priv->display.update_wm = ironlake_update_wm;
5215 else {
5216 DRM_DEBUG_KMS("Failed to get proper latency. "
5217 "Disable CxSR\n");
5218 dev_priv->display.update_wm = NULL;
5219 }
5220 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5221 } else if (IS_GEN6(dev)) {
5222 if (SNB_READ_WM0_LATENCY()) {
5223 dev_priv->display.update_wm = sandybridge_update_wm;
5224 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5225 } else {
5226 DRM_DEBUG_KMS("Failed to read display plane latency. "
5227 "Disable CxSR\n");
5228 dev_priv->display.update_wm = NULL;
5229 }
5230 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5231 } else if (IS_IVYBRIDGE(dev)) {
1fa61106 5232 if (SNB_READ_WM0_LATENCY()) {
c43d0188 5233 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5234 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5235 } else {
5236 DRM_DEBUG_KMS("Failed to read display plane latency. "
5237 "Disable CxSR\n");
5238 dev_priv->display.update_wm = NULL;
5239 }
5240 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5241 } else if (IS_HASWELL(dev)) {
3e1f7266 5242 if (I915_READ64(MCH_SSKPD)) {
1011d8c4 5243 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5244 dev_priv->display.update_sprite_wm =
5245 haswell_update_sprite_wm;
6b8a5eeb
ED		 5246 } else {
5247 DRM_DEBUG_KMS("Failed to read display plane latency. "
5248 "Disable CxSR\n");
5249 dev_priv->display.update_wm = NULL;
5250 }
cad2a2d7 5251 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5252 } else
5253 dev_priv->display.update_wm = NULL;
5254 } else if (IS_VALLEYVIEW(dev)) {
5255 dev_priv->display.update_wm = valleyview_update_wm;
5256 dev_priv->display.init_clock_gating =
5257 valleyview_init_clock_gating;
1fa61106
ED		 5258 } else if (IS_PINEVIEW(dev)) {
5259 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5260 dev_priv->is_ddr3,
5261 dev_priv->fsb_freq,
5262 dev_priv->mem_freq)) {
5263 DRM_INFO("failed to find known CxSR latency "
5264 "(found ddr%s fsb freq %d, mem freq %d), "
5265 "disabling CxSR\n",
5266 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5267 dev_priv->fsb_freq, dev_priv->mem_freq);
5268 /* Disable CxSR and never update its watermark again */
5269 pineview_disable_cxsr(dev);
5270 dev_priv->display.update_wm = NULL;
5271 } else
5272 dev_priv->display.update_wm = pineview_update_wm;
5273 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5274 } else if (IS_G4X(dev)) {
5275 dev_priv->display.update_wm = g4x_update_wm;
5276 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5277 } else if (IS_GEN4(dev)) {
5278 dev_priv->display.update_wm = i965_update_wm;
5279 if (IS_CRESTLINE(dev))
5280 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5281 else if (IS_BROADWATER(dev))
5282 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5283 } else if (IS_GEN3(dev)) {
5284 dev_priv->display.update_wm = i9xx_update_wm;
5285 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5286 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5287 } else if (IS_I865G(dev)) {
5288 dev_priv->display.update_wm = i830_update_wm;
5289 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5290 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5291 } else if (IS_I85X(dev)) {
5292 dev_priv->display.update_wm = i9xx_update_wm;
5293 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5294 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5295 } else {
5296 dev_priv->display.update_wm = i830_update_wm;
5297 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5298 if (IS_845G(dev))
5299 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5300 else
5301 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5302 }
5303}
5304
42c0526c
BW		 5305int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5306{
4fc688ce 5307 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5308
5309 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5310 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5311 return -EAGAIN;
5312 }
5313
5314 I915_WRITE(GEN6_PCODE_DATA, *val);
5315 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5316
5317 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5318 500)) {
5319 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5320 return -ETIMEDOUT;
5321 }
5322
5323 *val = I915_READ(GEN6_PCODE_DATA);
5324 I915_WRITE(GEN6_PCODE_DATA, 0);
5325
5326 return 0;
5327}
5328
5329int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5330{
4fc688ce 5331 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5332
5333 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5334 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5335 return -EAGAIN;
5336 }
5337
5338 I915_WRITE(GEN6_PCODE_DATA, val);
5339 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5340
5341 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5342 500)) {
5343 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5344 return -ETIMEDOUT;
5345 }
5346
5347 I915_WRITE(GEN6_PCODE_DATA, 0);
5348
5349 return 0;
5350}
a0e4e199 5351
855ba3be
JB		 5352int vlv_gpu_freq(int ddr_freq, int val)
5353{
5354 int mult, base;
5355
5356 switch (ddr_freq) {
5357 case 800:
5358 mult = 20;
5359 base = 120;
5360 break;
5361 case 1066:
5362 mult = 22;
5363 base = 133;
5364 break;
5365 case 1333:
5366 mult = 21;
5367 base = 125;
5368 break;
5369 default:
5370 return -1;
5371 }
5372
5373 return ((val - 0xbd) * mult) + base;
5374}
5375
5376int vlv_freq_opcode(int ddr_freq, int val)
5377{
5378 int mult, base;
5379
5380 switch (ddr_freq) {
5381 case 800:
5382 mult = 20;
5383 base = 120;
5384 break;
5385 case 1066:
5386 mult = 22;
5387 base = 133;
5388 break;
5389 case 1333:
5390 mult = 21;
5391 base = 125;
5392 break;
5393 default:
5394 return -1;
5395 }
5396
5397 val /= mult;
5398 val -= base / mult;
5399 val += 0xbd;
5400
5401 if (val > 0xea)
5402 val = 0xea;
5403
5404 return val;
5405}
5406
907b28c5
CW		 5407void intel_pm_init(struct drm_device *dev)
5408{
5409 struct drm_i915_private *dev_priv = dev->dev_private;
5410
5411 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5412 intel_gen6_powersave_work);
5413}
5414
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