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85208be0 ED |
1 | /* |
2 | * Copyright © 2012 Intel Corporation | |
3 | * | |
4 | * Permission is hereby granted, free of charge, to any person obtaining a | |
5 | * copy of this software and associated documentation files (the "Software"), | |
6 | * to deal in the Software without restriction, including without limitation | |
7 | * the rights to use, copy, modify, merge, publish, distribute, sublicense, | |
8 | * and/or sell copies of the Software, and to permit persons to whom the | |
9 | * Software is furnished to do so, subject to the following conditions: | |
10 | * | |
11 | * The above copyright notice and this permission notice (including the next | |
12 | * paragraph) shall be included in all copies or substantial portions of the | |
13 | * Software. | |
14 | * | |
15 | * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR | |
16 | * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, | |
17 | * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL | |
18 | * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER | |
19 | * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING | |
20 | * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS | |
21 | * IN THE SOFTWARE. | |
22 | * | |
23 | * Authors: | |
24 | * Eugeni Dodonov <eugeni.dodonov@intel.com> | |
25 | * | |
26 | */ | |
27 | ||
2b4e57bd | 28 | #include <linux/cpufreq.h> |
85208be0 ED |
29 | #include "i915_drv.h" |
30 | #include "intel_drv.h" | |
eb48eb00 DV |
31 | #include "../../../platform/x86/intel_ips.h" |
32 | #include <linux/module.h> | |
85208be0 | 33 | |
dc39fff7 BW |
34 | /** |
35 | * RC6 is a special power stage which allows the GPU to enter an very | |
36 | * low-voltage mode when idle, using down to 0V while at this stage. This | |
37 | * stage is entered automatically when the GPU is idle when RC6 support is | |
38 | * enabled, and as soon as new workload arises GPU wakes up automatically as well. | |
39 | * | |
40 | * There are different RC6 modes available in Intel GPU, which differentiate | |
41 | * among each other with the latency required to enter and leave RC6 and | |
42 | * voltage consumed by the GPU in different states. | |
43 | * | |
44 | * The combination of the following flags define which states GPU is allowed | |
45 | * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and | |
46 | * RC6pp is deepest RC6. Their support by hardware varies according to the | |
47 | * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one | |
48 | * which brings the most power savings; deeper states save more power, but | |
49 | * require higher latency to switch to and wake up. | |
50 | */ | |
51 | #define INTEL_RC6_ENABLE (1<<0) | |
52 | #define INTEL_RC6p_ENABLE (1<<1) | |
53 | #define INTEL_RC6pp_ENABLE (1<<2) | |
54 | ||
f6750b3c ED |
55 | /* FBC, or Frame Buffer Compression, is a technique employed to compress the |
56 | * framebuffer contents in-memory, aiming at reducing the required bandwidth | |
57 | * during in-memory transfers and, therefore, reduce the power packet. | |
85208be0 | 58 | * |
f6750b3c ED |
59 | * The benefits of FBC are mostly visible with solid backgrounds and |
60 | * variation-less patterns. | |
85208be0 | 61 | * |
f6750b3c ED |
62 | * FBC-related functionality can be enabled by the means of the |
63 | * i915.i915_enable_fbc parameter | |
85208be0 ED |
64 | */ |
65 | ||
da2078cd DL |
66 | static void gen9_init_clock_gating(struct drm_device *dev) |
67 | { | |
acd5c346 DL |
68 | struct drm_i915_private *dev_priv = dev->dev_private; |
69 | ||
70 | /* | |
71 | * WaDisableSDEUnitClockGating:skl | |
72 | * This seems to be a pre-production w/a. | |
73 | */ | |
74 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
75 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
91e41d16 | 76 | |
3ca5da43 DL |
77 | /* |
78 | * WaDisableDgMirrorFixInHalfSliceChicken5:skl | |
79 | * This is a pre-production w/a. | |
80 | */ | |
81 | I915_WRITE(GEN9_HALF_SLICE_CHICKEN5, | |
82 | I915_READ(GEN9_HALF_SLICE_CHICKEN5) & | |
83 | ~GEN9_DG_MIRROR_FIX_ENABLE); | |
84 | ||
91e41d16 DL |
85 | /* Wa4x4STCOptimizationDisable:skl */ |
86 | I915_WRITE(CACHE_MODE_1, | |
87 | _MASKED_BIT_ENABLE(GEN8_4x4_STC_OPTIMIZATION_DISABLE)); | |
da2078cd DL |
88 | } |
89 | ||
1fa61106 | 90 | static void i8xx_disable_fbc(struct drm_device *dev) |
85208be0 ED |
91 | { |
92 | struct drm_i915_private *dev_priv = dev->dev_private; | |
93 | u32 fbc_ctl; | |
94 | ||
9adccc60 PZ |
95 | dev_priv->fbc.enabled = false; |
96 | ||
85208be0 ED |
97 | /* Disable compression */ |
98 | fbc_ctl = I915_READ(FBC_CONTROL); | |
99 | if ((fbc_ctl & FBC_CTL_EN) == 0) | |
100 | return; | |
101 | ||
102 | fbc_ctl &= ~FBC_CTL_EN; | |
103 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
104 | ||
105 | /* Wait for compressing bit to clear */ | |
106 | if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) { | |
107 | DRM_DEBUG_KMS("FBC idle timed out\n"); | |
108 | return; | |
109 | } | |
110 | ||
111 | DRM_DEBUG_KMS("disabled FBC\n"); | |
112 | } | |
113 | ||
993495ae | 114 | static void i8xx_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
115 | { |
116 | struct drm_device *dev = crtc->dev; | |
117 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 118 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 119 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 ED |
120 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
121 | int cfb_pitch; | |
7f2cf220 | 122 | int i; |
159f9875 | 123 | u32 fbc_ctl; |
85208be0 | 124 | |
9adccc60 PZ |
125 | dev_priv->fbc.enabled = true; |
126 | ||
5c3fe8b0 | 127 | cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE; |
85208be0 ED |
128 | if (fb->pitches[0] < cfb_pitch) |
129 | cfb_pitch = fb->pitches[0]; | |
130 | ||
42a430f5 VS |
131 | /* FBC_CTL wants 32B or 64B units */ |
132 | if (IS_GEN2(dev)) | |
133 | cfb_pitch = (cfb_pitch / 32) - 1; | |
134 | else | |
135 | cfb_pitch = (cfb_pitch / 64) - 1; | |
85208be0 ED |
136 | |
137 | /* Clear old tags */ | |
138 | for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++) | |
139 | I915_WRITE(FBC_TAG + (i * 4), 0); | |
140 | ||
159f9875 VS |
141 | if (IS_GEN4(dev)) { |
142 | u32 fbc_ctl2; | |
143 | ||
144 | /* Set it up... */ | |
145 | fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE; | |
7f2cf220 | 146 | fbc_ctl2 |= FBC_CTL_PLANE(intel_crtc->plane); |
159f9875 VS |
147 | I915_WRITE(FBC_CONTROL2, fbc_ctl2); |
148 | I915_WRITE(FBC_FENCE_OFF, crtc->y); | |
149 | } | |
85208be0 ED |
150 | |
151 | /* enable it... */ | |
993495ae VS |
152 | fbc_ctl = I915_READ(FBC_CONTROL); |
153 | fbc_ctl &= 0x3fff << FBC_CTL_INTERVAL_SHIFT; | |
154 | fbc_ctl |= FBC_CTL_EN | FBC_CTL_PERIODIC; | |
85208be0 ED |
155 | if (IS_I945GM(dev)) |
156 | fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */ | |
157 | fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT; | |
85208be0 ED |
158 | fbc_ctl |= obj->fence_reg; |
159 | I915_WRITE(FBC_CONTROL, fbc_ctl); | |
160 | ||
5cd5410e | 161 | DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c\n", |
84f44ce7 | 162 | cfb_pitch, crtc->y, plane_name(intel_crtc->plane)); |
85208be0 ED |
163 | } |
164 | ||
1fa61106 | 165 | static bool i8xx_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
166 | { |
167 | struct drm_i915_private *dev_priv = dev->dev_private; | |
168 | ||
169 | return I915_READ(FBC_CONTROL) & FBC_CTL_EN; | |
170 | } | |
171 | ||
993495ae | 172 | static void g4x_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
173 | { |
174 | struct drm_device *dev = crtc->dev; | |
175 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 176 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 177 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 | 178 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
85208be0 ED |
179 | u32 dpfc_ctl; |
180 | ||
9adccc60 PZ |
181 | dev_priv->fbc.enabled = true; |
182 | ||
3fa2e0ee VS |
183 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane) | DPFC_SR_EN; |
184 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
185 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; | |
186 | else | |
187 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; | |
85208be0 | 188 | dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg; |
85208be0 | 189 | |
85208be0 ED |
190 | I915_WRITE(DPFC_FENCE_YOFF, crtc->y); |
191 | ||
192 | /* enable it... */ | |
fe74c1a5 | 193 | I915_WRITE(DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
85208be0 | 194 | |
84f44ce7 | 195 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
196 | } |
197 | ||
1fa61106 | 198 | static void g4x_disable_fbc(struct drm_device *dev) |
85208be0 ED |
199 | { |
200 | struct drm_i915_private *dev_priv = dev->dev_private; | |
201 | u32 dpfc_ctl; | |
202 | ||
9adccc60 PZ |
203 | dev_priv->fbc.enabled = false; |
204 | ||
85208be0 ED |
205 | /* Disable compression */ |
206 | dpfc_ctl = I915_READ(DPFC_CONTROL); | |
207 | if (dpfc_ctl & DPFC_CTL_EN) { | |
208 | dpfc_ctl &= ~DPFC_CTL_EN; | |
209 | I915_WRITE(DPFC_CONTROL, dpfc_ctl); | |
210 | ||
211 | DRM_DEBUG_KMS("disabled FBC\n"); | |
212 | } | |
213 | } | |
214 | ||
1fa61106 | 215 | static bool g4x_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
216 | { |
217 | struct drm_i915_private *dev_priv = dev->dev_private; | |
218 | ||
219 | return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN; | |
220 | } | |
221 | ||
222 | static void sandybridge_blit_fbc_update(struct drm_device *dev) | |
223 | { | |
224 | struct drm_i915_private *dev_priv = dev->dev_private; | |
225 | u32 blt_ecoskpd; | |
226 | ||
227 | /* Make sure blitter notifies FBC of writes */ | |
940aece4 D |
228 | |
229 | /* Blitter is part of Media powerwell on VLV. No impact of | |
230 | * his param in other platforms for now */ | |
231 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_MEDIA); | |
c8d9a590 | 232 | |
85208be0 ED |
233 | blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD); |
234 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY << | |
235 | GEN6_BLITTER_LOCK_SHIFT; | |
236 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
237 | blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY; | |
238 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
239 | blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY << | |
240 | GEN6_BLITTER_LOCK_SHIFT); | |
241 | I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd); | |
242 | POSTING_READ(GEN6_BLITTER_ECOSKPD); | |
c8d9a590 | 243 | |
940aece4 | 244 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_MEDIA); |
85208be0 ED |
245 | } |
246 | ||
993495ae | 247 | static void ironlake_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
248 | { |
249 | struct drm_device *dev = crtc->dev; | |
250 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 251 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 252 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
85208be0 | 253 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
85208be0 ED |
254 | u32 dpfc_ctl; |
255 | ||
9adccc60 PZ |
256 | dev_priv->fbc.enabled = true; |
257 | ||
46f3dab9 | 258 | dpfc_ctl = DPFC_CTL_PLANE(intel_crtc->plane); |
3fa2e0ee | 259 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) |
5e59f717 BW |
260 | dev_priv->fbc.threshold++; |
261 | ||
262 | switch (dev_priv->fbc.threshold) { | |
263 | case 4: | |
264 | case 3: | |
265 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
266 | break; | |
267 | case 2: | |
3fa2e0ee | 268 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
269 | break; |
270 | case 1: | |
3fa2e0ee | 271 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
272 | break; |
273 | } | |
d629336b VS |
274 | dpfc_ctl |= DPFC_CTL_FENCE_EN; |
275 | if (IS_GEN5(dev)) | |
276 | dpfc_ctl |= obj->fence_reg; | |
85208be0 | 277 | |
85208be0 | 278 | I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y); |
f343c5f6 | 279 | I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID); |
85208be0 ED |
280 | /* enable it... */ |
281 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); | |
282 | ||
283 | if (IS_GEN6(dev)) { | |
284 | I915_WRITE(SNB_DPFC_CTL_SA, | |
285 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
286 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
287 | sandybridge_blit_fbc_update(dev); | |
288 | } | |
289 | ||
84f44ce7 | 290 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
85208be0 ED |
291 | } |
292 | ||
1fa61106 | 293 | static void ironlake_disable_fbc(struct drm_device *dev) |
85208be0 ED |
294 | { |
295 | struct drm_i915_private *dev_priv = dev->dev_private; | |
296 | u32 dpfc_ctl; | |
297 | ||
9adccc60 PZ |
298 | dev_priv->fbc.enabled = false; |
299 | ||
85208be0 ED |
300 | /* Disable compression */ |
301 | dpfc_ctl = I915_READ(ILK_DPFC_CONTROL); | |
302 | if (dpfc_ctl & DPFC_CTL_EN) { | |
303 | dpfc_ctl &= ~DPFC_CTL_EN; | |
304 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl); | |
305 | ||
306 | DRM_DEBUG_KMS("disabled FBC\n"); | |
307 | } | |
308 | } | |
309 | ||
1fa61106 | 310 | static bool ironlake_fbc_enabled(struct drm_device *dev) |
85208be0 ED |
311 | { |
312 | struct drm_i915_private *dev_priv = dev->dev_private; | |
313 | ||
314 | return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN; | |
315 | } | |
316 | ||
993495ae | 317 | static void gen7_enable_fbc(struct drm_crtc *crtc) |
abe959c7 RV |
318 | { |
319 | struct drm_device *dev = crtc->dev; | |
320 | struct drm_i915_private *dev_priv = dev->dev_private; | |
f4510a27 | 321 | struct drm_framebuffer *fb = crtc->primary->fb; |
2ff8fde1 | 322 | struct drm_i915_gem_object *obj = intel_fb_obj(fb); |
abe959c7 | 323 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3fa2e0ee | 324 | u32 dpfc_ctl; |
abe959c7 | 325 | |
9adccc60 PZ |
326 | dev_priv->fbc.enabled = true; |
327 | ||
3fa2e0ee VS |
328 | dpfc_ctl = IVB_DPFC_CTL_PLANE(intel_crtc->plane); |
329 | if (drm_format_plane_cpp(fb->pixel_format, 0) == 2) | |
5e59f717 BW |
330 | dev_priv->fbc.threshold++; |
331 | ||
332 | switch (dev_priv->fbc.threshold) { | |
333 | case 4: | |
334 | case 3: | |
335 | dpfc_ctl |= DPFC_CTL_LIMIT_4X; | |
336 | break; | |
337 | case 2: | |
3fa2e0ee | 338 | dpfc_ctl |= DPFC_CTL_LIMIT_2X; |
5e59f717 BW |
339 | break; |
340 | case 1: | |
3fa2e0ee | 341 | dpfc_ctl |= DPFC_CTL_LIMIT_1X; |
5e59f717 BW |
342 | break; |
343 | } | |
344 | ||
3fa2e0ee VS |
345 | dpfc_ctl |= IVB_DPFC_CTL_FENCE_EN; |
346 | ||
da46f936 RV |
347 | if (dev_priv->fbc.false_color) |
348 | dpfc_ctl |= FBC_CTL_FALSE_COLOR; | |
349 | ||
3fa2e0ee | 350 | I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN); |
abe959c7 | 351 | |
891348b2 | 352 | if (IS_IVYBRIDGE(dev)) { |
7dd23ba0 | 353 | /* WaFbcAsynchFlipDisableFbcQueue:ivb */ |
2adb6db8 VS |
354 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
355 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
356 | ILK_FBCQ_DIS); | |
28554164 | 357 | } else { |
2adb6db8 | 358 | /* WaFbcAsynchFlipDisableFbcQueue:hsw,bdw */ |
8f670bb1 VS |
359 | I915_WRITE(CHICKEN_PIPESL_1(intel_crtc->pipe), |
360 | I915_READ(CHICKEN_PIPESL_1(intel_crtc->pipe)) | | |
361 | HSW_FBCQ_DIS); | |
891348b2 | 362 | } |
b74ea102 | 363 | |
abe959c7 RV |
364 | I915_WRITE(SNB_DPFC_CTL_SA, |
365 | SNB_CPU_FENCE_ENABLE | obj->fence_reg); | |
366 | I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y); | |
367 | ||
368 | sandybridge_blit_fbc_update(dev); | |
369 | ||
b19870ee | 370 | DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane)); |
abe959c7 RV |
371 | } |
372 | ||
85208be0 ED |
373 | bool intel_fbc_enabled(struct drm_device *dev) |
374 | { | |
375 | struct drm_i915_private *dev_priv = dev->dev_private; | |
376 | ||
9adccc60 | 377 | return dev_priv->fbc.enabled; |
85208be0 ED |
378 | } |
379 | ||
1d73c2a8 | 380 | void bdw_fbc_sw_flush(struct drm_device *dev, u32 value) |
c5ad011d RV |
381 | { |
382 | struct drm_i915_private *dev_priv = dev->dev_private; | |
383 | ||
384 | if (!IS_GEN8(dev)) | |
385 | return; | |
386 | ||
01d06e9f RV |
387 | if (!intel_fbc_enabled(dev)) |
388 | return; | |
389 | ||
c5ad011d RV |
390 | I915_WRITE(MSG_FBC_REND_STATE, value); |
391 | } | |
392 | ||
85208be0 ED |
393 | static void intel_fbc_work_fn(struct work_struct *__work) |
394 | { | |
395 | struct intel_fbc_work *work = | |
396 | container_of(to_delayed_work(__work), | |
397 | struct intel_fbc_work, work); | |
398 | struct drm_device *dev = work->crtc->dev; | |
399 | struct drm_i915_private *dev_priv = dev->dev_private; | |
400 | ||
401 | mutex_lock(&dev->struct_mutex); | |
5c3fe8b0 | 402 | if (work == dev_priv->fbc.fbc_work) { |
85208be0 ED |
403 | /* Double check that we haven't switched fb without cancelling |
404 | * the prior work. | |
405 | */ | |
f4510a27 | 406 | if (work->crtc->primary->fb == work->fb) { |
993495ae | 407 | dev_priv->display.enable_fbc(work->crtc); |
85208be0 | 408 | |
5c3fe8b0 | 409 | dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane; |
f4510a27 | 410 | dev_priv->fbc.fb_id = work->crtc->primary->fb->base.id; |
5c3fe8b0 | 411 | dev_priv->fbc.y = work->crtc->y; |
85208be0 ED |
412 | } |
413 | ||
5c3fe8b0 | 414 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
415 | } |
416 | mutex_unlock(&dev->struct_mutex); | |
417 | ||
418 | kfree(work); | |
419 | } | |
420 | ||
421 | static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv) | |
422 | { | |
5c3fe8b0 | 423 | if (dev_priv->fbc.fbc_work == NULL) |
85208be0 ED |
424 | return; |
425 | ||
426 | DRM_DEBUG_KMS("cancelling pending FBC enable\n"); | |
427 | ||
428 | /* Synchronisation is provided by struct_mutex and checking of | |
5c3fe8b0 | 429 | * dev_priv->fbc.fbc_work, so we can perform the cancellation |
85208be0 ED |
430 | * entirely asynchronously. |
431 | */ | |
5c3fe8b0 | 432 | if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work)) |
85208be0 | 433 | /* tasklet was killed before being run, clean up */ |
5c3fe8b0 | 434 | kfree(dev_priv->fbc.fbc_work); |
85208be0 ED |
435 | |
436 | /* Mark the work as no longer wanted so that if it does | |
437 | * wake-up (because the work was already running and waiting | |
438 | * for our mutex), it will discover that is no longer | |
439 | * necessary to run. | |
440 | */ | |
5c3fe8b0 | 441 | dev_priv->fbc.fbc_work = NULL; |
85208be0 ED |
442 | } |
443 | ||
993495ae | 444 | static void intel_enable_fbc(struct drm_crtc *crtc) |
85208be0 ED |
445 | { |
446 | struct intel_fbc_work *work; | |
447 | struct drm_device *dev = crtc->dev; | |
448 | struct drm_i915_private *dev_priv = dev->dev_private; | |
449 | ||
450 | if (!dev_priv->display.enable_fbc) | |
451 | return; | |
452 | ||
453 | intel_cancel_fbc_work(dev_priv); | |
454 | ||
b14c5679 | 455 | work = kzalloc(sizeof(*work), GFP_KERNEL); |
85208be0 | 456 | if (work == NULL) { |
6cdcb5e7 | 457 | DRM_ERROR("Failed to allocate FBC work structure\n"); |
993495ae | 458 | dev_priv->display.enable_fbc(crtc); |
85208be0 ED |
459 | return; |
460 | } | |
461 | ||
462 | work->crtc = crtc; | |
f4510a27 | 463 | work->fb = crtc->primary->fb; |
85208be0 ED |
464 | INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn); |
465 | ||
5c3fe8b0 | 466 | dev_priv->fbc.fbc_work = work; |
85208be0 | 467 | |
85208be0 ED |
468 | /* Delay the actual enabling to let pageflipping cease and the |
469 | * display to settle before starting the compression. Note that | |
470 | * this delay also serves a second purpose: it allows for a | |
471 | * vblank to pass after disabling the FBC before we attempt | |
472 | * to modify the control registers. | |
473 | * | |
474 | * A more complicated solution would involve tracking vblanks | |
475 | * following the termination of the page-flipping sequence | |
476 | * and indeed performing the enable as a co-routine and not | |
477 | * waiting synchronously upon the vblank. | |
7457d617 DL |
478 | * |
479 | * WaFbcWaitForVBlankBeforeEnable:ilk,snb | |
85208be0 ED |
480 | */ |
481 | schedule_delayed_work(&work->work, msecs_to_jiffies(50)); | |
482 | } | |
483 | ||
484 | void intel_disable_fbc(struct drm_device *dev) | |
485 | { | |
486 | struct drm_i915_private *dev_priv = dev->dev_private; | |
487 | ||
488 | intel_cancel_fbc_work(dev_priv); | |
489 | ||
490 | if (!dev_priv->display.disable_fbc) | |
491 | return; | |
492 | ||
493 | dev_priv->display.disable_fbc(dev); | |
5c3fe8b0 | 494 | dev_priv->fbc.plane = -1; |
85208be0 ED |
495 | } |
496 | ||
29ebf90f CW |
497 | static bool set_no_fbc_reason(struct drm_i915_private *dev_priv, |
498 | enum no_fbc_reason reason) | |
499 | { | |
500 | if (dev_priv->fbc.no_fbc_reason == reason) | |
501 | return false; | |
502 | ||
503 | dev_priv->fbc.no_fbc_reason = reason; | |
504 | return true; | |
505 | } | |
506 | ||
85208be0 ED |
507 | /** |
508 | * intel_update_fbc - enable/disable FBC as needed | |
509 | * @dev: the drm_device | |
510 | * | |
511 | * Set up the framebuffer compression hardware at mode set time. We | |
512 | * enable it if possible: | |
513 | * - plane A only (on pre-965) | |
514 | * - no pixel mulitply/line duplication | |
515 | * - no alpha buffer discard | |
516 | * - no dual wide | |
f85da868 | 517 | * - framebuffer <= max_hdisplay in width, max_vdisplay in height |
85208be0 ED |
518 | * |
519 | * We can't assume that any compression will take place (worst case), | |
520 | * so the compressed buffer has to be the same size as the uncompressed | |
521 | * one. It also must reside (along with the line length buffer) in | |
522 | * stolen memory. | |
523 | * | |
524 | * We need to enable/disable FBC on a global basis. | |
525 | */ | |
526 | void intel_update_fbc(struct drm_device *dev) | |
527 | { | |
528 | struct drm_i915_private *dev_priv = dev->dev_private; | |
529 | struct drm_crtc *crtc = NULL, *tmp_crtc; | |
530 | struct intel_crtc *intel_crtc; | |
531 | struct drm_framebuffer *fb; | |
85208be0 | 532 | struct drm_i915_gem_object *obj; |
ef644fda | 533 | const struct drm_display_mode *adjusted_mode; |
37327abd | 534 | unsigned int max_width, max_height; |
85208be0 | 535 | |
3a77c4c4 | 536 | if (!HAS_FBC(dev)) { |
29ebf90f | 537 | set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED); |
85208be0 | 538 | return; |
29ebf90f | 539 | } |
85208be0 | 540 | |
d330a953 | 541 | if (!i915.powersave) { |
29ebf90f CW |
542 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
543 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 | 544 | return; |
29ebf90f | 545 | } |
85208be0 ED |
546 | |
547 | /* | |
548 | * If FBC is already on, we just have to verify that we can | |
549 | * keep it that way... | |
550 | * Need to disable if: | |
551 | * - more than one pipe is active | |
552 | * - changing FBC params (stride, fence, mode) | |
553 | * - new fb is too large to fit in compressed buffer | |
554 | * - going to an unsupported config (interlace, pixel multiply, etc.) | |
555 | */ | |
70e1e0ec | 556 | for_each_crtc(dev, tmp_crtc) { |
3490ea5d | 557 | if (intel_crtc_active(tmp_crtc) && |
4c445e0e | 558 | to_intel_crtc(tmp_crtc)->primary_enabled) { |
85208be0 | 559 | if (crtc) { |
29ebf90f CW |
560 | if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES)) |
561 | DRM_DEBUG_KMS("more than one pipe active, disabling compression\n"); | |
85208be0 ED |
562 | goto out_disable; |
563 | } | |
564 | crtc = tmp_crtc; | |
565 | } | |
566 | } | |
567 | ||
f4510a27 | 568 | if (!crtc || crtc->primary->fb == NULL) { |
29ebf90f CW |
569 | if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT)) |
570 | DRM_DEBUG_KMS("no output, disabling\n"); | |
85208be0 ED |
571 | goto out_disable; |
572 | } | |
573 | ||
574 | intel_crtc = to_intel_crtc(crtc); | |
f4510a27 | 575 | fb = crtc->primary->fb; |
2ff8fde1 | 576 | obj = intel_fb_obj(fb); |
ef644fda | 577 | adjusted_mode = &intel_crtc->config.adjusted_mode; |
85208be0 | 578 | |
0368920e | 579 | if (i915.enable_fbc < 0) { |
29ebf90f CW |
580 | if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT)) |
581 | DRM_DEBUG_KMS("disabled per chip default\n"); | |
8a5729a3 | 582 | goto out_disable; |
85208be0 | 583 | } |
d330a953 | 584 | if (!i915.enable_fbc) { |
29ebf90f CW |
585 | if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM)) |
586 | DRM_DEBUG_KMS("fbc disabled per module param\n"); | |
85208be0 ED |
587 | goto out_disable; |
588 | } | |
ef644fda VS |
589 | if ((adjusted_mode->flags & DRM_MODE_FLAG_INTERLACE) || |
590 | (adjusted_mode->flags & DRM_MODE_FLAG_DBLSCAN)) { | |
29ebf90f CW |
591 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) |
592 | DRM_DEBUG_KMS("mode incompatible with compression, " | |
593 | "disabling\n"); | |
85208be0 ED |
594 | goto out_disable; |
595 | } | |
f85da868 | 596 | |
032843a5 DS |
597 | if (INTEL_INFO(dev)->gen >= 8 || IS_HASWELL(dev)) { |
598 | max_width = 4096; | |
599 | max_height = 4096; | |
600 | } else if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) { | |
37327abd VS |
601 | max_width = 4096; |
602 | max_height = 2048; | |
f85da868 | 603 | } else { |
37327abd VS |
604 | max_width = 2048; |
605 | max_height = 1536; | |
f85da868 | 606 | } |
37327abd VS |
607 | if (intel_crtc->config.pipe_src_w > max_width || |
608 | intel_crtc->config.pipe_src_h > max_height) { | |
29ebf90f CW |
609 | if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE)) |
610 | DRM_DEBUG_KMS("mode too large for compression, disabling\n"); | |
85208be0 ED |
611 | goto out_disable; |
612 | } | |
8f94d24b | 613 | if ((INTEL_INFO(dev)->gen < 4 || HAS_DDI(dev)) && |
c5a44aa0 | 614 | intel_crtc->plane != PLANE_A) { |
29ebf90f | 615 | if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE)) |
c5a44aa0 | 616 | DRM_DEBUG_KMS("plane not A, disabling compression\n"); |
85208be0 ED |
617 | goto out_disable; |
618 | } | |
619 | ||
620 | /* The use of a CPU fence is mandatory in order to detect writes | |
621 | * by the CPU to the scanout and trigger updates to the FBC. | |
622 | */ | |
623 | if (obj->tiling_mode != I915_TILING_X || | |
624 | obj->fence_reg == I915_FENCE_REG_NONE) { | |
29ebf90f CW |
625 | if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED)) |
626 | DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n"); | |
85208be0 ED |
627 | goto out_disable; |
628 | } | |
48404c1e SJ |
629 | if (INTEL_INFO(dev)->gen <= 4 && !IS_G4X(dev) && |
630 | to_intel_plane(crtc->primary)->rotation != BIT(DRM_ROTATE_0)) { | |
631 | if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE)) | |
632 | DRM_DEBUG_KMS("Rotation unsupported, disabling\n"); | |
633 | goto out_disable; | |
634 | } | |
85208be0 ED |
635 | |
636 | /* If the kernel debugger is active, always disable compression */ | |
637 | if (in_dbg_master()) | |
638 | goto out_disable; | |
639 | ||
2ff8fde1 | 640 | if (i915_gem_stolen_setup_compression(dev, obj->base.size, |
5e59f717 | 641 | drm_format_plane_cpp(fb->pixel_format, 0))) { |
29ebf90f CW |
642 | if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL)) |
643 | DRM_DEBUG_KMS("framebuffer too large, disabling compression\n"); | |
11be49eb CW |
644 | goto out_disable; |
645 | } | |
646 | ||
85208be0 ED |
647 | /* If the scanout has not changed, don't modify the FBC settings. |
648 | * Note that we make the fundamental assumption that the fb->obj | |
649 | * cannot be unpinned (and have its GTT offset and fence revoked) | |
650 | * without first being decoupled from the scanout and FBC disabled. | |
651 | */ | |
5c3fe8b0 BW |
652 | if (dev_priv->fbc.plane == intel_crtc->plane && |
653 | dev_priv->fbc.fb_id == fb->base.id && | |
654 | dev_priv->fbc.y == crtc->y) | |
85208be0 ED |
655 | return; |
656 | ||
657 | if (intel_fbc_enabled(dev)) { | |
658 | /* We update FBC along two paths, after changing fb/crtc | |
659 | * configuration (modeswitching) and after page-flipping | |
660 | * finishes. For the latter, we know that not only did | |
661 | * we disable the FBC at the start of the page-flip | |
662 | * sequence, but also more than one vblank has passed. | |
663 | * | |
664 | * For the former case of modeswitching, it is possible | |
665 | * to switch between two FBC valid configurations | |
666 | * instantaneously so we do need to disable the FBC | |
667 | * before we can modify its control registers. We also | |
668 | * have to wait for the next vblank for that to take | |
669 | * effect. However, since we delay enabling FBC we can | |
670 | * assume that a vblank has passed since disabling and | |
671 | * that we can safely alter the registers in the deferred | |
672 | * callback. | |
673 | * | |
674 | * In the scenario that we go from a valid to invalid | |
675 | * and then back to valid FBC configuration we have | |
676 | * no strict enforcement that a vblank occurred since | |
677 | * disabling the FBC. However, along all current pipe | |
678 | * disabling paths we do need to wait for a vblank at | |
679 | * some point. And we wait before enabling FBC anyway. | |
680 | */ | |
681 | DRM_DEBUG_KMS("disabling active FBC for update\n"); | |
682 | intel_disable_fbc(dev); | |
683 | } | |
684 | ||
993495ae | 685 | intel_enable_fbc(crtc); |
29ebf90f | 686 | dev_priv->fbc.no_fbc_reason = FBC_OK; |
85208be0 ED |
687 | return; |
688 | ||
689 | out_disable: | |
690 | /* Multiple disables should be harmless */ | |
691 | if (intel_fbc_enabled(dev)) { | |
692 | DRM_DEBUG_KMS("unsupported config, disabling FBC\n"); | |
693 | intel_disable_fbc(dev); | |
694 | } | |
11be49eb | 695 | i915_gem_stolen_cleanup_compression(dev); |
85208be0 ED |
696 | } |
697 | ||
c921aba8 DV |
698 | static void i915_pineview_get_mem_freq(struct drm_device *dev) |
699 | { | |
50227e1c | 700 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
701 | u32 tmp; |
702 | ||
703 | tmp = I915_READ(CLKCFG); | |
704 | ||
705 | switch (tmp & CLKCFG_FSB_MASK) { | |
706 | case CLKCFG_FSB_533: | |
707 | dev_priv->fsb_freq = 533; /* 133*4 */ | |
708 | break; | |
709 | case CLKCFG_FSB_800: | |
710 | dev_priv->fsb_freq = 800; /* 200*4 */ | |
711 | break; | |
712 | case CLKCFG_FSB_667: | |
713 | dev_priv->fsb_freq = 667; /* 167*4 */ | |
714 | break; | |
715 | case CLKCFG_FSB_400: | |
716 | dev_priv->fsb_freq = 400; /* 100*4 */ | |
717 | break; | |
718 | } | |
719 | ||
720 | switch (tmp & CLKCFG_MEM_MASK) { | |
721 | case CLKCFG_MEM_533: | |
722 | dev_priv->mem_freq = 533; | |
723 | break; | |
724 | case CLKCFG_MEM_667: | |
725 | dev_priv->mem_freq = 667; | |
726 | break; | |
727 | case CLKCFG_MEM_800: | |
728 | dev_priv->mem_freq = 800; | |
729 | break; | |
730 | } | |
731 | ||
732 | /* detect pineview DDR3 setting */ | |
733 | tmp = I915_READ(CSHRDDR3CTL); | |
734 | dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0; | |
735 | } | |
736 | ||
737 | static void i915_ironlake_get_mem_freq(struct drm_device *dev) | |
738 | { | |
50227e1c | 739 | struct drm_i915_private *dev_priv = dev->dev_private; |
c921aba8 DV |
740 | u16 ddrpll, csipll; |
741 | ||
742 | ddrpll = I915_READ16(DDRMPLL1); | |
743 | csipll = I915_READ16(CSIPLL0); | |
744 | ||
745 | switch (ddrpll & 0xff) { | |
746 | case 0xc: | |
747 | dev_priv->mem_freq = 800; | |
748 | break; | |
749 | case 0x10: | |
750 | dev_priv->mem_freq = 1066; | |
751 | break; | |
752 | case 0x14: | |
753 | dev_priv->mem_freq = 1333; | |
754 | break; | |
755 | case 0x18: | |
756 | dev_priv->mem_freq = 1600; | |
757 | break; | |
758 | default: | |
759 | DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n", | |
760 | ddrpll & 0xff); | |
761 | dev_priv->mem_freq = 0; | |
762 | break; | |
763 | } | |
764 | ||
20e4d407 | 765 | dev_priv->ips.r_t = dev_priv->mem_freq; |
c921aba8 DV |
766 | |
767 | switch (csipll & 0x3ff) { | |
768 | case 0x00c: | |
769 | dev_priv->fsb_freq = 3200; | |
770 | break; | |
771 | case 0x00e: | |
772 | dev_priv->fsb_freq = 3733; | |
773 | break; | |
774 | case 0x010: | |
775 | dev_priv->fsb_freq = 4266; | |
776 | break; | |
777 | case 0x012: | |
778 | dev_priv->fsb_freq = 4800; | |
779 | break; | |
780 | case 0x014: | |
781 | dev_priv->fsb_freq = 5333; | |
782 | break; | |
783 | case 0x016: | |
784 | dev_priv->fsb_freq = 5866; | |
785 | break; | |
786 | case 0x018: | |
787 | dev_priv->fsb_freq = 6400; | |
788 | break; | |
789 | default: | |
790 | DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n", | |
791 | csipll & 0x3ff); | |
792 | dev_priv->fsb_freq = 0; | |
793 | break; | |
794 | } | |
795 | ||
796 | if (dev_priv->fsb_freq == 3200) { | |
20e4d407 | 797 | dev_priv->ips.c_m = 0; |
c921aba8 | 798 | } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) { |
20e4d407 | 799 | dev_priv->ips.c_m = 1; |
c921aba8 | 800 | } else { |
20e4d407 | 801 | dev_priv->ips.c_m = 2; |
c921aba8 DV |
802 | } |
803 | } | |
804 | ||
b445e3b0 ED |
805 | static const struct cxsr_latency cxsr_latency_table[] = { |
806 | {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */ | |
807 | {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */ | |
808 | {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */ | |
809 | {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */ | |
810 | {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */ | |
811 | ||
812 | {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */ | |
813 | {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */ | |
814 | {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */ | |
815 | {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */ | |
816 | {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */ | |
817 | ||
818 | {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */ | |
819 | {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */ | |
820 | {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */ | |
821 | {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */ | |
822 | {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */ | |
823 | ||
824 | {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */ | |
825 | {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */ | |
826 | {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */ | |
827 | {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */ | |
828 | {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */ | |
829 | ||
830 | {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */ | |
831 | {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */ | |
832 | {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */ | |
833 | {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */ | |
834 | {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */ | |
835 | ||
836 | {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */ | |
837 | {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */ | |
838 | {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */ | |
839 | {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */ | |
840 | {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */ | |
841 | }; | |
842 | ||
63c62275 | 843 | static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop, |
b445e3b0 ED |
844 | int is_ddr3, |
845 | int fsb, | |
846 | int mem) | |
847 | { | |
848 | const struct cxsr_latency *latency; | |
849 | int i; | |
850 | ||
851 | if (fsb == 0 || mem == 0) | |
852 | return NULL; | |
853 | ||
854 | for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) { | |
855 | latency = &cxsr_latency_table[i]; | |
856 | if (is_desktop == latency->is_desktop && | |
857 | is_ddr3 == latency->is_ddr3 && | |
858 | fsb == latency->fsb_freq && mem == latency->mem_freq) | |
859 | return latency; | |
860 | } | |
861 | ||
862 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
863 | ||
864 | return NULL; | |
865 | } | |
866 | ||
5209b1f4 | 867 | void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable) |
b445e3b0 | 868 | { |
5209b1f4 ID |
869 | struct drm_device *dev = dev_priv->dev; |
870 | u32 val; | |
b445e3b0 | 871 | |
5209b1f4 ID |
872 | if (IS_VALLEYVIEW(dev)) { |
873 | I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0); | |
874 | } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) { | |
875 | I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0); | |
876 | } else if (IS_PINEVIEW(dev)) { | |
877 | val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN; | |
878 | val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0; | |
879 | I915_WRITE(DSPFW3, val); | |
880 | } else if (IS_I945G(dev) || IS_I945GM(dev)) { | |
881 | val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) : | |
882 | _MASKED_BIT_DISABLE(FW_BLC_SELF_EN); | |
883 | I915_WRITE(FW_BLC_SELF, val); | |
884 | } else if (IS_I915GM(dev)) { | |
885 | val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) : | |
886 | _MASKED_BIT_DISABLE(INSTPM_SELF_EN); | |
887 | I915_WRITE(INSTPM, val); | |
888 | } else { | |
889 | return; | |
890 | } | |
b445e3b0 | 891 | |
5209b1f4 ID |
892 | DRM_DEBUG_KMS("memory self-refresh is %s\n", |
893 | enable ? "enabled" : "disabled"); | |
b445e3b0 ED |
894 | } |
895 | ||
896 | /* | |
897 | * Latency for FIFO fetches is dependent on several factors: | |
898 | * - memory configuration (speed, channels) | |
899 | * - chipset | |
900 | * - current MCH state | |
901 | * It can be fairly high in some situations, so here we assume a fairly | |
902 | * pessimal value. It's a tradeoff between extra memory fetches (if we | |
903 | * set this value too high, the FIFO will fetch frequently to stay full) | |
904 | * and power consumption (set it too low to save power and we might see | |
905 | * FIFO underruns and display "flicker"). | |
906 | * | |
907 | * A value of 5us seems to be a good balance; safe for very low end | |
908 | * platforms but not overly aggressive on lower latency configs. | |
909 | */ | |
5aef6003 | 910 | static const int pessimal_latency_ns = 5000; |
b445e3b0 | 911 | |
1fa61106 | 912 | static int i9xx_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
913 | { |
914 | struct drm_i915_private *dev_priv = dev->dev_private; | |
915 | uint32_t dsparb = I915_READ(DSPARB); | |
916 | int size; | |
917 | ||
918 | size = dsparb & 0x7f; | |
919 | if (plane) | |
920 | size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size; | |
921 | ||
922 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
923 | plane ? "B" : "A", size); | |
924 | ||
925 | return size; | |
926 | } | |
927 | ||
feb56b93 | 928 | static int i830_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
929 | { |
930 | struct drm_i915_private *dev_priv = dev->dev_private; | |
931 | uint32_t dsparb = I915_READ(DSPARB); | |
932 | int size; | |
933 | ||
934 | size = dsparb & 0x1ff; | |
935 | if (plane) | |
936 | size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size; | |
937 | size >>= 1; /* Convert to cachelines */ | |
938 | ||
939 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
940 | plane ? "B" : "A", size); | |
941 | ||
942 | return size; | |
943 | } | |
944 | ||
1fa61106 | 945 | static int i845_get_fifo_size(struct drm_device *dev, int plane) |
b445e3b0 ED |
946 | { |
947 | struct drm_i915_private *dev_priv = dev->dev_private; | |
948 | uint32_t dsparb = I915_READ(DSPARB); | |
949 | int size; | |
950 | ||
951 | size = dsparb & 0x7f; | |
952 | size >>= 2; /* Convert to cachelines */ | |
953 | ||
954 | DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb, | |
955 | plane ? "B" : "A", | |
956 | size); | |
957 | ||
958 | return size; | |
959 | } | |
960 | ||
b445e3b0 ED |
961 | /* Pineview has different values for various configs */ |
962 | static const struct intel_watermark_params pineview_display_wm = { | |
e0f0273e VS |
963 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
964 | .max_wm = PINEVIEW_MAX_WM, | |
965 | .default_wm = PINEVIEW_DFT_WM, | |
966 | .guard_size = PINEVIEW_GUARD_WM, | |
967 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
968 | }; |
969 | static const struct intel_watermark_params pineview_display_hplloff_wm = { | |
e0f0273e VS |
970 | .fifo_size = PINEVIEW_DISPLAY_FIFO, |
971 | .max_wm = PINEVIEW_MAX_WM, | |
972 | .default_wm = PINEVIEW_DFT_HPLLOFF_WM, | |
973 | .guard_size = PINEVIEW_GUARD_WM, | |
974 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
975 | }; |
976 | static const struct intel_watermark_params pineview_cursor_wm = { | |
e0f0273e VS |
977 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
978 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
979 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
980 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
981 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
982 | }; |
983 | static const struct intel_watermark_params pineview_cursor_hplloff_wm = { | |
e0f0273e VS |
984 | .fifo_size = PINEVIEW_CURSOR_FIFO, |
985 | .max_wm = PINEVIEW_CURSOR_MAX_WM, | |
986 | .default_wm = PINEVIEW_CURSOR_DFT_WM, | |
987 | .guard_size = PINEVIEW_CURSOR_GUARD_WM, | |
988 | .cacheline_size = PINEVIEW_FIFO_LINE_SIZE, | |
b445e3b0 ED |
989 | }; |
990 | static const struct intel_watermark_params g4x_wm_info = { | |
e0f0273e VS |
991 | .fifo_size = G4X_FIFO_SIZE, |
992 | .max_wm = G4X_MAX_WM, | |
993 | .default_wm = G4X_MAX_WM, | |
994 | .guard_size = 2, | |
995 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
996 | }; |
997 | static const struct intel_watermark_params g4x_cursor_wm_info = { | |
e0f0273e VS |
998 | .fifo_size = I965_CURSOR_FIFO, |
999 | .max_wm = I965_CURSOR_MAX_WM, | |
1000 | .default_wm = I965_CURSOR_DFT_WM, | |
1001 | .guard_size = 2, | |
1002 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1003 | }; |
1004 | static const struct intel_watermark_params valleyview_wm_info = { | |
e0f0273e VS |
1005 | .fifo_size = VALLEYVIEW_FIFO_SIZE, |
1006 | .max_wm = VALLEYVIEW_MAX_WM, | |
1007 | .default_wm = VALLEYVIEW_MAX_WM, | |
1008 | .guard_size = 2, | |
1009 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1010 | }; |
1011 | static const struct intel_watermark_params valleyview_cursor_wm_info = { | |
e0f0273e VS |
1012 | .fifo_size = I965_CURSOR_FIFO, |
1013 | .max_wm = VALLEYVIEW_CURSOR_MAX_WM, | |
1014 | .default_wm = I965_CURSOR_DFT_WM, | |
1015 | .guard_size = 2, | |
1016 | .cacheline_size = G4X_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1017 | }; |
1018 | static const struct intel_watermark_params i965_cursor_wm_info = { | |
e0f0273e VS |
1019 | .fifo_size = I965_CURSOR_FIFO, |
1020 | .max_wm = I965_CURSOR_MAX_WM, | |
1021 | .default_wm = I965_CURSOR_DFT_WM, | |
1022 | .guard_size = 2, | |
1023 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1024 | }; |
1025 | static const struct intel_watermark_params i945_wm_info = { | |
e0f0273e VS |
1026 | .fifo_size = I945_FIFO_SIZE, |
1027 | .max_wm = I915_MAX_WM, | |
1028 | .default_wm = 1, | |
1029 | .guard_size = 2, | |
1030 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1031 | }; |
1032 | static const struct intel_watermark_params i915_wm_info = { | |
e0f0273e VS |
1033 | .fifo_size = I915_FIFO_SIZE, |
1034 | .max_wm = I915_MAX_WM, | |
1035 | .default_wm = 1, | |
1036 | .guard_size = 2, | |
1037 | .cacheline_size = I915_FIFO_LINE_SIZE, | |
b445e3b0 | 1038 | }; |
9d539105 | 1039 | static const struct intel_watermark_params i830_a_wm_info = { |
e0f0273e VS |
1040 | .fifo_size = I855GM_FIFO_SIZE, |
1041 | .max_wm = I915_MAX_WM, | |
1042 | .default_wm = 1, | |
1043 | .guard_size = 2, | |
1044 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 | 1045 | }; |
9d539105 VS |
1046 | static const struct intel_watermark_params i830_bc_wm_info = { |
1047 | .fifo_size = I855GM_FIFO_SIZE, | |
1048 | .max_wm = I915_MAX_WM/2, | |
1049 | .default_wm = 1, | |
1050 | .guard_size = 2, | |
1051 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
1052 | }; | |
feb56b93 | 1053 | static const struct intel_watermark_params i845_wm_info = { |
e0f0273e VS |
1054 | .fifo_size = I830_FIFO_SIZE, |
1055 | .max_wm = I915_MAX_WM, | |
1056 | .default_wm = 1, | |
1057 | .guard_size = 2, | |
1058 | .cacheline_size = I830_FIFO_LINE_SIZE, | |
b445e3b0 ED |
1059 | }; |
1060 | ||
b445e3b0 ED |
1061 | /** |
1062 | * intel_calculate_wm - calculate watermark level | |
1063 | * @clock_in_khz: pixel clock | |
1064 | * @wm: chip FIFO params | |
1065 | * @pixel_size: display pixel size | |
1066 | * @latency_ns: memory latency for the platform | |
1067 | * | |
1068 | * Calculate the watermark level (the level at which the display plane will | |
1069 | * start fetching from memory again). Each chip has a different display | |
1070 | * FIFO size and allocation, so the caller needs to figure that out and pass | |
1071 | * in the correct intel_watermark_params structure. | |
1072 | * | |
1073 | * As the pixel clock runs, the FIFO will be drained at a rate that depends | |
1074 | * on the pixel size. When it reaches the watermark level, it'll start | |
1075 | * fetching FIFO line sized based chunks from memory until the FIFO fills | |
1076 | * past the watermark point. If the FIFO drains completely, a FIFO underrun | |
1077 | * will occur, and a display engine hang could result. | |
1078 | */ | |
1079 | static unsigned long intel_calculate_wm(unsigned long clock_in_khz, | |
1080 | const struct intel_watermark_params *wm, | |
1081 | int fifo_size, | |
1082 | int pixel_size, | |
1083 | unsigned long latency_ns) | |
1084 | { | |
1085 | long entries_required, wm_size; | |
1086 | ||
1087 | /* | |
1088 | * Note: we need to make sure we don't overflow for various clock & | |
1089 | * latency values. | |
1090 | * clocks go from a few thousand to several hundred thousand. | |
1091 | * latency is usually a few thousand | |
1092 | */ | |
1093 | entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) / | |
1094 | 1000; | |
1095 | entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size); | |
1096 | ||
1097 | DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required); | |
1098 | ||
1099 | wm_size = fifo_size - (entries_required + wm->guard_size); | |
1100 | ||
1101 | DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size); | |
1102 | ||
1103 | /* Don't promote wm_size to unsigned... */ | |
1104 | if (wm_size > (long)wm->max_wm) | |
1105 | wm_size = wm->max_wm; | |
1106 | if (wm_size <= 0) | |
1107 | wm_size = wm->default_wm; | |
d6feb196 VS |
1108 | |
1109 | /* | |
1110 | * Bspec seems to indicate that the value shouldn't be lower than | |
1111 | * 'burst size + 1'. Certainly 830 is quite unhappy with low values. | |
1112 | * Lets go for 8 which is the burst size since certain platforms | |
1113 | * already use a hardcoded 8 (which is what the spec says should be | |
1114 | * done). | |
1115 | */ | |
1116 | if (wm_size <= 8) | |
1117 | wm_size = 8; | |
1118 | ||
b445e3b0 ED |
1119 | return wm_size; |
1120 | } | |
1121 | ||
1122 | static struct drm_crtc *single_enabled_crtc(struct drm_device *dev) | |
1123 | { | |
1124 | struct drm_crtc *crtc, *enabled = NULL; | |
1125 | ||
70e1e0ec | 1126 | for_each_crtc(dev, crtc) { |
3490ea5d | 1127 | if (intel_crtc_active(crtc)) { |
b445e3b0 ED |
1128 | if (enabled) |
1129 | return NULL; | |
1130 | enabled = crtc; | |
1131 | } | |
1132 | } | |
1133 | ||
1134 | return enabled; | |
1135 | } | |
1136 | ||
46ba614c | 1137 | static void pineview_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1138 | { |
46ba614c | 1139 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1140 | struct drm_i915_private *dev_priv = dev->dev_private; |
1141 | struct drm_crtc *crtc; | |
1142 | const struct cxsr_latency *latency; | |
1143 | u32 reg; | |
1144 | unsigned long wm; | |
1145 | ||
1146 | latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3, | |
1147 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
1148 | if (!latency) { | |
1149 | DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n"); | |
5209b1f4 | 1150 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1151 | return; |
1152 | } | |
1153 | ||
1154 | crtc = single_enabled_crtc(dev); | |
1155 | if (crtc) { | |
241bfc38 | 1156 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1157 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
241bfc38 DL |
1158 | int clock; |
1159 | ||
1160 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; | |
1161 | clock = adjusted_mode->crtc_clock; | |
b445e3b0 ED |
1162 | |
1163 | /* Display SR */ | |
1164 | wm = intel_calculate_wm(clock, &pineview_display_wm, | |
1165 | pineview_display_wm.fifo_size, | |
1166 | pixel_size, latency->display_sr); | |
1167 | reg = I915_READ(DSPFW1); | |
1168 | reg &= ~DSPFW_SR_MASK; | |
1169 | reg |= wm << DSPFW_SR_SHIFT; | |
1170 | I915_WRITE(DSPFW1, reg); | |
1171 | DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg); | |
1172 | ||
1173 | /* cursor SR */ | |
1174 | wm = intel_calculate_wm(clock, &pineview_cursor_wm, | |
1175 | pineview_display_wm.fifo_size, | |
1176 | pixel_size, latency->cursor_sr); | |
1177 | reg = I915_READ(DSPFW3); | |
1178 | reg &= ~DSPFW_CURSOR_SR_MASK; | |
1179 | reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT; | |
1180 | I915_WRITE(DSPFW3, reg); | |
1181 | ||
1182 | /* Display HPLL off SR */ | |
1183 | wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm, | |
1184 | pineview_display_hplloff_wm.fifo_size, | |
1185 | pixel_size, latency->display_hpll_disable); | |
1186 | reg = I915_READ(DSPFW3); | |
1187 | reg &= ~DSPFW_HPLL_SR_MASK; | |
1188 | reg |= wm & DSPFW_HPLL_SR_MASK; | |
1189 | I915_WRITE(DSPFW3, reg); | |
1190 | ||
1191 | /* cursor HPLL off SR */ | |
1192 | wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm, | |
1193 | pineview_display_hplloff_wm.fifo_size, | |
1194 | pixel_size, latency->cursor_hpll_disable); | |
1195 | reg = I915_READ(DSPFW3); | |
1196 | reg &= ~DSPFW_HPLL_CURSOR_MASK; | |
1197 | reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT; | |
1198 | I915_WRITE(DSPFW3, reg); | |
1199 | DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg); | |
1200 | ||
5209b1f4 | 1201 | intel_set_memory_cxsr(dev_priv, true); |
b445e3b0 | 1202 | } else { |
5209b1f4 | 1203 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1204 | } |
1205 | } | |
1206 | ||
1207 | static bool g4x_compute_wm0(struct drm_device *dev, | |
1208 | int plane, | |
1209 | const struct intel_watermark_params *display, | |
1210 | int display_latency_ns, | |
1211 | const struct intel_watermark_params *cursor, | |
1212 | int cursor_latency_ns, | |
1213 | int *plane_wm, | |
1214 | int *cursor_wm) | |
1215 | { | |
1216 | struct drm_crtc *crtc; | |
4fe8590a | 1217 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1218 | int htotal, hdisplay, clock, pixel_size; |
1219 | int line_time_us, line_count; | |
1220 | int entries, tlb_miss; | |
1221 | ||
1222 | crtc = intel_get_crtc_for_plane(dev, plane); | |
3490ea5d | 1223 | if (!intel_crtc_active(crtc)) { |
b445e3b0 ED |
1224 | *cursor_wm = cursor->guard_size; |
1225 | *plane_wm = display->guard_size; | |
1226 | return false; | |
1227 | } | |
1228 | ||
4fe8590a | 1229 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1230 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1231 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1232 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1233 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1234 | |
1235 | /* Use the small buffer method to calculate plane watermark */ | |
1236 | entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000; | |
1237 | tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8; | |
1238 | if (tlb_miss > 0) | |
1239 | entries += tlb_miss; | |
1240 | entries = DIV_ROUND_UP(entries, display->cacheline_size); | |
1241 | *plane_wm = entries + display->guard_size; | |
1242 | if (*plane_wm > (int)display->max_wm) | |
1243 | *plane_wm = display->max_wm; | |
1244 | ||
1245 | /* Use the large buffer method to calculate cursor watermark */ | |
922044c9 | 1246 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 | 1247 | line_count = (cursor_latency_ns / line_time_us + 1000) / 1000; |
7bb836dd | 1248 | entries = line_count * to_intel_crtc(crtc)->cursor_width * pixel_size; |
b445e3b0 ED |
1249 | tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8; |
1250 | if (tlb_miss > 0) | |
1251 | entries += tlb_miss; | |
1252 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); | |
1253 | *cursor_wm = entries + cursor->guard_size; | |
1254 | if (*cursor_wm > (int)cursor->max_wm) | |
1255 | *cursor_wm = (int)cursor->max_wm; | |
1256 | ||
1257 | return true; | |
1258 | } | |
1259 | ||
1260 | /* | |
1261 | * Check the wm result. | |
1262 | * | |
1263 | * If any calculated watermark values is larger than the maximum value that | |
1264 | * can be programmed into the associated watermark register, that watermark | |
1265 | * must be disabled. | |
1266 | */ | |
1267 | static bool g4x_check_srwm(struct drm_device *dev, | |
1268 | int display_wm, int cursor_wm, | |
1269 | const struct intel_watermark_params *display, | |
1270 | const struct intel_watermark_params *cursor) | |
1271 | { | |
1272 | DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n", | |
1273 | display_wm, cursor_wm); | |
1274 | ||
1275 | if (display_wm > display->max_wm) { | |
1276 | DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n", | |
1277 | display_wm, display->max_wm); | |
1278 | return false; | |
1279 | } | |
1280 | ||
1281 | if (cursor_wm > cursor->max_wm) { | |
1282 | DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n", | |
1283 | cursor_wm, cursor->max_wm); | |
1284 | return false; | |
1285 | } | |
1286 | ||
1287 | if (!(display_wm || cursor_wm)) { | |
1288 | DRM_DEBUG_KMS("SR latency is 0, disabling\n"); | |
1289 | return false; | |
1290 | } | |
1291 | ||
1292 | return true; | |
1293 | } | |
1294 | ||
1295 | static bool g4x_compute_srwm(struct drm_device *dev, | |
1296 | int plane, | |
1297 | int latency_ns, | |
1298 | const struct intel_watermark_params *display, | |
1299 | const struct intel_watermark_params *cursor, | |
1300 | int *display_wm, int *cursor_wm) | |
1301 | { | |
1302 | struct drm_crtc *crtc; | |
4fe8590a | 1303 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1304 | int hdisplay, htotal, pixel_size, clock; |
1305 | unsigned long line_time_us; | |
1306 | int line_count, line_size; | |
1307 | int small, large; | |
1308 | int entries; | |
1309 | ||
1310 | if (!latency_ns) { | |
1311 | *display_wm = *cursor_wm = 0; | |
1312 | return false; | |
1313 | } | |
1314 | ||
1315 | crtc = intel_get_crtc_for_plane(dev, plane); | |
4fe8590a | 1316 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
241bfc38 | 1317 | clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1318 | htotal = adjusted_mode->crtc_htotal; |
37327abd | 1319 | hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1320 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 | 1321 | |
922044c9 | 1322 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1323 | line_count = (latency_ns / line_time_us + 1000) / 1000; |
1324 | line_size = hdisplay * pixel_size; | |
1325 | ||
1326 | /* Use the minimum of the small and large buffer method for primary */ | |
1327 | small = ((clock * pixel_size / 1000) * latency_ns) / 1000; | |
1328 | large = line_count * line_size; | |
1329 | ||
1330 | entries = DIV_ROUND_UP(min(small, large), display->cacheline_size); | |
1331 | *display_wm = entries + display->guard_size; | |
1332 | ||
1333 | /* calculate the self-refresh watermark for display cursor */ | |
7bb836dd | 1334 | entries = line_count * pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1335 | entries = DIV_ROUND_UP(entries, cursor->cacheline_size); |
1336 | *cursor_wm = entries + cursor->guard_size; | |
1337 | ||
1338 | return g4x_check_srwm(dev, | |
1339 | *display_wm, *cursor_wm, | |
1340 | display, cursor); | |
1341 | } | |
1342 | ||
0948c265 GB |
1343 | static bool vlv_compute_drain_latency(struct drm_crtc *crtc, |
1344 | int pixel_size, | |
1345 | int *prec_mult, | |
1346 | int *drain_latency) | |
b445e3b0 | 1347 | { |
5e56ba45 | 1348 | struct drm_device *dev = crtc->dev; |
b445e3b0 | 1349 | int entries; |
0948c265 | 1350 | int clock = to_intel_crtc(crtc)->config.adjusted_mode.crtc_clock; |
b445e3b0 | 1351 | |
0948c265 | 1352 | if (WARN(clock == 0, "Pixel clock is zero!\n")) |
b445e3b0 ED |
1353 | return false; |
1354 | ||
0948c265 GB |
1355 | if (WARN(pixel_size == 0, "Pixel size is zero!\n")) |
1356 | return false; | |
b445e3b0 | 1357 | |
a398e9c7 | 1358 | entries = DIV_ROUND_UP(clock, 1000) * pixel_size; |
5e56ba45 RV |
1359 | if (IS_CHERRYVIEW(dev)) |
1360 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_32 : | |
1361 | DRAIN_LATENCY_PRECISION_16; | |
1362 | else | |
1363 | *prec_mult = (entries > 128) ? DRAIN_LATENCY_PRECISION_64 : | |
1364 | DRAIN_LATENCY_PRECISION_32; | |
0948c265 | 1365 | *drain_latency = (64 * (*prec_mult) * 4) / entries; |
b445e3b0 | 1366 | |
a398e9c7 GB |
1367 | if (*drain_latency > DRAIN_LATENCY_MASK) |
1368 | *drain_latency = DRAIN_LATENCY_MASK; | |
b445e3b0 ED |
1369 | |
1370 | return true; | |
1371 | } | |
1372 | ||
1373 | /* | |
1374 | * Update drain latency registers of memory arbiter | |
1375 | * | |
1376 | * Valleyview SoC has a new memory arbiter and needs drain latency registers | |
1377 | * to be programmed. Each plane has a drain latency multiplier and a drain | |
1378 | * latency value. | |
1379 | */ | |
1380 | ||
41aad816 | 1381 | static void vlv_update_drain_latency(struct drm_crtc *crtc) |
b445e3b0 | 1382 | { |
5e56ba45 RV |
1383 | struct drm_device *dev = crtc->dev; |
1384 | struct drm_i915_private *dev_priv = dev->dev_private; | |
0948c265 GB |
1385 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1386 | int pixel_size; | |
1387 | int drain_latency; | |
1388 | enum pipe pipe = intel_crtc->pipe; | |
1389 | int plane_prec, prec_mult, plane_dl; | |
5e56ba45 RV |
1390 | const int high_precision = IS_CHERRYVIEW(dev) ? |
1391 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
b445e3b0 | 1392 | |
5e56ba45 RV |
1393 | plane_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_PLANE_PRECISION_HIGH | |
1394 | DRAIN_LATENCY_MASK | DDL_CURSOR_PRECISION_HIGH | | |
0948c265 GB |
1395 | (DRAIN_LATENCY_MASK << DDL_CURSOR_SHIFT)); |
1396 | ||
1397 | if (!intel_crtc_active(crtc)) { | |
1398 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
1399 | return; | |
1400 | } | |
b445e3b0 | 1401 | |
0948c265 GB |
1402 | /* Primary plane Drain Latency */ |
1403 | pixel_size = crtc->primary->fb->bits_per_pixel / 8; /* BPP */ | |
1404 | if (vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
5e56ba45 RV |
1405 | plane_prec = (prec_mult == high_precision) ? |
1406 | DDL_PLANE_PRECISION_HIGH : | |
1407 | DDL_PLANE_PRECISION_LOW; | |
0948c265 | 1408 | plane_dl |= plane_prec | drain_latency; |
b445e3b0 ED |
1409 | } |
1410 | ||
0948c265 GB |
1411 | /* Cursor Drain Latency |
1412 | * BPP is always 4 for cursor | |
1413 | */ | |
1414 | pixel_size = 4; | |
b445e3b0 | 1415 | |
0948c265 GB |
1416 | /* Program cursor DL only if it is enabled */ |
1417 | if (intel_crtc->cursor_base && | |
1418 | vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, &drain_latency)) { | |
5e56ba45 RV |
1419 | plane_prec = (prec_mult == high_precision) ? |
1420 | DDL_CURSOR_PRECISION_HIGH : | |
1421 | DDL_CURSOR_PRECISION_LOW; | |
0948c265 | 1422 | plane_dl |= plane_prec | (drain_latency << DDL_CURSOR_SHIFT); |
b445e3b0 | 1423 | } |
0948c265 GB |
1424 | |
1425 | I915_WRITE(VLV_DDL(pipe), plane_dl); | |
b445e3b0 ED |
1426 | } |
1427 | ||
1428 | #define single_plane_enabled(mask) is_power_of_2(mask) | |
1429 | ||
46ba614c | 1430 | static void valleyview_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1431 | { |
46ba614c | 1432 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1433 | static const int sr_latency_ns = 12000; |
1434 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1435 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1436 | int plane_sr, cursor_sr; | |
af6c4575 | 1437 | int ignore_plane_sr, ignore_cursor_sr; |
b445e3b0 | 1438 | unsigned int enabled = 0; |
9858425c | 1439 | bool cxsr_enabled; |
b445e3b0 | 1440 | |
41aad816 | 1441 | vlv_update_drain_latency(crtc); |
b445e3b0 | 1442 | |
51cea1f4 | 1443 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1444 | &valleyview_wm_info, pessimal_latency_ns, |
1445 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1446 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1447 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1448 | |
51cea1f4 | 1449 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1450 | &valleyview_wm_info, pessimal_latency_ns, |
1451 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1452 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1453 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1454 | |
b445e3b0 ED |
1455 | if (single_plane_enabled(enabled) && |
1456 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1457 | sr_latency_ns, | |
1458 | &valleyview_wm_info, | |
1459 | &valleyview_cursor_wm_info, | |
af6c4575 CW |
1460 | &plane_sr, &ignore_cursor_sr) && |
1461 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1462 | 2*sr_latency_ns, | |
1463 | &valleyview_wm_info, | |
1464 | &valleyview_cursor_wm_info, | |
52bd02d8 | 1465 | &ignore_plane_sr, &cursor_sr)) { |
9858425c | 1466 | cxsr_enabled = true; |
52bd02d8 | 1467 | } else { |
9858425c | 1468 | cxsr_enabled = false; |
5209b1f4 | 1469 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1470 | plane_sr = cursor_sr = 0; |
1471 | } | |
b445e3b0 | 1472 | |
a5043453 VS |
1473 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1474 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1475 | planea_wm, cursora_wm, |
1476 | planeb_wm, cursorb_wm, | |
1477 | plane_sr, cursor_sr); | |
1478 | ||
1479 | I915_WRITE(DSPFW1, | |
1480 | (plane_sr << DSPFW_SR_SHIFT) | | |
1481 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1482 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1483 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1484 | I915_WRITE(DSPFW2, |
8c919b28 | 1485 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1486 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1487 | I915_WRITE(DSPFW3, | |
8c919b28 CW |
1488 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | |
1489 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1490 | |
1491 | if (cxsr_enabled) | |
1492 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1493 | } |
1494 | ||
3c2777fd VS |
1495 | static void cherryview_update_wm(struct drm_crtc *crtc) |
1496 | { | |
1497 | struct drm_device *dev = crtc->dev; | |
1498 | static const int sr_latency_ns = 12000; | |
1499 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1500 | int planea_wm, planeb_wm, planec_wm; | |
1501 | int cursora_wm, cursorb_wm, cursorc_wm; | |
1502 | int plane_sr, cursor_sr; | |
1503 | int ignore_plane_sr, ignore_cursor_sr; | |
1504 | unsigned int enabled = 0; | |
1505 | bool cxsr_enabled; | |
1506 | ||
1507 | vlv_update_drain_latency(crtc); | |
1508 | ||
1509 | if (g4x_compute_wm0(dev, PIPE_A, | |
5aef6003 CW |
1510 | &valleyview_wm_info, pessimal_latency_ns, |
1511 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1512 | &planea_wm, &cursora_wm)) |
1513 | enabled |= 1 << PIPE_A; | |
1514 | ||
1515 | if (g4x_compute_wm0(dev, PIPE_B, | |
5aef6003 CW |
1516 | &valleyview_wm_info, pessimal_latency_ns, |
1517 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1518 | &planeb_wm, &cursorb_wm)) |
1519 | enabled |= 1 << PIPE_B; | |
1520 | ||
1521 | if (g4x_compute_wm0(dev, PIPE_C, | |
5aef6003 CW |
1522 | &valleyview_wm_info, pessimal_latency_ns, |
1523 | &valleyview_cursor_wm_info, pessimal_latency_ns, | |
3c2777fd VS |
1524 | &planec_wm, &cursorc_wm)) |
1525 | enabled |= 1 << PIPE_C; | |
1526 | ||
1527 | if (single_plane_enabled(enabled) && | |
1528 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1529 | sr_latency_ns, | |
1530 | &valleyview_wm_info, | |
1531 | &valleyview_cursor_wm_info, | |
1532 | &plane_sr, &ignore_cursor_sr) && | |
1533 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1534 | 2*sr_latency_ns, | |
1535 | &valleyview_wm_info, | |
1536 | &valleyview_cursor_wm_info, | |
1537 | &ignore_plane_sr, &cursor_sr)) { | |
1538 | cxsr_enabled = true; | |
1539 | } else { | |
1540 | cxsr_enabled = false; | |
1541 | intel_set_memory_cxsr(dev_priv, false); | |
1542 | plane_sr = cursor_sr = 0; | |
1543 | } | |
1544 | ||
1545 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " | |
1546 | "B: plane=%d, cursor=%d, C: plane=%d, cursor=%d, " | |
1547 | "SR: plane=%d, cursor=%d\n", | |
1548 | planea_wm, cursora_wm, | |
1549 | planeb_wm, cursorb_wm, | |
1550 | planec_wm, cursorc_wm, | |
1551 | plane_sr, cursor_sr); | |
1552 | ||
1553 | I915_WRITE(DSPFW1, | |
1554 | (plane_sr << DSPFW_SR_SHIFT) | | |
1555 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1556 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
1557 | (planea_wm << DSPFW_PLANEA_SHIFT)); | |
1558 | I915_WRITE(DSPFW2, | |
1559 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | | |
1560 | (cursora_wm << DSPFW_CURSORA_SHIFT)); | |
1561 | I915_WRITE(DSPFW3, | |
1562 | (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) | | |
1563 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
1564 | I915_WRITE(DSPFW9_CHV, | |
1565 | (I915_READ(DSPFW9_CHV) & ~(DSPFW_PLANEC_MASK | | |
1566 | DSPFW_CURSORC_MASK)) | | |
1567 | (planec_wm << DSPFW_PLANEC_SHIFT) | | |
1568 | (cursorc_wm << DSPFW_CURSORC_SHIFT)); | |
1569 | ||
1570 | if (cxsr_enabled) | |
1571 | intel_set_memory_cxsr(dev_priv, true); | |
1572 | } | |
1573 | ||
01e184cc GB |
1574 | static void valleyview_update_sprite_wm(struct drm_plane *plane, |
1575 | struct drm_crtc *crtc, | |
1576 | uint32_t sprite_width, | |
1577 | uint32_t sprite_height, | |
1578 | int pixel_size, | |
1579 | bool enabled, bool scaled) | |
1580 | { | |
1581 | struct drm_device *dev = crtc->dev; | |
1582 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1583 | int pipe = to_intel_plane(plane)->pipe; | |
1584 | int sprite = to_intel_plane(plane)->plane; | |
1585 | int drain_latency; | |
1586 | int plane_prec; | |
1587 | int sprite_dl; | |
1588 | int prec_mult; | |
5e56ba45 RV |
1589 | const int high_precision = IS_CHERRYVIEW(dev) ? |
1590 | DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_64; | |
01e184cc | 1591 | |
5e56ba45 | 1592 | sprite_dl = I915_READ(VLV_DDL(pipe)) & ~(DDL_SPRITE_PRECISION_HIGH(sprite) | |
01e184cc GB |
1593 | (DRAIN_LATENCY_MASK << DDL_SPRITE_SHIFT(sprite))); |
1594 | ||
1595 | if (enabled && vlv_compute_drain_latency(crtc, pixel_size, &prec_mult, | |
1596 | &drain_latency)) { | |
5e56ba45 RV |
1597 | plane_prec = (prec_mult == high_precision) ? |
1598 | DDL_SPRITE_PRECISION_HIGH(sprite) : | |
1599 | DDL_SPRITE_PRECISION_LOW(sprite); | |
01e184cc GB |
1600 | sprite_dl |= plane_prec | |
1601 | (drain_latency << DDL_SPRITE_SHIFT(sprite)); | |
1602 | } | |
1603 | ||
1604 | I915_WRITE(VLV_DDL(pipe), sprite_dl); | |
1605 | } | |
1606 | ||
46ba614c | 1607 | static void g4x_update_wm(struct drm_crtc *crtc) |
b445e3b0 | 1608 | { |
46ba614c | 1609 | struct drm_device *dev = crtc->dev; |
b445e3b0 ED |
1610 | static const int sr_latency_ns = 12000; |
1611 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1612 | int planea_wm, planeb_wm, cursora_wm, cursorb_wm; | |
1613 | int plane_sr, cursor_sr; | |
1614 | unsigned int enabled = 0; | |
9858425c | 1615 | bool cxsr_enabled; |
b445e3b0 | 1616 | |
51cea1f4 | 1617 | if (g4x_compute_wm0(dev, PIPE_A, |
5aef6003 CW |
1618 | &g4x_wm_info, pessimal_latency_ns, |
1619 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1620 | &planea_wm, &cursora_wm)) |
51cea1f4 | 1621 | enabled |= 1 << PIPE_A; |
b445e3b0 | 1622 | |
51cea1f4 | 1623 | if (g4x_compute_wm0(dev, PIPE_B, |
5aef6003 CW |
1624 | &g4x_wm_info, pessimal_latency_ns, |
1625 | &g4x_cursor_wm_info, pessimal_latency_ns, | |
b445e3b0 | 1626 | &planeb_wm, &cursorb_wm)) |
51cea1f4 | 1627 | enabled |= 1 << PIPE_B; |
b445e3b0 | 1628 | |
b445e3b0 ED |
1629 | if (single_plane_enabled(enabled) && |
1630 | g4x_compute_srwm(dev, ffs(enabled) - 1, | |
1631 | sr_latency_ns, | |
1632 | &g4x_wm_info, | |
1633 | &g4x_cursor_wm_info, | |
52bd02d8 | 1634 | &plane_sr, &cursor_sr)) { |
9858425c | 1635 | cxsr_enabled = true; |
52bd02d8 | 1636 | } else { |
9858425c | 1637 | cxsr_enabled = false; |
5209b1f4 | 1638 | intel_set_memory_cxsr(dev_priv, false); |
52bd02d8 CW |
1639 | plane_sr = cursor_sr = 0; |
1640 | } | |
b445e3b0 | 1641 | |
a5043453 VS |
1642 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, " |
1643 | "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n", | |
b445e3b0 ED |
1644 | planea_wm, cursora_wm, |
1645 | planeb_wm, cursorb_wm, | |
1646 | plane_sr, cursor_sr); | |
1647 | ||
1648 | I915_WRITE(DSPFW1, | |
1649 | (plane_sr << DSPFW_SR_SHIFT) | | |
1650 | (cursorb_wm << DSPFW_CURSORB_SHIFT) | | |
1651 | (planeb_wm << DSPFW_PLANEB_SHIFT) | | |
0a560674 | 1652 | (planea_wm << DSPFW_PLANEA_SHIFT)); |
b445e3b0 | 1653 | I915_WRITE(DSPFW2, |
8c919b28 | 1654 | (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) | |
b445e3b0 ED |
1655 | (cursora_wm << DSPFW_CURSORA_SHIFT)); |
1656 | /* HPLL off in SR has some issues on G4x... disable it */ | |
1657 | I915_WRITE(DSPFW3, | |
8c919b28 | 1658 | (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) | |
b445e3b0 | 1659 | (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); |
9858425c ID |
1660 | |
1661 | if (cxsr_enabled) | |
1662 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1663 | } |
1664 | ||
46ba614c | 1665 | static void i965_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1666 | { |
46ba614c | 1667 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1668 | struct drm_i915_private *dev_priv = dev->dev_private; |
1669 | struct drm_crtc *crtc; | |
1670 | int srwm = 1; | |
1671 | int cursor_sr = 16; | |
9858425c | 1672 | bool cxsr_enabled; |
b445e3b0 ED |
1673 | |
1674 | /* Calc sr entries for one plane configs */ | |
1675 | crtc = single_enabled_crtc(dev); | |
1676 | if (crtc) { | |
1677 | /* self-refresh has much higher latency */ | |
1678 | static const int sr_latency_ns = 12000; | |
4fe8590a VS |
1679 | const struct drm_display_mode *adjusted_mode = |
1680 | &to_intel_crtc(crtc)->config.adjusted_mode; | |
241bfc38 | 1681 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1682 | int htotal = adjusted_mode->crtc_htotal; |
37327abd | 1683 | int hdisplay = to_intel_crtc(crtc)->config.pipe_src_w; |
f4510a27 | 1684 | int pixel_size = crtc->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1685 | unsigned long line_time_us; |
1686 | int entries; | |
1687 | ||
922044c9 | 1688 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1689 | |
1690 | /* Use ns/us then divide to preserve precision */ | |
1691 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1692 | pixel_size * hdisplay; | |
1693 | entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE); | |
1694 | srwm = I965_FIFO_SIZE - entries; | |
1695 | if (srwm < 0) | |
1696 | srwm = 1; | |
1697 | srwm &= 0x1ff; | |
1698 | DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n", | |
1699 | entries, srwm); | |
1700 | ||
1701 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
7bb836dd | 1702 | pixel_size * to_intel_crtc(crtc)->cursor_width; |
b445e3b0 ED |
1703 | entries = DIV_ROUND_UP(entries, |
1704 | i965_cursor_wm_info.cacheline_size); | |
1705 | cursor_sr = i965_cursor_wm_info.fifo_size - | |
1706 | (entries + i965_cursor_wm_info.guard_size); | |
1707 | ||
1708 | if (cursor_sr > i965_cursor_wm_info.max_wm) | |
1709 | cursor_sr = i965_cursor_wm_info.max_wm; | |
1710 | ||
1711 | DRM_DEBUG_KMS("self-refresh watermark: display plane %d " | |
1712 | "cursor %d\n", srwm, cursor_sr); | |
1713 | ||
9858425c | 1714 | cxsr_enabled = true; |
b445e3b0 | 1715 | } else { |
9858425c | 1716 | cxsr_enabled = false; |
b445e3b0 | 1717 | /* Turn off self refresh if both pipes are enabled */ |
5209b1f4 | 1718 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1719 | } |
1720 | ||
1721 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n", | |
1722 | srwm); | |
1723 | ||
1724 | /* 965 has limitations... */ | |
1725 | I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) | | |
0a560674 VS |
1726 | (8 << DSPFW_CURSORB_SHIFT) | |
1727 | (8 << DSPFW_PLANEB_SHIFT) | | |
1728 | (8 << DSPFW_PLANEA_SHIFT)); | |
1729 | I915_WRITE(DSPFW2, (8 << DSPFW_CURSORA_SHIFT) | | |
1730 | (8 << DSPFW_PLANEC_SHIFT_OLD)); | |
b445e3b0 ED |
1731 | /* update cursor SR watermark */ |
1732 | I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT)); | |
9858425c ID |
1733 | |
1734 | if (cxsr_enabled) | |
1735 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1736 | } |
1737 | ||
46ba614c | 1738 | static void i9xx_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1739 | { |
46ba614c | 1740 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1741 | struct drm_i915_private *dev_priv = dev->dev_private; |
1742 | const struct intel_watermark_params *wm_info; | |
1743 | uint32_t fwater_lo; | |
1744 | uint32_t fwater_hi; | |
1745 | int cwm, srwm = 1; | |
1746 | int fifo_size; | |
1747 | int planea_wm, planeb_wm; | |
1748 | struct drm_crtc *crtc, *enabled = NULL; | |
1749 | ||
1750 | if (IS_I945GM(dev)) | |
1751 | wm_info = &i945_wm_info; | |
1752 | else if (!IS_GEN2(dev)) | |
1753 | wm_info = &i915_wm_info; | |
1754 | else | |
9d539105 | 1755 | wm_info = &i830_a_wm_info; |
b445e3b0 ED |
1756 | |
1757 | fifo_size = dev_priv->display.get_fifo_size(dev, 0); | |
1758 | crtc = intel_get_crtc_for_plane(dev, 0); | |
3490ea5d | 1759 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1760 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1761 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1762 | if (IS_GEN2(dev)) |
1763 | cpp = 4; | |
1764 | ||
241bfc38 DL |
1765 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1766 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1767 | wm_info, fifo_size, cpp, |
5aef6003 | 1768 | pessimal_latency_ns); |
b445e3b0 | 1769 | enabled = crtc; |
9d539105 | 1770 | } else { |
b445e3b0 | 1771 | planea_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1772 | if (planea_wm > (long)wm_info->max_wm) |
1773 | planea_wm = wm_info->max_wm; | |
1774 | } | |
1775 | ||
1776 | if (IS_GEN2(dev)) | |
1777 | wm_info = &i830_bc_wm_info; | |
b445e3b0 ED |
1778 | |
1779 | fifo_size = dev_priv->display.get_fifo_size(dev, 1); | |
1780 | crtc = intel_get_crtc_for_plane(dev, 1); | |
3490ea5d | 1781 | if (intel_crtc_active(crtc)) { |
241bfc38 | 1782 | const struct drm_display_mode *adjusted_mode; |
f4510a27 | 1783 | int cpp = crtc->primary->fb->bits_per_pixel / 8; |
b9e0bda3 CW |
1784 | if (IS_GEN2(dev)) |
1785 | cpp = 4; | |
1786 | ||
241bfc38 DL |
1787 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1788 | planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
b9e0bda3 | 1789 | wm_info, fifo_size, cpp, |
5aef6003 | 1790 | pessimal_latency_ns); |
b445e3b0 ED |
1791 | if (enabled == NULL) |
1792 | enabled = crtc; | |
1793 | else | |
1794 | enabled = NULL; | |
9d539105 | 1795 | } else { |
b445e3b0 | 1796 | planeb_wm = fifo_size - wm_info->guard_size; |
9d539105 VS |
1797 | if (planeb_wm > (long)wm_info->max_wm) |
1798 | planeb_wm = wm_info->max_wm; | |
1799 | } | |
b445e3b0 ED |
1800 | |
1801 | DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm); | |
1802 | ||
2ab1bc9d | 1803 | if (IS_I915GM(dev) && enabled) { |
2ff8fde1 | 1804 | struct drm_i915_gem_object *obj; |
2ab1bc9d | 1805 | |
2ff8fde1 | 1806 | obj = intel_fb_obj(enabled->primary->fb); |
2ab1bc9d DV |
1807 | |
1808 | /* self-refresh seems busted with untiled */ | |
2ff8fde1 | 1809 | if (obj->tiling_mode == I915_TILING_NONE) |
2ab1bc9d DV |
1810 | enabled = NULL; |
1811 | } | |
1812 | ||
b445e3b0 ED |
1813 | /* |
1814 | * Overlay gets an aggressive default since video jitter is bad. | |
1815 | */ | |
1816 | cwm = 2; | |
1817 | ||
1818 | /* Play safe and disable self-refresh before adjusting watermarks. */ | |
5209b1f4 | 1819 | intel_set_memory_cxsr(dev_priv, false); |
b445e3b0 ED |
1820 | |
1821 | /* Calc sr entries for one plane configs */ | |
1822 | if (HAS_FW_BLC(dev) && enabled) { | |
1823 | /* self-refresh has much higher latency */ | |
1824 | static const int sr_latency_ns = 6000; | |
4fe8590a VS |
1825 | const struct drm_display_mode *adjusted_mode = |
1826 | &to_intel_crtc(enabled)->config.adjusted_mode; | |
241bfc38 | 1827 | int clock = adjusted_mode->crtc_clock; |
fec8cba3 | 1828 | int htotal = adjusted_mode->crtc_htotal; |
f727b490 | 1829 | int hdisplay = to_intel_crtc(enabled)->config.pipe_src_w; |
f4510a27 | 1830 | int pixel_size = enabled->primary->fb->bits_per_pixel / 8; |
b445e3b0 ED |
1831 | unsigned long line_time_us; |
1832 | int entries; | |
1833 | ||
922044c9 | 1834 | line_time_us = max(htotal * 1000 / clock, 1); |
b445e3b0 ED |
1835 | |
1836 | /* Use ns/us then divide to preserve precision */ | |
1837 | entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) * | |
1838 | pixel_size * hdisplay; | |
1839 | entries = DIV_ROUND_UP(entries, wm_info->cacheline_size); | |
1840 | DRM_DEBUG_KMS("self-refresh entries: %d\n", entries); | |
1841 | srwm = wm_info->fifo_size - entries; | |
1842 | if (srwm < 0) | |
1843 | srwm = 1; | |
1844 | ||
1845 | if (IS_I945G(dev) || IS_I945GM(dev)) | |
1846 | I915_WRITE(FW_BLC_SELF, | |
1847 | FW_BLC_SELF_FIFO_MASK | (srwm & 0xff)); | |
1848 | else if (IS_I915GM(dev)) | |
1849 | I915_WRITE(FW_BLC_SELF, srwm & 0x3f); | |
1850 | } | |
1851 | ||
1852 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n", | |
1853 | planea_wm, planeb_wm, cwm, srwm); | |
1854 | ||
1855 | fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f); | |
1856 | fwater_hi = (cwm & 0x1f); | |
1857 | ||
1858 | /* Set request length to 8 cachelines per fetch */ | |
1859 | fwater_lo = fwater_lo | (1 << 24) | (1 << 8); | |
1860 | fwater_hi = fwater_hi | (1 << 8); | |
1861 | ||
1862 | I915_WRITE(FW_BLC, fwater_lo); | |
1863 | I915_WRITE(FW_BLC2, fwater_hi); | |
1864 | ||
5209b1f4 ID |
1865 | if (enabled) |
1866 | intel_set_memory_cxsr(dev_priv, true); | |
b445e3b0 ED |
1867 | } |
1868 | ||
feb56b93 | 1869 | static void i845_update_wm(struct drm_crtc *unused_crtc) |
b445e3b0 | 1870 | { |
46ba614c | 1871 | struct drm_device *dev = unused_crtc->dev; |
b445e3b0 ED |
1872 | struct drm_i915_private *dev_priv = dev->dev_private; |
1873 | struct drm_crtc *crtc; | |
241bfc38 | 1874 | const struct drm_display_mode *adjusted_mode; |
b445e3b0 ED |
1875 | uint32_t fwater_lo; |
1876 | int planea_wm; | |
1877 | ||
1878 | crtc = single_enabled_crtc(dev); | |
1879 | if (crtc == NULL) | |
1880 | return; | |
1881 | ||
241bfc38 DL |
1882 | adjusted_mode = &to_intel_crtc(crtc)->config.adjusted_mode; |
1883 | planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock, | |
feb56b93 | 1884 | &i845_wm_info, |
b445e3b0 | 1885 | dev_priv->display.get_fifo_size(dev, 0), |
5aef6003 | 1886 | 4, pessimal_latency_ns); |
b445e3b0 ED |
1887 | fwater_lo = I915_READ(FW_BLC) & ~0xfff; |
1888 | fwater_lo |= (3<<8) | planea_wm; | |
1889 | ||
1890 | DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm); | |
1891 | ||
1892 | I915_WRITE(FW_BLC, fwater_lo); | |
1893 | } | |
1894 | ||
3658729a VS |
1895 | static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev, |
1896 | struct drm_crtc *crtc) | |
801bcfff PZ |
1897 | { |
1898 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
fd4daa9c | 1899 | uint32_t pixel_rate; |
801bcfff | 1900 | |
241bfc38 | 1901 | pixel_rate = intel_crtc->config.adjusted_mode.crtc_clock; |
801bcfff PZ |
1902 | |
1903 | /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to | |
1904 | * adjust the pixel_rate here. */ | |
1905 | ||
fd4daa9c | 1906 | if (intel_crtc->config.pch_pfit.enabled) { |
801bcfff | 1907 | uint64_t pipe_w, pipe_h, pfit_w, pfit_h; |
fd4daa9c | 1908 | uint32_t pfit_size = intel_crtc->config.pch_pfit.size; |
801bcfff | 1909 | |
37327abd VS |
1910 | pipe_w = intel_crtc->config.pipe_src_w; |
1911 | pipe_h = intel_crtc->config.pipe_src_h; | |
801bcfff PZ |
1912 | pfit_w = (pfit_size >> 16) & 0xFFFF; |
1913 | pfit_h = pfit_size & 0xFFFF; | |
1914 | if (pipe_w < pfit_w) | |
1915 | pipe_w = pfit_w; | |
1916 | if (pipe_h < pfit_h) | |
1917 | pipe_h = pfit_h; | |
1918 | ||
1919 | pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h, | |
1920 | pfit_w * pfit_h); | |
1921 | } | |
1922 | ||
1923 | return pixel_rate; | |
1924 | } | |
1925 | ||
37126462 | 1926 | /* latency must be in 0.1us units. */ |
23297044 | 1927 | static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, |
801bcfff PZ |
1928 | uint32_t latency) |
1929 | { | |
1930 | uint64_t ret; | |
1931 | ||
3312ba65 VS |
1932 | if (WARN(latency == 0, "Latency value missing\n")) |
1933 | return UINT_MAX; | |
1934 | ||
801bcfff PZ |
1935 | ret = (uint64_t) pixel_rate * bytes_per_pixel * latency; |
1936 | ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2; | |
1937 | ||
1938 | return ret; | |
1939 | } | |
1940 | ||
37126462 | 1941 | /* latency must be in 0.1us units. */ |
23297044 | 1942 | static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, |
801bcfff PZ |
1943 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, |
1944 | uint32_t latency) | |
1945 | { | |
1946 | uint32_t ret; | |
1947 | ||
3312ba65 VS |
1948 | if (WARN(latency == 0, "Latency value missing\n")) |
1949 | return UINT_MAX; | |
1950 | ||
801bcfff PZ |
1951 | ret = (latency * pixel_rate) / (pipe_htotal * 10000); |
1952 | ret = (ret + 1) * horiz_pixels * bytes_per_pixel; | |
1953 | ret = DIV_ROUND_UP(ret, 64) + 2; | |
1954 | return ret; | |
1955 | } | |
1956 | ||
23297044 | 1957 | static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels, |
cca32e9a PZ |
1958 | uint8_t bytes_per_pixel) |
1959 | { | |
1960 | return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2; | |
1961 | } | |
1962 | ||
2ac96d2a PB |
1963 | struct skl_pipe_wm_parameters { |
1964 | bool active; | |
1965 | uint32_t pipe_htotal; | |
1966 | uint32_t pixel_rate; /* in KHz */ | |
1967 | struct intel_plane_wm_parameters plane[I915_MAX_PLANES]; | |
1968 | struct intel_plane_wm_parameters cursor; | |
1969 | }; | |
1970 | ||
820c1980 | 1971 | struct ilk_pipe_wm_parameters { |
801bcfff | 1972 | bool active; |
801bcfff PZ |
1973 | uint32_t pipe_htotal; |
1974 | uint32_t pixel_rate; | |
c35426d2 VS |
1975 | struct intel_plane_wm_parameters pri; |
1976 | struct intel_plane_wm_parameters spr; | |
1977 | struct intel_plane_wm_parameters cur; | |
801bcfff PZ |
1978 | }; |
1979 | ||
820c1980 | 1980 | struct ilk_wm_maximums { |
cca32e9a PZ |
1981 | uint16_t pri; |
1982 | uint16_t spr; | |
1983 | uint16_t cur; | |
1984 | uint16_t fbc; | |
1985 | }; | |
1986 | ||
240264f4 VS |
1987 | /* used in computing the new watermarks state */ |
1988 | struct intel_wm_config { | |
1989 | unsigned int num_pipes_active; | |
1990 | bool sprites_enabled; | |
1991 | bool sprites_scaled; | |
240264f4 VS |
1992 | }; |
1993 | ||
37126462 VS |
1994 | /* |
1995 | * For both WM_PIPE and WM_LP. | |
1996 | * mem_value must be in 0.1us units. | |
1997 | */ | |
820c1980 | 1998 | static uint32_t ilk_compute_pri_wm(const struct ilk_pipe_wm_parameters *params, |
cca32e9a PZ |
1999 | uint32_t mem_value, |
2000 | bool is_lp) | |
801bcfff | 2001 | { |
cca32e9a PZ |
2002 | uint32_t method1, method2; |
2003 | ||
c35426d2 | 2004 | if (!params->active || !params->pri.enabled) |
801bcfff PZ |
2005 | return 0; |
2006 | ||
23297044 | 2007 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 2008 | params->pri.bytes_per_pixel, |
cca32e9a PZ |
2009 | mem_value); |
2010 | ||
2011 | if (!is_lp) | |
2012 | return method1; | |
2013 | ||
23297044 | 2014 | method2 = ilk_wm_method2(params->pixel_rate, |
cca32e9a | 2015 | params->pipe_htotal, |
c35426d2 VS |
2016 | params->pri.horiz_pixels, |
2017 | params->pri.bytes_per_pixel, | |
cca32e9a PZ |
2018 | mem_value); |
2019 | ||
2020 | return min(method1, method2); | |
801bcfff PZ |
2021 | } |
2022 | ||
37126462 VS |
2023 | /* |
2024 | * For both WM_PIPE and WM_LP. | |
2025 | * mem_value must be in 0.1us units. | |
2026 | */ | |
820c1980 | 2027 | static uint32_t ilk_compute_spr_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
2028 | uint32_t mem_value) |
2029 | { | |
2030 | uint32_t method1, method2; | |
2031 | ||
c35426d2 | 2032 | if (!params->active || !params->spr.enabled) |
801bcfff PZ |
2033 | return 0; |
2034 | ||
23297044 | 2035 | method1 = ilk_wm_method1(params->pixel_rate, |
c35426d2 | 2036 | params->spr.bytes_per_pixel, |
801bcfff | 2037 | mem_value); |
23297044 | 2038 | method2 = ilk_wm_method2(params->pixel_rate, |
801bcfff | 2039 | params->pipe_htotal, |
c35426d2 VS |
2040 | params->spr.horiz_pixels, |
2041 | params->spr.bytes_per_pixel, | |
801bcfff PZ |
2042 | mem_value); |
2043 | return min(method1, method2); | |
2044 | } | |
2045 | ||
37126462 VS |
2046 | /* |
2047 | * For both WM_PIPE and WM_LP. | |
2048 | * mem_value must be in 0.1us units. | |
2049 | */ | |
820c1980 | 2050 | static uint32_t ilk_compute_cur_wm(const struct ilk_pipe_wm_parameters *params, |
801bcfff PZ |
2051 | uint32_t mem_value) |
2052 | { | |
c35426d2 | 2053 | if (!params->active || !params->cur.enabled) |
801bcfff PZ |
2054 | return 0; |
2055 | ||
23297044 | 2056 | return ilk_wm_method2(params->pixel_rate, |
801bcfff | 2057 | params->pipe_htotal, |
c35426d2 VS |
2058 | params->cur.horiz_pixels, |
2059 | params->cur.bytes_per_pixel, | |
801bcfff PZ |
2060 | mem_value); |
2061 | } | |
2062 | ||
cca32e9a | 2063 | /* Only for WM_LP. */ |
820c1980 | 2064 | static uint32_t ilk_compute_fbc_wm(const struct ilk_pipe_wm_parameters *params, |
1fda9882 | 2065 | uint32_t pri_val) |
cca32e9a | 2066 | { |
c35426d2 | 2067 | if (!params->active || !params->pri.enabled) |
cca32e9a PZ |
2068 | return 0; |
2069 | ||
23297044 | 2070 | return ilk_wm_fbc(pri_val, |
c35426d2 VS |
2071 | params->pri.horiz_pixels, |
2072 | params->pri.bytes_per_pixel); | |
cca32e9a PZ |
2073 | } |
2074 | ||
158ae64f VS |
2075 | static unsigned int ilk_display_fifo_size(const struct drm_device *dev) |
2076 | { | |
416f4727 VS |
2077 | if (INTEL_INFO(dev)->gen >= 8) |
2078 | return 3072; | |
2079 | else if (INTEL_INFO(dev)->gen >= 7) | |
158ae64f VS |
2080 | return 768; |
2081 | else | |
2082 | return 512; | |
2083 | } | |
2084 | ||
4e975081 VS |
2085 | static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev, |
2086 | int level, bool is_sprite) | |
2087 | { | |
2088 | if (INTEL_INFO(dev)->gen >= 8) | |
2089 | /* BDW primary/sprite plane watermarks */ | |
2090 | return level == 0 ? 255 : 2047; | |
2091 | else if (INTEL_INFO(dev)->gen >= 7) | |
2092 | /* IVB/HSW primary/sprite plane watermarks */ | |
2093 | return level == 0 ? 127 : 1023; | |
2094 | else if (!is_sprite) | |
2095 | /* ILK/SNB primary plane watermarks */ | |
2096 | return level == 0 ? 127 : 511; | |
2097 | else | |
2098 | /* ILK/SNB sprite plane watermarks */ | |
2099 | return level == 0 ? 63 : 255; | |
2100 | } | |
2101 | ||
2102 | static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev, | |
2103 | int level) | |
2104 | { | |
2105 | if (INTEL_INFO(dev)->gen >= 7) | |
2106 | return level == 0 ? 63 : 255; | |
2107 | else | |
2108 | return level == 0 ? 31 : 63; | |
2109 | } | |
2110 | ||
2111 | static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev) | |
2112 | { | |
2113 | if (INTEL_INFO(dev)->gen >= 8) | |
2114 | return 31; | |
2115 | else | |
2116 | return 15; | |
2117 | } | |
2118 | ||
158ae64f VS |
2119 | /* Calculate the maximum primary/sprite plane watermark */ |
2120 | static unsigned int ilk_plane_wm_max(const struct drm_device *dev, | |
2121 | int level, | |
240264f4 | 2122 | const struct intel_wm_config *config, |
158ae64f VS |
2123 | enum intel_ddb_partitioning ddb_partitioning, |
2124 | bool is_sprite) | |
2125 | { | |
2126 | unsigned int fifo_size = ilk_display_fifo_size(dev); | |
158ae64f VS |
2127 | |
2128 | /* if sprites aren't enabled, sprites get nothing */ | |
240264f4 | 2129 | if (is_sprite && !config->sprites_enabled) |
158ae64f VS |
2130 | return 0; |
2131 | ||
2132 | /* HSW allows LP1+ watermarks even with multiple pipes */ | |
240264f4 | 2133 | if (level == 0 || config->num_pipes_active > 1) { |
158ae64f VS |
2134 | fifo_size /= INTEL_INFO(dev)->num_pipes; |
2135 | ||
2136 | /* | |
2137 | * For some reason the non self refresh | |
2138 | * FIFO size is only half of the self | |
2139 | * refresh FIFO size on ILK/SNB. | |
2140 | */ | |
2141 | if (INTEL_INFO(dev)->gen <= 6) | |
2142 | fifo_size /= 2; | |
2143 | } | |
2144 | ||
240264f4 | 2145 | if (config->sprites_enabled) { |
158ae64f VS |
2146 | /* level 0 is always calculated with 1:1 split */ |
2147 | if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) { | |
2148 | if (is_sprite) | |
2149 | fifo_size *= 5; | |
2150 | fifo_size /= 6; | |
2151 | } else { | |
2152 | fifo_size /= 2; | |
2153 | } | |
2154 | } | |
2155 | ||
2156 | /* clamp to max that the registers can hold */ | |
4e975081 | 2157 | return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite)); |
158ae64f VS |
2158 | } |
2159 | ||
2160 | /* Calculate the maximum cursor plane watermark */ | |
2161 | static unsigned int ilk_cursor_wm_max(const struct drm_device *dev, | |
240264f4 VS |
2162 | int level, |
2163 | const struct intel_wm_config *config) | |
158ae64f VS |
2164 | { |
2165 | /* HSW LP1+ watermarks w/ multiple pipes */ | |
240264f4 | 2166 | if (level > 0 && config->num_pipes_active > 1) |
158ae64f VS |
2167 | return 64; |
2168 | ||
2169 | /* otherwise just report max that registers can hold */ | |
4e975081 | 2170 | return ilk_cursor_wm_reg_max(dev, level); |
158ae64f VS |
2171 | } |
2172 | ||
d34ff9c6 | 2173 | static void ilk_compute_wm_maximums(const struct drm_device *dev, |
34982fe1 VS |
2174 | int level, |
2175 | const struct intel_wm_config *config, | |
2176 | enum intel_ddb_partitioning ddb_partitioning, | |
820c1980 | 2177 | struct ilk_wm_maximums *max) |
158ae64f | 2178 | { |
240264f4 VS |
2179 | max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false); |
2180 | max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true); | |
2181 | max->cur = ilk_cursor_wm_max(dev, level, config); | |
4e975081 | 2182 | max->fbc = ilk_fbc_wm_reg_max(dev); |
158ae64f VS |
2183 | } |
2184 | ||
a3cb4048 VS |
2185 | static void ilk_compute_wm_reg_maximums(struct drm_device *dev, |
2186 | int level, | |
2187 | struct ilk_wm_maximums *max) | |
2188 | { | |
2189 | max->pri = ilk_plane_wm_reg_max(dev, level, false); | |
2190 | max->spr = ilk_plane_wm_reg_max(dev, level, true); | |
2191 | max->cur = ilk_cursor_wm_reg_max(dev, level); | |
2192 | max->fbc = ilk_fbc_wm_reg_max(dev); | |
2193 | } | |
2194 | ||
d9395655 | 2195 | static bool ilk_validate_wm_level(int level, |
820c1980 | 2196 | const struct ilk_wm_maximums *max, |
d9395655 | 2197 | struct intel_wm_level *result) |
a9786a11 VS |
2198 | { |
2199 | bool ret; | |
2200 | ||
2201 | /* already determined to be invalid? */ | |
2202 | if (!result->enable) | |
2203 | return false; | |
2204 | ||
2205 | result->enable = result->pri_val <= max->pri && | |
2206 | result->spr_val <= max->spr && | |
2207 | result->cur_val <= max->cur; | |
2208 | ||
2209 | ret = result->enable; | |
2210 | ||
2211 | /* | |
2212 | * HACK until we can pre-compute everything, | |
2213 | * and thus fail gracefully if LP0 watermarks | |
2214 | * are exceeded... | |
2215 | */ | |
2216 | if (level == 0 && !result->enable) { | |
2217 | if (result->pri_val > max->pri) | |
2218 | DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n", | |
2219 | level, result->pri_val, max->pri); | |
2220 | if (result->spr_val > max->spr) | |
2221 | DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n", | |
2222 | level, result->spr_val, max->spr); | |
2223 | if (result->cur_val > max->cur) | |
2224 | DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n", | |
2225 | level, result->cur_val, max->cur); | |
2226 | ||
2227 | result->pri_val = min_t(uint32_t, result->pri_val, max->pri); | |
2228 | result->spr_val = min_t(uint32_t, result->spr_val, max->spr); | |
2229 | result->cur_val = min_t(uint32_t, result->cur_val, max->cur); | |
2230 | result->enable = true; | |
2231 | } | |
2232 | ||
a9786a11 VS |
2233 | return ret; |
2234 | } | |
2235 | ||
d34ff9c6 | 2236 | static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv, |
6f5ddd17 | 2237 | int level, |
820c1980 | 2238 | const struct ilk_pipe_wm_parameters *p, |
1fd527cc | 2239 | struct intel_wm_level *result) |
6f5ddd17 VS |
2240 | { |
2241 | uint16_t pri_latency = dev_priv->wm.pri_latency[level]; | |
2242 | uint16_t spr_latency = dev_priv->wm.spr_latency[level]; | |
2243 | uint16_t cur_latency = dev_priv->wm.cur_latency[level]; | |
2244 | ||
2245 | /* WM1+ latency values stored in 0.5us units */ | |
2246 | if (level > 0) { | |
2247 | pri_latency *= 5; | |
2248 | spr_latency *= 5; | |
2249 | cur_latency *= 5; | |
2250 | } | |
2251 | ||
2252 | result->pri_val = ilk_compute_pri_wm(p, pri_latency, level); | |
2253 | result->spr_val = ilk_compute_spr_wm(p, spr_latency); | |
2254 | result->cur_val = ilk_compute_cur_wm(p, cur_latency); | |
2255 | result->fbc_val = ilk_compute_fbc_wm(p, result->pri_val); | |
2256 | result->enable = true; | |
2257 | } | |
2258 | ||
801bcfff PZ |
2259 | static uint32_t |
2260 | hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc) | |
1f8eeabf ED |
2261 | { |
2262 | struct drm_i915_private *dev_priv = dev->dev_private; | |
1011d8c4 | 2263 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
1011d8c4 | 2264 | struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode; |
85a02deb | 2265 | u32 linetime, ips_linetime; |
1f8eeabf | 2266 | |
801bcfff PZ |
2267 | if (!intel_crtc_active(crtc)) |
2268 | return 0; | |
1011d8c4 | 2269 | |
1f8eeabf ED |
2270 | /* The WM are computed with base on how long it takes to fill a single |
2271 | * row at the given clock rate, multiplied by 8. | |
2272 | * */ | |
fec8cba3 JB |
2273 | linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, |
2274 | mode->crtc_clock); | |
2275 | ips_linetime = DIV_ROUND_CLOSEST(mode->crtc_htotal * 1000 * 8, | |
85a02deb | 2276 | intel_ddi_get_cdclk_freq(dev_priv)); |
1f8eeabf | 2277 | |
801bcfff PZ |
2278 | return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) | |
2279 | PIPE_WM_LINETIME_TIME(linetime); | |
1f8eeabf ED |
2280 | } |
2281 | ||
2af30a5c | 2282 | static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8]) |
12b134df VS |
2283 | { |
2284 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2285 | ||
2af30a5c PB |
2286 | if (IS_GEN9(dev)) { |
2287 | uint32_t val; | |
2288 | int ret; | |
367294be | 2289 | int level, max_level = ilk_wm_max_level(dev); |
2af30a5c PB |
2290 | |
2291 | /* read the first set of memory latencies[0:3] */ | |
2292 | val = 0; /* data0 to be programmed to 0 for first set */ | |
2293 | mutex_lock(&dev_priv->rps.hw_lock); | |
2294 | ret = sandybridge_pcode_read(dev_priv, | |
2295 | GEN9_PCODE_READ_MEM_LATENCY, | |
2296 | &val); | |
2297 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2298 | ||
2299 | if (ret) { | |
2300 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2301 | return; | |
2302 | } | |
2303 | ||
2304 | wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2305 | wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2306 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2307 | wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2308 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2309 | wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2310 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2311 | ||
2312 | /* read the second set of memory latencies[4:7] */ | |
2313 | val = 1; /* data0 to be programmed to 1 for second set */ | |
2314 | mutex_lock(&dev_priv->rps.hw_lock); | |
2315 | ret = sandybridge_pcode_read(dev_priv, | |
2316 | GEN9_PCODE_READ_MEM_LATENCY, | |
2317 | &val); | |
2318 | mutex_unlock(&dev_priv->rps.hw_lock); | |
2319 | if (ret) { | |
2320 | DRM_ERROR("SKL Mailbox read error = %d\n", ret); | |
2321 | return; | |
2322 | } | |
2323 | ||
2324 | wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK; | |
2325 | wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) & | |
2326 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2327 | wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) & | |
2328 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2329 | wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) & | |
2330 | GEN9_MEM_LATENCY_LEVEL_MASK; | |
2331 | ||
367294be VK |
2332 | /* |
2333 | * punit doesn't take into account the read latency so we need | |
2334 | * to add 2us to the various latency levels we retrieve from | |
2335 | * the punit. | |
2336 | * - W0 is a bit special in that it's the only level that | |
2337 | * can't be disabled if we want to have display working, so | |
2338 | * we always add 2us there. | |
2339 | * - For levels >=1, punit returns 0us latency when they are | |
2340 | * disabled, so we respect that and don't add 2us then | |
2341 | */ | |
2342 | wm[0] += 2; | |
2343 | for (level = 1; level <= max_level; level++) | |
2344 | if (wm[level] != 0) | |
2345 | wm[level] += 2; | |
2346 | ||
2af30a5c | 2347 | } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
12b134df VS |
2348 | uint64_t sskpd = I915_READ64(MCH_SSKPD); |
2349 | ||
2350 | wm[0] = (sskpd >> 56) & 0xFF; | |
2351 | if (wm[0] == 0) | |
2352 | wm[0] = sskpd & 0xF; | |
e5d5019e VS |
2353 | wm[1] = (sskpd >> 4) & 0xFF; |
2354 | wm[2] = (sskpd >> 12) & 0xFF; | |
2355 | wm[3] = (sskpd >> 20) & 0x1FF; | |
2356 | wm[4] = (sskpd >> 32) & 0x1FF; | |
63cf9a13 VS |
2357 | } else if (INTEL_INFO(dev)->gen >= 6) { |
2358 | uint32_t sskpd = I915_READ(MCH_SSKPD); | |
2359 | ||
2360 | wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK; | |
2361 | wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK; | |
2362 | wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK; | |
2363 | wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK; | |
3a88d0ac VS |
2364 | } else if (INTEL_INFO(dev)->gen >= 5) { |
2365 | uint32_t mltr = I915_READ(MLTR_ILK); | |
2366 | ||
2367 | /* ILK primary LP0 latency is 700 ns */ | |
2368 | wm[0] = 7; | |
2369 | wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK; | |
2370 | wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK; | |
12b134df VS |
2371 | } |
2372 | } | |
2373 | ||
53615a5e VS |
2374 | static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5]) |
2375 | { | |
2376 | /* ILK sprite LP0 latency is 1300 ns */ | |
2377 | if (INTEL_INFO(dev)->gen == 5) | |
2378 | wm[0] = 13; | |
2379 | } | |
2380 | ||
2381 | static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5]) | |
2382 | { | |
2383 | /* ILK cursor LP0 latency is 1300 ns */ | |
2384 | if (INTEL_INFO(dev)->gen == 5) | |
2385 | wm[0] = 13; | |
2386 | ||
2387 | /* WaDoubleCursorLP3Latency:ivb */ | |
2388 | if (IS_IVYBRIDGE(dev)) | |
2389 | wm[3] *= 2; | |
2390 | } | |
2391 | ||
546c81fd | 2392 | int ilk_wm_max_level(const struct drm_device *dev) |
26ec971e | 2393 | { |
26ec971e | 2394 | /* how many WM levels are we expecting */ |
2af30a5c PB |
2395 | if (IS_GEN9(dev)) |
2396 | return 7; | |
2397 | else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) | |
ad0d6dc4 | 2398 | return 4; |
26ec971e | 2399 | else if (INTEL_INFO(dev)->gen >= 6) |
ad0d6dc4 | 2400 | return 3; |
26ec971e | 2401 | else |
ad0d6dc4 VS |
2402 | return 2; |
2403 | } | |
7526ed79 | 2404 | |
ad0d6dc4 VS |
2405 | static void intel_print_wm_latency(struct drm_device *dev, |
2406 | const char *name, | |
2af30a5c | 2407 | const uint16_t wm[8]) |
ad0d6dc4 VS |
2408 | { |
2409 | int level, max_level = ilk_wm_max_level(dev); | |
26ec971e VS |
2410 | |
2411 | for (level = 0; level <= max_level; level++) { | |
2412 | unsigned int latency = wm[level]; | |
2413 | ||
2414 | if (latency == 0) { | |
2415 | DRM_ERROR("%s WM%d latency not provided\n", | |
2416 | name, level); | |
2417 | continue; | |
2418 | } | |
2419 | ||
2af30a5c PB |
2420 | /* |
2421 | * - latencies are in us on gen9. | |
2422 | * - before then, WM1+ latency values are in 0.5us units | |
2423 | */ | |
2424 | if (IS_GEN9(dev)) | |
2425 | latency *= 10; | |
2426 | else if (level > 0) | |
26ec971e VS |
2427 | latency *= 5; |
2428 | ||
2429 | DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n", | |
2430 | name, level, wm[level], | |
2431 | latency / 10, latency % 10); | |
2432 | } | |
2433 | } | |
2434 | ||
e95a2f75 VS |
2435 | static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv, |
2436 | uint16_t wm[5], uint16_t min) | |
2437 | { | |
2438 | int level, max_level = ilk_wm_max_level(dev_priv->dev); | |
2439 | ||
2440 | if (wm[0] >= min) | |
2441 | return false; | |
2442 | ||
2443 | wm[0] = max(wm[0], min); | |
2444 | for (level = 1; level <= max_level; level++) | |
2445 | wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5)); | |
2446 | ||
2447 | return true; | |
2448 | } | |
2449 | ||
2450 | static void snb_wm_latency_quirk(struct drm_device *dev) | |
2451 | { | |
2452 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2453 | bool changed; | |
2454 | ||
2455 | /* | |
2456 | * The BIOS provided WM memory latency values are often | |
2457 | * inadequate for high resolution displays. Adjust them. | |
2458 | */ | |
2459 | changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) | | |
2460 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) | | |
2461 | ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12); | |
2462 | ||
2463 | if (!changed) | |
2464 | return; | |
2465 | ||
2466 | DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n"); | |
2467 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2468 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2469 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
2470 | } | |
2471 | ||
fa50ad61 | 2472 | static void ilk_setup_wm_latency(struct drm_device *dev) |
53615a5e VS |
2473 | { |
2474 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2475 | ||
2476 | intel_read_wm_latency(dev, dev_priv->wm.pri_latency); | |
2477 | ||
2478 | memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency, | |
2479 | sizeof(dev_priv->wm.pri_latency)); | |
2480 | memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency, | |
2481 | sizeof(dev_priv->wm.pri_latency)); | |
2482 | ||
2483 | intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency); | |
2484 | intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency); | |
26ec971e VS |
2485 | |
2486 | intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency); | |
2487 | intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency); | |
2488 | intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency); | |
e95a2f75 VS |
2489 | |
2490 | if (IS_GEN6(dev)) | |
2491 | snb_wm_latency_quirk(dev); | |
53615a5e VS |
2492 | } |
2493 | ||
2af30a5c PB |
2494 | static void skl_setup_wm_latency(struct drm_device *dev) |
2495 | { | |
2496 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2497 | ||
2498 | intel_read_wm_latency(dev, dev_priv->wm.skl_latency); | |
2499 | intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency); | |
2500 | } | |
2501 | ||
820c1980 | 2502 | static void ilk_compute_wm_parameters(struct drm_crtc *crtc, |
2a44b76b | 2503 | struct ilk_pipe_wm_parameters *p) |
1011d8c4 | 2504 | { |
7c4a395f VS |
2505 | struct drm_device *dev = crtc->dev; |
2506 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
2507 | enum pipe pipe = intel_crtc->pipe; | |
7c4a395f | 2508 | struct drm_plane *plane; |
1011d8c4 | 2509 | |
2a44b76b VS |
2510 | if (!intel_crtc_active(crtc)) |
2511 | return; | |
801bcfff | 2512 | |
2a44b76b VS |
2513 | p->active = true; |
2514 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; | |
2515 | p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc); | |
2516 | p->pri.bytes_per_pixel = crtc->primary->fb->bits_per_pixel / 8; | |
2517 | p->cur.bytes_per_pixel = 4; | |
2518 | p->pri.horiz_pixels = intel_crtc->config.pipe_src_w; | |
2519 | p->cur.horiz_pixels = intel_crtc->cursor_width; | |
2520 | /* TODO: for now, assume primary and cursor planes are always enabled. */ | |
2521 | p->pri.enabled = true; | |
2522 | p->cur.enabled = true; | |
7c4a395f | 2523 | |
af2b653b | 2524 | drm_for_each_legacy_plane(plane, &dev->mode_config.plane_list) { |
801bcfff | 2525 | struct intel_plane *intel_plane = to_intel_plane(plane); |
801bcfff | 2526 | |
2a44b76b | 2527 | if (intel_plane->pipe == pipe) { |
7c4a395f | 2528 | p->spr = intel_plane->wm; |
2a44b76b VS |
2529 | break; |
2530 | } | |
2531 | } | |
2532 | } | |
2533 | ||
2534 | static void ilk_compute_wm_config(struct drm_device *dev, | |
2535 | struct intel_wm_config *config) | |
2536 | { | |
2537 | struct intel_crtc *intel_crtc; | |
2538 | ||
2539 | /* Compute the currently _active_ config */ | |
d3fcc808 | 2540 | for_each_intel_crtc(dev, intel_crtc) { |
2a44b76b | 2541 | const struct intel_pipe_wm *wm = &intel_crtc->wm.active; |
cca32e9a | 2542 | |
2a44b76b VS |
2543 | if (!wm->pipe_enabled) |
2544 | continue; | |
cca32e9a | 2545 | |
2a44b76b VS |
2546 | config->sprites_enabled |= wm->sprites_enabled; |
2547 | config->sprites_scaled |= wm->sprites_scaled; | |
2548 | config->num_pipes_active++; | |
cca32e9a | 2549 | } |
801bcfff PZ |
2550 | } |
2551 | ||
0b2ae6d7 VS |
2552 | /* Compute new watermarks for the pipe */ |
2553 | static bool intel_compute_pipe_wm(struct drm_crtc *crtc, | |
820c1980 | 2554 | const struct ilk_pipe_wm_parameters *params, |
0b2ae6d7 VS |
2555 | struct intel_pipe_wm *pipe_wm) |
2556 | { | |
2557 | struct drm_device *dev = crtc->dev; | |
d34ff9c6 | 2558 | const struct drm_i915_private *dev_priv = dev->dev_private; |
0b2ae6d7 VS |
2559 | int level, max_level = ilk_wm_max_level(dev); |
2560 | /* LP0 watermark maximums depend on this pipe alone */ | |
2561 | struct intel_wm_config config = { | |
2562 | .num_pipes_active = 1, | |
2563 | .sprites_enabled = params->spr.enabled, | |
2564 | .sprites_scaled = params->spr.scaled, | |
2565 | }; | |
820c1980 | 2566 | struct ilk_wm_maximums max; |
0b2ae6d7 | 2567 | |
2a44b76b VS |
2568 | pipe_wm->pipe_enabled = params->active; |
2569 | pipe_wm->sprites_enabled = params->spr.enabled; | |
2570 | pipe_wm->sprites_scaled = params->spr.scaled; | |
2571 | ||
7b39a0b7 VS |
2572 | /* ILK/SNB: LP2+ watermarks only w/o sprites */ |
2573 | if (INTEL_INFO(dev)->gen <= 6 && params->spr.enabled) | |
2574 | max_level = 1; | |
2575 | ||
2576 | /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */ | |
2577 | if (params->spr.scaled) | |
2578 | max_level = 0; | |
2579 | ||
a3cb4048 | 2580 | ilk_compute_wm_level(dev_priv, 0, params, &pipe_wm->wm[0]); |
0b2ae6d7 | 2581 | |
a42a5719 | 2582 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 2583 | pipe_wm->linetime = hsw_compute_linetime_wm(dev, crtc); |
0b2ae6d7 | 2584 | |
a3cb4048 VS |
2585 | /* LP0 watermarks always use 1/2 DDB partitioning */ |
2586 | ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max); | |
2587 | ||
0b2ae6d7 | 2588 | /* At least LP0 must be valid */ |
a3cb4048 VS |
2589 | if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) |
2590 | return false; | |
2591 | ||
2592 | ilk_compute_wm_reg_maximums(dev, 1, &max); | |
2593 | ||
2594 | for (level = 1; level <= max_level; level++) { | |
2595 | struct intel_wm_level wm = {}; | |
2596 | ||
2597 | ilk_compute_wm_level(dev_priv, level, params, &wm); | |
2598 | ||
2599 | /* | |
2600 | * Disable any watermark level that exceeds the | |
2601 | * register maximums since such watermarks are | |
2602 | * always invalid. | |
2603 | */ | |
2604 | if (!ilk_validate_wm_level(level, &max, &wm)) | |
2605 | break; | |
2606 | ||
2607 | pipe_wm->wm[level] = wm; | |
2608 | } | |
2609 | ||
2610 | return true; | |
0b2ae6d7 VS |
2611 | } |
2612 | ||
2613 | /* | |
2614 | * Merge the watermarks from all active pipes for a specific level. | |
2615 | */ | |
2616 | static void ilk_merge_wm_level(struct drm_device *dev, | |
2617 | int level, | |
2618 | struct intel_wm_level *ret_wm) | |
2619 | { | |
2620 | const struct intel_crtc *intel_crtc; | |
2621 | ||
d52fea5b VS |
2622 | ret_wm->enable = true; |
2623 | ||
d3fcc808 | 2624 | for_each_intel_crtc(dev, intel_crtc) { |
fe392efd VS |
2625 | const struct intel_pipe_wm *active = &intel_crtc->wm.active; |
2626 | const struct intel_wm_level *wm = &active->wm[level]; | |
2627 | ||
2628 | if (!active->pipe_enabled) | |
2629 | continue; | |
0b2ae6d7 | 2630 | |
d52fea5b VS |
2631 | /* |
2632 | * The watermark values may have been used in the past, | |
2633 | * so we must maintain them in the registers for some | |
2634 | * time even if the level is now disabled. | |
2635 | */ | |
0b2ae6d7 | 2636 | if (!wm->enable) |
d52fea5b | 2637 | ret_wm->enable = false; |
0b2ae6d7 VS |
2638 | |
2639 | ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val); | |
2640 | ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val); | |
2641 | ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val); | |
2642 | ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val); | |
2643 | } | |
0b2ae6d7 VS |
2644 | } |
2645 | ||
2646 | /* | |
2647 | * Merge all low power watermarks for all active pipes. | |
2648 | */ | |
2649 | static void ilk_wm_merge(struct drm_device *dev, | |
0ba22e26 | 2650 | const struct intel_wm_config *config, |
820c1980 | 2651 | const struct ilk_wm_maximums *max, |
0b2ae6d7 VS |
2652 | struct intel_pipe_wm *merged) |
2653 | { | |
2654 | int level, max_level = ilk_wm_max_level(dev); | |
d52fea5b | 2655 | int last_enabled_level = max_level; |
0b2ae6d7 | 2656 | |
0ba22e26 VS |
2657 | /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */ |
2658 | if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) && | |
2659 | config->num_pipes_active > 1) | |
2660 | return; | |
2661 | ||
6c8b6c28 VS |
2662 | /* ILK: FBC WM must be disabled always */ |
2663 | merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6; | |
0b2ae6d7 VS |
2664 | |
2665 | /* merge each WM1+ level */ | |
2666 | for (level = 1; level <= max_level; level++) { | |
2667 | struct intel_wm_level *wm = &merged->wm[level]; | |
2668 | ||
2669 | ilk_merge_wm_level(dev, level, wm); | |
2670 | ||
d52fea5b VS |
2671 | if (level > last_enabled_level) |
2672 | wm->enable = false; | |
2673 | else if (!ilk_validate_wm_level(level, max, wm)) | |
2674 | /* make sure all following levels get disabled */ | |
2675 | last_enabled_level = level - 1; | |
0b2ae6d7 VS |
2676 | |
2677 | /* | |
2678 | * The spec says it is preferred to disable | |
2679 | * FBC WMs instead of disabling a WM level. | |
2680 | */ | |
2681 | if (wm->fbc_val > max->fbc) { | |
d52fea5b VS |
2682 | if (wm->enable) |
2683 | merged->fbc_wm_enabled = false; | |
0b2ae6d7 VS |
2684 | wm->fbc_val = 0; |
2685 | } | |
2686 | } | |
6c8b6c28 VS |
2687 | |
2688 | /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */ | |
2689 | /* | |
2690 | * FIXME this is racy. FBC might get enabled later. | |
2691 | * What we should check here is whether FBC can be | |
2692 | * enabled sometime later. | |
2693 | */ | |
2694 | if (IS_GEN5(dev) && !merged->fbc_wm_enabled && intel_fbc_enabled(dev)) { | |
2695 | for (level = 2; level <= max_level; level++) { | |
2696 | struct intel_wm_level *wm = &merged->wm[level]; | |
2697 | ||
2698 | wm->enable = false; | |
2699 | } | |
2700 | } | |
0b2ae6d7 VS |
2701 | } |
2702 | ||
b380ca3c VS |
2703 | static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm) |
2704 | { | |
2705 | /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */ | |
2706 | return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable); | |
2707 | } | |
2708 | ||
a68d68ee VS |
2709 | /* The value we need to program into the WM_LPx latency field */ |
2710 | static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level) | |
2711 | { | |
2712 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2713 | ||
a42a5719 | 2714 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
a68d68ee VS |
2715 | return 2 * level; |
2716 | else | |
2717 | return dev_priv->wm.pri_latency[level]; | |
2718 | } | |
2719 | ||
820c1980 | 2720 | static void ilk_compute_wm_results(struct drm_device *dev, |
0362c781 | 2721 | const struct intel_pipe_wm *merged, |
609cedef | 2722 | enum intel_ddb_partitioning partitioning, |
820c1980 | 2723 | struct ilk_wm_values *results) |
801bcfff | 2724 | { |
0b2ae6d7 VS |
2725 | struct intel_crtc *intel_crtc; |
2726 | int level, wm_lp; | |
cca32e9a | 2727 | |
0362c781 | 2728 | results->enable_fbc_wm = merged->fbc_wm_enabled; |
609cedef | 2729 | results->partitioning = partitioning; |
cca32e9a | 2730 | |
0b2ae6d7 | 2731 | /* LP1+ register values */ |
cca32e9a | 2732 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { |
1fd527cc | 2733 | const struct intel_wm_level *r; |
801bcfff | 2734 | |
b380ca3c | 2735 | level = ilk_wm_lp_to_level(wm_lp, merged); |
0b2ae6d7 | 2736 | |
0362c781 | 2737 | r = &merged->wm[level]; |
cca32e9a | 2738 | |
d52fea5b VS |
2739 | /* |
2740 | * Maintain the watermark values even if the level is | |
2741 | * disabled. Doing otherwise could cause underruns. | |
2742 | */ | |
2743 | results->wm_lp[wm_lp - 1] = | |
a68d68ee | 2744 | (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) | |
416f4727 VS |
2745 | (r->pri_val << WM1_LP_SR_SHIFT) | |
2746 | r->cur_val; | |
2747 | ||
d52fea5b VS |
2748 | if (r->enable) |
2749 | results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN; | |
2750 | ||
416f4727 VS |
2751 | if (INTEL_INFO(dev)->gen >= 8) |
2752 | results->wm_lp[wm_lp - 1] |= | |
2753 | r->fbc_val << WM1_LP_FBC_SHIFT_BDW; | |
2754 | else | |
2755 | results->wm_lp[wm_lp - 1] |= | |
2756 | r->fbc_val << WM1_LP_FBC_SHIFT; | |
2757 | ||
d52fea5b VS |
2758 | /* |
2759 | * Always set WM1S_LP_EN when spr_val != 0, even if the | |
2760 | * level is disabled. Doing otherwise could cause underruns. | |
2761 | */ | |
6cef2b8a VS |
2762 | if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) { |
2763 | WARN_ON(wm_lp != 1); | |
2764 | results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val; | |
2765 | } else | |
2766 | results->wm_lp_spr[wm_lp - 1] = r->spr_val; | |
cca32e9a | 2767 | } |
801bcfff | 2768 | |
0b2ae6d7 | 2769 | /* LP0 register values */ |
d3fcc808 | 2770 | for_each_intel_crtc(dev, intel_crtc) { |
0b2ae6d7 VS |
2771 | enum pipe pipe = intel_crtc->pipe; |
2772 | const struct intel_wm_level *r = | |
2773 | &intel_crtc->wm.active.wm[0]; | |
2774 | ||
2775 | if (WARN_ON(!r->enable)) | |
2776 | continue; | |
2777 | ||
2778 | results->wm_linetime[pipe] = intel_crtc->wm.active.linetime; | |
1011d8c4 | 2779 | |
0b2ae6d7 VS |
2780 | results->wm_pipe[pipe] = |
2781 | (r->pri_val << WM0_PIPE_PLANE_SHIFT) | | |
2782 | (r->spr_val << WM0_PIPE_SPRITE_SHIFT) | | |
2783 | r->cur_val; | |
801bcfff PZ |
2784 | } |
2785 | } | |
2786 | ||
861f3389 PZ |
2787 | /* Find the result with the highest level enabled. Check for enable_fbc_wm in |
2788 | * case both are at the same level. Prefer r1 in case they're the same. */ | |
820c1980 | 2789 | static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev, |
198a1e9b VS |
2790 | struct intel_pipe_wm *r1, |
2791 | struct intel_pipe_wm *r2) | |
861f3389 | 2792 | { |
198a1e9b VS |
2793 | int level, max_level = ilk_wm_max_level(dev); |
2794 | int level1 = 0, level2 = 0; | |
861f3389 | 2795 | |
198a1e9b VS |
2796 | for (level = 1; level <= max_level; level++) { |
2797 | if (r1->wm[level].enable) | |
2798 | level1 = level; | |
2799 | if (r2->wm[level].enable) | |
2800 | level2 = level; | |
861f3389 PZ |
2801 | } |
2802 | ||
198a1e9b VS |
2803 | if (level1 == level2) { |
2804 | if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled) | |
861f3389 PZ |
2805 | return r2; |
2806 | else | |
2807 | return r1; | |
198a1e9b | 2808 | } else if (level1 > level2) { |
861f3389 PZ |
2809 | return r1; |
2810 | } else { | |
2811 | return r2; | |
2812 | } | |
2813 | } | |
2814 | ||
49a687c4 VS |
2815 | /* dirty bits used to track which watermarks need changes */ |
2816 | #define WM_DIRTY_PIPE(pipe) (1 << (pipe)) | |
2817 | #define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe))) | |
2818 | #define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp))) | |
2819 | #define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3)) | |
2820 | #define WM_DIRTY_FBC (1 << 24) | |
2821 | #define WM_DIRTY_DDB (1 << 25) | |
2822 | ||
055e393f | 2823 | static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv, |
820c1980 ID |
2824 | const struct ilk_wm_values *old, |
2825 | const struct ilk_wm_values *new) | |
49a687c4 VS |
2826 | { |
2827 | unsigned int dirty = 0; | |
2828 | enum pipe pipe; | |
2829 | int wm_lp; | |
2830 | ||
055e393f | 2831 | for_each_pipe(dev_priv, pipe) { |
49a687c4 VS |
2832 | if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) { |
2833 | dirty |= WM_DIRTY_LINETIME(pipe); | |
2834 | /* Must disable LP1+ watermarks too */ | |
2835 | dirty |= WM_DIRTY_LP_ALL; | |
2836 | } | |
2837 | ||
2838 | if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) { | |
2839 | dirty |= WM_DIRTY_PIPE(pipe); | |
2840 | /* Must disable LP1+ watermarks too */ | |
2841 | dirty |= WM_DIRTY_LP_ALL; | |
2842 | } | |
2843 | } | |
2844 | ||
2845 | if (old->enable_fbc_wm != new->enable_fbc_wm) { | |
2846 | dirty |= WM_DIRTY_FBC; | |
2847 | /* Must disable LP1+ watermarks too */ | |
2848 | dirty |= WM_DIRTY_LP_ALL; | |
2849 | } | |
2850 | ||
2851 | if (old->partitioning != new->partitioning) { | |
2852 | dirty |= WM_DIRTY_DDB; | |
2853 | /* Must disable LP1+ watermarks too */ | |
2854 | dirty |= WM_DIRTY_LP_ALL; | |
2855 | } | |
2856 | ||
2857 | /* LP1+ watermarks already deemed dirty, no need to continue */ | |
2858 | if (dirty & WM_DIRTY_LP_ALL) | |
2859 | return dirty; | |
2860 | ||
2861 | /* Find the lowest numbered LP1+ watermark in need of an update... */ | |
2862 | for (wm_lp = 1; wm_lp <= 3; wm_lp++) { | |
2863 | if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] || | |
2864 | old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1]) | |
2865 | break; | |
2866 | } | |
2867 | ||
2868 | /* ...and mark it and all higher numbered LP1+ watermarks as dirty */ | |
2869 | for (; wm_lp <= 3; wm_lp++) | |
2870 | dirty |= WM_DIRTY_LP(wm_lp); | |
2871 | ||
2872 | return dirty; | |
2873 | } | |
2874 | ||
8553c18e VS |
2875 | static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv, |
2876 | unsigned int dirty) | |
801bcfff | 2877 | { |
820c1980 | 2878 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e | 2879 | bool changed = false; |
801bcfff | 2880 | |
facd619b VS |
2881 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) { |
2882 | previous->wm_lp[2] &= ~WM1_LP_SR_EN; | |
2883 | I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]); | |
8553c18e | 2884 | changed = true; |
facd619b VS |
2885 | } |
2886 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) { | |
2887 | previous->wm_lp[1] &= ~WM1_LP_SR_EN; | |
2888 | I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]); | |
8553c18e | 2889 | changed = true; |
facd619b VS |
2890 | } |
2891 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) { | |
2892 | previous->wm_lp[0] &= ~WM1_LP_SR_EN; | |
2893 | I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]); | |
8553c18e | 2894 | changed = true; |
facd619b | 2895 | } |
801bcfff | 2896 | |
facd619b VS |
2897 | /* |
2898 | * Don't touch WM1S_LP_EN here. | |
2899 | * Doing so could cause underruns. | |
2900 | */ | |
6cef2b8a | 2901 | |
8553c18e VS |
2902 | return changed; |
2903 | } | |
2904 | ||
2905 | /* | |
2906 | * The spec says we shouldn't write when we don't need, because every write | |
2907 | * causes WMs to be re-evaluated, expending some power. | |
2908 | */ | |
820c1980 ID |
2909 | static void ilk_write_wm_values(struct drm_i915_private *dev_priv, |
2910 | struct ilk_wm_values *results) | |
8553c18e VS |
2911 | { |
2912 | struct drm_device *dev = dev_priv->dev; | |
820c1980 | 2913 | struct ilk_wm_values *previous = &dev_priv->wm.hw; |
8553c18e VS |
2914 | unsigned int dirty; |
2915 | uint32_t val; | |
2916 | ||
055e393f | 2917 | dirty = ilk_compute_wm_dirty(dev_priv, previous, results); |
8553c18e VS |
2918 | if (!dirty) |
2919 | return; | |
2920 | ||
2921 | _ilk_disable_lp_wm(dev_priv, dirty); | |
2922 | ||
49a687c4 | 2923 | if (dirty & WM_DIRTY_PIPE(PIPE_A)) |
801bcfff | 2924 | I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]); |
49a687c4 | 2925 | if (dirty & WM_DIRTY_PIPE(PIPE_B)) |
801bcfff | 2926 | I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]); |
49a687c4 | 2927 | if (dirty & WM_DIRTY_PIPE(PIPE_C)) |
801bcfff PZ |
2928 | I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]); |
2929 | ||
49a687c4 | 2930 | if (dirty & WM_DIRTY_LINETIME(PIPE_A)) |
801bcfff | 2931 | I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]); |
49a687c4 | 2932 | if (dirty & WM_DIRTY_LINETIME(PIPE_B)) |
801bcfff | 2933 | I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]); |
49a687c4 | 2934 | if (dirty & WM_DIRTY_LINETIME(PIPE_C)) |
801bcfff PZ |
2935 | I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]); |
2936 | ||
49a687c4 | 2937 | if (dirty & WM_DIRTY_DDB) { |
a42a5719 | 2938 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) { |
ac9545fd VS |
2939 | val = I915_READ(WM_MISC); |
2940 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2941 | val &= ~WM_MISC_DATA_PARTITION_5_6; | |
2942 | else | |
2943 | val |= WM_MISC_DATA_PARTITION_5_6; | |
2944 | I915_WRITE(WM_MISC, val); | |
2945 | } else { | |
2946 | val = I915_READ(DISP_ARB_CTL2); | |
2947 | if (results->partitioning == INTEL_DDB_PART_1_2) | |
2948 | val &= ~DISP_DATA_PARTITION_5_6; | |
2949 | else | |
2950 | val |= DISP_DATA_PARTITION_5_6; | |
2951 | I915_WRITE(DISP_ARB_CTL2, val); | |
2952 | } | |
1011d8c4 PZ |
2953 | } |
2954 | ||
49a687c4 | 2955 | if (dirty & WM_DIRTY_FBC) { |
cca32e9a PZ |
2956 | val = I915_READ(DISP_ARB_CTL); |
2957 | if (results->enable_fbc_wm) | |
2958 | val &= ~DISP_FBC_WM_DIS; | |
2959 | else | |
2960 | val |= DISP_FBC_WM_DIS; | |
2961 | I915_WRITE(DISP_ARB_CTL, val); | |
2962 | } | |
2963 | ||
954911eb ID |
2964 | if (dirty & WM_DIRTY_LP(1) && |
2965 | previous->wm_lp_spr[0] != results->wm_lp_spr[0]) | |
2966 | I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]); | |
2967 | ||
2968 | if (INTEL_INFO(dev)->gen >= 7) { | |
6cef2b8a VS |
2969 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1]) |
2970 | I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]); | |
2971 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2]) | |
2972 | I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]); | |
2973 | } | |
801bcfff | 2974 | |
facd619b | 2975 | if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0]) |
801bcfff | 2976 | I915_WRITE(WM1_LP_ILK, results->wm_lp[0]); |
facd619b | 2977 | if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1]) |
801bcfff | 2978 | I915_WRITE(WM2_LP_ILK, results->wm_lp[1]); |
facd619b | 2979 | if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2]) |
801bcfff | 2980 | I915_WRITE(WM3_LP_ILK, results->wm_lp[2]); |
609cedef VS |
2981 | |
2982 | dev_priv->wm.hw = *results; | |
801bcfff PZ |
2983 | } |
2984 | ||
8553c18e VS |
2985 | static bool ilk_disable_lp_wm(struct drm_device *dev) |
2986 | { | |
2987 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2988 | ||
2989 | return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL); | |
2990 | } | |
2991 | ||
b9cec075 DL |
2992 | /* |
2993 | * On gen9, we need to allocate Display Data Buffer (DDB) portions to the | |
2994 | * different active planes. | |
2995 | */ | |
2996 | ||
2997 | #define SKL_DDB_SIZE 896 /* in blocks */ | |
2998 | ||
2999 | static void | |
3000 | skl_ddb_get_pipe_allocation_limits(struct drm_device *dev, | |
3001 | struct drm_crtc *for_crtc, | |
3002 | const struct intel_wm_config *config, | |
3003 | const struct skl_pipe_wm_parameters *params, | |
3004 | struct skl_ddb_entry *alloc /* out */) | |
3005 | { | |
3006 | struct drm_crtc *crtc; | |
3007 | unsigned int pipe_size, ddb_size; | |
3008 | int nth_active_pipe; | |
3009 | ||
3010 | if (!params->active) { | |
3011 | alloc->start = 0; | |
3012 | alloc->end = 0; | |
3013 | return; | |
3014 | } | |
3015 | ||
3016 | ddb_size = SKL_DDB_SIZE; | |
3017 | ||
3018 | ddb_size -= 4; /* 4 blocks for bypass path allocation */ | |
3019 | ||
3020 | nth_active_pipe = 0; | |
3021 | for_each_crtc(dev, crtc) { | |
3022 | if (!intel_crtc_active(crtc)) | |
3023 | continue; | |
3024 | ||
3025 | if (crtc == for_crtc) | |
3026 | break; | |
3027 | ||
3028 | nth_active_pipe++; | |
3029 | } | |
3030 | ||
3031 | pipe_size = ddb_size / config->num_pipes_active; | |
3032 | alloc->start = nth_active_pipe * ddb_size / config->num_pipes_active; | |
3033 | alloc->end = alloc->start + pipe_size - 1; | |
3034 | } | |
3035 | ||
3036 | static unsigned int skl_cursor_allocation(const struct intel_wm_config *config) | |
3037 | { | |
3038 | if (config->num_pipes_active == 1) | |
3039 | return 32; | |
3040 | ||
3041 | return 8; | |
3042 | } | |
3043 | ||
3044 | static unsigned int | |
3045 | skl_plane_relative_data_rate(const struct intel_plane_wm_parameters *p) | |
3046 | { | |
3047 | return p->horiz_pixels * p->vert_pixels * p->bytes_per_pixel; | |
3048 | } | |
3049 | ||
3050 | /* | |
3051 | * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching | |
3052 | * a 8192x4096@32bpp framebuffer: | |
3053 | * 3 * 4096 * 8192 * 4 < 2^32 | |
3054 | */ | |
3055 | static unsigned int | |
3056 | skl_get_total_relative_data_rate(struct intel_crtc *intel_crtc, | |
3057 | const struct skl_pipe_wm_parameters *params) | |
3058 | { | |
3059 | unsigned int total_data_rate = 0; | |
3060 | int plane; | |
3061 | ||
3062 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
3063 | const struct intel_plane_wm_parameters *p; | |
3064 | ||
3065 | p = ¶ms->plane[plane]; | |
3066 | if (!p->enabled) | |
3067 | continue; | |
3068 | ||
3069 | total_data_rate += skl_plane_relative_data_rate(p); | |
3070 | } | |
3071 | ||
3072 | return total_data_rate; | |
3073 | } | |
3074 | ||
3075 | static void | |
3076 | skl_allocate_pipe_ddb(struct drm_crtc *crtc, | |
3077 | const struct intel_wm_config *config, | |
3078 | const struct skl_pipe_wm_parameters *params, | |
3079 | struct skl_ddb_allocation *ddb /* out */) | |
3080 | { | |
3081 | struct drm_device *dev = crtc->dev; | |
3082 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3083 | enum pipe pipe = intel_crtc->pipe; | |
3084 | struct skl_ddb_entry alloc; | |
3085 | uint16_t alloc_size, start, cursor_blocks; | |
3086 | unsigned int total_data_rate; | |
3087 | int plane; | |
3088 | ||
3089 | skl_ddb_get_pipe_allocation_limits(dev, crtc, config, params, &alloc); | |
3090 | alloc_size = skl_ddb_entry_size(&alloc); | |
3091 | if (alloc_size == 0) { | |
3092 | memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe])); | |
3093 | memset(&ddb->cursor[pipe], 0, sizeof(ddb->cursor[pipe])); | |
3094 | return; | |
3095 | } | |
3096 | ||
3097 | cursor_blocks = skl_cursor_allocation(config); | |
3098 | ddb->cursor[pipe].start = alloc.end - cursor_blocks + 1; | |
3099 | ddb->cursor[pipe].end = alloc.end; | |
3100 | ||
3101 | alloc_size -= cursor_blocks; | |
3102 | alloc.end -= cursor_blocks; | |
3103 | ||
3104 | /* | |
3105 | * Each active plane get a portion of the remaining space, in | |
3106 | * proportion to the amount of data they need to fetch from memory. | |
3107 | * | |
3108 | * FIXME: we may not allocate every single block here. | |
3109 | */ | |
3110 | total_data_rate = skl_get_total_relative_data_rate(intel_crtc, params); | |
3111 | ||
3112 | start = alloc.start; | |
3113 | for (plane = 0; plane < intel_num_planes(intel_crtc); plane++) { | |
3114 | const struct intel_plane_wm_parameters *p; | |
3115 | unsigned int data_rate; | |
3116 | uint16_t plane_blocks; | |
3117 | ||
3118 | p = ¶ms->plane[plane]; | |
3119 | if (!p->enabled) | |
3120 | continue; | |
3121 | ||
3122 | data_rate = skl_plane_relative_data_rate(p); | |
3123 | ||
3124 | /* | |
3125 | * promote the expression to 64 bits to avoid overflowing, the | |
3126 | * result is < available as data_rate / total_data_rate < 1 | |
3127 | */ | |
3128 | plane_blocks = div_u64((uint64_t)alloc_size * data_rate, | |
3129 | total_data_rate); | |
3130 | ||
3131 | ddb->plane[pipe][plane].start = start; | |
3132 | ddb->plane[pipe][plane].end = start + plane_blocks - 1; | |
3133 | ||
3134 | start += plane_blocks; | |
3135 | } | |
3136 | ||
3137 | } | |
3138 | ||
2d41c0b5 PB |
3139 | static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_config *config) |
3140 | { | |
3141 | /* TODO: Take into account the scalers once we support them */ | |
3142 | return config->adjusted_mode.crtc_clock; | |
3143 | } | |
3144 | ||
3145 | /* | |
3146 | * The max latency should be 257 (max the punit can code is 255 and we add 2us | |
3147 | * for the read latency) and bytes_per_pixel should always be <= 8, so that | |
3148 | * should allow pixel_rate up to ~2 GHz which seems sufficient since max | |
3149 | * 2xcdclk is 1350 MHz and the pixel rate should never exceed that. | |
3150 | */ | |
3151 | static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel, | |
3152 | uint32_t latency) | |
3153 | { | |
3154 | uint32_t wm_intermediate_val, ret; | |
3155 | ||
3156 | if (latency == 0) | |
3157 | return UINT_MAX; | |
3158 | ||
3159 | wm_intermediate_val = latency * pixel_rate * bytes_per_pixel; | |
3160 | ret = DIV_ROUND_UP(wm_intermediate_val, 1000); | |
3161 | ||
3162 | return ret; | |
3163 | } | |
3164 | ||
3165 | static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal, | |
3166 | uint32_t horiz_pixels, uint8_t bytes_per_pixel, | |
3167 | uint32_t latency) | |
3168 | { | |
3169 | uint32_t ret, plane_bytes_per_line, wm_intermediate_val; | |
3170 | ||
3171 | if (latency == 0) | |
3172 | return UINT_MAX; | |
3173 | ||
3174 | plane_bytes_per_line = horiz_pixels * bytes_per_pixel; | |
3175 | wm_intermediate_val = latency * pixel_rate; | |
3176 | ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) * | |
3177 | plane_bytes_per_line; | |
3178 | ||
3179 | return ret; | |
3180 | } | |
3181 | ||
3182 | static void skl_compute_transition_wm(struct drm_crtc *crtc, | |
3183 | struct skl_pipe_wm_parameters *params, | |
3184 | struct skl_pipe_wm *pipe_wm) | |
3185 | { | |
3186 | /* | |
3187 | * For now it is suggested to use the LP0 wm val of corresponding | |
3188 | * plane as transition wm val. This is done while computing results. | |
3189 | */ | |
3190 | if (!params->active) | |
3191 | return; | |
3192 | } | |
3193 | ||
3194 | static uint32_t | |
3195 | skl_compute_linetime_wm(struct drm_crtc *crtc, struct skl_pipe_wm_parameters *p) | |
3196 | { | |
3197 | if (!intel_crtc_active(crtc)) | |
3198 | return 0; | |
3199 | ||
3200 | return DIV_ROUND_UP(8 * p->pipe_htotal * 1000, p->pixel_rate); | |
3201 | ||
3202 | } | |
3203 | ||
3204 | static bool skl_ddb_allocation_changed(const struct skl_ddb_allocation *new_ddb, | |
3205 | const struct intel_crtc *intel_crtc) | |
3206 | { | |
3207 | struct drm_device *dev = intel_crtc->base.dev; | |
3208 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3209 | const struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb; | |
3210 | enum pipe pipe = intel_crtc->pipe; | |
3211 | ||
3212 | if (memcmp(new_ddb->plane[pipe], cur_ddb->plane[pipe], | |
3213 | sizeof(new_ddb->plane[pipe]))) | |
3214 | return true; | |
3215 | ||
3216 | if (memcmp(&new_ddb->cursor[pipe], &cur_ddb->cursor[pipe], | |
3217 | sizeof(new_ddb->cursor[pipe]))) | |
3218 | return true; | |
3219 | ||
3220 | return false; | |
3221 | } | |
3222 | ||
3223 | static void skl_compute_wm_global_parameters(struct drm_device *dev, | |
3224 | struct intel_wm_config *config) | |
3225 | { | |
3226 | struct drm_crtc *crtc; | |
3227 | struct drm_plane *plane; | |
3228 | ||
3229 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3230 | config->num_pipes_active += intel_crtc_active(crtc); | |
3231 | ||
3232 | /* FIXME: I don't think we need those two global parameters on SKL */ | |
3233 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
3234 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3235 | ||
3236 | config->sprites_enabled |= intel_plane->wm.enabled; | |
3237 | config->sprites_scaled |= intel_plane->wm.scaled; | |
3238 | } | |
3239 | } | |
3240 | ||
3241 | static void skl_compute_wm_pipe_parameters(struct drm_crtc *crtc, | |
3242 | struct skl_pipe_wm_parameters *p) | |
3243 | { | |
3244 | struct drm_device *dev = crtc->dev; | |
3245 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3246 | enum pipe pipe = intel_crtc->pipe; | |
3247 | struct drm_plane *plane; | |
3248 | int i = 1; /* Index for sprite planes start */ | |
3249 | ||
3250 | p->active = intel_crtc_active(crtc); | |
3251 | if (p->active) { | |
3252 | p->pipe_htotal = intel_crtc->config.adjusted_mode.crtc_htotal; | |
3253 | p->pixel_rate = skl_pipe_pixel_rate(&intel_crtc->config); | |
3254 | ||
3255 | /* | |
3256 | * For now, assume primary and cursor planes are always enabled. | |
3257 | */ | |
3258 | p->plane[0].enabled = true; | |
3259 | p->plane[0].bytes_per_pixel = | |
3260 | crtc->primary->fb->bits_per_pixel / 8; | |
3261 | p->plane[0].horiz_pixels = intel_crtc->config.pipe_src_w; | |
3262 | p->plane[0].vert_pixels = intel_crtc->config.pipe_src_h; | |
3263 | ||
3264 | p->cursor.enabled = true; | |
3265 | p->cursor.bytes_per_pixel = 4; | |
3266 | p->cursor.horiz_pixels = intel_crtc->cursor_width ? | |
3267 | intel_crtc->cursor_width : 64; | |
3268 | } | |
3269 | ||
3270 | list_for_each_entry(plane, &dev->mode_config.plane_list, head) { | |
3271 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3272 | ||
3273 | if (intel_plane->pipe == pipe) | |
3274 | p->plane[i++] = intel_plane->wm; | |
3275 | } | |
3276 | } | |
3277 | ||
3278 | static bool skl_compute_plane_wm(struct skl_pipe_wm_parameters *p, | |
3279 | struct intel_plane_wm_parameters *p_params, | |
3280 | uint16_t max_page_buff_alloc, | |
3281 | uint32_t mem_value, | |
3282 | uint16_t *res_blocks, /* out */ | |
3283 | uint8_t *res_lines /* out */) | |
3284 | { | |
3285 | uint32_t method1, method2, plane_bytes_per_line; | |
3286 | uint32_t result_bytes; | |
3287 | ||
3288 | if (!p->active || !p_params->enabled) | |
3289 | return false; | |
3290 | ||
3291 | method1 = skl_wm_method1(p->pixel_rate, | |
3292 | p_params->bytes_per_pixel, | |
3293 | mem_value); | |
3294 | method2 = skl_wm_method2(p->pixel_rate, | |
3295 | p->pipe_htotal, | |
3296 | p_params->horiz_pixels, | |
3297 | p_params->bytes_per_pixel, | |
3298 | mem_value); | |
3299 | ||
3300 | plane_bytes_per_line = p_params->horiz_pixels * | |
3301 | p_params->bytes_per_pixel; | |
3302 | ||
3303 | /* For now xtile and linear */ | |
3304 | if (((max_page_buff_alloc * 512) / plane_bytes_per_line) >= 1) | |
3305 | result_bytes = min(method1, method2); | |
3306 | else | |
3307 | result_bytes = method1; | |
3308 | ||
3309 | *res_blocks = DIV_ROUND_UP(result_bytes, 512) + 1; | |
3310 | *res_lines = DIV_ROUND_UP(result_bytes, plane_bytes_per_line); | |
3311 | ||
3312 | return true; | |
3313 | } | |
3314 | ||
3315 | static void skl_compute_wm_level(const struct drm_i915_private *dev_priv, | |
3316 | struct skl_ddb_allocation *ddb, | |
3317 | struct skl_pipe_wm_parameters *p, | |
3318 | enum pipe pipe, | |
3319 | int level, | |
3320 | int num_planes, | |
3321 | struct skl_wm_level *result) | |
3322 | { | |
3323 | uint16_t latency = dev_priv->wm.skl_latency[level]; | |
3324 | uint16_t ddb_blocks; | |
3325 | int i; | |
3326 | ||
3327 | for (i = 0; i < num_planes; i++) { | |
3328 | ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]); | |
3329 | ||
3330 | result->plane_en[i] = skl_compute_plane_wm(p, &p->plane[i], | |
3331 | ddb_blocks, | |
3332 | latency, | |
3333 | &result->plane_res_b[i], | |
3334 | &result->plane_res_l[i]); | |
3335 | } | |
3336 | ||
3337 | ddb_blocks = skl_ddb_entry_size(&ddb->cursor[pipe]); | |
3338 | result->cursor_en = skl_compute_plane_wm(p, &p->cursor, ddb_blocks, | |
3339 | latency, &result->cursor_res_b, | |
3340 | &result->cursor_res_l); | |
3341 | } | |
3342 | ||
3343 | static void skl_compute_pipe_wm(struct drm_crtc *crtc, | |
3344 | struct skl_ddb_allocation *ddb, | |
3345 | struct skl_pipe_wm_parameters *params, | |
3346 | struct skl_pipe_wm *pipe_wm) | |
3347 | { | |
3348 | struct drm_device *dev = crtc->dev; | |
3349 | const struct drm_i915_private *dev_priv = dev->dev_private; | |
3350 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3351 | int level, max_level = ilk_wm_max_level(dev); | |
3352 | ||
3353 | for (level = 0; level <= max_level; level++) { | |
3354 | skl_compute_wm_level(dev_priv, ddb, params, intel_crtc->pipe, | |
3355 | level, intel_num_planes(intel_crtc), | |
3356 | &pipe_wm->wm[level]); | |
3357 | } | |
3358 | pipe_wm->linetime = skl_compute_linetime_wm(crtc, params); | |
3359 | ||
3360 | skl_compute_transition_wm(crtc, params, pipe_wm); | |
3361 | } | |
3362 | ||
3363 | static void skl_compute_wm_results(struct drm_device *dev, | |
3364 | struct skl_pipe_wm_parameters *p, | |
3365 | struct skl_pipe_wm *p_wm, | |
3366 | struct skl_wm_values *r, | |
3367 | struct intel_crtc *intel_crtc) | |
3368 | { | |
3369 | int level, max_level = ilk_wm_max_level(dev); | |
3370 | enum pipe pipe = intel_crtc->pipe; | |
3371 | ||
3372 | for (level = 0; level <= max_level; level++) { | |
3373 | uint16_t ddb_blocks; | |
3374 | uint32_t temp; | |
3375 | int i; | |
3376 | ||
3377 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3378 | temp = 0; | |
3379 | ddb_blocks = skl_ddb_entry_size(&r->ddb.plane[pipe][i]); | |
3380 | ||
3381 | if ((p_wm->wm[level].plane_res_b[i] > ddb_blocks) || | |
3382 | (p_wm->wm[level].plane_res_l[i] > 31)) | |
3383 | p_wm->wm[level].plane_en[i] = false; | |
3384 | ||
3385 | temp |= p_wm->wm[level].plane_res_l[i] << | |
3386 | PLANE_WM_LINES_SHIFT; | |
3387 | temp |= p_wm->wm[level].plane_res_b[i]; | |
3388 | if (p_wm->wm[level].plane_en[i]) | |
3389 | temp |= PLANE_WM_EN; | |
3390 | ||
3391 | r->plane[pipe][i][level] = temp; | |
3392 | /* Use the LP0 WM value for transition WM for now. */ | |
3393 | if (level == 0) | |
3394 | r->plane_trans[pipe][i] = temp; | |
3395 | } | |
3396 | ||
3397 | temp = 0; | |
3398 | ddb_blocks = skl_ddb_entry_size(&r->ddb.cursor[pipe]); | |
3399 | ||
3400 | if ((p_wm->wm[level].cursor_res_b > ddb_blocks) || | |
3401 | (p_wm->wm[level].cursor_res_l > 31)) | |
3402 | p_wm->wm[level].cursor_en = false; | |
3403 | ||
3404 | temp |= p_wm->wm[level].cursor_res_l << PLANE_WM_LINES_SHIFT; | |
3405 | temp |= p_wm->wm[level].cursor_res_b; | |
3406 | ||
3407 | if (p_wm->wm[level].cursor_en) | |
3408 | temp |= PLANE_WM_EN; | |
3409 | ||
3410 | r->cursor[pipe][level] = temp; | |
3411 | /* Use the LP0 WM value for transition WM for now. */ | |
3412 | if (level == 0) | |
3413 | r->cursor_trans[pipe] = temp; | |
3414 | ||
3415 | } | |
3416 | ||
3417 | r->wm_linetime[pipe] = p_wm->linetime; | |
3418 | } | |
3419 | ||
3420 | static void skl_write_wm_values(struct drm_i915_private *dev_priv, | |
3421 | const struct skl_wm_values *new) | |
3422 | { | |
3423 | struct drm_device *dev = dev_priv->dev; | |
3424 | struct intel_crtc *crtc; | |
3425 | ||
3426 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, base.head) { | |
3427 | int i, level, max_level = ilk_wm_max_level(dev); | |
3428 | enum pipe pipe = crtc->pipe; | |
3429 | ||
3430 | if (new->dirty[pipe]) { | |
3431 | I915_WRITE(PIPE_WM_LINETIME(pipe), | |
3432 | new->wm_linetime[pipe]); | |
3433 | ||
3434 | for (level = 0; level <= max_level; level++) { | |
3435 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3436 | I915_WRITE(PLANE_WM(pipe, i, level), | |
3437 | new->plane[pipe][i][level]); | |
3438 | I915_WRITE(CUR_WM(pipe, level), | |
3439 | new->cursor[pipe][level]); | |
3440 | } | |
3441 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3442 | I915_WRITE(PLANE_WM_TRANS(pipe, i), | |
3443 | new->plane_trans[pipe][i]); | |
3444 | I915_WRITE(CUR_WM_TRANS(pipe), new->cursor_trans[pipe]); | |
8211bd5b DL |
3445 | |
3446 | for (i = 0; i < intel_num_planes(crtc); i++) | |
3447 | I915_WRITE(PLANE_BUF_CFG(pipe, i), | |
3448 | new->ddb.plane[pipe][i].end << 16 | | |
3449 | new->ddb.plane[pipe][i].start); | |
3450 | ||
3451 | I915_WRITE(CUR_BUF_CFG(pipe), | |
3452 | new->ddb.cursor[pipe].end << 16 | | |
3453 | new->ddb.cursor[pipe].start); | |
2d41c0b5 PB |
3454 | } |
3455 | } | |
3456 | ||
3457 | dev_priv->wm.skl_hw = *new; | |
3458 | } | |
3459 | ||
3460 | static bool skl_update_pipe_wm(struct drm_crtc *crtc, | |
3461 | struct skl_pipe_wm_parameters *params, | |
3462 | struct intel_wm_config *config, | |
3463 | struct skl_ddb_allocation *ddb, /* out */ | |
3464 | struct skl_pipe_wm *pipe_wm /* out */) | |
3465 | { | |
3466 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3467 | ||
3468 | skl_compute_wm_pipe_parameters(crtc, params); | |
b9cec075 | 3469 | skl_allocate_pipe_ddb(crtc, config, params, ddb); |
2d41c0b5 PB |
3470 | skl_compute_pipe_wm(crtc, ddb, params, pipe_wm); |
3471 | ||
3472 | if (!memcmp(&intel_crtc->wm.skl_active, pipe_wm, sizeof(*pipe_wm))) | |
3473 | return false; | |
3474 | ||
3475 | intel_crtc->wm.skl_active = *pipe_wm; | |
3476 | return true; | |
3477 | } | |
3478 | ||
3479 | static void skl_update_other_pipe_wm(struct drm_device *dev, | |
3480 | struct drm_crtc *crtc, | |
3481 | struct intel_wm_config *config, | |
3482 | struct skl_wm_values *r) | |
3483 | { | |
3484 | struct intel_crtc *intel_crtc; | |
3485 | struct intel_crtc *this_crtc = to_intel_crtc(crtc); | |
3486 | ||
3487 | /* | |
3488 | * If the WM update hasn't changed the allocation for this_crtc (the | |
3489 | * crtc we are currently computing the new WM values for), other | |
3490 | * enabled crtcs will keep the same allocation and we don't need to | |
3491 | * recompute anything for them. | |
3492 | */ | |
3493 | if (!skl_ddb_allocation_changed(&r->ddb, this_crtc)) | |
3494 | return; | |
3495 | ||
3496 | /* | |
3497 | * Otherwise, because of this_crtc being freshly enabled/disabled, the | |
3498 | * other active pipes need new DDB allocation and WM values. | |
3499 | */ | |
3500 | list_for_each_entry(intel_crtc, &dev->mode_config.crtc_list, | |
3501 | base.head) { | |
3502 | struct skl_pipe_wm_parameters params = {}; | |
3503 | struct skl_pipe_wm pipe_wm = {}; | |
3504 | bool wm_changed; | |
3505 | ||
3506 | if (this_crtc->pipe == intel_crtc->pipe) | |
3507 | continue; | |
3508 | ||
3509 | if (!intel_crtc->active) | |
3510 | continue; | |
3511 | ||
3512 | wm_changed = skl_update_pipe_wm(&intel_crtc->base, | |
3513 | ¶ms, config, | |
3514 | &r->ddb, &pipe_wm); | |
3515 | ||
3516 | /* | |
3517 | * If we end up re-computing the other pipe WM values, it's | |
3518 | * because it was really needed, so we expect the WM values to | |
3519 | * be different. | |
3520 | */ | |
3521 | WARN_ON(!wm_changed); | |
3522 | ||
3523 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, r, intel_crtc); | |
3524 | r->dirty[intel_crtc->pipe] = true; | |
3525 | } | |
3526 | } | |
3527 | ||
3528 | static void skl_update_wm(struct drm_crtc *crtc) | |
3529 | { | |
3530 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3531 | struct drm_device *dev = crtc->dev; | |
3532 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3533 | struct skl_pipe_wm_parameters params = {}; | |
3534 | struct skl_wm_values *results = &dev_priv->wm.skl_results; | |
3535 | struct skl_pipe_wm pipe_wm = {}; | |
3536 | struct intel_wm_config config = {}; | |
3537 | ||
3538 | memset(results, 0, sizeof(*results)); | |
3539 | ||
3540 | skl_compute_wm_global_parameters(dev, &config); | |
3541 | ||
3542 | if (!skl_update_pipe_wm(crtc, ¶ms, &config, | |
3543 | &results->ddb, &pipe_wm)) | |
3544 | return; | |
3545 | ||
3546 | skl_compute_wm_results(dev, ¶ms, &pipe_wm, results, intel_crtc); | |
3547 | results->dirty[intel_crtc->pipe] = true; | |
3548 | ||
3549 | skl_update_other_pipe_wm(dev, crtc, &config, results); | |
3550 | skl_write_wm_values(dev_priv, results); | |
3551 | } | |
3552 | ||
3553 | static void | |
3554 | skl_update_sprite_wm(struct drm_plane *plane, struct drm_crtc *crtc, | |
3555 | uint32_t sprite_width, uint32_t sprite_height, | |
3556 | int pixel_size, bool enabled, bool scaled) | |
3557 | { | |
3558 | struct intel_plane *intel_plane = to_intel_plane(plane); | |
3559 | ||
3560 | intel_plane->wm.enabled = enabled; | |
3561 | intel_plane->wm.scaled = scaled; | |
3562 | intel_plane->wm.horiz_pixels = sprite_width; | |
3563 | intel_plane->wm.vert_pixels = sprite_height; | |
3564 | intel_plane->wm.bytes_per_pixel = pixel_size; | |
3565 | ||
3566 | skl_update_wm(crtc); | |
3567 | } | |
3568 | ||
820c1980 | 3569 | static void ilk_update_wm(struct drm_crtc *crtc) |
801bcfff | 3570 | { |
7c4a395f | 3571 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
46ba614c | 3572 | struct drm_device *dev = crtc->dev; |
801bcfff | 3573 | struct drm_i915_private *dev_priv = dev->dev_private; |
820c1980 ID |
3574 | struct ilk_wm_maximums max; |
3575 | struct ilk_pipe_wm_parameters params = {}; | |
3576 | struct ilk_wm_values results = {}; | |
77c122bc | 3577 | enum intel_ddb_partitioning partitioning; |
7c4a395f | 3578 | struct intel_pipe_wm pipe_wm = {}; |
198a1e9b | 3579 | struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm; |
a485bfb8 | 3580 | struct intel_wm_config config = {}; |
7c4a395f | 3581 | |
2a44b76b | 3582 | ilk_compute_wm_parameters(crtc, ¶ms); |
7c4a395f VS |
3583 | |
3584 | intel_compute_pipe_wm(crtc, ¶ms, &pipe_wm); | |
3585 | ||
3586 | if (!memcmp(&intel_crtc->wm.active, &pipe_wm, sizeof(pipe_wm))) | |
3587 | return; | |
861f3389 | 3588 | |
7c4a395f | 3589 | intel_crtc->wm.active = pipe_wm; |
861f3389 | 3590 | |
2a44b76b VS |
3591 | ilk_compute_wm_config(dev, &config); |
3592 | ||
34982fe1 | 3593 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max); |
0ba22e26 | 3594 | ilk_wm_merge(dev, &config, &max, &lp_wm_1_2); |
a485bfb8 VS |
3595 | |
3596 | /* 5/6 split only in single pipe config on IVB+ */ | |
ec98c8d1 VS |
3597 | if (INTEL_INFO(dev)->gen >= 7 && |
3598 | config.num_pipes_active == 1 && config.sprites_enabled) { | |
34982fe1 | 3599 | ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max); |
0ba22e26 | 3600 | ilk_wm_merge(dev, &config, &max, &lp_wm_5_6); |
0362c781 | 3601 | |
820c1980 | 3602 | best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6); |
861f3389 | 3603 | } else { |
198a1e9b | 3604 | best_lp_wm = &lp_wm_1_2; |
861f3389 PZ |
3605 | } |
3606 | ||
198a1e9b | 3607 | partitioning = (best_lp_wm == &lp_wm_1_2) ? |
77c122bc | 3608 | INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6; |
801bcfff | 3609 | |
820c1980 | 3610 | ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results); |
609cedef | 3611 | |
820c1980 | 3612 | ilk_write_wm_values(dev_priv, &results); |
1011d8c4 PZ |
3613 | } |
3614 | ||
ed57cb8a DL |
3615 | static void |
3616 | ilk_update_sprite_wm(struct drm_plane *plane, | |
3617 | struct drm_crtc *crtc, | |
3618 | uint32_t sprite_width, uint32_t sprite_height, | |
3619 | int pixel_size, bool enabled, bool scaled) | |
526682e9 | 3620 | { |
8553c18e | 3621 | struct drm_device *dev = plane->dev; |
adf3d35e | 3622 | struct intel_plane *intel_plane = to_intel_plane(plane); |
526682e9 | 3623 | |
adf3d35e VS |
3624 | intel_plane->wm.enabled = enabled; |
3625 | intel_plane->wm.scaled = scaled; | |
3626 | intel_plane->wm.horiz_pixels = sprite_width; | |
ed57cb8a | 3627 | intel_plane->wm.vert_pixels = sprite_width; |
adf3d35e | 3628 | intel_plane->wm.bytes_per_pixel = pixel_size; |
526682e9 | 3629 | |
8553c18e VS |
3630 | /* |
3631 | * IVB workaround: must disable low power watermarks for at least | |
3632 | * one frame before enabling scaling. LP watermarks can be re-enabled | |
3633 | * when scaling is disabled. | |
3634 | * | |
3635 | * WaCxSRDisabledForSpriteScaling:ivb | |
3636 | */ | |
3637 | if (IS_IVYBRIDGE(dev) && scaled && ilk_disable_lp_wm(dev)) | |
3638 | intel_wait_for_vblank(dev, intel_plane->pipe); | |
3639 | ||
820c1980 | 3640 | ilk_update_wm(crtc); |
526682e9 PZ |
3641 | } |
3642 | ||
3078999f PB |
3643 | static void skl_pipe_wm_active_state(uint32_t val, |
3644 | struct skl_pipe_wm *active, | |
3645 | bool is_transwm, | |
3646 | bool is_cursor, | |
3647 | int i, | |
3648 | int level) | |
3649 | { | |
3650 | bool is_enabled = (val & PLANE_WM_EN) != 0; | |
3651 | ||
3652 | if (!is_transwm) { | |
3653 | if (!is_cursor) { | |
3654 | active->wm[level].plane_en[i] = is_enabled; | |
3655 | active->wm[level].plane_res_b[i] = | |
3656 | val & PLANE_WM_BLOCKS_MASK; | |
3657 | active->wm[level].plane_res_l[i] = | |
3658 | (val >> PLANE_WM_LINES_SHIFT) & | |
3659 | PLANE_WM_LINES_MASK; | |
3660 | } else { | |
3661 | active->wm[level].cursor_en = is_enabled; | |
3662 | active->wm[level].cursor_res_b = | |
3663 | val & PLANE_WM_BLOCKS_MASK; | |
3664 | active->wm[level].cursor_res_l = | |
3665 | (val >> PLANE_WM_LINES_SHIFT) & | |
3666 | PLANE_WM_LINES_MASK; | |
3667 | } | |
3668 | } else { | |
3669 | if (!is_cursor) { | |
3670 | active->trans_wm.plane_en[i] = is_enabled; | |
3671 | active->trans_wm.plane_res_b[i] = | |
3672 | val & PLANE_WM_BLOCKS_MASK; | |
3673 | active->trans_wm.plane_res_l[i] = | |
3674 | (val >> PLANE_WM_LINES_SHIFT) & | |
3675 | PLANE_WM_LINES_MASK; | |
3676 | } else { | |
3677 | active->trans_wm.cursor_en = is_enabled; | |
3678 | active->trans_wm.cursor_res_b = | |
3679 | val & PLANE_WM_BLOCKS_MASK; | |
3680 | active->trans_wm.cursor_res_l = | |
3681 | (val >> PLANE_WM_LINES_SHIFT) & | |
3682 | PLANE_WM_LINES_MASK; | |
3683 | } | |
3684 | } | |
3685 | } | |
3686 | ||
3687 | static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc) | |
3688 | { | |
3689 | struct drm_device *dev = crtc->dev; | |
3690 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3691 | struct skl_wm_values *hw = &dev_priv->wm.skl_hw; | |
3692 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); | |
3693 | struct skl_pipe_wm *active = &intel_crtc->wm.skl_active; | |
3694 | enum pipe pipe = intel_crtc->pipe; | |
3695 | int level, i, max_level; | |
3696 | uint32_t temp; | |
3697 | ||
3698 | max_level = ilk_wm_max_level(dev); | |
3699 | ||
3700 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); | |
3701 | ||
3702 | for (level = 0; level <= max_level; level++) { | |
3703 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3704 | hw->plane[pipe][i][level] = | |
3705 | I915_READ(PLANE_WM(pipe, i, level)); | |
3706 | hw->cursor[pipe][level] = I915_READ(CUR_WM(pipe, level)); | |
3707 | } | |
3708 | ||
3709 | for (i = 0; i < intel_num_planes(intel_crtc); i++) | |
3710 | hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i)); | |
3711 | hw->cursor_trans[pipe] = I915_READ(CUR_WM_TRANS(pipe)); | |
3712 | ||
3713 | if (!intel_crtc_active(crtc)) | |
3714 | return; | |
3715 | ||
3716 | hw->dirty[pipe] = true; | |
3717 | ||
3718 | active->linetime = hw->wm_linetime[pipe]; | |
3719 | ||
3720 | for (level = 0; level <= max_level; level++) { | |
3721 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3722 | temp = hw->plane[pipe][i][level]; | |
3723 | skl_pipe_wm_active_state(temp, active, false, | |
3724 | false, i, level); | |
3725 | } | |
3726 | temp = hw->cursor[pipe][level]; | |
3727 | skl_pipe_wm_active_state(temp, active, false, true, i, level); | |
3728 | } | |
3729 | ||
3730 | for (i = 0; i < intel_num_planes(intel_crtc); i++) { | |
3731 | temp = hw->plane_trans[pipe][i]; | |
3732 | skl_pipe_wm_active_state(temp, active, true, false, i, 0); | |
3733 | } | |
3734 | ||
3735 | temp = hw->cursor_trans[pipe]; | |
3736 | skl_pipe_wm_active_state(temp, active, true, true, i, 0); | |
3737 | } | |
3738 | ||
3739 | void skl_wm_get_hw_state(struct drm_device *dev) | |
3740 | { | |
3741 | struct drm_crtc *crtc; | |
3742 | ||
3743 | list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) | |
3744 | skl_pipe_wm_get_hw_state(crtc); | |
3745 | } | |
3746 | ||
243e6a44 VS |
3747 | static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc) |
3748 | { | |
3749 | struct drm_device *dev = crtc->dev; | |
3750 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3751 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3752 | struct intel_crtc *intel_crtc = to_intel_crtc(crtc); |
3753 | struct intel_pipe_wm *active = &intel_crtc->wm.active; | |
3754 | enum pipe pipe = intel_crtc->pipe; | |
3755 | static const unsigned int wm0_pipe_reg[] = { | |
3756 | [PIPE_A] = WM0_PIPEA_ILK, | |
3757 | [PIPE_B] = WM0_PIPEB_ILK, | |
3758 | [PIPE_C] = WM0_PIPEC_IVB, | |
3759 | }; | |
3760 | ||
3761 | hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]); | |
a42a5719 | 3762 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ce0e0713 | 3763 | hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe)); |
243e6a44 | 3764 | |
2a44b76b VS |
3765 | active->pipe_enabled = intel_crtc_active(crtc); |
3766 | ||
3767 | if (active->pipe_enabled) { | |
243e6a44 VS |
3768 | u32 tmp = hw->wm_pipe[pipe]; |
3769 | ||
3770 | /* | |
3771 | * For active pipes LP0 watermark is marked as | |
3772 | * enabled, and LP1+ watermaks as disabled since | |
3773 | * we can't really reverse compute them in case | |
3774 | * multiple pipes are active. | |
3775 | */ | |
3776 | active->wm[0].enable = true; | |
3777 | active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT; | |
3778 | active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT; | |
3779 | active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK; | |
3780 | active->linetime = hw->wm_linetime[pipe]; | |
3781 | } else { | |
3782 | int level, max_level = ilk_wm_max_level(dev); | |
3783 | ||
3784 | /* | |
3785 | * For inactive pipes, all watermark levels | |
3786 | * should be marked as enabled but zeroed, | |
3787 | * which is what we'd compute them to. | |
3788 | */ | |
3789 | for (level = 0; level <= max_level; level++) | |
3790 | active->wm[level].enable = true; | |
3791 | } | |
3792 | } | |
3793 | ||
3794 | void ilk_wm_get_hw_state(struct drm_device *dev) | |
3795 | { | |
3796 | struct drm_i915_private *dev_priv = dev->dev_private; | |
820c1980 | 3797 | struct ilk_wm_values *hw = &dev_priv->wm.hw; |
243e6a44 VS |
3798 | struct drm_crtc *crtc; |
3799 | ||
70e1e0ec | 3800 | for_each_crtc(dev, crtc) |
243e6a44 VS |
3801 | ilk_pipe_wm_get_hw_state(crtc); |
3802 | ||
3803 | hw->wm_lp[0] = I915_READ(WM1_LP_ILK); | |
3804 | hw->wm_lp[1] = I915_READ(WM2_LP_ILK); | |
3805 | hw->wm_lp[2] = I915_READ(WM3_LP_ILK); | |
3806 | ||
3807 | hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK); | |
cfa7698b VS |
3808 | if (INTEL_INFO(dev)->gen >= 7) { |
3809 | hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB); | |
3810 | hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB); | |
3811 | } | |
243e6a44 | 3812 | |
a42a5719 | 3813 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
ac9545fd VS |
3814 | hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ? |
3815 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
3816 | else if (IS_IVYBRIDGE(dev)) | |
3817 | hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ? | |
3818 | INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2; | |
243e6a44 VS |
3819 | |
3820 | hw->enable_fbc_wm = | |
3821 | !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS); | |
3822 | } | |
3823 | ||
b445e3b0 ED |
3824 | /** |
3825 | * intel_update_watermarks - update FIFO watermark values based on current modes | |
3826 | * | |
3827 | * Calculate watermark values for the various WM regs based on current mode | |
3828 | * and plane configuration. | |
3829 | * | |
3830 | * There are several cases to deal with here: | |
3831 | * - normal (i.e. non-self-refresh) | |
3832 | * - self-refresh (SR) mode | |
3833 | * - lines are large relative to FIFO size (buffer can hold up to 2) | |
3834 | * - lines are small relative to FIFO size (buffer can hold more than 2 | |
3835 | * lines), so need to account for TLB latency | |
3836 | * | |
3837 | * The normal calculation is: | |
3838 | * watermark = dotclock * bytes per pixel * latency | |
3839 | * where latency is platform & configuration dependent (we assume pessimal | |
3840 | * values here). | |
3841 | * | |
3842 | * The SR calculation is: | |
3843 | * watermark = (trunc(latency/line time)+1) * surface width * | |
3844 | * bytes per pixel | |
3845 | * where | |
3846 | * line time = htotal / dotclock | |
3847 | * surface width = hdisplay for normal plane and 64 for cursor | |
3848 | * and latency is assumed to be high, as above. | |
3849 | * | |
3850 | * The final value programmed to the register should always be rounded up, | |
3851 | * and include an extra 2 entries to account for clock crossings. | |
3852 | * | |
3853 | * We don't use the sprite, so we can ignore that. And on Crestline we have | |
3854 | * to set the non-SR watermarks to 8. | |
3855 | */ | |
46ba614c | 3856 | void intel_update_watermarks(struct drm_crtc *crtc) |
b445e3b0 | 3857 | { |
46ba614c | 3858 | struct drm_i915_private *dev_priv = crtc->dev->dev_private; |
b445e3b0 ED |
3859 | |
3860 | if (dev_priv->display.update_wm) | |
46ba614c | 3861 | dev_priv->display.update_wm(crtc); |
b445e3b0 ED |
3862 | } |
3863 | ||
adf3d35e VS |
3864 | void intel_update_sprite_watermarks(struct drm_plane *plane, |
3865 | struct drm_crtc *crtc, | |
ed57cb8a DL |
3866 | uint32_t sprite_width, |
3867 | uint32_t sprite_height, | |
3868 | int pixel_size, | |
39db4a4d | 3869 | bool enabled, bool scaled) |
b445e3b0 | 3870 | { |
adf3d35e | 3871 | struct drm_i915_private *dev_priv = plane->dev->dev_private; |
b445e3b0 ED |
3872 | |
3873 | if (dev_priv->display.update_sprite_wm) | |
ed57cb8a DL |
3874 | dev_priv->display.update_sprite_wm(plane, crtc, |
3875 | sprite_width, sprite_height, | |
39db4a4d | 3876 | pixel_size, enabled, scaled); |
b445e3b0 ED |
3877 | } |
3878 | ||
2b4e57bd ED |
3879 | static struct drm_i915_gem_object * |
3880 | intel_alloc_context_page(struct drm_device *dev) | |
3881 | { | |
3882 | struct drm_i915_gem_object *ctx; | |
3883 | int ret; | |
3884 | ||
3885 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
3886 | ||
3887 | ctx = i915_gem_alloc_object(dev, 4096); | |
3888 | if (!ctx) { | |
3889 | DRM_DEBUG("failed to alloc power context, RC6 disabled\n"); | |
3890 | return NULL; | |
3891 | } | |
3892 | ||
c69766f2 | 3893 | ret = i915_gem_obj_ggtt_pin(ctx, 4096, 0); |
2b4e57bd ED |
3894 | if (ret) { |
3895 | DRM_ERROR("failed to pin power context: %d\n", ret); | |
3896 | goto err_unref; | |
3897 | } | |
3898 | ||
3899 | ret = i915_gem_object_set_to_gtt_domain(ctx, 1); | |
3900 | if (ret) { | |
3901 | DRM_ERROR("failed to set-domain on power context: %d\n", ret); | |
3902 | goto err_unpin; | |
3903 | } | |
3904 | ||
3905 | return ctx; | |
3906 | ||
3907 | err_unpin: | |
d7f46fc4 | 3908 | i915_gem_object_ggtt_unpin(ctx); |
2b4e57bd ED |
3909 | err_unref: |
3910 | drm_gem_object_unreference(&ctx->base); | |
2b4e57bd ED |
3911 | return NULL; |
3912 | } | |
3913 | ||
9270388e DV |
3914 | /** |
3915 | * Lock protecting IPS related data structures | |
9270388e DV |
3916 | */ |
3917 | DEFINE_SPINLOCK(mchdev_lock); | |
3918 | ||
3919 | /* Global for IPS driver to get at the current i915 device. Protected by | |
3920 | * mchdev_lock. */ | |
3921 | static struct drm_i915_private *i915_mch_dev; | |
3922 | ||
2b4e57bd ED |
3923 | bool ironlake_set_drps(struct drm_device *dev, u8 val) |
3924 | { | |
3925 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3926 | u16 rgvswctl; | |
3927 | ||
9270388e DV |
3928 | assert_spin_locked(&mchdev_lock); |
3929 | ||
2b4e57bd ED |
3930 | rgvswctl = I915_READ16(MEMSWCTL); |
3931 | if (rgvswctl & MEMCTL_CMD_STS) { | |
3932 | DRM_DEBUG("gpu busy, RCS change rejected\n"); | |
3933 | return false; /* still busy with another command */ | |
3934 | } | |
3935 | ||
3936 | rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) | | |
3937 | (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM; | |
3938 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3939 | POSTING_READ16(MEMSWCTL); | |
3940 | ||
3941 | rgvswctl |= MEMCTL_CMD_STS; | |
3942 | I915_WRITE16(MEMSWCTL, rgvswctl); | |
3943 | ||
3944 | return true; | |
3945 | } | |
3946 | ||
8090c6b9 | 3947 | static void ironlake_enable_drps(struct drm_device *dev) |
2b4e57bd ED |
3948 | { |
3949 | struct drm_i915_private *dev_priv = dev->dev_private; | |
3950 | u32 rgvmodectl = I915_READ(MEMMODECTL); | |
3951 | u8 fmax, fmin, fstart, vstart; | |
3952 | ||
9270388e DV |
3953 | spin_lock_irq(&mchdev_lock); |
3954 | ||
2b4e57bd ED |
3955 | /* Enable temp reporting */ |
3956 | I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN); | |
3957 | I915_WRITE16(TSC1, I915_READ(TSC1) | TSE); | |
3958 | ||
3959 | /* 100ms RC evaluation intervals */ | |
3960 | I915_WRITE(RCUPEI, 100000); | |
3961 | I915_WRITE(RCDNEI, 100000); | |
3962 | ||
3963 | /* Set max/min thresholds to 90ms and 80ms respectively */ | |
3964 | I915_WRITE(RCBMAXAVG, 90000); | |
3965 | I915_WRITE(RCBMINAVG, 80000); | |
3966 | ||
3967 | I915_WRITE(MEMIHYST, 1); | |
3968 | ||
3969 | /* Set up min, max, and cur for interrupt handling */ | |
3970 | fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT; | |
3971 | fmin = (rgvmodectl & MEMMODE_FMIN_MASK); | |
3972 | fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >> | |
3973 | MEMMODE_FSTART_SHIFT; | |
3974 | ||
3975 | vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >> | |
3976 | PXVFREQ_PX_SHIFT; | |
3977 | ||
20e4d407 DV |
3978 | dev_priv->ips.fmax = fmax; /* IPS callback will increase this */ |
3979 | dev_priv->ips.fstart = fstart; | |
2b4e57bd | 3980 | |
20e4d407 DV |
3981 | dev_priv->ips.max_delay = fstart; |
3982 | dev_priv->ips.min_delay = fmin; | |
3983 | dev_priv->ips.cur_delay = fstart; | |
2b4e57bd ED |
3984 | |
3985 | DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n", | |
3986 | fmax, fmin, fstart); | |
3987 | ||
3988 | I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN); | |
3989 | ||
3990 | /* | |
3991 | * Interrupts will be enabled in ironlake_irq_postinstall | |
3992 | */ | |
3993 | ||
3994 | I915_WRITE(VIDSTART, vstart); | |
3995 | POSTING_READ(VIDSTART); | |
3996 | ||
3997 | rgvmodectl |= MEMMODE_SWMODE_EN; | |
3998 | I915_WRITE(MEMMODECTL, rgvmodectl); | |
3999 | ||
9270388e | 4000 | if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10)) |
2b4e57bd | 4001 | DRM_ERROR("stuck trying to change perf mode\n"); |
9270388e | 4002 | mdelay(1); |
2b4e57bd ED |
4003 | |
4004 | ironlake_set_drps(dev, fstart); | |
4005 | ||
20e4d407 | 4006 | dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) + |
2b4e57bd | 4007 | I915_READ(0x112e0); |
20e4d407 DV |
4008 | dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies); |
4009 | dev_priv->ips.last_count2 = I915_READ(0x112f4); | |
5ed0bdf2 | 4010 | dev_priv->ips.last_time2 = ktime_get_raw_ns(); |
9270388e DV |
4011 | |
4012 | spin_unlock_irq(&mchdev_lock); | |
2b4e57bd ED |
4013 | } |
4014 | ||
8090c6b9 | 4015 | static void ironlake_disable_drps(struct drm_device *dev) |
2b4e57bd ED |
4016 | { |
4017 | struct drm_i915_private *dev_priv = dev->dev_private; | |
9270388e DV |
4018 | u16 rgvswctl; |
4019 | ||
4020 | spin_lock_irq(&mchdev_lock); | |
4021 | ||
4022 | rgvswctl = I915_READ16(MEMSWCTL); | |
2b4e57bd ED |
4023 | |
4024 | /* Ack interrupts, disable EFC interrupt */ | |
4025 | I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN); | |
4026 | I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG); | |
4027 | I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT); | |
4028 | I915_WRITE(DEIIR, DE_PCU_EVENT); | |
4029 | I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT); | |
4030 | ||
4031 | /* Go back to the starting frequency */ | |
20e4d407 | 4032 | ironlake_set_drps(dev, dev_priv->ips.fstart); |
9270388e | 4033 | mdelay(1); |
2b4e57bd ED |
4034 | rgvswctl |= MEMCTL_CMD_STS; |
4035 | I915_WRITE(MEMSWCTL, rgvswctl); | |
9270388e | 4036 | mdelay(1); |
2b4e57bd | 4037 | |
9270388e | 4038 | spin_unlock_irq(&mchdev_lock); |
2b4e57bd ED |
4039 | } |
4040 | ||
acbe9475 DV |
4041 | /* There's a funny hw issue where the hw returns all 0 when reading from |
4042 | * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value | |
4043 | * ourselves, instead of doing a rmw cycle (which might result in us clearing | |
4044 | * all limits and the gpu stuck at whatever frequency it is at atm). | |
4045 | */ | |
6917c7b9 | 4046 | static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 val) |
2b4e57bd | 4047 | { |
7b9e0ae6 | 4048 | u32 limits; |
2b4e57bd | 4049 | |
20b46e59 DV |
4050 | /* Only set the down limit when we've reached the lowest level to avoid |
4051 | * getting more interrupts, otherwise leave this clear. This prevents a | |
4052 | * race in the hw when coming out of rc6: There's a tiny window where | |
4053 | * the hw runs at the minimal clock before selecting the desired | |
4054 | * frequency, if the down threshold expires in that window we will not | |
4055 | * receive a down interrupt. */ | |
b39fb297 BW |
4056 | limits = dev_priv->rps.max_freq_softlimit << 24; |
4057 | if (val <= dev_priv->rps.min_freq_softlimit) | |
4058 | limits |= dev_priv->rps.min_freq_softlimit << 16; | |
20b46e59 DV |
4059 | |
4060 | return limits; | |
4061 | } | |
4062 | ||
dd75fdc8 CW |
4063 | static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val) |
4064 | { | |
4065 | int new_power; | |
4066 | ||
4067 | new_power = dev_priv->rps.power; | |
4068 | switch (dev_priv->rps.power) { | |
4069 | case LOW_POWER: | |
b39fb297 | 4070 | if (val > dev_priv->rps.efficient_freq + 1 && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4071 | new_power = BETWEEN; |
4072 | break; | |
4073 | ||
4074 | case BETWEEN: | |
b39fb297 | 4075 | if (val <= dev_priv->rps.efficient_freq && val < dev_priv->rps.cur_freq) |
dd75fdc8 | 4076 | new_power = LOW_POWER; |
b39fb297 | 4077 | else if (val >= dev_priv->rps.rp0_freq && val > dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4078 | new_power = HIGH_POWER; |
4079 | break; | |
4080 | ||
4081 | case HIGH_POWER: | |
b39fb297 | 4082 | if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 && val < dev_priv->rps.cur_freq) |
dd75fdc8 CW |
4083 | new_power = BETWEEN; |
4084 | break; | |
4085 | } | |
4086 | /* Max/min bins are special */ | |
b39fb297 | 4087 | if (val == dev_priv->rps.min_freq_softlimit) |
dd75fdc8 | 4088 | new_power = LOW_POWER; |
b39fb297 | 4089 | if (val == dev_priv->rps.max_freq_softlimit) |
dd75fdc8 CW |
4090 | new_power = HIGH_POWER; |
4091 | if (new_power == dev_priv->rps.power) | |
4092 | return; | |
4093 | ||
4094 | /* Note the units here are not exactly 1us, but 1280ns. */ | |
4095 | switch (new_power) { | |
4096 | case LOW_POWER: | |
4097 | /* Upclock if more than 95% busy over 16ms */ | |
4098 | I915_WRITE(GEN6_RP_UP_EI, 12500); | |
4099 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 11800); | |
4100 | ||
4101 | /* Downclock if less than 85% busy over 32ms */ | |
4102 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
4103 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 21250); | |
4104 | ||
4105 | I915_WRITE(GEN6_RP_CONTROL, | |
4106 | GEN6_RP_MEDIA_TURBO | | |
4107 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4108 | GEN6_RP_MEDIA_IS_GFX | | |
4109 | GEN6_RP_ENABLE | | |
4110 | GEN6_RP_UP_BUSY_AVG | | |
4111 | GEN6_RP_DOWN_IDLE_AVG); | |
4112 | break; | |
4113 | ||
4114 | case BETWEEN: | |
4115 | /* Upclock if more than 90% busy over 13ms */ | |
4116 | I915_WRITE(GEN6_RP_UP_EI, 10250); | |
4117 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 9225); | |
4118 | ||
4119 | /* Downclock if less than 75% busy over 32ms */ | |
4120 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
4121 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 18750); | |
4122 | ||
4123 | I915_WRITE(GEN6_RP_CONTROL, | |
4124 | GEN6_RP_MEDIA_TURBO | | |
4125 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4126 | GEN6_RP_MEDIA_IS_GFX | | |
4127 | GEN6_RP_ENABLE | | |
4128 | GEN6_RP_UP_BUSY_AVG | | |
4129 | GEN6_RP_DOWN_IDLE_AVG); | |
4130 | break; | |
4131 | ||
4132 | case HIGH_POWER: | |
4133 | /* Upclock if more than 85% busy over 10ms */ | |
4134 | I915_WRITE(GEN6_RP_UP_EI, 8000); | |
4135 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 6800); | |
4136 | ||
4137 | /* Downclock if less than 60% busy over 32ms */ | |
4138 | I915_WRITE(GEN6_RP_DOWN_EI, 25000); | |
4139 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 15000); | |
4140 | ||
4141 | I915_WRITE(GEN6_RP_CONTROL, | |
4142 | GEN6_RP_MEDIA_TURBO | | |
4143 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4144 | GEN6_RP_MEDIA_IS_GFX | | |
4145 | GEN6_RP_ENABLE | | |
4146 | GEN6_RP_UP_BUSY_AVG | | |
4147 | GEN6_RP_DOWN_IDLE_AVG); | |
4148 | break; | |
4149 | } | |
4150 | ||
4151 | dev_priv->rps.power = new_power; | |
4152 | dev_priv->rps.last_adj = 0; | |
4153 | } | |
4154 | ||
2876ce73 CW |
4155 | static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val) |
4156 | { | |
4157 | u32 mask = 0; | |
4158 | ||
4159 | if (val > dev_priv->rps.min_freq_softlimit) | |
4160 | mask |= GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT; | |
4161 | if (val < dev_priv->rps.max_freq_softlimit) | |
4162 | mask |= GEN6_PM_RP_UP_THRESHOLD; | |
4163 | ||
7b3c29f6 CW |
4164 | mask |= dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED); |
4165 | mask &= dev_priv->pm_rps_events; | |
4166 | ||
2876ce73 CW |
4167 | /* IVB and SNB hard hangs on looping batchbuffer |
4168 | * if GEN6_PM_UP_EI_EXPIRED is masked. | |
4169 | */ | |
4170 | if (INTEL_INFO(dev_priv->dev)->gen <= 7 && !IS_HASWELL(dev_priv->dev)) | |
4171 | mask |= GEN6_PM_RP_UP_EI_EXPIRED; | |
4172 | ||
baccd458 D |
4173 | if (IS_GEN8(dev_priv->dev)) |
4174 | mask |= GEN8_PMINTR_REDIRECT_TO_NON_DISP; | |
4175 | ||
2876ce73 CW |
4176 | return ~mask; |
4177 | } | |
4178 | ||
b8a5ff8d JM |
4179 | /* gen6_set_rps is called to update the frequency request, but should also be |
4180 | * called when the range (min_delay and max_delay) is modified so that we can | |
4181 | * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */ | |
20b46e59 DV |
4182 | void gen6_set_rps(struct drm_device *dev, u8 val) |
4183 | { | |
4184 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7b9e0ae6 | 4185 | |
4fc688ce | 4186 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
4187 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
4188 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
004777cb | 4189 | |
eb64cad1 CW |
4190 | /* min/max delay may still have been modified so be sure to |
4191 | * write the limits value. | |
4192 | */ | |
4193 | if (val != dev_priv->rps.cur_freq) { | |
4194 | gen6_set_rps_thresholds(dev_priv, val); | |
b8a5ff8d | 4195 | |
50e6a2a7 | 4196 | if (IS_HASWELL(dev) || IS_BROADWELL(dev)) |
eb64cad1 CW |
4197 | I915_WRITE(GEN6_RPNSWREQ, |
4198 | HSW_FREQUENCY(val)); | |
4199 | else | |
4200 | I915_WRITE(GEN6_RPNSWREQ, | |
4201 | GEN6_FREQUENCY(val) | | |
4202 | GEN6_OFFSET(0) | | |
4203 | GEN6_AGGRESSIVE_TURBO); | |
b8a5ff8d | 4204 | } |
7b9e0ae6 | 4205 | |
7b9e0ae6 CW |
4206 | /* Make sure we continue to get interrupts |
4207 | * until we hit the minimum or maximum frequencies. | |
4208 | */ | |
eb64cad1 | 4209 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, gen6_rps_limits(dev_priv, val)); |
2876ce73 | 4210 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
7b9e0ae6 | 4211 | |
d5570a72 BW |
4212 | POSTING_READ(GEN6_RPNSWREQ); |
4213 | ||
b39fb297 | 4214 | dev_priv->rps.cur_freq = val; |
be2cde9a | 4215 | trace_intel_gpu_freq_change(val * 50); |
2b4e57bd ED |
4216 | } |
4217 | ||
76c3552f D |
4218 | /* vlv_set_rps_idle: Set the frequency to Rpn if Gfx clocks are down |
4219 | * | |
4220 | * * If Gfx is Idle, then | |
4221 | * 1. Mask Turbo interrupts | |
4222 | * 2. Bring up Gfx clock | |
4223 | * 3. Change the freq to Rpn and wait till P-Unit updates freq | |
4224 | * 4. Clear the Force GFX CLK ON bit so that Gfx can down | |
4225 | * 5. Unmask Turbo interrupts | |
4226 | */ | |
4227 | static void vlv_set_rps_idle(struct drm_i915_private *dev_priv) | |
4228 | { | |
5549d25f D |
4229 | struct drm_device *dev = dev_priv->dev; |
4230 | ||
4231 | /* Latest VLV doesn't need to force the gfx clock */ | |
4232 | if (dev->pdev->revision >= 0xd) { | |
4233 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
4234 | return; | |
4235 | } | |
4236 | ||
76c3552f D |
4237 | /* |
4238 | * When we are idle. Drop to min voltage state. | |
4239 | */ | |
4240 | ||
b39fb297 | 4241 | if (dev_priv->rps.cur_freq <= dev_priv->rps.min_freq_softlimit) |
76c3552f D |
4242 | return; |
4243 | ||
4244 | /* Mask turbo interrupt so that they will not come in between */ | |
4245 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); | |
4246 | ||
650ad970 | 4247 | vlv_force_gfx_clock(dev_priv, true); |
76c3552f | 4248 | |
b39fb297 | 4249 | dev_priv->rps.cur_freq = dev_priv->rps.min_freq_softlimit; |
76c3552f D |
4250 | |
4251 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, | |
b39fb297 | 4252 | dev_priv->rps.min_freq_softlimit); |
76c3552f D |
4253 | |
4254 | if (wait_for(((vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) | |
4255 | & GENFREQSTATUS) == 0, 5)) | |
4256 | DRM_ERROR("timed out waiting for Punit\n"); | |
4257 | ||
650ad970 | 4258 | vlv_force_gfx_clock(dev_priv, false); |
76c3552f | 4259 | |
2876ce73 CW |
4260 | I915_WRITE(GEN6_PMINTRMSK, |
4261 | gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq)); | |
76c3552f D |
4262 | } |
4263 | ||
b29c19b6 CW |
4264 | void gen6_rps_idle(struct drm_i915_private *dev_priv) |
4265 | { | |
691bb717 DL |
4266 | struct drm_device *dev = dev_priv->dev; |
4267 | ||
b29c19b6 | 4268 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4269 | if (dev_priv->rps.enabled) { |
34638118 D |
4270 | if (IS_CHERRYVIEW(dev)) |
4271 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); | |
4272 | else if (IS_VALLEYVIEW(dev)) | |
76c3552f | 4273 | vlv_set_rps_idle(dev_priv); |
7526ed79 | 4274 | else |
b39fb297 | 4275 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
c0951f0c CW |
4276 | dev_priv->rps.last_adj = 0; |
4277 | } | |
b29c19b6 CW |
4278 | mutex_unlock(&dev_priv->rps.hw_lock); |
4279 | } | |
4280 | ||
4281 | void gen6_rps_boost(struct drm_i915_private *dev_priv) | |
4282 | { | |
691bb717 DL |
4283 | struct drm_device *dev = dev_priv->dev; |
4284 | ||
b29c19b6 | 4285 | mutex_lock(&dev_priv->rps.hw_lock); |
c0951f0c | 4286 | if (dev_priv->rps.enabled) { |
691bb717 | 4287 | if (IS_VALLEYVIEW(dev)) |
b39fb297 | 4288 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
7526ed79 | 4289 | else |
b39fb297 | 4290 | gen6_set_rps(dev_priv->dev, dev_priv->rps.max_freq_softlimit); |
c0951f0c CW |
4291 | dev_priv->rps.last_adj = 0; |
4292 | } | |
b29c19b6 CW |
4293 | mutex_unlock(&dev_priv->rps.hw_lock); |
4294 | } | |
4295 | ||
0a073b84 JB |
4296 | void valleyview_set_rps(struct drm_device *dev, u8 val) |
4297 | { | |
4298 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7a67092a | 4299 | |
0a073b84 | 4300 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
b39fb297 BW |
4301 | WARN_ON(val > dev_priv->rps.max_freq_softlimit); |
4302 | WARN_ON(val < dev_priv->rps.min_freq_softlimit); | |
0a073b84 | 4303 | |
1c14762d VS |
4304 | if (WARN_ONCE(IS_CHERRYVIEW(dev) && (val & 1), |
4305 | "Odd GPU freq value\n")) | |
4306 | val &= ~1; | |
4307 | ||
67956867 VS |
4308 | if (val != dev_priv->rps.cur_freq) { |
4309 | DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n", | |
4310 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
4311 | dev_priv->rps.cur_freq, | |
4312 | vlv_gpu_freq(dev_priv, val), val); | |
4313 | ||
2876ce73 | 4314 | vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val); |
67956867 | 4315 | } |
0a073b84 | 4316 | |
09c87db8 | 4317 | I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val)); |
0a073b84 | 4318 | |
b39fb297 | 4319 | dev_priv->rps.cur_freq = val; |
2ec3815f | 4320 | trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv, val)); |
0a073b84 JB |
4321 | } |
4322 | ||
0961021a BW |
4323 | static void gen8_disable_rps_interrupts(struct drm_device *dev) |
4324 | { | |
4325 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7526ed79 DV |
4326 | |
4327 | I915_WRITE(GEN6_PMINTRMSK, ~GEN8_PMINTR_REDIRECT_TO_NON_DISP); | |
4328 | I915_WRITE(GEN8_GT_IER(2), I915_READ(GEN8_GT_IER(2)) & | |
4329 | ~dev_priv->pm_rps_events); | |
4330 | /* Complete PM interrupt masking here doesn't race with the rps work | |
4331 | * item again unmasking PM interrupts because that is using a different | |
4332 | * register (GEN8_GT_IMR(2)) to mask PM interrupts. The only risk is in | |
4333 | * leaving stale bits in GEN8_GT_IIR(2) and GEN8_GT_IMR(2) which | |
4334 | * gen8_enable_rps will clean up. */ | |
4335 | ||
4336 | spin_lock_irq(&dev_priv->irq_lock); | |
4337 | dev_priv->rps.pm_iir = 0; | |
4338 | spin_unlock_irq(&dev_priv->irq_lock); | |
4339 | ||
4340 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); | |
0961021a BW |
4341 | } |
4342 | ||
44fc7d5c | 4343 | static void gen6_disable_rps_interrupts(struct drm_device *dev) |
2b4e57bd ED |
4344 | { |
4345 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4346 | ||
2b4e57bd | 4347 | I915_WRITE(GEN6_PMINTRMSK, 0xffffffff); |
a6706b45 D |
4348 | I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & |
4349 | ~dev_priv->pm_rps_events); | |
2b4e57bd ED |
4350 | /* Complete PM interrupt masking here doesn't race with the rps work |
4351 | * item again unmasking PM interrupts because that is using a different | |
4352 | * register (PMIMR) to mask PM interrupts. The only risk is in leaving | |
4353 | * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */ | |
4354 | ||
59cdb63d | 4355 | spin_lock_irq(&dev_priv->irq_lock); |
c6a828d3 | 4356 | dev_priv->rps.pm_iir = 0; |
59cdb63d | 4357 | spin_unlock_irq(&dev_priv->irq_lock); |
2b4e57bd | 4358 | |
a6706b45 | 4359 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
2b4e57bd ED |
4360 | } |
4361 | ||
44fc7d5c | 4362 | static void gen6_disable_rps(struct drm_device *dev) |
d20d4f0c JB |
4363 | { |
4364 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4365 | ||
4366 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
44fc7d5c | 4367 | I915_WRITE(GEN6_RPNSWREQ, 1 << 31); |
d20d4f0c | 4368 | |
0961021a BW |
4369 | if (IS_BROADWELL(dev)) |
4370 | gen8_disable_rps_interrupts(dev); | |
4371 | else | |
4372 | gen6_disable_rps_interrupts(dev); | |
44fc7d5c DV |
4373 | } |
4374 | ||
38807746 D |
4375 | static void cherryview_disable_rps(struct drm_device *dev) |
4376 | { | |
4377 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4378 | ||
4379 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
3497a562 D |
4380 | |
4381 | gen8_disable_rps_interrupts(dev); | |
38807746 D |
4382 | } |
4383 | ||
44fc7d5c DV |
4384 | static void valleyview_disable_rps(struct drm_device *dev) |
4385 | { | |
4386 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4387 | ||
98a2e5f9 D |
4388 | /* we're doing forcewake before Disabling RC6, |
4389 | * This what the BIOS expects when going into suspend */ | |
4390 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
4391 | ||
44fc7d5c | 4392 | I915_WRITE(GEN6_RC_CONTROL, 0); |
d20d4f0c | 4393 | |
98a2e5f9 D |
4394 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
4395 | ||
44fc7d5c | 4396 | gen6_disable_rps_interrupts(dev); |
d20d4f0c JB |
4397 | } |
4398 | ||
dc39fff7 BW |
4399 | static void intel_print_rc6_info(struct drm_device *dev, u32 mode) |
4400 | { | |
91ca689a ID |
4401 | if (IS_VALLEYVIEW(dev)) { |
4402 | if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1))) | |
4403 | mode = GEN6_RC_CTL_RC6_ENABLE; | |
4404 | else | |
4405 | mode = 0; | |
4406 | } | |
58abf1da RV |
4407 | if (HAS_RC6p(dev)) |
4408 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s RC6p %s RC6pp %s\n", | |
4409 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off", | |
4410 | (mode & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off", | |
4411 | (mode & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off"); | |
4412 | ||
4413 | else | |
4414 | DRM_DEBUG_KMS("Enabling RC6 states: RC6 %s\n", | |
4415 | (mode & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off"); | |
dc39fff7 BW |
4416 | } |
4417 | ||
e6069ca8 | 4418 | static int sanitize_rc6_option(const struct drm_device *dev, int enable_rc6) |
2b4e57bd | 4419 | { |
eb4926e4 DL |
4420 | /* No RC6 before Ironlake */ |
4421 | if (INTEL_INFO(dev)->gen < 5) | |
4422 | return 0; | |
4423 | ||
e6069ca8 ID |
4424 | /* RC6 is only on Ironlake mobile not on desktop */ |
4425 | if (INTEL_INFO(dev)->gen == 5 && !IS_IRONLAKE_M(dev)) | |
4426 | return 0; | |
4427 | ||
456470eb | 4428 | /* Respect the kernel parameter if it is set */ |
e6069ca8 ID |
4429 | if (enable_rc6 >= 0) { |
4430 | int mask; | |
4431 | ||
58abf1da | 4432 | if (HAS_RC6p(dev)) |
e6069ca8 ID |
4433 | mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE | |
4434 | INTEL_RC6pp_ENABLE; | |
4435 | else | |
4436 | mask = INTEL_RC6_ENABLE; | |
4437 | ||
4438 | if ((enable_rc6 & mask) != enable_rc6) | |
8dfd1f04 DV |
4439 | DRM_DEBUG_KMS("Adjusting RC6 mask to %d (requested %d, valid %d)\n", |
4440 | enable_rc6 & mask, enable_rc6, mask); | |
e6069ca8 ID |
4441 | |
4442 | return enable_rc6 & mask; | |
4443 | } | |
2b4e57bd | 4444 | |
6567d748 CW |
4445 | /* Disable RC6 on Ironlake */ |
4446 | if (INTEL_INFO(dev)->gen == 5) | |
4447 | return 0; | |
2b4e57bd | 4448 | |
8bade1ad | 4449 | if (IS_IVYBRIDGE(dev)) |
cca84a1f | 4450 | return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE); |
8bade1ad BW |
4451 | |
4452 | return INTEL_RC6_ENABLE; | |
2b4e57bd ED |
4453 | } |
4454 | ||
e6069ca8 ID |
4455 | int intel_enable_rc6(const struct drm_device *dev) |
4456 | { | |
4457 | return i915.enable_rc6; | |
4458 | } | |
4459 | ||
0961021a BW |
4460 | static void gen8_enable_rps_interrupts(struct drm_device *dev) |
4461 | { | |
4462 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4463 | ||
4464 | spin_lock_irq(&dev_priv->irq_lock); | |
4465 | WARN_ON(dev_priv->rps.pm_iir); | |
480c8033 | 4466 | gen8_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
0961021a BW |
4467 | I915_WRITE(GEN8_GT_IIR(2), dev_priv->pm_rps_events); |
4468 | spin_unlock_irq(&dev_priv->irq_lock); | |
4469 | } | |
4470 | ||
44fc7d5c DV |
4471 | static void gen6_enable_rps_interrupts(struct drm_device *dev) |
4472 | { | |
4473 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4474 | ||
4475 | spin_lock_irq(&dev_priv->irq_lock); | |
a0b3335a | 4476 | WARN_ON(dev_priv->rps.pm_iir); |
480c8033 | 4477 | gen6_enable_pm_irq(dev_priv, dev_priv->pm_rps_events); |
a6706b45 | 4478 | I915_WRITE(GEN6_PMIIR, dev_priv->pm_rps_events); |
44fc7d5c | 4479 | spin_unlock_irq(&dev_priv->irq_lock); |
44fc7d5c DV |
4480 | } |
4481 | ||
3280e8b0 BW |
4482 | static void parse_rp_state_cap(struct drm_i915_private *dev_priv, u32 rp_state_cap) |
4483 | { | |
4484 | /* All of these values are in units of 50MHz */ | |
4485 | dev_priv->rps.cur_freq = 0; | |
4486 | /* static values from HW: RP0 < RPe < RP1 < RPn (min_freq) */ | |
4487 | dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff; | |
4488 | dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff; | |
4489 | dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff; | |
4490 | /* XXX: only BYT has a special efficient freq */ | |
4491 | dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq; | |
4492 | /* hw_max = RP0 until we check for overclocking */ | |
4493 | dev_priv->rps.max_freq = dev_priv->rps.rp0_freq; | |
4494 | ||
4495 | /* Preserve min/max settings in case of re-init */ | |
4496 | if (dev_priv->rps.max_freq_softlimit == 0) | |
4497 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
4498 | ||
4499 | if (dev_priv->rps.min_freq_softlimit == 0) | |
4500 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
4501 | } | |
4502 | ||
6edee7f3 BW |
4503 | static void gen8_enable_rps(struct drm_device *dev) |
4504 | { | |
4505 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 4506 | struct intel_engine_cs *ring; |
6edee7f3 BW |
4507 | uint32_t rc6_mask = 0, rp_state_cap; |
4508 | int unused; | |
4509 | ||
4510 | /* 1a: Software RC state - RC0 */ | |
4511 | I915_WRITE(GEN6_RC_STATE, 0); | |
4512 | ||
4513 | /* 1c & 1d: Get forcewake during program sequence. Although the driver | |
4514 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
c8d9a590 | 4515 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4516 | |
4517 | /* 2a: Disable RC states. */ | |
4518 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4519 | ||
4520 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); | |
3280e8b0 | 4521 | parse_rp_state_cap(dev_priv, rp_state_cap); |
6edee7f3 BW |
4522 | |
4523 | /* 2b: Program RC6 thresholds.*/ | |
4524 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
4525 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
4526 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
4527 | for_each_ring(ring, dev_priv, unused) | |
4528 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
4529 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
0d68b25e TR |
4530 | if (IS_BROADWELL(dev)) |
4531 | I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */ | |
4532 | else | |
4533 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
6edee7f3 BW |
4534 | |
4535 | /* 3: Enable RC6 */ | |
4536 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) | |
4537 | rc6_mask = GEN6_RC_CTL_RC6_ENABLE; | |
abbf9d2c | 4538 | intel_print_rc6_info(dev, rc6_mask); |
0d68b25e TR |
4539 | if (IS_BROADWELL(dev)) |
4540 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4541 | GEN7_RC_CTL_TO_MODE | | |
4542 | rc6_mask); | |
4543 | else | |
4544 | I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE | | |
4545 | GEN6_RC_CTL_EI_MODE(1) | | |
4546 | rc6_mask); | |
6edee7f3 BW |
4547 | |
4548 | /* 4 Program defaults and thresholds for RPS*/ | |
f9bdc585 BW |
4549 | I915_WRITE(GEN6_RPNSWREQ, |
4550 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
4551 | I915_WRITE(GEN6_RC_VIDEO_FREQ, | |
4552 | HSW_FREQUENCY(dev_priv->rps.rp1_freq)); | |
7526ed79 DV |
4553 | /* NB: Docs say 1s, and 1000000 - which aren't equivalent */ |
4554 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */ | |
4555 | ||
4556 | /* Docs recommend 900MHz, and 300 MHz respectively */ | |
4557 | I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, | |
4558 | dev_priv->rps.max_freq_softlimit << 24 | | |
4559 | dev_priv->rps.min_freq_softlimit << 16); | |
4560 | ||
4561 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */ | |
4562 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/ | |
4563 | I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */ | |
4564 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */ | |
4565 | ||
4566 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
6edee7f3 BW |
4567 | |
4568 | /* 5: Enable RPS */ | |
7526ed79 DV |
4569 | I915_WRITE(GEN6_RP_CONTROL, |
4570 | GEN6_RP_MEDIA_TURBO | | |
4571 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
4572 | GEN6_RP_MEDIA_IS_GFX | | |
4573 | GEN6_RP_ENABLE | | |
4574 | GEN6_RP_UP_BUSY_AVG | | |
4575 | GEN6_RP_DOWN_IDLE_AVG); | |
4576 | ||
4577 | /* 6: Ring frequency + overclocking (our driver does this later */ | |
4578 | ||
6edee7f3 | 4579 | gen6_set_rps(dev, (I915_READ(GEN6_GT_PERF_STATUS) & 0xff00) >> 8); |
7526ed79 DV |
4580 | |
4581 | gen8_enable_rps_interrupts(dev); | |
6edee7f3 | 4582 | |
c8d9a590 | 4583 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
6edee7f3 BW |
4584 | } |
4585 | ||
79f5b2c7 | 4586 | static void gen6_enable_rps(struct drm_device *dev) |
2b4e57bd | 4587 | { |
79f5b2c7 | 4588 | struct drm_i915_private *dev_priv = dev->dev_private; |
a4872ba6 | 4589 | struct intel_engine_cs *ring; |
2a5913a8 | 4590 | u32 rp_state_cap; |
d060c169 | 4591 | u32 rc6vids, pcu_mbox = 0, rc6_mask = 0; |
2b4e57bd | 4592 | u32 gtfifodbg; |
2b4e57bd | 4593 | int rc6_mode; |
42c0526c | 4594 | int i, ret; |
2b4e57bd | 4595 | |
4fc688ce | 4596 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4597 | |
2b4e57bd ED |
4598 | /* Here begins a magic sequence of register writes to enable |
4599 | * auto-downclocking. | |
4600 | * | |
4601 | * Perhaps there might be some value in exposing these to | |
4602 | * userspace... | |
4603 | */ | |
4604 | I915_WRITE(GEN6_RC_STATE, 0); | |
2b4e57bd ED |
4605 | |
4606 | /* Clear the DBG now so we don't confuse earlier errors */ | |
4607 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { | |
4608 | DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg); | |
4609 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
4610 | } | |
4611 | ||
c8d9a590 | 4612 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); |
2b4e57bd | 4613 | |
7b9e0ae6 | 4614 | rp_state_cap = I915_READ(GEN6_RP_STATE_CAP); |
7b9e0ae6 | 4615 | |
3280e8b0 | 4616 | parse_rp_state_cap(dev_priv, rp_state_cap); |
dd0a1aa1 | 4617 | |
2b4e57bd ED |
4618 | /* disable the counters and set deterministic thresholds */ |
4619 | I915_WRITE(GEN6_RC_CONTROL, 0); | |
4620 | ||
4621 | I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16); | |
4622 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30); | |
4623 | I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30); | |
4624 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
4625 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
4626 | ||
b4519513 CW |
4627 | for_each_ring(ring, dev_priv, i) |
4628 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
2b4e57bd ED |
4629 | |
4630 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
4631 | I915_WRITE(GEN6_RC1e_THRESHOLD, 1000); | |
29c78f60 | 4632 | if (IS_IVYBRIDGE(dev)) |
351aa566 SM |
4633 | I915_WRITE(GEN6_RC6_THRESHOLD, 125000); |
4634 | else | |
4635 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); | |
0920a487 | 4636 | I915_WRITE(GEN6_RC6p_THRESHOLD, 150000); |
2b4e57bd ED |
4637 | I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */ |
4638 | ||
5a7dc92a | 4639 | /* Check if we are enabling RC6 */ |
2b4e57bd ED |
4640 | rc6_mode = intel_enable_rc6(dev_priv->dev); |
4641 | if (rc6_mode & INTEL_RC6_ENABLE) | |
4642 | rc6_mask |= GEN6_RC_CTL_RC6_ENABLE; | |
4643 | ||
5a7dc92a ED |
4644 | /* We don't use those on Haswell */ |
4645 | if (!IS_HASWELL(dev)) { | |
4646 | if (rc6_mode & INTEL_RC6p_ENABLE) | |
4647 | rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE; | |
2b4e57bd | 4648 | |
5a7dc92a ED |
4649 | if (rc6_mode & INTEL_RC6pp_ENABLE) |
4650 | rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE; | |
4651 | } | |
2b4e57bd | 4652 | |
dc39fff7 | 4653 | intel_print_rc6_info(dev, rc6_mask); |
2b4e57bd ED |
4654 | |
4655 | I915_WRITE(GEN6_RC_CONTROL, | |
4656 | rc6_mask | | |
4657 | GEN6_RC_CTL_EI_MODE(1) | | |
4658 | GEN6_RC_CTL_HW_ENABLE); | |
4659 | ||
dd75fdc8 CW |
4660 | /* Power down if completely idle for over 50ms */ |
4661 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000); | |
2b4e57bd | 4662 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); |
2b4e57bd | 4663 | |
42c0526c | 4664 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0); |
d060c169 | 4665 | if (ret) |
42c0526c | 4666 | DRM_DEBUG_DRIVER("Failed to set the min frequency\n"); |
d060c169 BW |
4667 | |
4668 | ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox); | |
4669 | if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */ | |
4670 | DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n", | |
b39fb297 | 4671 | (dev_priv->rps.max_freq_softlimit & 0xff) * 50, |
d060c169 | 4672 | (pcu_mbox & 0xff) * 50); |
b39fb297 | 4673 | dev_priv->rps.max_freq = pcu_mbox & 0xff; |
2b4e57bd ED |
4674 | } |
4675 | ||
dd75fdc8 | 4676 | dev_priv->rps.power = HIGH_POWER; /* force a reset */ |
b39fb297 | 4677 | gen6_set_rps(dev_priv->dev, dev_priv->rps.min_freq_softlimit); |
2b4e57bd | 4678 | |
44fc7d5c | 4679 | gen6_enable_rps_interrupts(dev); |
2b4e57bd | 4680 | |
31643d54 BW |
4681 | rc6vids = 0; |
4682 | ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids); | |
4683 | if (IS_GEN6(dev) && ret) { | |
4684 | DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n"); | |
4685 | } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) { | |
4686 | DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n", | |
4687 | GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450); | |
4688 | rc6vids &= 0xffff00; | |
4689 | rc6vids |= GEN6_ENCODE_RC6_VID(450); | |
4690 | ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids); | |
4691 | if (ret) | |
4692 | DRM_ERROR("Couldn't fix incorrect rc6 voltage\n"); | |
4693 | } | |
4694 | ||
c8d9a590 | 4695 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
2b4e57bd ED |
4696 | } |
4697 | ||
c2bc2fc5 | 4698 | static void __gen6_update_ring_freq(struct drm_device *dev) |
2b4e57bd | 4699 | { |
79f5b2c7 | 4700 | struct drm_i915_private *dev_priv = dev->dev_private; |
2b4e57bd | 4701 | int min_freq = 15; |
3ebecd07 CW |
4702 | unsigned int gpu_freq; |
4703 | unsigned int max_ia_freq, min_ring_freq; | |
2b4e57bd | 4704 | int scaling_factor = 180; |
eda79642 | 4705 | struct cpufreq_policy *policy; |
2b4e57bd | 4706 | |
4fc688ce | 4707 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
79f5b2c7 | 4708 | |
eda79642 BW |
4709 | policy = cpufreq_cpu_get(0); |
4710 | if (policy) { | |
4711 | max_ia_freq = policy->cpuinfo.max_freq; | |
4712 | cpufreq_cpu_put(policy); | |
4713 | } else { | |
4714 | /* | |
4715 | * Default to measured freq if none found, PCU will ensure we | |
4716 | * don't go over | |
4717 | */ | |
2b4e57bd | 4718 | max_ia_freq = tsc_khz; |
eda79642 | 4719 | } |
2b4e57bd ED |
4720 | |
4721 | /* Convert from kHz to MHz */ | |
4722 | max_ia_freq /= 1000; | |
4723 | ||
153b4b95 | 4724 | min_ring_freq = I915_READ(DCLK) & 0xf; |
f6aca45c BW |
4725 | /* convert DDR frequency from units of 266.6MHz to bandwidth */ |
4726 | min_ring_freq = mult_frac(min_ring_freq, 8, 3); | |
3ebecd07 | 4727 | |
2b4e57bd ED |
4728 | /* |
4729 | * For each potential GPU frequency, load a ring frequency we'd like | |
4730 | * to use for memory access. We do this by specifying the IA frequency | |
4731 | * the PCU should use as a reference to determine the ring frequency. | |
4732 | */ | |
b39fb297 | 4733 | for (gpu_freq = dev_priv->rps.max_freq_softlimit; gpu_freq >= dev_priv->rps.min_freq_softlimit; |
2b4e57bd | 4734 | gpu_freq--) { |
b39fb297 | 4735 | int diff = dev_priv->rps.max_freq_softlimit - gpu_freq; |
3ebecd07 CW |
4736 | unsigned int ia_freq = 0, ring_freq = 0; |
4737 | ||
46c764d4 BW |
4738 | if (INTEL_INFO(dev)->gen >= 8) { |
4739 | /* max(2 * GT, DDR). NB: GT is 50MHz units */ | |
4740 | ring_freq = max(min_ring_freq, gpu_freq); | |
4741 | } else if (IS_HASWELL(dev)) { | |
f6aca45c | 4742 | ring_freq = mult_frac(gpu_freq, 5, 4); |
3ebecd07 CW |
4743 | ring_freq = max(min_ring_freq, ring_freq); |
4744 | /* leave ia_freq as the default, chosen by cpufreq */ | |
4745 | } else { | |
4746 | /* On older processors, there is no separate ring | |
4747 | * clock domain, so in order to boost the bandwidth | |
4748 | * of the ring, we need to upclock the CPU (ia_freq). | |
4749 | * | |
4750 | * For GPU frequencies less than 750MHz, | |
4751 | * just use the lowest ring freq. | |
4752 | */ | |
4753 | if (gpu_freq < min_freq) | |
4754 | ia_freq = 800; | |
4755 | else | |
4756 | ia_freq = max_ia_freq - ((diff * scaling_factor) / 2); | |
4757 | ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100); | |
4758 | } | |
2b4e57bd | 4759 | |
42c0526c BW |
4760 | sandybridge_pcode_write(dev_priv, |
4761 | GEN6_PCODE_WRITE_MIN_FREQ_TABLE, | |
3ebecd07 CW |
4762 | ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT | |
4763 | ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT | | |
4764 | gpu_freq); | |
2b4e57bd | 4765 | } |
2b4e57bd ED |
4766 | } |
4767 | ||
c2bc2fc5 ID |
4768 | void gen6_update_ring_freq(struct drm_device *dev) |
4769 | { | |
4770 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4771 | ||
4772 | if (INTEL_INFO(dev)->gen < 6 || IS_VALLEYVIEW(dev)) | |
4773 | return; | |
4774 | ||
4775 | mutex_lock(&dev_priv->rps.hw_lock); | |
4776 | __gen6_update_ring_freq(dev); | |
4777 | mutex_unlock(&dev_priv->rps.hw_lock); | |
4778 | } | |
4779 | ||
03af2045 | 4780 | static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
4781 | { |
4782 | u32 val, rp0; | |
4783 | ||
4784 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4785 | rp0 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4786 | ||
4787 | return rp0; | |
4788 | } | |
4789 | ||
4790 | static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4791 | { | |
4792 | u32 val, rpe; | |
4793 | ||
4794 | val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG); | |
4795 | rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK; | |
4796 | ||
4797 | return rpe; | |
4798 | } | |
4799 | ||
7707df4a D |
4800 | static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4801 | { | |
4802 | u32 val, rp1; | |
4803 | ||
4804 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
4805 | rp1 = (val >> PUNIT_GPU_STATUS_MAX_FREQ_SHIFT) & PUNIT_GPU_STATUS_MAX_FREQ_MASK; | |
4806 | ||
4807 | return rp1; | |
4808 | } | |
4809 | ||
03af2045 | 4810 | static int cherryview_rps_min_freq(struct drm_i915_private *dev_priv) |
2b6b3a09 D |
4811 | { |
4812 | u32 val, rpn; | |
4813 | ||
4814 | val = vlv_punit_read(dev_priv, PUNIT_GPU_STATUS_REG); | |
4815 | rpn = (val >> PUNIT_GPU_STATIS_GFX_MIN_FREQ_SHIFT) & PUNIT_GPU_STATUS_GFX_MIN_FREQ_MASK; | |
4816 | return rpn; | |
4817 | } | |
4818 | ||
f8f2b001 D |
4819 | static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv) |
4820 | { | |
4821 | u32 val, rp1; | |
4822 | ||
4823 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); | |
4824 | ||
4825 | rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT; | |
4826 | ||
4827 | return rp1; | |
4828 | } | |
4829 | ||
03af2045 | 4830 | static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv) |
0a073b84 JB |
4831 | { |
4832 | u32 val, rp0; | |
4833 | ||
64936258 | 4834 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE); |
0a073b84 JB |
4835 | |
4836 | rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT; | |
4837 | /* Clamp to max */ | |
4838 | rp0 = min_t(u32, rp0, 0xea); | |
4839 | ||
4840 | return rp0; | |
4841 | } | |
4842 | ||
4843 | static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv) | |
4844 | { | |
4845 | u32 val, rpe; | |
4846 | ||
64936258 | 4847 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO); |
0a073b84 | 4848 | rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT; |
64936258 | 4849 | val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI); |
0a073b84 JB |
4850 | rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5; |
4851 | ||
4852 | return rpe; | |
4853 | } | |
4854 | ||
03af2045 | 4855 | static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv) |
0a073b84 | 4856 | { |
64936258 | 4857 | return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff; |
0a073b84 JB |
4858 | } |
4859 | ||
ae48434c ID |
4860 | /* Check that the pctx buffer wasn't move under us. */ |
4861 | static void valleyview_check_pctx(struct drm_i915_private *dev_priv) | |
4862 | { | |
4863 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4864 | ||
4865 | WARN_ON(pctx_addr != dev_priv->mm.stolen_base + | |
4866 | dev_priv->vlv_pctx->stolen->start); | |
4867 | } | |
4868 | ||
38807746 D |
4869 | |
4870 | /* Check that the pcbr address is not empty. */ | |
4871 | static void cherryview_check_pctx(struct drm_i915_private *dev_priv) | |
4872 | { | |
4873 | unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095; | |
4874 | ||
4875 | WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0); | |
4876 | } | |
4877 | ||
4878 | static void cherryview_setup_pctx(struct drm_device *dev) | |
4879 | { | |
4880 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4881 | unsigned long pctx_paddr, paddr; | |
4882 | struct i915_gtt *gtt = &dev_priv->gtt; | |
4883 | u32 pcbr; | |
4884 | int pctx_size = 32*1024; | |
4885 | ||
4886 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); | |
4887 | ||
4888 | pcbr = I915_READ(VLV_PCBR); | |
4889 | if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) { | |
4890 | paddr = (dev_priv->mm.stolen_base + | |
4891 | (gtt->stolen_size - pctx_size)); | |
4892 | ||
4893 | pctx_paddr = (paddr & (~4095)); | |
4894 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4895 | } | |
4896 | } | |
4897 | ||
c9cddffc JB |
4898 | static void valleyview_setup_pctx(struct drm_device *dev) |
4899 | { | |
4900 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4901 | struct drm_i915_gem_object *pctx; | |
4902 | unsigned long pctx_paddr; | |
4903 | u32 pcbr; | |
4904 | int pctx_size = 24*1024; | |
4905 | ||
17b0c1f7 ID |
4906 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
4907 | ||
c9cddffc JB |
4908 | pcbr = I915_READ(VLV_PCBR); |
4909 | if (pcbr) { | |
4910 | /* BIOS set it up already, grab the pre-alloc'd space */ | |
4911 | int pcbr_offset; | |
4912 | ||
4913 | pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base; | |
4914 | pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev, | |
4915 | pcbr_offset, | |
190d6cd5 | 4916 | I915_GTT_OFFSET_NONE, |
c9cddffc JB |
4917 | pctx_size); |
4918 | goto out; | |
4919 | } | |
4920 | ||
4921 | /* | |
4922 | * From the Gunit register HAS: | |
4923 | * The Gfx driver is expected to program this register and ensure | |
4924 | * proper allocation within Gfx stolen memory. For example, this | |
4925 | * register should be programmed such than the PCBR range does not | |
4926 | * overlap with other ranges, such as the frame buffer, protected | |
4927 | * memory, or any other relevant ranges. | |
4928 | */ | |
4929 | pctx = i915_gem_object_create_stolen(dev, pctx_size); | |
4930 | if (!pctx) { | |
4931 | DRM_DEBUG("not enough stolen space for PCTX, disabling\n"); | |
4932 | return; | |
4933 | } | |
4934 | ||
4935 | pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start; | |
4936 | I915_WRITE(VLV_PCBR, pctx_paddr); | |
4937 | ||
4938 | out: | |
4939 | dev_priv->vlv_pctx = pctx; | |
4940 | } | |
4941 | ||
ae48434c ID |
4942 | static void valleyview_cleanup_pctx(struct drm_device *dev) |
4943 | { | |
4944 | struct drm_i915_private *dev_priv = dev->dev_private; | |
4945 | ||
4946 | if (WARN_ON(!dev_priv->vlv_pctx)) | |
4947 | return; | |
4948 | ||
4949 | drm_gem_object_unreference(&dev_priv->vlv_pctx->base); | |
4950 | dev_priv->vlv_pctx = NULL; | |
4951 | } | |
4952 | ||
4e80519e ID |
4953 | static void valleyview_init_gt_powersave(struct drm_device *dev) |
4954 | { | |
4955 | struct drm_i915_private *dev_priv = dev->dev_private; | |
2bb25c17 | 4956 | u32 val; |
4e80519e ID |
4957 | |
4958 | valleyview_setup_pctx(dev); | |
4959 | ||
4960 | mutex_lock(&dev_priv->rps.hw_lock); | |
4961 | ||
2bb25c17 VS |
4962 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
4963 | switch ((val >> 6) & 3) { | |
4964 | case 0: | |
4965 | case 1: | |
4966 | dev_priv->mem_freq = 800; | |
4967 | break; | |
4968 | case 2: | |
4969 | dev_priv->mem_freq = 1066; | |
4970 | break; | |
4971 | case 3: | |
4972 | dev_priv->mem_freq = 1333; | |
4973 | break; | |
4974 | } | |
4975 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
4976 | ||
4e80519e ID |
4977 | dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv); |
4978 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
4979 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
4980 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
4981 | dev_priv->rps.max_freq); | |
4982 | ||
4983 | dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv); | |
4984 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
4985 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
4986 | dev_priv->rps.efficient_freq); | |
4987 | ||
f8f2b001 D |
4988 | dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv); |
4989 | DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n", | |
4990 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
4991 | dev_priv->rps.rp1_freq); | |
4992 | ||
4e80519e ID |
4993 | dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv); |
4994 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
4995 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
4996 | dev_priv->rps.min_freq); | |
4997 | ||
4998 | /* Preserve min/max settings in case of re-init */ | |
4999 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5000 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5001 | ||
5002 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5003 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5004 | ||
5005 | mutex_unlock(&dev_priv->rps.hw_lock); | |
5006 | } | |
5007 | ||
38807746 D |
5008 | static void cherryview_init_gt_powersave(struct drm_device *dev) |
5009 | { | |
2b6b3a09 | 5010 | struct drm_i915_private *dev_priv = dev->dev_private; |
2bb25c17 | 5011 | u32 val; |
2b6b3a09 | 5012 | |
38807746 | 5013 | cherryview_setup_pctx(dev); |
2b6b3a09 D |
5014 | |
5015 | mutex_lock(&dev_priv->rps.hw_lock); | |
5016 | ||
2bb25c17 VS |
5017 | val = vlv_punit_read(dev_priv, CCK_FUSE_REG); |
5018 | switch ((val >> 2) & 0x7) { | |
5019 | case 0: | |
5020 | case 1: | |
5021 | dev_priv->rps.cz_freq = 200; | |
5022 | dev_priv->mem_freq = 1600; | |
5023 | break; | |
5024 | case 2: | |
5025 | dev_priv->rps.cz_freq = 267; | |
5026 | dev_priv->mem_freq = 1600; | |
5027 | break; | |
5028 | case 3: | |
5029 | dev_priv->rps.cz_freq = 333; | |
5030 | dev_priv->mem_freq = 2000; | |
5031 | break; | |
5032 | case 4: | |
5033 | dev_priv->rps.cz_freq = 320; | |
5034 | dev_priv->mem_freq = 1600; | |
5035 | break; | |
5036 | case 5: | |
5037 | dev_priv->rps.cz_freq = 400; | |
5038 | dev_priv->mem_freq = 1600; | |
5039 | break; | |
5040 | } | |
5041 | DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq); | |
5042 | ||
2b6b3a09 D |
5043 | dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv); |
5044 | dev_priv->rps.rp0_freq = dev_priv->rps.max_freq; | |
5045 | DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n", | |
5046 | vlv_gpu_freq(dev_priv, dev_priv->rps.max_freq), | |
5047 | dev_priv->rps.max_freq); | |
5048 | ||
5049 | dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv); | |
5050 | DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n", | |
5051 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
5052 | dev_priv->rps.efficient_freq); | |
5053 | ||
7707df4a D |
5054 | dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv); |
5055 | DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n", | |
5056 | vlv_gpu_freq(dev_priv, dev_priv->rps.rp1_freq), | |
5057 | dev_priv->rps.rp1_freq); | |
5058 | ||
2b6b3a09 D |
5059 | dev_priv->rps.min_freq = cherryview_rps_min_freq(dev_priv); |
5060 | DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n", | |
5061 | vlv_gpu_freq(dev_priv, dev_priv->rps.min_freq), | |
5062 | dev_priv->rps.min_freq); | |
5063 | ||
1c14762d VS |
5064 | WARN_ONCE((dev_priv->rps.max_freq | |
5065 | dev_priv->rps.efficient_freq | | |
5066 | dev_priv->rps.rp1_freq | | |
5067 | dev_priv->rps.min_freq) & 1, | |
5068 | "Odd GPU freq values\n"); | |
5069 | ||
2b6b3a09 D |
5070 | /* Preserve min/max settings in case of re-init */ |
5071 | if (dev_priv->rps.max_freq_softlimit == 0) | |
5072 | dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq; | |
5073 | ||
5074 | if (dev_priv->rps.min_freq_softlimit == 0) | |
5075 | dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq; | |
5076 | ||
5077 | mutex_unlock(&dev_priv->rps.hw_lock); | |
38807746 D |
5078 | } |
5079 | ||
4e80519e ID |
5080 | static void valleyview_cleanup_gt_powersave(struct drm_device *dev) |
5081 | { | |
5082 | valleyview_cleanup_pctx(dev); | |
5083 | } | |
5084 | ||
38807746 D |
5085 | static void cherryview_enable_rps(struct drm_device *dev) |
5086 | { | |
5087 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5088 | struct intel_engine_cs *ring; | |
2b6b3a09 | 5089 | u32 gtfifodbg, val, rc6_mode = 0, pcbr; |
38807746 D |
5090 | int i; |
5091 | ||
5092 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5093 | ||
5094 | gtfifodbg = I915_READ(GTFIFODBG); | |
5095 | if (gtfifodbg) { | |
5096 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", | |
5097 | gtfifodbg); | |
5098 | I915_WRITE(GTFIFODBG, gtfifodbg); | |
5099 | } | |
5100 | ||
5101 | cherryview_check_pctx(dev_priv); | |
5102 | ||
5103 | /* 1a & 1b: Get forcewake during program sequence. Although the driver | |
5104 | * hasn't enabled a state yet where we need forcewake, BIOS may have.*/ | |
5105 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
5106 | ||
5107 | /* 2a: Program RC6 thresholds.*/ | |
5108 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16); | |
5109 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */ | |
5110 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */ | |
5111 | ||
5112 | for_each_ring(ring, dev_priv, i) | |
5113 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5114 | I915_WRITE(GEN6_RC_SLEEP, 0); | |
5115 | ||
5116 | I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */ | |
5117 | ||
5118 | /* allows RC6 residency counter to work */ | |
5119 | I915_WRITE(VLV_COUNTER_CONTROL, | |
5120 | _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH | | |
5121 | VLV_MEDIA_RC6_COUNT_EN | | |
5122 | VLV_RENDER_RC6_COUNT_EN)); | |
5123 | ||
5124 | /* For now we assume BIOS is allocating and populating the PCBR */ | |
5125 | pcbr = I915_READ(VLV_PCBR); | |
5126 | ||
5127 | DRM_DEBUG_DRIVER("PCBR offset : 0x%x\n", pcbr); | |
5128 | ||
5129 | /* 3: Enable RC6 */ | |
5130 | if ((intel_enable_rc6(dev) & INTEL_RC6_ENABLE) && | |
5131 | (pcbr >> VLV_PCBR_ADDR_SHIFT)) | |
5132 | rc6_mode = GEN6_RC_CTL_EI_MODE(1); | |
5133 | ||
5134 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); | |
5135 | ||
2b6b3a09 D |
5136 | /* 4 Program defaults and thresholds for RPS*/ |
5137 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
5138 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5139 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5140 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5141 | ||
5142 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
5143 | ||
7405f42c TR |
5144 | /* WaDisablePwrmtrEvent:chv (pre-production hw) */ |
5145 | I915_WRITE(0xA80C, I915_READ(0xA80C) & 0x00ffffff); | |
5146 | I915_WRITE(0xA810, I915_READ(0xA810) & 0xffffff00); | |
5147 | ||
2b6b3a09 D |
5148 | /* 5: Enable RPS */ |
5149 | I915_WRITE(GEN6_RP_CONTROL, | |
5150 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
7405f42c | 5151 | GEN6_RP_MEDIA_IS_GFX | /* WaSetMaskForGfxBusyness:chv (pre-production hw ?) */ |
2b6b3a09 D |
5152 | GEN6_RP_ENABLE | |
5153 | GEN6_RP_UP_BUSY_AVG | | |
5154 | GEN6_RP_DOWN_IDLE_AVG); | |
5155 | ||
5156 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); | |
5157 | ||
5158 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
5159 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
5160 | ||
5161 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; | |
5162 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", | |
5163 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), | |
5164 | dev_priv->rps.cur_freq); | |
5165 | ||
5166 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", | |
5167 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), | |
5168 | dev_priv->rps.efficient_freq); | |
5169 | ||
5170 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); | |
5171 | ||
3497a562 D |
5172 | gen8_enable_rps_interrupts(dev); |
5173 | ||
38807746 D |
5174 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
5175 | } | |
5176 | ||
0a073b84 JB |
5177 | static void valleyview_enable_rps(struct drm_device *dev) |
5178 | { | |
5179 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5180 | struct intel_engine_cs *ring; |
2a5913a8 | 5181 | u32 gtfifodbg, val, rc6_mode = 0; |
0a073b84 JB |
5182 | int i; |
5183 | ||
5184 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); | |
5185 | ||
ae48434c ID |
5186 | valleyview_check_pctx(dev_priv); |
5187 | ||
0a073b84 | 5188 | if ((gtfifodbg = I915_READ(GTFIFODBG))) { |
f7d85c1e JB |
5189 | DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n", |
5190 | gtfifodbg); | |
0a073b84 JB |
5191 | I915_WRITE(GTFIFODBG, gtfifodbg); |
5192 | } | |
5193 | ||
c8d9a590 D |
5194 | /* If VLV, Forcewake all wells, else re-direct to regular path */ |
5195 | gen6_gt_force_wake_get(dev_priv, FORCEWAKE_ALL); | |
0a073b84 JB |
5196 | |
5197 | I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400); | |
5198 | I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000); | |
5199 | I915_WRITE(GEN6_RP_UP_EI, 66000); | |
5200 | I915_WRITE(GEN6_RP_DOWN_EI, 350000); | |
5201 | ||
5202 | I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10); | |
31685c25 | 5203 | I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 0xf4240); |
0a073b84 JB |
5204 | |
5205 | I915_WRITE(GEN6_RP_CONTROL, | |
5206 | GEN6_RP_MEDIA_TURBO | | |
5207 | GEN6_RP_MEDIA_HW_NORMAL_MODE | | |
5208 | GEN6_RP_MEDIA_IS_GFX | | |
5209 | GEN6_RP_ENABLE | | |
5210 | GEN6_RP_UP_BUSY_AVG | | |
5211 | GEN6_RP_DOWN_IDLE_CONT); | |
5212 | ||
5213 | I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000); | |
5214 | I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); | |
5215 | I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); | |
5216 | ||
5217 | for_each_ring(ring, dev_priv, i) | |
5218 | I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10); | |
5219 | ||
2f0aa304 | 5220 | I915_WRITE(GEN6_RC6_THRESHOLD, 0x557); |
0a073b84 JB |
5221 | |
5222 | /* allows RC6 residency counter to work */ | |
49798eb2 | 5223 | I915_WRITE(VLV_COUNTER_CONTROL, |
31685c25 D |
5224 | _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN | |
5225 | VLV_RENDER_RC0_COUNT_EN | | |
49798eb2 JB |
5226 | VLV_MEDIA_RC6_COUNT_EN | |
5227 | VLV_RENDER_RC6_COUNT_EN)); | |
31685c25 | 5228 | |
a2b23fe0 | 5229 | if (intel_enable_rc6(dev) & INTEL_RC6_ENABLE) |
6b88f295 | 5230 | rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL; |
dc39fff7 BW |
5231 | |
5232 | intel_print_rc6_info(dev, rc6_mode); | |
5233 | ||
a2b23fe0 | 5234 | I915_WRITE(GEN6_RC_CONTROL, rc6_mode); |
0a073b84 | 5235 | |
64936258 | 5236 | val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS); |
0a073b84 JB |
5237 | |
5238 | DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no"); | |
5239 | DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val); | |
5240 | ||
b39fb297 | 5241 | dev_priv->rps.cur_freq = (val >> 8) & 0xff; |
73008b98 | 5242 | DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n", |
b39fb297 BW |
5243 | vlv_gpu_freq(dev_priv, dev_priv->rps.cur_freq), |
5244 | dev_priv->rps.cur_freq); | |
0a073b84 | 5245 | |
73008b98 | 5246 | DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n", |
b39fb297 BW |
5247 | vlv_gpu_freq(dev_priv, dev_priv->rps.efficient_freq), |
5248 | dev_priv->rps.efficient_freq); | |
0a073b84 | 5249 | |
b39fb297 | 5250 | valleyview_set_rps(dev_priv->dev, dev_priv->rps.efficient_freq); |
0a073b84 | 5251 | |
44fc7d5c | 5252 | gen6_enable_rps_interrupts(dev); |
0a073b84 | 5253 | |
c8d9a590 | 5254 | gen6_gt_force_wake_put(dev_priv, FORCEWAKE_ALL); |
0a073b84 JB |
5255 | } |
5256 | ||
930ebb46 | 5257 | void ironlake_teardown_rc6(struct drm_device *dev) |
2b4e57bd ED |
5258 | { |
5259 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5260 | ||
3e373948 | 5261 | if (dev_priv->ips.renderctx) { |
d7f46fc4 | 5262 | i915_gem_object_ggtt_unpin(dev_priv->ips.renderctx); |
3e373948 DV |
5263 | drm_gem_object_unreference(&dev_priv->ips.renderctx->base); |
5264 | dev_priv->ips.renderctx = NULL; | |
2b4e57bd ED |
5265 | } |
5266 | ||
3e373948 | 5267 | if (dev_priv->ips.pwrctx) { |
d7f46fc4 | 5268 | i915_gem_object_ggtt_unpin(dev_priv->ips.pwrctx); |
3e373948 DV |
5269 | drm_gem_object_unreference(&dev_priv->ips.pwrctx->base); |
5270 | dev_priv->ips.pwrctx = NULL; | |
2b4e57bd ED |
5271 | } |
5272 | } | |
5273 | ||
930ebb46 | 5274 | static void ironlake_disable_rc6(struct drm_device *dev) |
2b4e57bd ED |
5275 | { |
5276 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5277 | ||
5278 | if (I915_READ(PWRCTXA)) { | |
5279 | /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */ | |
5280 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT); | |
5281 | wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON), | |
5282 | 50); | |
5283 | ||
5284 | I915_WRITE(PWRCTXA, 0); | |
5285 | POSTING_READ(PWRCTXA); | |
5286 | ||
5287 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); | |
5288 | POSTING_READ(RSTDBYCTL); | |
5289 | } | |
2b4e57bd ED |
5290 | } |
5291 | ||
5292 | static int ironlake_setup_rc6(struct drm_device *dev) | |
5293 | { | |
5294 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5295 | ||
3e373948 DV |
5296 | if (dev_priv->ips.renderctx == NULL) |
5297 | dev_priv->ips.renderctx = intel_alloc_context_page(dev); | |
5298 | if (!dev_priv->ips.renderctx) | |
2b4e57bd ED |
5299 | return -ENOMEM; |
5300 | ||
3e373948 DV |
5301 | if (dev_priv->ips.pwrctx == NULL) |
5302 | dev_priv->ips.pwrctx = intel_alloc_context_page(dev); | |
5303 | if (!dev_priv->ips.pwrctx) { | |
2b4e57bd ED |
5304 | ironlake_teardown_rc6(dev); |
5305 | return -ENOMEM; | |
5306 | } | |
5307 | ||
5308 | return 0; | |
5309 | } | |
5310 | ||
930ebb46 | 5311 | static void ironlake_enable_rc6(struct drm_device *dev) |
2b4e57bd ED |
5312 | { |
5313 | struct drm_i915_private *dev_priv = dev->dev_private; | |
a4872ba6 | 5314 | struct intel_engine_cs *ring = &dev_priv->ring[RCS]; |
3e960501 | 5315 | bool was_interruptible; |
2b4e57bd ED |
5316 | int ret; |
5317 | ||
5318 | /* rc6 disabled by default due to repeated reports of hanging during | |
5319 | * boot and resume. | |
5320 | */ | |
5321 | if (!intel_enable_rc6(dev)) | |
5322 | return; | |
5323 | ||
79f5b2c7 DV |
5324 | WARN_ON(!mutex_is_locked(&dev->struct_mutex)); |
5325 | ||
2b4e57bd | 5326 | ret = ironlake_setup_rc6(dev); |
79f5b2c7 | 5327 | if (ret) |
2b4e57bd | 5328 | return; |
2b4e57bd | 5329 | |
3e960501 CW |
5330 | was_interruptible = dev_priv->mm.interruptible; |
5331 | dev_priv->mm.interruptible = false; | |
5332 | ||
2b4e57bd ED |
5333 | /* |
5334 | * GPU can automatically power down the render unit if given a page | |
5335 | * to save state. | |
5336 | */ | |
6d90c952 | 5337 | ret = intel_ring_begin(ring, 6); |
2b4e57bd ED |
5338 | if (ret) { |
5339 | ironlake_teardown_rc6(dev); | |
3e960501 | 5340 | dev_priv->mm.interruptible = was_interruptible; |
2b4e57bd ED |
5341 | return; |
5342 | } | |
5343 | ||
6d90c952 DV |
5344 | intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN); |
5345 | intel_ring_emit(ring, MI_SET_CONTEXT); | |
f343c5f6 | 5346 | intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) | |
6d90c952 DV |
5347 | MI_MM_SPACE_GTT | |
5348 | MI_SAVE_EXT_STATE_EN | | |
5349 | MI_RESTORE_EXT_STATE_EN | | |
5350 | MI_RESTORE_INHIBIT); | |
5351 | intel_ring_emit(ring, MI_SUSPEND_FLUSH); | |
5352 | intel_ring_emit(ring, MI_NOOP); | |
5353 | intel_ring_emit(ring, MI_FLUSH); | |
5354 | intel_ring_advance(ring); | |
2b4e57bd ED |
5355 | |
5356 | /* | |
5357 | * Wait for the command parser to advance past MI_SET_CONTEXT. The HW | |
5358 | * does an implicit flush, combined with MI_FLUSH above, it should be | |
5359 | * safe to assume that renderctx is valid | |
5360 | */ | |
3e960501 CW |
5361 | ret = intel_ring_idle(ring); |
5362 | dev_priv->mm.interruptible = was_interruptible; | |
2b4e57bd | 5363 | if (ret) { |
def27a58 | 5364 | DRM_ERROR("failed to enable ironlake power savings\n"); |
2b4e57bd | 5365 | ironlake_teardown_rc6(dev); |
2b4e57bd ED |
5366 | return; |
5367 | } | |
5368 | ||
f343c5f6 | 5369 | I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN); |
2b4e57bd | 5370 | I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT); |
dc39fff7 | 5371 | |
91ca689a | 5372 | intel_print_rc6_info(dev, GEN6_RC_CTL_RC6_ENABLE); |
2b4e57bd ED |
5373 | } |
5374 | ||
dde18883 ED |
5375 | static unsigned long intel_pxfreq(u32 vidfreq) |
5376 | { | |
5377 | unsigned long freq; | |
5378 | int div = (vidfreq & 0x3f0000) >> 16; | |
5379 | int post = (vidfreq & 0x3000) >> 12; | |
5380 | int pre = (vidfreq & 0x7); | |
5381 | ||
5382 | if (!pre) | |
5383 | return 0; | |
5384 | ||
5385 | freq = ((div * 133333) / ((1<<post) * pre)); | |
5386 | ||
5387 | return freq; | |
5388 | } | |
5389 | ||
eb48eb00 DV |
5390 | static const struct cparams { |
5391 | u16 i; | |
5392 | u16 t; | |
5393 | u16 m; | |
5394 | u16 c; | |
5395 | } cparams[] = { | |
5396 | { 1, 1333, 301, 28664 }, | |
5397 | { 1, 1066, 294, 24460 }, | |
5398 | { 1, 800, 294, 25192 }, | |
5399 | { 0, 1333, 276, 27605 }, | |
5400 | { 0, 1066, 276, 27605 }, | |
5401 | { 0, 800, 231, 23784 }, | |
5402 | }; | |
5403 | ||
f531dcb2 | 5404 | static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5405 | { |
5406 | u64 total_count, diff, ret; | |
5407 | u32 count1, count2, count3, m = 0, c = 0; | |
5408 | unsigned long now = jiffies_to_msecs(jiffies), diff1; | |
5409 | int i; | |
5410 | ||
02d71956 DV |
5411 | assert_spin_locked(&mchdev_lock); |
5412 | ||
20e4d407 | 5413 | diff1 = now - dev_priv->ips.last_time1; |
eb48eb00 DV |
5414 | |
5415 | /* Prevent division-by-zero if we are asking too fast. | |
5416 | * Also, we don't get interesting results if we are polling | |
5417 | * faster than once in 10ms, so just return the saved value | |
5418 | * in such cases. | |
5419 | */ | |
5420 | if (diff1 <= 10) | |
20e4d407 | 5421 | return dev_priv->ips.chipset_power; |
eb48eb00 DV |
5422 | |
5423 | count1 = I915_READ(DMIEC); | |
5424 | count2 = I915_READ(DDREC); | |
5425 | count3 = I915_READ(CSIEC); | |
5426 | ||
5427 | total_count = count1 + count2 + count3; | |
5428 | ||
5429 | /* FIXME: handle per-counter overflow */ | |
20e4d407 DV |
5430 | if (total_count < dev_priv->ips.last_count1) { |
5431 | diff = ~0UL - dev_priv->ips.last_count1; | |
eb48eb00 DV |
5432 | diff += total_count; |
5433 | } else { | |
20e4d407 | 5434 | diff = total_count - dev_priv->ips.last_count1; |
eb48eb00 DV |
5435 | } |
5436 | ||
5437 | for (i = 0; i < ARRAY_SIZE(cparams); i++) { | |
20e4d407 DV |
5438 | if (cparams[i].i == dev_priv->ips.c_m && |
5439 | cparams[i].t == dev_priv->ips.r_t) { | |
eb48eb00 DV |
5440 | m = cparams[i].m; |
5441 | c = cparams[i].c; | |
5442 | break; | |
5443 | } | |
5444 | } | |
5445 | ||
5446 | diff = div_u64(diff, diff1); | |
5447 | ret = ((m * diff) + c); | |
5448 | ret = div_u64(ret, 10); | |
5449 | ||
20e4d407 DV |
5450 | dev_priv->ips.last_count1 = total_count; |
5451 | dev_priv->ips.last_time1 = now; | |
eb48eb00 | 5452 | |
20e4d407 | 5453 | dev_priv->ips.chipset_power = ret; |
eb48eb00 DV |
5454 | |
5455 | return ret; | |
5456 | } | |
5457 | ||
f531dcb2 CW |
5458 | unsigned long i915_chipset_val(struct drm_i915_private *dev_priv) |
5459 | { | |
3d13ef2e | 5460 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5461 | unsigned long val; |
5462 | ||
3d13ef2e | 5463 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5464 | return 0; |
5465 | ||
5466 | spin_lock_irq(&mchdev_lock); | |
5467 | ||
5468 | val = __i915_chipset_val(dev_priv); | |
5469 | ||
5470 | spin_unlock_irq(&mchdev_lock); | |
5471 | ||
5472 | return val; | |
5473 | } | |
5474 | ||
eb48eb00 DV |
5475 | unsigned long i915_mch_val(struct drm_i915_private *dev_priv) |
5476 | { | |
5477 | unsigned long m, x, b; | |
5478 | u32 tsfs; | |
5479 | ||
5480 | tsfs = I915_READ(TSFS); | |
5481 | ||
5482 | m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT); | |
5483 | x = I915_READ8(TR1); | |
5484 | ||
5485 | b = tsfs & TSFS_INTR_MASK; | |
5486 | ||
5487 | return ((m * x) / 127) - b; | |
5488 | } | |
5489 | ||
5490 | static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid) | |
5491 | { | |
3d13ef2e | 5492 | struct drm_device *dev = dev_priv->dev; |
eb48eb00 DV |
5493 | static const struct v_table { |
5494 | u16 vd; /* in .1 mil */ | |
5495 | u16 vm; /* in .1 mil */ | |
5496 | } v_table[] = { | |
5497 | { 0, 0, }, | |
5498 | { 375, 0, }, | |
5499 | { 500, 0, }, | |
5500 | { 625, 0, }, | |
5501 | { 750, 0, }, | |
5502 | { 875, 0, }, | |
5503 | { 1000, 0, }, | |
5504 | { 1125, 0, }, | |
5505 | { 4125, 3000, }, | |
5506 | { 4125, 3000, }, | |
5507 | { 4125, 3000, }, | |
5508 | { 4125, 3000, }, | |
5509 | { 4125, 3000, }, | |
5510 | { 4125, 3000, }, | |
5511 | { 4125, 3000, }, | |
5512 | { 4125, 3000, }, | |
5513 | { 4125, 3000, }, | |
5514 | { 4125, 3000, }, | |
5515 | { 4125, 3000, }, | |
5516 | { 4125, 3000, }, | |
5517 | { 4125, 3000, }, | |
5518 | { 4125, 3000, }, | |
5519 | { 4125, 3000, }, | |
5520 | { 4125, 3000, }, | |
5521 | { 4125, 3000, }, | |
5522 | { 4125, 3000, }, | |
5523 | { 4125, 3000, }, | |
5524 | { 4125, 3000, }, | |
5525 | { 4125, 3000, }, | |
5526 | { 4125, 3000, }, | |
5527 | { 4125, 3000, }, | |
5528 | { 4125, 3000, }, | |
5529 | { 4250, 3125, }, | |
5530 | { 4375, 3250, }, | |
5531 | { 4500, 3375, }, | |
5532 | { 4625, 3500, }, | |
5533 | { 4750, 3625, }, | |
5534 | { 4875, 3750, }, | |
5535 | { 5000, 3875, }, | |
5536 | { 5125, 4000, }, | |
5537 | { 5250, 4125, }, | |
5538 | { 5375, 4250, }, | |
5539 | { 5500, 4375, }, | |
5540 | { 5625, 4500, }, | |
5541 | { 5750, 4625, }, | |
5542 | { 5875, 4750, }, | |
5543 | { 6000, 4875, }, | |
5544 | { 6125, 5000, }, | |
5545 | { 6250, 5125, }, | |
5546 | { 6375, 5250, }, | |
5547 | { 6500, 5375, }, | |
5548 | { 6625, 5500, }, | |
5549 | { 6750, 5625, }, | |
5550 | { 6875, 5750, }, | |
5551 | { 7000, 5875, }, | |
5552 | { 7125, 6000, }, | |
5553 | { 7250, 6125, }, | |
5554 | { 7375, 6250, }, | |
5555 | { 7500, 6375, }, | |
5556 | { 7625, 6500, }, | |
5557 | { 7750, 6625, }, | |
5558 | { 7875, 6750, }, | |
5559 | { 8000, 6875, }, | |
5560 | { 8125, 7000, }, | |
5561 | { 8250, 7125, }, | |
5562 | { 8375, 7250, }, | |
5563 | { 8500, 7375, }, | |
5564 | { 8625, 7500, }, | |
5565 | { 8750, 7625, }, | |
5566 | { 8875, 7750, }, | |
5567 | { 9000, 7875, }, | |
5568 | { 9125, 8000, }, | |
5569 | { 9250, 8125, }, | |
5570 | { 9375, 8250, }, | |
5571 | { 9500, 8375, }, | |
5572 | { 9625, 8500, }, | |
5573 | { 9750, 8625, }, | |
5574 | { 9875, 8750, }, | |
5575 | { 10000, 8875, }, | |
5576 | { 10125, 9000, }, | |
5577 | { 10250, 9125, }, | |
5578 | { 10375, 9250, }, | |
5579 | { 10500, 9375, }, | |
5580 | { 10625, 9500, }, | |
5581 | { 10750, 9625, }, | |
5582 | { 10875, 9750, }, | |
5583 | { 11000, 9875, }, | |
5584 | { 11125, 10000, }, | |
5585 | { 11250, 10125, }, | |
5586 | { 11375, 10250, }, | |
5587 | { 11500, 10375, }, | |
5588 | { 11625, 10500, }, | |
5589 | { 11750, 10625, }, | |
5590 | { 11875, 10750, }, | |
5591 | { 12000, 10875, }, | |
5592 | { 12125, 11000, }, | |
5593 | { 12250, 11125, }, | |
5594 | { 12375, 11250, }, | |
5595 | { 12500, 11375, }, | |
5596 | { 12625, 11500, }, | |
5597 | { 12750, 11625, }, | |
5598 | { 12875, 11750, }, | |
5599 | { 13000, 11875, }, | |
5600 | { 13125, 12000, }, | |
5601 | { 13250, 12125, }, | |
5602 | { 13375, 12250, }, | |
5603 | { 13500, 12375, }, | |
5604 | { 13625, 12500, }, | |
5605 | { 13750, 12625, }, | |
5606 | { 13875, 12750, }, | |
5607 | { 14000, 12875, }, | |
5608 | { 14125, 13000, }, | |
5609 | { 14250, 13125, }, | |
5610 | { 14375, 13250, }, | |
5611 | { 14500, 13375, }, | |
5612 | { 14625, 13500, }, | |
5613 | { 14750, 13625, }, | |
5614 | { 14875, 13750, }, | |
5615 | { 15000, 13875, }, | |
5616 | { 15125, 14000, }, | |
5617 | { 15250, 14125, }, | |
5618 | { 15375, 14250, }, | |
5619 | { 15500, 14375, }, | |
5620 | { 15625, 14500, }, | |
5621 | { 15750, 14625, }, | |
5622 | { 15875, 14750, }, | |
5623 | { 16000, 14875, }, | |
5624 | { 16125, 15000, }, | |
5625 | }; | |
3d13ef2e | 5626 | if (INTEL_INFO(dev)->is_mobile) |
eb48eb00 DV |
5627 | return v_table[pxvid].vm; |
5628 | else | |
5629 | return v_table[pxvid].vd; | |
5630 | } | |
5631 | ||
02d71956 | 5632 | static void __i915_update_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 | 5633 | { |
5ed0bdf2 | 5634 | u64 now, diff, diffms; |
eb48eb00 DV |
5635 | u32 count; |
5636 | ||
02d71956 | 5637 | assert_spin_locked(&mchdev_lock); |
eb48eb00 | 5638 | |
5ed0bdf2 TG |
5639 | now = ktime_get_raw_ns(); |
5640 | diffms = now - dev_priv->ips.last_time2; | |
5641 | do_div(diffms, NSEC_PER_MSEC); | |
eb48eb00 DV |
5642 | |
5643 | /* Don't divide by 0 */ | |
eb48eb00 DV |
5644 | if (!diffms) |
5645 | return; | |
5646 | ||
5647 | count = I915_READ(GFXEC); | |
5648 | ||
20e4d407 DV |
5649 | if (count < dev_priv->ips.last_count2) { |
5650 | diff = ~0UL - dev_priv->ips.last_count2; | |
eb48eb00 DV |
5651 | diff += count; |
5652 | } else { | |
20e4d407 | 5653 | diff = count - dev_priv->ips.last_count2; |
eb48eb00 DV |
5654 | } |
5655 | ||
20e4d407 DV |
5656 | dev_priv->ips.last_count2 = count; |
5657 | dev_priv->ips.last_time2 = now; | |
eb48eb00 DV |
5658 | |
5659 | /* More magic constants... */ | |
5660 | diff = diff * 1181; | |
5661 | diff = div_u64(diff, diffms * 10); | |
20e4d407 | 5662 | dev_priv->ips.gfx_power = diff; |
eb48eb00 DV |
5663 | } |
5664 | ||
02d71956 DV |
5665 | void i915_update_gfx_val(struct drm_i915_private *dev_priv) |
5666 | { | |
3d13ef2e DL |
5667 | struct drm_device *dev = dev_priv->dev; |
5668 | ||
5669 | if (INTEL_INFO(dev)->gen != 5) | |
02d71956 DV |
5670 | return; |
5671 | ||
9270388e | 5672 | spin_lock_irq(&mchdev_lock); |
02d71956 DV |
5673 | |
5674 | __i915_update_gfx_val(dev_priv); | |
5675 | ||
9270388e | 5676 | spin_unlock_irq(&mchdev_lock); |
02d71956 DV |
5677 | } |
5678 | ||
f531dcb2 | 5679 | static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv) |
eb48eb00 DV |
5680 | { |
5681 | unsigned long t, corr, state1, corr2, state2; | |
5682 | u32 pxvid, ext_v; | |
5683 | ||
02d71956 DV |
5684 | assert_spin_locked(&mchdev_lock); |
5685 | ||
b39fb297 | 5686 | pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_freq * 4)); |
eb48eb00 DV |
5687 | pxvid = (pxvid >> 24) & 0x7f; |
5688 | ext_v = pvid_to_extvid(dev_priv, pxvid); | |
5689 | ||
5690 | state1 = ext_v; | |
5691 | ||
5692 | t = i915_mch_val(dev_priv); | |
5693 | ||
5694 | /* Revel in the empirically derived constants */ | |
5695 | ||
5696 | /* Correction factor in 1/100000 units */ | |
5697 | if (t > 80) | |
5698 | corr = ((t * 2349) + 135940); | |
5699 | else if (t >= 50) | |
5700 | corr = ((t * 964) + 29317); | |
5701 | else /* < 50 */ | |
5702 | corr = ((t * 301) + 1004); | |
5703 | ||
5704 | corr = corr * ((150142 * state1) / 10000 - 78642); | |
5705 | corr /= 100000; | |
20e4d407 | 5706 | corr2 = (corr * dev_priv->ips.corr); |
eb48eb00 DV |
5707 | |
5708 | state2 = (corr2 * state1) / 10000; | |
5709 | state2 /= 100; /* convert to mW */ | |
5710 | ||
02d71956 | 5711 | __i915_update_gfx_val(dev_priv); |
eb48eb00 | 5712 | |
20e4d407 | 5713 | return dev_priv->ips.gfx_power + state2; |
eb48eb00 DV |
5714 | } |
5715 | ||
f531dcb2 CW |
5716 | unsigned long i915_gfx_val(struct drm_i915_private *dev_priv) |
5717 | { | |
3d13ef2e | 5718 | struct drm_device *dev = dev_priv->dev; |
f531dcb2 CW |
5719 | unsigned long val; |
5720 | ||
3d13ef2e | 5721 | if (INTEL_INFO(dev)->gen != 5) |
f531dcb2 CW |
5722 | return 0; |
5723 | ||
5724 | spin_lock_irq(&mchdev_lock); | |
5725 | ||
5726 | val = __i915_gfx_val(dev_priv); | |
5727 | ||
5728 | spin_unlock_irq(&mchdev_lock); | |
5729 | ||
5730 | return val; | |
5731 | } | |
5732 | ||
eb48eb00 DV |
5733 | /** |
5734 | * i915_read_mch_val - return value for IPS use | |
5735 | * | |
5736 | * Calculate and return a value for the IPS driver to use when deciding whether | |
5737 | * we have thermal and power headroom to increase CPU or GPU power budget. | |
5738 | */ | |
5739 | unsigned long i915_read_mch_val(void) | |
5740 | { | |
5741 | struct drm_i915_private *dev_priv; | |
5742 | unsigned long chipset_val, graphics_val, ret = 0; | |
5743 | ||
9270388e | 5744 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5745 | if (!i915_mch_dev) |
5746 | goto out_unlock; | |
5747 | dev_priv = i915_mch_dev; | |
5748 | ||
f531dcb2 CW |
5749 | chipset_val = __i915_chipset_val(dev_priv); |
5750 | graphics_val = __i915_gfx_val(dev_priv); | |
eb48eb00 DV |
5751 | |
5752 | ret = chipset_val + graphics_val; | |
5753 | ||
5754 | out_unlock: | |
9270388e | 5755 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5756 | |
5757 | return ret; | |
5758 | } | |
5759 | EXPORT_SYMBOL_GPL(i915_read_mch_val); | |
5760 | ||
5761 | /** | |
5762 | * i915_gpu_raise - raise GPU frequency limit | |
5763 | * | |
5764 | * Raise the limit; IPS indicates we have thermal headroom. | |
5765 | */ | |
5766 | bool i915_gpu_raise(void) | |
5767 | { | |
5768 | struct drm_i915_private *dev_priv; | |
5769 | bool ret = true; | |
5770 | ||
9270388e | 5771 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5772 | if (!i915_mch_dev) { |
5773 | ret = false; | |
5774 | goto out_unlock; | |
5775 | } | |
5776 | dev_priv = i915_mch_dev; | |
5777 | ||
20e4d407 DV |
5778 | if (dev_priv->ips.max_delay > dev_priv->ips.fmax) |
5779 | dev_priv->ips.max_delay--; | |
eb48eb00 DV |
5780 | |
5781 | out_unlock: | |
9270388e | 5782 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5783 | |
5784 | return ret; | |
5785 | } | |
5786 | EXPORT_SYMBOL_GPL(i915_gpu_raise); | |
5787 | ||
5788 | /** | |
5789 | * i915_gpu_lower - lower GPU frequency limit | |
5790 | * | |
5791 | * IPS indicates we're close to a thermal limit, so throttle back the GPU | |
5792 | * frequency maximum. | |
5793 | */ | |
5794 | bool i915_gpu_lower(void) | |
5795 | { | |
5796 | struct drm_i915_private *dev_priv; | |
5797 | bool ret = true; | |
5798 | ||
9270388e | 5799 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5800 | if (!i915_mch_dev) { |
5801 | ret = false; | |
5802 | goto out_unlock; | |
5803 | } | |
5804 | dev_priv = i915_mch_dev; | |
5805 | ||
20e4d407 DV |
5806 | if (dev_priv->ips.max_delay < dev_priv->ips.min_delay) |
5807 | dev_priv->ips.max_delay++; | |
eb48eb00 DV |
5808 | |
5809 | out_unlock: | |
9270388e | 5810 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5811 | |
5812 | return ret; | |
5813 | } | |
5814 | EXPORT_SYMBOL_GPL(i915_gpu_lower); | |
5815 | ||
5816 | /** | |
5817 | * i915_gpu_busy - indicate GPU business to IPS | |
5818 | * | |
5819 | * Tell the IPS driver whether or not the GPU is busy. | |
5820 | */ | |
5821 | bool i915_gpu_busy(void) | |
5822 | { | |
5823 | struct drm_i915_private *dev_priv; | |
a4872ba6 | 5824 | struct intel_engine_cs *ring; |
eb48eb00 | 5825 | bool ret = false; |
f047e395 | 5826 | int i; |
eb48eb00 | 5827 | |
9270388e | 5828 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5829 | if (!i915_mch_dev) |
5830 | goto out_unlock; | |
5831 | dev_priv = i915_mch_dev; | |
5832 | ||
f047e395 CW |
5833 | for_each_ring(ring, dev_priv, i) |
5834 | ret |= !list_empty(&ring->request_list); | |
eb48eb00 DV |
5835 | |
5836 | out_unlock: | |
9270388e | 5837 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5838 | |
5839 | return ret; | |
5840 | } | |
5841 | EXPORT_SYMBOL_GPL(i915_gpu_busy); | |
5842 | ||
5843 | /** | |
5844 | * i915_gpu_turbo_disable - disable graphics turbo | |
5845 | * | |
5846 | * Disable graphics turbo by resetting the max frequency and setting the | |
5847 | * current frequency to the default. | |
5848 | */ | |
5849 | bool i915_gpu_turbo_disable(void) | |
5850 | { | |
5851 | struct drm_i915_private *dev_priv; | |
5852 | bool ret = true; | |
5853 | ||
9270388e | 5854 | spin_lock_irq(&mchdev_lock); |
eb48eb00 DV |
5855 | if (!i915_mch_dev) { |
5856 | ret = false; | |
5857 | goto out_unlock; | |
5858 | } | |
5859 | dev_priv = i915_mch_dev; | |
5860 | ||
20e4d407 | 5861 | dev_priv->ips.max_delay = dev_priv->ips.fstart; |
eb48eb00 | 5862 | |
20e4d407 | 5863 | if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart)) |
eb48eb00 DV |
5864 | ret = false; |
5865 | ||
5866 | out_unlock: | |
9270388e | 5867 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5868 | |
5869 | return ret; | |
5870 | } | |
5871 | EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable); | |
5872 | ||
5873 | /** | |
5874 | * Tells the intel_ips driver that the i915 driver is now loaded, if | |
5875 | * IPS got loaded first. | |
5876 | * | |
5877 | * This awkward dance is so that neither module has to depend on the | |
5878 | * other in order for IPS to do the appropriate communication of | |
5879 | * GPU turbo limits to i915. | |
5880 | */ | |
5881 | static void | |
5882 | ips_ping_for_i915_load(void) | |
5883 | { | |
5884 | void (*link)(void); | |
5885 | ||
5886 | link = symbol_get(ips_link_to_i915_driver); | |
5887 | if (link) { | |
5888 | link(); | |
5889 | symbol_put(ips_link_to_i915_driver); | |
5890 | } | |
5891 | } | |
5892 | ||
5893 | void intel_gpu_ips_init(struct drm_i915_private *dev_priv) | |
5894 | { | |
02d71956 DV |
5895 | /* We only register the i915 ips part with intel-ips once everything is |
5896 | * set up, to avoid intel-ips sneaking in and reading bogus values. */ | |
9270388e | 5897 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5898 | i915_mch_dev = dev_priv; |
9270388e | 5899 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 DV |
5900 | |
5901 | ips_ping_for_i915_load(); | |
5902 | } | |
5903 | ||
5904 | void intel_gpu_ips_teardown(void) | |
5905 | { | |
9270388e | 5906 | spin_lock_irq(&mchdev_lock); |
eb48eb00 | 5907 | i915_mch_dev = NULL; |
9270388e | 5908 | spin_unlock_irq(&mchdev_lock); |
eb48eb00 | 5909 | } |
76c3552f | 5910 | |
8090c6b9 | 5911 | static void intel_init_emon(struct drm_device *dev) |
dde18883 ED |
5912 | { |
5913 | struct drm_i915_private *dev_priv = dev->dev_private; | |
5914 | u32 lcfuse; | |
5915 | u8 pxw[16]; | |
5916 | int i; | |
5917 | ||
5918 | /* Disable to program */ | |
5919 | I915_WRITE(ECR, 0); | |
5920 | POSTING_READ(ECR); | |
5921 | ||
5922 | /* Program energy weights for various events */ | |
5923 | I915_WRITE(SDEW, 0x15040d00); | |
5924 | I915_WRITE(CSIEW0, 0x007f0000); | |
5925 | I915_WRITE(CSIEW1, 0x1e220004); | |
5926 | I915_WRITE(CSIEW2, 0x04000004); | |
5927 | ||
5928 | for (i = 0; i < 5; i++) | |
5929 | I915_WRITE(PEW + (i * 4), 0); | |
5930 | for (i = 0; i < 3; i++) | |
5931 | I915_WRITE(DEW + (i * 4), 0); | |
5932 | ||
5933 | /* Program P-state weights to account for frequency power adjustment */ | |
5934 | for (i = 0; i < 16; i++) { | |
5935 | u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4)); | |
5936 | unsigned long freq = intel_pxfreq(pxvidfreq); | |
5937 | unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >> | |
5938 | PXVFREQ_PX_SHIFT; | |
5939 | unsigned long val; | |
5940 | ||
5941 | val = vid * vid; | |
5942 | val *= (freq / 1000); | |
5943 | val *= 255; | |
5944 | val /= (127*127*900); | |
5945 | if (val > 0xff) | |
5946 | DRM_ERROR("bad pxval: %ld\n", val); | |
5947 | pxw[i] = val; | |
5948 | } | |
5949 | /* Render standby states get 0 weight */ | |
5950 | pxw[14] = 0; | |
5951 | pxw[15] = 0; | |
5952 | ||
5953 | for (i = 0; i < 4; i++) { | |
5954 | u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) | | |
5955 | (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]); | |
5956 | I915_WRITE(PXW + (i * 4), val); | |
5957 | } | |
5958 | ||
5959 | /* Adjust magic regs to magic values (more experimental results) */ | |
5960 | I915_WRITE(OGW0, 0); | |
5961 | I915_WRITE(OGW1, 0); | |
5962 | I915_WRITE(EG0, 0x00007f00); | |
5963 | I915_WRITE(EG1, 0x0000000e); | |
5964 | I915_WRITE(EG2, 0x000e0000); | |
5965 | I915_WRITE(EG3, 0x68000300); | |
5966 | I915_WRITE(EG4, 0x42000000); | |
5967 | I915_WRITE(EG5, 0x00140031); | |
5968 | I915_WRITE(EG6, 0); | |
5969 | I915_WRITE(EG7, 0); | |
5970 | ||
5971 | for (i = 0; i < 8; i++) | |
5972 | I915_WRITE(PXWL + (i * 4), 0); | |
5973 | ||
5974 | /* Enable PMON + select events */ | |
5975 | I915_WRITE(ECR, 0x80000019); | |
5976 | ||
5977 | lcfuse = I915_READ(LCFUSE02); | |
5978 | ||
20e4d407 | 5979 | dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK); |
dde18883 ED |
5980 | } |
5981 | ||
ae48434c ID |
5982 | void intel_init_gt_powersave(struct drm_device *dev) |
5983 | { | |
e6069ca8 ID |
5984 | i915.enable_rc6 = sanitize_rc6_option(dev, i915.enable_rc6); |
5985 | ||
38807746 D |
5986 | if (IS_CHERRYVIEW(dev)) |
5987 | cherryview_init_gt_powersave(dev); | |
5988 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5989 | valleyview_init_gt_powersave(dev); |
ae48434c ID |
5990 | } |
5991 | ||
5992 | void intel_cleanup_gt_powersave(struct drm_device *dev) | |
5993 | { | |
38807746 D |
5994 | if (IS_CHERRYVIEW(dev)) |
5995 | return; | |
5996 | else if (IS_VALLEYVIEW(dev)) | |
4e80519e | 5997 | valleyview_cleanup_gt_powersave(dev); |
ae48434c ID |
5998 | } |
5999 | ||
156c7ca0 JB |
6000 | /** |
6001 | * intel_suspend_gt_powersave - suspend PM work and helper threads | |
6002 | * @dev: drm device | |
6003 | * | |
6004 | * We don't want to disable RC6 or other features here, we just want | |
6005 | * to make sure any work we've queued has finished and won't bother | |
6006 | * us while we're suspended. | |
6007 | */ | |
6008 | void intel_suspend_gt_powersave(struct drm_device *dev) | |
6009 | { | |
6010 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6011 | ||
6012 | /* Interrupts should be disabled already to avoid re-arming. */ | |
9df7575f | 6013 | WARN_ON(intel_irqs_enabled(dev_priv)); |
156c7ca0 JB |
6014 | |
6015 | flush_delayed_work(&dev_priv->rps.delayed_resume_work); | |
6016 | ||
6017 | cancel_work_sync(&dev_priv->rps.work); | |
b47adc17 D |
6018 | |
6019 | /* Force GPU to min freq during suspend */ | |
6020 | gen6_rps_idle(dev_priv); | |
156c7ca0 JB |
6021 | } |
6022 | ||
8090c6b9 DV |
6023 | void intel_disable_gt_powersave(struct drm_device *dev) |
6024 | { | |
1a01ab3b JB |
6025 | struct drm_i915_private *dev_priv = dev->dev_private; |
6026 | ||
fd0c0642 | 6027 | /* Interrupts should be disabled already to avoid re-arming. */ |
9df7575f | 6028 | WARN_ON(intel_irqs_enabled(dev_priv)); |
fd0c0642 | 6029 | |
930ebb46 | 6030 | if (IS_IRONLAKE_M(dev)) { |
8090c6b9 | 6031 | ironlake_disable_drps(dev); |
930ebb46 | 6032 | ironlake_disable_rc6(dev); |
38807746 | 6033 | } else if (INTEL_INFO(dev)->gen >= 6) { |
10d8d366 | 6034 | intel_suspend_gt_powersave(dev); |
e494837a | 6035 | |
4fc688ce | 6036 | mutex_lock(&dev_priv->rps.hw_lock); |
38807746 D |
6037 | if (IS_CHERRYVIEW(dev)) |
6038 | cherryview_disable_rps(dev); | |
6039 | else if (IS_VALLEYVIEW(dev)) | |
d20d4f0c JB |
6040 | valleyview_disable_rps(dev); |
6041 | else | |
6042 | gen6_disable_rps(dev); | |
c0951f0c | 6043 | dev_priv->rps.enabled = false; |
4fc688ce | 6044 | mutex_unlock(&dev_priv->rps.hw_lock); |
930ebb46 | 6045 | } |
8090c6b9 DV |
6046 | } |
6047 | ||
1a01ab3b JB |
6048 | static void intel_gen6_powersave_work(struct work_struct *work) |
6049 | { | |
6050 | struct drm_i915_private *dev_priv = | |
6051 | container_of(work, struct drm_i915_private, | |
6052 | rps.delayed_resume_work.work); | |
6053 | struct drm_device *dev = dev_priv->dev; | |
6054 | ||
4fc688ce | 6055 | mutex_lock(&dev_priv->rps.hw_lock); |
0a073b84 | 6056 | |
38807746 D |
6057 | if (IS_CHERRYVIEW(dev)) { |
6058 | cherryview_enable_rps(dev); | |
6059 | } else if (IS_VALLEYVIEW(dev)) { | |
0a073b84 | 6060 | valleyview_enable_rps(dev); |
6edee7f3 BW |
6061 | } else if (IS_BROADWELL(dev)) { |
6062 | gen8_enable_rps(dev); | |
c2bc2fc5 | 6063 | __gen6_update_ring_freq(dev); |
0a073b84 JB |
6064 | } else { |
6065 | gen6_enable_rps(dev); | |
c2bc2fc5 | 6066 | __gen6_update_ring_freq(dev); |
0a073b84 | 6067 | } |
c0951f0c | 6068 | dev_priv->rps.enabled = true; |
4fc688ce | 6069 | mutex_unlock(&dev_priv->rps.hw_lock); |
c6df39b5 ID |
6070 | |
6071 | intel_runtime_pm_put(dev_priv); | |
1a01ab3b JB |
6072 | } |
6073 | ||
8090c6b9 DV |
6074 | void intel_enable_gt_powersave(struct drm_device *dev) |
6075 | { | |
1a01ab3b JB |
6076 | struct drm_i915_private *dev_priv = dev->dev_private; |
6077 | ||
8090c6b9 | 6078 | if (IS_IRONLAKE_M(dev)) { |
dc1d0136 | 6079 | mutex_lock(&dev->struct_mutex); |
8090c6b9 DV |
6080 | ironlake_enable_drps(dev); |
6081 | ironlake_enable_rc6(dev); | |
6082 | intel_init_emon(dev); | |
dc1d0136 | 6083 | mutex_unlock(&dev->struct_mutex); |
38807746 | 6084 | } else if (INTEL_INFO(dev)->gen >= 6) { |
1a01ab3b JB |
6085 | /* |
6086 | * PCU communication is slow and this doesn't need to be | |
6087 | * done at any specific time, so do this out of our fast path | |
6088 | * to make resume and init faster. | |
c6df39b5 ID |
6089 | * |
6090 | * We depend on the HW RC6 power context save/restore | |
6091 | * mechanism when entering D3 through runtime PM suspend. So | |
6092 | * disable RPM until RPS/RC6 is properly setup. We can only | |
6093 | * get here via the driver load/system resume/runtime resume | |
6094 | * paths, so the _noresume version is enough (and in case of | |
6095 | * runtime resume it's necessary). | |
1a01ab3b | 6096 | */ |
c6df39b5 ID |
6097 | if (schedule_delayed_work(&dev_priv->rps.delayed_resume_work, |
6098 | round_jiffies_up_relative(HZ))) | |
6099 | intel_runtime_pm_get_noresume(dev_priv); | |
8090c6b9 DV |
6100 | } |
6101 | } | |
6102 | ||
c6df39b5 ID |
6103 | void intel_reset_gt_powersave(struct drm_device *dev) |
6104 | { | |
6105 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6106 | ||
6107 | dev_priv->rps.enabled = false; | |
6108 | intel_enable_gt_powersave(dev); | |
6109 | } | |
6110 | ||
3107bd48 DV |
6111 | static void ibx_init_clock_gating(struct drm_device *dev) |
6112 | { | |
6113 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6114 | ||
6115 | /* | |
6116 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6117 | * gating for the panel power sequencer or it will fail to | |
6118 | * start up when no ports are active. | |
6119 | */ | |
6120 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE); | |
6121 | } | |
6122 | ||
0e088b8f VS |
6123 | static void g4x_disable_trickle_feed(struct drm_device *dev) |
6124 | { | |
6125 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6126 | int pipe; | |
6127 | ||
055e393f | 6128 | for_each_pipe(dev_priv, pipe) { |
0e088b8f VS |
6129 | I915_WRITE(DSPCNTR(pipe), |
6130 | I915_READ(DSPCNTR(pipe)) | | |
6131 | DISPPLANE_TRICKLE_FEED_DISABLE); | |
1dba99f4 | 6132 | intel_flush_primary_plane(dev_priv, pipe); |
0e088b8f VS |
6133 | } |
6134 | } | |
6135 | ||
017636cc VS |
6136 | static void ilk_init_lp_watermarks(struct drm_device *dev) |
6137 | { | |
6138 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6139 | ||
6140 | I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN); | |
6141 | I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN); | |
6142 | I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN); | |
6143 | ||
6144 | /* | |
6145 | * Don't touch WM1S_LP_EN here. | |
6146 | * Doing so could cause underruns. | |
6147 | */ | |
6148 | } | |
6149 | ||
1fa61106 | 6150 | static void ironlake_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6151 | { |
6152 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6153 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6154 | |
f1e8fa56 DL |
6155 | /* |
6156 | * Required for FBC | |
6157 | * WaFbcDisableDpfcClockGating:ilk | |
6158 | */ | |
4d47e4f5 DL |
6159 | dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE | |
6160 | ILK_DPFCUNIT_CLOCK_GATE_DISABLE | | |
6161 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE; | |
6f1d69b0 ED |
6162 | |
6163 | I915_WRITE(PCH_3DCGDIS0, | |
6164 | MARIUNIT_CLOCK_GATE_DISABLE | | |
6165 | SVSMUNIT_CLOCK_GATE_DISABLE); | |
6166 | I915_WRITE(PCH_3DCGDIS1, | |
6167 | VFMUNIT_CLOCK_GATE_DISABLE); | |
6168 | ||
6f1d69b0 ED |
6169 | /* |
6170 | * According to the spec the following bits should be set in | |
6171 | * order to enable memory self-refresh | |
6172 | * The bit 22/21 of 0x42004 | |
6173 | * The bit 5 of 0x42020 | |
6174 | * The bit 15 of 0x45000 | |
6175 | */ | |
6176 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6177 | (I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6178 | ILK_DPARB_GATE | ILK_VSDPFD_FULL)); | |
4d47e4f5 | 6179 | dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE; |
6f1d69b0 ED |
6180 | I915_WRITE(DISP_ARB_CTL, |
6181 | (I915_READ(DISP_ARB_CTL) | | |
6182 | DISP_FBC_WM_DIS)); | |
017636cc VS |
6183 | |
6184 | ilk_init_lp_watermarks(dev); | |
6f1d69b0 ED |
6185 | |
6186 | /* | |
6187 | * Based on the document from hardware guys the following bits | |
6188 | * should be set unconditionally in order to enable FBC. | |
6189 | * The bit 22 of 0x42000 | |
6190 | * The bit 22 of 0x42004 | |
6191 | * The bit 7,8,9 of 0x42020. | |
6192 | */ | |
6193 | if (IS_IRONLAKE_M(dev)) { | |
4bb35334 | 6194 | /* WaFbcAsynchFlipDisableFbcQueue:ilk */ |
6f1d69b0 ED |
6195 | I915_WRITE(ILK_DISPLAY_CHICKEN1, |
6196 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6197 | ILK_FBCQ_DIS); | |
6198 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6199 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6200 | ILK_DPARB_GATE); | |
6f1d69b0 ED |
6201 | } |
6202 | ||
4d47e4f5 DL |
6203 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6204 | ||
6f1d69b0 ED |
6205 | I915_WRITE(ILK_DISPLAY_CHICKEN2, |
6206 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6207 | ILK_ELPIN_409_SELECT); | |
6208 | I915_WRITE(_3D_CHICKEN2, | |
6209 | _3D_CHICKEN2_WM_READ_PIPELINED << 16 | | |
6210 | _3D_CHICKEN2_WM_READ_PIPELINED); | |
4358a374 | 6211 | |
ecdb4eb7 | 6212 | /* WaDisableRenderCachePipelinedFlush:ilk */ |
4358a374 DV |
6213 | I915_WRITE(CACHE_MODE_0, |
6214 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
3107bd48 | 6215 | |
4e04632e AG |
6216 | /* WaDisable_RenderCache_OperationalFlush:ilk */ |
6217 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6218 | ||
0e088b8f | 6219 | g4x_disable_trickle_feed(dev); |
bdad2b2f | 6220 | |
3107bd48 DV |
6221 | ibx_init_clock_gating(dev); |
6222 | } | |
6223 | ||
6224 | static void cpt_init_clock_gating(struct drm_device *dev) | |
6225 | { | |
6226 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6227 | int pipe; | |
3f704fa2 | 6228 | uint32_t val; |
3107bd48 DV |
6229 | |
6230 | /* | |
6231 | * On Ibex Peak and Cougar Point, we need to disable clock | |
6232 | * gating for the panel power sequencer or it will fail to | |
6233 | * start up when no ports are active. | |
6234 | */ | |
cd664078 JB |
6235 | I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE | |
6236 | PCH_DPLUNIT_CLOCK_GATE_DISABLE | | |
6237 | PCH_CPUNIT_CLOCK_GATE_DISABLE); | |
3107bd48 DV |
6238 | I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) | |
6239 | DPLS_EDP_PPS_FIX_DIS); | |
335c07b7 TI |
6240 | /* The below fixes the weird display corruption, a few pixels shifted |
6241 | * downward, on (only) LVDS of some HP laptops with IVY. | |
6242 | */ | |
055e393f | 6243 | for_each_pipe(dev_priv, pipe) { |
dc4bd2d1 PZ |
6244 | val = I915_READ(TRANS_CHICKEN2(pipe)); |
6245 | val |= TRANS_CHICKEN2_TIMING_OVERRIDE; | |
6246 | val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED; | |
41aa3448 | 6247 | if (dev_priv->vbt.fdi_rx_polarity_inverted) |
3f704fa2 | 6248 | val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED; |
dc4bd2d1 PZ |
6249 | val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK; |
6250 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER; | |
6251 | val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH; | |
3f704fa2 PZ |
6252 | I915_WRITE(TRANS_CHICKEN2(pipe), val); |
6253 | } | |
3107bd48 | 6254 | /* WADP0ClockGatingDisable */ |
055e393f | 6255 | for_each_pipe(dev_priv, pipe) { |
3107bd48 DV |
6256 | I915_WRITE(TRANS_CHICKEN1(pipe), |
6257 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
6258 | } | |
6f1d69b0 ED |
6259 | } |
6260 | ||
1d7aaa0c DV |
6261 | static void gen6_check_mch_setup(struct drm_device *dev) |
6262 | { | |
6263 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6264 | uint32_t tmp; | |
6265 | ||
6266 | tmp = I915_READ(MCH_SSKPD); | |
df662a28 DV |
6267 | if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) |
6268 | DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n", | |
6269 | tmp); | |
1d7aaa0c DV |
6270 | } |
6271 | ||
1fa61106 | 6272 | static void gen6_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6273 | { |
6274 | struct drm_i915_private *dev_priv = dev->dev_private; | |
231e54f6 | 6275 | uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE; |
6f1d69b0 | 6276 | |
231e54f6 | 6277 | I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate); |
6f1d69b0 ED |
6278 | |
6279 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6280 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6281 | ILK_ELPIN_409_SELECT); | |
6282 | ||
ecdb4eb7 | 6283 | /* WaDisableHiZPlanesWhenMSAAEnabled:snb */ |
4283908e DV |
6284 | I915_WRITE(_3D_CHICKEN, |
6285 | _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB)); | |
6286 | ||
ecdb4eb7 | 6287 | /* WaSetupGtModeTdRowDispatch:snb */ |
6547fbdb DV |
6288 | if (IS_SNB_GT1(dev)) |
6289 | I915_WRITE(GEN6_GT_MODE, | |
6290 | _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE)); | |
6291 | ||
4e04632e AG |
6292 | /* WaDisable_RenderCache_OperationalFlush:snb */ |
6293 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6294 | ||
8d85d272 VS |
6295 | /* |
6296 | * BSpec recoomends 8x4 when MSAA is used, | |
6297 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6298 | * |
6299 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6300 | * disable bit, which we don't touch here, but it's good | |
6301 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
8d85d272 VS |
6302 | */ |
6303 | I915_WRITE(GEN6_GT_MODE, | |
6304 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
6305 | ||
017636cc | 6306 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6307 | |
6f1d69b0 | 6308 | I915_WRITE(CACHE_MODE_0, |
50743298 | 6309 | _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB)); |
6f1d69b0 ED |
6310 | |
6311 | I915_WRITE(GEN6_UCGCTL1, | |
6312 | I915_READ(GEN6_UCGCTL1) | | |
6313 | GEN6_BLBUNIT_CLOCK_GATE_DISABLE | | |
6314 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
6315 | ||
6316 | /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock | |
6317 | * gating disable must be set. Failure to set it results in | |
6318 | * flickering pixels due to Z write ordering failures after | |
6319 | * some amount of runtime in the Mesa "fire" demo, and Unigine | |
6320 | * Sanctuary and Tropics, and apparently anything else with | |
6321 | * alpha test or pixel discard. | |
6322 | * | |
6323 | * According to the spec, bit 11 (RCCUNIT) must also be set, | |
6324 | * but we didn't debug actual testcases to find it out. | |
0f846f81 | 6325 | * |
ef59318c VS |
6326 | * WaDisableRCCUnitClockGating:snb |
6327 | * WaDisableRCPBUnitClockGating:snb | |
6f1d69b0 ED |
6328 | */ |
6329 | I915_WRITE(GEN6_UCGCTL2, | |
6330 | GEN6_RCPBUNIT_CLOCK_GATE_DISABLE | | |
6331 | GEN6_RCCUNIT_CLOCK_GATE_DISABLE); | |
6332 | ||
5eb146dd | 6333 | /* WaStripsFansDisableFastClipPerformanceFix:snb */ |
743b57d8 VS |
6334 | I915_WRITE(_3D_CHICKEN3, |
6335 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL)); | |
6f1d69b0 | 6336 | |
e927ecde VS |
6337 | /* |
6338 | * Bspec says: | |
6339 | * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and | |
6340 | * 3DSTATE_SF number of SF output attributes is more than 16." | |
6341 | */ | |
6342 | I915_WRITE(_3D_CHICKEN3, | |
6343 | _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH)); | |
6344 | ||
6f1d69b0 ED |
6345 | /* |
6346 | * According to the spec the following bits should be | |
6347 | * set in order to enable memory self-refresh and fbc: | |
6348 | * The bit21 and bit22 of 0x42000 | |
6349 | * The bit21 and bit22 of 0x42004 | |
6350 | * The bit5 and bit7 of 0x42020 | |
6351 | * The bit14 of 0x70180 | |
6352 | * The bit14 of 0x71180 | |
4bb35334 DL |
6353 | * |
6354 | * WaFbcAsynchFlipDisableFbcQueue:snb | |
6f1d69b0 ED |
6355 | */ |
6356 | I915_WRITE(ILK_DISPLAY_CHICKEN1, | |
6357 | I915_READ(ILK_DISPLAY_CHICKEN1) | | |
6358 | ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS); | |
6359 | I915_WRITE(ILK_DISPLAY_CHICKEN2, | |
6360 | I915_READ(ILK_DISPLAY_CHICKEN2) | | |
6361 | ILK_DPARB_GATE | ILK_VSDPFD_FULL); | |
231e54f6 DL |
6362 | I915_WRITE(ILK_DSPCLK_GATE_D, |
6363 | I915_READ(ILK_DSPCLK_GATE_D) | | |
6364 | ILK_DPARBUNIT_CLOCK_GATE_ENABLE | | |
6365 | ILK_DPFDUNIT_CLOCK_GATE_ENABLE); | |
6f1d69b0 | 6366 | |
0e088b8f | 6367 | g4x_disable_trickle_feed(dev); |
f8f2ac9a | 6368 | |
3107bd48 | 6369 | cpt_init_clock_gating(dev); |
1d7aaa0c DV |
6370 | |
6371 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6372 | } |
6373 | ||
6374 | static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv) | |
6375 | { | |
6376 | uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE); | |
6377 | ||
3aad9059 | 6378 | /* |
46680e0a | 6379 | * WaVSThreadDispatchOverride:ivb,vlv |
3aad9059 VS |
6380 | * |
6381 | * This actually overrides the dispatch | |
6382 | * mode for all thread types. | |
6383 | */ | |
6f1d69b0 ED |
6384 | reg &= ~GEN7_FF_SCHED_MASK; |
6385 | reg |= GEN7_FF_TS_SCHED_HW; | |
6386 | reg |= GEN7_FF_VS_SCHED_HW; | |
6387 | reg |= GEN7_FF_DS_SCHED_HW; | |
6388 | ||
6389 | I915_WRITE(GEN7_FF_THREAD_MODE, reg); | |
6390 | } | |
6391 | ||
17a303ec PZ |
6392 | static void lpt_init_clock_gating(struct drm_device *dev) |
6393 | { | |
6394 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6395 | ||
6396 | /* | |
6397 | * TODO: this bit should only be enabled when really needed, then | |
6398 | * disabled when not needed anymore in order to save power. | |
6399 | */ | |
6400 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) | |
6401 | I915_WRITE(SOUTH_DSPCLK_GATE_D, | |
6402 | I915_READ(SOUTH_DSPCLK_GATE_D) | | |
6403 | PCH_LP_PARTITION_LEVEL_DISABLE); | |
0a790cdb PZ |
6404 | |
6405 | /* WADPOClockGatingDisable:hsw */ | |
6406 | I915_WRITE(_TRANSA_CHICKEN1, | |
6407 | I915_READ(_TRANSA_CHICKEN1) | | |
6408 | TRANS_CHICKEN1_DP0UNIT_GC_DISABLE); | |
17a303ec PZ |
6409 | } |
6410 | ||
7d708ee4 ID |
6411 | static void lpt_suspend_hw(struct drm_device *dev) |
6412 | { | |
6413 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6414 | ||
6415 | if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) { | |
6416 | uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D); | |
6417 | ||
6418 | val &= ~PCH_LP_PARTITION_LEVEL_DISABLE; | |
6419 | I915_WRITE(SOUTH_DSPCLK_GATE_D, val); | |
6420 | } | |
6421 | } | |
6422 | ||
47c2bd97 | 6423 | static void broadwell_init_clock_gating(struct drm_device *dev) |
1020a5c2 BW |
6424 | { |
6425 | struct drm_i915_private *dev_priv = dev->dev_private; | |
07d27e20 | 6426 | enum pipe pipe; |
1020a5c2 BW |
6427 | |
6428 | I915_WRITE(WM3_LP_ILK, 0); | |
6429 | I915_WRITE(WM2_LP_ILK, 0); | |
6430 | I915_WRITE(WM1_LP_ILK, 0); | |
50ed5fbd | 6431 | |
ab57fff1 | 6432 | /* WaSwitchSolVfFArbitrationPriority:bdw */ |
50ed5fbd | 6433 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
fe4ab3ce | 6434 | |
ab57fff1 | 6435 | /* WaPsrDPAMaskVBlankInSRD:bdw */ |
fe4ab3ce BW |
6436 | I915_WRITE(CHICKEN_PAR1_1, |
6437 | I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD); | |
6438 | ||
ab57fff1 | 6439 | /* WaPsrDPRSUnmaskVBlankInSRD:bdw */ |
055e393f | 6440 | for_each_pipe(dev_priv, pipe) { |
07d27e20 | 6441 | I915_WRITE(CHICKEN_PIPESL_1(pipe), |
c7c65622 | 6442 | I915_READ(CHICKEN_PIPESL_1(pipe)) | |
8f670bb1 | 6443 | BDW_DPRS_MASK_VBLANK_SRD); |
fe4ab3ce | 6444 | } |
63801f21 | 6445 | |
ab57fff1 BW |
6446 | /* WaVSRefCountFullforceMissDisable:bdw */ |
6447 | /* WaDSRefCountFullforceMissDisable:bdw */ | |
6448 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6449 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6450 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
36075a4c | 6451 | |
295e8bb7 VS |
6452 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, |
6453 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
4f1ca9e9 VS |
6454 | |
6455 | /* WaDisableSDEUnitClockGating:bdw */ | |
6456 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6457 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
5d708680 | 6458 | |
89d6b2b8 | 6459 | lpt_init_clock_gating(dev); |
1020a5c2 BW |
6460 | } |
6461 | ||
cad2a2d7 ED |
6462 | static void haswell_init_clock_gating(struct drm_device *dev) |
6463 | { | |
6464 | struct drm_i915_private *dev_priv = dev->dev_private; | |
cad2a2d7 | 6465 | |
017636cc | 6466 | ilk_init_lp_watermarks(dev); |
cad2a2d7 | 6467 | |
f3fc4884 FJ |
6468 | /* L3 caching of data atomics doesn't work -- disable it. */ |
6469 | I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE); | |
6470 | I915_WRITE(HSW_ROW_CHICKEN3, | |
6471 | _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE)); | |
6472 | ||
ecdb4eb7 | 6473 | /* This is required by WaCatErrorRejectionIssue:hsw */ |
cad2a2d7 ED |
6474 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6475 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6476 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6477 | ||
e36ea7ff VS |
6478 | /* WaVSRefCountFullforceMissDisable:hsw */ |
6479 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6480 | I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME); | |
cad2a2d7 | 6481 | |
4e04632e AG |
6482 | /* WaDisable_RenderCache_OperationalFlush:hsw */ |
6483 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6484 | ||
fe27c606 CW |
6485 | /* enable HiZ Raw Stall Optimization */ |
6486 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6487 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6488 | ||
ecdb4eb7 | 6489 | /* WaDisable4x2SubspanOptimization:hsw */ |
cad2a2d7 ED |
6490 | I915_WRITE(CACHE_MODE_1, |
6491 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
1544d9d5 | 6492 | |
a12c4967 VS |
6493 | /* |
6494 | * BSpec recommends 8x4 when MSAA is used, | |
6495 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6496 | * |
6497 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6498 | * disable bit, which we don't touch here, but it's good | |
6499 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a12c4967 VS |
6500 | */ |
6501 | I915_WRITE(GEN7_GT_MODE, | |
6502 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
6503 | ||
ecdb4eb7 | 6504 | /* WaSwitchSolVfFArbitrationPriority:hsw */ |
e3dff585 BW |
6505 | I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL); |
6506 | ||
90a88643 PZ |
6507 | /* WaRsPkgCStateDisplayPMReq:hsw */ |
6508 | I915_WRITE(CHICKEN_PAR1_1, | |
6509 | I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES); | |
1544d9d5 | 6510 | |
17a303ec | 6511 | lpt_init_clock_gating(dev); |
cad2a2d7 ED |
6512 | } |
6513 | ||
1fa61106 | 6514 | static void ivybridge_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6515 | { |
6516 | struct drm_i915_private *dev_priv = dev->dev_private; | |
20848223 | 6517 | uint32_t snpcr; |
6f1d69b0 | 6518 | |
017636cc | 6519 | ilk_init_lp_watermarks(dev); |
6f1d69b0 | 6520 | |
231e54f6 | 6521 | I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6522 | |
ecdb4eb7 | 6523 | /* WaDisableEarlyCull:ivb */ |
87f8020e JB |
6524 | I915_WRITE(_3D_CHICKEN3, |
6525 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6526 | ||
ecdb4eb7 | 6527 | /* WaDisableBackToBackFlipFix:ivb */ |
6f1d69b0 ED |
6528 | I915_WRITE(IVB_CHICKEN3, |
6529 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6530 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6531 | ||
ecdb4eb7 | 6532 | /* WaDisablePSDDualDispatchEnable:ivb */ |
12f3382b JB |
6533 | if (IS_IVB_GT1(dev)) |
6534 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, | |
6535 | _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6536 | |
4e04632e AG |
6537 | /* WaDisable_RenderCache_OperationalFlush:ivb */ |
6538 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6539 | ||
ecdb4eb7 | 6540 | /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */ |
6f1d69b0 ED |
6541 | I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1, |
6542 | GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC); | |
6543 | ||
ecdb4eb7 | 6544 | /* WaApplyL3ControlAndL3ChickenMode:ivb */ |
6f1d69b0 ED |
6545 | I915_WRITE(GEN7_L3CNTLREG1, |
6546 | GEN7_WA_FOR_GEN7_L3_CONTROL); | |
6547 | I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, | |
8ab43976 JB |
6548 | GEN7_WA_L3_CHICKEN_MODE); |
6549 | if (IS_IVB_GT1(dev)) | |
6550 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6551 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 VS |
6552 | else { |
6553 | /* must write both registers */ | |
6554 | I915_WRITE(GEN7_ROW_CHICKEN2, | |
6555 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
8ab43976 JB |
6556 | I915_WRITE(GEN7_ROW_CHICKEN2_GT2, |
6557 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
412236c2 | 6558 | } |
6f1d69b0 | 6559 | |
ecdb4eb7 | 6560 | /* WaForceL3Serialization:ivb */ |
61939d97 JB |
6561 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6562 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6563 | ||
1b80a19a | 6564 | /* |
0f846f81 | 6565 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6566 | * This implements the WaDisableRCZUnitClockGating:ivb workaround. |
0f846f81 JB |
6567 | */ |
6568 | I915_WRITE(GEN6_UCGCTL2, | |
28acf3b2 | 6569 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6570 | |
ecdb4eb7 | 6571 | /* This is required by WaCatErrorRejectionIssue:ivb */ |
6f1d69b0 ED |
6572 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6573 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6574 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6575 | ||
0e088b8f | 6576 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6577 | |
6578 | gen7_setup_fixed_func_scheduler(dev_priv); | |
97e1930f | 6579 | |
22721343 CW |
6580 | if (0) { /* causes HiZ corruption on ivb:gt1 */ |
6581 | /* enable HiZ Raw Stall Optimization */ | |
6582 | I915_WRITE(CACHE_MODE_0_GEN7, | |
6583 | _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE)); | |
6584 | } | |
116f2b6d | 6585 | |
ecdb4eb7 | 6586 | /* WaDisable4x2SubspanOptimization:ivb */ |
97e1930f DV |
6587 | I915_WRITE(CACHE_MODE_1, |
6588 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
20848223 | 6589 | |
a607c1a4 VS |
6590 | /* |
6591 | * BSpec recommends 8x4 when MSAA is used, | |
6592 | * however in practice 16x4 seems fastest. | |
c5c98a58 VS |
6593 | * |
6594 | * Note that PS/WM thread counts depend on the WIZ hashing | |
6595 | * disable bit, which we don't touch here, but it's good | |
6596 | * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM). | |
a607c1a4 VS |
6597 | */ |
6598 | I915_WRITE(GEN7_GT_MODE, | |
6599 | GEN6_WIZ_HASHING_MASK | GEN6_WIZ_HASHING_16x4); | |
6600 | ||
20848223 BW |
6601 | snpcr = I915_READ(GEN6_MBCUNIT_SNPCR); |
6602 | snpcr &= ~GEN6_MBC_SNPCR_MASK; | |
6603 | snpcr |= GEN6_MBC_SNPCR_MED; | |
6604 | I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr); | |
3107bd48 | 6605 | |
ab5c608b BW |
6606 | if (!HAS_PCH_NOP(dev)) |
6607 | cpt_init_clock_gating(dev); | |
1d7aaa0c DV |
6608 | |
6609 | gen6_check_mch_setup(dev); | |
6f1d69b0 ED |
6610 | } |
6611 | ||
1fa61106 | 6612 | static void valleyview_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6613 | { |
6614 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6f1d69b0 | 6615 | |
d7fe0cc0 | 6616 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); |
6f1d69b0 | 6617 | |
ecdb4eb7 | 6618 | /* WaDisableEarlyCull:vlv */ |
87f8020e JB |
6619 | I915_WRITE(_3D_CHICKEN3, |
6620 | _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL)); | |
6621 | ||
ecdb4eb7 | 6622 | /* WaDisableBackToBackFlipFix:vlv */ |
6f1d69b0 ED |
6623 | I915_WRITE(IVB_CHICKEN3, |
6624 | CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE | | |
6625 | CHICKEN3_DGMG_DONE_FIX_DISABLE); | |
6626 | ||
fad7d36e | 6627 | /* WaPsdDispatchEnable:vlv */ |
ecdb4eb7 | 6628 | /* WaDisablePSDDualDispatchEnable:vlv */ |
12f3382b | 6629 | I915_WRITE(GEN7_HALF_SLICE_CHICKEN1, |
d3bc0303 JB |
6630 | _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP | |
6631 | GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE)); | |
12f3382b | 6632 | |
4e04632e AG |
6633 | /* WaDisable_RenderCache_OperationalFlush:vlv */ |
6634 | I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6635 | ||
ecdb4eb7 | 6636 | /* WaForceL3Serialization:vlv */ |
61939d97 JB |
6637 | I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) & |
6638 | ~L3SQ_URB_READ_CAM_MATCH_DISABLE); | |
6639 | ||
ecdb4eb7 | 6640 | /* WaDisableDopClockGating:vlv */ |
8ab43976 JB |
6641 | I915_WRITE(GEN7_ROW_CHICKEN2, |
6642 | _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE)); | |
6643 | ||
ecdb4eb7 | 6644 | /* This is required by WaCatErrorRejectionIssue:vlv */ |
6f1d69b0 ED |
6645 | I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG, |
6646 | I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) | | |
6647 | GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB); | |
6648 | ||
46680e0a VS |
6649 | gen7_setup_fixed_func_scheduler(dev_priv); |
6650 | ||
3c0edaeb | 6651 | /* |
0f846f81 | 6652 | * According to the spec, bit 13 (RCZUNIT) must be set on IVB. |
ecdb4eb7 | 6653 | * This implements the WaDisableRCZUnitClockGating:vlv workaround. |
0f846f81 JB |
6654 | */ |
6655 | I915_WRITE(GEN6_UCGCTL2, | |
3c0edaeb | 6656 | GEN6_RCZUNIT_CLOCK_GATE_DISABLE); |
0f846f81 | 6657 | |
c98f5062 AG |
6658 | /* WaDisableL3Bank2xClockGate:vlv |
6659 | * Disabling L3 clock gating- MMIO 940c[25] = 1 | |
6660 | * Set bit 25, to disable L3_BANK_2x_CLK_GATING */ | |
6661 | I915_WRITE(GEN7_UCGCTL4, | |
6662 | I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE); | |
e3f33d46 | 6663 | |
e0d8d59b | 6664 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); |
6f1d69b0 | 6665 | |
afd58e79 VS |
6666 | /* |
6667 | * BSpec says this must be set, even though | |
6668 | * WaDisable4x2SubspanOptimization isn't listed for VLV. | |
6669 | */ | |
6b26c86d DV |
6670 | I915_WRITE(CACHE_MODE_1, |
6671 | _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE)); | |
7983117f | 6672 | |
031994ee VS |
6673 | /* |
6674 | * WaIncreaseL3CreditsForVLVB0:vlv | |
6675 | * This is the hardware default actually. | |
6676 | */ | |
6677 | I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE); | |
6678 | ||
2d809570 | 6679 | /* |
ecdb4eb7 | 6680 | * WaDisableVLVClockGating_VBIIssue:vlv |
2d809570 JB |
6681 | * Disable clock gating on th GCFG unit to prevent a delay |
6682 | * in the reporting of vblank events. | |
6683 | */ | |
7a0d1eed | 6684 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS); |
6f1d69b0 ED |
6685 | } |
6686 | ||
a4565da8 VS |
6687 | static void cherryview_init_clock_gating(struct drm_device *dev) |
6688 | { | |
6689 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6690 | ||
6691 | I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE); | |
6692 | ||
6693 | I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE); | |
dd811e70 | 6694 | |
232ce337 VS |
6695 | /* WaVSRefCountFullforceMissDisable:chv */ |
6696 | /* WaDSRefCountFullforceMissDisable:chv */ | |
6697 | I915_WRITE(GEN7_FF_THREAD_MODE, | |
6698 | I915_READ(GEN7_FF_THREAD_MODE) & | |
6699 | ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME)); | |
acea6f95 VS |
6700 | |
6701 | /* WaDisableSemaphoreAndSyncFlipWait:chv */ | |
6702 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6703 | _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE)); | |
0846697c VS |
6704 | |
6705 | /* WaDisableCSUnitClockGating:chv */ | |
6706 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | | |
6707 | GEN6_CSUNIT_CLOCK_GATE_DISABLE); | |
c631780f VS |
6708 | |
6709 | /* WaDisableSDEUnitClockGating:chv */ | |
6710 | I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) | | |
6711 | GEN8_SDEUNIT_CLOCK_GATE_DISABLE); | |
e0d34ce7 | 6712 | |
e4443e45 VS |
6713 | /* WaDisableGunitClockGating:chv (pre-production hw) */ |
6714 | I915_WRITE(VLV_GUNIT_CLOCK_GATE, I915_READ(VLV_GUNIT_CLOCK_GATE) | | |
6715 | GINT_DIS); | |
6716 | ||
6717 | /* WaDisableFfDopClockGating:chv (pre-production hw) */ | |
6718 | I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL, | |
6719 | _MASKED_BIT_ENABLE(GEN8_FF_DOP_CLOCK_GATE_DISABLE)); | |
6720 | ||
6721 | /* WaDisableDopClockGating:chv (pre-production hw) */ | |
e4443e45 VS |
6722 | I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) | |
6723 | GEN6_EU_TCUNIT_CLOCK_GATE_DISABLE); | |
a4565da8 VS |
6724 | } |
6725 | ||
1fa61106 | 6726 | static void g4x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6727 | { |
6728 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6729 | uint32_t dspclk_gate; | |
6730 | ||
6731 | I915_WRITE(RENCLK_GATE_D1, 0); | |
6732 | I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE | | |
6733 | GS_UNIT_CLOCK_GATE_DISABLE | | |
6734 | CL_UNIT_CLOCK_GATE_DISABLE); | |
6735 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6736 | dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE | | |
6737 | OVRUNIT_CLOCK_GATE_DISABLE | | |
6738 | OVCUNIT_CLOCK_GATE_DISABLE; | |
6739 | if (IS_GM45(dev)) | |
6740 | dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE; | |
6741 | I915_WRITE(DSPCLK_GATE_D, dspclk_gate); | |
4358a374 DV |
6742 | |
6743 | /* WaDisableRenderCachePipelinedFlush */ | |
6744 | I915_WRITE(CACHE_MODE_0, | |
6745 | _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE)); | |
de1aa629 | 6746 | |
4e04632e AG |
6747 | /* WaDisable_RenderCache_OperationalFlush:g4x */ |
6748 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6749 | ||
0e088b8f | 6750 | g4x_disable_trickle_feed(dev); |
6f1d69b0 ED |
6751 | } |
6752 | ||
1fa61106 | 6753 | static void crestline_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6754 | { |
6755 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6756 | ||
6757 | I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE); | |
6758 | I915_WRITE(RENCLK_GATE_D2, 0); | |
6759 | I915_WRITE(DSPCLK_GATE_D, 0); | |
6760 | I915_WRITE(RAMCLK_GATE_D, 0); | |
6761 | I915_WRITE16(DEUC, 0); | |
20f94967 VS |
6762 | I915_WRITE(MI_ARB_STATE, |
6763 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6764 | |
6765 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6766 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6767 | } |
6768 | ||
1fa61106 | 6769 | static void broadwater_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6770 | { |
6771 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6772 | ||
6773 | I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE | | |
6774 | I965_RCC_CLOCK_GATE_DISABLE | | |
6775 | I965_RCPB_CLOCK_GATE_DISABLE | | |
6776 | I965_ISC_CLOCK_GATE_DISABLE | | |
6777 | I965_FBC_CLOCK_GATE_DISABLE); | |
6778 | I915_WRITE(RENCLK_GATE_D2, 0); | |
20f94967 VS |
6779 | I915_WRITE(MI_ARB_STATE, |
6780 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
4e04632e AG |
6781 | |
6782 | /* WaDisable_RenderCache_OperationalFlush:gen4 */ | |
6783 | I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE)); | |
6f1d69b0 ED |
6784 | } |
6785 | ||
1fa61106 | 6786 | static void gen3_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6787 | { |
6788 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6789 | u32 dstate = I915_READ(D_STATE); | |
6790 | ||
6791 | dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING | | |
6792 | DSTATE_DOT_CLOCK_GATING; | |
6793 | I915_WRITE(D_STATE, dstate); | |
13a86b85 CW |
6794 | |
6795 | if (IS_PINEVIEW(dev)) | |
6796 | I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY)); | |
974a3b0f DV |
6797 | |
6798 | /* IIR "flip pending" means done if this bit is set */ | |
6799 | I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE)); | |
12fabbcb VS |
6800 | |
6801 | /* interrupts should cause a wake up from C3 */ | |
3299254f | 6802 | I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN)); |
dbb42748 VS |
6803 | |
6804 | /* On GEN3 we really need to make sure the ARB C3 LP bit is set */ | |
6805 | I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE)); | |
1038392b VS |
6806 | |
6807 | I915_WRITE(MI_ARB_STATE, | |
6808 | _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6809 | } |
6810 | ||
1fa61106 | 6811 | static void i85x_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6812 | { |
6813 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6814 | ||
6815 | I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE); | |
54e472ae VS |
6816 | |
6817 | /* interrupts should cause a wake up from C3 */ | |
6818 | I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) | | |
6819 | _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE)); | |
1038392b VS |
6820 | |
6821 | I915_WRITE(MEM_MODE, | |
6822 | _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6823 | } |
6824 | ||
1fa61106 | 6825 | static void i830_init_clock_gating(struct drm_device *dev) |
6f1d69b0 ED |
6826 | { |
6827 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6828 | ||
6829 | I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE); | |
1038392b VS |
6830 | |
6831 | I915_WRITE(MEM_MODE, | |
6832 | _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) | | |
6833 | _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE)); | |
6f1d69b0 ED |
6834 | } |
6835 | ||
6f1d69b0 ED |
6836 | void intel_init_clock_gating(struct drm_device *dev) |
6837 | { | |
6838 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6839 | ||
6840 | dev_priv->display.init_clock_gating(dev); | |
6f1d69b0 ED |
6841 | } |
6842 | ||
7d708ee4 ID |
6843 | void intel_suspend_hw(struct drm_device *dev) |
6844 | { | |
6845 | if (HAS_PCH_LPT(dev)) | |
6846 | lpt_suspend_hw(dev); | |
6847 | } | |
6848 | ||
d2dee86c PZ |
6849 | static void intel_init_fbc(struct drm_i915_private *dev_priv) |
6850 | { | |
9adccc60 PZ |
6851 | if (!HAS_FBC(dev_priv)) { |
6852 | dev_priv->fbc.enabled = false; | |
d2dee86c | 6853 | return; |
9adccc60 | 6854 | } |
d2dee86c PZ |
6855 | |
6856 | if (INTEL_INFO(dev_priv)->gen >= 7) { | |
6857 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
6858 | dev_priv->display.enable_fbc = gen7_enable_fbc; | |
6859 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6860 | } else if (INTEL_INFO(dev_priv)->gen >= 5) { | |
6861 | dev_priv->display.fbc_enabled = ironlake_fbc_enabled; | |
6862 | dev_priv->display.enable_fbc = ironlake_enable_fbc; | |
6863 | dev_priv->display.disable_fbc = ironlake_disable_fbc; | |
6864 | } else if (IS_GM45(dev_priv)) { | |
6865 | dev_priv->display.fbc_enabled = g4x_fbc_enabled; | |
6866 | dev_priv->display.enable_fbc = g4x_enable_fbc; | |
6867 | dev_priv->display.disable_fbc = g4x_disable_fbc; | |
6868 | } else { | |
6869 | dev_priv->display.fbc_enabled = i8xx_fbc_enabled; | |
6870 | dev_priv->display.enable_fbc = i8xx_enable_fbc; | |
6871 | dev_priv->display.disable_fbc = i8xx_disable_fbc; | |
6872 | ||
6873 | /* This value was pulled out of someone's hat */ | |
6874 | I915_WRITE(FBC_CONTROL, 500 << FBC_CTL_INTERVAL_SHIFT); | |
6875 | } | |
9adccc60 PZ |
6876 | |
6877 | dev_priv->fbc.enabled = dev_priv->display.fbc_enabled(dev_priv->dev); | |
d2dee86c PZ |
6878 | } |
6879 | ||
1fa61106 ED |
6880 | /* Set up chip specific power management-related functions */ |
6881 | void intel_init_pm(struct drm_device *dev) | |
6882 | { | |
6883 | struct drm_i915_private *dev_priv = dev->dev_private; | |
6884 | ||
d2dee86c | 6885 | intel_init_fbc(dev_priv); |
1fa61106 | 6886 | |
c921aba8 DV |
6887 | /* For cxsr */ |
6888 | if (IS_PINEVIEW(dev)) | |
6889 | i915_pineview_get_mem_freq(dev); | |
6890 | else if (IS_GEN5(dev)) | |
6891 | i915_ironlake_get_mem_freq(dev); | |
6892 | ||
1fa61106 | 6893 | /* For FIFO watermark updates */ |
c83155a6 | 6894 | if (IS_GEN9(dev)) { |
2af30a5c PB |
6895 | skl_setup_wm_latency(dev); |
6896 | ||
c83155a6 | 6897 | dev_priv->display.init_clock_gating = gen9_init_clock_gating; |
2d41c0b5 PB |
6898 | dev_priv->display.update_wm = skl_update_wm; |
6899 | dev_priv->display.update_sprite_wm = skl_update_sprite_wm; | |
c83155a6 | 6900 | } else if (HAS_PCH_SPLIT(dev)) { |
fa50ad61 | 6901 | ilk_setup_wm_latency(dev); |
53615a5e | 6902 | |
bd602544 VS |
6903 | if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] && |
6904 | dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) || | |
6905 | (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] && | |
6906 | dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) { | |
6907 | dev_priv->display.update_wm = ilk_update_wm; | |
6908 | dev_priv->display.update_sprite_wm = ilk_update_sprite_wm; | |
6909 | } else { | |
6910 | DRM_DEBUG_KMS("Failed to read display plane latency. " | |
6911 | "Disable CxSR\n"); | |
6912 | } | |
6913 | ||
6914 | if (IS_GEN5(dev)) | |
1fa61106 | 6915 | dev_priv->display.init_clock_gating = ironlake_init_clock_gating; |
bd602544 | 6916 | else if (IS_GEN6(dev)) |
1fa61106 | 6917 | dev_priv->display.init_clock_gating = gen6_init_clock_gating; |
bd602544 | 6918 | else if (IS_IVYBRIDGE(dev)) |
1fa61106 | 6919 | dev_priv->display.init_clock_gating = ivybridge_init_clock_gating; |
bd602544 | 6920 | else if (IS_HASWELL(dev)) |
cad2a2d7 | 6921 | dev_priv->display.init_clock_gating = haswell_init_clock_gating; |
bd602544 | 6922 | else if (INTEL_INFO(dev)->gen == 8) |
47c2bd97 | 6923 | dev_priv->display.init_clock_gating = broadwell_init_clock_gating; |
a4565da8 | 6924 | } else if (IS_CHERRYVIEW(dev)) { |
3c2777fd | 6925 | dev_priv->display.update_wm = cherryview_update_wm; |
01e184cc | 6926 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
a4565da8 VS |
6927 | dev_priv->display.init_clock_gating = |
6928 | cherryview_init_clock_gating; | |
1fa61106 ED |
6929 | } else if (IS_VALLEYVIEW(dev)) { |
6930 | dev_priv->display.update_wm = valleyview_update_wm; | |
01e184cc | 6931 | dev_priv->display.update_sprite_wm = valleyview_update_sprite_wm; |
1fa61106 ED |
6932 | dev_priv->display.init_clock_gating = |
6933 | valleyview_init_clock_gating; | |
1fa61106 ED |
6934 | } else if (IS_PINEVIEW(dev)) { |
6935 | if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev), | |
6936 | dev_priv->is_ddr3, | |
6937 | dev_priv->fsb_freq, | |
6938 | dev_priv->mem_freq)) { | |
6939 | DRM_INFO("failed to find known CxSR latency " | |
6940 | "(found ddr%s fsb freq %d, mem freq %d), " | |
6941 | "disabling CxSR\n", | |
6942 | (dev_priv->is_ddr3 == 1) ? "3" : "2", | |
6943 | dev_priv->fsb_freq, dev_priv->mem_freq); | |
6944 | /* Disable CxSR and never update its watermark again */ | |
5209b1f4 | 6945 | intel_set_memory_cxsr(dev_priv, false); |
1fa61106 ED |
6946 | dev_priv->display.update_wm = NULL; |
6947 | } else | |
6948 | dev_priv->display.update_wm = pineview_update_wm; | |
6949 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
6950 | } else if (IS_G4X(dev)) { | |
6951 | dev_priv->display.update_wm = g4x_update_wm; | |
6952 | dev_priv->display.init_clock_gating = g4x_init_clock_gating; | |
6953 | } else if (IS_GEN4(dev)) { | |
6954 | dev_priv->display.update_wm = i965_update_wm; | |
6955 | if (IS_CRESTLINE(dev)) | |
6956 | dev_priv->display.init_clock_gating = crestline_init_clock_gating; | |
6957 | else if (IS_BROADWATER(dev)) | |
6958 | dev_priv->display.init_clock_gating = broadwater_init_clock_gating; | |
6959 | } else if (IS_GEN3(dev)) { | |
6960 | dev_priv->display.update_wm = i9xx_update_wm; | |
6961 | dev_priv->display.get_fifo_size = i9xx_get_fifo_size; | |
6962 | dev_priv->display.init_clock_gating = gen3_init_clock_gating; | |
feb56b93 DV |
6963 | } else if (IS_GEN2(dev)) { |
6964 | if (INTEL_INFO(dev)->num_pipes == 1) { | |
6965 | dev_priv->display.update_wm = i845_update_wm; | |
1fa61106 | 6966 | dev_priv->display.get_fifo_size = i845_get_fifo_size; |
feb56b93 DV |
6967 | } else { |
6968 | dev_priv->display.update_wm = i9xx_update_wm; | |
1fa61106 | 6969 | dev_priv->display.get_fifo_size = i830_get_fifo_size; |
feb56b93 DV |
6970 | } |
6971 | ||
6972 | if (IS_I85X(dev) || IS_I865G(dev)) | |
6973 | dev_priv->display.init_clock_gating = i85x_init_clock_gating; | |
6974 | else | |
6975 | dev_priv->display.init_clock_gating = i830_init_clock_gating; | |
6976 | } else { | |
6977 | DRM_ERROR("unexpected fall-through in intel_init_pm\n"); | |
1fa61106 ED |
6978 | } |
6979 | } | |
6980 | ||
42c0526c BW |
6981 | int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val) |
6982 | { | |
4fc688ce | 6983 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
6984 | |
6985 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
6986 | DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n"); | |
6987 | return -EAGAIN; | |
6988 | } | |
6989 | ||
6990 | I915_WRITE(GEN6_PCODE_DATA, *val); | |
2af30a5c PB |
6991 | if (INTEL_INFO(dev_priv)->gen >= 9) |
6992 | I915_WRITE(GEN9_PCODE_DATA1, 0); | |
42c0526c BW |
6993 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); |
6994 | ||
6995 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
6996 | 500)) { | |
6997 | DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox); | |
6998 | return -ETIMEDOUT; | |
6999 | } | |
7000 | ||
7001 | *val = I915_READ(GEN6_PCODE_DATA); | |
7002 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7003 | ||
7004 | return 0; | |
7005 | } | |
7006 | ||
7007 | int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val) | |
7008 | { | |
4fc688ce | 7009 | WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock)); |
42c0526c BW |
7010 | |
7011 | if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) { | |
7012 | DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n"); | |
7013 | return -EAGAIN; | |
7014 | } | |
7015 | ||
7016 | I915_WRITE(GEN6_PCODE_DATA, val); | |
7017 | I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox); | |
7018 | ||
7019 | if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0, | |
7020 | 500)) { | |
7021 | DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox); | |
7022 | return -ETIMEDOUT; | |
7023 | } | |
7024 | ||
7025 | I915_WRITE(GEN6_PCODE_DATA, 0); | |
7026 | ||
7027 | return 0; | |
7028 | } | |
a0e4e199 | 7029 | |
b55dd647 | 7030 | static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7031 | { |
07ab118b | 7032 | int div; |
855ba3be | 7033 | |
07ab118b | 7034 | /* 4 x czclk */ |
2ec3815f | 7035 | switch (dev_priv->mem_freq) { |
855ba3be | 7036 | case 800: |
07ab118b | 7037 | div = 10; |
855ba3be JB |
7038 | break; |
7039 | case 1066: | |
07ab118b | 7040 | div = 12; |
855ba3be JB |
7041 | break; |
7042 | case 1333: | |
07ab118b | 7043 | div = 16; |
855ba3be JB |
7044 | break; |
7045 | default: | |
7046 | return -1; | |
7047 | } | |
7048 | ||
2ec3815f | 7049 | return DIV_ROUND_CLOSEST(dev_priv->mem_freq * (val + 6 - 0xbd), 4 * div); |
855ba3be JB |
7050 | } |
7051 | ||
b55dd647 | 7052 | static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val) |
855ba3be | 7053 | { |
07ab118b | 7054 | int mul; |
855ba3be | 7055 | |
07ab118b | 7056 | /* 4 x czclk */ |
2ec3815f | 7057 | switch (dev_priv->mem_freq) { |
855ba3be | 7058 | case 800: |
07ab118b | 7059 | mul = 10; |
855ba3be JB |
7060 | break; |
7061 | case 1066: | |
07ab118b | 7062 | mul = 12; |
855ba3be JB |
7063 | break; |
7064 | case 1333: | |
07ab118b | 7065 | mul = 16; |
855ba3be JB |
7066 | break; |
7067 | default: | |
7068 | return -1; | |
7069 | } | |
7070 | ||
2ec3815f | 7071 | return DIV_ROUND_CLOSEST(4 * mul * val, dev_priv->mem_freq) + 0xbd - 6; |
855ba3be JB |
7072 | } |
7073 | ||
b55dd647 | 7074 | static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 D |
7075 | { |
7076 | int div, freq; | |
7077 | ||
7078 | switch (dev_priv->rps.cz_freq) { | |
7079 | case 200: | |
7080 | div = 5; | |
7081 | break; | |
7082 | case 267: | |
7083 | div = 6; | |
7084 | break; | |
7085 | case 320: | |
7086 | case 333: | |
7087 | case 400: | |
7088 | div = 8; | |
7089 | break; | |
7090 | default: | |
7091 | return -1; | |
7092 | } | |
7093 | ||
7094 | freq = (DIV_ROUND_CLOSEST((dev_priv->rps.cz_freq * val), 2 * div) / 2); | |
7095 | ||
7096 | return freq; | |
7097 | } | |
7098 | ||
b55dd647 | 7099 | static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val) |
22b1b2f8 D |
7100 | { |
7101 | int mul, opcode; | |
7102 | ||
7103 | switch (dev_priv->rps.cz_freq) { | |
7104 | case 200: | |
7105 | mul = 5; | |
7106 | break; | |
7107 | case 267: | |
7108 | mul = 6; | |
7109 | break; | |
7110 | case 320: | |
7111 | case 333: | |
7112 | case 400: | |
7113 | mul = 8; | |
7114 | break; | |
7115 | default: | |
7116 | return -1; | |
7117 | } | |
7118 | ||
1c14762d | 7119 | /* CHV needs even values */ |
22b1b2f8 D |
7120 | opcode = (DIV_ROUND_CLOSEST((val * 2 * mul), dev_priv->rps.cz_freq) * 2); |
7121 | ||
7122 | return opcode; | |
7123 | } | |
7124 | ||
7125 | int vlv_gpu_freq(struct drm_i915_private *dev_priv, int val) | |
7126 | { | |
7127 | int ret = -1; | |
7128 | ||
7129 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
7130 | ret = chv_gpu_freq(dev_priv, val); | |
7131 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
7132 | ret = byt_gpu_freq(dev_priv, val); | |
7133 | ||
7134 | return ret; | |
7135 | } | |
7136 | ||
7137 | int vlv_freq_opcode(struct drm_i915_private *dev_priv, int val) | |
7138 | { | |
7139 | int ret = -1; | |
7140 | ||
7141 | if (IS_CHERRYVIEW(dev_priv->dev)) | |
7142 | ret = chv_freq_opcode(dev_priv, val); | |
7143 | else if (IS_VALLEYVIEW(dev_priv->dev)) | |
7144 | ret = byt_freq_opcode(dev_priv, val); | |
7145 | ||
7146 | return ret; | |
7147 | } | |
7148 | ||
f742a552 | 7149 | void intel_pm_setup(struct drm_device *dev) |
907b28c5 CW |
7150 | { |
7151 | struct drm_i915_private *dev_priv = dev->dev_private; | |
7152 | ||
f742a552 DV |
7153 | mutex_init(&dev_priv->rps.hw_lock); |
7154 | ||
907b28c5 CW |
7155 | INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work, |
7156 | intel_gen6_powersave_work); | |
5d584b2e | 7157 | |
33688d95 | 7158 | dev_priv->pm.suspended = false; |
907b28c5 | 7159 | } |