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drm/i915: Use 'enabled' instead of 'enable' consistently in sprite WM code
[mirror_ubuntu-bionic-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
f4db9321 33#include <drm/i915_powerwell.h>
85208be0 34
f6750b3c
ED		 35/* FBC, or Frame Buffer Compression, is a technique employed to compress the
36 * framebuffer contents in-memory, aiming at reducing the required bandwidth
37 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 38 *
f6750b3c
ED		 39 * The benefits of FBC are mostly visible with solid backgrounds and
40 * variation-less patterns.
85208be0 41 *
f6750b3c
ED		 42 * FBC-related functionality can be enabled by the means of the
43 * i915.i915_enable_fbc parameter
85208be0
ED		 44 */
45
3490ea5d
CW		 46static bool intel_crtc_active(struct drm_crtc *crtc)
47{
48 /* Be paranoid as we can arrive here with only partial
49 * state retrieved from the hardware during setup.
50 */
51 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
52}
53
1fa61106 54static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 55{
56 struct drm_i915_private *dev_priv = dev->dev_private;
57 u32 fbc_ctl;
58
59 /* Disable compression */
60 fbc_ctl = I915_READ(FBC_CONTROL);
61 if ((fbc_ctl & FBC_CTL_EN) == 0)
62 return;
63
64 fbc_ctl &= ~FBC_CTL_EN;
65 I915_WRITE(FBC_CONTROL, fbc_ctl);
66
67 /* Wait for compressing bit to clear */
68 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
69 DRM_DEBUG_KMS("FBC idle timed out\n");
70 return;
71 }
72
73 DRM_DEBUG_KMS("disabled FBC\n");
74}
75
1fa61106 76static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 77{
78 struct drm_device *dev = crtc->dev;
79 struct drm_i915_private *dev_priv = dev->dev_private;
80 struct drm_framebuffer *fb = crtc->fb;
81 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
82 struct drm_i915_gem_object *obj = intel_fb->obj;
83 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
84 int cfb_pitch;
85 int plane, i;
86 u32 fbc_ctl, fbc_ctl2;
87
5c3fe8b0 88 cfb_pitch = dev_priv->fbc.size / FBC_LL_SIZE;
85208be0
ED		 89 if (fb->pitches[0] < cfb_pitch)
90 cfb_pitch = fb->pitches[0];
91
92 /* FBC_CTL wants 64B units */
93 cfb_pitch = (cfb_pitch / 64) - 1;
94 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
95
96 /* Clear old tags */
97 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
98 I915_WRITE(FBC_TAG + (i * 4), 0);
99
100 /* Set it up... */
101 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
102 fbc_ctl2 |= plane;
103 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
104 I915_WRITE(FBC_FENCE_OFF, crtc->y);
105
106 /* enable it... */
107 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
108 if (IS_I945GM(dev))
109 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
110 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
111 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
112 fbc_ctl |= obj->fence_reg;
113 I915_WRITE(FBC_CONTROL, fbc_ctl);
114
84f44ce7
VS		 115 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %c, ",
116 cfb_pitch, crtc->y, plane_name(intel_crtc->plane));
85208be0
ED		 117}
118
1fa61106 119static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 120{
121 struct drm_i915_private *dev_priv = dev->dev_private;
122
123 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
124}
125
1fa61106 126static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 127{
128 struct drm_device *dev = crtc->dev;
129 struct drm_i915_private *dev_priv = dev->dev_private;
130 struct drm_framebuffer *fb = crtc->fb;
131 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
132 struct drm_i915_gem_object *obj = intel_fb->obj;
133 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
134 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
135 unsigned long stall_watermark = 200;
136 u32 dpfc_ctl;
137
138 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
139 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
140 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
141
142 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
143 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
144 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
145 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
146
147 /* enable it... */
148 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
149
84f44ce7 150 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 151}
152
1fa61106 153static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 154{
155 struct drm_i915_private *dev_priv = dev->dev_private;
156 u32 dpfc_ctl;
157
158 /* Disable compression */
159 dpfc_ctl = I915_READ(DPFC_CONTROL);
160 if (dpfc_ctl & DPFC_CTL_EN) {
161 dpfc_ctl &= ~DPFC_CTL_EN;
162 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
163
164 DRM_DEBUG_KMS("disabled FBC\n");
165 }
166}
167
1fa61106 168static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 169{
170 struct drm_i915_private *dev_priv = dev->dev_private;
171
172 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
173}
174
175static void sandybridge_blit_fbc_update(struct drm_device *dev)
176{
177 struct drm_i915_private *dev_priv = dev->dev_private;
178 u32 blt_ecoskpd;
179
180 /* Make sure blitter notifies FBC of writes */
181 gen6_gt_force_wake_get(dev_priv);
182 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
183 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
184 GEN6_BLITTER_LOCK_SHIFT;
185 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
186 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
187 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
188 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
189 GEN6_BLITTER_LOCK_SHIFT);
190 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
191 POSTING_READ(GEN6_BLITTER_ECOSKPD);
192 gen6_gt_force_wake_put(dev_priv);
193}
194
1fa61106 195static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 196{
197 struct drm_device *dev = crtc->dev;
198 struct drm_i915_private *dev_priv = dev->dev_private;
199 struct drm_framebuffer *fb = crtc->fb;
200 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
201 struct drm_i915_gem_object *obj = intel_fb->obj;
202 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
203 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
204 unsigned long stall_watermark = 200;
205 u32 dpfc_ctl;
206
207 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
208 dpfc_ctl &= DPFC_RESERVED;
209 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
210 /* Set persistent mode for front-buffer rendering, ala X. */
211 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
212 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
213 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
214
215 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
216 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
217 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
218 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
f343c5f6 219 I915_WRITE(ILK_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj) | ILK_FBC_RT_VALID);
85208be0
ED		 220 /* enable it... */
221 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
222
223 if (IS_GEN6(dev)) {
224 I915_WRITE(SNB_DPFC_CTL_SA,
225 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
226 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
227 sandybridge_blit_fbc_update(dev);
228 }
229
84f44ce7 230 DRM_DEBUG_KMS("enabled fbc on plane %c\n", plane_name(intel_crtc->plane));
85208be0
ED		 231}
232
1fa61106 233static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 234{
235 struct drm_i915_private *dev_priv = dev->dev_private;
236 u32 dpfc_ctl;
237
238 /* Disable compression */
239 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
240 if (dpfc_ctl & DPFC_CTL_EN) {
241 dpfc_ctl &= ~DPFC_CTL_EN;
242 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
243
b74ea102 244 if (IS_IVYBRIDGE(dev))
7dd23ba0 245 /* WaFbcDisableDpfcClockGating:ivb */
b74ea102
RV		 246 I915_WRITE(ILK_DSPCLK_GATE_D,
247 I915_READ(ILK_DSPCLK_GATE_D) &
248 ~ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
249
d89f2071 250 if (IS_HASWELL(dev))
7dd23ba0 251 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 252 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
253 I915_READ(HSW_CLKGATE_DISABLE_PART_1) &
254 ~HSW_DPFC_GATING_DISABLE);
255
85208be0
ED		 256 DRM_DEBUG_KMS("disabled FBC\n");
257 }
258}
259
1fa61106 260static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 261{
262 struct drm_i915_private *dev_priv = dev->dev_private;
263
264 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
265}
266
abe959c7
RV		 267static void gen7_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
268{
269 struct drm_device *dev = crtc->dev;
270 struct drm_i915_private *dev_priv = dev->dev_private;
271 struct drm_framebuffer *fb = crtc->fb;
272 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
273 struct drm_i915_gem_object *obj = intel_fb->obj;
274 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
275
f343c5f6 276 I915_WRITE(IVB_FBC_RT_BASE, i915_gem_obj_ggtt_offset(obj));
abe959c7
RV		 277
278 I915_WRITE(ILK_DPFC_CONTROL, DPFC_CTL_EN | DPFC_CTL_LIMIT_1X |
279 IVB_DPFC_CTL_FENCE_EN |
280 intel_crtc->plane << IVB_DPFC_CTL_PLANE_SHIFT);
281
891348b2 282 if (IS_IVYBRIDGE(dev)) {
7dd23ba0 283 /* WaFbcAsynchFlipDisableFbcQueue:ivb */
891348b2 284 I915_WRITE(ILK_DISPLAY_CHICKEN1, ILK_FBCQ_DIS);
7dd23ba0 285 /* WaFbcDisableDpfcClockGating:ivb */
891348b2
RV		 286 I915_WRITE(ILK_DSPCLK_GATE_D,
287 I915_READ(ILK_DSPCLK_GATE_D) |
288 ILK_DPFCUNIT_CLOCK_GATE_DISABLE);
28554164 289 } else {
7dd23ba0 290 /* WaFbcAsynchFlipDisableFbcQueue:hsw */
28554164
RV		 291 I915_WRITE(HSW_PIPE_SLICE_CHICKEN_1(intel_crtc->pipe),
292 HSW_BYPASS_FBC_QUEUE);
7dd23ba0 293 /* WaFbcDisableDpfcClockGating:hsw */
d89f2071
RV		 294 I915_WRITE(HSW_CLKGATE_DISABLE_PART_1,
295 I915_READ(HSW_CLKGATE_DISABLE_PART_1) |
296 HSW_DPFC_GATING_DISABLE);
891348b2 297 }
b74ea102 298
abe959c7
RV		 299 I915_WRITE(SNB_DPFC_CTL_SA,
300 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
301 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
302
303 sandybridge_blit_fbc_update(dev);
304
305 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
306}
307
85208be0
ED		 308bool intel_fbc_enabled(struct drm_device *dev)
309{
310 struct drm_i915_private *dev_priv = dev->dev_private;
311
312 if (!dev_priv->display.fbc_enabled)
313 return false;
314
315 return dev_priv->display.fbc_enabled(dev);
316}
317
318static void intel_fbc_work_fn(struct work_struct *__work)
319{
320 struct intel_fbc_work *work =
321 container_of(to_delayed_work(__work),
322 struct intel_fbc_work, work);
323 struct drm_device *dev = work->crtc->dev;
324 struct drm_i915_private *dev_priv = dev->dev_private;
325
326 mutex_lock(&dev->struct_mutex);
5c3fe8b0 327 if (work == dev_priv->fbc.fbc_work) {
85208be0
ED		 328 /* Double check that we haven't switched fb without cancelling
329 * the prior work.
330 */
331 if (work->crtc->fb == work->fb) {
332 dev_priv->display.enable_fbc(work->crtc,
333 work->interval);
334
5c3fe8b0
BW		 335 dev_priv->fbc.plane = to_intel_crtc(work->crtc)->plane;
336 dev_priv->fbc.fb_id = work->crtc->fb->base.id;
337 dev_priv->fbc.y = work->crtc->y;
85208be0
ED		 338 }
339
5c3fe8b0 340 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 341 }
342 mutex_unlock(&dev->struct_mutex);
343
344 kfree(work);
345}
346
347static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
348{
5c3fe8b0 349 if (dev_priv->fbc.fbc_work == NULL)
85208be0
ED		 350 return;
351
352 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
353
354 /* Synchronisation is provided by struct_mutex and checking of
5c3fe8b0 355 * dev_priv->fbc.fbc_work, so we can perform the cancellation
85208be0
ED		 356 * entirely asynchronously.
357 */
5c3fe8b0 358 if (cancel_delayed_work(&dev_priv->fbc.fbc_work->work))
85208be0 359 /* tasklet was killed before being run, clean up */
5c3fe8b0 360 kfree(dev_priv->fbc.fbc_work);
85208be0
ED		 361
362 /* Mark the work as no longer wanted so that if it does
363 * wake-up (because the work was already running and waiting
364 * for our mutex), it will discover that is no longer
365 * necessary to run.
366 */
5c3fe8b0 367 dev_priv->fbc.fbc_work = NULL;
85208be0
ED		 368}
369
b63fb44c 370static void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 371{
372 struct intel_fbc_work *work;
373 struct drm_device *dev = crtc->dev;
374 struct drm_i915_private *dev_priv = dev->dev_private;
375
376 if (!dev_priv->display.enable_fbc)
377 return;
378
379 intel_cancel_fbc_work(dev_priv);
380
381 work = kzalloc(sizeof *work, GFP_KERNEL);
382 if (work == NULL) {
6cdcb5e7 383 DRM_ERROR("Failed to allocate FBC work structure\n");
85208be0
ED		 384 dev_priv->display.enable_fbc(crtc, interval);
385 return;
386 }
387
388 work->crtc = crtc;
389 work->fb = crtc->fb;
390 work->interval = interval;
391 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
392
5c3fe8b0 393 dev_priv->fbc.fbc_work = work;
85208be0 394
85208be0
ED		 395 /* Delay the actual enabling to let pageflipping cease and the
396 * display to settle before starting the compression. Note that
397 * this delay also serves a second purpose: it allows for a
398 * vblank to pass after disabling the FBC before we attempt
399 * to modify the control registers.
400 *
401 * A more complicated solution would involve tracking vblanks
402 * following the termination of the page-flipping sequence
403 * and indeed performing the enable as a co-routine and not
404 * waiting synchronously upon the vblank.
7457d617
DL		 405 *
406 * WaFbcWaitForVBlankBeforeEnable:ilk,snb
85208be0
ED		 407 */
408 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
409}
410
411void intel_disable_fbc(struct drm_device *dev)
412{
413 struct drm_i915_private *dev_priv = dev->dev_private;
414
415 intel_cancel_fbc_work(dev_priv);
416
417 if (!dev_priv->display.disable_fbc)
418 return;
419
420 dev_priv->display.disable_fbc(dev);
5c3fe8b0 421 dev_priv->fbc.plane = -1;
85208be0
ED		 422}
423
29ebf90f
CW		 424static bool set_no_fbc_reason(struct drm_i915_private *dev_priv,
425 enum no_fbc_reason reason)
426{
427 if (dev_priv->fbc.no_fbc_reason == reason)
428 return false;
429
430 dev_priv->fbc.no_fbc_reason = reason;
431 return true;
432}
433
85208be0
ED		 434/**
435 * intel_update_fbc - enable/disable FBC as needed
436 * @dev: the drm_device
437 *
438 * Set up the framebuffer compression hardware at mode set time. We
439 * enable it if possible:
440 * - plane A only (on pre-965)
441 * - no pixel mulitply/line duplication
442 * - no alpha buffer discard
443 * - no dual wide
f85da868 444 * - framebuffer <= max_hdisplay in width, max_vdisplay in height
85208be0
ED		 445 *
446 * We can't assume that any compression will take place (worst case),
447 * so the compressed buffer has to be the same size as the uncompressed
448 * one. It also must reside (along with the line length buffer) in
449 * stolen memory.
450 *
451 * We need to enable/disable FBC on a global basis.
452 */
453void intel_update_fbc(struct drm_device *dev)
454{
455 struct drm_i915_private *dev_priv = dev->dev_private;
456 struct drm_crtc *crtc = NULL, *tmp_crtc;
457 struct intel_crtc *intel_crtc;
458 struct drm_framebuffer *fb;
459 struct intel_framebuffer *intel_fb;
460 struct drm_i915_gem_object *obj;
f85da868 461 unsigned int max_hdisplay, max_vdisplay;
85208be0 462
29ebf90f
CW		 463 if (!I915_HAS_FBC(dev)) {
464 set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED);
85208be0 465 return;
29ebf90f 466 }
85208be0 467
29ebf90f
CW		 468 if (!i915_powersave) {
469 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
470 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0 471 return;
29ebf90f 472 }
85208be0
ED		 473
474 /*
475 * If FBC is already on, we just have to verify that we can
476 * keep it that way...
477 * Need to disable if:
478 * - more than one pipe is active
479 * - changing FBC params (stride, fence, mode)
480 * - new fb is too large to fit in compressed buffer
481 * - going to an unsupported config (interlace, pixel multiply, etc.)
482 */
483 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 484 if (intel_crtc_active(tmp_crtc) &&
485 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0 486 if (crtc) {
29ebf90f
CW		 487 if (set_no_fbc_reason(dev_priv, FBC_MULTIPLE_PIPES))
488 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
85208be0
ED		 489 goto out_disable;
490 }
491 crtc = tmp_crtc;
492 }
493 }
494
495 if (!crtc || crtc->fb == NULL) {
29ebf90f
CW		 496 if (set_no_fbc_reason(dev_priv, FBC_NO_OUTPUT))
497 DRM_DEBUG_KMS("no output, disabling\n");
85208be0
ED		 498 goto out_disable;
499 }
500
501 intel_crtc = to_intel_crtc(crtc);
502 fb = crtc->fb;
503 intel_fb = to_intel_framebuffer(fb);
504 obj = intel_fb->obj;
505
8a5729a3
DL		 506 if (i915_enable_fbc < 0 &&
507 INTEL_INFO(dev)->gen <= 7 && !IS_HASWELL(dev)) {
29ebf90f
CW		 508 if (set_no_fbc_reason(dev_priv, FBC_CHIP_DEFAULT))
509 DRM_DEBUG_KMS("disabled per chip default\n");
8a5729a3 510 goto out_disable;
85208be0 511 }
8a5729a3 512 if (!i915_enable_fbc) {
29ebf90f
CW		 513 if (set_no_fbc_reason(dev_priv, FBC_MODULE_PARAM))
514 DRM_DEBUG_KMS("fbc disabled per module param\n");
85208be0
ED		 515 goto out_disable;
516 }
85208be0
ED		 517 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
518 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
29ebf90f
CW		 519 if (set_no_fbc_reason(dev_priv, FBC_UNSUPPORTED_MODE))
520 DRM_DEBUG_KMS("mode incompatible with compression, "
521 "disabling\n");
85208be0
ED		 522 goto out_disable;
523 }
f85da868
PZ		 524
525 if (IS_G4X(dev) || INTEL_INFO(dev)->gen >= 5) {
526 max_hdisplay = 4096;
527 max_vdisplay = 2048;
528 } else {
529 max_hdisplay = 2048;
530 max_vdisplay = 1536;
531 }
532 if ((crtc->mode.hdisplay > max_hdisplay) ||
533 (crtc->mode.vdisplay > max_vdisplay)) {
29ebf90f
CW		 534 if (set_no_fbc_reason(dev_priv, FBC_MODE_TOO_LARGE))
535 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
85208be0
ED		 536 goto out_disable;
537 }
891348b2
RV		 538 if ((IS_I915GM(dev) || IS_I945GM(dev) || IS_HASWELL(dev)) &&
539 intel_crtc->plane != 0) {
29ebf90f
CW		 540 if (set_no_fbc_reason(dev_priv, FBC_BAD_PLANE))
541 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
85208be0
ED		 542 goto out_disable;
543 }
544
545 /* The use of a CPU fence is mandatory in order to detect writes
546 * by the CPU to the scanout and trigger updates to the FBC.
547 */
548 if (obj->tiling_mode != I915_TILING_X ||
549 obj->fence_reg == I915_FENCE_REG_NONE) {
29ebf90f
CW		 550 if (set_no_fbc_reason(dev_priv, FBC_NOT_TILED))
551 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
85208be0
ED		 552 goto out_disable;
553 }
554
555 /* If the kernel debugger is active, always disable compression */
556 if (in_dbg_master())
557 goto out_disable;
558
11be49eb 559 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
29ebf90f
CW		 560 if (set_no_fbc_reason(dev_priv, FBC_STOLEN_TOO_SMALL))
561 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
11be49eb
CW		 562 goto out_disable;
563 }
564
85208be0
ED		 565 /* If the scanout has not changed, don't modify the FBC settings.
566 * Note that we make the fundamental assumption that the fb->obj
567 * cannot be unpinned (and have its GTT offset and fence revoked)
568 * without first being decoupled from the scanout and FBC disabled.
569 */
5c3fe8b0
BW		 570 if (dev_priv->fbc.plane == intel_crtc->plane &&
571 dev_priv->fbc.fb_id == fb->base.id &&
572 dev_priv->fbc.y == crtc->y)
85208be0
ED		 573 return;
574
575 if (intel_fbc_enabled(dev)) {
576 /* We update FBC along two paths, after changing fb/crtc
577 * configuration (modeswitching) and after page-flipping
578 * finishes. For the latter, we know that not only did
579 * we disable the FBC at the start of the page-flip
580 * sequence, but also more than one vblank has passed.
581 *
582 * For the former case of modeswitching, it is possible
583 * to switch between two FBC valid configurations
584 * instantaneously so we do need to disable the FBC
585 * before we can modify its control registers. We also
586 * have to wait for the next vblank for that to take
587 * effect. However, since we delay enabling FBC we can
588 * assume that a vblank has passed since disabling and
589 * that we can safely alter the registers in the deferred
590 * callback.
591 *
592 * In the scenario that we go from a valid to invalid
593 * and then back to valid FBC configuration we have
594 * no strict enforcement that a vblank occurred since
595 * disabling the FBC. However, along all current pipe
596 * disabling paths we do need to wait for a vblank at
597 * some point. And we wait before enabling FBC anyway.
598 */
599 DRM_DEBUG_KMS("disabling active FBC for update\n");
600 intel_disable_fbc(dev);
601 }
602
603 intel_enable_fbc(crtc, 500);
29ebf90f 604 dev_priv->fbc.no_fbc_reason = FBC_OK;
85208be0
ED		 605 return;
606
607out_disable:
608 /* Multiple disables should be harmless */
609 if (intel_fbc_enabled(dev)) {
610 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
611 intel_disable_fbc(dev);
612 }
11be49eb 613 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 614}
615
c921aba8
DV		 616static void i915_pineview_get_mem_freq(struct drm_device *dev)
617{
618 drm_i915_private_t *dev_priv = dev->dev_private;
619 u32 tmp;
620
621 tmp = I915_READ(CLKCFG);
622
623 switch (tmp & CLKCFG_FSB_MASK) {
624 case CLKCFG_FSB_533:
625 dev_priv->fsb_freq = 533; /* 133*4 */
626 break;
627 case CLKCFG_FSB_800:
628 dev_priv->fsb_freq = 800; /* 200*4 */
629 break;
630 case CLKCFG_FSB_667:
631 dev_priv->fsb_freq = 667; /* 167*4 */
632 break;
633 case CLKCFG_FSB_400:
634 dev_priv->fsb_freq = 400; /* 100*4 */
635 break;
636 }
637
638 switch (tmp & CLKCFG_MEM_MASK) {
639 case CLKCFG_MEM_533:
640 dev_priv->mem_freq = 533;
641 break;
642 case CLKCFG_MEM_667:
643 dev_priv->mem_freq = 667;
644 break;
645 case CLKCFG_MEM_800:
646 dev_priv->mem_freq = 800;
647 break;
648 }
649
650 /* detect pineview DDR3 setting */
651 tmp = I915_READ(CSHRDDR3CTL);
652 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
653}
654
655static void i915_ironlake_get_mem_freq(struct drm_device *dev)
656{
657 drm_i915_private_t *dev_priv = dev->dev_private;
658 u16 ddrpll, csipll;
659
660 ddrpll = I915_READ16(DDRMPLL1);
661 csipll = I915_READ16(CSIPLL0);
662
663 switch (ddrpll & 0xff) {
664 case 0xc:
665 dev_priv->mem_freq = 800;
666 break;
667 case 0x10:
668 dev_priv->mem_freq = 1066;
669 break;
670 case 0x14:
671 dev_priv->mem_freq = 1333;
672 break;
673 case 0x18:
674 dev_priv->mem_freq = 1600;
675 break;
676 default:
677 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
678 ddrpll & 0xff);
679 dev_priv->mem_freq = 0;
680 break;
681 }
682
20e4d407 683 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 684
685 switch (csipll & 0x3ff) {
686 case 0x00c:
687 dev_priv->fsb_freq = 3200;
688 break;
689 case 0x00e:
690 dev_priv->fsb_freq = 3733;
691 break;
692 case 0x010:
693 dev_priv->fsb_freq = 4266;
694 break;
695 case 0x012:
696 dev_priv->fsb_freq = 4800;
697 break;
698 case 0x014:
699 dev_priv->fsb_freq = 5333;
700 break;
701 case 0x016:
702 dev_priv->fsb_freq = 5866;
703 break;
704 case 0x018:
705 dev_priv->fsb_freq = 6400;
706 break;
707 default:
708 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
709 csipll & 0x3ff);
710 dev_priv->fsb_freq = 0;
711 break;
712 }
713
714 if (dev_priv->fsb_freq == 3200) {
20e4d407 715 dev_priv->ips.c_m = 0;
c921aba8 716 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 717 dev_priv->ips.c_m = 1;
c921aba8 718 } else {
20e4d407 719 dev_priv->ips.c_m = 2;
c921aba8
DV		 720 }
721}
722
b445e3b0
ED		 723static const struct cxsr_latency cxsr_latency_table[] = {
724 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
725 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
726 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
727 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
728 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
729
730 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
731 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
732 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
733 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
734 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
735
736 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
737 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
738 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
739 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
740 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
741
742 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
743 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
744 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
745 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
746 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
747
748 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
749 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
750 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
751 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
752 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
753
754 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
755 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
756 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
757 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
758 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
759};
760
63c62275 761static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 762 int is_ddr3,
763 int fsb,
764 int mem)
765{
766 const struct cxsr_latency *latency;
767 int i;
768
769 if (fsb == 0 || mem == 0)
770 return NULL;
771
772 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
773 latency = &cxsr_latency_table[i];
774 if (is_desktop == latency->is_desktop &&
775 is_ddr3 == latency->is_ddr3 &&
776 fsb == latency->fsb_freq && mem == latency->mem_freq)
777 return latency;
778 }
779
780 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
781
782 return NULL;
783}
784
1fa61106 785static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 786{
787 struct drm_i915_private *dev_priv = dev->dev_private;
788
789 /* deactivate cxsr */
790 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
791}
792
793/*
794 * Latency for FIFO fetches is dependent on several factors:
795 * - memory configuration (speed, channels)
796 * - chipset
797 * - current MCH state
798 * It can be fairly high in some situations, so here we assume a fairly
799 * pessimal value. It's a tradeoff between extra memory fetches (if we
800 * set this value too high, the FIFO will fetch frequently to stay full)
801 * and power consumption (set it too low to save power and we might see
802 * FIFO underruns and display "flicker").
803 *
804 * A value of 5us seems to be a good balance; safe for very low end
805 * platforms but not overly aggressive on lower latency configs.
806 */
807static const int latency_ns = 5000;
808
1fa61106 809static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 810{
811 struct drm_i915_private *dev_priv = dev->dev_private;
812 uint32_t dsparb = I915_READ(DSPARB);
813 int size;
814
815 size = dsparb & 0x7f;
816 if (plane)
817 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
818
819 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
820 plane ? "B" : "A", size);
821
822 return size;
823}
824
1fa61106 825static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 826{
827 struct drm_i915_private *dev_priv = dev->dev_private;
828 uint32_t dsparb = I915_READ(DSPARB);
829 int size;
830
831 size = dsparb & 0x1ff;
832 if (plane)
833 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
834 size >>= 1; /* Convert to cachelines */
835
836 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
837 plane ? "B" : "A", size);
838
839 return size;
840}
841
1fa61106 842static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 843{
844 struct drm_i915_private *dev_priv = dev->dev_private;
845 uint32_t dsparb = I915_READ(DSPARB);
846 int size;
847
848 size = dsparb & 0x7f;
849 size >>= 2; /* Convert to cachelines */
850
851 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
852 plane ? "B" : "A",
853 size);
854
855 return size;
856}
857
1fa61106 858static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 859{
860 struct drm_i915_private *dev_priv = dev->dev_private;
861 uint32_t dsparb = I915_READ(DSPARB);
862 int size;
863
864 size = dsparb & 0x7f;
865 size >>= 1; /* Convert to cachelines */
866
867 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
868 plane ? "B" : "A", size);
869
870 return size;
871}
872
873/* Pineview has different values for various configs */
874static const struct intel_watermark_params pineview_display_wm = {
875 PINEVIEW_DISPLAY_FIFO,
876 PINEVIEW_MAX_WM,
877 PINEVIEW_DFT_WM,
878 PINEVIEW_GUARD_WM,
879 PINEVIEW_FIFO_LINE_SIZE
880};
881static const struct intel_watermark_params pineview_display_hplloff_wm = {
882 PINEVIEW_DISPLAY_FIFO,
883 PINEVIEW_MAX_WM,
884 PINEVIEW_DFT_HPLLOFF_WM,
885 PINEVIEW_GUARD_WM,
886 PINEVIEW_FIFO_LINE_SIZE
887};
888static const struct intel_watermark_params pineview_cursor_wm = {
889 PINEVIEW_CURSOR_FIFO,
890 PINEVIEW_CURSOR_MAX_WM,
891 PINEVIEW_CURSOR_DFT_WM,
892 PINEVIEW_CURSOR_GUARD_WM,
893 PINEVIEW_FIFO_LINE_SIZE,
894};
895static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
896 PINEVIEW_CURSOR_FIFO,
897 PINEVIEW_CURSOR_MAX_WM,
898 PINEVIEW_CURSOR_DFT_WM,
899 PINEVIEW_CURSOR_GUARD_WM,
900 PINEVIEW_FIFO_LINE_SIZE
901};
902static const struct intel_watermark_params g4x_wm_info = {
903 G4X_FIFO_SIZE,
904 G4X_MAX_WM,
905 G4X_MAX_WM,
906 2,
907 G4X_FIFO_LINE_SIZE,
908};
909static const struct intel_watermark_params g4x_cursor_wm_info = {
910 I965_CURSOR_FIFO,
911 I965_CURSOR_MAX_WM,
912 I965_CURSOR_DFT_WM,
913 2,
914 G4X_FIFO_LINE_SIZE,
915};
916static const struct intel_watermark_params valleyview_wm_info = {
917 VALLEYVIEW_FIFO_SIZE,
918 VALLEYVIEW_MAX_WM,
919 VALLEYVIEW_MAX_WM,
920 2,
921 G4X_FIFO_LINE_SIZE,
922};
923static const struct intel_watermark_params valleyview_cursor_wm_info = {
924 I965_CURSOR_FIFO,
925 VALLEYVIEW_CURSOR_MAX_WM,
926 I965_CURSOR_DFT_WM,
927 2,
928 G4X_FIFO_LINE_SIZE,
929};
930static const struct intel_watermark_params i965_cursor_wm_info = {
931 I965_CURSOR_FIFO,
932 I965_CURSOR_MAX_WM,
933 I965_CURSOR_DFT_WM,
934 2,
935 I915_FIFO_LINE_SIZE,
936};
937static const struct intel_watermark_params i945_wm_info = {
938 I945_FIFO_SIZE,
939 I915_MAX_WM,
940 1,
941 2,
942 I915_FIFO_LINE_SIZE
943};
944static const struct intel_watermark_params i915_wm_info = {
945 I915_FIFO_SIZE,
946 I915_MAX_WM,
947 1,
948 2,
949 I915_FIFO_LINE_SIZE
950};
951static const struct intel_watermark_params i855_wm_info = {
952 I855GM_FIFO_SIZE,
953 I915_MAX_WM,
954 1,
955 2,
956 I830_FIFO_LINE_SIZE
957};
958static const struct intel_watermark_params i830_wm_info = {
959 I830_FIFO_SIZE,
960 I915_MAX_WM,
961 1,
962 2,
963 I830_FIFO_LINE_SIZE
964};
965
966static const struct intel_watermark_params ironlake_display_wm_info = {
967 ILK_DISPLAY_FIFO,
968 ILK_DISPLAY_MAXWM,
969 ILK_DISPLAY_DFTWM,
970 2,
971 ILK_FIFO_LINE_SIZE
972};
973static const struct intel_watermark_params ironlake_cursor_wm_info = {
974 ILK_CURSOR_FIFO,
975 ILK_CURSOR_MAXWM,
976 ILK_CURSOR_DFTWM,
977 2,
978 ILK_FIFO_LINE_SIZE
979};
980static const struct intel_watermark_params ironlake_display_srwm_info = {
981 ILK_DISPLAY_SR_FIFO,
982 ILK_DISPLAY_MAX_SRWM,
983 ILK_DISPLAY_DFT_SRWM,
984 2,
985 ILK_FIFO_LINE_SIZE
986};
987static const struct intel_watermark_params ironlake_cursor_srwm_info = {
988 ILK_CURSOR_SR_FIFO,
989 ILK_CURSOR_MAX_SRWM,
990 ILK_CURSOR_DFT_SRWM,
991 2,
992 ILK_FIFO_LINE_SIZE
993};
994
995static const struct intel_watermark_params sandybridge_display_wm_info = {
996 SNB_DISPLAY_FIFO,
997 SNB_DISPLAY_MAXWM,
998 SNB_DISPLAY_DFTWM,
999 2,
1000 SNB_FIFO_LINE_SIZE
1001};
1002static const struct intel_watermark_params sandybridge_cursor_wm_info = {
1003 SNB_CURSOR_FIFO,
1004 SNB_CURSOR_MAXWM,
1005 SNB_CURSOR_DFTWM,
1006 2,
1007 SNB_FIFO_LINE_SIZE
1008};
1009static const struct intel_watermark_params sandybridge_display_srwm_info = {
1010 SNB_DISPLAY_SR_FIFO,
1011 SNB_DISPLAY_MAX_SRWM,
1012 SNB_DISPLAY_DFT_SRWM,
1013 2,
1014 SNB_FIFO_LINE_SIZE
1015};
1016static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
1017 SNB_CURSOR_SR_FIFO,
1018 SNB_CURSOR_MAX_SRWM,
1019 SNB_CURSOR_DFT_SRWM,
1020 2,
1021 SNB_FIFO_LINE_SIZE
1022};
1023
1024
1025/**
1026 * intel_calculate_wm - calculate watermark level
1027 * @clock_in_khz: pixel clock
1028 * @wm: chip FIFO params
1029 * @pixel_size: display pixel size
1030 * @latency_ns: memory latency for the platform
1031 *
1032 * Calculate the watermark level (the level at which the display plane will
1033 * start fetching from memory again). Each chip has a different display
1034 * FIFO size and allocation, so the caller needs to figure that out and pass
1035 * in the correct intel_watermark_params structure.
1036 *
1037 * As the pixel clock runs, the FIFO will be drained at a rate that depends
1038 * on the pixel size. When it reaches the watermark level, it'll start
1039 * fetching FIFO line sized based chunks from memory until the FIFO fills
1040 * past the watermark point. If the FIFO drains completely, a FIFO underrun
1041 * will occur, and a display engine hang could result.
1042 */
1043static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
1044 const struct intel_watermark_params *wm,
1045 int fifo_size,
1046 int pixel_size,
1047 unsigned long latency_ns)
1048{
1049 long entries_required, wm_size;
1050
1051 /*
1052 * Note: we need to make sure we don't overflow for various clock &
1053 * latency values.
1054 * clocks go from a few thousand to several hundred thousand.
1055 * latency is usually a few thousand
1056 */
1057 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
1058 1000;
1059 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
1060
1061 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
1062
1063 wm_size = fifo_size - (entries_required + wm->guard_size);
1064
1065 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
1066
1067 /* Don't promote wm_size to unsigned... */
1068 if (wm_size > (long)wm->max_wm)
1069 wm_size = wm->max_wm;
1070 if (wm_size <= 0)
1071 wm_size = wm->default_wm;
1072 return wm_size;
1073}
1074
1075static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1076{
1077 struct drm_crtc *crtc, *enabled = NULL;
1078
1079 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1080 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1081 if (enabled)
1082 return NULL;
1083 enabled = crtc;
1084 }
1085 }
1086
1087 return enabled;
1088}
1089
1fa61106 1090static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1091{
1092 struct drm_i915_private *dev_priv = dev->dev_private;
1093 struct drm_crtc *crtc;
1094 const struct cxsr_latency *latency;
1095 u32 reg;
1096 unsigned long wm;
1097
1098 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1099 dev_priv->fsb_freq, dev_priv->mem_freq);
1100 if (!latency) {
1101 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1102 pineview_disable_cxsr(dev);
1103 return;
1104 }
1105
1106 crtc = single_enabled_crtc(dev);
1107 if (crtc) {
1108 int clock = crtc->mode.clock;
1109 int pixel_size = crtc->fb->bits_per_pixel / 8;
1110
1111 /* Display SR */
1112 wm = intel_calculate_wm(clock, &pineview_display_wm,
1113 pineview_display_wm.fifo_size,
1114 pixel_size, latency->display_sr);
1115 reg = I915_READ(DSPFW1);
1116 reg &= ~DSPFW_SR_MASK;
1117 reg |= wm << DSPFW_SR_SHIFT;
1118 I915_WRITE(DSPFW1, reg);
1119 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1120
1121 /* cursor SR */
1122 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1123 pineview_display_wm.fifo_size,
1124 pixel_size, latency->cursor_sr);
1125 reg = I915_READ(DSPFW3);
1126 reg &= ~DSPFW_CURSOR_SR_MASK;
1127 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1128 I915_WRITE(DSPFW3, reg);
1129
1130 /* Display HPLL off SR */
1131 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1132 pineview_display_hplloff_wm.fifo_size,
1133 pixel_size, latency->display_hpll_disable);
1134 reg = I915_READ(DSPFW3);
1135 reg &= ~DSPFW_HPLL_SR_MASK;
1136 reg |= wm & DSPFW_HPLL_SR_MASK;
1137 I915_WRITE(DSPFW3, reg);
1138
1139 /* cursor HPLL off SR */
1140 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1141 pineview_display_hplloff_wm.fifo_size,
1142 pixel_size, latency->cursor_hpll_disable);
1143 reg = I915_READ(DSPFW3);
1144 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1145 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1146 I915_WRITE(DSPFW3, reg);
1147 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1148
1149 /* activate cxsr */
1150 I915_WRITE(DSPFW3,
1151 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1152 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1153 } else {
1154 pineview_disable_cxsr(dev);
1155 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1156 }
1157}
1158
1159static bool g4x_compute_wm0(struct drm_device *dev,
1160 int plane,
1161 const struct intel_watermark_params *display,
1162 int display_latency_ns,
1163 const struct intel_watermark_params *cursor,
1164 int cursor_latency_ns,
1165 int *plane_wm,
1166 int *cursor_wm)
1167{
1168 struct drm_crtc *crtc;
1169 int htotal, hdisplay, clock, pixel_size;
1170 int line_time_us, line_count;
1171 int entries, tlb_miss;
1172
1173 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1174 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1175 *cursor_wm = cursor->guard_size;
1176 *plane_wm = display->guard_size;
1177 return false;
1178 }
1179
1180 htotal = crtc->mode.htotal;
1181 hdisplay = crtc->mode.hdisplay;
1182 clock = crtc->mode.clock;
1183 pixel_size = crtc->fb->bits_per_pixel / 8;
1184
1185 /* Use the small buffer method to calculate plane watermark */
1186 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1187 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1188 if (tlb_miss > 0)
1189 entries += tlb_miss;
1190 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1191 *plane_wm = entries + display->guard_size;
1192 if (*plane_wm > (int)display->max_wm)
1193 *plane_wm = display->max_wm;
1194
1195 /* Use the large buffer method to calculate cursor watermark */
1196 line_time_us = ((htotal * 1000) / clock);
1197 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1198 entries = line_count * 64 * pixel_size;
1199 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1200 if (tlb_miss > 0)
1201 entries += tlb_miss;
1202 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1203 *cursor_wm = entries + cursor->guard_size;
1204 if (*cursor_wm > (int)cursor->max_wm)
1205 *cursor_wm = (int)cursor->max_wm;
1206
1207 return true;
1208}
1209
1210/*
1211 * Check the wm result.
1212 *
1213 * If any calculated watermark values is larger than the maximum value that
1214 * can be programmed into the associated watermark register, that watermark
1215 * must be disabled.
1216 */
1217static bool g4x_check_srwm(struct drm_device *dev,
1218 int display_wm, int cursor_wm,
1219 const struct intel_watermark_params *display,
1220 const struct intel_watermark_params *cursor)
1221{
1222 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1223 display_wm, cursor_wm);
1224
1225 if (display_wm > display->max_wm) {
1226 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1227 display_wm, display->max_wm);
1228 return false;
1229 }
1230
1231 if (cursor_wm > cursor->max_wm) {
1232 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1233 cursor_wm, cursor->max_wm);
1234 return false;
1235 }
1236
1237 if (!(display_wm || cursor_wm)) {
1238 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1239 return false;
1240 }
1241
1242 return true;
1243}
1244
1245static bool g4x_compute_srwm(struct drm_device *dev,
1246 int plane,
1247 int latency_ns,
1248 const struct intel_watermark_params *display,
1249 const struct intel_watermark_params *cursor,
1250 int *display_wm, int *cursor_wm)
1251{
1252 struct drm_crtc *crtc;
1253 int hdisplay, htotal, pixel_size, clock;
1254 unsigned long line_time_us;
1255 int line_count, line_size;
1256 int small, large;
1257 int entries;
1258
1259 if (!latency_ns) {
1260 *display_wm = *cursor_wm = 0;
1261 return false;
1262 }
1263
1264 crtc = intel_get_crtc_for_plane(dev, plane);
1265 hdisplay = crtc->mode.hdisplay;
1266 htotal = crtc->mode.htotal;
1267 clock = crtc->mode.clock;
1268 pixel_size = crtc->fb->bits_per_pixel / 8;
1269
1270 line_time_us = (htotal * 1000) / clock;
1271 line_count = (latency_ns / line_time_us + 1000) / 1000;
1272 line_size = hdisplay * pixel_size;
1273
1274 /* Use the minimum of the small and large buffer method for primary */
1275 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1276 large = line_count * line_size;
1277
1278 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1279 *display_wm = entries + display->guard_size;
1280
1281 /* calculate the self-refresh watermark for display cursor */
1282 entries = line_count * pixel_size * 64;
1283 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1284 *cursor_wm = entries + cursor->guard_size;
1285
1286 return g4x_check_srwm(dev,
1287 *display_wm, *cursor_wm,
1288 display, cursor);
1289}
1290
1291static bool vlv_compute_drain_latency(struct drm_device *dev,
1292 int plane,
1293 int *plane_prec_mult,
1294 int *plane_dl,
1295 int *cursor_prec_mult,
1296 int *cursor_dl)
1297{
1298 struct drm_crtc *crtc;
1299 int clock, pixel_size;
1300 int entries;
1301
1302 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1303 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1304 return false;
1305
1306 clock = crtc->mode.clock; /* VESA DOT Clock */
1307 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1308
1309 entries = (clock / 1000) * pixel_size;
1310 *plane_prec_mult = (entries > 256) ?
1311 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1312 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1313 pixel_size);
1314
1315 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1316 *cursor_prec_mult = (entries > 256) ?
1317 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1318 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1319
1320 return true;
1321}
1322
1323/*
1324 * Update drain latency registers of memory arbiter
1325 *
1326 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1327 * to be programmed. Each plane has a drain latency multiplier and a drain
1328 * latency value.
1329 */
1330
1331static void vlv_update_drain_latency(struct drm_device *dev)
1332{
1333 struct drm_i915_private *dev_priv = dev->dev_private;
1334 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1335 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1336 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1337 either 16 or 32 */
1338
1339 /* For plane A, Cursor A */
1340 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1341 &cursor_prec_mult, &cursora_dl)) {
1342 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1343 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1344 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1345 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1346
1347 I915_WRITE(VLV_DDL1, cursora_prec |
1348 (cursora_dl << DDL_CURSORA_SHIFT) |
1349 planea_prec | planea_dl);
1350 }
1351
1352 /* For plane B, Cursor B */
1353 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1354 &cursor_prec_mult, &cursorb_dl)) {
1355 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1356 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1357 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1358 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1359
1360 I915_WRITE(VLV_DDL2, cursorb_prec |
1361 (cursorb_dl << DDL_CURSORB_SHIFT) |
1362 planeb_prec | planeb_dl);
1363 }
1364}
1365
1366#define single_plane_enabled(mask) is_power_of_2(mask)
1367
1fa61106 1368static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1369{
1370 static const int sr_latency_ns = 12000;
1371 struct drm_i915_private *dev_priv = dev->dev_private;
1372 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1373 int plane_sr, cursor_sr;
af6c4575 1374 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1375 unsigned int enabled = 0;
1376
1377 vlv_update_drain_latency(dev);
1378
51cea1f4 1379 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1380 &valleyview_wm_info, latency_ns,
1381 &valleyview_cursor_wm_info, latency_ns,
1382 &planea_wm, &cursora_wm))
51cea1f4 1383 enabled |= 1 << PIPE_A;
b445e3b0 1384
51cea1f4 1385 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1386 &valleyview_wm_info, latency_ns,
1387 &valleyview_cursor_wm_info, latency_ns,
1388 &planeb_wm, &cursorb_wm))
51cea1f4 1389 enabled |= 1 << PIPE_B;
b445e3b0 1390
b445e3b0
ED		 1391 if (single_plane_enabled(enabled) &&
1392 g4x_compute_srwm(dev, ffs(enabled) - 1,
1393 sr_latency_ns,
1394 &valleyview_wm_info,
1395 &valleyview_cursor_wm_info,
af6c4575
CW		 1396 &plane_sr, &ignore_cursor_sr) &&
1397 g4x_compute_srwm(dev, ffs(enabled) - 1,
1398 2*sr_latency_ns,
1399 &valleyview_wm_info,
1400 &valleyview_cursor_wm_info,
52bd02d8 1401 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1402 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1403 } else {
b445e3b0
ED		 1404 I915_WRITE(FW_BLC_SELF_VLV,
1405 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1406 plane_sr = cursor_sr = 0;
1407 }
b445e3b0
ED		 1408
1409 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1410 planea_wm, cursora_wm,
1411 planeb_wm, cursorb_wm,
1412 plane_sr, cursor_sr);
1413
1414 I915_WRITE(DSPFW1,
1415 (plane_sr << DSPFW_SR_SHIFT) |
1416 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1417 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1418 planea_wm);
1419 I915_WRITE(DSPFW2,
8c919b28 1420 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1421 (cursora_wm << DSPFW_CURSORA_SHIFT));
1422 I915_WRITE(DSPFW3,
8c919b28
CW		 1423 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1424 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1425}
1426
1fa61106 1427static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1428{
1429 static const int sr_latency_ns = 12000;
1430 struct drm_i915_private *dev_priv = dev->dev_private;
1431 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1432 int plane_sr, cursor_sr;
1433 unsigned int enabled = 0;
1434
51cea1f4 1435 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1436 &g4x_wm_info, latency_ns,
1437 &g4x_cursor_wm_info, latency_ns,
1438 &planea_wm, &cursora_wm))
51cea1f4 1439 enabled |= 1 << PIPE_A;
b445e3b0 1440
51cea1f4 1441 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1442 &g4x_wm_info, latency_ns,
1443 &g4x_cursor_wm_info, latency_ns,
1444 &planeb_wm, &cursorb_wm))
51cea1f4 1445 enabled |= 1 << PIPE_B;
b445e3b0 1446
b445e3b0
ED		 1447 if (single_plane_enabled(enabled) &&
1448 g4x_compute_srwm(dev, ffs(enabled) - 1,
1449 sr_latency_ns,
1450 &g4x_wm_info,
1451 &g4x_cursor_wm_info,
52bd02d8 1452 &plane_sr, &cursor_sr)) {
b445e3b0 1453 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1454 } else {
b445e3b0
ED		 1455 I915_WRITE(FW_BLC_SELF,
1456 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1457 plane_sr = cursor_sr = 0;
1458 }
b445e3b0
ED		 1459
1460 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1461 planea_wm, cursora_wm,
1462 planeb_wm, cursorb_wm,
1463 plane_sr, cursor_sr);
1464
1465 I915_WRITE(DSPFW1,
1466 (plane_sr << DSPFW_SR_SHIFT) |
1467 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1468 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1469 planea_wm);
1470 I915_WRITE(DSPFW2,
8c919b28 1471 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1472 (cursora_wm << DSPFW_CURSORA_SHIFT));
1473 /* HPLL off in SR has some issues on G4x... disable it */
1474 I915_WRITE(DSPFW3,
8c919b28 1475 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1476 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1477}
1478
1fa61106 1479static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1480{
1481 struct drm_i915_private *dev_priv = dev->dev_private;
1482 struct drm_crtc *crtc;
1483 int srwm = 1;
1484 int cursor_sr = 16;
1485
1486 /* Calc sr entries for one plane configs */
1487 crtc = single_enabled_crtc(dev);
1488 if (crtc) {
1489 /* self-refresh has much higher latency */
1490 static const int sr_latency_ns = 12000;
1491 int clock = crtc->mode.clock;
1492 int htotal = crtc->mode.htotal;
1493 int hdisplay = crtc->mode.hdisplay;
1494 int pixel_size = crtc->fb->bits_per_pixel / 8;
1495 unsigned long line_time_us;
1496 int entries;
1497
1498 line_time_us = ((htotal * 1000) / clock);
1499
1500 /* Use ns/us then divide to preserve precision */
1501 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1502 pixel_size * hdisplay;
1503 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1504 srwm = I965_FIFO_SIZE - entries;
1505 if (srwm < 0)
1506 srwm = 1;
1507 srwm &= 0x1ff;
1508 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1509 entries, srwm);
1510
1511 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1512 pixel_size * 64;
1513 entries = DIV_ROUND_UP(entries,
1514 i965_cursor_wm_info.cacheline_size);
1515 cursor_sr = i965_cursor_wm_info.fifo_size -
1516 (entries + i965_cursor_wm_info.guard_size);
1517
1518 if (cursor_sr > i965_cursor_wm_info.max_wm)
1519 cursor_sr = i965_cursor_wm_info.max_wm;
1520
1521 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1522 "cursor %d\n", srwm, cursor_sr);
1523
1524 if (IS_CRESTLINE(dev))
1525 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1526 } else {
1527 /* Turn off self refresh if both pipes are enabled */
1528 if (IS_CRESTLINE(dev))
1529 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1530 & ~FW_BLC_SELF_EN);
1531 }
1532
1533 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1534 srwm);
1535
1536 /* 965 has limitations... */
1537 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1538 (8 << 16) | (8 << 8) | (8 << 0));
1539 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1540 /* update cursor SR watermark */
1541 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1542}
1543
1fa61106 1544static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1545{
1546 struct drm_i915_private *dev_priv = dev->dev_private;
1547 const struct intel_watermark_params *wm_info;
1548 uint32_t fwater_lo;
1549 uint32_t fwater_hi;
1550 int cwm, srwm = 1;
1551 int fifo_size;
1552 int planea_wm, planeb_wm;
1553 struct drm_crtc *crtc, *enabled = NULL;
1554
1555 if (IS_I945GM(dev))
1556 wm_info = &i945_wm_info;
1557 else if (!IS_GEN2(dev))
1558 wm_info = &i915_wm_info;
1559 else
1560 wm_info = &i855_wm_info;
1561
1562 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1563 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1564 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1565 int cpp = crtc->fb->bits_per_pixel / 8;
1566 if (IS_GEN2(dev))
1567 cpp = 4;
1568
b445e3b0 1569 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
b445e3b0
ED		 1571 latency_ns);
1572 enabled = crtc;
1573 } else
1574 planea_wm = fifo_size - wm_info->guard_size;
1575
1576 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1577 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1578 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1579 int cpp = crtc->fb->bits_per_pixel / 8;
1580 if (IS_GEN2(dev))
1581 cpp = 4;
1582
b445e3b0 1583 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1584 wm_info, fifo_size, cpp,
b445e3b0
ED		 1585 latency_ns);
1586 if (enabled == NULL)
1587 enabled = crtc;
1588 else
1589 enabled = NULL;
1590 } else
1591 planeb_wm = fifo_size - wm_info->guard_size;
1592
1593 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1594
1595 /*
1596 * Overlay gets an aggressive default since video jitter is bad.
1597 */
1598 cwm = 2;
1599
1600 /* Play safe and disable self-refresh before adjusting watermarks. */
1601 if (IS_I945G(dev) || IS_I945GM(dev))
1602 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1603 else if (IS_I915GM(dev))
1604 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1605
1606 /* Calc sr entries for one plane configs */
1607 if (HAS_FW_BLC(dev) && enabled) {
1608 /* self-refresh has much higher latency */
1609 static const int sr_latency_ns = 6000;
1610 int clock = enabled->mode.clock;
1611 int htotal = enabled->mode.htotal;
1612 int hdisplay = enabled->mode.hdisplay;
1613 int pixel_size = enabled->fb->bits_per_pixel / 8;
1614 unsigned long line_time_us;
1615 int entries;
1616
1617 line_time_us = (htotal * 1000) / clock;
1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1621 pixel_size * hdisplay;
1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
1628 if (IS_I945G(dev) || IS_I945GM(dev))
1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1631 else if (IS_I915GM(dev))
1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
1648 if (HAS_FW_BLC(dev)) {
1649 if (enabled) {
1650 if (IS_I945G(dev) || IS_I945GM(dev))
1651 I915_WRITE(FW_BLC_SELF,
1652 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1653 else if (IS_I915GM(dev))
1654 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1655 DRM_DEBUG_KMS("memory self refresh enabled\n");
1656 } else
1657 DRM_DEBUG_KMS("memory self refresh disabled\n");
1658 }
1659}
1660
1fa61106 1661static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1662{
1663 struct drm_i915_private *dev_priv = dev->dev_private;
1664 struct drm_crtc *crtc;
1665 uint32_t fwater_lo;
1666 int planea_wm;
1667
1668 crtc = single_enabled_crtc(dev);
1669 if (crtc == NULL)
1670 return;
1671
1672 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1673 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1674 4, latency_ns);
b445e3b0
ED		 1675 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1676 fwater_lo |= (3<<8) | planea_wm;
1677
1678 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1679
1680 I915_WRITE(FW_BLC, fwater_lo);
1681}
1682
b445e3b0
ED		 1683/*
1684 * Check the wm result.
1685 *
1686 * If any calculated watermark values is larger than the maximum value that
1687 * can be programmed into the associated watermark register, that watermark
1688 * must be disabled.
1689 */
1690static bool ironlake_check_srwm(struct drm_device *dev, int level,
1691 int fbc_wm, int display_wm, int cursor_wm,
1692 const struct intel_watermark_params *display,
1693 const struct intel_watermark_params *cursor)
1694{
1695 struct drm_i915_private *dev_priv = dev->dev_private;
1696
1697 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1698 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1699
1700 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1701 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1702 fbc_wm, SNB_FBC_MAX_SRWM, level);
1703
1704 /* fbc has it's own way to disable FBC WM */
1705 I915_WRITE(DISP_ARB_CTL,
1706 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1707 return false;
615aaa5f
VS		 1708 } else if (INTEL_INFO(dev)->gen >= 6) {
1709 /* enable FBC WM (except on ILK, where it must remain off) */
1710 I915_WRITE(DISP_ARB_CTL,
1711 I915_READ(DISP_ARB_CTL) & ~DISP_FBC_WM_DIS);
b445e3b0
ED		 1712 }
1713
1714 if (display_wm > display->max_wm) {
1715 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1716 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1717 return false;
1718 }
1719
1720 if (cursor_wm > cursor->max_wm) {
1721 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1722 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1723 return false;
1724 }
1725
1726 if (!(fbc_wm || display_wm || cursor_wm)) {
1727 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1728 return false;
1729 }
1730
1731 return true;
1732}
1733
1734/*
1735 * Compute watermark values of WM[1-3],
1736 */
1737static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1738 int latency_ns,
1739 const struct intel_watermark_params *display,
1740 const struct intel_watermark_params *cursor,
1741 int *fbc_wm, int *display_wm, int *cursor_wm)
1742{
1743 struct drm_crtc *crtc;
1744 unsigned long line_time_us;
1745 int hdisplay, htotal, pixel_size, clock;
1746 int line_count, line_size;
1747 int small, large;
1748 int entries;
1749
1750 if (!latency_ns) {
1751 *fbc_wm = *display_wm = *cursor_wm = 0;
1752 return false;
1753 }
1754
1755 crtc = intel_get_crtc_for_plane(dev, plane);
1756 hdisplay = crtc->mode.hdisplay;
1757 htotal = crtc->mode.htotal;
1758 clock = crtc->mode.clock;
1759 pixel_size = crtc->fb->bits_per_pixel / 8;
1760
1761 line_time_us = (htotal * 1000) / clock;
1762 line_count = (latency_ns / line_time_us + 1000) / 1000;
1763 line_size = hdisplay * pixel_size;
1764
1765 /* Use the minimum of the small and large buffer method for primary */
1766 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1767 large = line_count * line_size;
1768
1769 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1770 *display_wm = entries + display->guard_size;
1771
1772 /*
1773 * Spec says:
1774 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1775 */
1776 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1777
1778 /* calculate the self-refresh watermark for display cursor */
1779 entries = line_count * pixel_size * 64;
1780 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1781 *cursor_wm = entries + cursor->guard_size;
1782
1783 return ironlake_check_srwm(dev, level,
1784 *fbc_wm, *display_wm, *cursor_wm,
1785 display, cursor);
1786}
1787
1fa61106 1788static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1789{
1790 struct drm_i915_private *dev_priv = dev->dev_private;
1791 int fbc_wm, plane_wm, cursor_wm;
1792 unsigned int enabled;
1793
1794 enabled = 0;
51cea1f4 1795 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0 1796 &ironlake_display_wm_info,
b0aea5dc 1797 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1798 &ironlake_cursor_wm_info,
b0aea5dc 1799 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1800 &plane_wm, &cursor_wm)) {
1801 I915_WRITE(WM0_PIPEA_ILK,
1802 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1803 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1804 " plane %d, " "cursor: %d\n",
1805 plane_wm, cursor_wm);
51cea1f4 1806 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1807 }
1808
51cea1f4 1809 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0 1810 &ironlake_display_wm_info,
b0aea5dc 1811 dev_priv->wm.pri_latency[0] * 100,
b445e3b0 1812 &ironlake_cursor_wm_info,
b0aea5dc 1813 dev_priv->wm.cur_latency[0] * 100,
b445e3b0
ED		 1814 &plane_wm, &cursor_wm)) {
1815 I915_WRITE(WM0_PIPEB_ILK,
1816 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1817 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1818 " plane %d, cursor: %d\n",
1819 plane_wm, cursor_wm);
51cea1f4 1820 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1821 }
1822
1823 /*
1824 * Calculate and update the self-refresh watermark only when one
1825 * display plane is used.
1826 */
1827 I915_WRITE(WM3_LP_ILK, 0);
1828 I915_WRITE(WM2_LP_ILK, 0);
1829 I915_WRITE(WM1_LP_ILK, 0);
1830
1831 if (!single_plane_enabled(enabled))
1832 return;
1833 enabled = ffs(enabled) - 1;
1834
1835 /* WM1 */
1836 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1837 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 1838 &ironlake_display_srwm_info,
1839 &ironlake_cursor_srwm_info,
1840 &fbc_wm, &plane_wm, &cursor_wm))
1841 return;
1842
1843 I915_WRITE(WM1_LP_ILK,
1844 WM1_LP_SR_EN |
b0aea5dc 1845 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1846 (fbc_wm << WM1_LP_FBC_SHIFT) |
1847 (plane_wm << WM1_LP_SR_SHIFT) |
1848 cursor_wm);
1849
1850 /* WM2 */
1851 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1852 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 1853 &ironlake_display_srwm_info,
1854 &ironlake_cursor_srwm_info,
1855 &fbc_wm, &plane_wm, &cursor_wm))
1856 return;
1857
1858 I915_WRITE(WM2_LP_ILK,
1859 WM2_LP_EN |
b0aea5dc 1860 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 1861 (fbc_wm << WM1_LP_FBC_SHIFT) |
1862 (plane_wm << WM1_LP_SR_SHIFT) |
1863 cursor_wm);
1864
1865 /*
1866 * WM3 is unsupported on ILK, probably because we don't have latency
1867 * data for that power state
1868 */
1869}
1870
1fa61106 1871static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1872{
1873 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1874 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 1875 u32 val;
1876 int fbc_wm, plane_wm, cursor_wm;
1877 unsigned int enabled;
1878
1879 enabled = 0;
51cea1f4 1880 if (g4x_compute_wm0(dev, PIPE_A,
b445e3b0
ED		 1881 &sandybridge_display_wm_info, latency,
1882 &sandybridge_cursor_wm_info, latency,
1883 &plane_wm, &cursor_wm)) {
1884 val = I915_READ(WM0_PIPEA_ILK);
1885 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1886 I915_WRITE(WM0_PIPEA_ILK, val |
1887 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1888 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1889 " plane %d, " "cursor: %d\n",
1890 plane_wm, cursor_wm);
51cea1f4 1891 enabled |= 1 << PIPE_A;
b445e3b0
ED		 1892 }
1893
51cea1f4 1894 if (g4x_compute_wm0(dev, PIPE_B,
b445e3b0
ED		 1895 &sandybridge_display_wm_info, latency,
1896 &sandybridge_cursor_wm_info, latency,
1897 &plane_wm, &cursor_wm)) {
1898 val = I915_READ(WM0_PIPEB_ILK);
1899 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1900 I915_WRITE(WM0_PIPEB_ILK, val |
1901 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1902 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1903 " plane %d, cursor: %d\n",
1904 plane_wm, cursor_wm);
51cea1f4 1905 enabled |= 1 << PIPE_B;
b445e3b0
ED		 1906 }
1907
c43d0188
CW		 1908 /*
1909 * Calculate and update the self-refresh watermark only when one
1910 * display plane is used.
1911 *
1912 * SNB support 3 levels of watermark.
1913 *
1914 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1915 * and disabled in the descending order
1916 *
1917 */
1918 I915_WRITE(WM3_LP_ILK, 0);
1919 I915_WRITE(WM2_LP_ILK, 0);
1920 I915_WRITE(WM1_LP_ILK, 0);
1921
1922 if (!single_plane_enabled(enabled) ||
1923 dev_priv->sprite_scaling_enabled)
1924 return;
1925 enabled = ffs(enabled) - 1;
1926
1927 /* WM1 */
1928 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 1929 dev_priv->wm.pri_latency[1] * 500,
c43d0188
CW		 1930 &sandybridge_display_srwm_info,
1931 &sandybridge_cursor_srwm_info,
1932 &fbc_wm, &plane_wm, &cursor_wm))
1933 return;
1934
1935 I915_WRITE(WM1_LP_ILK,
1936 WM1_LP_SR_EN |
b0aea5dc 1937 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1938 (fbc_wm << WM1_LP_FBC_SHIFT) |
1939 (plane_wm << WM1_LP_SR_SHIFT) |
1940 cursor_wm);
1941
1942 /* WM2 */
1943 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 1944 dev_priv->wm.pri_latency[2] * 500,
c43d0188
CW		 1945 &sandybridge_display_srwm_info,
1946 &sandybridge_cursor_srwm_info,
1947 &fbc_wm, &plane_wm, &cursor_wm))
1948 return;
1949
1950 I915_WRITE(WM2_LP_ILK,
1951 WM2_LP_EN |
b0aea5dc 1952 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1953 (fbc_wm << WM1_LP_FBC_SHIFT) |
1954 (plane_wm << WM1_LP_SR_SHIFT) |
1955 cursor_wm);
1956
1957 /* WM3 */
1958 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 1959 dev_priv->wm.pri_latency[3] * 500,
c43d0188
CW		 1960 &sandybridge_display_srwm_info,
1961 &sandybridge_cursor_srwm_info,
1962 &fbc_wm, &plane_wm, &cursor_wm))
1963 return;
1964
1965 I915_WRITE(WM3_LP_ILK,
1966 WM3_LP_EN |
b0aea5dc 1967 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
c43d0188
CW		 1968 (fbc_wm << WM1_LP_FBC_SHIFT) |
1969 (plane_wm << WM1_LP_SR_SHIFT) |
1970 cursor_wm);
1971}
1972
1973static void ivybridge_update_wm(struct drm_device *dev)
1974{
1975 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 1976 int latency = dev_priv->wm.pri_latency[0] * 100; /* In unit 0.1us */
c43d0188
CW		 1977 u32 val;
1978 int fbc_wm, plane_wm, cursor_wm;
1979 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1980 unsigned int enabled;
1981
1982 enabled = 0;
51cea1f4 1983 if (g4x_compute_wm0(dev, PIPE_A,
c43d0188
CW		 1984 &sandybridge_display_wm_info, latency,
1985 &sandybridge_cursor_wm_info, latency,
1986 &plane_wm, &cursor_wm)) {
1987 val = I915_READ(WM0_PIPEA_ILK);
1988 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1989 I915_WRITE(WM0_PIPEA_ILK, val |
1990 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1991 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1992 " plane %d, " "cursor: %d\n",
1993 plane_wm, cursor_wm);
51cea1f4 1994 enabled |= 1 << PIPE_A;
c43d0188
CW		 1995 }
1996
51cea1f4 1997 if (g4x_compute_wm0(dev, PIPE_B,
c43d0188
CW		 1998 &sandybridge_display_wm_info, latency,
1999 &sandybridge_cursor_wm_info, latency,
2000 &plane_wm, &cursor_wm)) {
2001 val = I915_READ(WM0_PIPEB_ILK);
2002 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2003 I915_WRITE(WM0_PIPEB_ILK, val |
2004 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2005 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
2006 " plane %d, cursor: %d\n",
2007 plane_wm, cursor_wm);
51cea1f4 2008 enabled |= 1 << PIPE_B;
c43d0188
CW		 2009 }
2010
51cea1f4 2011 if (g4x_compute_wm0(dev, PIPE_C,
b445e3b0
ED		 2012 &sandybridge_display_wm_info, latency,
2013 &sandybridge_cursor_wm_info, latency,
2014 &plane_wm, &cursor_wm)) {
2015 val = I915_READ(WM0_PIPEC_IVB);
2016 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
2017 I915_WRITE(WM0_PIPEC_IVB, val |
2018 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
2019 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
2020 " plane %d, cursor: %d\n",
2021 plane_wm, cursor_wm);
51cea1f4 2022 enabled |= 1 << PIPE_C;
b445e3b0
ED		 2023 }
2024
2025 /*
2026 * Calculate and update the self-refresh watermark only when one
2027 * display plane is used.
2028 *
2029 * SNB support 3 levels of watermark.
2030 *
2031 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
2032 * and disabled in the descending order
2033 *
2034 */
2035 I915_WRITE(WM3_LP_ILK, 0);
2036 I915_WRITE(WM2_LP_ILK, 0);
2037 I915_WRITE(WM1_LP_ILK, 0);
2038
2039 if (!single_plane_enabled(enabled) ||
2040 dev_priv->sprite_scaling_enabled)
2041 return;
2042 enabled = ffs(enabled) - 1;
2043
2044 /* WM1 */
2045 if (!ironlake_compute_srwm(dev, 1, enabled,
b0aea5dc 2046 dev_priv->wm.pri_latency[1] * 500,
b445e3b0
ED		 2047 &sandybridge_display_srwm_info,
2048 &sandybridge_cursor_srwm_info,
2049 &fbc_wm, &plane_wm, &cursor_wm))
2050 return;
2051
2052 I915_WRITE(WM1_LP_ILK,
2053 WM1_LP_SR_EN |
b0aea5dc 2054 (dev_priv->wm.pri_latency[1] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2055 (fbc_wm << WM1_LP_FBC_SHIFT) |
2056 (plane_wm << WM1_LP_SR_SHIFT) |
2057 cursor_wm);
2058
2059 /* WM2 */
2060 if (!ironlake_compute_srwm(dev, 2, enabled,
b0aea5dc 2061 dev_priv->wm.pri_latency[2] * 500,
b445e3b0
ED		 2062 &sandybridge_display_srwm_info,
2063 &sandybridge_cursor_srwm_info,
2064 &fbc_wm, &plane_wm, &cursor_wm))
2065 return;
2066
2067 I915_WRITE(WM2_LP_ILK,
2068 WM2_LP_EN |
b0aea5dc 2069 (dev_priv->wm.pri_latency[2] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2070 (fbc_wm << WM1_LP_FBC_SHIFT) |
2071 (plane_wm << WM1_LP_SR_SHIFT) |
2072 cursor_wm);
2073
c43d0188 2074 /* WM3, note we have to correct the cursor latency */
b445e3b0 2075 if (!ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2076 dev_priv->wm.pri_latency[3] * 500,
b445e3b0
ED		 2077 &sandybridge_display_srwm_info,
2078 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2079 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2080 !ironlake_compute_srwm(dev, 3, enabled,
b0aea5dc 2081 dev_priv->wm.cur_latency[3] * 500,
c43d0188
CW		 2082 &sandybridge_display_srwm_info,
2083 &sandybridge_cursor_srwm_info,
2084 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2085 return;
2086
2087 I915_WRITE(WM3_LP_ILK,
2088 WM3_LP_EN |
b0aea5dc 2089 (dev_priv->wm.pri_latency[3] << WM1_LP_LATENCY_SHIFT) |
b445e3b0
ED		 2090 (fbc_wm << WM1_LP_FBC_SHIFT) |
2091 (plane_wm << WM1_LP_SR_SHIFT) |
2092 cursor_wm);
2093}
2094
3658729a
VS		 2095static uint32_t ilk_pipe_pixel_rate(struct drm_device *dev,
2096 struct drm_crtc *crtc)
801bcfff
PZ		 2097{
2098 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2099 uint32_t pixel_rate, pfit_size;
2100
ff9a6750 2101 pixel_rate = intel_crtc->config.adjusted_mode.clock;
801bcfff
PZ		 2102
2103 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
2104 * adjust the pixel_rate here. */
2105
2106 pfit_size = intel_crtc->config.pch_pfit.size;
2107 if (pfit_size) {
2108 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
2109
2110 pipe_w = intel_crtc->config.requested_mode.hdisplay;
2111 pipe_h = intel_crtc->config.requested_mode.vdisplay;
2112 pfit_w = (pfit_size >> 16) & 0xFFFF;
2113 pfit_h = pfit_size & 0xFFFF;
2114 if (pipe_w < pfit_w)
2115 pipe_w = pfit_w;
2116 if (pipe_h < pfit_h)
2117 pipe_h = pfit_h;
2118
2119 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
2120 pfit_w * pfit_h);
2121 }
2122
2123 return pixel_rate;
2124}
2125
37126462 2126/* latency must be in 0.1us units. */
23297044 2127static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t bytes_per_pixel,
801bcfff
PZ		 2128 uint32_t latency)
2129{
2130 uint64_t ret;
2131
3312ba65
VS		 2132 if (WARN(latency == 0, "Latency value missing\n"))
2133 return UINT_MAX;
2134
801bcfff
PZ		 2135 ret = (uint64_t) pixel_rate * bytes_per_pixel * latency;
2136 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
2137
2138 return ret;
2139}
2140
37126462 2141/* latency must be in 0.1us units. */
23297044 2142static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
801bcfff
PZ		 2143 uint32_t horiz_pixels, uint8_t bytes_per_pixel,
2144 uint32_t latency)
2145{
2146 uint32_t ret;
2147
3312ba65
VS		 2148 if (WARN(latency == 0, "Latency value missing\n"))
2149 return UINT_MAX;
2150
801bcfff
PZ		 2151 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
2152 ret = (ret + 1) * horiz_pixels * bytes_per_pixel;
2153 ret = DIV_ROUND_UP(ret, 64) + 2;
2154 return ret;
2155}
2156
23297044 2157static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
cca32e9a
PZ		 2158 uint8_t bytes_per_pixel)
2159{
2160 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * bytes_per_pixel) + 2;
2161}
2162
801bcfff
PZ		 2163struct hsw_pipe_wm_parameters {
2164 bool active;
2165 bool sprite_enabled;
2166 uint8_t pri_bytes_per_pixel;
2167 uint8_t spr_bytes_per_pixel;
2168 uint8_t cur_bytes_per_pixel;
2169 uint32_t pri_horiz_pixels;
2170 uint32_t spr_horiz_pixels;
2171 uint32_t cur_horiz_pixels;
2172 uint32_t pipe_htotal;
2173 uint32_t pixel_rate;
2174};
2175
cca32e9a
PZ		 2176struct hsw_wm_maximums {
2177 uint16_t pri;
2178 uint16_t spr;
2179 uint16_t cur;
2180 uint16_t fbc;
2181};
2182
2183struct hsw_lp_wm_result {
2184 bool enable;
2185 bool fbc_enable;
2186 uint32_t pri_val;
2187 uint32_t spr_val;
2188 uint32_t cur_val;
2189 uint32_t fbc_val;
2190};
2191
801bcfff
PZ		 2192struct hsw_wm_values {
2193 uint32_t wm_pipe[3];
2194 uint32_t wm_lp[3];
2195 uint32_t wm_lp_spr[3];
2196 uint32_t wm_linetime[3];
cca32e9a 2197 bool enable_fbc_wm;
801bcfff
PZ		 2198};
2199
2200enum hsw_data_buf_partitioning {
2201 HSW_DATA_BUF_PART_1_2,
2202 HSW_DATA_BUF_PART_5_6,
2203};
2204
37126462
VS		 2205/*
2206 * For both WM_PIPE and WM_LP.
2207 * mem_value must be in 0.1us units.
2208 */
23297044 2209static uint32_t ilk_compute_pri_wm(struct hsw_pipe_wm_parameters *params,
cca32e9a
PZ		 2210 uint32_t mem_value,
2211 bool is_lp)
801bcfff 2212{
cca32e9a
PZ		 2213 uint32_t method1, method2;
2214
801bcfff
PZ		 2215 /* TODO: for now, assume the primary plane is always enabled. */
2216 if (!params->active)
2217 return 0;
2218
23297044 2219 method1 = ilk_wm_method1(params->pixel_rate,
cca32e9a
PZ		 2220 params->pri_bytes_per_pixel,
2221 mem_value);
2222
2223 if (!is_lp)
2224 return method1;
2225
23297044 2226 method2 = ilk_wm_method2(params->pixel_rate,
cca32e9a
PZ		 2227 params->pipe_htotal,
2228 params->pri_horiz_pixels,
2229 params->pri_bytes_per_pixel,
2230 mem_value);
2231
2232 return min(method1, method2);
801bcfff
PZ		 2233}
2234
37126462
VS		 2235/*
2236 * For both WM_PIPE and WM_LP.
2237 * mem_value must be in 0.1us units.
2238 */
23297044 2239static uint32_t ilk_compute_spr_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2240 uint32_t mem_value)
2241{
2242 uint32_t method1, method2;
2243
2244 if (!params->active || !params->sprite_enabled)
2245 return 0;
2246
23297044 2247 method1 = ilk_wm_method1(params->pixel_rate,
801bcfff
PZ		 2248 params->spr_bytes_per_pixel,
2249 mem_value);
23297044 2250 method2 = ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2251 params->pipe_htotal,
2252 params->spr_horiz_pixels,
2253 params->spr_bytes_per_pixel,
2254 mem_value);
2255 return min(method1, method2);
2256}
2257
37126462
VS		 2258/*
2259 * For both WM_PIPE and WM_LP.
2260 * mem_value must be in 0.1us units.
2261 */
23297044 2262static uint32_t ilk_compute_cur_wm(struct hsw_pipe_wm_parameters *params,
801bcfff
PZ		 2263 uint32_t mem_value)
2264{
2265 if (!params->active)
2266 return 0;
2267
23297044 2268 return ilk_wm_method2(params->pixel_rate,
801bcfff
PZ		 2269 params->pipe_htotal,
2270 params->cur_horiz_pixels,
2271 params->cur_bytes_per_pixel,
2272 mem_value);
2273}
2274
cca32e9a 2275/* Only for WM_LP. */
23297044 2276static uint32_t ilk_compute_fbc_wm(struct hsw_pipe_wm_parameters *params,
1fda9882 2277 uint32_t pri_val)
cca32e9a
PZ		 2278{
2279 if (!params->active)
2280 return 0;
2281
23297044 2282 return ilk_wm_fbc(pri_val,
cca32e9a
PZ		 2283 params->pri_horiz_pixels,
2284 params->pri_bytes_per_pixel);
2285}
2286
5b77da33
VS		 2287static bool hsw_compute_lp_wm(struct drm_i915_private *dev_priv,
2288 int level, struct hsw_wm_maximums *max,
cca32e9a
PZ		 2289 struct hsw_pipe_wm_parameters *params,
2290 struct hsw_lp_wm_result *result)
2291{
2292 enum pipe pipe;
2293 uint32_t pri_val[3], spr_val[3], cur_val[3], fbc_val[3];
2294
2295 for (pipe = PIPE_A; pipe <= PIPE_C; pipe++) {
2296 struct hsw_pipe_wm_parameters *p = &params[pipe];
5b77da33
VS		 2297 /* WM1+ latency values stored in 0.5us units */
2298 uint16_t pri_latency = dev_priv->wm.pri_latency[level] * 5;
2299 uint16_t spr_latency = dev_priv->wm.spr_latency[level] * 5;
2300 uint16_t cur_latency = dev_priv->wm.cur_latency[level] * 5;
2301
2302 pri_val[pipe] = ilk_compute_pri_wm(p, pri_latency, true);
2303 spr_val[pipe] = ilk_compute_spr_wm(p, spr_latency);
2304 cur_val[pipe] = ilk_compute_cur_wm(p, cur_latency);
1fda9882 2305 fbc_val[pipe] = ilk_compute_fbc_wm(p, pri_val[pipe]);
cca32e9a
PZ		 2306 }
2307
2308 result->pri_val = max3(pri_val[0], pri_val[1], pri_val[2]);
2309 result->spr_val = max3(spr_val[0], spr_val[1], spr_val[2]);
2310 result->cur_val = max3(cur_val[0], cur_val[1], cur_val[2]);
2311 result->fbc_val = max3(fbc_val[0], fbc_val[1], fbc_val[2]);
2312
2313 if (result->fbc_val > max->fbc) {
2314 result->fbc_enable = false;
2315 result->fbc_val = 0;
2316 } else {
2317 result->fbc_enable = true;
2318 }
2319
2320 result->enable = result->pri_val <= max->pri &&
2321 result->spr_val <= max->spr &&
2322 result->cur_val <= max->cur;
2323 return result->enable;
2324}
2325
801bcfff 2326static uint32_t hsw_compute_wm_pipe(struct drm_i915_private *dev_priv,
5b77da33 2327 enum pipe pipe,
801bcfff
PZ		 2328 struct hsw_pipe_wm_parameters *params)
2329{
2330 uint32_t pri_val, cur_val, spr_val;
5b77da33
VS		 2331 /* WM0 latency values stored in 0.1us units */
2332 uint16_t pri_latency = dev_priv->wm.pri_latency[0];
2333 uint16_t spr_latency = dev_priv->wm.spr_latency[0];
2334 uint16_t cur_latency = dev_priv->wm.cur_latency[0];
801bcfff 2335
5b77da33
VS		 2336 pri_val = ilk_compute_pri_wm(params, pri_latency, false);
2337 spr_val = ilk_compute_spr_wm(params, spr_latency);
2338 cur_val = ilk_compute_cur_wm(params, cur_latency);
801bcfff
PZ		 2339
2340 WARN(pri_val > 127,
2341 "Primary WM error, mode not supported for pipe %c\n",
2342 pipe_name(pipe));
2343 WARN(spr_val > 127,
2344 "Sprite WM error, mode not supported for pipe %c\n",
2345 pipe_name(pipe));
2346 WARN(cur_val > 63,
2347 "Cursor WM error, mode not supported for pipe %c\n",
2348 pipe_name(pipe));
2349
2350 return (pri_val << WM0_PIPE_PLANE_SHIFT) |
2351 (spr_val << WM0_PIPE_SPRITE_SHIFT) |
2352 cur_val;
2353}
2354
2355static uint32_t
2356hsw_compute_linetime_wm(struct drm_device *dev, struct drm_crtc *crtc)
1f8eeabf
ED		 2357{
2358 struct drm_i915_private *dev_priv = dev->dev_private;
1011d8c4 2359 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1011d8c4 2360 struct drm_display_mode *mode = &intel_crtc->config.adjusted_mode;
85a02deb 2361 u32 linetime, ips_linetime;
1f8eeabf 2362
801bcfff
PZ		 2363 if (!intel_crtc_active(crtc))
2364 return 0;
1011d8c4 2365
1f8eeabf
ED		 2366 /* The WM are computed with base on how long it takes to fill a single
2367 * row at the given clock rate, multiplied by 8.
2368 * */
85a02deb
PZ		 2369 linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8, mode->clock);
2370 ips_linetime = DIV_ROUND_CLOSEST(mode->htotal * 1000 * 8,
2371 intel_ddi_get_cdclk_freq(dev_priv));
1f8eeabf 2372
801bcfff
PZ		 2373 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2374 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2375}
2376
12b134df
VS		 2377static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[5])
2378{
2379 struct drm_i915_private *dev_priv = dev->dev_private;
2380
2381 if (IS_HASWELL(dev)) {
2382 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2383
2384 wm[0] = (sskpd >> 56) & 0xFF;
2385 if (wm[0] == 0)
2386 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2387 wm[1] = (sskpd >> 4) & 0xFF;
2388 wm[2] = (sskpd >> 12) & 0xFF;
2389 wm[3] = (sskpd >> 20) & 0x1FF;
2390 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2391 } else if (INTEL_INFO(dev)->gen >= 6) {
2392 uint32_t sskpd = I915_READ(MCH_SSKPD);
2393
2394 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2395 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2396 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2397 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2398 } else if (INTEL_INFO(dev)->gen >= 5) {
2399 uint32_t mltr = I915_READ(MLTR_ILK);
2400
2401 /* ILK primary LP0 latency is 700 ns */
2402 wm[0] = 7;
2403 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2404 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2405 }
2406}
2407
53615a5e
VS		 2408static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2409{
2410 /* ILK sprite LP0 latency is 1300 ns */
2411 if (INTEL_INFO(dev)->gen == 5)
2412 wm[0] = 13;
2413}
2414
2415static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2416{
2417 /* ILK cursor LP0 latency is 1300 ns */
2418 if (INTEL_INFO(dev)->gen == 5)
2419 wm[0] = 13;
2420
2421 /* WaDoubleCursorLP3Latency:ivb */
2422 if (IS_IVYBRIDGE(dev))
2423 wm[3] *= 2;
2424}
2425
26ec971e
VS		 2426static void intel_print_wm_latency(struct drm_device *dev,
2427 const char *name,
2428 const uint16_t wm[5])
2429{
2430 int level, max_level;
2431
2432 /* how many WM levels are we expecting */
2433 if (IS_HASWELL(dev))
2434 max_level = 4;
2435 else if (INTEL_INFO(dev)->gen >= 6)
2436 max_level = 3;
2437 else
2438 max_level = 2;
2439
2440 for (level = 0; level <= max_level; level++) {
2441 unsigned int latency = wm[level];
2442
2443 if (latency == 0) {
2444 DRM_ERROR("%s WM%d latency not provided\n",
2445 name, level);
2446 continue;
2447 }
2448
2449 /* WM1+ latency values in 0.5us units */
2450 if (level > 0)
2451 latency *= 5;
2452
2453 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2454 name, level, wm[level],
2455 latency / 10, latency % 10);
2456 }
2457}
2458
53615a5e
VS		 2459static void intel_setup_wm_latency(struct drm_device *dev)
2460{
2461 struct drm_i915_private *dev_priv = dev->dev_private;
2462
2463 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2464
2465 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2466 sizeof(dev_priv->wm.pri_latency));
2467 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2468 sizeof(dev_priv->wm.pri_latency));
2469
2470 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2471 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2472
2473 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2474 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2475 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
53615a5e
VS		 2476}
2477
801bcfff
PZ		 2478static void hsw_compute_wm_parameters(struct drm_device *dev,
2479 struct hsw_pipe_wm_parameters *params,
861f3389
PZ		 2480 struct hsw_wm_maximums *lp_max_1_2,
2481 struct hsw_wm_maximums *lp_max_5_6)
1011d8c4 2482{
1011d8c4 2483 struct drm_crtc *crtc;
801bcfff 2484 struct drm_plane *plane;
1011d8c4 2485 enum pipe pipe;
cca32e9a 2486 int pipes_active = 0, sprites_enabled = 0;
1011d8c4 2487
801bcfff
PZ		 2488 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
2489 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
2490 struct hsw_pipe_wm_parameters *p;
2491
2492 pipe = intel_crtc->pipe;
2493 p = &params[pipe];
2494
2495 p->active = intel_crtc_active(crtc);
2496 if (!p->active)
2497 continue;
2498
cca32e9a
PZ		 2499 pipes_active++;
2500
801bcfff 2501 p->pipe_htotal = intel_crtc->config.adjusted_mode.htotal;
3658729a 2502 p->pixel_rate = ilk_pipe_pixel_rate(dev, crtc);
801bcfff
PZ		 2503 p->pri_bytes_per_pixel = crtc->fb->bits_per_pixel / 8;
2504 p->cur_bytes_per_pixel = 4;
2505 p->pri_horiz_pixels =
2506 intel_crtc->config.requested_mode.hdisplay;
2507 p->cur_horiz_pixels = 64;
2508 }
2509
2510 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2511 struct intel_plane *intel_plane = to_intel_plane(plane);
2512 struct hsw_pipe_wm_parameters *p;
2513
2514 pipe = intel_plane->pipe;
2515 p = &params[pipe];
2516
bdd57d03 2517 p->sprite_enabled = intel_plane->wm.enabled;
801bcfff
PZ		 2518 p->spr_bytes_per_pixel = intel_plane->wm.bytes_per_pixel;
2519 p->spr_horiz_pixels = intel_plane->wm.horiz_pixels;
cca32e9a
PZ		 2520
2521 if (p->sprite_enabled)
2522 sprites_enabled++;
2523 }
2524
2525 if (pipes_active > 1) {
861f3389
PZ		 2526 lp_max_1_2->pri = lp_max_5_6->pri = sprites_enabled ? 128 : 256;
2527 lp_max_1_2->spr = lp_max_5_6->spr = 128;
2528 lp_max_1_2->cur = lp_max_5_6->cur = 64;
cca32e9a
PZ		 2529 } else {
2530 lp_max_1_2->pri = sprites_enabled ? 384 : 768;
861f3389 2531 lp_max_5_6->pri = sprites_enabled ? 128 : 768;
cca32e9a 2532 lp_max_1_2->spr = 384;
861f3389
PZ		 2533 lp_max_5_6->spr = 640;
2534 lp_max_1_2->cur = lp_max_5_6->cur = 255;
801bcfff 2535 }
861f3389 2536 lp_max_1_2->fbc = lp_max_5_6->fbc = 15;
801bcfff
PZ		 2537}
2538
2539static void hsw_compute_wm_results(struct drm_device *dev,
2540 struct hsw_pipe_wm_parameters *params,
cca32e9a 2541 struct hsw_wm_maximums *lp_maximums,
801bcfff
PZ		 2542 struct hsw_wm_values *results)
2543{
2544 struct drm_i915_private *dev_priv = dev->dev_private;
2545 struct drm_crtc *crtc;
cca32e9a 2546 struct hsw_lp_wm_result lp_results[4] = {};
801bcfff 2547 enum pipe pipe;
cca32e9a
PZ		 2548 int level, max_level, wm_lp;
2549
2550 for (level = 1; level <= 4; level++)
5b77da33
VS		 2551 if (!hsw_compute_lp_wm(dev_priv, level,
2552 lp_maximums, params,
cca32e9a
PZ		 2553 &lp_results[level - 1]))
2554 break;
2555 max_level = level - 1;
2556
2557 /* The spec says it is preferred to disable FBC WMs instead of disabling
2558 * a WM level. */
2559 results->enable_fbc_wm = true;
2560 for (level = 1; level <= max_level; level++) {
2561 if (!lp_results[level - 1].fbc_enable) {
2562 results->enable_fbc_wm = false;
2563 break;
2564 }
2565 }
2566
2567 memset(results, 0, sizeof(*results));
2568 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2569 const struct hsw_lp_wm_result *r;
801bcfff 2570
cca32e9a
PZ		 2571 level = (max_level == 4 && wm_lp > 1) ? wm_lp + 1 : wm_lp;
2572 if (level > max_level)
2573 break;
2574
2575 r = &lp_results[level - 1];
2576 results->wm_lp[wm_lp - 1] = HSW_WM_LP_VAL(level * 2,
2577 r->fbc_val,
2578 r->pri_val,
2579 r->cur_val);
2580 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
2581 }
801bcfff
PZ		 2582
2583 for_each_pipe(pipe)
5b77da33 2584 results->wm_pipe[pipe] = hsw_compute_wm_pipe(dev_priv, pipe,
801bcfff 2585 &params[pipe]);
1011d8c4
PZ		 2586
2587 for_each_pipe(pipe) {
2588 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
801bcfff
PZ		 2589 results->wm_linetime[pipe] = hsw_compute_linetime_wm(dev, crtc);
2590 }
2591}
2592
861f3389
PZ		 2593/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2594 * case both are at the same level. Prefer r1 in case they're the same. */
f4db9321
DL		 2595static struct hsw_wm_values *hsw_find_best_result(struct hsw_wm_values *r1,
2596 struct hsw_wm_values *r2)
861f3389
PZ		 2597{
2598 int i, val_r1 = 0, val_r2 = 0;
2599
2600 for (i = 0; i < 3; i++) {
2601 if (r1->wm_lp[i] & WM3_LP_EN)
2602 val_r1 = r1->wm_lp[i] & WM1_LP_LATENCY_MASK;
2603 if (r2->wm_lp[i] & WM3_LP_EN)
2604 val_r2 = r2->wm_lp[i] & WM1_LP_LATENCY_MASK;
2605 }
2606
2607 if (val_r1 == val_r2) {
2608 if (r2->enable_fbc_wm && !r1->enable_fbc_wm)
2609 return r2;
2610 else
2611 return r1;
2612 } else if (val_r1 > val_r2) {
2613 return r1;
2614 } else {
2615 return r2;
2616 }
2617}
2618
801bcfff
PZ		 2619/*
2620 * The spec says we shouldn't write when we don't need, because every write
2621 * causes WMs to be re-evaluated, expending some power.
2622 */
2623static void hsw_write_wm_values(struct drm_i915_private *dev_priv,
2624 struct hsw_wm_values *results,
2625 enum hsw_data_buf_partitioning partitioning)
2626{
2627 struct hsw_wm_values previous;
2628 uint32_t val;
2629 enum hsw_data_buf_partitioning prev_partitioning;
cca32e9a 2630 bool prev_enable_fbc_wm;
801bcfff
PZ		 2631
2632 previous.wm_pipe[0] = I915_READ(WM0_PIPEA_ILK);
2633 previous.wm_pipe[1] = I915_READ(WM0_PIPEB_ILK);
2634 previous.wm_pipe[2] = I915_READ(WM0_PIPEC_IVB);
2635 previous.wm_lp[0] = I915_READ(WM1_LP_ILK);
2636 previous.wm_lp[1] = I915_READ(WM2_LP_ILK);
2637 previous.wm_lp[2] = I915_READ(WM3_LP_ILK);
2638 previous.wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
2639 previous.wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
2640 previous.wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
2641 previous.wm_linetime[0] = I915_READ(PIPE_WM_LINETIME(PIPE_A));
2642 previous.wm_linetime[1] = I915_READ(PIPE_WM_LINETIME(PIPE_B));
2643 previous.wm_linetime[2] = I915_READ(PIPE_WM_LINETIME(PIPE_C));
2644
2645 prev_partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
2646 HSW_DATA_BUF_PART_5_6 : HSW_DATA_BUF_PART_1_2;
2647
cca32e9a
PZ		 2648 prev_enable_fbc_wm = !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
2649
801bcfff
PZ		 2650 if (memcmp(results->wm_pipe, previous.wm_pipe,
2651 sizeof(results->wm_pipe)) == 0 &&
2652 memcmp(results->wm_lp, previous.wm_lp,
2653 sizeof(results->wm_lp)) == 0 &&
2654 memcmp(results->wm_lp_spr, previous.wm_lp_spr,
2655 sizeof(results->wm_lp_spr)) == 0 &&
2656 memcmp(results->wm_linetime, previous.wm_linetime,
2657 sizeof(results->wm_linetime)) == 0 &&
cca32e9a
PZ		 2658 partitioning == prev_partitioning &&
2659 results->enable_fbc_wm == prev_enable_fbc_wm)
801bcfff
PZ		 2660 return;
2661
2662 if (previous.wm_lp[2] != 0)
2663 I915_WRITE(WM3_LP_ILK, 0);
2664 if (previous.wm_lp[1] != 0)
2665 I915_WRITE(WM2_LP_ILK, 0);
2666 if (previous.wm_lp[0] != 0)
2667 I915_WRITE(WM1_LP_ILK, 0);
2668
2669 if (previous.wm_pipe[0] != results->wm_pipe[0])
2670 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
2671 if (previous.wm_pipe[1] != results->wm_pipe[1])
2672 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
2673 if (previous.wm_pipe[2] != results->wm_pipe[2])
2674 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2675
2676 if (previous.wm_linetime[0] != results->wm_linetime[0])
2677 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
2678 if (previous.wm_linetime[1] != results->wm_linetime[1])
2679 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
2680 if (previous.wm_linetime[2] != results->wm_linetime[2])
2681 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2682
2683 if (prev_partitioning != partitioning) {
2684 val = I915_READ(WM_MISC);
2685 if (partitioning == HSW_DATA_BUF_PART_1_2)
2686 val &= ~WM_MISC_DATA_PARTITION_5_6;
2687 else
2688 val |= WM_MISC_DATA_PARTITION_5_6;
2689 I915_WRITE(WM_MISC, val);
1011d8c4
PZ		 2690 }
2691
cca32e9a
PZ		 2692 if (prev_enable_fbc_wm != results->enable_fbc_wm) {
2693 val = I915_READ(DISP_ARB_CTL);
2694 if (results->enable_fbc_wm)
2695 val &= ~DISP_FBC_WM_DIS;
2696 else
2697 val |= DISP_FBC_WM_DIS;
2698 I915_WRITE(DISP_ARB_CTL, val);
2699 }
2700
801bcfff
PZ		 2701 if (previous.wm_lp_spr[0] != results->wm_lp_spr[0])
2702 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2703 if (previous.wm_lp_spr[1] != results->wm_lp_spr[1])
2704 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2705 if (previous.wm_lp_spr[2] != results->wm_lp_spr[2])
2706 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2707
2708 if (results->wm_lp[0] != 0)
2709 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
2710 if (results->wm_lp[1] != 0)
2711 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
2712 if (results->wm_lp[2] != 0)
2713 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
2714}
2715
2716static void haswell_update_wm(struct drm_device *dev)
2717{
2718 struct drm_i915_private *dev_priv = dev->dev_private;
861f3389 2719 struct hsw_wm_maximums lp_max_1_2, lp_max_5_6;
801bcfff 2720 struct hsw_pipe_wm_parameters params[3];
861f3389 2721 struct hsw_wm_values results_1_2, results_5_6, *best_results;
861f3389
PZ		 2722 enum hsw_data_buf_partitioning partitioning;
2723
12b134df 2724 hsw_compute_wm_parameters(dev, params, &lp_max_1_2, &lp_max_5_6);
861f3389 2725
53615a5e 2726 hsw_compute_wm_results(dev, params,
53615a5e 2727 &lp_max_1_2, &results_1_2);
861f3389 2728 if (lp_max_1_2.pri != lp_max_5_6.pri) {
53615a5e 2729 hsw_compute_wm_results(dev, params,
53615a5e 2730 &lp_max_5_6, &results_5_6);
861f3389
PZ		 2731 best_results = hsw_find_best_result(&results_1_2, &results_5_6);
2732 } else {
2733 best_results = &results_1_2;
2734 }
2735
2736 partitioning = (best_results == &results_1_2) ?
2737 HSW_DATA_BUF_PART_1_2 : HSW_DATA_BUF_PART_5_6;
801bcfff 2738
861f3389 2739 hsw_write_wm_values(dev_priv, best_results, partitioning);
1011d8c4
PZ		 2740}
2741
526682e9
PZ		 2742static void haswell_update_sprite_wm(struct drm_device *dev, int pipe,
2743 uint32_t sprite_width, int pixel_size,
bdd57d03 2744 bool enabled, bool scaled)
526682e9
PZ		 2745{
2746 struct drm_plane *plane;
2747
2748 list_for_each_entry(plane, &dev->mode_config.plane_list, head) {
2749 struct intel_plane *intel_plane = to_intel_plane(plane);
2750
2751 if (intel_plane->pipe == pipe) {
bdd57d03
VS		 2752 intel_plane->wm.enabled = enabled;
2753 intel_plane->wm.scaled = scaled;
67ca28f3 2754 intel_plane->wm.horiz_pixels = sprite_width;
526682e9
PZ		 2755 intel_plane->wm.bytes_per_pixel = pixel_size;
2756 break;
2757 }
2758 }
2759
2760 haswell_update_wm(dev);
2761}
2762
b445e3b0
ED		 2763static bool
2764sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2765 uint32_t sprite_width, int pixel_size,
2766 const struct intel_watermark_params *display,
2767 int display_latency_ns, int *sprite_wm)
2768{
2769 struct drm_crtc *crtc;
2770 int clock;
2771 int entries, tlb_miss;
2772
2773 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2774 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2775 *sprite_wm = display->guard_size;
2776 return false;
2777 }
2778
2779 clock = crtc->mode.clock;
2780
2781 /* Use the small buffer method to calculate the sprite watermark */
2782 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2783 tlb_miss = display->fifo_size*display->cacheline_size -
2784 sprite_width * 8;
2785 if (tlb_miss > 0)
2786 entries += tlb_miss;
2787 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2788 *sprite_wm = entries + display->guard_size;
2789 if (*sprite_wm > (int)display->max_wm)
2790 *sprite_wm = display->max_wm;
2791
2792 return true;
2793}
2794
2795static bool
2796sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2797 uint32_t sprite_width, int pixel_size,
2798 const struct intel_watermark_params *display,
2799 int latency_ns, int *sprite_wm)
2800{
2801 struct drm_crtc *crtc;
2802 unsigned long line_time_us;
2803 int clock;
2804 int line_count, line_size;
2805 int small, large;
2806 int entries;
2807
2808 if (!latency_ns) {
2809 *sprite_wm = 0;
2810 return false;
2811 }
2812
2813 crtc = intel_get_crtc_for_plane(dev, plane);
2814 clock = crtc->mode.clock;
2815 if (!clock) {
2816 *sprite_wm = 0;
2817 return false;
2818 }
2819
2820 line_time_us = (sprite_width * 1000) / clock;
2821 if (!line_time_us) {
2822 *sprite_wm = 0;
2823 return false;
2824 }
2825
2826 line_count = (latency_ns / line_time_us + 1000) / 1000;
2827 line_size = sprite_width * pixel_size;
2828
2829 /* Use the minimum of the small and large buffer method for primary */
2830 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2831 large = line_count * line_size;
2832
2833 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2834 *sprite_wm = entries + display->guard_size;
2835
2836 return *sprite_wm > 0x3ff ? false : true;
2837}
2838
1fa61106 2839static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
4c4ff43a 2840 uint32_t sprite_width, int pixel_size,
39db4a4d 2841 bool enabled, bool scaled)
b445e3b0
ED		 2842{
2843 struct drm_i915_private *dev_priv = dev->dev_private;
b0aea5dc 2844 int latency = dev_priv->wm.spr_latency[0] * 100; /* In unit 0.1us */
b445e3b0
ED		 2845 u32 val;
2846 int sprite_wm, reg;
2847 int ret;
2848
39db4a4d 2849 if (!enabled)
4c4ff43a
PZ		 2850 return;
2851
b445e3b0
ED		 2852 switch (pipe) {
2853 case 0:
2854 reg = WM0_PIPEA_ILK;
2855 break;
2856 case 1:
2857 reg = WM0_PIPEB_ILK;
2858 break;
2859 case 2:
2860 reg = WM0_PIPEC_IVB;
2861 break;
2862 default:
2863 return; /* bad pipe */
2864 }
2865
2866 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2867 &sandybridge_display_wm_info,
2868 latency, &sprite_wm);
2869 if (!ret) {
84f44ce7
VS		 2870 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %c\n",
2871 pipe_name(pipe));
b445e3b0
ED		 2872 return;
2873 }
2874
2875 val = I915_READ(reg);
2876 val &= ~WM0_PIPE_SPRITE_MASK;
2877 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
84f44ce7 2878 DRM_DEBUG_KMS("sprite watermarks For pipe %c - %d\n", pipe_name(pipe), sprite_wm);
b445e3b0
ED		 2879
2880
2881 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2882 pixel_size,
2883 &sandybridge_display_srwm_info,
b0aea5dc 2884 dev_priv->wm.spr_latency[1] * 500,
b445e3b0
ED		 2885 &sprite_wm);
2886 if (!ret) {
84f44ce7
VS		 2887 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %c\n",
2888 pipe_name(pipe));
b445e3b0
ED		 2889 return;
2890 }
2891 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2892
2893 /* Only IVB has two more LP watermarks for sprite */
2894 if (!IS_IVYBRIDGE(dev))
2895 return;
2896
2897 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2898 pixel_size,
2899 &sandybridge_display_srwm_info,
b0aea5dc 2900 dev_priv->wm.spr_latency[2] * 500,
b445e3b0
ED		 2901 &sprite_wm);
2902 if (!ret) {
84f44ce7
VS		 2903 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %c\n",
2904 pipe_name(pipe));
b445e3b0
ED		 2905 return;
2906 }
2907 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2908
2909 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2910 pixel_size,
2911 &sandybridge_display_srwm_info,
b0aea5dc 2912 dev_priv->wm.spr_latency[3] * 500,
b445e3b0
ED		 2913 &sprite_wm);
2914 if (!ret) {
84f44ce7
VS		 2915 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %c\n",
2916 pipe_name(pipe));
b445e3b0
ED		 2917 return;
2918 }
2919 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2920}
2921
2922/**
2923 * intel_update_watermarks - update FIFO watermark values based on current modes
2924 *
2925 * Calculate watermark values for the various WM regs based on current mode
2926 * and plane configuration.
2927 *
2928 * There are several cases to deal with here:
2929 * - normal (i.e. non-self-refresh)
2930 * - self-refresh (SR) mode
2931 * - lines are large relative to FIFO size (buffer can hold up to 2)
2932 * - lines are small relative to FIFO size (buffer can hold more than 2
2933 * lines), so need to account for TLB latency
2934 *
2935 * The normal calculation is:
2936 * watermark = dotclock * bytes per pixel * latency
2937 * where latency is platform & configuration dependent (we assume pessimal
2938 * values here).
2939 *
2940 * The SR calculation is:
2941 * watermark = (trunc(latency/line time)+1) * surface width *
2942 * bytes per pixel
2943 * where
2944 * line time = htotal / dotclock
2945 * surface width = hdisplay for normal plane and 64 for cursor
2946 * and latency is assumed to be high, as above.
2947 *
2948 * The final value programmed to the register should always be rounded up,
2949 * and include an extra 2 entries to account for clock crossings.
2950 *
2951 * We don't use the sprite, so we can ignore that. And on Crestline we have
2952 * to set the non-SR watermarks to 8.
2953 */
2954void intel_update_watermarks(struct drm_device *dev)
2955{
2956 struct drm_i915_private *dev_priv = dev->dev_private;
2957
2958 if (dev_priv->display.update_wm)
2959 dev_priv->display.update_wm(dev);
2960}
2961
2962void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
4c4ff43a 2963 uint32_t sprite_width, int pixel_size,
39db4a4d 2964 bool enabled, bool scaled)
b445e3b0
ED		 2965{
2966 struct drm_i915_private *dev_priv = dev->dev_private;
2967
2968 if (dev_priv->display.update_sprite_wm)
2969 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
39db4a4d 2970 pixel_size, enabled, scaled);
b445e3b0
ED		 2971}
2972
2b4e57bd
ED		 2973static struct drm_i915_gem_object *
2974intel_alloc_context_page(struct drm_device *dev)
2975{
2976 struct drm_i915_gem_object *ctx;
2977 int ret;
2978
2979 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2980
2981 ctx = i915_gem_alloc_object(dev, 4096);
2982 if (!ctx) {
2983 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2984 return NULL;
2985 }
2986
c37e2204 2987 ret = i915_gem_obj_ggtt_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2988 if (ret) {
2989 DRM_ERROR("failed to pin power context: %d\n", ret);
2990 goto err_unref;
2991 }
2992
2993 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2994 if (ret) {
2995 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2996 goto err_unpin;
2997 }
2998
2999 return ctx;
3000
3001err_unpin:
3002 i915_gem_object_unpin(ctx);
3003err_unref:
3004 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 3005 return NULL;
3006}
3007
9270388e
DV		 3008/**
3009 * Lock protecting IPS related data structures
9270388e
DV		 3010 */
3011DEFINE_SPINLOCK(mchdev_lock);
3012
3013/* Global for IPS driver to get at the current i915 device. Protected by
3014 * mchdev_lock. */
3015static struct drm_i915_private *i915_mch_dev;
3016
2b4e57bd
ED		 3017bool ironlake_set_drps(struct drm_device *dev, u8 val)
3018{
3019 struct drm_i915_private *dev_priv = dev->dev_private;
3020 u16 rgvswctl;
3021
9270388e
DV		 3022 assert_spin_locked(&mchdev_lock);
3023
2b4e57bd
ED		 3024 rgvswctl = I915_READ16(MEMSWCTL);
3025 if (rgvswctl & MEMCTL_CMD_STS) {
3026 DRM_DEBUG("gpu busy, RCS change rejected\n");
3027 return false; /* still busy with another command */
3028 }
3029
3030 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
3031 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
3032 I915_WRITE16(MEMSWCTL, rgvswctl);
3033 POSTING_READ16(MEMSWCTL);
3034
3035 rgvswctl |= MEMCTL_CMD_STS;
3036 I915_WRITE16(MEMSWCTL, rgvswctl);
3037
3038 return true;
3039}
3040
8090c6b9 3041static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 3042{
3043 struct drm_i915_private *dev_priv = dev->dev_private;
3044 u32 rgvmodectl = I915_READ(MEMMODECTL);
3045 u8 fmax, fmin, fstart, vstart;
3046
9270388e
DV		 3047 spin_lock_irq(&mchdev_lock);
3048
2b4e57bd
ED		 3049 /* Enable temp reporting */
3050 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
3051 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
3052
3053 /* 100ms RC evaluation intervals */
3054 I915_WRITE(RCUPEI, 100000);
3055 I915_WRITE(RCDNEI, 100000);
3056
3057 /* Set max/min thresholds to 90ms and 80ms respectively */
3058 I915_WRITE(RCBMAXAVG, 90000);
3059 I915_WRITE(RCBMINAVG, 80000);
3060
3061 I915_WRITE(MEMIHYST, 1);
3062
3063 /* Set up min, max, and cur for interrupt handling */
3064 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
3065 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
3066 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
3067 MEMMODE_FSTART_SHIFT;
3068
3069 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
3070 PXVFREQ_PX_SHIFT;
3071
20e4d407
DV		 3072 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
3073 dev_priv->ips.fstart = fstart;
2b4e57bd 3074
20e4d407
DV		 3075 dev_priv->ips.max_delay = fstart;
3076 dev_priv->ips.min_delay = fmin;
3077 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 3078
3079 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
3080 fmax, fmin, fstart);
3081
3082 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
3083
3084 /*
3085 * Interrupts will be enabled in ironlake_irq_postinstall
3086 */
3087
3088 I915_WRITE(VIDSTART, vstart);
3089 POSTING_READ(VIDSTART);
3090
3091 rgvmodectl |= MEMMODE_SWMODE_EN;
3092 I915_WRITE(MEMMODECTL, rgvmodectl);
3093
9270388e 3094 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 3095 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 3096 mdelay(1);
2b4e57bd
ED		 3097
3098 ironlake_set_drps(dev, fstart);
3099
20e4d407 3100 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 3101 I915_READ(0x112e0);
20e4d407
DV		 3102 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
3103 dev_priv->ips.last_count2 = I915_READ(0x112f4);
3104 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 3105
3106 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3107}
3108
8090c6b9 3109static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 3110{
3111 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 3112 u16 rgvswctl;
3113
3114 spin_lock_irq(&mchdev_lock);
3115
3116 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 3117
3118 /* Ack interrupts, disable EFC interrupt */
3119 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
3120 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
3121 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
3122 I915_WRITE(DEIIR, DE_PCU_EVENT);
3123 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
3124
3125 /* Go back to the starting frequency */
20e4d407 3126 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 3127 mdelay(1);
2b4e57bd
ED		 3128 rgvswctl |= MEMCTL_CMD_STS;
3129 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 3130 mdelay(1);
2b4e57bd 3131
9270388e 3132 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 3133}
3134
acbe9475
DV		 3135/* There's a funny hw issue where the hw returns all 0 when reading from
3136 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
3137 * ourselves, instead of doing a rmw cycle (which might result in us clearing
3138 * all limits and the gpu stuck at whatever frequency it is at atm).
3139 */
65bccb5c 3140static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 3141{
7b9e0ae6 3142 u32 limits;
2b4e57bd 3143
7b9e0ae6 3144 limits = 0;
c6a828d3
DV		 3145
3146 if (*val >= dev_priv->rps.max_delay)
3147 *val = dev_priv->rps.max_delay;
3148 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 3149
3150 /* Only set the down limit when we've reached the lowest level to avoid
3151 * getting more interrupts, otherwise leave this clear. This prevents a
3152 * race in the hw when coming out of rc6: There's a tiny window where
3153 * the hw runs at the minimal clock before selecting the desired
3154 * frequency, if the down threshold expires in that window we will not
3155 * receive a down interrupt. */
c6a828d3
DV		 3156 if (*val <= dev_priv->rps.min_delay) {
3157 *val = dev_priv->rps.min_delay;
3158 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 3159 }
3160
3161 return limits;
3162}
3163
3164void gen6_set_rps(struct drm_device *dev, u8 val)
3165{
3166 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 3167 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 3168
4fc688ce 3169 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 3170 WARN_ON(val > dev_priv->rps.max_delay);
3171 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 3172
c6a828d3 3173 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 3174 return;
3175
92bd1bf0
RV		 3176 if (IS_HASWELL(dev))
3177 I915_WRITE(GEN6_RPNSWREQ,
3178 HSW_FREQUENCY(val));
3179 else
3180 I915_WRITE(GEN6_RPNSWREQ,
3181 GEN6_FREQUENCY(val) |
3182 GEN6_OFFSET(0) |
3183 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 3184
3185 /* Make sure we continue to get interrupts
3186 * until we hit the minimum or maximum frequencies.
3187 */
3188 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
3189
d5570a72
BW		 3190 POSTING_READ(GEN6_RPNSWREQ);
3191
c6a828d3 3192 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 3193
3194 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 3195}
3196
80814ae4
VS		 3197/*
3198 * Wait until the previous freq change has completed,
3199 * or the timeout elapsed, and then update our notion
3200 * of the current GPU frequency.
3201 */
3202static void vlv_update_rps_cur_delay(struct drm_i915_private *dev_priv)
3203{
80814ae4
VS		 3204 u32 pval;
3205
3206 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3207
e8474409
VS		 3208 if (wait_for(((pval = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS)) & GENFREQSTATUS) == 0, 10))
3209 DRM_DEBUG_DRIVER("timed out waiting for Punit\n");
80814ae4
VS		 3210
3211 pval >>= 8;
3212
3213 if (pval != dev_priv->rps.cur_delay)
3214 DRM_DEBUG_DRIVER("Punit overrode GPU freq: %d MHz (%u) requested, but got %d Mhz (%u)\n",
3215 vlv_gpu_freq(dev_priv->mem_freq, dev_priv->rps.cur_delay),
3216 dev_priv->rps.cur_delay,
3217 vlv_gpu_freq(dev_priv->mem_freq, pval), pval);
3218
3219 dev_priv->rps.cur_delay = pval;
3220}
3221
0a073b84
JB		 3222void valleyview_set_rps(struct drm_device *dev, u8 val)
3223{
3224 struct drm_i915_private *dev_priv = dev->dev_private;
7a67092a
VS		 3225
3226 gen6_rps_limits(dev_priv, &val);
0a073b84
JB		 3227
3228 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3229 WARN_ON(val > dev_priv->rps.max_delay);
3230 WARN_ON(val < dev_priv->rps.min_delay);
3231
80814ae4
VS		 3232 vlv_update_rps_cur_delay(dev_priv);
3233
73008b98 3234 DRM_DEBUG_DRIVER("GPU freq request from %d MHz (%u) to %d MHz (%u)\n",
0a073b84
JB		 3235 vlv_gpu_freq(dev_priv->mem_freq,
3236 dev_priv->rps.cur_delay),
73008b98
VS		 3237 dev_priv->rps.cur_delay,
3238 vlv_gpu_freq(dev_priv->mem_freq, val), val);
0a073b84
JB		 3239
3240 if (val == dev_priv->rps.cur_delay)
3241 return;
3242
ae99258f 3243 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
0a073b84 3244
80814ae4 3245 dev_priv->rps.cur_delay = val;
0a073b84
JB		 3246
3247 trace_intel_gpu_freq_change(vlv_gpu_freq(dev_priv->mem_freq, val));
3248}
3249
44fc7d5c 3250static void gen6_disable_rps_interrupts(struct drm_device *dev)
2b4e57bd
ED		 3251{
3252 struct drm_i915_private *dev_priv = dev->dev_private;
3253
2b4e57bd 3254 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
4848405c 3255 I915_WRITE(GEN6_PMIER, I915_READ(GEN6_PMIER) & ~GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3256 /* Complete PM interrupt masking here doesn't race with the rps work
3257 * item again unmasking PM interrupts because that is using a different
3258 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
3259 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
3260
59cdb63d 3261 spin_lock_irq(&dev_priv->irq_lock);
c6a828d3 3262 dev_priv->rps.pm_iir = 0;
59cdb63d 3263 spin_unlock_irq(&dev_priv->irq_lock);
2b4e57bd 3264
4848405c 3265 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
2b4e57bd
ED		 3266}
3267
44fc7d5c 3268static void gen6_disable_rps(struct drm_device *dev)
d20d4f0c
JB		 3269{
3270 struct drm_i915_private *dev_priv = dev->dev_private;
3271
3272 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 3273 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
d20d4f0c 3274
44fc7d5c
DV		 3275 gen6_disable_rps_interrupts(dev);
3276}
3277
3278static void valleyview_disable_rps(struct drm_device *dev)
3279{
3280 struct drm_i915_private *dev_priv = dev->dev_private;
3281
3282 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 3283
44fc7d5c 3284 gen6_disable_rps_interrupts(dev);
c9cddffc
JB		 3285
3286 if (dev_priv->vlv_pctx) {
3287 drm_gem_object_unreference(&dev_priv->vlv_pctx->base);
3288 dev_priv->vlv_pctx = NULL;
3289 }
d20d4f0c
JB		 3290}
3291
2b4e57bd
ED		 3292int intel_enable_rc6(const struct drm_device *dev)
3293{
eb4926e4
DL		 3294 /* No RC6 before Ironlake */
3295 if (INTEL_INFO(dev)->gen < 5)
3296 return 0;
3297
456470eb 3298 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 3299 if (i915_enable_rc6 >= 0)
3300 return i915_enable_rc6;
3301
6567d748
CW		 3302 /* Disable RC6 on Ironlake */
3303 if (INTEL_INFO(dev)->gen == 5)
3304 return 0;
2b4e57bd 3305
456470eb
DV		 3306 if (IS_HASWELL(dev)) {
3307 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 3308 return INTEL_RC6_ENABLE;
456470eb 3309 }
2b4e57bd 3310
456470eb 3311 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 3312 if (INTEL_INFO(dev)->gen == 6) {
3313 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
3314 return INTEL_RC6_ENABLE;
3315 }
456470eb 3316
2b4e57bd
ED		 3317 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
3318 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
3319}
3320
44fc7d5c
DV		 3321static void gen6_enable_rps_interrupts(struct drm_device *dev)
3322{
3323 struct drm_i915_private *dev_priv = dev->dev_private;
3324
3325 spin_lock_irq(&dev_priv->irq_lock);
a0b3335a 3326 WARN_ON(dev_priv->rps.pm_iir);
44fc7d5c
DV		 3327 I915_WRITE(GEN6_PMIMR, I915_READ(GEN6_PMIMR) & ~GEN6_PM_RPS_EVENTS);
3328 I915_WRITE(GEN6_PMIIR, GEN6_PM_RPS_EVENTS);
3329 spin_unlock_irq(&dev_priv->irq_lock);
3330 /* unmask all PM interrupts */
3331 I915_WRITE(GEN6_PMINTRMSK, 0);
3332}
3333
79f5b2c7 3334static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 3335{
79f5b2c7 3336 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 3337 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 3338 u32 rp_state_cap;
3339 u32 gt_perf_status;
31643d54 3340 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 3341 u32 gtfifodbg;
2b4e57bd 3342 int rc6_mode;
42c0526c 3343 int i, ret;
2b4e57bd 3344
4fc688ce 3345 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3346
2b4e57bd
ED		 3347 /* Here begins a magic sequence of register writes to enable
3348 * auto-downclocking.
3349 *
3350 * Perhaps there might be some value in exposing these to
3351 * userspace...
3352 */
3353 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 3354
3355 /* Clear the DBG now so we don't confuse earlier errors */
3356 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3357 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3358 I915_WRITE(GTFIFODBG, gtfifodbg);
3359 }
3360
3361 gen6_gt_force_wake_get(dev_priv);
3362
7b9e0ae6
CW		 3363 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
3364 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
3365
31c77388
BW		 3366 /* In units of 50MHz */
3367 dev_priv->rps.hw_max = dev_priv->rps.max_delay = rp_state_cap & 0xff;
c6a828d3
DV		 3368 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
3369 dev_priv->rps.cur_delay = 0;
7b9e0ae6 3370
2b4e57bd
ED		 3371 /* disable the counters and set deterministic thresholds */
3372 I915_WRITE(GEN6_RC_CONTROL, 0);
3373
3374 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
3375 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
3376 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
3377 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3378 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3379
b4519513
CW		 3380 for_each_ring(ring, dev_priv, i)
3381 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 3382
3383 I915_WRITE(GEN6_RC_SLEEP, 0);
3384 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
3385 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 3386 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 3387 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
3388
5a7dc92a 3389 /* Check if we are enabling RC6 */
2b4e57bd
ED		 3390 rc6_mode = intel_enable_rc6(dev_priv->dev);
3391 if (rc6_mode & INTEL_RC6_ENABLE)
3392 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
3393
5a7dc92a
ED		 3394 /* We don't use those on Haswell */
3395 if (!IS_HASWELL(dev)) {
3396 if (rc6_mode & INTEL_RC6p_ENABLE)
3397 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 3398
5a7dc92a
ED		 3399 if (rc6_mode & INTEL_RC6pp_ENABLE)
3400 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
3401 }
2b4e57bd
ED		 3402
3403 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 3404 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
3405 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
3406 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 3407
3408 I915_WRITE(GEN6_RC_CONTROL,
3409 rc6_mask |
3410 GEN6_RC_CTL_EI_MODE(1) |
3411 GEN6_RC_CTL_HW_ENABLE);
3412
92bd1bf0
RV		 3413 if (IS_HASWELL(dev)) {
3414 I915_WRITE(GEN6_RPNSWREQ,
3415 HSW_FREQUENCY(10));
3416 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3417 HSW_FREQUENCY(12));
3418 } else {
3419 I915_WRITE(GEN6_RPNSWREQ,
3420 GEN6_FREQUENCY(10) |
3421 GEN6_OFFSET(0) |
3422 GEN6_AGGRESSIVE_TURBO);
3423 I915_WRITE(GEN6_RC_VIDEO_FREQ,
3424 GEN6_FREQUENCY(12));
3425 }
2b4e57bd
ED		 3426
3427 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
3428 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 3429 dev_priv->rps.max_delay << 24 |
3430 dev_priv->rps.min_delay << 16);
5a7dc92a 3431
1ee9ae32
DV		 3432 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3433 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3434 I915_WRITE(GEN6_RP_UP_EI, 66000);
3435 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 3436
2b4e57bd
ED		 3437 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3438 I915_WRITE(GEN6_RP_CONTROL,
3439 GEN6_RP_MEDIA_TURBO |
89ba829e 3440 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 3441 GEN6_RP_MEDIA_IS_GFX |
3442 GEN6_RP_ENABLE |
3443 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 3444 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 3445
42c0526c 3446 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
988b36e5 3447 if (!ret) {
42c0526c
BW		 3448 pcu_mbox = 0;
3449 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01 3450 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
10e08497 3451 DRM_DEBUG_DRIVER("Overclocking supported. Max: %dMHz, Overclock max: %dMHz\n",
a2b3fc01
BW		 3452 (dev_priv->rps.max_delay & 0xff) * 50,
3453 (pcu_mbox & 0xff) * 50);
31c77388 3454 dev_priv->rps.hw_max = pcu_mbox & 0xff;
42c0526c
BW		 3455 }
3456 } else {
3457 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 3458 }
3459
7b9e0ae6 3460 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd 3461
44fc7d5c 3462 gen6_enable_rps_interrupts(dev);
2b4e57bd 3463
31643d54
BW		 3464 rc6vids = 0;
3465 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
3466 if (IS_GEN6(dev) && ret) {
3467 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
3468 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
3469 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
3470 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
3471 rc6vids &= 0xffff00;
3472 rc6vids |= GEN6_ENCODE_RC6_VID(450);
3473 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
3474 if (ret)
3475 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
3476 }
3477
2b4e57bd 3478 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 3479}
3480
79f5b2c7 3481static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 3482{
79f5b2c7 3483 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 3484 int min_freq = 15;
3ebecd07
CW		 3485 unsigned int gpu_freq;
3486 unsigned int max_ia_freq, min_ring_freq;
2b4e57bd
ED		 3487 int scaling_factor = 180;
3488
4fc688ce 3489 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 3490
2b4e57bd
ED		 3491 max_ia_freq = cpufreq_quick_get_max(0);
3492 /*
3493 * Default to measured freq if none found, PCU will ensure we don't go
3494 * over
3495 */
3496 if (!max_ia_freq)
3497 max_ia_freq = tsc_khz;
3498
3499 /* Convert from kHz to MHz */
3500 max_ia_freq /= 1000;
3501
3ebecd07
CW		 3502 min_ring_freq = I915_READ(MCHBAR_MIRROR_BASE_SNB + DCLK);
3503 /* convert DDR frequency from units of 133.3MHz to bandwidth */
3504 min_ring_freq = (2 * 4 * min_ring_freq + 2) / 3;
3505
2b4e57bd
ED		 3506 /*
3507 * For each potential GPU frequency, load a ring frequency we'd like
3508 * to use for memory access. We do this by specifying the IA frequency
3509 * the PCU should use as a reference to determine the ring frequency.
3510 */
c6a828d3 3511 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 3512 gpu_freq--) {
c6a828d3 3513 int diff = dev_priv->rps.max_delay - gpu_freq;
3ebecd07
CW		 3514 unsigned int ia_freq = 0, ring_freq = 0;
3515
3516 if (IS_HASWELL(dev)) {
3517 ring_freq = (gpu_freq * 5 + 3) / 4;
3518 ring_freq = max(min_ring_freq, ring_freq);
3519 /* leave ia_freq as the default, chosen by cpufreq */
3520 } else {
3521 /* On older processors, there is no separate ring
3522 * clock domain, so in order to boost the bandwidth
3523 * of the ring, we need to upclock the CPU (ia_freq).
3524 *
3525 * For GPU frequencies less than 750MHz,
3526 * just use the lowest ring freq.
3527 */
3528 if (gpu_freq < min_freq)
3529 ia_freq = 800;
3530 else
3531 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
3532 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
3533 }
2b4e57bd 3534
42c0526c
BW		 3535 sandybridge_pcode_write(dev_priv,
3536 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 3537 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
3538 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
3539 gpu_freq);
2b4e57bd 3540 }
2b4e57bd
ED		 3541}
3542
0a073b84
JB		 3543int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
3544{
3545 u32 val, rp0;
3546
64936258 3547 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 3548
3549 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
3550 /* Clamp to max */
3551 rp0 = min_t(u32, rp0, 0xea);
3552
3553 return rp0;
3554}
3555
3556static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
3557{
3558 u32 val, rpe;
3559
64936258 3560 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 3561 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 3562 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 3563 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
3564
3565 return rpe;
3566}
3567
3568int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
3569{
64936258 3570 return vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
0a073b84
JB		 3571}
3572
52ceb908
JB		 3573static void vlv_rps_timer_work(struct work_struct *work)
3574{
3575 drm_i915_private_t *dev_priv = container_of(work, drm_i915_private_t,
3576 rps.vlv_work.work);
3577
3578 /*
3579 * Timer fired, we must be idle. Drop to min voltage state.
3580 * Note: we use RPe here since it should match the
3581 * Vmin we were shooting for. That should give us better
3582 * perf when we come back out of RC6 than if we used the
3583 * min freq available.
3584 */
3585 mutex_lock(&dev_priv->rps.hw_lock);
6dc58488
VS		 3586 if (dev_priv->rps.cur_delay > dev_priv->rps.rpe_delay)
3587 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
52ceb908
JB		 3588 mutex_unlock(&dev_priv->rps.hw_lock);
3589}
3590
c9cddffc
JB		 3591static void valleyview_setup_pctx(struct drm_device *dev)
3592{
3593 struct drm_i915_private *dev_priv = dev->dev_private;
3594 struct drm_i915_gem_object *pctx;
3595 unsigned long pctx_paddr;
3596 u32 pcbr;
3597 int pctx_size = 24*1024;
3598
3599 pcbr = I915_READ(VLV_PCBR);
3600 if (pcbr) {
3601 /* BIOS set it up already, grab the pre-alloc'd space */
3602 int pcbr_offset;
3603
3604 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
3605 pctx = i915_gem_object_create_stolen_for_preallocated(dev_priv->dev,
3606 pcbr_offset,
190d6cd5 3607 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 3608 pctx_size);
3609 goto out;
3610 }
3611
3612 /*
3613 * From the Gunit register HAS:
3614 * The Gfx driver is expected to program this register and ensure
3615 * proper allocation within Gfx stolen memory. For example, this
3616 * register should be programmed such than the PCBR range does not
3617 * overlap with other ranges, such as the frame buffer, protected
3618 * memory, or any other relevant ranges.
3619 */
3620 pctx = i915_gem_object_create_stolen(dev, pctx_size);
3621 if (!pctx) {
3622 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
3623 return;
3624 }
3625
3626 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
3627 I915_WRITE(VLV_PCBR, pctx_paddr);
3628
3629out:
3630 dev_priv->vlv_pctx = pctx;
3631}
3632
0a073b84
JB		 3633static void valleyview_enable_rps(struct drm_device *dev)
3634{
3635 struct drm_i915_private *dev_priv = dev->dev_private;
3636 struct intel_ring_buffer *ring;
73008b98 3637 u32 gtfifodbg, val;
0a073b84
JB		 3638 int i;
3639
3640 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
3641
3642 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
3643 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
3644 I915_WRITE(GTFIFODBG, gtfifodbg);
3645 }
3646
c9cddffc
JB		 3647 valleyview_setup_pctx(dev);
3648
0a073b84
JB		 3649 gen6_gt_force_wake_get(dev_priv);
3650
3651 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
3652 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
3653 I915_WRITE(GEN6_RP_UP_EI, 66000);
3654 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
3655
3656 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
3657
3658 I915_WRITE(GEN6_RP_CONTROL,
3659 GEN6_RP_MEDIA_TURBO |
3660 GEN6_RP_MEDIA_HW_NORMAL_MODE |
3661 GEN6_RP_MEDIA_IS_GFX |
3662 GEN6_RP_ENABLE |
3663 GEN6_RP_UP_BUSY_AVG |
3664 GEN6_RP_DOWN_IDLE_CONT);
3665
3666 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
3667 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
3668 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
3669
3670 for_each_ring(ring, dev_priv, i)
3671 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
3672
3673 I915_WRITE(GEN6_RC6_THRESHOLD, 0xc350);
3674
3675 /* allows RC6 residency counter to work */
3676 I915_WRITE(0x138104, _MASKED_BIT_ENABLE(0x3));
3677 I915_WRITE(GEN6_RC_CONTROL,
3678 GEN7_RC_CTL_TO_MODE);
3679
64936258 3680 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
2445966e
JB		 3681 switch ((val >> 6) & 3) {
3682 case 0:
3683 case 1:
3684 dev_priv->mem_freq = 800;
3685 break;
3686 case 2:
3687 dev_priv->mem_freq = 1066;
3688 break;
3689 case 3:
3690 dev_priv->mem_freq = 1333;
3691 break;
3692 }
0a073b84
JB		 3693 DRM_DEBUG_DRIVER("DDR speed: %d MHz", dev_priv->mem_freq);
3694
3695 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", val & 0x10 ? "yes" : "no");
3696 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
3697
0a073b84 3698 dev_priv->rps.cur_delay = (val >> 8) & 0xff;
73008b98
VS		 3699 DRM_DEBUG_DRIVER("current GPU freq: %d MHz (%u)\n",
3700 vlv_gpu_freq(dev_priv->mem_freq,
3701 dev_priv->rps.cur_delay),
3702 dev_priv->rps.cur_delay);
0a073b84
JB		 3703
3704 dev_priv->rps.max_delay = valleyview_rps_max_freq(dev_priv);
3705 dev_priv->rps.hw_max = dev_priv->rps.max_delay;
73008b98
VS		 3706 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
3707 vlv_gpu_freq(dev_priv->mem_freq,
3708 dev_priv->rps.max_delay),
3709 dev_priv->rps.max_delay);
0a073b84 3710
73008b98
VS		 3711 dev_priv->rps.rpe_delay = valleyview_rps_rpe_freq(dev_priv);
3712 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
3713 vlv_gpu_freq(dev_priv->mem_freq,
3714 dev_priv->rps.rpe_delay),
3715 dev_priv->rps.rpe_delay);
0a073b84 3716
73008b98
VS		 3717 dev_priv->rps.min_delay = valleyview_rps_min_freq(dev_priv);
3718 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
3719 vlv_gpu_freq(dev_priv->mem_freq,
3720 dev_priv->rps.min_delay),
3721 dev_priv->rps.min_delay);
0a073b84 3722
73008b98
VS		 3723 DRM_DEBUG_DRIVER("setting GPU freq to %d MHz (%u)\n",
3724 vlv_gpu_freq(dev_priv->mem_freq,
3725 dev_priv->rps.rpe_delay),
3726 dev_priv->rps.rpe_delay);
0a073b84 3727
52ceb908
JB		 3728 INIT_DELAYED_WORK(&dev_priv->rps.vlv_work, vlv_rps_timer_work);
3729
73008b98 3730 valleyview_set_rps(dev_priv->dev, dev_priv->rps.rpe_delay);
0a073b84 3731
44fc7d5c 3732 gen6_enable_rps_interrupts(dev);
0a073b84
JB		 3733
3734 gen6_gt_force_wake_put(dev_priv);
3735}
3736
930ebb46 3737void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 3738{
3739 struct drm_i915_private *dev_priv = dev->dev_private;
3740
3e373948
DV		 3741 if (dev_priv->ips.renderctx) {
3742 i915_gem_object_unpin(dev_priv->ips.renderctx);
3743 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
3744 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 3745 }
3746
3e373948
DV		 3747 if (dev_priv->ips.pwrctx) {
3748 i915_gem_object_unpin(dev_priv->ips.pwrctx);
3749 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
3750 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 3751 }
3752}
3753
930ebb46 3754static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3755{
3756 struct drm_i915_private *dev_priv = dev->dev_private;
3757
3758 if (I915_READ(PWRCTXA)) {
3759 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
3760 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
3761 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
3762 50);
3763
3764 I915_WRITE(PWRCTXA, 0);
3765 POSTING_READ(PWRCTXA);
3766
3767 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
3768 POSTING_READ(RSTDBYCTL);
3769 }
2b4e57bd
ED		 3770}
3771
3772static int ironlake_setup_rc6(struct drm_device *dev)
3773{
3774 struct drm_i915_private *dev_priv = dev->dev_private;
3775
3e373948
DV		 3776 if (dev_priv->ips.renderctx == NULL)
3777 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
3778 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 3779 return -ENOMEM;
3780
3e373948
DV		 3781 if (dev_priv->ips.pwrctx == NULL)
3782 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
3783 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 3784 ironlake_teardown_rc6(dev);
3785 return -ENOMEM;
3786 }
3787
3788 return 0;
3789}
3790
930ebb46 3791static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 3792{
3793 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 3794 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 3795 bool was_interruptible;
2b4e57bd
ED		 3796 int ret;
3797
3798 /* rc6 disabled by default due to repeated reports of hanging during
3799 * boot and resume.
3800 */
3801 if (!intel_enable_rc6(dev))
3802 return;
3803
79f5b2c7
DV		 3804 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
3805
2b4e57bd 3806 ret = ironlake_setup_rc6(dev);
79f5b2c7 3807 if (ret)
2b4e57bd 3808 return;
2b4e57bd 3809
3e960501
CW		 3810 was_interruptible = dev_priv->mm.interruptible;
3811 dev_priv->mm.interruptible = false;
3812
2b4e57bd
ED		 3813 /*
3814 * GPU can automatically power down the render unit if given a page
3815 * to save state.
3816 */
6d90c952 3817 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 3818 if (ret) {
3819 ironlake_teardown_rc6(dev);
3e960501 3820 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 3821 return;
3822 }
3823
6d90c952
DV		 3824 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
3825 intel_ring_emit(ring, MI_SET_CONTEXT);
f343c5f6 3826 intel_ring_emit(ring, i915_gem_obj_ggtt_offset(dev_priv->ips.renderctx) |
6d90c952
DV		 3827 MI_MM_SPACE_GTT |
3828 MI_SAVE_EXT_STATE_EN |
3829 MI_RESTORE_EXT_STATE_EN |
3830 MI_RESTORE_INHIBIT);
3831 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
3832 intel_ring_emit(ring, MI_NOOP);
3833 intel_ring_emit(ring, MI_FLUSH);
3834 intel_ring_advance(ring);
2b4e57bd
ED		 3835
3836 /*
3837 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
3838 * does an implicit flush, combined with MI_FLUSH above, it should be
3839 * safe to assume that renderctx is valid
3840 */
3e960501
CW		 3841 ret = intel_ring_idle(ring);
3842 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 3843 if (ret) {
def27a58 3844 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 3845 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 3846 return;
3847 }
3848
f343c5f6 3849 I915_WRITE(PWRCTXA, i915_gem_obj_ggtt_offset(dev_priv->ips.pwrctx) | PWRCTX_EN);
2b4e57bd 3850 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 3851}
3852
dde18883
ED		 3853static unsigned long intel_pxfreq(u32 vidfreq)
3854{
3855 unsigned long freq;
3856 int div = (vidfreq & 0x3f0000) >> 16;
3857 int post = (vidfreq & 0x3000) >> 12;
3858 int pre = (vidfreq & 0x7);
3859
3860 if (!pre)
3861 return 0;
3862
3863 freq = ((div * 133333) / ((1<<post) * pre));
3864
3865 return freq;
3866}
3867
eb48eb00
DV		 3868static const struct cparams {
3869 u16 i;
3870 u16 t;
3871 u16 m;
3872 u16 c;
3873} cparams[] = {
3874 { 1, 1333, 301, 28664 },
3875 { 1, 1066, 294, 24460 },
3876 { 1, 800, 294, 25192 },
3877 { 0, 1333, 276, 27605 },
3878 { 0, 1066, 276, 27605 },
3879 { 0, 800, 231, 23784 },
3880};
3881
f531dcb2 3882static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3883{
3884 u64 total_count, diff, ret;
3885 u32 count1, count2, count3, m = 0, c = 0;
3886 unsigned long now = jiffies_to_msecs(jiffies), diff1;
3887 int i;
3888
02d71956
DV		 3889 assert_spin_locked(&mchdev_lock);
3890
20e4d407 3891 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 3892
3893 /* Prevent division-by-zero if we are asking too fast.
3894 * Also, we don't get interesting results if we are polling
3895 * faster than once in 10ms, so just return the saved value
3896 * in such cases.
3897 */
3898 if (diff1 <= 10)
20e4d407 3899 return dev_priv->ips.chipset_power;
eb48eb00
DV		 3900
3901 count1 = I915_READ(DMIEC);
3902 count2 = I915_READ(DDREC);
3903 count3 = I915_READ(CSIEC);
3904
3905 total_count = count1 + count2 + count3;
3906
3907 /* FIXME: handle per-counter overflow */
20e4d407
DV		 3908 if (total_count < dev_priv->ips.last_count1) {
3909 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 3910 diff += total_count;
3911 } else {
20e4d407 3912 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 3913 }
3914
3915 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 3916 if (cparams[i].i == dev_priv->ips.c_m &&
3917 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 3918 m = cparams[i].m;
3919 c = cparams[i].c;
3920 break;
3921 }
3922 }
3923
3924 diff = div_u64(diff, diff1);
3925 ret = ((m * diff) + c);
3926 ret = div_u64(ret, 10);
3927
20e4d407
DV		 3928 dev_priv->ips.last_count1 = total_count;
3929 dev_priv->ips.last_time1 = now;
eb48eb00 3930
20e4d407 3931 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 3932
3933 return ret;
3934}
3935
f531dcb2
CW		 3936unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
3937{
3938 unsigned long val;
3939
3940 if (dev_priv->info->gen != 5)
3941 return 0;
3942
3943 spin_lock_irq(&mchdev_lock);
3944
3945 val = __i915_chipset_val(dev_priv);
3946
3947 spin_unlock_irq(&mchdev_lock);
3948
3949 return val;
3950}
3951
eb48eb00
DV		 3952unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
3953{
3954 unsigned long m, x, b;
3955 u32 tsfs;
3956
3957 tsfs = I915_READ(TSFS);
3958
3959 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
3960 x = I915_READ8(TR1);
3961
3962 b = tsfs & TSFS_INTR_MASK;
3963
3964 return ((m * x) / 127) - b;
3965}
3966
3967static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
3968{
3969 static const struct v_table {
3970 u16 vd; /* in .1 mil */
3971 u16 vm; /* in .1 mil */
3972 } v_table[] = {
3973 { 0, 0, },
3974 { 375, 0, },
3975 { 500, 0, },
3976 { 625, 0, },
3977 { 750, 0, },
3978 { 875, 0, },
3979 { 1000, 0, },
3980 { 1125, 0, },
3981 { 4125, 3000, },
3982 { 4125, 3000, },
3983 { 4125, 3000, },
3984 { 4125, 3000, },
3985 { 4125, 3000, },
3986 { 4125, 3000, },
3987 { 4125, 3000, },
3988 { 4125, 3000, },
3989 { 4125, 3000, },
3990 { 4125, 3000, },
3991 { 4125, 3000, },
3992 { 4125, 3000, },
3993 { 4125, 3000, },
3994 { 4125, 3000, },
3995 { 4125, 3000, },
3996 { 4125, 3000, },
3997 { 4125, 3000, },
3998 { 4125, 3000, },
3999 { 4125, 3000, },
4000 { 4125, 3000, },
4001 { 4125, 3000, },
4002 { 4125, 3000, },
4003 { 4125, 3000, },
4004 { 4125, 3000, },
4005 { 4250, 3125, },
4006 { 4375, 3250, },
4007 { 4500, 3375, },
4008 { 4625, 3500, },
4009 { 4750, 3625, },
4010 { 4875, 3750, },
4011 { 5000, 3875, },
4012 { 5125, 4000, },
4013 { 5250, 4125, },
4014 { 5375, 4250, },
4015 { 5500, 4375, },
4016 { 5625, 4500, },
4017 { 5750, 4625, },
4018 { 5875, 4750, },
4019 { 6000, 4875, },
4020 { 6125, 5000, },
4021 { 6250, 5125, },
4022 { 6375, 5250, },
4023 { 6500, 5375, },
4024 { 6625, 5500, },
4025 { 6750, 5625, },
4026 { 6875, 5750, },
4027 { 7000, 5875, },
4028 { 7125, 6000, },
4029 { 7250, 6125, },
4030 { 7375, 6250, },
4031 { 7500, 6375, },
4032 { 7625, 6500, },
4033 { 7750, 6625, },
4034 { 7875, 6750, },
4035 { 8000, 6875, },
4036 { 8125, 7000, },
4037 { 8250, 7125, },
4038 { 8375, 7250, },
4039 { 8500, 7375, },
4040 { 8625, 7500, },
4041 { 8750, 7625, },
4042 { 8875, 7750, },
4043 { 9000, 7875, },
4044 { 9125, 8000, },
4045 { 9250, 8125, },
4046 { 9375, 8250, },
4047 { 9500, 8375, },
4048 { 9625, 8500, },
4049 { 9750, 8625, },
4050 { 9875, 8750, },
4051 { 10000, 8875, },
4052 { 10125, 9000, },
4053 { 10250, 9125, },
4054 { 10375, 9250, },
4055 { 10500, 9375, },
4056 { 10625, 9500, },
4057 { 10750, 9625, },
4058 { 10875, 9750, },
4059 { 11000, 9875, },
4060 { 11125, 10000, },
4061 { 11250, 10125, },
4062 { 11375, 10250, },
4063 { 11500, 10375, },
4064 { 11625, 10500, },
4065 { 11750, 10625, },
4066 { 11875, 10750, },
4067 { 12000, 10875, },
4068 { 12125, 11000, },
4069 { 12250, 11125, },
4070 { 12375, 11250, },
4071 { 12500, 11375, },
4072 { 12625, 11500, },
4073 { 12750, 11625, },
4074 { 12875, 11750, },
4075 { 13000, 11875, },
4076 { 13125, 12000, },
4077 { 13250, 12125, },
4078 { 13375, 12250, },
4079 { 13500, 12375, },
4080 { 13625, 12500, },
4081 { 13750, 12625, },
4082 { 13875, 12750, },
4083 { 14000, 12875, },
4084 { 14125, 13000, },
4085 { 14250, 13125, },
4086 { 14375, 13250, },
4087 { 14500, 13375, },
4088 { 14625, 13500, },
4089 { 14750, 13625, },
4090 { 14875, 13750, },
4091 { 15000, 13875, },
4092 { 15125, 14000, },
4093 { 15250, 14125, },
4094 { 15375, 14250, },
4095 { 15500, 14375, },
4096 { 15625, 14500, },
4097 { 15750, 14625, },
4098 { 15875, 14750, },
4099 { 16000, 14875, },
4100 { 16125, 15000, },
4101 };
4102 if (dev_priv->info->is_mobile)
4103 return v_table[pxvid].vm;
4104 else
4105 return v_table[pxvid].vd;
4106}
4107
02d71956 4108static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4109{
4110 struct timespec now, diff1;
4111 u64 diff;
4112 unsigned long diffms;
4113 u32 count;
4114
02d71956 4115 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 4116
4117 getrawmonotonic(&now);
20e4d407 4118 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 4119
4120 /* Don't divide by 0 */
4121 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
4122 if (!diffms)
4123 return;
4124
4125 count = I915_READ(GFXEC);
4126
20e4d407
DV		 4127 if (count < dev_priv->ips.last_count2) {
4128 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 4129 diff += count;
4130 } else {
20e4d407 4131 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 4132 }
4133
20e4d407
DV		 4134 dev_priv->ips.last_count2 = count;
4135 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 4136
4137 /* More magic constants... */
4138 diff = diff * 1181;
4139 diff = div_u64(diff, diffms * 10);
20e4d407 4140 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 4141}
4142
02d71956
DV		 4143void i915_update_gfx_val(struct drm_i915_private *dev_priv)
4144{
4145 if (dev_priv->info->gen != 5)
4146 return;
4147
9270388e 4148 spin_lock_irq(&mchdev_lock);
02d71956
DV		 4149
4150 __i915_update_gfx_val(dev_priv);
4151
9270388e 4152 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 4153}
4154
f531dcb2 4155static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 4156{
4157 unsigned long t, corr, state1, corr2, state2;
4158 u32 pxvid, ext_v;
4159
02d71956
DV		 4160 assert_spin_locked(&mchdev_lock);
4161
c6a828d3 4162 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 4163 pxvid = (pxvid >> 24) & 0x7f;
4164 ext_v = pvid_to_extvid(dev_priv, pxvid);
4165
4166 state1 = ext_v;
4167
4168 t = i915_mch_val(dev_priv);
4169
4170 /* Revel in the empirically derived constants */
4171
4172 /* Correction factor in 1/100000 units */
4173 if (t > 80)
4174 corr = ((t * 2349) + 135940);
4175 else if (t >= 50)
4176 corr = ((t * 964) + 29317);
4177 else /* < 50 */
4178 corr = ((t * 301) + 1004);
4179
4180 corr = corr * ((150142 * state1) / 10000 - 78642);
4181 corr /= 100000;
20e4d407 4182 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 4183
4184 state2 = (corr2 * state1) / 10000;
4185 state2 /= 100; /* convert to mW */
4186
02d71956 4187 __i915_update_gfx_val(dev_priv);
eb48eb00 4188
20e4d407 4189 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 4190}
4191
f531dcb2
CW		 4192unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
4193{
4194 unsigned long val;
4195
4196 if (dev_priv->info->gen != 5)
4197 return 0;
4198
4199 spin_lock_irq(&mchdev_lock);
4200
4201 val = __i915_gfx_val(dev_priv);
4202
4203 spin_unlock_irq(&mchdev_lock);
4204
4205 return val;
4206}
4207
eb48eb00
DV		 4208/**
4209 * i915_read_mch_val - return value for IPS use
4210 *
4211 * Calculate and return a value for the IPS driver to use when deciding whether
4212 * we have thermal and power headroom to increase CPU or GPU power budget.
4213 */
4214unsigned long i915_read_mch_val(void)
4215{
4216 struct drm_i915_private *dev_priv;
4217 unsigned long chipset_val, graphics_val, ret = 0;
4218
9270388e 4219 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4220 if (!i915_mch_dev)
4221 goto out_unlock;
4222 dev_priv = i915_mch_dev;
4223
f531dcb2
CW		 4224 chipset_val = __i915_chipset_val(dev_priv);
4225 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 4226
4227 ret = chipset_val + graphics_val;
4228
4229out_unlock:
9270388e 4230 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4231
4232 return ret;
4233}
4234EXPORT_SYMBOL_GPL(i915_read_mch_val);
4235
4236/**
4237 * i915_gpu_raise - raise GPU frequency limit
4238 *
4239 * Raise the limit; IPS indicates we have thermal headroom.
4240 */
4241bool i915_gpu_raise(void)
4242{
4243 struct drm_i915_private *dev_priv;
4244 bool ret = true;
4245
9270388e 4246 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4247 if (!i915_mch_dev) {
4248 ret = false;
4249 goto out_unlock;
4250 }
4251 dev_priv = i915_mch_dev;
4252
20e4d407
DV		 4253 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
4254 dev_priv->ips.max_delay--;
eb48eb00
DV		 4255
4256out_unlock:
9270388e 4257 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4258
4259 return ret;
4260}
4261EXPORT_SYMBOL_GPL(i915_gpu_raise);
4262
4263/**
4264 * i915_gpu_lower - lower GPU frequency limit
4265 *
4266 * IPS indicates we're close to a thermal limit, so throttle back the GPU
4267 * frequency maximum.
4268 */
4269bool i915_gpu_lower(void)
4270{
4271 struct drm_i915_private *dev_priv;
4272 bool ret = true;
4273
9270388e 4274 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4275 if (!i915_mch_dev) {
4276 ret = false;
4277 goto out_unlock;
4278 }
4279 dev_priv = i915_mch_dev;
4280
20e4d407
DV		 4281 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
4282 dev_priv->ips.max_delay++;
eb48eb00
DV		 4283
4284out_unlock:
9270388e 4285 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4286
4287 return ret;
4288}
4289EXPORT_SYMBOL_GPL(i915_gpu_lower);
4290
4291/**
4292 * i915_gpu_busy - indicate GPU business to IPS
4293 *
4294 * Tell the IPS driver whether or not the GPU is busy.
4295 */
4296bool i915_gpu_busy(void)
4297{
4298 struct drm_i915_private *dev_priv;
f047e395 4299 struct intel_ring_buffer *ring;
eb48eb00 4300 bool ret = false;
f047e395 4301 int i;
eb48eb00 4302
9270388e 4303 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4304 if (!i915_mch_dev)
4305 goto out_unlock;
4306 dev_priv = i915_mch_dev;
4307
f047e395
CW		 4308 for_each_ring(ring, dev_priv, i)
4309 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 4310
4311out_unlock:
9270388e 4312 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4313
4314 return ret;
4315}
4316EXPORT_SYMBOL_GPL(i915_gpu_busy);
4317
4318/**
4319 * i915_gpu_turbo_disable - disable graphics turbo
4320 *
4321 * Disable graphics turbo by resetting the max frequency and setting the
4322 * current frequency to the default.
4323 */
4324bool i915_gpu_turbo_disable(void)
4325{
4326 struct drm_i915_private *dev_priv;
4327 bool ret = true;
4328
9270388e 4329 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 4330 if (!i915_mch_dev) {
4331 ret = false;
4332 goto out_unlock;
4333 }
4334 dev_priv = i915_mch_dev;
4335
20e4d407 4336 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 4337
20e4d407 4338 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 4339 ret = false;
4340
4341out_unlock:
9270388e 4342 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4343
4344 return ret;
4345}
4346EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
4347
4348/**
4349 * Tells the intel_ips driver that the i915 driver is now loaded, if
4350 * IPS got loaded first.
4351 *
4352 * This awkward dance is so that neither module has to depend on the
4353 * other in order for IPS to do the appropriate communication of
4354 * GPU turbo limits to i915.
4355 */
4356static void
4357ips_ping_for_i915_load(void)
4358{
4359 void (*link)(void);
4360
4361 link = symbol_get(ips_link_to_i915_driver);
4362 if (link) {
4363 link();
4364 symbol_put(ips_link_to_i915_driver);
4365 }
4366}
4367
4368void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
4369{
02d71956
DV		 4370 /* We only register the i915 ips part with intel-ips once everything is
4371 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 4372 spin_lock_irq(&mchdev_lock);
eb48eb00 4373 i915_mch_dev = dev_priv;
9270388e 4374 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 4375
4376 ips_ping_for_i915_load();
4377}
4378
4379void intel_gpu_ips_teardown(void)
4380{
9270388e 4381 spin_lock_irq(&mchdev_lock);
eb48eb00 4382 i915_mch_dev = NULL;
9270388e 4383 spin_unlock_irq(&mchdev_lock);
eb48eb00 4384}
8090c6b9 4385static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 4386{
4387 struct drm_i915_private *dev_priv = dev->dev_private;
4388 u32 lcfuse;
4389 u8 pxw[16];
4390 int i;
4391
4392 /* Disable to program */
4393 I915_WRITE(ECR, 0);
4394 POSTING_READ(ECR);
4395
4396 /* Program energy weights for various events */
4397 I915_WRITE(SDEW, 0x15040d00);
4398 I915_WRITE(CSIEW0, 0x007f0000);
4399 I915_WRITE(CSIEW1, 0x1e220004);
4400 I915_WRITE(CSIEW2, 0x04000004);
4401
4402 for (i = 0; i < 5; i++)
4403 I915_WRITE(PEW + (i * 4), 0);
4404 for (i = 0; i < 3; i++)
4405 I915_WRITE(DEW + (i * 4), 0);
4406
4407 /* Program P-state weights to account for frequency power adjustment */
4408 for (i = 0; i < 16; i++) {
4409 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
4410 unsigned long freq = intel_pxfreq(pxvidfreq);
4411 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
4412 PXVFREQ_PX_SHIFT;
4413 unsigned long val;
4414
4415 val = vid * vid;
4416 val *= (freq / 1000);
4417 val *= 255;
4418 val /= (127*127*900);
4419 if (val > 0xff)
4420 DRM_ERROR("bad pxval: %ld\n", val);
4421 pxw[i] = val;
4422 }
4423 /* Render standby states get 0 weight */
4424 pxw[14] = 0;
4425 pxw[15] = 0;
4426
4427 for (i = 0; i < 4; i++) {
4428 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
4429 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
4430 I915_WRITE(PXW + (i * 4), val);
4431 }
4432
4433 /* Adjust magic regs to magic values (more experimental results) */
4434 I915_WRITE(OGW0, 0);
4435 I915_WRITE(OGW1, 0);
4436 I915_WRITE(EG0, 0x00007f00);
4437 I915_WRITE(EG1, 0x0000000e);
4438 I915_WRITE(EG2, 0x000e0000);
4439 I915_WRITE(EG3, 0x68000300);
4440 I915_WRITE(EG4, 0x42000000);
4441 I915_WRITE(EG5, 0x00140031);
4442 I915_WRITE(EG6, 0);
4443 I915_WRITE(EG7, 0);
4444
4445 for (i = 0; i < 8; i++)
4446 I915_WRITE(PXWL + (i * 4), 0);
4447
4448 /* Enable PMON + select events */
4449 I915_WRITE(ECR, 0x80000019);
4450
4451 lcfuse = I915_READ(LCFUSE02);
4452
20e4d407 4453 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 4454}
4455
8090c6b9
DV		 4456void intel_disable_gt_powersave(struct drm_device *dev)
4457{
1a01ab3b
JB		 4458 struct drm_i915_private *dev_priv = dev->dev_private;
4459
fd0c0642
DV		 4460 /* Interrupts should be disabled already to avoid re-arming. */
4461 WARN_ON(dev->irq_enabled);
4462
930ebb46 4463 if (IS_IRONLAKE_M(dev)) {
8090c6b9 4464 ironlake_disable_drps(dev);
930ebb46 4465 ironlake_disable_rc6(dev);
0a073b84 4466 } else if (INTEL_INFO(dev)->gen >= 6) {
1a01ab3b 4467 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
250848ca 4468 cancel_work_sync(&dev_priv->rps.work);
52ceb908
JB		 4469 if (IS_VALLEYVIEW(dev))
4470 cancel_delayed_work_sync(&dev_priv->rps.vlv_work);
4fc688ce 4471 mutex_lock(&dev_priv->rps.hw_lock);
d20d4f0c
JB		 4472 if (IS_VALLEYVIEW(dev))
4473 valleyview_disable_rps(dev);
4474 else
4475 gen6_disable_rps(dev);
4fc688ce 4476 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 4477 }
8090c6b9
DV		 4478}
4479
1a01ab3b
JB		 4480static void intel_gen6_powersave_work(struct work_struct *work)
4481{
4482 struct drm_i915_private *dev_priv =
4483 container_of(work, struct drm_i915_private,
4484 rps.delayed_resume_work.work);
4485 struct drm_device *dev = dev_priv->dev;
4486
4fc688ce 4487 mutex_lock(&dev_priv->rps.hw_lock);
0a073b84
JB		 4488
4489 if (IS_VALLEYVIEW(dev)) {
4490 valleyview_enable_rps(dev);
4491 } else {
4492 gen6_enable_rps(dev);
4493 gen6_update_ring_freq(dev);
4494 }
4fc688ce 4495 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 4496}
4497
8090c6b9
DV		 4498void intel_enable_gt_powersave(struct drm_device *dev)
4499{
1a01ab3b
JB		 4500 struct drm_i915_private *dev_priv = dev->dev_private;
4501
8090c6b9
DV		 4502 if (IS_IRONLAKE_M(dev)) {
4503 ironlake_enable_drps(dev);
4504 ironlake_enable_rc6(dev);
4505 intel_init_emon(dev);
0a073b84 4506 } else if (IS_GEN6(dev) || IS_GEN7(dev)) {
1a01ab3b
JB		 4507 /*
4508 * PCU communication is slow and this doesn't need to be
4509 * done at any specific time, so do this out of our fast path
4510 * to make resume and init faster.
4511 */
4512 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
4513 round_jiffies_up_relative(HZ));
8090c6b9
DV		 4514 }
4515}
4516
3107bd48
DV		 4517static void ibx_init_clock_gating(struct drm_device *dev)
4518{
4519 struct drm_i915_private *dev_priv = dev->dev_private;
4520
4521 /*
4522 * On Ibex Peak and Cougar Point, we need to disable clock
4523 * gating for the panel power sequencer or it will fail to
4524 * start up when no ports are active.
4525 */
4526 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4527}
4528
0e088b8f
VS		 4529static void g4x_disable_trickle_feed(struct drm_device *dev)
4530{
4531 struct drm_i915_private *dev_priv = dev->dev_private;
4532 int pipe;
4533
4534 for_each_pipe(pipe) {
4535 I915_WRITE(DSPCNTR(pipe),
4536 I915_READ(DSPCNTR(pipe)) |
4537 DISPPLANE_TRICKLE_FEED_DISABLE);
4538 intel_flush_display_plane(dev_priv, pipe);
4539 }
4540}
4541
1fa61106 4542static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4543{
4544 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4545 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4546
f1e8fa56
DL		 4547 /*
4548 * Required for FBC
4549 * WaFbcDisableDpfcClockGating:ilk
4550 */
4d47e4f5
DL		 4551 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
4552 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
4553 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4554
4555 I915_WRITE(PCH_3DCGDIS0,
4556 MARIUNIT_CLOCK_GATE_DISABLE |
4557 SVSMUNIT_CLOCK_GATE_DISABLE);
4558 I915_WRITE(PCH_3DCGDIS1,
4559 VFMUNIT_CLOCK_GATE_DISABLE);
4560
6f1d69b0
ED		 4561 /*
4562 * According to the spec the following bits should be set in
4563 * order to enable memory self-refresh
4564 * The bit 22/21 of 0x42004
4565 * The bit 5 of 0x42020
4566 * The bit 15 of 0x45000
4567 */
4568 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4569 (I915_READ(ILK_DISPLAY_CHICKEN2) |
4570 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 4571 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 4572 I915_WRITE(DISP_ARB_CTL,
4573 (I915_READ(DISP_ARB_CTL) |
4574 DISP_FBC_WM_DIS));
4575 I915_WRITE(WM3_LP_ILK, 0);
4576 I915_WRITE(WM2_LP_ILK, 0);
4577 I915_WRITE(WM1_LP_ILK, 0);
4578
4579 /*
4580 * Based on the document from hardware guys the following bits
4581 * should be set unconditionally in order to enable FBC.
4582 * The bit 22 of 0x42000
4583 * The bit 22 of 0x42004
4584 * The bit 7,8,9 of 0x42020.
4585 */
4586 if (IS_IRONLAKE_M(dev)) {
4bb35334 4587 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 4588 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4589 I915_READ(ILK_DISPLAY_CHICKEN1) |
4590 ILK_FBCQ_DIS);
4591 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4592 I915_READ(ILK_DISPLAY_CHICKEN2) |
4593 ILK_DPARB_GATE);
6f1d69b0
ED		 4594 }
4595
4d47e4f5
DL		 4596 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
4597
6f1d69b0
ED		 4598 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4599 I915_READ(ILK_DISPLAY_CHICKEN2) |
4600 ILK_ELPIN_409_SELECT);
4601 I915_WRITE(_3D_CHICKEN2,
4602 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
4603 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 4604
ecdb4eb7 4605 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 4606 I915_WRITE(CACHE_MODE_0,
4607 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 4608
0e088b8f 4609 g4x_disable_trickle_feed(dev);
bdad2b2f 4610
3107bd48
DV		 4611 ibx_init_clock_gating(dev);
4612}
4613
4614static void cpt_init_clock_gating(struct drm_device *dev)
4615{
4616 struct drm_i915_private *dev_priv = dev->dev_private;
4617 int pipe;
3f704fa2 4618 uint32_t val;
3107bd48
DV		 4619
4620 /*
4621 * On Ibex Peak and Cougar Point, we need to disable clock
4622 * gating for the panel power sequencer or it will fail to
4623 * start up when no ports are active.
4624 */
4625 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
4626 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
4627 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 4628 /* The below fixes the weird display corruption, a few pixels shifted
4629 * downward, on (only) LVDS of some HP laptops with IVY.
4630 */
3f704fa2 4631 for_each_pipe(pipe) {
dc4bd2d1
PZ		 4632 val = I915_READ(TRANS_CHICKEN2(pipe));
4633 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
4634 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 4635 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 4636 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 4637 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
4638 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
4639 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 4640 I915_WRITE(TRANS_CHICKEN2(pipe), val);
4641 }
3107bd48
DV		 4642 /* WADP0ClockGatingDisable */
4643 for_each_pipe(pipe) {
4644 I915_WRITE(TRANS_CHICKEN1(pipe),
4645 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
4646 }
6f1d69b0
ED		 4647}
4648
1d7aaa0c
DV		 4649static void gen6_check_mch_setup(struct drm_device *dev)
4650{
4651 struct drm_i915_private *dev_priv = dev->dev_private;
4652 uint32_t tmp;
4653
4654 tmp = I915_READ(MCH_SSKPD);
4655 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
4656 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
4657 DRM_INFO("This can cause pipe underruns and display issues.\n");
4658 DRM_INFO("Please upgrade your BIOS to fix this.\n");
4659 }
4660}
4661
1fa61106 4662static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4663{
4664 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 4665 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 4666
231e54f6 4667 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 4668
4669 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4670 I915_READ(ILK_DISPLAY_CHICKEN2) |
4671 ILK_ELPIN_409_SELECT);
4672
ecdb4eb7 4673 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 4674 I915_WRITE(_3D_CHICKEN,
4675 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
4676
ecdb4eb7 4677 /* WaSetupGtModeTdRowDispatch:snb */
6547fbdb
DV		 4678 if (IS_SNB_GT1(dev))
4679 I915_WRITE(GEN6_GT_MODE,
4680 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
4681
6f1d69b0
ED		 4682 I915_WRITE(WM3_LP_ILK, 0);
4683 I915_WRITE(WM2_LP_ILK, 0);
4684 I915_WRITE(WM1_LP_ILK, 0);
4685
6f1d69b0 4686 I915_WRITE(CACHE_MODE_0,
50743298 4687 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 4688
4689 I915_WRITE(GEN6_UCGCTL1,
4690 I915_READ(GEN6_UCGCTL1) |
4691 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
4692 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
4693
4694 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4695 * gating disable must be set. Failure to set it results in
4696 * flickering pixels due to Z write ordering failures after
4697 * some amount of runtime in the Mesa "fire" demo, and Unigine
4698 * Sanctuary and Tropics, and apparently anything else with
4699 * alpha test or pixel discard.
4700 *
4701 * According to the spec, bit 11 (RCCUNIT) must also be set,
4702 * but we didn't debug actual testcases to find it out.
0f846f81 4703 *
ecdb4eb7
DL		 4704 * Also apply WaDisableVDSUnitClockGating:snb and
4705 * WaDisableRCPBUnitClockGating:snb.
6f1d69b0
ED		 4706 */
4707 I915_WRITE(GEN6_UCGCTL2,
0f846f81 4708 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 4709 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
4710 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4711
4712 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 4713 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
4714 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 4715
4716 /*
4717 * According to the spec the following bits should be
4718 * set in order to enable memory self-refresh and fbc:
4719 * The bit21 and bit22 of 0x42000
4720 * The bit21 and bit22 of 0x42004
4721 * The bit5 and bit7 of 0x42020
4722 * The bit14 of 0x70180
4723 * The bit14 of 0x71180
4bb35334
DL		 4724 *
4725 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 4726 */
4727 I915_WRITE(ILK_DISPLAY_CHICKEN1,
4728 I915_READ(ILK_DISPLAY_CHICKEN1) |
4729 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
4730 I915_WRITE(ILK_DISPLAY_CHICKEN2,
4731 I915_READ(ILK_DISPLAY_CHICKEN2) |
4732 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 4733 I915_WRITE(ILK_DSPCLK_GATE_D,
4734 I915_READ(ILK_DSPCLK_GATE_D) |
4735 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
4736 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 4737
ecdb4eb7 4738 /* WaMbcDriverBootEnable:snb */
b4ae3f22
JB		 4739 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4740 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4741
0e088b8f 4742 g4x_disable_trickle_feed(dev);
f8f2ac9a
BW		 4743
4744 /* The default value should be 0x200 according to docs, but the two
4745 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
4746 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
4747 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 4748
4749 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4750
4751 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4752}
4753
4754static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
4755{
4756 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
4757
4758 reg &= ~GEN7_FF_SCHED_MASK;
4759 reg |= GEN7_FF_TS_SCHED_HW;
4760 reg |= GEN7_FF_VS_SCHED_HW;
4761 reg |= GEN7_FF_DS_SCHED_HW;
4762
41c0b3a8
BW		 4763 if (IS_HASWELL(dev_priv->dev))
4764 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
4765
6f1d69b0
ED		 4766 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
4767}
4768
17a303ec
PZ		 4769static void lpt_init_clock_gating(struct drm_device *dev)
4770{
4771 struct drm_i915_private *dev_priv = dev->dev_private;
4772
4773 /*
4774 * TODO: this bit should only be enabled when really needed, then
4775 * disabled when not needed anymore in order to save power.
4776 */
4777 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
4778 I915_WRITE(SOUTH_DSPCLK_GATE_D,
4779 I915_READ(SOUTH_DSPCLK_GATE_D) |
4780 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 4781
4782 /* WADPOClockGatingDisable:hsw */
4783 I915_WRITE(_TRANSA_CHICKEN1,
4784 I915_READ(_TRANSA_CHICKEN1) |
4785 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 4786}
4787
7d708ee4
ID		 4788static void lpt_suspend_hw(struct drm_device *dev)
4789{
4790 struct drm_i915_private *dev_priv = dev->dev_private;
4791
4792 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE) {
4793 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
4794
4795 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
4796 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
4797 }
4798}
4799
cad2a2d7
ED		 4800static void haswell_init_clock_gating(struct drm_device *dev)
4801{
4802 struct drm_i915_private *dev_priv = dev->dev_private;
cad2a2d7
ED		 4803
4804 I915_WRITE(WM3_LP_ILK, 0);
4805 I915_WRITE(WM2_LP_ILK, 0);
4806 I915_WRITE(WM1_LP_ILK, 0);
4807
4808 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4809 * This implements the WaDisableRCZUnitClockGating:hsw workaround.
cad2a2d7
ED		 4810 */
4811 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
4812
ecdb4eb7 4813 /* Apply the WaDisableRHWOOptimizationForRenderHang:hsw workaround. */
cad2a2d7
ED		 4814 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4815 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4816
ecdb4eb7 4817 /* WaApplyL3ControlAndL3ChickenMode:hsw */
cad2a2d7
ED		 4818 I915_WRITE(GEN7_L3CNTLREG1,
4819 GEN7_WA_FOR_GEN7_L3_CONTROL);
4820 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
4821 GEN7_WA_L3_CHICKEN_MODE);
4822
ecdb4eb7 4823 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 4824 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4825 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4826 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4827
0e088b8f 4828 g4x_disable_trickle_feed(dev);
cad2a2d7 4829
ecdb4eb7 4830 /* WaVSRefCountFullforceMissDisable:hsw */
cad2a2d7
ED		 4831 gen7_setup_fixed_func_scheduler(dev_priv);
4832
ecdb4eb7 4833 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 4834 I915_WRITE(CACHE_MODE_1,
4835 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 4836
ecdb4eb7 4837 /* WaMbcDriverBootEnable:hsw */
b3bf0766
PZ		 4838 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4839 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4840
ecdb4eb7 4841 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 4842 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
4843
90a88643
PZ		 4844 /* WaRsPkgCStateDisplayPMReq:hsw */
4845 I915_WRITE(CHICKEN_PAR1_1,
4846 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 4847
17a303ec 4848 lpt_init_clock_gating(dev);
cad2a2d7
ED		 4849}
4850
1fa61106 4851static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4852{
4853 struct drm_i915_private *dev_priv = dev->dev_private;
20848223 4854 uint32_t snpcr;
6f1d69b0 4855
6f1d69b0
ED		 4856 I915_WRITE(WM3_LP_ILK, 0);
4857 I915_WRITE(WM2_LP_ILK, 0);
4858 I915_WRITE(WM1_LP_ILK, 0);
4859
231e54f6 4860 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4861
ecdb4eb7 4862 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 4863 I915_WRITE(_3D_CHICKEN3,
4864 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4865
ecdb4eb7 4866 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 4867 I915_WRITE(IVB_CHICKEN3,
4868 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4869 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4870
ecdb4eb7 4871 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 4872 if (IS_IVB_GT1(dev))
4873 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
4874 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4875 else
4876 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
4877 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
4878
ecdb4eb7 4879 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 4880 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4881 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4882
ecdb4eb7 4883 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 4884 I915_WRITE(GEN7_L3CNTLREG1,
4885 GEN7_WA_FOR_GEN7_L3_CONTROL);
4886 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 4887 GEN7_WA_L3_CHICKEN_MODE);
4888 if (IS_IVB_GT1(dev))
4889 I915_WRITE(GEN7_ROW_CHICKEN2,
4890 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4891 else
4892 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
4893 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4894
6f1d69b0 4895
ecdb4eb7 4896 /* WaForceL3Serialization:ivb */
61939d97
JB		 4897 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4898 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4899
0f846f81
JB		 4900 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4901 * gating disable must be set. Failure to set it results in
4902 * flickering pixels due to Z write ordering failures after
4903 * some amount of runtime in the Mesa "fire" demo, and Unigine
4904 * Sanctuary and Tropics, and apparently anything else with
4905 * alpha test or pixel discard.
4906 *
4907 * According to the spec, bit 11 (RCCUNIT) must also be set,
4908 * but we didn't debug actual testcases to find it out.
4909 *
4910 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 4911 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 4912 */
4913 I915_WRITE(GEN6_UCGCTL2,
4914 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
4915 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
4916
ecdb4eb7 4917 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 4918 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4919 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4920 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4921
0e088b8f 4922 g4x_disable_trickle_feed(dev);
6f1d69b0 4923
ecdb4eb7 4924 /* WaMbcDriverBootEnable:ivb */
b4ae3f22
JB		 4925 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4926 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4927
ecdb4eb7 4928 /* WaVSRefCountFullforceMissDisable:ivb */
6f1d69b0 4929 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 4930
ecdb4eb7 4931 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 4932 I915_WRITE(CACHE_MODE_1,
4933 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 4934
4935 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
4936 snpcr &= ~GEN6_MBC_SNPCR_MASK;
4937 snpcr |= GEN6_MBC_SNPCR_MED;
4938 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 4939
ab5c608b
BW		 4940 if (!HAS_PCH_NOP(dev))
4941 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 4942
4943 gen6_check_mch_setup(dev);
6f1d69b0
ED		 4944}
4945
1fa61106 4946static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4947{
4948 struct drm_i915_private *dev_priv = dev->dev_private;
6f1d69b0 4949
d7fe0cc0 4950 I915_WRITE(DSPCLK_GATE_D, VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 4951
ecdb4eb7 4952 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 4953 I915_WRITE(_3D_CHICKEN3,
4954 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
4955
ecdb4eb7 4956 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 4957 I915_WRITE(IVB_CHICKEN3,
4958 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
4959 CHICKEN3_DGMG_DONE_FIX_DISABLE);
4960
ecdb4eb7 4961 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 4962 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 4963 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
4964 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 4965
ecdb4eb7 4966 /* Apply the WaDisableRHWOOptimizationForRenderHang:vlv workaround. */
6f1d69b0
ED		 4967 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
4968 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
4969
ecdb4eb7 4970 /* WaApplyL3ControlAndL3ChickenMode:vlv */
d0cf5ead 4971 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 4972 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
4973
ecdb4eb7 4974 /* WaForceL3Serialization:vlv */
61939d97
JB		 4975 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
4976 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
4977
ecdb4eb7 4978 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 4979 I915_WRITE(GEN7_ROW_CHICKEN2,
4980 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
4981
ecdb4eb7 4982 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 4983 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
4984 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
4985 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
4986
ecdb4eb7 4987 /* WaMbcDriverBootEnable:vlv */
b4ae3f22
JB		 4988 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
4989 GEN6_MBCTL_ENABLE_BOOT_FETCH);
4990
0f846f81
JB		 4991
4992 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
4993 * gating disable must be set. Failure to set it results in
4994 * flickering pixels due to Z write ordering failures after
4995 * some amount of runtime in the Mesa "fire" demo, and Unigine
4996 * Sanctuary and Tropics, and apparently anything else with
4997 * alpha test or pixel discard.
4998 *
4999 * According to the spec, bit 11 (RCCUNIT) must also be set,
5000 * but we didn't debug actual testcases to find it out.
5001 *
5002 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 5003 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81 5004 *
ecdb4eb7
DL		 5005 * Also apply WaDisableVDSUnitClockGating:vlv and
5006 * WaDisableRCPBUnitClockGating:vlv.
0f846f81
JB		 5007 */
5008 I915_WRITE(GEN6_UCGCTL2,
5009 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 5010 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 5011 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
5012 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
5013 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
5014
e3f33d46
JB		 5015 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
5016
e0d8d59b 5017 I915_WRITE(MI_ARB_VLV, MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
6f1d69b0 5018
6b26c86d
DV		 5019 I915_WRITE(CACHE_MODE_1,
5020 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 5021
2d809570 5022 /*
ecdb4eb7 5023 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 5024 * Disable clock gating on th GCFG unit to prevent a delay
5025 * in the reporting of vblank events.
5026 */
4e8c84a5
JB		 5027 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
5028
5029 /* Conservative clock gating settings for now */
5030 I915_WRITE(0x9400, 0xffffffff);
5031 I915_WRITE(0x9404, 0xffffffff);
5032 I915_WRITE(0x9408, 0xffffffff);
5033 I915_WRITE(0x940c, 0xffffffff);
5034 I915_WRITE(0x9410, 0xffffffff);
5035 I915_WRITE(0x9414, 0xffffffff);
5036 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 5037}
5038
1fa61106 5039static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5040{
5041 struct drm_i915_private *dev_priv = dev->dev_private;
5042 uint32_t dspclk_gate;
5043
5044 I915_WRITE(RENCLK_GATE_D1, 0);
5045 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
5046 GS_UNIT_CLOCK_GATE_DISABLE |
5047 CL_UNIT_CLOCK_GATE_DISABLE);
5048 I915_WRITE(RAMCLK_GATE_D, 0);
5049 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
5050 OVRUNIT_CLOCK_GATE_DISABLE |
5051 OVCUNIT_CLOCK_GATE_DISABLE;
5052 if (IS_GM45(dev))
5053 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
5054 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 5055
5056 /* WaDisableRenderCachePipelinedFlush */
5057 I915_WRITE(CACHE_MODE_0,
5058 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 5059
0e088b8f 5060 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 5061}
5062
1fa61106 5063static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5064{
5065 struct drm_i915_private *dev_priv = dev->dev_private;
5066
5067 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
5068 I915_WRITE(RENCLK_GATE_D2, 0);
5069 I915_WRITE(DSPCLK_GATE_D, 0);
5070 I915_WRITE(RAMCLK_GATE_D, 0);
5071 I915_WRITE16(DEUC, 0);
20f94967
VS		 5072 I915_WRITE(MI_ARB_STATE,
5073 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5074}
5075
1fa61106 5076static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5077{
5078 struct drm_i915_private *dev_priv = dev->dev_private;
5079
5080 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
5081 I965_RCC_CLOCK_GATE_DISABLE |
5082 I965_RCPB_CLOCK_GATE_DISABLE |
5083 I965_ISC_CLOCK_GATE_DISABLE |
5084 I965_FBC_CLOCK_GATE_DISABLE);
5085 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 5086 I915_WRITE(MI_ARB_STATE,
5087 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 5088}
5089
1fa61106 5090static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5091{
5092 struct drm_i915_private *dev_priv = dev->dev_private;
5093 u32 dstate = I915_READ(D_STATE);
5094
5095 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
5096 DSTATE_DOT_CLOCK_GATING;
5097 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 5098
5099 if (IS_PINEVIEW(dev))
5100 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 5101
5102 /* IIR "flip pending" means done if this bit is set */
5103 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 5104}
5105
1fa61106 5106static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5107{
5108 struct drm_i915_private *dev_priv = dev->dev_private;
5109
5110 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
5111}
5112
1fa61106 5113static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 5114{
5115 struct drm_i915_private *dev_priv = dev->dev_private;
5116
5117 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
5118}
5119
6f1d69b0
ED		 5120void intel_init_clock_gating(struct drm_device *dev)
5121{
5122 struct drm_i915_private *dev_priv = dev->dev_private;
5123
5124 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 5125}
5126
7d708ee4
ID		 5127void intel_suspend_hw(struct drm_device *dev)
5128{
5129 if (HAS_PCH_LPT(dev))
5130 lpt_suspend_hw(dev);
5131}
5132
15d199ea
PZ		 5133/**
5134 * We should only use the power well if we explicitly asked the hardware to
5135 * enable it, so check if it's enabled and also check if we've requested it to
5136 * be enabled.
5137 */
b97186f0
PZ		 5138bool intel_display_power_enabled(struct drm_device *dev,
5139 enum intel_display_power_domain domain)
15d199ea
PZ		 5140{
5141 struct drm_i915_private *dev_priv = dev->dev_private;
5142
b97186f0
PZ		 5143 if (!HAS_POWER_WELL(dev))
5144 return true;
5145
5146 switch (domain) {
5147 case POWER_DOMAIN_PIPE_A:
5148 case POWER_DOMAIN_TRANSCODER_EDP:
5149 return true;
5150 case POWER_DOMAIN_PIPE_B:
5151 case POWER_DOMAIN_PIPE_C:
5152 case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
5153 case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
5154 case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
5155 case POWER_DOMAIN_TRANSCODER_A:
5156 case POWER_DOMAIN_TRANSCODER_B:
5157 case POWER_DOMAIN_TRANSCODER_C:
15d199ea
PZ		 5158 return I915_READ(HSW_PWR_WELL_DRIVER) ==
5159 (HSW_PWR_WELL_ENABLE | HSW_PWR_WELL_STATE);
b97186f0
PZ		 5160 default:
5161 BUG();
5162 }
15d199ea
PZ		 5163}
5164
a38911a3 5165static void __intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 5166{
5167 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 5168 bool is_enabled, enable_requested;
5169 uint32_t tmp;
d0d3e513 5170
fa42e23c
PZ		 5171 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
5172 is_enabled = tmp & HSW_PWR_WELL_STATE;
5173 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 5174
fa42e23c
PZ		 5175 if (enable) {
5176 if (!enable_requested)
5177 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 5178
fa42e23c
PZ		 5179 if (!is_enabled) {
5180 DRM_DEBUG_KMS("Enabling power well\n");
5181 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
5182 HSW_PWR_WELL_STATE), 20))
5183 DRM_ERROR("Timeout enabling power well\n");
5184 }
5185 } else {
5186 if (enable_requested) {
5187 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
5188 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 5189 }
5190 }
fa42e23c 5191}
d0d3e513 5192
a38911a3
WX		 5193static struct i915_power_well *hsw_pwr;
5194
5195/* Display audio driver power well request */
5196void i915_request_power_well(void)
5197{
5198 if (WARN_ON(!hsw_pwr))
5199 return;
5200
5201 spin_lock_irq(&hsw_pwr->lock);
5202 if (!hsw_pwr->count++ &&
5203 !hsw_pwr->i915_request)
5204 __intel_set_power_well(hsw_pwr->device, true);
5205 spin_unlock_irq(&hsw_pwr->lock);
5206}
5207EXPORT_SYMBOL_GPL(i915_request_power_well);
5208
5209/* Display audio driver power well release */
5210void i915_release_power_well(void)
5211{
5212 if (WARN_ON(!hsw_pwr))
5213 return;
5214
5215 spin_lock_irq(&hsw_pwr->lock);
5216 WARN_ON(!hsw_pwr->count);
5217 if (!--hsw_pwr->count &&
5218 !hsw_pwr->i915_request)
5219 __intel_set_power_well(hsw_pwr->device, false);
5220 spin_unlock_irq(&hsw_pwr->lock);
5221}
5222EXPORT_SYMBOL_GPL(i915_release_power_well);
5223
5224int i915_init_power_well(struct drm_device *dev)
5225{
5226 struct drm_i915_private *dev_priv = dev->dev_private;
5227
5228 hsw_pwr = &dev_priv->power_well;
5229
5230 hsw_pwr->device = dev;
5231 spin_lock_init(&hsw_pwr->lock);
5232 hsw_pwr->count = 0;
5233
5234 return 0;
5235}
5236
5237void i915_remove_power_well(struct drm_device *dev)
5238{
5239 hsw_pwr = NULL;
5240}
5241
5242void intel_set_power_well(struct drm_device *dev, bool enable)
5243{
5244 struct drm_i915_private *dev_priv = dev->dev_private;
5245 struct i915_power_well *power_well = &dev_priv->power_well;
5246
5247 if (!HAS_POWER_WELL(dev))
5248 return;
5249
5250 if (!i915_disable_power_well && !enable)
5251 return;
5252
5253 spin_lock_irq(&power_well->lock);
5254 power_well->i915_request = enable;
5255
5256 /* only reject "disable" power well request */
5257 if (power_well->count && !enable) {
5258 spin_unlock_irq(&power_well->lock);
5259 return;
5260 }
5261
5262 __intel_set_power_well(dev, enable);
5263 spin_unlock_irq(&power_well->lock);
5264}
5265
fa42e23c
PZ		 5266/*
5267 * Starting with Haswell, we have a "Power Down Well" that can be turned off
5268 * when not needed anymore. We have 4 registers that can request the power well
5269 * to be enabled, and it will only be disabled if none of the registers is
5270 * requesting it to be enabled.
d0d3e513 5271 */
fa42e23c 5272void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 5273{
5274 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 5275
86d52df6 5276 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 5277 return;
5278
fa42e23c
PZ		 5279 /* For now, we need the power well to be always enabled. */
5280 intel_set_power_well(dev, true);
d0d3e513 5281
fa42e23c
PZ		 5282 /* We're taking over the BIOS, so clear any requests made by it since
5283 * the driver is in charge now. */
5284 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
5285 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 5286}
5287
1fa61106
ED		 5288/* Set up chip specific power management-related functions */
5289void intel_init_pm(struct drm_device *dev)
5290{
5291 struct drm_i915_private *dev_priv = dev->dev_private;
5292
5293 if (I915_HAS_FBC(dev)) {
5294 if (HAS_PCH_SPLIT(dev)) {
5295 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
891348b2 5296 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
abe959c7
RV		 5297 dev_priv->display.enable_fbc =
5298 gen7_enable_fbc;
5299 else
5300 dev_priv->display.enable_fbc =
5301 ironlake_enable_fbc;
1fa61106
ED		 5302 dev_priv->display.disable_fbc = ironlake_disable_fbc;
5303 } else if (IS_GM45(dev)) {
5304 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
5305 dev_priv->display.enable_fbc = g4x_enable_fbc;
5306 dev_priv->display.disable_fbc = g4x_disable_fbc;
5307 } else if (IS_CRESTLINE(dev)) {
5308 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
5309 dev_priv->display.enable_fbc = i8xx_enable_fbc;
5310 dev_priv->display.disable_fbc = i8xx_disable_fbc;
5311 }
5312 /* 855GM needs testing */
5313 }
5314
c921aba8
DV		 5315 /* For cxsr */
5316 if (IS_PINEVIEW(dev))
5317 i915_pineview_get_mem_freq(dev);
5318 else if (IS_GEN5(dev))
5319 i915_ironlake_get_mem_freq(dev);
5320
1fa61106
ED		 5321 /* For FIFO watermark updates */
5322 if (HAS_PCH_SPLIT(dev)) {
53615a5e
VS		 5323 intel_setup_wm_latency(dev);
5324
1fa61106 5325 if (IS_GEN5(dev)) {
53615a5e
VS		 5326 if (dev_priv->wm.pri_latency[1] &&
5327 dev_priv->wm.spr_latency[1] &&
5328 dev_priv->wm.cur_latency[1])
1fa61106
ED		 5329 dev_priv->display.update_wm = ironlake_update_wm;
5330 else {
5331 DRM_DEBUG_KMS("Failed to get proper latency. "
5332 "Disable CxSR\n");
5333 dev_priv->display.update_wm = NULL;
5334 }
5335 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
5336 } else if (IS_GEN6(dev)) {
53615a5e
VS		 5337 if (dev_priv->wm.pri_latency[0] &&
5338 dev_priv->wm.spr_latency[0] &&
5339 dev_priv->wm.cur_latency[0]) {
1fa61106
ED		 5340 dev_priv->display.update_wm = sandybridge_update_wm;
5341 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5342 } else {
5343 DRM_DEBUG_KMS("Failed to read display plane latency. "
5344 "Disable CxSR\n");
5345 dev_priv->display.update_wm = NULL;
5346 }
5347 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
5348 } else if (IS_IVYBRIDGE(dev)) {
53615a5e
VS		 5349 if (dev_priv->wm.pri_latency[0] &&
5350 dev_priv->wm.spr_latency[0] &&
5351 dev_priv->wm.cur_latency[0]) {
c43d0188 5352 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 5353 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
5354 } else {
5355 DRM_DEBUG_KMS("Failed to read display plane latency. "
5356 "Disable CxSR\n");
5357 dev_priv->display.update_wm = NULL;
5358 }
5359 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb 5360 } else if (IS_HASWELL(dev)) {
53615a5e
VS		 5361 if (dev_priv->wm.pri_latency[0] &&
5362 dev_priv->wm.spr_latency[0] &&
5363 dev_priv->wm.cur_latency[0]) {
1011d8c4 5364 dev_priv->display.update_wm = haswell_update_wm;
526682e9
PZ		 5365 dev_priv->display.update_sprite_wm =
5366 haswell_update_sprite_wm;
6b8a5eeb
ED		 5367 } else {
5368 DRM_DEBUG_KMS("Failed to read display plane latency. "
5369 "Disable CxSR\n");
5370 dev_priv->display.update_wm = NULL;
5371 }
cad2a2d7 5372 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 5373 } else
5374 dev_priv->display.update_wm = NULL;
5375 } else if (IS_VALLEYVIEW(dev)) {
5376 dev_priv->display.update_wm = valleyview_update_wm;
5377 dev_priv->display.init_clock_gating =
5378 valleyview_init_clock_gating;
1fa61106
ED		 5379 } else if (IS_PINEVIEW(dev)) {
5380 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
5381 dev_priv->is_ddr3,
5382 dev_priv->fsb_freq,
5383 dev_priv->mem_freq)) {
5384 DRM_INFO("failed to find known CxSR latency "
5385 "(found ddr%s fsb freq %d, mem freq %d), "
5386 "disabling CxSR\n",
5387 (dev_priv->is_ddr3 == 1) ? "3" : "2",
5388 dev_priv->fsb_freq, dev_priv->mem_freq);
5389 /* Disable CxSR and never update its watermark again */
5390 pineview_disable_cxsr(dev);
5391 dev_priv->display.update_wm = NULL;
5392 } else
5393 dev_priv->display.update_wm = pineview_update_wm;
5394 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5395 } else if (IS_G4X(dev)) {
5396 dev_priv->display.update_wm = g4x_update_wm;
5397 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
5398 } else if (IS_GEN4(dev)) {
5399 dev_priv->display.update_wm = i965_update_wm;
5400 if (IS_CRESTLINE(dev))
5401 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
5402 else if (IS_BROADWATER(dev))
5403 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
5404 } else if (IS_GEN3(dev)) {
5405 dev_priv->display.update_wm = i9xx_update_wm;
5406 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
5407 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
5408 } else if (IS_I865G(dev)) {
5409 dev_priv->display.update_wm = i830_update_wm;
5410 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5411 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5412 } else if (IS_I85X(dev)) {
5413 dev_priv->display.update_wm = i9xx_update_wm;
5414 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
5415 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
5416 } else {
5417 dev_priv->display.update_wm = i830_update_wm;
5418 dev_priv->display.init_clock_gating = i830_init_clock_gating;
5419 if (IS_845G(dev))
5420 dev_priv->display.get_fifo_size = i845_get_fifo_size;
5421 else
5422 dev_priv->display.get_fifo_size = i830_get_fifo_size;
5423 }
5424}
5425
42c0526c
BW		 5426int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
5427{
4fc688ce 5428 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5429
5430 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5431 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
5432 return -EAGAIN;
5433 }
5434
5435 I915_WRITE(GEN6_PCODE_DATA, *val);
5436 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5437
5438 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5439 500)) {
5440 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
5441 return -ETIMEDOUT;
5442 }
5443
5444 *val = I915_READ(GEN6_PCODE_DATA);
5445 I915_WRITE(GEN6_PCODE_DATA, 0);
5446
5447 return 0;
5448}
5449
5450int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
5451{
4fc688ce 5452 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 5453
5454 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
5455 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
5456 return -EAGAIN;
5457 }
5458
5459 I915_WRITE(GEN6_PCODE_DATA, val);
5460 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
5461
5462 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
5463 500)) {
5464 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
5465 return -ETIMEDOUT;
5466 }
5467
5468 I915_WRITE(GEN6_PCODE_DATA, 0);
5469
5470 return 0;
5471}
a0e4e199 5472
855ba3be
JB		 5473int vlv_gpu_freq(int ddr_freq, int val)
5474{
5475 int mult, base;
5476
5477 switch (ddr_freq) {
5478 case 800:
5479 mult = 20;
5480 base = 120;
5481 break;
5482 case 1066:
5483 mult = 22;
5484 base = 133;
5485 break;
5486 case 1333:
5487 mult = 21;
5488 base = 125;
5489 break;
5490 default:
5491 return -1;
5492 }
5493
5494 return ((val - 0xbd) * mult) + base;
5495}
5496
5497int vlv_freq_opcode(int ddr_freq, int val)
5498{
5499 int mult, base;
5500
5501 switch (ddr_freq) {
5502 case 800:
5503 mult = 20;
5504 base = 120;
5505 break;
5506 case 1066:
5507 mult = 22;
5508 base = 133;
5509 break;
5510 case 1333:
5511 mult = 21;
5512 base = 125;
5513 break;
5514 default:
5515 return -1;
5516 }
5517
5518 val /= mult;
5519 val -= base / mult;
5520 val += 0xbd;
5521
5522 if (val > 0xea)
5523 val = 0xea;
5524
5525 return val;
5526}
5527
907b28c5
CW		 5528void intel_pm_init(struct drm_device *dev)
5529{
5530 struct drm_i915_private *dev_priv = dev->dev_private;
5531
5532 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
5533 intel_gen6_powersave_work);
5534}
5535
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