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drm/i915: Allocate intel_engine_cs structure only for the enabled engines
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
44a655ca
TU		 255static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
256 bool is_ddr3,
b445e3b0
ED		 257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
5209b1f4
ID		 337 } else if (IS_I945G(dev) || IS_I945GM(dev)) {
338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
5209b1f4 342 } else if (IS_I915GM(dev)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
652 dev_priv->fsb_freq, dev_priv->mem_freq);
653 if (!latency) {
654 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 655 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 656 return;
657 }
658
659 crtc = single_enabled_crtc(dev);
660 if (crtc) {
7c5f93b0 661 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 662 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 663 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 664
665 /* Display SR */
666 wm = intel_calculate_wm(clock, &pineview_display_wm,
667 pineview_display_wm.fifo_size,
ac484963 668 cpp, latency->display_sr);
b445e3b0
ED		 669 reg = I915_READ(DSPFW1);
670 reg &= ~DSPFW_SR_MASK;
f4998963 671 reg |= FW_WM(wm, SR);
b445e3b0
ED		 672 I915_WRITE(DSPFW1, reg);
673 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
674
675 /* cursor SR */
676 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
677 pineview_display_wm.fifo_size,
ac484963 678 cpp, latency->cursor_sr);
b445e3b0
ED		 679 reg = I915_READ(DSPFW3);
680 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 681 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 682 I915_WRITE(DSPFW3, reg);
683
684 /* Display HPLL off SR */
685 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
686 pineview_display_hplloff_wm.fifo_size,
ac484963 687 cpp, latency->display_hpll_disable);
b445e3b0
ED		 688 reg = I915_READ(DSPFW3);
689 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 690 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 691 I915_WRITE(DSPFW3, reg);
692
693 /* cursor HPLL off SR */
694 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
695 pineview_display_hplloff_wm.fifo_size,
ac484963 696 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 697 reg = I915_READ(DSPFW3);
698 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 699 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 700 I915_WRITE(DSPFW3, reg);
701 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
702
5209b1f4 703 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 704 } else {
5209b1f4 705 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 706 }
707}
708
709static bool g4x_compute_wm0(struct drm_device *dev,
710 int plane,
711 const struct intel_watermark_params *display,
712 int display_latency_ns,
713 const struct intel_watermark_params *cursor,
714 int cursor_latency_ns,
715 int *plane_wm,
716 int *cursor_wm)
717{
718 struct drm_crtc *crtc;
4fe8590a 719 const struct drm_display_mode *adjusted_mode;
ac484963 720 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 721 int line_time_us, line_count;
722 int entries, tlb_miss;
723
724 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 725 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 726 *cursor_wm = cursor->guard_size;
727 *plane_wm = display->guard_size;
728 return false;
729 }
730
6e3c9717 731 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 732 clock = adjusted_mode->crtc_clock;
fec8cba3 733 htotal = adjusted_mode->crtc_htotal;
6e3c9717 734 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 735 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 736
737 /* Use the small buffer method to calculate plane watermark */
ac484963 738 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 739 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
740 if (tlb_miss > 0)
741 entries += tlb_miss;
742 entries = DIV_ROUND_UP(entries, display->cacheline_size);
743 *plane_wm = entries + display->guard_size;
744 if (*plane_wm > (int)display->max_wm)
745 *plane_wm = display->max_wm;
746
747 /* Use the large buffer method to calculate cursor watermark */
922044c9 748 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 749 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 750 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 751 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
752 if (tlb_miss > 0)
753 entries += tlb_miss;
754 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
755 *cursor_wm = entries + cursor->guard_size;
756 if (*cursor_wm > (int)cursor->max_wm)
757 *cursor_wm = (int)cursor->max_wm;
758
759 return true;
760}
761
762/*
763 * Check the wm result.
764 *
765 * If any calculated watermark values is larger than the maximum value that
766 * can be programmed into the associated watermark register, that watermark
767 * must be disabled.
768 */
769static bool g4x_check_srwm(struct drm_device *dev,
770 int display_wm, int cursor_wm,
771 const struct intel_watermark_params *display,
772 const struct intel_watermark_params *cursor)
773{
774 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
775 display_wm, cursor_wm);
776
777 if (display_wm > display->max_wm) {
ae9400ca 778 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 779 display_wm, display->max_wm);
780 return false;
781 }
782
783 if (cursor_wm > cursor->max_wm) {
ae9400ca 784 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 785 cursor_wm, cursor->max_wm);
786 return false;
787 }
788
789 if (!(display_wm || cursor_wm)) {
790 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
791 return false;
792 }
793
794 return true;
795}
796
797static bool g4x_compute_srwm(struct drm_device *dev,
798 int plane,
799 int latency_ns,
800 const struct intel_watermark_params *display,
801 const struct intel_watermark_params *cursor,
802 int *display_wm, int *cursor_wm)
803{
804 struct drm_crtc *crtc;
4fe8590a 805 const struct drm_display_mode *adjusted_mode;
ac484963 806 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 807 unsigned long line_time_us;
808 int line_count, line_size;
809 int small, large;
810 int entries;
811
812 if (!latency_ns) {
813 *display_wm = *cursor_wm = 0;
814 return false;
815 }
816
817 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 818 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 819 clock = adjusted_mode->crtc_clock;
fec8cba3 820 htotal = adjusted_mode->crtc_htotal;
6e3c9717 821 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 822 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 823
922044c9 824 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 825 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 826 line_size = hdisplay * cpp;
b445e3b0
ED		 827
828 /* Use the minimum of the small and large buffer method for primary */
ac484963 829 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 830 large = line_count * line_size;
831
832 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
833 *display_wm = entries + display->guard_size;
834
835 /* calculate the self-refresh watermark for display cursor */
ac484963 836 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 837 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
838 *cursor_wm = entries + cursor->guard_size;
839
840 return g4x_check_srwm(dev,
841 *display_wm, *cursor_wm,
842 display, cursor);
843}
844
15665979
VS		 845#define FW_WM_VLV(value, plane) \
846 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
847
0018fda1
VS		 848static void vlv_write_wm_values(struct intel_crtc *crtc,
849 const struct vlv_wm_values *wm)
850{
851 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
852 enum pipe pipe = crtc->pipe;
853
854 I915_WRITE(VLV_DDL(pipe),
855 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
856 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
857 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
858 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
859
ae80152d 860 I915_WRITE(DSPFW1,
15665979
VS		 861 FW_WM(wm->sr.plane, SR) |
862 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
863 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
864 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 865 I915_WRITE(DSPFW2,
15665979
VS		 866 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
867 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 869 I915_WRITE(DSPFW3,
15665979 870 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 871
872 if (IS_CHERRYVIEW(dev_priv)) {
873 I915_WRITE(DSPFW7_CHV,
15665979
VS		 874 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
875 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 876 I915_WRITE(DSPFW8_CHV,
15665979
VS		 877 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
878 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 879 I915_WRITE(DSPFW9_CHV,
15665979
VS		 880 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
881 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 882 I915_WRITE(DSPHOWM,
15665979
VS		 883 FW_WM(wm->sr.plane >> 9, SR_HI) |
884 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
885 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
886 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
887 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
888 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
890 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
891 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
892 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 893 } else {
894 I915_WRITE(DSPFW7,
15665979
VS		 895 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
896 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 897 I915_WRITE(DSPHOWM,
15665979
VS		 898 FW_WM(wm->sr.plane >> 9, SR_HI) |
899 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
900 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
901 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
902 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
903 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
904 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 905 }
906
2cb389b7
VS		 907 /* zero (unused) WM1 watermarks */
908 I915_WRITE(DSPFW4, 0);
909 I915_WRITE(DSPFW5, 0);
910 I915_WRITE(DSPFW6, 0);
911 I915_WRITE(DSPHOWM1, 0);
912
ae80152d 913 POSTING_READ(DSPFW1);
0018fda1
VS		 914}
915
15665979
VS		 916#undef FW_WM_VLV
917
6eb1a681
VS		 918enum vlv_wm_level {
919 VLV_WM_LEVEL_PM2,
920 VLV_WM_LEVEL_PM5,
921 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 922};
923
262cd2e1
VS		 924/* latency must be in 0.1us units. */
925static unsigned int vlv_wm_method2(unsigned int pixel_rate,
926 unsigned int pipe_htotal,
927 unsigned int horiz_pixels,
ac484963 928 unsigned int cpp,
262cd2e1
VS		 929 unsigned int latency)
930{
931 unsigned int ret;
932
933 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 934 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 935 ret = DIV_ROUND_UP(ret, 64);
936
937 return ret;
938}
939
940static void vlv_setup_wm_latency(struct drm_device *dev)
941{
fac5e23e 942 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 943
944 /* all latencies in usec */
945 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
946
58590c14
VS		 947 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
948
262cd2e1
VS		 949 if (IS_CHERRYVIEW(dev_priv)) {
950 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
951 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 952
953 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 954 }
955}
956
957static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
958 struct intel_crtc *crtc,
959 const struct intel_plane_state *state,
960 int level)
961{
962 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 963 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 964
965 if (dev_priv->wm.pri_latency[level] == 0)
966 return USHRT_MAX;
967
936e71e3 968 if (!state->base.visible)
262cd2e1
VS		 969 return 0;
970
ac484963 971 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 972 clock = crtc->config->base.adjusted_mode.crtc_clock;
973 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
974 width = crtc->config->pipe_src_w;
975 if (WARN_ON(htotal == 0))
976 htotal = 1;
977
978 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
979 /*
980 * FIXME the formula gives values that are
981 * too big for the cursor FIFO, and hence we
982 * would never be able to use cursors. For
983 * now just hardcode the watermark.
984 */
985 wm = 63;
986 } else {
ac484963 987 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 988 dev_priv->wm.pri_latency[level] * 10);
989 }
990
991 return min_t(int, wm, USHRT_MAX);
992}
993
54f1b6e1
VS		 994static void vlv_compute_fifo(struct intel_crtc *crtc)
995{
996 struct drm_device *dev = crtc->base.dev;
997 struct vlv_wm_state *wm_state = &crtc->wm_state;
998 struct intel_plane *plane;
999 unsigned int total_rate = 0;
1000 const int fifo_size = 512 - 1;
1001 int fifo_extra, fifo_left = fifo_size;
1002
1003 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1004 struct intel_plane_state *state =
1005 to_intel_plane_state(plane->base.state);
1006
1007 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1008 continue;
1009
936e71e3 1010 if (state->base.visible) {
54f1b6e1
VS		 1011 wm_state->num_active_planes++;
1012 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1013 }
1014 }
1015
1016 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1017 struct intel_plane_state *state =
1018 to_intel_plane_state(plane->base.state);
1019 unsigned int rate;
1020
1021 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1022 plane->wm.fifo_size = 63;
1023 continue;
1024 }
1025
936e71e3 1026 if (!state->base.visible) {
54f1b6e1
VS		 1027 plane->wm.fifo_size = 0;
1028 continue;
1029 }
1030
1031 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1032 plane->wm.fifo_size = fifo_size * rate / total_rate;
1033 fifo_left -= plane->wm.fifo_size;
1034 }
1035
1036 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1037
1038 /* spread the remainder evenly */
1039 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1040 int plane_extra;
1041
1042 if (fifo_left == 0)
1043 break;
1044
1045 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1046 continue;
1047
1048 /* give it all to the first plane if none are active */
1049 if (plane->wm.fifo_size == 0 &&
1050 wm_state->num_active_planes)
1051 continue;
1052
1053 plane_extra = min(fifo_extra, fifo_left);
1054 plane->wm.fifo_size += plane_extra;
1055 fifo_left -= plane_extra;
1056 }
1057
1058 WARN_ON(fifo_left != 0);
1059}
1060
262cd2e1
VS		 1061static void vlv_invert_wms(struct intel_crtc *crtc)
1062{
1063 struct vlv_wm_state *wm_state = &crtc->wm_state;
1064 int level;
1065
1066 for (level = 0; level < wm_state->num_levels; level++) {
1067 struct drm_device *dev = crtc->base.dev;
1068 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1069 struct intel_plane *plane;
1070
1071 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1072 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1073
1074 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1075 switch (plane->base.type) {
1076 int sprite;
1077 case DRM_PLANE_TYPE_CURSOR:
1078 wm_state->wm[level].cursor = plane->wm.fifo_size -
1079 wm_state->wm[level].cursor;
1080 break;
1081 case DRM_PLANE_TYPE_PRIMARY:
1082 wm_state->wm[level].primary = plane->wm.fifo_size -
1083 wm_state->wm[level].primary;
1084 break;
1085 case DRM_PLANE_TYPE_OVERLAY:
1086 sprite = plane->plane;
1087 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1088 wm_state->wm[level].sprite[sprite];
1089 break;
1090 }
1091 }
1092 }
1093}
1094
26e1fe4f 1095static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1096{
1097 struct drm_device *dev = crtc->base.dev;
1098 struct vlv_wm_state *wm_state = &crtc->wm_state;
1099 struct intel_plane *plane;
1100 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1101 int level;
1102
1103 memset(wm_state, 0, sizeof(*wm_state));
1104
852eb00d 1105 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1106 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1107
1108 wm_state->num_active_planes = 0;
262cd2e1 1109
54f1b6e1 1110 vlv_compute_fifo(crtc);
262cd2e1
VS		 1111
1112 if (wm_state->num_active_planes != 1)
1113 wm_state->cxsr = false;
1114
1115 if (wm_state->cxsr) {
1116 for (level = 0; level < wm_state->num_levels; level++) {
1117 wm_state->sr[level].plane = sr_fifo_size;
1118 wm_state->sr[level].cursor = 63;
1119 }
1120 }
1121
1122 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1123 struct intel_plane_state *state =
1124 to_intel_plane_state(plane->base.state);
1125
936e71e3 1126 if (!state->base.visible)
262cd2e1
VS		 1127 continue;
1128
1129 /* normal watermarks */
1130 for (level = 0; level < wm_state->num_levels; level++) {
1131 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1132 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1133
1134 /* hack */
1135 if (WARN_ON(level == 0 && wm > max_wm))
1136 wm = max_wm;
1137
1138 if (wm > plane->wm.fifo_size)
1139 break;
1140
1141 switch (plane->base.type) {
1142 int sprite;
1143 case DRM_PLANE_TYPE_CURSOR:
1144 wm_state->wm[level].cursor = wm;
1145 break;
1146 case DRM_PLANE_TYPE_PRIMARY:
1147 wm_state->wm[level].primary = wm;
1148 break;
1149 case DRM_PLANE_TYPE_OVERLAY:
1150 sprite = plane->plane;
1151 wm_state->wm[level].sprite[sprite] = wm;
1152 break;
1153 }
1154 }
1155
1156 wm_state->num_levels = level;
1157
1158 if (!wm_state->cxsr)
1159 continue;
1160
1161 /* maxfifo watermarks */
1162 switch (plane->base.type) {
1163 int sprite, level;
1164 case DRM_PLANE_TYPE_CURSOR:
1165 for (level = 0; level < wm_state->num_levels; level++)
1166 wm_state->sr[level].cursor =
5a37ed0a 1167 wm_state->wm[level].cursor;
262cd2e1
VS		 1168 break;
1169 case DRM_PLANE_TYPE_PRIMARY:
1170 for (level = 0; level < wm_state->num_levels; level++)
1171 wm_state->sr[level].plane =
1172 min(wm_state->sr[level].plane,
1173 wm_state->wm[level].primary);
1174 break;
1175 case DRM_PLANE_TYPE_OVERLAY:
1176 sprite = plane->plane;
1177 for (level = 0; level < wm_state->num_levels; level++)
1178 wm_state->sr[level].plane =
1179 min(wm_state->sr[level].plane,
1180 wm_state->wm[level].sprite[sprite]);
1181 break;
1182 }
1183 }
1184
1185 /* clear any (partially) filled invalid levels */
58590c14 1186 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1187 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1188 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1189 }
1190
1191 vlv_invert_wms(crtc);
1192}
1193
54f1b6e1
VS		 1194#define VLV_FIFO(plane, value) \
1195 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1196
1197static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1198{
1199 struct drm_device *dev = crtc->base.dev;
1200 struct drm_i915_private *dev_priv = to_i915(dev);
1201 struct intel_plane *plane;
1202 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1203
1204 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1205 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1206 WARN_ON(plane->wm.fifo_size != 63);
1207 continue;
1208 }
1209
1210 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1211 sprite0_start = plane->wm.fifo_size;
1212 else if (plane->plane == 0)
1213 sprite1_start = sprite0_start + plane->wm.fifo_size;
1214 else
1215 fifo_size = sprite1_start + plane->wm.fifo_size;
1216 }
1217
1218 WARN_ON(fifo_size != 512 - 1);
1219
1220 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1221 pipe_name(crtc->pipe), sprite0_start,
1222 sprite1_start, fifo_size);
1223
1224 switch (crtc->pipe) {
1225 uint32_t dsparb, dsparb2, dsparb3;
1226 case PIPE_A:
1227 dsparb = I915_READ(DSPARB);
1228 dsparb2 = I915_READ(DSPARB2);
1229
1230 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1231 VLV_FIFO(SPRITEB, 0xff));
1232 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1233 VLV_FIFO(SPRITEB, sprite1_start));
1234
1235 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1236 VLV_FIFO(SPRITEB_HI, 0x1));
1237 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1238 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1239
1240 I915_WRITE(DSPARB, dsparb);
1241 I915_WRITE(DSPARB2, dsparb2);
1242 break;
1243 case PIPE_B:
1244 dsparb = I915_READ(DSPARB);
1245 dsparb2 = I915_READ(DSPARB2);
1246
1247 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1248 VLV_FIFO(SPRITED, 0xff));
1249 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1250 VLV_FIFO(SPRITED, sprite1_start));
1251
1252 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1253 VLV_FIFO(SPRITED_HI, 0xff));
1254 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1255 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1256
1257 I915_WRITE(DSPARB, dsparb);
1258 I915_WRITE(DSPARB2, dsparb2);
1259 break;
1260 case PIPE_C:
1261 dsparb3 = I915_READ(DSPARB3);
1262 dsparb2 = I915_READ(DSPARB2);
1263
1264 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1265 VLV_FIFO(SPRITEF, 0xff));
1266 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1267 VLV_FIFO(SPRITEF, sprite1_start));
1268
1269 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1270 VLV_FIFO(SPRITEF_HI, 0xff));
1271 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1272 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1273
1274 I915_WRITE(DSPARB3, dsparb3);
1275 I915_WRITE(DSPARB2, dsparb2);
1276 break;
1277 default:
1278 break;
1279 }
1280}
1281
1282#undef VLV_FIFO
1283
262cd2e1
VS		 1284static void vlv_merge_wm(struct drm_device *dev,
1285 struct vlv_wm_values *wm)
1286{
1287 struct intel_crtc *crtc;
1288 int num_active_crtcs = 0;
1289
58590c14 1290 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1291 wm->cxsr = true;
1292
1293 for_each_intel_crtc(dev, crtc) {
1294 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1295
1296 if (!crtc->active)
1297 continue;
1298
1299 if (!wm_state->cxsr)
1300 wm->cxsr = false;
1301
1302 num_active_crtcs++;
1303 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1304 }
1305
1306 if (num_active_crtcs != 1)
1307 wm->cxsr = false;
1308
6f9c784b
VS		 1309 if (num_active_crtcs > 1)
1310 wm->level = VLV_WM_LEVEL_PM2;
1311
262cd2e1
VS		 1312 for_each_intel_crtc(dev, crtc) {
1313 struct vlv_wm_state *wm_state = &crtc->wm_state;
1314 enum pipe pipe = crtc->pipe;
1315
1316 if (!crtc->active)
1317 continue;
1318
1319 wm->pipe[pipe] = wm_state->wm[wm->level];
1320 if (wm->cxsr)
1321 wm->sr = wm_state->sr[wm->level];
1322
1323 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1324 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1325 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1327 }
1328}
1329
1330static void vlv_update_wm(struct drm_crtc *crtc)
1331{
1332 struct drm_device *dev = crtc->dev;
fac5e23e 1333 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1334 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1335 enum pipe pipe = intel_crtc->pipe;
1336 struct vlv_wm_values wm = {};
1337
26e1fe4f 1338 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1339 vlv_merge_wm(dev, &wm);
1340
54f1b6e1
VS		 1341 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1342 /* FIXME should be part of crtc atomic commit */
1343 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1344 return;
54f1b6e1 1345 }
262cd2e1
VS		 1346
1347 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1348 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1349 chv_set_memory_dvfs(dev_priv, false);
1350
1351 if (wm.level < VLV_WM_LEVEL_PM5 &&
1352 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1353 chv_set_memory_pm5(dev_priv, false);
1354
852eb00d 1355 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1356 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1357
54f1b6e1
VS		 1358 /* FIXME should be part of crtc atomic commit */
1359 vlv_pipe_set_fifo_size(intel_crtc);
1360
262cd2e1
VS		 1361 vlv_write_wm_values(intel_crtc, &wm);
1362
1363 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1364 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1365 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1366 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1367 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1368
852eb00d 1369 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1370 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1371
1372 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1373 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1374 chv_set_memory_pm5(dev_priv, true);
1375
1376 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1377 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1378 chv_set_memory_dvfs(dev_priv, true);
1379
1380 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1381}
1382
ae80152d
VS		 1383#define single_plane_enabled(mask) is_power_of_2(mask)
1384
46ba614c 1385static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1386{
46ba614c 1387 struct drm_device *dev = crtc->dev;
b445e3b0 1388 static const int sr_latency_ns = 12000;
fac5e23e 1389 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1390 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1391 int plane_sr, cursor_sr;
1392 unsigned int enabled = 0;
9858425c 1393 bool cxsr_enabled;
b445e3b0 1394
51cea1f4 1395 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1396 &g4x_wm_info, pessimal_latency_ns,
1397 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1398 &planea_wm, &cursora_wm))
51cea1f4 1399 enabled |= 1 << PIPE_A;
b445e3b0 1400
51cea1f4 1401 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1402 &g4x_wm_info, pessimal_latency_ns,
1403 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1404 &planeb_wm, &cursorb_wm))
51cea1f4 1405 enabled |= 1 << PIPE_B;
b445e3b0 1406
b445e3b0
ED		 1407 if (single_plane_enabled(enabled) &&
1408 g4x_compute_srwm(dev, ffs(enabled) - 1,
1409 sr_latency_ns,
1410 &g4x_wm_info,
1411 &g4x_cursor_wm_info,
52bd02d8 1412 &plane_sr, &cursor_sr)) {
9858425c 1413 cxsr_enabled = true;
52bd02d8 1414 } else {
9858425c 1415 cxsr_enabled = false;
5209b1f4 1416 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1417 plane_sr = cursor_sr = 0;
1418 }
b445e3b0 1419
a5043453
VS		 1420 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1421 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1422 planea_wm, cursora_wm,
1423 planeb_wm, cursorb_wm,
1424 plane_sr, cursor_sr);
1425
1426 I915_WRITE(DSPFW1,
f4998963
VS		 1427 FW_WM(plane_sr, SR) |
1428 FW_WM(cursorb_wm, CURSORB) |
1429 FW_WM(planeb_wm, PLANEB) |
1430 FW_WM(planea_wm, PLANEA));
b445e3b0 1431 I915_WRITE(DSPFW2,
8c919b28 1432 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1433 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1434 /* HPLL off in SR has some issues on G4x... disable it */
1435 I915_WRITE(DSPFW3,
8c919b28 1436 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1437 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1438
1439 if (cxsr_enabled)
1440 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1441}
1442
46ba614c 1443static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1444{
46ba614c 1445 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1446 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1447 struct drm_crtc *crtc;
1448 int srwm = 1;
1449 int cursor_sr = 16;
9858425c 1450 bool cxsr_enabled;
b445e3b0
ED		 1451
1452 /* Calc sr entries for one plane configs */
1453 crtc = single_enabled_crtc(dev);
1454 if (crtc) {
1455 /* self-refresh has much higher latency */
1456 static const int sr_latency_ns = 12000;
124abe07 1457 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1458 int clock = adjusted_mode->crtc_clock;
fec8cba3 1459 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1460 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1461 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1462 unsigned long line_time_us;
1463 int entries;
1464
922044c9 1465 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1466
1467 /* Use ns/us then divide to preserve precision */
1468 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1469 cpp * hdisplay;
b445e3b0
ED		 1470 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1471 srwm = I965_FIFO_SIZE - entries;
1472 if (srwm < 0)
1473 srwm = 1;
1474 srwm &= 0x1ff;
1475 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1476 entries, srwm);
1477
1478 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1479 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1480 entries = DIV_ROUND_UP(entries,
1481 i965_cursor_wm_info.cacheline_size);
1482 cursor_sr = i965_cursor_wm_info.fifo_size -
1483 (entries + i965_cursor_wm_info.guard_size);
1484
1485 if (cursor_sr > i965_cursor_wm_info.max_wm)
1486 cursor_sr = i965_cursor_wm_info.max_wm;
1487
1488 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1489 "cursor %d\n", srwm, cursor_sr);
1490
9858425c 1491 cxsr_enabled = true;
b445e3b0 1492 } else {
9858425c 1493 cxsr_enabled = false;
b445e3b0 1494 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1495 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1496 }
1497
1498 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1499 srwm);
1500
1501 /* 965 has limitations... */
f4998963
VS		 1502 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1503 FW_WM(8, CURSORB) |
1504 FW_WM(8, PLANEB) |
1505 FW_WM(8, PLANEA));
1506 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1507 FW_WM(8, PLANEC_OLD));
b445e3b0 1508 /* update cursor SR watermark */
f4998963 1509 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1510
1511 if (cxsr_enabled)
1512 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1513}
1514
f4998963
VS		 1515#undef FW_WM
1516
46ba614c 1517static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1518{
46ba614c 1519 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1520 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1521 const struct intel_watermark_params *wm_info;
1522 uint32_t fwater_lo;
1523 uint32_t fwater_hi;
1524 int cwm, srwm = 1;
1525 int fifo_size;
1526 int planea_wm, planeb_wm;
1527 struct drm_crtc *crtc, *enabled = NULL;
1528
1529 if (IS_I945GM(dev))
1530 wm_info = &i945_wm_info;
1531 else if (!IS_GEN2(dev))
1532 wm_info = &i915_wm_info;
1533 else
9d539105 1534 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1535
1536 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1537 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1538 if (intel_crtc_active(crtc)) {
241bfc38 1539 const struct drm_display_mode *adjusted_mode;
ac484963 1540 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1541 if (IS_GEN2(dev))
1542 cpp = 4;
1543
6e3c9717 1544 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1545 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1546 wm_info, fifo_size, cpp,
5aef6003 1547 pessimal_latency_ns);
b445e3b0 1548 enabled = crtc;
9d539105 1549 } else {
b445e3b0 1550 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1551 if (planea_wm > (long)wm_info->max_wm)
1552 planea_wm = wm_info->max_wm;
1553 }
1554
1555 if (IS_GEN2(dev))
1556 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1557
1558 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1559 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1560 if (intel_crtc_active(crtc)) {
241bfc38 1561 const struct drm_display_mode *adjusted_mode;
ac484963 1562 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1563 if (IS_GEN2(dev))
1564 cpp = 4;
1565
6e3c9717 1566 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1567 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1568 wm_info, fifo_size, cpp,
5aef6003 1569 pessimal_latency_ns);
b445e3b0
ED		 1570 if (enabled == NULL)
1571 enabled = crtc;
1572 else
1573 enabled = NULL;
9d539105 1574 } else {
b445e3b0 1575 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1576 if (planeb_wm > (long)wm_info->max_wm)
1577 planeb_wm = wm_info->max_wm;
1578 }
b445e3b0
ED		 1579
1580 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1581
2ab1bc9d 1582 if (IS_I915GM(dev) && enabled) {
2ff8fde1 1583 struct drm_i915_gem_object *obj;
2ab1bc9d 1584
59bea882 1585 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1586
1587 /* self-refresh seems busted with untiled */
3e510a8e 1588 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1589 enabled = NULL;
1590 }
1591
b445e3b0
ED		 1592 /*
1593 * Overlay gets an aggressive default since video jitter is bad.
1594 */
1595 cwm = 2;
1596
1597 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1598 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1599
1600 /* Calc sr entries for one plane configs */
1601 if (HAS_FW_BLC(dev) && enabled) {
1602 /* self-refresh has much higher latency */
1603 static const int sr_latency_ns = 6000;
124abe07 1604 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1605 int clock = adjusted_mode->crtc_clock;
fec8cba3 1606 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1607 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1608 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1609 unsigned long line_time_us;
1610 int entries;
1611
2d1b5056
VS		 1612 if (IS_I915GM(dev) || IS_I945GM(dev))
1613 cpp = 4;
1614
922044c9 1615 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1616
1617 /* Use ns/us then divide to preserve precision */
1618 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1619 cpp * hdisplay;
b445e3b0
ED		 1620 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1621 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1622 srwm = wm_info->fifo_size - entries;
1623 if (srwm < 0)
1624 srwm = 1;
1625
1626 if (IS_I945G(dev) || IS_I945GM(dev))
1627 I915_WRITE(FW_BLC_SELF,
1628 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1629 else
b445e3b0
ED		 1630 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1631 }
1632
1633 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1634 planea_wm, planeb_wm, cwm, srwm);
1635
1636 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1637 fwater_hi = (cwm & 0x1f);
1638
1639 /* Set request length to 8 cachelines per fetch */
1640 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1641 fwater_hi = fwater_hi | (1 << 8);
1642
1643 I915_WRITE(FW_BLC, fwater_lo);
1644 I915_WRITE(FW_BLC2, fwater_hi);
1645
5209b1f4
ID		 1646 if (enabled)
1647 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1648}
1649
feb56b93 1650static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1651{
46ba614c 1652 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1653 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1654 struct drm_crtc *crtc;
241bfc38 1655 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1656 uint32_t fwater_lo;
1657 int planea_wm;
1658
1659 crtc = single_enabled_crtc(dev);
1660 if (crtc == NULL)
1661 return;
1662
6e3c9717 1663 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1664 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1665 &i845_wm_info,
b445e3b0 1666 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1667 4, pessimal_latency_ns);
b445e3b0
ED		 1668 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1669 fwater_lo |= (3<<8) | planea_wm;
1670
1671 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1672
1673 I915_WRITE(FW_BLC, fwater_lo);
1674}
1675
8cfb3407 1676uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1677{
fd4daa9c 1678 uint32_t pixel_rate;
801bcfff 1679
8cfb3407 1680 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1681
1682 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1683 * adjust the pixel_rate here. */
1684
8cfb3407 1685 if (pipe_config->pch_pfit.enabled) {
801bcfff 1686 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1687 uint32_t pfit_size = pipe_config->pch_pfit.size;
1688
1689 pipe_w = pipe_config->pipe_src_w;
1690 pipe_h = pipe_config->pipe_src_h;
801bcfff 1691
801bcfff
PZ		 1692 pfit_w = (pfit_size >> 16) & 0xFFFF;
1693 pfit_h = pfit_size & 0xFFFF;
1694 if (pipe_w < pfit_w)
1695 pipe_w = pfit_w;
1696 if (pipe_h < pfit_h)
1697 pipe_h = pfit_h;
1698
15126882
MR		 1699 if (WARN_ON(!pfit_w || !pfit_h))
1700 return pixel_rate;
1701
801bcfff
PZ		 1702 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1703 pfit_w * pfit_h);
1704 }
1705
1706 return pixel_rate;
1707}
1708
37126462 1709/* latency must be in 0.1us units. */
ac484963 1710static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1711{
1712 uint64_t ret;
1713
3312ba65
VS		 1714 if (WARN(latency == 0, "Latency value missing\n"))
1715 return UINT_MAX;
1716
ac484963 1717 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1718 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1719
1720 return ret;
1721}
1722
37126462 1723/* latency must be in 0.1us units. */
23297044 1724static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1725 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1726 uint32_t latency)
1727{
1728 uint32_t ret;
1729
3312ba65
VS		 1730 if (WARN(latency == 0, "Latency value missing\n"))
1731 return UINT_MAX;
15126882
MR		 1732 if (WARN_ON(!pipe_htotal))
1733 return UINT_MAX;
3312ba65 1734
801bcfff 1735 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1736 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1737 ret = DIV_ROUND_UP(ret, 64) + 2;
1738 return ret;
1739}
1740
23297044 1741static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1742 uint8_t cpp)
cca32e9a 1743{
15126882
MR		 1744 /*
1745 * Neither of these should be possible since this function shouldn't be
1746 * called if the CRTC is off or the plane is invisible. But let's be
1747 * extra paranoid to avoid a potential divide-by-zero if we screw up
1748 * elsewhere in the driver.
1749 */
ac484963 1750 if (WARN_ON(!cpp))
15126882
MR		 1751 return 0;
1752 if (WARN_ON(!horiz_pixels))
1753 return 0;
1754
ac484963 1755 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1756}
1757
820c1980 1758struct ilk_wm_maximums {
cca32e9a
PZ		 1759 uint16_t pri;
1760 uint16_t spr;
1761 uint16_t cur;
1762 uint16_t fbc;
1763};
1764
37126462
VS		 1765/*
1766 * For both WM_PIPE and WM_LP.
1767 * mem_value must be in 0.1us units.
1768 */
7221fc33 1769static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1770 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1771 uint32_t mem_value,
1772 bool is_lp)
801bcfff 1773{
ac484963
VS		 1774 int cpp = pstate->base.fb ?
1775 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1776 uint32_t method1, method2;
1777
936e71e3 1778 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1779 return 0;
1780
ac484963 1781 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1782
1783 if (!is_lp)
1784 return method1;
1785
7221fc33
MR		 1786 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1787 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1788 drm_rect_width(&pstate->base.dst),
ac484963 1789 cpp, mem_value);
cca32e9a
PZ		 1790
1791 return min(method1, method2);
801bcfff
PZ		 1792}
1793
37126462
VS		 1794/*
1795 * For both WM_PIPE and WM_LP.
1796 * mem_value must be in 0.1us units.
1797 */
7221fc33 1798static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1799 const struct intel_plane_state *pstate,
801bcfff
PZ		 1800 uint32_t mem_value)
1801{
ac484963
VS		 1802 int cpp = pstate->base.fb ?
1803 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1804 uint32_t method1, method2;
1805
936e71e3 1806 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1807 return 0;
1808
ac484963 1809 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1810 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1811 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1812 drm_rect_width(&pstate->base.dst),
ac484963 1813 cpp, mem_value);
801bcfff
PZ		 1814 return min(method1, method2);
1815}
1816
37126462
VS		 1817/*
1818 * For both WM_PIPE and WM_LP.
1819 * mem_value must be in 0.1us units.
1820 */
7221fc33 1821static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1822 const struct intel_plane_state *pstate,
801bcfff
PZ		 1823 uint32_t mem_value)
1824{
b2435692
MR		 1825 /*
1826 * We treat the cursor plane as always-on for the purposes of watermark
1827 * calculation. Until we have two-stage watermark programming merged,
1828 * this is necessary to avoid flickering.
1829 */
1830 int cpp = 4;
936e71e3 1831 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1832
b2435692 1833 if (!cstate->base.active)
801bcfff
PZ		 1834 return 0;
1835
7221fc33
MR		 1836 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1837 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1838 width, cpp, mem_value);
801bcfff
PZ		 1839}
1840
cca32e9a 1841/* Only for WM_LP. */
7221fc33 1842static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1843 const struct intel_plane_state *pstate,
1fda9882 1844 uint32_t pri_val)
cca32e9a 1845{
ac484963
VS		 1846 int cpp = pstate->base.fb ?
1847 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1848
936e71e3 1849 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1850 return 0;
1851
936e71e3 1852 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1853}
1854
158ae64f
VS		 1855static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1856{
416f4727
VS		 1857 if (INTEL_INFO(dev)->gen >= 8)
1858 return 3072;
1859 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1860 return 768;
1861 else
1862 return 512;
1863}
1864
4e975081
VS		 1865static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1866 int level, bool is_sprite)
1867{
1868 if (INTEL_INFO(dev)->gen >= 8)
1869 /* BDW primary/sprite plane watermarks */
1870 return level == 0 ? 255 : 2047;
1871 else if (INTEL_INFO(dev)->gen >= 7)
1872 /* IVB/HSW primary/sprite plane watermarks */
1873 return level == 0 ? 127 : 1023;
1874 else if (!is_sprite)
1875 /* ILK/SNB primary plane watermarks */
1876 return level == 0 ? 127 : 511;
1877 else
1878 /* ILK/SNB sprite plane watermarks */
1879 return level == 0 ? 63 : 255;
1880}
1881
1882static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1883 int level)
1884{
1885 if (INTEL_INFO(dev)->gen >= 7)
1886 return level == 0 ? 63 : 255;
1887 else
1888 return level == 0 ? 31 : 63;
1889}
1890
1891static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1892{
1893 if (INTEL_INFO(dev)->gen >= 8)
1894 return 31;
1895 else
1896 return 15;
1897}
1898
158ae64f
VS		 1899/* Calculate the maximum primary/sprite plane watermark */
1900static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1901 int level,
240264f4 1902 const struct intel_wm_config *config,
158ae64f
VS		 1903 enum intel_ddb_partitioning ddb_partitioning,
1904 bool is_sprite)
1905{
1906 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1907
1908 /* if sprites aren't enabled, sprites get nothing */
240264f4 1909 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1910 return 0;
1911
1912 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1913 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1914 fifo_size /= INTEL_INFO(dev)->num_pipes;
1915
1916 /*
1917 * For some reason the non self refresh
1918 * FIFO size is only half of the self
1919 * refresh FIFO size on ILK/SNB.
1920 */
1921 if (INTEL_INFO(dev)->gen <= 6)
1922 fifo_size /= 2;
1923 }
1924
240264f4 1925 if (config->sprites_enabled) {
158ae64f
VS		 1926 /* level 0 is always calculated with 1:1 split */
1927 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1928 if (is_sprite)
1929 fifo_size *= 5;
1930 fifo_size /= 6;
1931 } else {
1932 fifo_size /= 2;
1933 }
1934 }
1935
1936 /* clamp to max that the registers can hold */
4e975081 1937 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1938}
1939
1940/* Calculate the maximum cursor plane watermark */
1941static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1942 int level,
1943 const struct intel_wm_config *config)
158ae64f
VS		 1944{
1945 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1946 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1947 return 64;
1948
1949 /* otherwise just report max that registers can hold */
4e975081 1950 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1951}
1952
d34ff9c6 1953static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1954 int level,
1955 const struct intel_wm_config *config,
1956 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1957 struct ilk_wm_maximums *max)
158ae64f 1958{
240264f4
VS		 1959 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1960 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1961 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1962 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1963}
1964
a3cb4048
VS		 1965static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1966 int level,
1967 struct ilk_wm_maximums *max)
1968{
1969 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1970 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1971 max->cur = ilk_cursor_wm_reg_max(dev, level);
1972 max->fbc = ilk_fbc_wm_reg_max(dev);
1973}
1974
d9395655 1975static bool ilk_validate_wm_level(int level,
820c1980 1976 const struct ilk_wm_maximums *max,
d9395655 1977 struct intel_wm_level *result)
a9786a11
VS		 1978{
1979 bool ret;
1980
1981 /* already determined to be invalid? */
1982 if (!result->enable)
1983 return false;
1984
1985 result->enable = result->pri_val <= max->pri &&
1986 result->spr_val <= max->spr &&
1987 result->cur_val <= max->cur;
1988
1989 ret = result->enable;
1990
1991 /*
1992 * HACK until we can pre-compute everything,
1993 * and thus fail gracefully if LP0 watermarks
1994 * are exceeded...
1995 */
1996 if (level == 0 && !result->enable) {
1997 if (result->pri_val > max->pri)
1998 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
1999 level, result->pri_val, max->pri);
2000 if (result->spr_val > max->spr)
2001 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2002 level, result->spr_val, max->spr);
2003 if (result->cur_val > max->cur)
2004 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2005 level, result->cur_val, max->cur);
2006
2007 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2008 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2009 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2010 result->enable = true;
2011 }
2012
a9786a11
VS		 2013 return ret;
2014}
2015
d34ff9c6 2016static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2017 const struct intel_crtc *intel_crtc,
6f5ddd17 2018 int level,
7221fc33 2019 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2020 struct intel_plane_state *pristate,
2021 struct intel_plane_state *sprstate,
2022 struct intel_plane_state *curstate,
1fd527cc 2023 struct intel_wm_level *result)
6f5ddd17
VS		 2024{
2025 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2026 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2027 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2028
2029 /* WM1+ latency values stored in 0.5us units */
2030 if (level > 0) {
2031 pri_latency *= 5;
2032 spr_latency *= 5;
2033 cur_latency *= 5;
2034 }
2035
e3bddded
ML		 2036 if (pristate) {
2037 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2038 pri_latency, level);
2039 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2040 }
2041
2042 if (sprstate)
2043 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2044
2045 if (curstate)
2046 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2047
6f5ddd17
VS		 2048 result->enable = true;
2049}
2050
801bcfff 2051static uint32_t
532f7a7f 2052hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2053{
532f7a7f
VS		 2054 const struct intel_atomic_state *intel_state =
2055 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2056 const struct drm_display_mode *adjusted_mode =
2057 &cstate->base.adjusted_mode;
85a02deb 2058 u32 linetime, ips_linetime;
1f8eeabf 2059
ee91a159
MR		 2060 if (!cstate->base.active)
2061 return 0;
2062 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2063 return 0;
532f7a7f 2064 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2065 return 0;
1011d8c4 2066
1f8eeabf
ED		 2067 /* The WM are computed with base on how long it takes to fill a single
2068 * row at the given clock rate, multiplied by 8.
2069 * */
124abe07
VS		 2070 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2071 adjusted_mode->crtc_clock);
2072 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2073 intel_state->cdclk);
1f8eeabf 2074
801bcfff
PZ		 2075 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2076 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2077}
2078
2af30a5c 2079static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2080{
fac5e23e 2081 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2082
2af30a5c
PB		 2083 if (IS_GEN9(dev)) {
2084 uint32_t val;
4f947386 2085 int ret, i;
367294be 2086 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2087
2088 /* read the first set of memory latencies[0:3] */
2089 val = 0; /* data0 to be programmed to 0 for first set */
2090 mutex_lock(&dev_priv->rps.hw_lock);
2091 ret = sandybridge_pcode_read(dev_priv,
2092 GEN9_PCODE_READ_MEM_LATENCY,
2093 &val);
2094 mutex_unlock(&dev_priv->rps.hw_lock);
2095
2096 if (ret) {
2097 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2098 return;
2099 }
2100
2101 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2102 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2103 GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108
2109 /* read the second set of memory latencies[4:7] */
2110 val = 1; /* data0 to be programmed to 1 for second set */
2111 mutex_lock(&dev_priv->rps.hw_lock);
2112 ret = sandybridge_pcode_read(dev_priv,
2113 GEN9_PCODE_READ_MEM_LATENCY,
2114 &val);
2115 mutex_unlock(&dev_priv->rps.hw_lock);
2116 if (ret) {
2117 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2118 return;
2119 }
2120
2121 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2122 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2123 GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128
0727e40a
PZ		 2129 /*
2130 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2131 * need to be disabled. We make sure to sanitize the values out
2132 * of the punit to satisfy this requirement.
2133 */
2134 for (level = 1; level <= max_level; level++) {
2135 if (wm[level] == 0) {
2136 for (i = level + 1; i <= max_level; i++)
2137 wm[i] = 0;
2138 break;
2139 }
2140 }
2141
367294be 2142 /*
6f97235b
DL		 2143 * WaWmMemoryReadLatency:skl
2144 *
367294be 2145 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2146 * to add 2us to the various latency levels we retrieve from the
2147 * punit when level 0 response data us 0us.
367294be 2148 */
0727e40a
PZ		 2149 if (wm[0] == 0) {
2150 wm[0] += 2;
2151 for (level = 1; level <= max_level; level++) {
2152 if (wm[level] == 0)
2153 break;
367294be 2154 wm[level] += 2;
4f947386 2155 }
0727e40a
PZ		 2156 }
2157
2af30a5c 2158 } else if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
12b134df
VS		 2159 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2160
2161 wm[0] = (sskpd >> 56) & 0xFF;
2162 if (wm[0] == 0)
2163 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2164 wm[1] = (sskpd >> 4) & 0xFF;
2165 wm[2] = (sskpd >> 12) & 0xFF;
2166 wm[3] = (sskpd >> 20) & 0x1FF;
2167 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2168 } else if (INTEL_INFO(dev)->gen >= 6) {
2169 uint32_t sskpd = I915_READ(MCH_SSKPD);
2170
2171 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2172 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2173 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2174 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2175 } else if (INTEL_INFO(dev)->gen >= 5) {
2176 uint32_t mltr = I915_READ(MLTR_ILK);
2177
2178 /* ILK primary LP0 latency is 700 ns */
2179 wm[0] = 7;
2180 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2181 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2182 }
2183}
2184
53615a5e
VS		 2185static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2186{
2187 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2188 if (IS_GEN5(dev))
53615a5e
VS		 2189 wm[0] = 13;
2190}
2191
2192static void intel_fixup_cur_wm_latency(struct drm_device *dev, uint16_t wm[5])
2193{
2194 /* ILK cursor LP0 latency is 1300 ns */
7e22dbbb 2195 if (IS_GEN5(dev))
53615a5e
VS		 2196 wm[0] = 13;
2197
2198 /* WaDoubleCursorLP3Latency:ivb */
2199 if (IS_IVYBRIDGE(dev))
2200 wm[3] *= 2;
2201}
2202
546c81fd 2203int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2204{
26ec971e 2205 /* how many WM levels are we expecting */
b6e742f6 2206 if (INTEL_INFO(dev)->gen >= 9)
2af30a5c
PB		 2207 return 7;
2208 else if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ad0d6dc4 2209 return 4;
26ec971e 2210 else if (INTEL_INFO(dev)->gen >= 6)
ad0d6dc4 2211 return 3;
26ec971e 2212 else
ad0d6dc4
VS		 2213 return 2;
2214}
7526ed79 2215
ad0d6dc4
VS		 2216static void intel_print_wm_latency(struct drm_device *dev,
2217 const char *name,
2af30a5c 2218 const uint16_t wm[8])
ad0d6dc4
VS		 2219{
2220 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2221
2222 for (level = 0; level <= max_level; level++) {
2223 unsigned int latency = wm[level];
2224
2225 if (latency == 0) {
2226 DRM_ERROR("%s WM%d latency not provided\n",
2227 name, level);
2228 continue;
2229 }
2230
2af30a5c
PB		 2231 /*
2232 * - latencies are in us on gen9.
2233 * - before then, WM1+ latency values are in 0.5us units
2234 */
2235 if (IS_GEN9(dev))
2236 latency *= 10;
2237 else if (level > 0)
26ec971e
VS		 2238 latency *= 5;
2239
2240 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2241 name, level, wm[level],
2242 latency / 10, latency % 10);
2243 }
2244}
2245
e95a2f75
VS		 2246static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2247 uint16_t wm[5], uint16_t min)
2248{
91c8a326 2249 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2250
2251 if (wm[0] >= min)
2252 return false;
2253
2254 wm[0] = max(wm[0], min);
2255 for (level = 1; level <= max_level; level++)
2256 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2257
2258 return true;
2259}
2260
2261static void snb_wm_latency_quirk(struct drm_device *dev)
2262{
fac5e23e 2263 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2264 bool changed;
2265
2266 /*
2267 * The BIOS provided WM memory latency values are often
2268 * inadequate for high resolution displays. Adjust them.
2269 */
2270 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2271 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2272 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2273
2274 if (!changed)
2275 return;
2276
2277 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2278 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2279 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2280 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2281}
2282
fa50ad61 2283static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2284{
fac5e23e 2285 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2286
2287 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2288
2289 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2290 sizeof(dev_priv->wm.pri_latency));
2291 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2292 sizeof(dev_priv->wm.pri_latency));
2293
2294 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
2295 intel_fixup_cur_wm_latency(dev, dev_priv->wm.cur_latency);
26ec971e
VS		 2296
2297 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2298 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2299 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2300
2301 if (IS_GEN6(dev))
2302 snb_wm_latency_quirk(dev);
53615a5e
VS		 2303}
2304
2af30a5c
PB		 2305static void skl_setup_wm_latency(struct drm_device *dev)
2306{
fac5e23e 2307 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2308
2309 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2310 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2311}
2312
ed4a6a7c
MR		 2313static bool ilk_validate_pipe_wm(struct drm_device *dev,
2314 struct intel_pipe_wm *pipe_wm)
2315{
2316 /* LP0 watermark maximums depend on this pipe alone */
2317 const struct intel_wm_config config = {
2318 .num_pipes_active = 1,
2319 .sprites_enabled = pipe_wm->sprites_enabled,
2320 .sprites_scaled = pipe_wm->sprites_scaled,
2321 };
2322 struct ilk_wm_maximums max;
2323
2324 /* LP0 watermarks always use 1/2 DDB partitioning */
2325 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2326
2327 /* At least LP0 must be valid */
2328 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2329 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2330 return false;
2331 }
2332
2333 return true;
2334}
2335
0b2ae6d7 2336/* Compute new watermarks for the pipe */
e3bddded 2337static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2338{
e3bddded
ML		 2339 struct drm_atomic_state *state = cstate->base.state;
2340 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2341 struct intel_pipe_wm *pipe_wm;
e3bddded 2342 struct drm_device *dev = state->dev;
fac5e23e 2343 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2344 struct intel_plane *intel_plane;
86c8bbbe 2345 struct intel_plane_state *pristate = NULL;
43d59eda 2346 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2347 struct intel_plane_state *curstate = NULL;
d81f04c5 2348 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2349 struct ilk_wm_maximums max;
0b2ae6d7 2350
e8f1f02e 2351 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2352
43d59eda 2353 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2354 struct intel_plane_state *ps;
2355
2356 ps = intel_atomic_get_existing_plane_state(state,
2357 intel_plane);
2358 if (!ps)
2359 continue;
86c8bbbe
MR		 2360
2361 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2362 pristate = ps;
86c8bbbe 2363 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2364 sprstate = ps;
86c8bbbe 2365 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2366 curstate = ps;
43d59eda
MR		 2367 }
2368
ed4a6a7c 2369 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2370 if (sprstate) {
936e71e3
VS		 2371 pipe_wm->sprites_enabled = sprstate->base.visible;
2372 pipe_wm->sprites_scaled = sprstate->base.visible &&
2373 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2374 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2375 }
2376
d81f04c5
ML		 2377 usable_level = max_level;
2378
7b39a0b7 2379 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2380 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2381 usable_level = 1;
7b39a0b7
VS		 2382
2383 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2384 if (pipe_wm->sprites_scaled)
d81f04c5 2385 usable_level = 0;
7b39a0b7 2386
86c8bbbe 2387 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2388 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2389
2390 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2391 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2392
a42a5719 2393 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
532f7a7f 2394 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2395
ed4a6a7c 2396 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2397 return -EINVAL;
a3cb4048
VS		 2398
2399 ilk_compute_wm_reg_maximums(dev, 1, &max);
2400
2401 for (level = 1; level <= max_level; level++) {
71f0a626 2402 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2403
86c8bbbe 2404 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2405 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2406
2407 /*
2408 * Disable any watermark level that exceeds the
2409 * register maximums since such watermarks are
2410 * always invalid.
2411 */
71f0a626
ML		 2412 if (level > usable_level)
2413 continue;
2414
2415 if (ilk_validate_wm_level(level, &max, wm))
2416 pipe_wm->wm[level] = *wm;
2417 else
d81f04c5 2418 usable_level = level;
a3cb4048
VS		 2419 }
2420
86c8bbbe 2421 return 0;
0b2ae6d7
VS		 2422}
2423
ed4a6a7c
MR		 2424/*
2425 * Build a set of 'intermediate' watermark values that satisfy both the old
2426 * state and the new state. These can be programmed to the hardware
2427 * immediately.
2428 */
2429static int ilk_compute_intermediate_wm(struct drm_device *dev,
2430 struct intel_crtc *intel_crtc,
2431 struct intel_crtc_state *newstate)
2432{
e8f1f02e 2433 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2434 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2435 int level, max_level = ilk_wm_max_level(dev);
2436
2437 /*
2438 * Start with the final, target watermarks, then combine with the
2439 * currently active watermarks to get values that are safe both before
2440 * and after the vblank.
2441 */
e8f1f02e 2442 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2443 a->pipe_enabled |= b->pipe_enabled;
2444 a->sprites_enabled |= b->sprites_enabled;
2445 a->sprites_scaled |= b->sprites_scaled;
2446
2447 for (level = 0; level <= max_level; level++) {
2448 struct intel_wm_level *a_wm = &a->wm[level];
2449 const struct intel_wm_level *b_wm = &b->wm[level];
2450
2451 a_wm->enable &= b_wm->enable;
2452 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2453 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2454 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2455 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2456 }
2457
2458 /*
2459 * We need to make sure that these merged watermark values are
2460 * actually a valid configuration themselves. If they're not,
2461 * there's no safe way to transition from the old state to
2462 * the new state, so we need to fail the atomic transaction.
2463 */
2464 if (!ilk_validate_pipe_wm(dev, a))
2465 return -EINVAL;
2466
2467 /*
2468 * If our intermediate WM are identical to the final WM, then we can
2469 * omit the post-vblank programming; only update if it's different.
2470 */
e8f1f02e 2471 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2472 newstate->wm.need_postvbl_update = false;
2473
2474 return 0;
2475}
2476
0b2ae6d7
VS		 2477/*
2478 * Merge the watermarks from all active pipes for a specific level.
2479 */
2480static void ilk_merge_wm_level(struct drm_device *dev,
2481 int level,
2482 struct intel_wm_level *ret_wm)
2483{
2484 const struct intel_crtc *intel_crtc;
2485
d52fea5b
VS		 2486 ret_wm->enable = true;
2487
d3fcc808 2488 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2489 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2490 const struct intel_wm_level *wm = &active->wm[level];
2491
2492 if (!active->pipe_enabled)
2493 continue;
0b2ae6d7 2494
d52fea5b
VS		 2495 /*
2496 * The watermark values may have been used in the past,
2497 * so we must maintain them in the registers for some
2498 * time even if the level is now disabled.
2499 */
0b2ae6d7 2500 if (!wm->enable)
d52fea5b 2501 ret_wm->enable = false;
0b2ae6d7
VS		 2502
2503 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2504 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2505 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2506 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2507 }
0b2ae6d7
VS		 2508}
2509
2510/*
2511 * Merge all low power watermarks for all active pipes.
2512 */
2513static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2514 const struct intel_wm_config *config,
820c1980 2515 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2516 struct intel_pipe_wm *merged)
2517{
fac5e23e 2518 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2519 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2520 int last_enabled_level = max_level;
0b2ae6d7 2521
0ba22e26
VS		 2522 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
2523 if ((INTEL_INFO(dev)->gen <= 6 || IS_IVYBRIDGE(dev)) &&
2524 config->num_pipes_active > 1)
1204d5ba 2525 last_enabled_level = 0;
0ba22e26 2526
6c8b6c28
VS		 2527 /* ILK: FBC WM must be disabled always */
2528 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2529
2530 /* merge each WM1+ level */
2531 for (level = 1; level <= max_level; level++) {
2532 struct intel_wm_level *wm = &merged->wm[level];
2533
2534 ilk_merge_wm_level(dev, level, wm);
2535
d52fea5b
VS		 2536 if (level > last_enabled_level)
2537 wm->enable = false;
2538 else if (!ilk_validate_wm_level(level, max, wm))
2539 /* make sure all following levels get disabled */
2540 last_enabled_level = level - 1;
0b2ae6d7
VS		 2541
2542 /*
2543 * The spec says it is preferred to disable
2544 * FBC WMs instead of disabling a WM level.
2545 */
2546 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2547 if (wm->enable)
2548 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2549 wm->fbc_val = 0;
2550 }
2551 }
6c8b6c28
VS		 2552
2553 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2554 /*
2555 * FIXME this is racy. FBC might get enabled later.
2556 * What we should check here is whether FBC can be
2557 * enabled sometime later.
2558 */
7733b49b 2559 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2560 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2561 for (level = 2; level <= max_level; level++) {
2562 struct intel_wm_level *wm = &merged->wm[level];
2563
2564 wm->enable = false;
2565 }
2566 }
0b2ae6d7
VS		 2567}
2568
b380ca3c
VS		 2569static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2570{
2571 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2572 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2573}
2574
a68d68ee
VS		 2575/* The value we need to program into the WM_LPx latency field */
2576static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2577{
fac5e23e 2578 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2579
a42a5719 2580 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
a68d68ee
VS		 2581 return 2 * level;
2582 else
2583 return dev_priv->wm.pri_latency[level];
2584}
2585
820c1980 2586static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2587 const struct intel_pipe_wm *merged,
609cedef 2588 enum intel_ddb_partitioning partitioning,
820c1980 2589 struct ilk_wm_values *results)
801bcfff 2590{
0b2ae6d7
VS		 2591 struct intel_crtc *intel_crtc;
2592 int level, wm_lp;
cca32e9a 2593
0362c781 2594 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2595 results->partitioning = partitioning;
cca32e9a 2596
0b2ae6d7 2597 /* LP1+ register values */
cca32e9a 2598 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2599 const struct intel_wm_level *r;
801bcfff 2600
b380ca3c 2601 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2602
0362c781 2603 r = &merged->wm[level];
cca32e9a 2604
d52fea5b
VS		 2605 /*
2606 * Maintain the watermark values even if the level is
2607 * disabled. Doing otherwise could cause underruns.
2608 */
2609 results->wm_lp[wm_lp - 1] =
a68d68ee 2610 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2611 (r->pri_val << WM1_LP_SR_SHIFT) |
2612 r->cur_val;
2613
d52fea5b
VS		 2614 if (r->enable)
2615 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2616
416f4727
VS		 2617 if (INTEL_INFO(dev)->gen >= 8)
2618 results->wm_lp[wm_lp - 1] |=
2619 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2620 else
2621 results->wm_lp[wm_lp - 1] |=
2622 r->fbc_val << WM1_LP_FBC_SHIFT;
2623
d52fea5b
VS		 2624 /*
2625 * Always set WM1S_LP_EN when spr_val != 0, even if the
2626 * level is disabled. Doing otherwise could cause underruns.
2627 */
6cef2b8a
VS		 2628 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2629 WARN_ON(wm_lp != 1);
2630 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2631 } else
2632 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2633 }
801bcfff 2634
0b2ae6d7 2635 /* LP0 register values */
d3fcc808 2636 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2637 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2638 const struct intel_wm_level *r =
2639 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2640
2641 if (WARN_ON(!r->enable))
2642 continue;
2643
ed4a6a7c 2644 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2645
0b2ae6d7
VS		 2646 results->wm_pipe[pipe] =
2647 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2648 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2649 r->cur_val;
801bcfff
PZ		 2650 }
2651}
2652
861f3389
PZ		 2653/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2654 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2655static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2656 struct intel_pipe_wm *r1,
2657 struct intel_pipe_wm *r2)
861f3389 2658{
198a1e9b
VS		 2659 int level, max_level = ilk_wm_max_level(dev);
2660 int level1 = 0, level2 = 0;
861f3389 2661
198a1e9b
VS		 2662 for (level = 1; level <= max_level; level++) {
2663 if (r1->wm[level].enable)
2664 level1 = level;
2665 if (r2->wm[level].enable)
2666 level2 = level;
861f3389
PZ		 2667 }
2668
198a1e9b
VS		 2669 if (level1 == level2) {
2670 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2671 return r2;
2672 else
2673 return r1;
198a1e9b 2674 } else if (level1 > level2) {
861f3389
PZ		 2675 return r1;
2676 } else {
2677 return r2;
2678 }
2679}
2680
49a687c4
VS		 2681/* dirty bits used to track which watermarks need changes */
2682#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2683#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2684#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2685#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2686#define WM_DIRTY_FBC (1 << 24)
2687#define WM_DIRTY_DDB (1 << 25)
2688
055e393f 2689static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2690 const struct ilk_wm_values *old,
2691 const struct ilk_wm_values *new)
49a687c4
VS		 2692{
2693 unsigned int dirty = 0;
2694 enum pipe pipe;
2695 int wm_lp;
2696
055e393f 2697 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2698 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2699 dirty |= WM_DIRTY_LINETIME(pipe);
2700 /* Must disable LP1+ watermarks too */
2701 dirty |= WM_DIRTY_LP_ALL;
2702 }
2703
2704 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2705 dirty |= WM_DIRTY_PIPE(pipe);
2706 /* Must disable LP1+ watermarks too */
2707 dirty |= WM_DIRTY_LP_ALL;
2708 }
2709 }
2710
2711 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2712 dirty |= WM_DIRTY_FBC;
2713 /* Must disable LP1+ watermarks too */
2714 dirty |= WM_DIRTY_LP_ALL;
2715 }
2716
2717 if (old->partitioning != new->partitioning) {
2718 dirty |= WM_DIRTY_DDB;
2719 /* Must disable LP1+ watermarks too */
2720 dirty |= WM_DIRTY_LP_ALL;
2721 }
2722
2723 /* LP1+ watermarks already deemed dirty, no need to continue */
2724 if (dirty & WM_DIRTY_LP_ALL)
2725 return dirty;
2726
2727 /* Find the lowest numbered LP1+ watermark in need of an update... */
2728 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2729 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2730 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2731 break;
2732 }
2733
2734 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2735 for (; wm_lp <= 3; wm_lp++)
2736 dirty |= WM_DIRTY_LP(wm_lp);
2737
2738 return dirty;
2739}
2740
8553c18e
VS		 2741static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2742 unsigned int dirty)
801bcfff 2743{
820c1980 2744 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2745 bool changed = false;
801bcfff 2746
facd619b
VS		 2747 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2748 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2749 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2750 changed = true;
facd619b
VS		 2751 }
2752 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2753 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2755 changed = true;
facd619b
VS		 2756 }
2757 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2758 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2760 changed = true;
facd619b 2761 }
801bcfff 2762
facd619b
VS		 2763 /*
2764 * Don't touch WM1S_LP_EN here.
2765 * Doing so could cause underruns.
2766 */
6cef2b8a 2767
8553c18e
VS		 2768 return changed;
2769}
2770
2771/*
2772 * The spec says we shouldn't write when we don't need, because every write
2773 * causes WMs to be re-evaluated, expending some power.
2774 */
820c1980
ID		 2775static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2776 struct ilk_wm_values *results)
8553c18e 2777{
91c8a326 2778 struct drm_device *dev = &dev_priv->drm;
820c1980 2779 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2780 unsigned int dirty;
2781 uint32_t val;
2782
055e393f 2783 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2784 if (!dirty)
2785 return;
2786
2787 _ilk_disable_lp_wm(dev_priv, dirty);
2788
49a687c4 2789 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2790 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2791 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2792 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2793 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2794 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2795
49a687c4 2796 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2797 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2798 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2799 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2800 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2801 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2802
49a687c4 2803 if (dirty & WM_DIRTY_DDB) {
a42a5719 2804 if (IS_HASWELL(dev) || IS_BROADWELL(dev)) {
ac9545fd
VS		 2805 val = I915_READ(WM_MISC);
2806 if (results->partitioning == INTEL_DDB_PART_1_2)
2807 val &= ~WM_MISC_DATA_PARTITION_5_6;
2808 else
2809 val |= WM_MISC_DATA_PARTITION_5_6;
2810 I915_WRITE(WM_MISC, val);
2811 } else {
2812 val = I915_READ(DISP_ARB_CTL2);
2813 if (results->partitioning == INTEL_DDB_PART_1_2)
2814 val &= ~DISP_DATA_PARTITION_5_6;
2815 else
2816 val |= DISP_DATA_PARTITION_5_6;
2817 I915_WRITE(DISP_ARB_CTL2, val);
2818 }
1011d8c4
PZ		 2819 }
2820
49a687c4 2821 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2822 val = I915_READ(DISP_ARB_CTL);
2823 if (results->enable_fbc_wm)
2824 val &= ~DISP_FBC_WM_DIS;
2825 else
2826 val |= DISP_FBC_WM_DIS;
2827 I915_WRITE(DISP_ARB_CTL, val);
2828 }
2829
954911eb
ID		 2830 if (dirty & WM_DIRTY_LP(1) &&
2831 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2832 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2833
2834 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2835 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2836 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2837 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2838 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2839 }
801bcfff 2840
facd619b 2841 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2842 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2843 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2844 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2845 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2846 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2847
2848 dev_priv->wm.hw = *results;
801bcfff
PZ		 2849}
2850
ed4a6a7c 2851bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2852{
fac5e23e 2853 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2854
2855 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2856}
2857
656d1b89 2858#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2859
024c9045
MR		 2860/*
2861 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2862 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2863 * other universal planes are in indices 1..n. Note that this may leave unused
2864 * indices between the top "sprite" plane and the cursor.
2865 */
2866static int
2867skl_wm_plane_id(const struct intel_plane *plane)
2868{
2869 switch (plane->base.type) {
2870 case DRM_PLANE_TYPE_PRIMARY:
2871 return 0;
2872 case DRM_PLANE_TYPE_CURSOR:
2873 return PLANE_CURSOR;
2874 case DRM_PLANE_TYPE_OVERLAY:
2875 return plane->plane + 1;
2876 default:
2877 MISSING_CASE(plane->base.type);
2878 return plane->plane;
2879 }
2880}
2881
56feca91
PZ		 2882static bool
2883intel_has_sagv(struct drm_i915_private *dev_priv)
2884{
6e3100ec
PZ		 2885 if (IS_KABYLAKE(dev_priv))
2886 return true;
2887
2888 if (IS_SKYLAKE(dev_priv) &&
2889 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2890 return true;
2891
2892 return false;
56feca91
PZ		 2893}
2894
656d1b89
L		 2895/*
2896 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2897 * depending on power and performance requirements. The display engine access
2898 * to system memory is blocked during the adjustment time. Because of the
2899 * blocking time, having this enabled can cause full system hangs and/or pipe
2900 * underruns if we don't meet all of the following requirements:
2901 *
2902 * - <= 1 pipe enabled
2903 * - All planes can enable watermarks for latencies >= SAGV engine block time
2904 * - We're not using an interlaced display configuration
2905 */
2906int
16dcdc4e 2907intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2908{
2909 int ret;
2910
56feca91
PZ		 2911 if (!intel_has_sagv(dev_priv))
2912 return 0;
2913
2914 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2915 return 0;
2916
2917 DRM_DEBUG_KMS("Enabling the SAGV\n");
2918 mutex_lock(&dev_priv->rps.hw_lock);
2919
2920 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2921 GEN9_SAGV_ENABLE);
2922
2923 /* We don't need to wait for the SAGV when enabling */
2924 mutex_unlock(&dev_priv->rps.hw_lock);
2925
2926 /*
2927 * Some skl systems, pre-release machines in particular,
2928 * don't actually have an SAGV.
2929 */
6e3100ec 2930 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2931 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2932 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2933 return 0;
2934 } else if (ret < 0) {
2935 DRM_ERROR("Failed to enable the SAGV\n");
2936 return ret;
2937 }
2938
16dcdc4e 2939 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2940 return 0;
2941}
2942
2943static int
16dcdc4e 2944intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2945{
2946 int ret;
2947 uint32_t temp = GEN9_SAGV_DISABLE;
2948
2949 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2950 &temp);
2951 if (ret)
2952 return ret;
2953 else
2954 return temp & GEN9_SAGV_IS_DISABLED;
2955}
2956
2957int
16dcdc4e 2958intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2959{
2960 int ret, result;
2961
56feca91
PZ		 2962 if (!intel_has_sagv(dev_priv))
2963 return 0;
2964
2965 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2966 return 0;
2967
2968 DRM_DEBUG_KMS("Disabling the SAGV\n");
2969 mutex_lock(&dev_priv->rps.hw_lock);
2970
2971 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2972 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2973 mutex_unlock(&dev_priv->rps.hw_lock);
2974
2975 if (ret == -ETIMEDOUT) {
2976 DRM_ERROR("Request to disable SAGV timed out\n");
2977 return -ETIMEDOUT;
2978 }
2979
2980 /*
2981 * Some skl systems, pre-release machines in particular,
2982 * don't actually have an SAGV.
2983 */
6e3100ec 2984 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2985 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2986 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2987 return 0;
2988 } else if (result < 0) {
2989 DRM_ERROR("Failed to disable the SAGV\n");
2990 return result;
2991 }
2992
16dcdc4e 2993 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2994 return 0;
2995}
2996
16dcdc4e 2997bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 2998{
2999 struct drm_device *dev = state->dev;
3000 struct drm_i915_private *dev_priv = to_i915(dev);
3001 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3002 struct drm_crtc *crtc;
3003 enum pipe pipe;
3004 int level, plane;
3005
56feca91
PZ		 3006 if (!intel_has_sagv(dev_priv))
3007 return false;
3008
656d1b89
L		 3009 /*
3010 * SKL workaround: bspec recommends we disable the SAGV when we have
3011 * more then one pipe enabled
3012 *
3013 * If there are no active CRTCs, no additional checks need be performed
3014 */
3015 if (hweight32(intel_state->active_crtcs) == 0)
3016 return true;
3017 else if (hweight32(intel_state->active_crtcs) > 1)
3018 return false;
3019
3020 /* Since we're now guaranteed to only have one active CRTC... */
3021 pipe = ffs(intel_state->active_crtcs) - 1;
3022 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3023
3024 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3025 return false;
3026
3027 for_each_plane(dev_priv, pipe, plane) {
3028 /* Skip this plane if it's not enabled */
3029 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3030 continue;
3031
3032 /* Find the highest enabled wm level for this plane */
3033 for (level = ilk_wm_max_level(dev);
3034 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3035 { }
3036
3037 /*
3038 * If any of the planes on this pipe don't enable wm levels
3039 * that incur memory latencies higher then 30µs we can't enable
3040 * the SAGV
3041 */
3042 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3043 return false;
3044 }
3045
3046 return true;
3047}
3048
b9cec075
DL		 3049static void
3050skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3051 const struct intel_crtc_state *cstate,
c107acfe
MR		 3052 struct skl_ddb_entry *alloc, /* out */
3053 int *num_active /* out */)
b9cec075 3054{
c107acfe
MR		 3055 struct drm_atomic_state *state = cstate->base.state;
3056 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3057 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3058 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3059 unsigned int pipe_size, ddb_size;
3060 int nth_active_pipe;
c107acfe
MR		 3061 int pipe = to_intel_crtc(for_crtc)->pipe;
3062
a6d3460e 3063 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3064 alloc->start = 0;
3065 alloc->end = 0;
a6d3460e 3066 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3067 return;
3068 }
3069
a6d3460e
MR		 3070 if (intel_state->active_pipe_changes)
3071 *num_active = hweight32(intel_state->active_crtcs);
3072 else
3073 *num_active = hweight32(dev_priv->active_crtcs);
3074
6f3fff60
D		 3075 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3076 WARN_ON(ddb_size == 0);
b9cec075
DL		 3077
3078 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3079
c107acfe 3080 /*
a6d3460e
MR		 3081 * If the state doesn't change the active CRTC's, then there's
3082 * no need to recalculate; the existing pipe allocation limits
3083 * should remain unchanged. Note that we're safe from racing
3084 * commits since any racing commit that changes the active CRTC
3085 * list would need to grab _all_ crtc locks, including the one
3086 * we currently hold.
c107acfe 3087 */
a6d3460e
MR		 3088 if (!intel_state->active_pipe_changes) {
3089 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3090 return;
c107acfe 3091 }
a6d3460e
MR		 3092
3093 nth_active_pipe = hweight32(intel_state->active_crtcs &
3094 (drm_crtc_mask(for_crtc) - 1));
3095 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3096 alloc->start = nth_active_pipe * ddb_size / *num_active;
3097 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3098}
3099
c107acfe 3100static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3101{
c107acfe 3102 if (num_active == 1)
b9cec075
DL		 3103 return 32;
3104
3105 return 8;
3106}
3107
a269c583
DL		 3108static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3109{
3110 entry->start = reg & 0x3ff;
3111 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3112 if (entry->end)
3113 entry->end += 1;
a269c583
DL		 3114}
3115
08db6652
DL		 3116void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3117 struct skl_ddb_allocation *ddb /* out */)
a269c583 3118{
a269c583
DL		 3119 enum pipe pipe;
3120 int plane;
3121 u32 val;
3122
b10f1b20
ML		 3123 memset(ddb, 0, sizeof(*ddb));
3124
a269c583 3125 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3126 enum intel_display_power_domain power_domain;
3127
3128 power_domain = POWER_DOMAIN_PIPE(pipe);
3129 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3130 continue;
3131
dd740780 3132 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3133 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3134 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3135 val);
3136 }
3137
3138 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3139 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3140 val);
4d800030
ID		 3141
3142 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3143 }
3144}
3145
9c2f7a9d
KM		 3146/*
3147 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3148 * The bspec defines downscale amount as:
3149 *
3150 * """
3151 * Horizontal down scale amount = maximum[1, Horizontal source size /
3152 * Horizontal destination size]
3153 * Vertical down scale amount = maximum[1, Vertical source size /
3154 * Vertical destination size]
3155 * Total down scale amount = Horizontal down scale amount *
3156 * Vertical down scale amount
3157 * """
3158 *
3159 * Return value is provided in 16.16 fixed point form to retain fractional part.
3160 * Caller should take care of dividing & rounding off the value.
3161 */
3162static uint32_t
3163skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3164{
3165 uint32_t downscale_h, downscale_w;
3166 uint32_t src_w, src_h, dst_w, dst_h;
3167
936e71e3 3168 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3169 return DRM_PLANE_HELPER_NO_SCALING;
3170
3171 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3172 src_w = drm_rect_width(&pstate->base.src);
3173 src_h = drm_rect_height(&pstate->base.src);
3174 dst_w = drm_rect_width(&pstate->base.dst);
3175 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3176 if (intel_rotation_90_or_270(pstate->base.rotation))
3177 swap(dst_w, dst_h);
3178
3179 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3180 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3181
3182 /* Provide result in 16.16 fixed point */
3183 return (uint64_t)downscale_w * downscale_h >> 16;
3184}
3185
b9cec075 3186static unsigned int
024c9045
MR		 3187skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3188 const struct drm_plane_state *pstate,
3189 int y)
b9cec075 3190{
a280f7dd 3191 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3192 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3193 uint32_t down_scale_amount, data_rate;
a280f7dd 3194 uint32_t width = 0, height = 0;
a1de91e5
MR		 3195 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3196
936e71e3 3197 if (!intel_pstate->base.visible)
a1de91e5
MR		 3198 return 0;
3199 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3200 return 0;
3201 if (y && format != DRM_FORMAT_NV12)
3202 return 0;
a280f7dd 3203
936e71e3
VS		 3204 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3205 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3206
3207 if (intel_rotation_90_or_270(pstate->rotation))
3208 swap(width, height);
2cd601c6
CK		 3209
3210 /* for planar format */
a1de91e5 3211 if (format == DRM_FORMAT_NV12) {
2cd601c6 3212 if (y) /* y-plane data rate */
8d19d7d9 3213 data_rate = width * height *
a1de91e5 3214 drm_format_plane_cpp(format, 0);
2cd601c6 3215 else /* uv-plane data rate */
8d19d7d9 3216 data_rate = (width / 2) * (height / 2) *
a1de91e5 3217 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3218 } else {
3219 /* for packed formats */
3220 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3221 }
3222
8d19d7d9
KM		 3223 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3224
3225 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3226}
3227
3228/*
3229 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3230 * a 8192x4096@32bpp framebuffer:
3231 * 3 * 4096 * 8192 * 4 < 2^32
3232 */
3233static unsigned int
9c74d826 3234skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3235{
9c74d826
MR		 3236 struct drm_crtc_state *cstate = &intel_cstate->base;
3237 struct drm_atomic_state *state = cstate->state;
3238 struct drm_crtc *crtc = cstate->crtc;
3239 struct drm_device *dev = crtc->dev;
3240 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3241 const struct drm_plane *plane;
024c9045 3242 const struct intel_plane *intel_plane;
a6d3460e 3243 struct drm_plane_state *pstate;
a1de91e5 3244 unsigned int rate, total_data_rate = 0;
9c74d826 3245 int id;
a6d3460e
MR		 3246 int i;
3247
3248 if (WARN_ON(!state))
3249 return 0;
b9cec075 3250
a1de91e5 3251 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3252 for_each_plane_in_state(state, plane, pstate, i) {
3253 id = skl_wm_plane_id(to_intel_plane(plane));
3254 intel_plane = to_intel_plane(plane);
3255
3256 if (intel_plane->pipe != intel_crtc->pipe)
3257 continue;
3258
3259 /* packed/uv */
3260 rate = skl_plane_relative_data_rate(intel_cstate,
3261 pstate, 0);
3262 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3263
3264 /* y-plane */
3265 rate = skl_plane_relative_data_rate(intel_cstate,
3266 pstate, 1);
3267 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3268 }
024c9045 3269
a1de91e5
MR		 3270 /* Calculate CRTC's total data rate from cached values */
3271 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3272 int id = skl_wm_plane_id(intel_plane);
024c9045 3273
a1de91e5 3274 /* packed/uv */
9c74d826
MR		 3275 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3276 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3277 }
3278
3279 return total_data_rate;
3280}
3281
cbcfd14b
KM		 3282static uint16_t
3283skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3284 const int y)
3285{
3286 struct drm_framebuffer *fb = pstate->fb;
3287 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3288 uint32_t src_w, src_h;
3289 uint32_t min_scanlines = 8;
3290 uint8_t plane_bpp;
3291
3292 if (WARN_ON(!fb))
3293 return 0;
3294
3295 /* For packed formats, no y-plane, return 0 */
3296 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3297 return 0;
3298
3299 /* For Non Y-tile return 8-blocks */
3300 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3301 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3302 return 8;
3303
936e71e3
VS		 3304 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3305 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3306
3307 if (intel_rotation_90_or_270(pstate->rotation))
3308 swap(src_w, src_h);
3309
3310 /* Halve UV plane width and height for NV12 */
3311 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3312 src_w /= 2;
3313 src_h /= 2;
3314 }
3315
3316 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3317 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3318 else
3319 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3320
3321 if (intel_rotation_90_or_270(pstate->rotation)) {
3322 switch (plane_bpp) {
3323 case 1:
3324 min_scanlines = 32;
3325 break;
3326 case 2:
3327 min_scanlines = 16;
3328 break;
3329 case 4:
3330 min_scanlines = 8;
3331 break;
3332 case 8:
3333 min_scanlines = 4;
3334 break;
3335 default:
3336 WARN(1, "Unsupported pixel depth %u for rotation",
3337 plane_bpp);
3338 min_scanlines = 32;
3339 }
3340 }
3341
3342 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3343}
3344
c107acfe 3345static int
024c9045 3346skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3347 struct skl_ddb_allocation *ddb /* out */)
3348{
c107acfe 3349 struct drm_atomic_state *state = cstate->base.state;
024c9045 3350 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3351 struct drm_device *dev = crtc->dev;
3352 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3353 struct intel_plane *intel_plane;
c107acfe
MR		 3354 struct drm_plane *plane;
3355 struct drm_plane_state *pstate;
b9cec075 3356 enum pipe pipe = intel_crtc->pipe;
34bb56af 3357 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3358 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3359 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3360 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3361 unsigned int total_data_rate;
c107acfe
MR		 3362 int num_active;
3363 int id, i;
b9cec075 3364
5a920b85
PZ		 3365 /* Clear the partitioning for disabled planes. */
3366 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3367 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3368
a6d3460e
MR		 3369 if (WARN_ON(!state))
3370 return 0;
3371
c107acfe
MR		 3372 if (!cstate->base.active) {
3373 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
c107acfe
MR		 3374 return 0;
3375 }
3376
a6d3460e 3377 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3378 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3379 if (alloc_size == 0) {
3380 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3381 return 0;
b9cec075
DL		 3382 }
3383
c107acfe 3384 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3385 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3386 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3387
3388 alloc_size -= cursor_blocks;
b9cec075 3389
80958155 3390 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3391 for_each_plane_in_state(state, plane, pstate, i) {
3392 intel_plane = to_intel_plane(plane);
3393 id = skl_wm_plane_id(intel_plane);
c107acfe 3394
a6d3460e
MR		 3395 if (intel_plane->pipe != pipe)
3396 continue;
c107acfe 3397
936e71e3 3398 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3399 minimum[id] = 0;
3400 y_minimum[id] = 0;
3401 continue;
3402 }
3403 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3404 minimum[id] = 0;
3405 y_minimum[id] = 0;
3406 continue;
c107acfe 3407 }
a6d3460e 3408
cbcfd14b
KM		 3409 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3410 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3411 }
80958155 3412
c107acfe
MR		 3413 for (i = 0; i < PLANE_CURSOR; i++) {
3414 alloc_size -= minimum[i];
3415 alloc_size -= y_minimum[i];
80958155
DL		 3416 }
3417
b9cec075 3418 /*
80958155
DL		 3419 * 2. Distribute the remaining space in proportion to the amount of
3420 * data each plane needs to fetch from memory.
b9cec075
DL		 3421 *
3422 * FIXME: we may not allocate every single block here.
3423 */
024c9045 3424 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3425 if (total_data_rate == 0)
c107acfe 3426 return 0;
b9cec075 3427
34bb56af 3428 start = alloc->start;
024c9045 3429 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3430 unsigned int data_rate, y_data_rate;
3431 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3432 int id = skl_wm_plane_id(intel_plane);
b9cec075 3433
a1de91e5 3434 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3435
3436 /*
2cd601c6 3437 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3438 * promote the expression to 64 bits to avoid overflowing, the
3439 * result is < available as data_rate / total_data_rate < 1
3440 */
024c9045 3441 plane_blocks = minimum[id];
80958155
DL		 3442 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3443 total_data_rate);
b9cec075 3444
c107acfe
MR		 3445 /* Leave disabled planes at (0,0) */
3446 if (data_rate) {
3447 ddb->plane[pipe][id].start = start;
3448 ddb->plane[pipe][id].end = start + plane_blocks;
3449 }
b9cec075
DL		 3450
3451 start += plane_blocks;
2cd601c6
CK		 3452
3453 /*
3454 * allocation for y_plane part of planar format:
3455 */
a1de91e5
MR		 3456 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3457
3458 y_plane_blocks = y_minimum[id];
3459 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3460 total_data_rate);
2cd601c6 3461
c107acfe
MR		 3462 if (y_data_rate) {
3463 ddb->y_plane[pipe][id].start = start;
3464 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3465 }
a1de91e5
MR		 3466
3467 start += y_plane_blocks;
b9cec075
DL		 3468 }
3469
c107acfe 3470 return 0;
b9cec075
DL		 3471}
3472
5cec258b 3473static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3474{
3475 /* TODO: Take into account the scalers once we support them */
2d112de7 3476 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3477}
3478
3479/*
3480 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3481 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3482 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3483 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3484*/
ac484963 3485static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3486{
3487 uint32_t wm_intermediate_val, ret;
3488
3489 if (latency == 0)
3490 return UINT_MAX;
3491
ac484963 3492 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3493 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3494
3495 return ret;
3496}
3497
3498static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3499 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3500{
d4c2aa60 3501 uint32_t ret;
d4c2aa60 3502 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3503
3504 if (latency == 0)
3505 return UINT_MAX;
3506
2d41c0b5
PB		 3507 wm_intermediate_val = latency * pixel_rate;
3508 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3509 plane_blocks_per_line;
2d41c0b5
PB		 3510
3511 return ret;
3512}
3513
9c2f7a9d
KM		 3514static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3515 struct intel_plane_state *pstate)
3516{
3517 uint64_t adjusted_pixel_rate;
3518 uint64_t downscale_amount;
3519 uint64_t pixel_rate;
3520
3521 /* Shouldn't reach here on disabled planes... */
936e71e3 3522 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3523 return 0;
3524
3525 /*
3526 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3527 * with additional adjustments for plane-specific scaling.
3528 */
3529 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3530 downscale_amount = skl_plane_downscale_amount(pstate);
3531
3532 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3533 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3534
3535 return pixel_rate;
3536}
3537
55994c2c
MR		 3538static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3539 struct intel_crtc_state *cstate,
3540 struct intel_plane_state *intel_pstate,
3541 uint16_t ddb_allocation,
3542 int level,
3543 uint16_t *out_blocks, /* out */
3544 uint8_t *out_lines, /* out */
3545 bool *enabled /* out */)
2d41c0b5 3546{
33815fa5
MR		 3547 struct drm_plane_state *pstate = &intel_pstate->base;
3548 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3549 uint32_t latency = dev_priv->wm.skl_latency[level];
3550 uint32_t method1, method2;
3551 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3552 uint32_t res_blocks, res_lines;
3553 uint32_t selected_result;
ac484963 3554 uint8_t cpp;
a280f7dd 3555 uint32_t width = 0, height = 0;
9c2f7a9d 3556 uint32_t plane_pixel_rate;
75676ed4 3557 uint32_t y_tile_minimum, y_min_scanlines;
2d41c0b5 3558
936e71e3 3559 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3560 *enabled = false;
3561 return 0;
3562 }
2d41c0b5 3563
936e71e3
VS		 3564 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3565 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3566
33815fa5 3567 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3568 swap(width, height);
3569
ac484963 3570 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3571 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3572
1186fa85
PZ		 3573 if (intel_rotation_90_or_270(pstate->rotation)) {
3574 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3575 drm_format_plane_cpp(fb->pixel_format, 1) :
3576 drm_format_plane_cpp(fb->pixel_format, 0);
3577
3578 switch (cpp) {
3579 case 1:
3580 y_min_scanlines = 16;
3581 break;
3582 case 2:
3583 y_min_scanlines = 8;
3584 break;
1186fa85
PZ		 3585 case 4:
3586 y_min_scanlines = 4;
3587 break;
86a462bc
PZ		 3588 default:
3589 MISSING_CASE(cpp);
3590 return -EINVAL;
1186fa85
PZ		 3591 }
3592 } else {
3593 y_min_scanlines = 4;
3594 }
3595
7a1a8aed
PZ		 3596 plane_bytes_per_line = width * cpp;
3597 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3598 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3599 plane_blocks_per_line =
3600 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3601 plane_blocks_per_line /= y_min_scanlines;
3602 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3603 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3604 + 1;
3605 } else {
3606 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3607 }
3608
9c2f7a9d
KM		 3609 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3610 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3611 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3612 latency,
7a1a8aed 3613 plane_blocks_per_line);
2d41c0b5 3614
75676ed4
PZ		 3615 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3616
024c9045
MR		 3617 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3618 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3619 selected_result = max(method2, y_tile_minimum);
3620 } else {
f1db3eaf
PZ		 3621 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3622 (plane_bytes_per_line / 512 < 1))
3623 selected_result = method2;
3624 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3625 selected_result = min(method1, method2);
3626 else
3627 selected_result = method1;
3628 }
2d41c0b5 3629
d4c2aa60
TU		 3630 res_blocks = selected_result + 1;
3631 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3632
0fda6568 3633 if (level >= 1 && level <= 7) {
024c9045 3634 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3635 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3636 res_blocks += y_tile_minimum;
1186fa85 3637 res_lines += y_min_scanlines;
75676ed4 3638 } else {
0fda6568 3639 res_blocks++;
75676ed4 3640 }
0fda6568 3641 }
e6d66171 3642
55994c2c
MR		 3643 if (res_blocks >= ddb_allocation || res_lines > 31) {
3644 *enabled = false;
6b6bada7
MR		 3645
3646 /*
3647 * If there are no valid level 0 watermarks, then we can't
3648 * support this display configuration.
3649 */
3650 if (level) {
3651 return 0;
3652 } else {
3653 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3654 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3655 to_intel_crtc(cstate->base.crtc)->pipe,
3656 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3657 res_blocks, ddb_allocation, res_lines);
3658
3659 return -EINVAL;
3660 }
55994c2c 3661 }
e6d66171
DL		 3662
3663 *out_blocks = res_blocks;
3664 *out_lines = res_lines;
55994c2c 3665 *enabled = true;
2d41c0b5 3666
55994c2c 3667 return 0;
2d41c0b5
PB		 3668}
3669
f4a96752
MR		 3670static int
3671skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3672 struct skl_ddb_allocation *ddb,
3673 struct intel_crtc_state *cstate,
3674 int level,
3675 struct skl_wm_level *result)
2d41c0b5 3676{
f4a96752 3677 struct drm_atomic_state *state = cstate->base.state;
024c9045 3678 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3679 struct drm_plane *plane;
024c9045 3680 struct intel_plane *intel_plane;
33815fa5 3681 struct intel_plane_state *intel_pstate;
2d41c0b5 3682 uint16_t ddb_blocks;
024c9045 3683 enum pipe pipe = intel_crtc->pipe;
55994c2c 3684 int ret;
024c9045 3685
f4a96752
MR		 3686 /*
3687 * We'll only calculate watermarks for planes that are actually
3688 * enabled, so make sure all other planes are set as disabled.
3689 */
3690 memset(result, 0, sizeof(*result));
3691
91c8a326
CW		 3692 for_each_intel_plane_mask(&dev_priv->drm,
3693 intel_plane,
3694 cstate->base.plane_mask) {
024c9045 3695 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3696
f4a96752
MR		 3697 plane = &intel_plane->base;
3698 intel_pstate = NULL;
3699 if (state)
3700 intel_pstate =
3701 intel_atomic_get_existing_plane_state(state,
3702 intel_plane);
3703
3704 /*
3705 * Note: If we start supporting multiple pending atomic commits
3706 * against the same planes/CRTC's in the future, plane->state
3707 * will no longer be the correct pre-state to use for the
3708 * calculations here and we'll need to change where we get the
3709 * 'unchanged' plane data from.
3710 *
3711 * For now this is fine because we only allow one queued commit
3712 * against a CRTC. Even if the plane isn't modified by this
3713 * transaction and we don't have a plane lock, we still have
3714 * the CRTC's lock, so we know that no other transactions are
3715 * racing with us to update it.
3716 */
3717 if (!intel_pstate)
3718 intel_pstate = to_intel_plane_state(plane->state);
3719
3720 WARN_ON(!intel_pstate->base.fb);
3721
2d41c0b5
PB		 3722 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3723
55994c2c
MR		 3724 ret = skl_compute_plane_wm(dev_priv,
3725 cstate,
3726 intel_pstate,
3727 ddb_blocks,
3728 level,
3729 &result->plane_res_b[i],
3730 &result->plane_res_l[i],
3731 &result->plane_en[i]);
3732 if (ret)
3733 return ret;
2d41c0b5 3734 }
f4a96752
MR		 3735
3736 return 0;
2d41c0b5
PB		 3737}
3738
407b50f3 3739static uint32_t
024c9045 3740skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3741{
024c9045 3742 if (!cstate->base.active)
407b50f3
DL		 3743 return 0;
3744
024c9045 3745 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3746 return 0;
407b50f3 3747
024c9045
MR		 3748 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3749 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3750}
3751
024c9045 3752static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3753 struct skl_wm_level *trans_wm /* out */)
407b50f3 3754{
024c9045 3755 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3756 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3757 struct intel_plane *intel_plane;
9414f563 3758
024c9045 3759 if (!cstate->base.active)
407b50f3 3760 return;
9414f563
DL		 3761
3762 /* Until we know more, just disable transition WMs */
024c9045
MR		 3763 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3764 int i = skl_wm_plane_id(intel_plane);
3765
9414f563 3766 trans_wm->plane_en[i] = false;
024c9045 3767 }
407b50f3
DL		 3768}
3769
55994c2c
MR		 3770static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3771 struct skl_ddb_allocation *ddb,
3772 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3773{
024c9045 3774 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3775 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3776 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3777 int ret;
2d41c0b5
PB		 3778
3779 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3780 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3781 level, &pipe_wm->wm[level]);
3782 if (ret)
3783 return ret;
2d41c0b5 3784 }
024c9045 3785 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3786
024c9045 3787 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3788
3789 return 0;
2d41c0b5
PB		 3790}
3791
3792static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3793 struct skl_pipe_wm *p_wm,
3794 struct skl_wm_values *r,
3795 struct intel_crtc *intel_crtc)
3796{
3797 int level, max_level = ilk_wm_max_level(dev);
3798 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3799 uint32_t temp;
3800 int i;
2d41c0b5
PB		 3801
3802 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3803 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3804 temp = 0;
2d41c0b5
PB		 3805
3806 temp |= p_wm->wm[level].plane_res_l[i] <<
3807 PLANE_WM_LINES_SHIFT;
3808 temp |= p_wm->wm[level].plane_res_b[i];
3809 if (p_wm->wm[level].plane_en[i])
3810 temp |= PLANE_WM_EN;
3811
3812 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3813 }
3814
3815 temp = 0;
2d41c0b5 3816
4969d33e
MR		 3817 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3818 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3819
4969d33e 3820 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3821 temp |= PLANE_WM_EN;
3822
4969d33e 3823 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3824
3825 }
3826
9414f563
DL		 3827 /* transition WMs */
3828 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3829 temp = 0;
3830 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3831 temp |= p_wm->trans_wm.plane_res_b[i];
3832 if (p_wm->trans_wm.plane_en[i])
3833 temp |= PLANE_WM_EN;
3834
3835 r->plane_trans[pipe][i] = temp;
3836 }
3837
3838 temp = 0;
4969d33e
MR		 3839 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3840 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3841 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3842 temp |= PLANE_WM_EN;
3843
4969d33e 3844 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3845
2d41c0b5
PB		 3846 r->wm_linetime[pipe] = p_wm->linetime;
3847}
3848
f0f59a00
VS		 3849static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3850 i915_reg_t reg,
16160e3d
DL		 3851 const struct skl_ddb_entry *entry)
3852{
3853 if (entry->end)
3854 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3855 else
3856 I915_WRITE(reg, 0);
3857}
3858
62e0fb88
L		 3859void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3860 const struct skl_wm_values *wm,
3861 int plane)
3862{
3863 struct drm_crtc *crtc = &intel_crtc->base;
3864 struct drm_device *dev = crtc->dev;
3865 struct drm_i915_private *dev_priv = to_i915(dev);
3866 int level, max_level = ilk_wm_max_level(dev);
3867 enum pipe pipe = intel_crtc->pipe;
3868
3869 for (level = 0; level <= max_level; level++) {
3870 I915_WRITE(PLANE_WM(pipe, plane, level),
3871 wm->plane[pipe][plane][level]);
3872 }
3873 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3874
3875 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3876 &wm->ddb.plane[pipe][plane]);
3877 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3878 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3879}
3880
3881void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3882 const struct skl_wm_values *wm)
3883{
3884 struct drm_crtc *crtc = &intel_crtc->base;
3885 struct drm_device *dev = crtc->dev;
3886 struct drm_i915_private *dev_priv = to_i915(dev);
3887 int level, max_level = ilk_wm_max_level(dev);
3888 enum pipe pipe = intel_crtc->pipe;
3889
3890 for (level = 0; level <= max_level; level++) {
3891 I915_WRITE(CUR_WM(pipe, level),
3892 wm->plane[pipe][PLANE_CURSOR][level]);
3893 }
3894 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3895
27082493
L		 3896 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3897 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3898}
3899
27082493
L		 3900bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3901 const struct skl_ddb_allocation *new,
3902 enum pipe pipe)
0e8fb7ba 3903{
27082493
L		 3904 return new->pipe[pipe].start == old->pipe[pipe].start &&
3905 new->pipe[pipe].end == old->pipe[pipe].end;
0e8fb7ba
DL		 3906}
3907
27082493
L		 3908static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3909 const struct skl_ddb_entry *b)
0e8fb7ba 3910{
27082493 3911 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3912}
3913
27082493
L		 3914bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3915 const struct skl_ddb_allocation *old,
3916 const struct skl_ddb_allocation *new,
3917 enum pipe pipe)
0e8fb7ba 3918{
27082493
L		 3919 struct drm_device *dev = state->dev;
3920 struct intel_crtc *intel_crtc;
3921 enum pipe otherp;
0e8fb7ba 3922
27082493
L		 3923 for_each_intel_crtc(dev, intel_crtc) {
3924 otherp = intel_crtc->pipe;
0e8fb7ba 3925
27082493 3926 if (otherp == pipe)
0e8fb7ba
DL		 3927 continue;
3928
27082493
L		 3929 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3930 &old->pipe[otherp]))
3931 return true;
0e8fb7ba
DL		 3932 }
3933
27082493 3934 return false;
0e8fb7ba
DL		 3935}
3936
55994c2c
MR		 3937static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3938 struct skl_ddb_allocation *ddb, /* out */
3939 struct skl_pipe_wm *pipe_wm, /* out */
3940 bool *changed /* out */)
2d41c0b5 3941{
f4a96752
MR		 3942 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3943 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3944 int ret;
2d41c0b5 3945
55994c2c
MR		 3946 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3947 if (ret)
3948 return ret;
2d41c0b5 3949
4e0963c7 3950 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3951 *changed = false;
3952 else
3953 *changed = true;
2d41c0b5 3954
55994c2c 3955 return 0;
2d41c0b5
PB		 3956}
3957
9b613022
MR		 3958static uint32_t
3959pipes_modified(struct drm_atomic_state *state)
3960{
3961 struct drm_crtc *crtc;
3962 struct drm_crtc_state *cstate;
3963 uint32_t i, ret = 0;
3964
3965 for_each_crtc_in_state(state, crtc, cstate, i)
3966 ret |= drm_crtc_mask(crtc);
3967
3968 return ret;
3969}
3970
bb7791bd 3971static int
7f60e200
PZ		 3972skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3973{
3974 struct drm_atomic_state *state = cstate->base.state;
3975 struct drm_device *dev = state->dev;
3976 struct drm_crtc *crtc = cstate->base.crtc;
3977 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3978 struct drm_i915_private *dev_priv = to_i915(dev);
3979 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3980 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3981 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3982 struct drm_plane_state *plane_state;
3983 struct drm_plane *plane;
3984 enum pipe pipe = intel_crtc->pipe;
3985 int id;
3986
3987 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3988
3989 drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3990 id = skl_wm_plane_id(to_intel_plane(plane));
3991
3992 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3993 &new_ddb->plane[pipe][id]) &&
3994 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
3995 &new_ddb->y_plane[pipe][id]))
3996 continue;
3997
3998 plane_state = drm_atomic_get_plane_state(state, plane);
3999 if (IS_ERR(plane_state))
4000 return PTR_ERR(plane_state);
4001 }
4002
4003 return 0;
4004}
4005
98d39494
MR		 4006static int
4007skl_compute_ddb(struct drm_atomic_state *state)
4008{
4009 struct drm_device *dev = state->dev;
4010 struct drm_i915_private *dev_priv = to_i915(dev);
4011 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4012 struct intel_crtc *intel_crtc;
734fa01f 4013 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4014 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4015 int ret;
4016
4017 /*
4018 * If this is our first atomic update following hardware readout,
4019 * we can't trust the DDB that the BIOS programmed for us. Let's
4020 * pretend that all pipes switched active status so that we'll
4021 * ensure a full DDB recompute.
4022 */
1b54a880
MR		 4023 if (dev_priv->wm.distrust_bios_wm) {
4024 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4025 state->acquire_ctx);
4026 if (ret)
4027 return ret;
4028
98d39494
MR		 4029 intel_state->active_pipe_changes = ~0;
4030
1b54a880
MR		 4031 /*
4032 * We usually only initialize intel_state->active_crtcs if we
4033 * we're doing a modeset; make sure this field is always
4034 * initialized during the sanitization process that happens
4035 * on the first commit too.
4036 */
4037 if (!intel_state->modeset)
4038 intel_state->active_crtcs = dev_priv->active_crtcs;
4039 }
4040
98d39494
MR		 4041 /*
4042 * If the modeset changes which CRTC's are active, we need to
4043 * recompute the DDB allocation for *all* active pipes, even
4044 * those that weren't otherwise being modified in any way by this
4045 * atomic commit. Due to the shrinking of the per-pipe allocations
4046 * when new active CRTC's are added, it's possible for a pipe that
4047 * we were already using and aren't changing at all here to suddenly
4048 * become invalid if its DDB needs exceeds its new allocation.
4049 *
4050 * Note that if we wind up doing a full DDB recompute, we can't let
4051 * any other display updates race with this transaction, so we need
4052 * to grab the lock on *all* CRTC's.
4053 */
734fa01f 4054 if (intel_state->active_pipe_changes) {
98d39494 4055 realloc_pipes = ~0;
734fa01f
MR		 4056 intel_state->wm_results.dirty_pipes = ~0;
4057 }
98d39494 4058
5a920b85
PZ		 4059 /*
4060 * We're not recomputing for the pipes not included in the commit, so
4061 * make sure we start with the current state.
4062 */
4063 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4064
98d39494
MR		 4065 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4066 struct intel_crtc_state *cstate;
4067
4068 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4069 if (IS_ERR(cstate))
4070 return PTR_ERR(cstate);
4071
734fa01f 4072 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4073 if (ret)
4074 return ret;
05a76d3d 4075
7f60e200 4076 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4077 if (ret)
4078 return ret;
98d39494
MR		 4079 }
4080
4081 return 0;
4082}
4083
2722efb9
MR		 4084static void
4085skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4086 struct skl_wm_values *src,
4087 enum pipe pipe)
4088{
4089 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4090 memcpy(dst->plane[pipe], src->plane[pipe],
4091 sizeof(dst->plane[pipe]));
4092 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4093 sizeof(dst->plane_trans[pipe]));
4094
4095 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4096 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4097 sizeof(dst->ddb.y_plane[pipe]));
4098 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4099 sizeof(dst->ddb.plane[pipe]));
4100}
4101
98d39494
MR		 4102static int
4103skl_compute_wm(struct drm_atomic_state *state)
4104{
4105 struct drm_crtc *crtc;
4106 struct drm_crtc_state *cstate;
734fa01f
MR		 4107 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4108 struct skl_wm_values *results = &intel_state->wm_results;
4109 struct skl_pipe_wm *pipe_wm;
98d39494 4110 bool changed = false;
734fa01f 4111 int ret, i;
98d39494
MR		 4112
4113 /*
4114 * If this transaction isn't actually touching any CRTC's, don't
4115 * bother with watermark calculation. Note that if we pass this
4116 * test, we're guaranteed to hold at least one CRTC state mutex,
4117 * which means we can safely use values like dev_priv->active_crtcs
4118 * since any racing commits that want to update them would need to
4119 * hold _all_ CRTC state mutexes.
4120 */
4121 for_each_crtc_in_state(state, crtc, cstate, i)
4122 changed = true;
4123 if (!changed)
4124 return 0;
4125
734fa01f
MR		 4126 /* Clear all dirty flags */
4127 results->dirty_pipes = 0;
4128
98d39494
MR		 4129 ret = skl_compute_ddb(state);
4130 if (ret)
4131 return ret;
4132
734fa01f
MR		 4133 /*
4134 * Calculate WM's for all pipes that are part of this transaction.
4135 * Note that the DDB allocation above may have added more CRTC's that
4136 * weren't otherwise being modified (and set bits in dirty_pipes) if
4137 * pipe allocations had to change.
4138 *
4139 * FIXME: Now that we're doing this in the atomic check phase, we
4140 * should allow skl_update_pipe_wm() to return failure in cases where
4141 * no suitable watermark values can be found.
4142 */
4143 for_each_crtc_in_state(state, crtc, cstate, i) {
4144 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4145 struct intel_crtc_state *intel_cstate =
4146 to_intel_crtc_state(cstate);
4147
4148 pipe_wm = &intel_cstate->wm.skl.optimal;
4149 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4150 &changed);
4151 if (ret)
4152 return ret;
4153
4154 if (changed)
4155 results->dirty_pipes |= drm_crtc_mask(crtc);
4156
4157 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4158 /* This pipe's WM's did not change */
4159 continue;
4160
4161 intel_cstate->update_wm_pre = true;
4162 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4163 }
4164
98d39494
MR		 4165 return 0;
4166}
4167
2d41c0b5
PB		 4168static void skl_update_wm(struct drm_crtc *crtc)
4169{
4170 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4171 struct drm_device *dev = crtc->dev;
fac5e23e 4172 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4173 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4174 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4175 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4176 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4177 enum pipe pipe = intel_crtc->pipe;
adda50b8 4178
734fa01f 4179 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4180 return;
4181
734fa01f
MR		 4182 intel_crtc->wm.active.skl = *pipe_wm;
4183
4184 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4185
2722efb9 4186 /*
27082493
L		 4187 * If this pipe isn't active already, we're going to be enabling it
4188 * very soon. Since it's safe to update a pipe's ddb allocation while
4189 * the pipe's shut off, just do so here. Already active pipes will have
4190 * their watermarks updated once we update their planes.
2722efb9 4191 */
27082493
L		 4192 if (crtc->state->active_changed) {
4193 int plane;
4194
4195 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4196 skl_write_plane_wm(intel_crtc, results, plane);
4197
4198 skl_write_cursor_wm(intel_crtc, results);
4199 }
4200
4201 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4202
4203 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4204}
4205
d890565c
VS		 4206static void ilk_compute_wm_config(struct drm_device *dev,
4207 struct intel_wm_config *config)
4208{
4209 struct intel_crtc *crtc;
4210
4211 /* Compute the currently _active_ config */
4212 for_each_intel_crtc(dev, crtc) {
4213 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4214
4215 if (!wm->pipe_enabled)
4216 continue;
4217
4218 config->sprites_enabled |= wm->sprites_enabled;
4219 config->sprites_scaled |= wm->sprites_scaled;
4220 config->num_pipes_active++;
4221 }
4222}
4223
ed4a6a7c 4224static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4225{
91c8a326 4226 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4227 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4228 struct ilk_wm_maximums max;
d890565c 4229 struct intel_wm_config config = {};
820c1980 4230 struct ilk_wm_values results = {};
77c122bc 4231 enum intel_ddb_partitioning partitioning;
261a27d1 4232
d890565c
VS		 4233 ilk_compute_wm_config(dev, &config);
4234
4235 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4236 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4237
4238 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4239 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4240 config.num_pipes_active == 1 && config.sprites_enabled) {
4241 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4242 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4243
820c1980 4244 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4245 } else {
198a1e9b 4246 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4247 }
4248
198a1e9b 4249 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4250 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4251
820c1980 4252 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4253
820c1980 4254 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4255}
4256
ed4a6a7c 4257static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4258{
ed4a6a7c
MR		 4259 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4260 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4261
ed4a6a7c 4262 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4263 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4264 ilk_program_watermarks(dev_priv);
4265 mutex_unlock(&dev_priv->wm.wm_mutex);
4266}
bf220452 4267
ed4a6a7c
MR		 4268static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4269{
4270 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4271 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4272
ed4a6a7c
MR		 4273 mutex_lock(&dev_priv->wm.wm_mutex);
4274 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4275 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4276 ilk_program_watermarks(dev_priv);
4277 }
4278 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4279}
4280
3078999f
PB		 4281static void skl_pipe_wm_active_state(uint32_t val,
4282 struct skl_pipe_wm *active,
4283 bool is_transwm,
4284 bool is_cursor,
4285 int i,
4286 int level)
4287{
4288 bool is_enabled = (val & PLANE_WM_EN) != 0;
4289
4290 if (!is_transwm) {
4291 if (!is_cursor) {
4292 active->wm[level].plane_en[i] = is_enabled;
4293 active->wm[level].plane_res_b[i] =
4294 val & PLANE_WM_BLOCKS_MASK;
4295 active->wm[level].plane_res_l[i] =
4296 (val >> PLANE_WM_LINES_SHIFT) &
4297 PLANE_WM_LINES_MASK;
4298 } else {
4969d33e
MR		 4299 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4300 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4301 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4302 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4303 (val >> PLANE_WM_LINES_SHIFT) &
4304 PLANE_WM_LINES_MASK;
4305 }
4306 } else {
4307 if (!is_cursor) {
4308 active->trans_wm.plane_en[i] = is_enabled;
4309 active->trans_wm.plane_res_b[i] =
4310 val & PLANE_WM_BLOCKS_MASK;
4311 active->trans_wm.plane_res_l[i] =
4312 (val >> PLANE_WM_LINES_SHIFT) &
4313 PLANE_WM_LINES_MASK;
4314 } else {
4969d33e
MR		 4315 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4316 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4317 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4318 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4319 (val >> PLANE_WM_LINES_SHIFT) &
4320 PLANE_WM_LINES_MASK;
4321 }
4322 }
4323}
4324
4325static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4326{
4327 struct drm_device *dev = crtc->dev;
fac5e23e 4328 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4329 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4330 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4331 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4332 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4333 enum pipe pipe = intel_crtc->pipe;
4334 int level, i, max_level;
4335 uint32_t temp;
4336
4337 max_level = ilk_wm_max_level(dev);
4338
4339 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4340
4341 for (level = 0; level <= max_level; level++) {
4342 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4343 hw->plane[pipe][i][level] =
4344 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4345 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4346 }
4347
4348 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4349 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4350 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4351
3ef00284 4352 if (!intel_crtc->active)
3078999f
PB		 4353 return;
4354
2b4b9f35 4355 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4356
4357 active->linetime = hw->wm_linetime[pipe];
4358
4359 for (level = 0; level <= max_level; level++) {
4360 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4361 temp = hw->plane[pipe][i][level];
4362 skl_pipe_wm_active_state(temp, active, false,
4363 false, i, level);
4364 }
4969d33e 4365 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4366 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4367 }
4368
4369 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4370 temp = hw->plane_trans[pipe][i];
4371 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4372 }
4373
4969d33e 4374 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4375 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4376
4377 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4378}
4379
4380void skl_wm_get_hw_state(struct drm_device *dev)
4381{
fac5e23e 4382 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4383 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4384 struct drm_crtc *crtc;
4385
a269c583 4386 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4387 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4388 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4389
279e99d7
MR		 4390 if (dev_priv->active_crtcs) {
4391 /* Fully recompute DDB on first atomic commit */
4392 dev_priv->wm.distrust_bios_wm = true;
4393 } else {
4394 /* Easy/common case; just sanitize DDB now if everything off */
4395 memset(ddb, 0, sizeof(*ddb));
4396 }
3078999f
PB		 4397}
4398
243e6a44
VS		 4399static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4400{
4401 struct drm_device *dev = crtc->dev;
fac5e23e 4402 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4403 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4404 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4405 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4406 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4407 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4408 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4409 [PIPE_A] = WM0_PIPEA_ILK,
4410 [PIPE_B] = WM0_PIPEB_ILK,
4411 [PIPE_C] = WM0_PIPEC_IVB,
4412 };
4413
4414 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
a42a5719 4415 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ce0e0713 4416 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4417
15606534
VS		 4418 memset(active, 0, sizeof(*active));
4419
3ef00284 4420 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4421
4422 if (active->pipe_enabled) {
243e6a44
VS		 4423 u32 tmp = hw->wm_pipe[pipe];
4424
4425 /*
4426 * For active pipes LP0 watermark is marked as
4427 * enabled, and LP1+ watermaks as disabled since
4428 * we can't really reverse compute them in case
4429 * multiple pipes are active.
4430 */
4431 active->wm[0].enable = true;
4432 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4433 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4434 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4435 active->linetime = hw->wm_linetime[pipe];
4436 } else {
4437 int level, max_level = ilk_wm_max_level(dev);
4438
4439 /*
4440 * For inactive pipes, all watermark levels
4441 * should be marked as enabled but zeroed,
4442 * which is what we'd compute them to.
4443 */
4444 for (level = 0; level <= max_level; level++)
4445 active->wm[level].enable = true;
4446 }
4e0963c7
MR		 4447
4448 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4449}
4450
6eb1a681
VS		 4451#define _FW_WM(value, plane) \
4452 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4453#define _FW_WM_VLV(value, plane) \
4454 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4455
4456static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4457 struct vlv_wm_values *wm)
4458{
4459 enum pipe pipe;
4460 uint32_t tmp;
4461
4462 for_each_pipe(dev_priv, pipe) {
4463 tmp = I915_READ(VLV_DDL(pipe));
4464
4465 wm->ddl[pipe].primary =
4466 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4467 wm->ddl[pipe].cursor =
4468 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4469 wm->ddl[pipe].sprite[0] =
4470 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4471 wm->ddl[pipe].sprite[1] =
4472 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4473 }
4474
4475 tmp = I915_READ(DSPFW1);
4476 wm->sr.plane = _FW_WM(tmp, SR);
4477 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4478 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4479 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4480
4481 tmp = I915_READ(DSPFW2);
4482 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4483 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4484 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4485
4486 tmp = I915_READ(DSPFW3);
4487 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4488
4489 if (IS_CHERRYVIEW(dev_priv)) {
4490 tmp = I915_READ(DSPFW7_CHV);
4491 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4492 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4493
4494 tmp = I915_READ(DSPFW8_CHV);
4495 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4496 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4497
4498 tmp = I915_READ(DSPFW9_CHV);
4499 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4500 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4501
4502 tmp = I915_READ(DSPHOWM);
4503 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4504 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4505 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4506 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4507 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4508 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4509 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4510 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4511 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4512 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4513 } else {
4514 tmp = I915_READ(DSPFW7);
4515 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4516 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4517
4518 tmp = I915_READ(DSPHOWM);
4519 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4520 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4521 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4522 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4523 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4524 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4525 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4526 }
4527}
4528
4529#undef _FW_WM
4530#undef _FW_WM_VLV
4531
4532void vlv_wm_get_hw_state(struct drm_device *dev)
4533{
4534 struct drm_i915_private *dev_priv = to_i915(dev);
4535 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4536 struct intel_plane *plane;
4537 enum pipe pipe;
4538 u32 val;
4539
4540 vlv_read_wm_values(dev_priv, wm);
4541
4542 for_each_intel_plane(dev, plane) {
4543 switch (plane->base.type) {
4544 int sprite;
4545 case DRM_PLANE_TYPE_CURSOR:
4546 plane->wm.fifo_size = 63;
4547 break;
4548 case DRM_PLANE_TYPE_PRIMARY:
4549 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4550 break;
4551 case DRM_PLANE_TYPE_OVERLAY:
4552 sprite = plane->plane;
4553 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4554 break;
4555 }
4556 }
4557
4558 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4559 wm->level = VLV_WM_LEVEL_PM2;
4560
4561 if (IS_CHERRYVIEW(dev_priv)) {
4562 mutex_lock(&dev_priv->rps.hw_lock);
4563
4564 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4565 if (val & DSP_MAXFIFO_PM5_ENABLE)
4566 wm->level = VLV_WM_LEVEL_PM5;
4567
58590c14
VS		 4568 /*
4569 * If DDR DVFS is disabled in the BIOS, Punit
4570 * will never ack the request. So if that happens
4571 * assume we don't have to enable/disable DDR DVFS
4572 * dynamically. To test that just set the REQ_ACK
4573 * bit to poke the Punit, but don't change the
4574 * HIGH/LOW bits so that we don't actually change
4575 * the current state.
4576 */
6eb1a681 4577 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4578 val |= FORCE_DDR_FREQ_REQ_ACK;
4579 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4580
4581 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4582 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4583 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4584 "assuming DDR DVFS is disabled\n");
4585 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4586 } else {
4587 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4588 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4589 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4590 }
6eb1a681
VS		 4591
4592 mutex_unlock(&dev_priv->rps.hw_lock);
4593 }
4594
4595 for_each_pipe(dev_priv, pipe)
4596 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4597 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4598 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4599
4600 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4601 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4602}
4603
243e6a44
VS		 4604void ilk_wm_get_hw_state(struct drm_device *dev)
4605{
fac5e23e 4606 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4607 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4608 struct drm_crtc *crtc;
4609
70e1e0ec 4610 for_each_crtc(dev, crtc)
243e6a44
VS		 4611 ilk_pipe_wm_get_hw_state(crtc);
4612
4613 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4614 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4615 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4616
4617 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4618 if (INTEL_INFO(dev)->gen >= 7) {
4619 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4620 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4621 }
243e6a44 4622
a42a5719 4623 if (IS_HASWELL(dev) || IS_BROADWELL(dev))
ac9545fd
VS		 4624 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4625 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
4626 else if (IS_IVYBRIDGE(dev))
4627 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4628 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4629
4630 hw->enable_fbc_wm =
4631 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4632}
4633
b445e3b0
ED		 4634/**
4635 * intel_update_watermarks - update FIFO watermark values based on current modes
4636 *
4637 * Calculate watermark values for the various WM regs based on current mode
4638 * and plane configuration.
4639 *
4640 * There are several cases to deal with here:
4641 * - normal (i.e. non-self-refresh)
4642 * - self-refresh (SR) mode
4643 * - lines are large relative to FIFO size (buffer can hold up to 2)
4644 * - lines are small relative to FIFO size (buffer can hold more than 2
4645 * lines), so need to account for TLB latency
4646 *
4647 * The normal calculation is:
4648 * watermark = dotclock * bytes per pixel * latency
4649 * where latency is platform & configuration dependent (we assume pessimal
4650 * values here).
4651 *
4652 * The SR calculation is:
4653 * watermark = (trunc(latency/line time)+1) * surface width *
4654 * bytes per pixel
4655 * where
4656 * line time = htotal / dotclock
4657 * surface width = hdisplay for normal plane and 64 for cursor
4658 * and latency is assumed to be high, as above.
4659 *
4660 * The final value programmed to the register should always be rounded up,
4661 * and include an extra 2 entries to account for clock crossings.
4662 *
4663 * We don't use the sprite, so we can ignore that. And on Crestline we have
4664 * to set the non-SR watermarks to 8.
4665 */
46ba614c 4666void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4667{
fac5e23e 4668 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4669
4670 if (dev_priv->display.update_wm)
46ba614c 4671 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4672}
4673
e2828914 4674/*
9270388e 4675 * Lock protecting IPS related data structures
9270388e
DV		 4676 */
4677DEFINE_SPINLOCK(mchdev_lock);
4678
4679/* Global for IPS driver to get at the current i915 device. Protected by
4680 * mchdev_lock. */
4681static struct drm_i915_private *i915_mch_dev;
4682
91d14251 4683bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4684{
2b4e57bd
ED		 4685 u16 rgvswctl;
4686
9270388e
DV		 4687 assert_spin_locked(&mchdev_lock);
4688
2b4e57bd
ED		 4689 rgvswctl = I915_READ16(MEMSWCTL);
4690 if (rgvswctl & MEMCTL_CMD_STS) {
4691 DRM_DEBUG("gpu busy, RCS change rejected\n");
4692 return false; /* still busy with another command */
4693 }
4694
4695 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4696 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4697 I915_WRITE16(MEMSWCTL, rgvswctl);
4698 POSTING_READ16(MEMSWCTL);
4699
4700 rgvswctl |= MEMCTL_CMD_STS;
4701 I915_WRITE16(MEMSWCTL, rgvswctl);
4702
4703 return true;
4704}
4705
91d14251 4706static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4707{
84f1b20f 4708 u32 rgvmodectl;
2b4e57bd
ED		 4709 u8 fmax, fmin, fstart, vstart;
4710
9270388e
DV		 4711 spin_lock_irq(&mchdev_lock);
4712
84f1b20f
TU		 4713 rgvmodectl = I915_READ(MEMMODECTL);
4714
2b4e57bd
ED		 4715 /* Enable temp reporting */
4716 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4717 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4718
4719 /* 100ms RC evaluation intervals */
4720 I915_WRITE(RCUPEI, 100000);
4721 I915_WRITE(RCDNEI, 100000);
4722
4723 /* Set max/min thresholds to 90ms and 80ms respectively */
4724 I915_WRITE(RCBMAXAVG, 90000);
4725 I915_WRITE(RCBMINAVG, 80000);
4726
4727 I915_WRITE(MEMIHYST, 1);
4728
4729 /* Set up min, max, and cur for interrupt handling */
4730 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4731 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4732 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4733 MEMMODE_FSTART_SHIFT;
4734
616847e7 4735 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4736 PXVFREQ_PX_SHIFT;
4737
20e4d407
DV		 4738 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4739 dev_priv->ips.fstart = fstart;
2b4e57bd 4740
20e4d407
DV		 4741 dev_priv->ips.max_delay = fstart;
4742 dev_priv->ips.min_delay = fmin;
4743 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4744
4745 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4746 fmax, fmin, fstart);
4747
4748 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4749
4750 /*
4751 * Interrupts will be enabled in ironlake_irq_postinstall
4752 */
4753
4754 I915_WRITE(VIDSTART, vstart);
4755 POSTING_READ(VIDSTART);
4756
4757 rgvmodectl |= MEMMODE_SWMODE_EN;
4758 I915_WRITE(MEMMODECTL, rgvmodectl);
4759
9270388e 4760 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4761 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4762 mdelay(1);
2b4e57bd 4763
91d14251 4764 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4765
7d81c3e0
VS		 4766 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4767 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4768 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4769 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4770 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4771
4772 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4773}
4774
91d14251 4775static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4776{
9270388e
DV		 4777 u16 rgvswctl;
4778
4779 spin_lock_irq(&mchdev_lock);
4780
4781 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4782
4783 /* Ack interrupts, disable EFC interrupt */
4784 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4785 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4786 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4787 I915_WRITE(DEIIR, DE_PCU_EVENT);
4788 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4789
4790 /* Go back to the starting frequency */
91d14251 4791 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4792 mdelay(1);
2b4e57bd
ED		 4793 rgvswctl |= MEMCTL_CMD_STS;
4794 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4795 mdelay(1);
2b4e57bd 4796
9270388e 4797 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4798}
4799
acbe9475
DV		 4800/* There's a funny hw issue where the hw returns all 0 when reading from
4801 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4802 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4803 * all limits and the gpu stuck at whatever frequency it is at atm).
4804 */
74ef1173 4805static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4806{
7b9e0ae6 4807 u32 limits;
2b4e57bd 4808
20b46e59
DV		 4809 /* Only set the down limit when we've reached the lowest level to avoid
4810 * getting more interrupts, otherwise leave this clear. This prevents a
4811 * race in the hw when coming out of rc6: There's a tiny window where
4812 * the hw runs at the minimal clock before selecting the desired
4813 * frequency, if the down threshold expires in that window we will not
4814 * receive a down interrupt. */
2d1fe073 4815 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4816 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4817 if (val <= dev_priv->rps.min_freq_softlimit)
4818 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4819 } else {
4820 limits = dev_priv->rps.max_freq_softlimit << 24;
4821 if (val <= dev_priv->rps.min_freq_softlimit)
4822 limits |= dev_priv->rps.min_freq_softlimit << 16;
4823 }
20b46e59
DV		 4824
4825 return limits;
4826}
4827
dd75fdc8
CW		 4828static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4829{
4830 int new_power;
8a586437
AG		 4831 u32 threshold_up = 0, threshold_down = 0; /* in % */
4832 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4833
4834 new_power = dev_priv->rps.power;
4835 switch (dev_priv->rps.power) {
4836 case LOW_POWER:
a72b5623
CW		 4837 if (val > dev_priv->rps.efficient_freq + 1 &&
4838 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4839 new_power = BETWEEN;
4840 break;
4841
4842 case BETWEEN:
a72b5623
CW		 4843 if (val <= dev_priv->rps.efficient_freq &&
4844 val < dev_priv->rps.cur_freq)
dd75fdc8 4845 new_power = LOW_POWER;
a72b5623
CW		 4846 else if (val >= dev_priv->rps.rp0_freq &&
4847 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4848 new_power = HIGH_POWER;
4849 break;
4850
4851 case HIGH_POWER:
a72b5623
CW		 4852 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4853 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4854 new_power = BETWEEN;
4855 break;
4856 }
4857 /* Max/min bins are special */
aed242ff 4858 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4859 new_power = LOW_POWER;
aed242ff 4860 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4861 new_power = HIGH_POWER;
4862 if (new_power == dev_priv->rps.power)
4863 return;
4864
4865 /* Note the units here are not exactly 1us, but 1280ns. */
4866 switch (new_power) {
4867 case LOW_POWER:
4868 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4869 ei_up = 16000;
4870 threshold_up = 95;
dd75fdc8
CW		 4871
4872 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4873 ei_down = 32000;
4874 threshold_down = 85;
dd75fdc8
CW		 4875 break;
4876
4877 case BETWEEN:
4878 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4879 ei_up = 13000;
4880 threshold_up = 90;
dd75fdc8
CW		 4881
4882 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4883 ei_down = 32000;
4884 threshold_down = 75;
dd75fdc8
CW		 4885 break;
4886
4887 case HIGH_POWER:
4888 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4889 ei_up = 10000;
4890 threshold_up = 85;
dd75fdc8
CW		 4891
4892 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4893 ei_down = 32000;
4894 threshold_down = 60;
dd75fdc8
CW		 4895 break;
4896 }
4897
8a586437 4898 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4899 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4900 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4901 GT_INTERVAL_FROM_US(dev_priv,
4902 ei_up * threshold_up / 100));
8a586437
AG		 4903
4904 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4905 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4906 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4907 GT_INTERVAL_FROM_US(dev_priv,
4908 ei_down * threshold_down / 100));
4909
4910 I915_WRITE(GEN6_RP_CONTROL,
4911 GEN6_RP_MEDIA_TURBO |
4912 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4913 GEN6_RP_MEDIA_IS_GFX |
4914 GEN6_RP_ENABLE |
4915 GEN6_RP_UP_BUSY_AVG |
4916 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4917
dd75fdc8 4918 dev_priv->rps.power = new_power;
8fb55197
CW		 4919 dev_priv->rps.up_threshold = threshold_up;
4920 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4921 dev_priv->rps.last_adj = 0;
4922}
4923
2876ce73
CW		 4924static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4925{
4926 u32 mask = 0;
4927
4928 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4929 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4930 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4931 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4932
7b3c29f6
CW		 4933 mask &= dev_priv->pm_rps_events;
4934
59d02a1f 4935 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4936}
4937
b8a5ff8d
JM		 4938/* gen6_set_rps is called to update the frequency request, but should also be
4939 * called when the range (min_delay and max_delay) is modified so that we can
4940 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4941static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4942{
23eafea6 4943 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4944 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4945 return;
4946
4fc688ce 4947 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4948 WARN_ON(val > dev_priv->rps.max_freq);
4949 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4950
eb64cad1
CW		 4951 /* min/max delay may still have been modified so be sure to
4952 * write the limits value.
4953 */
4954 if (val != dev_priv->rps.cur_freq) {
4955 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4956
dc97997a 4957 if (IS_GEN9(dev_priv))
5704195c
AG		 4958 I915_WRITE(GEN6_RPNSWREQ,
4959 GEN9_FREQUENCY(val));
dc97997a 4960 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4961 I915_WRITE(GEN6_RPNSWREQ,
4962 HSW_FREQUENCY(val));
4963 else
4964 I915_WRITE(GEN6_RPNSWREQ,
4965 GEN6_FREQUENCY(val) |
4966 GEN6_OFFSET(0) |
4967 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4968 }
7b9e0ae6 4969
7b9e0ae6
CW		 4970 /* Make sure we continue to get interrupts
4971 * until we hit the minimum or maximum frequencies.
4972 */
74ef1173 4973 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4974 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4975
d5570a72
BW		 4976 POSTING_READ(GEN6_RPNSWREQ);
4977
b39fb297 4978 dev_priv->rps.cur_freq = val;
0f94592e 4979 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4980}
4981
dc97997a 4982static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4983{
ffe02b40 4984 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4985 WARN_ON(val > dev_priv->rps.max_freq);
4986 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4987
dc97997a 4988 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4989 "Odd GPU freq value\n"))
4990 val &= ~1;
4991
cd25dd5b
D		 4992 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4993
8fb55197 4994 if (val != dev_priv->rps.cur_freq) {
ffe02b40 4995 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 4996 if (!IS_CHERRYVIEW(dev_priv))
4997 gen6_set_rps_thresholds(dev_priv, val);
4998 }
ffe02b40 4999
ffe02b40
VS		 5000 dev_priv->rps.cur_freq = val;
5001 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5002}
5003
a7f6e231 5004/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5005 *
5006 * * If Gfx is Idle, then
a7f6e231
D		 5007 * 1. Forcewake Media well.
5008 * 2. Request idle freq.
5009 * 3. Release Forcewake of Media well.
76c3552f
D		 5010*/
5011static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5012{
aed242ff 5013 u32 val = dev_priv->rps.idle_freq;
5549d25f 5014
aed242ff 5015 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5016 return;
5017
a7f6e231
D		 5018 /* Wake up the media well, as that takes a lot less
5019 * power than the Render well. */
5020 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5021 valleyview_set_rps(dev_priv, val);
a7f6e231 5022 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5023}
5024
43cf3bf0
CW		 5025void gen6_rps_busy(struct drm_i915_private *dev_priv)
5026{
5027 mutex_lock(&dev_priv->rps.hw_lock);
5028 if (dev_priv->rps.enabled) {
5029 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5030 gen6_rps_reset_ei(dev_priv);
5031 I915_WRITE(GEN6_PMINTRMSK,
5032 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5033
c33d247d
CW		 5034 gen6_enable_rps_interrupts(dev_priv);
5035
2b83c4c4
MW		 5036 /* Ensure we start at the user's desired frequency */
5037 intel_set_rps(dev_priv,
5038 clamp(dev_priv->rps.cur_freq,
5039 dev_priv->rps.min_freq_softlimit,
5040 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5041 }
5042 mutex_unlock(&dev_priv->rps.hw_lock);
5043}
5044
b29c19b6
CW		 5045void gen6_rps_idle(struct drm_i915_private *dev_priv)
5046{
c33d247d
CW		 5047 /* Flush our bottom-half so that it does not race with us
5048 * setting the idle frequency and so that it is bounded by
5049 * our rpm wakeref. And then disable the interrupts to stop any
5050 * futher RPS reclocking whilst we are asleep.
5051 */
5052 gen6_disable_rps_interrupts(dev_priv);
5053
b29c19b6 5054 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5055 if (dev_priv->rps.enabled) {
dc97997a 5056 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5057 vlv_set_rps_idle(dev_priv);
7526ed79 5058 else
dc97997a 5059 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5060 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5061 I915_WRITE(GEN6_PMINTRMSK,
5062 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5063 }
8d3afd7d 5064 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5065
8d3afd7d 5066 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5067 while (!list_empty(&dev_priv->rps.clients))
5068 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5069 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5070}
5071
1854d5ca 5072void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5073 struct intel_rps_client *rps,
5074 unsigned long submitted)
b29c19b6 5075{
8d3afd7d
CW		 5076 /* This is intentionally racy! We peek at the state here, then
5077 * validate inside the RPS worker.
5078 */
67d97da3 5079 if (!(dev_priv->gt.awake &&
8d3afd7d 5080 dev_priv->rps.enabled &&
29ecd78d 5081 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5082 return;
43cf3bf0 5083
e61b9958
CW		 5084 /* Force a RPS boost (and don't count it against the client) if
5085 * the GPU is severely congested.
5086 */
d0bc54f2 5087 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5088 rps = NULL;
5089
8d3afd7d
CW		 5090 spin_lock(&dev_priv->rps.client_lock);
5091 if (rps == NULL || list_empty(&rps->link)) {
5092 spin_lock_irq(&dev_priv->irq_lock);
5093 if (dev_priv->rps.interrupts_enabled) {
5094 dev_priv->rps.client_boost = true;
c33d247d 5095 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5096 }
5097 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5098
2e1b8730
CW		 5099 if (rps != NULL) {
5100 list_add(&rps->link, &dev_priv->rps.clients);
5101 rps->boosts++;
1854d5ca
CW		 5102 } else
5103 dev_priv->rps.boosts++;
c0951f0c 5104 }
8d3afd7d 5105 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5106}
5107
dc97997a 5108void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5109{
dc97997a
CW		 5110 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5111 valleyview_set_rps(dev_priv, val);
ffe02b40 5112 else
dc97997a 5113 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5114}
5115
dc97997a 5116static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5117{
20e49366 5118 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5119 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5120}
5121
dc97997a 5122static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5123{
2030d684
AG		 5124 I915_WRITE(GEN6_RP_CONTROL, 0);
5125}
5126
dc97997a 5127static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5128{
d20d4f0c 5129 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5130 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5131 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5132}
5133
dc97997a 5134static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5135{
38807746
D		 5136 I915_WRITE(GEN6_RC_CONTROL, 0);
5137}
5138
dc97997a 5139static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5140{
98a2e5f9
D		 5141 /* we're doing forcewake before Disabling RC6,
5142 * This what the BIOS expects when going into suspend */
59bad947 5143 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5144
44fc7d5c 5145 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5146
59bad947 5147 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5148}
5149
dc97997a 5150static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5151{
dc97997a 5152 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5153 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5154 mode = GEN6_RC_CTL_RC6_ENABLE;
5155 else
5156 mode = 0;
5157 }
dc97997a 5158 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5159 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5160 "RC6 %s RC6p %s RC6pp %s\n",
5161 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5162 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5163 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5164
5165 else
b99d49cc
ID		 5166 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5167 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5168}
5169
dc97997a 5170static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5171{
72e96d64 5172 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5173 bool enable_rc6 = true;
5174 unsigned long rc6_ctx_base;
fc619841
ID		 5175 u32 rc_ctl;
5176 int rc_sw_target;
5177
5178 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5179 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5180 RC_SW_TARGET_STATE_SHIFT;
5181 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5182 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5183 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5184 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5185 rc_sw_target);
274008e8
SAK		 5186
5187 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5188 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5189 enable_rc6 = false;
5190 }
5191
5192 /*
5193 * The exact context size is not known for BXT, so assume a page size
5194 * for this check.
5195 */
5196 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5197 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5198 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5199 ggtt->stolen_reserved_size))) {
b99d49cc 5200 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5201 enable_rc6 = false;
5202 }
5203
5204 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5205 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5206 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5207 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5208 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5209 enable_rc6 = false;
5210 }
5211
fc619841
ID		 5212 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5213 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5214 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5215 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5216 enable_rc6 = false;
5217 }
5218
5219 if (!I915_READ(GEN6_GFXPAUSE)) {
5220 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5221 enable_rc6 = false;
5222 }
5223
5224 if (!I915_READ(GEN8_MISC_CTRL0)) {
5225 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5226 enable_rc6 = false;
5227 }
5228
5229 return enable_rc6;
5230}
5231
dc97997a 5232int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5233{
e7d66d89 5234 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5235 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5236 return 0;
5237
274008e8
SAK		 5238 if (!enable_rc6)
5239 return 0;
5240
dc97997a 5241 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5242 DRM_INFO("RC6 disabled by BIOS\n");
5243 return 0;
5244 }
5245
456470eb 5246 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5247 if (enable_rc6 >= 0) {
5248 int mask;
5249
dc97997a 5250 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5251 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5252 INTEL_RC6pp_ENABLE;
5253 else
5254 mask = INTEL_RC6_ENABLE;
5255
5256 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5257 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5258 "(requested %d, valid %d)\n",
5259 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5260
5261 return enable_rc6 & mask;
5262 }
2b4e57bd 5263
dc97997a 5264 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5265 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5266
5267 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5268}
5269
dc97997a 5270static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5271{
5272 /* All of these values are in units of 50MHz */
773ea9a8 5273
93ee2920 5274 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5275 if (IS_BROXTON(dev_priv)) {
773ea9a8 5276 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5277 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5278 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5279 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5280 } else {
773ea9a8 5281 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5282 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5283 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5284 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5285 }
3280e8b0 5286 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5287 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5288
93ee2920 5289 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5290 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5291 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5292 u32 ddcc_status = 0;
5293
5294 if (sandybridge_pcode_read(dev_priv,
5295 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5296 &ddcc_status) == 0)
93ee2920 5297 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5298 clamp_t(u8,
5299 ((ddcc_status >> 8) & 0xff),
5300 dev_priv->rps.min_freq,
5301 dev_priv->rps.max_freq);
93ee2920
TR		 5302 }
5303
dc97997a 5304 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5305 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5306 * the natural hardware unit for SKL
5307 */
c5e0688c
AG		 5308 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5309 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5310 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5311 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5312 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5313 }
3280e8b0
BW		 5314}
5315
3a45b05c
CW		 5316static void reset_rps(struct drm_i915_private *dev_priv,
5317 void (*set)(struct drm_i915_private *, u8))
5318{
5319 u8 freq = dev_priv->rps.cur_freq;
5320
5321 /* force a reset */
5322 dev_priv->rps.power = -1;
5323 dev_priv->rps.cur_freq = -1;
5324
5325 set(dev_priv, freq);
5326}
5327
b6fef0ef 5328/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5329static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5330{
b6fef0ef
JB		 5331 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5332
23eafea6 5333 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5334 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5335 /*
5336 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5337 * clear out the Control register just to avoid inconsitency
5338 * with debugfs interface, which will show Turbo as enabled
5339 * only and that is not expected by the User after adding the
5340 * WaGsvDisableTurbo. Apart from this there is no problem even
5341 * if the Turbo is left enabled in the Control register, as the
5342 * Up/Down interrupts would remain masked.
5343 */
dc97997a 5344 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5345 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5346 return;
5347 }
5348
0beb059a
AG		 5349 /* Program defaults and thresholds for RPS*/
5350 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5351 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5352
5353 /* 1 second timeout*/
5354 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5355 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5356
b6fef0ef 5357 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5358
0beb059a
AG		 5359 /* Leaning on the below call to gen6_set_rps to program/setup the
5360 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5361 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5362 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5363
5364 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5365}
5366
dc97997a 5367static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5368{
e2f80391 5369 struct intel_engine_cs *engine;
3b3f1650 5370 enum intel_engine_id id;
20e49366 5371 uint32_t rc6_mask = 0;
20e49366
ZW		 5372
5373 /* 1a: Software RC state - RC0 */
5374 I915_WRITE(GEN6_RC_STATE, 0);
5375
5376 /* 1b: Get forcewake during program sequence. Although the driver
5377 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5378 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5379
5380 /* 2a: Disable RC states. */
5381 I915_WRITE(GEN6_RC_CONTROL, 0);
5382
5383 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5384
5385 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5386 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5387 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5388 else
5389 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5390 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5391 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5392 for_each_engine(engine, dev_priv, id)
e2f80391 5393 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5394
1a3d1898 5395 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5396 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5397
20e49366 5398 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5399
38c23527
ZW		 5400 /* 2c: Program Coarse Power Gating Policies. */
5401 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5402 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5403
20e49366 5404 /* 3a: Enable RC6 */
dc97997a 5405 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5406 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5407 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5408 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5409 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5410 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5411 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5412 GEN7_RC_CTL_TO_MODE |
5413 rc6_mask);
3e7732a0
SAK		 5414 } else {
5415 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5416 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5417 GEN6_RC_CTL_EI_MODE(1) |
5418 rc6_mask);
3e7732a0 5419 }
20e49366 5420
cb07bae0
SK		 5421 /*
5422 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5423 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5424 */
dc97997a 5425 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5426 I915_WRITE(GEN9_PG_ENABLE, 0);
5427 else
5428 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5429 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5430
59bad947 5431 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5432}
5433
dc97997a 5434static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5435{
e2f80391 5436 struct intel_engine_cs *engine;
3b3f1650 5437 enum intel_engine_id id;
93ee2920 5438 uint32_t rc6_mask = 0;
6edee7f3
BW		 5439
5440 /* 1a: Software RC state - RC0 */
5441 I915_WRITE(GEN6_RC_STATE, 0);
5442
5443 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5444 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5445 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5446
5447 /* 2a: Disable RC states. */
5448 I915_WRITE(GEN6_RC_CONTROL, 0);
5449
6edee7f3
BW		 5450 /* 2b: Program RC6 thresholds.*/
5451 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5452 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5453 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5454 for_each_engine(engine, dev_priv, id)
e2f80391 5455 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5456 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5457 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5458 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5459 else
5460 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5461
5462 /* 3: Enable RC6 */
dc97997a 5463 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5464 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5465 intel_print_rc6_info(dev_priv, rc6_mask);
5466 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5467 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5468 GEN7_RC_CTL_TO_MODE |
5469 rc6_mask);
5470 else
5471 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5472 GEN6_RC_CTL_EI_MODE(1) |
5473 rc6_mask);
6edee7f3
BW		 5474
5475 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5476 I915_WRITE(GEN6_RPNSWREQ,
5477 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5478 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5479 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5480 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5481 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5482
5483 /* Docs recommend 900MHz, and 300 MHz respectively */
5484 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5485 dev_priv->rps.max_freq_softlimit << 24 |
5486 dev_priv->rps.min_freq_softlimit << 16);
5487
5488 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5489 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5490 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5491 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5492
5493 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5494
5495 /* 5: Enable RPS */
7526ed79
DV		 5496 I915_WRITE(GEN6_RP_CONTROL,
5497 GEN6_RP_MEDIA_TURBO |
5498 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5499 GEN6_RP_MEDIA_IS_GFX |
5500 GEN6_RP_ENABLE |
5501 GEN6_RP_UP_BUSY_AVG |
5502 GEN6_RP_DOWN_IDLE_AVG);
5503
5504 /* 6: Ring frequency + overclocking (our driver does this later */
5505
3a45b05c 5506 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5507
59bad947 5508 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5509}
5510
dc97997a 5511static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5512{
e2f80391 5513 struct intel_engine_cs *engine;
3b3f1650 5514 enum intel_engine_id id;
99ac9612 5515 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5516 u32 gtfifodbg;
2b4e57bd 5517 int rc6_mode;
b4ac5afc 5518 int ret;
2b4e57bd 5519
4fc688ce 5520 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5521
2b4e57bd
ED		 5522 /* Here begins a magic sequence of register writes to enable
5523 * auto-downclocking.
5524 *
5525 * Perhaps there might be some value in exposing these to
5526 * userspace...
5527 */
5528 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5529
5530 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5531 gtfifodbg = I915_READ(GTFIFODBG);
5532 if (gtfifodbg) {
2b4e57bd
ED		 5533 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5534 I915_WRITE(GTFIFODBG, gtfifodbg);
5535 }
5536
59bad947 5537 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5538
5539 /* disable the counters and set deterministic thresholds */
5540 I915_WRITE(GEN6_RC_CONTROL, 0);
5541
5542 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5543 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5544 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5545 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5546 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5547
3b3f1650 5548 for_each_engine(engine, dev_priv, id)
e2f80391 5549 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5550
5551 I915_WRITE(GEN6_RC_SLEEP, 0);
5552 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5553 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5554 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5555 else
5556 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5557 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5558 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5559
5a7dc92a 5560 /* Check if we are enabling RC6 */
dc97997a 5561 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5562 if (rc6_mode & INTEL_RC6_ENABLE)
5563 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5564
5a7dc92a 5565 /* We don't use those on Haswell */
dc97997a 5566 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5567 if (rc6_mode & INTEL_RC6p_ENABLE)
5568 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5569
5a7dc92a
ED		 5570 if (rc6_mode & INTEL_RC6pp_ENABLE)
5571 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5572 }
2b4e57bd 5573
dc97997a 5574 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5575
5576 I915_WRITE(GEN6_RC_CONTROL,
5577 rc6_mask |
5578 GEN6_RC_CTL_EI_MODE(1) |
5579 GEN6_RC_CTL_HW_ENABLE);
5580
dd75fdc8
CW		 5581 /* Power down if completely idle for over 50ms */
5582 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5583 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5584
42c0526c 5585 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5586 if (ret)
42c0526c 5587 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5588
3a45b05c 5589 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5590
31643d54
BW		 5591 rc6vids = 0;
5592 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5593 if (IS_GEN6(dev_priv) && ret) {
31643d54 5594 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5595 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5596 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5597 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5598 rc6vids &= 0xffff00;
5599 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5600 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5601 if (ret)
5602 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5603 }
5604
59bad947 5605 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5606}
5607
fb7404e8 5608static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5609{
5610 int min_freq = 15;
3ebecd07
CW		 5611 unsigned int gpu_freq;
5612 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5613 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5614 int scaling_factor = 180;
eda79642 5615 struct cpufreq_policy *policy;
2b4e57bd 5616
4fc688ce 5617 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5618
eda79642
BW		 5619 policy = cpufreq_cpu_get(0);
5620 if (policy) {
5621 max_ia_freq = policy->cpuinfo.max_freq;
5622 cpufreq_cpu_put(policy);
5623 } else {
5624 /*
5625 * Default to measured freq if none found, PCU will ensure we
5626 * don't go over
5627 */
2b4e57bd 5628 max_ia_freq = tsc_khz;
eda79642 5629 }
2b4e57bd
ED		 5630
5631 /* Convert from kHz to MHz */
5632 max_ia_freq /= 1000;
5633
153b4b95 5634 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5635 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5636 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5637
dc97997a 5638 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5639 /* Convert GT frequency to 50 HZ units */
5640 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5641 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5642 } else {
5643 min_gpu_freq = dev_priv->rps.min_freq;
5644 max_gpu_freq = dev_priv->rps.max_freq;
5645 }
5646
2b4e57bd
ED		 5647 /*
5648 * For each potential GPU frequency, load a ring frequency we'd like
5649 * to use for memory access. We do this by specifying the IA frequency
5650 * the PCU should use as a reference to determine the ring frequency.
5651 */
4c8c7743
AG		 5652 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5653 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5654 unsigned int ia_freq = 0, ring_freq = 0;
5655
dc97997a 5656 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5657 /*
5658 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5659 * No floor required for ring frequency on SKL.
5660 */
5661 ring_freq = gpu_freq;
dc97997a 5662 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5663 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5664 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5665 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5666 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5667 ring_freq = max(min_ring_freq, ring_freq);
5668 /* leave ia_freq as the default, chosen by cpufreq */
5669 } else {
5670 /* On older processors, there is no separate ring
5671 * clock domain, so in order to boost the bandwidth
5672 * of the ring, we need to upclock the CPU (ia_freq).
5673 *
5674 * For GPU frequencies less than 750MHz,
5675 * just use the lowest ring freq.
5676 */
5677 if (gpu_freq < min_freq)
5678 ia_freq = 800;
5679 else
5680 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5681 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5682 }
2b4e57bd 5683
42c0526c
BW		 5684 sandybridge_pcode_write(dev_priv,
5685 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5686 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5687 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5688 gpu_freq);
2b4e57bd 5689 }
2b4e57bd
ED		 5690}
5691
03af2045 5692static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5693{
5694 u32 val, rp0;
5695
5b5929cb 5696 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5697
43b67998 5698 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5699 case 8:
5700 /* (2 * 4) config */
5701 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5702 break;
5703 case 12:
5704 /* (2 * 6) config */
5705 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5706 break;
5707 case 16:
5708 /* (2 * 8) config */
5709 default:
5710 /* Setting (2 * 8) Min RP0 for any other combination */
5711 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5712 break;
095acd5f 5713 }
5b5929cb
JN		 5714
5715 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5716
2b6b3a09
D		 5717 return rp0;
5718}
5719
5720static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5721{
5722 u32 val, rpe;
5723
5724 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5725 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5726
5727 return rpe;
5728}
5729
7707df4a
D		 5730static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5731{
5732 u32 val, rp1;
5733
5b5929cb
JN		 5734 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5735 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5736
7707df4a
D		 5737 return rp1;
5738}
5739
f8f2b001
D		 5740static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5741{
5742 u32 val, rp1;
5743
5744 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5745
5746 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5747
5748 return rp1;
5749}
5750
03af2045 5751static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5752{
5753 u32 val, rp0;
5754
64936258 5755 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5756
5757 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5758 /* Clamp to max */
5759 rp0 = min_t(u32, rp0, 0xea);
5760
5761 return rp0;
5762}
5763
5764static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5765{
5766 u32 val, rpe;
5767
64936258 5768 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5769 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5770 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5771 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5772
5773 return rpe;
5774}
5775
03af2045 5776static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5777{
36146035
ID		 5778 u32 val;
5779
5780 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5781 /*
5782 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5783 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5784 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5785 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5786 * to make sure it matches what Punit accepts.
5787 */
5788 return max_t(u32, val, 0xc0);
0a073b84
JB		 5789}
5790
ae48434c
ID		 5791/* Check that the pctx buffer wasn't move under us. */
5792static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5793{
5794 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5795
5796 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5797 dev_priv->vlv_pctx->stolen->start);
5798}
5799
38807746
D		 5800
5801/* Check that the pcbr address is not empty. */
5802static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5803{
5804 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5805
5806 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5807}
5808
dc97997a 5809static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5810{
62106b4f 5811 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5812 unsigned long pctx_paddr, paddr;
38807746
D		 5813 u32 pcbr;
5814 int pctx_size = 32*1024;
5815
38807746
D		 5816 pcbr = I915_READ(VLV_PCBR);
5817 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5818 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5819 paddr = (dev_priv->mm.stolen_base +
62106b4f 5820 (ggtt->stolen_size - pctx_size));
38807746
D		 5821
5822 pctx_paddr = (paddr & (~4095));
5823 I915_WRITE(VLV_PCBR, pctx_paddr);
5824 }
ce611ef8
VS		 5825
5826 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5827}
5828
dc97997a 5829static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5830{
c9cddffc
JB		 5831 struct drm_i915_gem_object *pctx;
5832 unsigned long pctx_paddr;
5833 u32 pcbr;
5834 int pctx_size = 24*1024;
5835
5836 pcbr = I915_READ(VLV_PCBR);
5837 if (pcbr) {
5838 /* BIOS set it up already, grab the pre-alloc'd space */
5839 int pcbr_offset;
5840
5841 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5842 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5843 pcbr_offset,
190d6cd5 5844 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5845 pctx_size);
5846 goto out;
5847 }
5848
ce611ef8
VS		 5849 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5850
c9cddffc
JB		 5851 /*
5852 * From the Gunit register HAS:
5853 * The Gfx driver is expected to program this register and ensure
5854 * proper allocation within Gfx stolen memory. For example, this
5855 * register should be programmed such than the PCBR range does not
5856 * overlap with other ranges, such as the frame buffer, protected
5857 * memory, or any other relevant ranges.
5858 */
91c8a326 5859 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5860 if (!pctx) {
5861 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5862 goto out;
c9cddffc
JB		 5863 }
5864
5865 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5866 I915_WRITE(VLV_PCBR, pctx_paddr);
5867
5868out:
ce611ef8 5869 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5870 dev_priv->vlv_pctx = pctx;
5871}
5872
dc97997a 5873static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5874{
ae48434c
ID		 5875 if (WARN_ON(!dev_priv->vlv_pctx))
5876 return;
5877
34911fd3 5878 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5879 dev_priv->vlv_pctx = NULL;
5880}
5881
c30fec65
VS		 5882static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5883{
5884 dev_priv->rps.gpll_ref_freq =
5885 vlv_get_cck_clock(dev_priv, "GPLL ref",
5886 CCK_GPLL_CLOCK_CONTROL,
5887 dev_priv->czclk_freq);
5888
5889 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5890 dev_priv->rps.gpll_ref_freq);
5891}
5892
dc97997a 5893static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5894{
2bb25c17 5895 u32 val;
4e80519e 5896
dc97997a 5897 valleyview_setup_pctx(dev_priv);
4e80519e 5898
c30fec65
VS		 5899 vlv_init_gpll_ref_freq(dev_priv);
5900
2bb25c17
VS		 5901 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5902 switch ((val >> 6) & 3) {
5903 case 0:
5904 case 1:
5905 dev_priv->mem_freq = 800;
5906 break;
5907 case 2:
5908 dev_priv->mem_freq = 1066;
5909 break;
5910 case 3:
5911 dev_priv->mem_freq = 1333;
5912 break;
5913 }
80b83b62 5914 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5915
4e80519e
ID		 5916 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5917 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5918 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5919 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5920 dev_priv->rps.max_freq);
5921
5922 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5923 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5924 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5925 dev_priv->rps.efficient_freq);
5926
f8f2b001
D		 5927 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5928 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5929 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5930 dev_priv->rps.rp1_freq);
5931
4e80519e
ID		 5932 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5933 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5934 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5935 dev_priv->rps.min_freq);
4e80519e
ID		 5936}
5937
dc97997a 5938static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5939{
2bb25c17 5940 u32 val;
2b6b3a09 5941
dc97997a 5942 cherryview_setup_pctx(dev_priv);
2b6b3a09 5943
c30fec65
VS		 5944 vlv_init_gpll_ref_freq(dev_priv);
5945
a580516d 5946 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5947 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5948 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5949
2bb25c17 5950 switch ((val >> 2) & 0x7) {
2bb25c17 5951 case 3:
2bb25c17
VS		 5952 dev_priv->mem_freq = 2000;
5953 break;
bfa7df01 5954 default:
2bb25c17
VS		 5955 dev_priv->mem_freq = 1600;
5956 break;
5957 }
80b83b62 5958 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5959
2b6b3a09
D		 5960 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5961 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5962 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5963 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5964 dev_priv->rps.max_freq);
5965
5966 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5967 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5968 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5969 dev_priv->rps.efficient_freq);
5970
7707df4a
D		 5971 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5972 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5973 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5974 dev_priv->rps.rp1_freq);
5975
5b7c91b7
D		 5976 /* PUnit validated range is only [RPe, RP0] */
5977 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5978 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5979 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5980 dev_priv->rps.min_freq);
5981
1c14762d
VS		 5982 WARN_ONCE((dev_priv->rps.max_freq |
5983 dev_priv->rps.efficient_freq |
5984 dev_priv->rps.rp1_freq |
5985 dev_priv->rps.min_freq) & 1,
5986 "Odd GPU freq values\n");
38807746
D		 5987}
5988
dc97997a 5989static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5990{
dc97997a 5991 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5992}
5993
dc97997a 5994static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 5995{
e2f80391 5996 struct intel_engine_cs *engine;
3b3f1650 5997 enum intel_engine_id id;
2b6b3a09 5998 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 5999
6000 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6001
297b32ec
VS		 6002 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6003 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6004 if (gtfifodbg) {
6005 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6006 gtfifodbg);
6007 I915_WRITE(GTFIFODBG, gtfifodbg);
6008 }
6009
6010 cherryview_check_pctx(dev_priv);
6011
6012 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6013 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6014 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6015
160614a2
VS		 6016 /* Disable RC states. */
6017 I915_WRITE(GEN6_RC_CONTROL, 0);
6018
38807746
D		 6019 /* 2a: Program RC6 thresholds.*/
6020 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6021 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6022 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6023
3b3f1650 6024 for_each_engine(engine, dev_priv, id)
e2f80391 6025 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6026 I915_WRITE(GEN6_RC_SLEEP, 0);
6027
f4f71c7d
D		 6028 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6029 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6030
6031 /* allows RC6 residency counter to work */
6032 I915_WRITE(VLV_COUNTER_CONTROL,
6033 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6034 VLV_MEDIA_RC6_COUNT_EN |
6035 VLV_RENDER_RC6_COUNT_EN));
6036
6037 /* For now we assume BIOS is allocating and populating the PCBR */
6038 pcbr = I915_READ(VLV_PCBR);
6039
38807746 6040 /* 3: Enable RC6 */
dc97997a
CW		 6041 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6042 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6043 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6044
6045 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6046
2b6b3a09 6047 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6048 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6049 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6050 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6051 I915_WRITE(GEN6_RP_UP_EI, 66000);
6052 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6053
6054 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6055
6056 /* 5: Enable RPS */
6057 I915_WRITE(GEN6_RP_CONTROL,
6058 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6059 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6060 GEN6_RP_ENABLE |
6061 GEN6_RP_UP_BUSY_AVG |
6062 GEN6_RP_DOWN_IDLE_AVG);
6063
3ef62342
D		 6064 /* Setting Fixed Bias */
6065 val = VLV_OVERRIDE_EN |
6066 VLV_SOC_TDP_EN |
6067 CHV_BIAS_CPU_50_SOC_50;
6068 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6069
2b6b3a09
D		 6070 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6071
8d40c3ae
VS		 6072 /* RPS code assumes GPLL is used */
6073 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6074
742f491d 6075 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6076 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6077
3a45b05c 6078 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6079
59bad947 6080 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6081}
6082
dc97997a 6083static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6084{
e2f80391 6085 struct intel_engine_cs *engine;
3b3f1650 6086 enum intel_engine_id id;
2a5913a8 6087 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6088
6089 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6090
ae48434c
ID		 6091 valleyview_check_pctx(dev_priv);
6092
297b32ec
VS		 6093 gtfifodbg = I915_READ(GTFIFODBG);
6094 if (gtfifodbg) {
f7d85c1e
JB		 6095 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6096 gtfifodbg);
0a073b84
JB		 6097 I915_WRITE(GTFIFODBG, gtfifodbg);
6098 }
6099
c8d9a590 6100 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6101 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6102
160614a2
VS		 6103 /* Disable RC states. */
6104 I915_WRITE(GEN6_RC_CONTROL, 0);
6105
cad725fe 6106 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6107 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6108 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6109 I915_WRITE(GEN6_RP_UP_EI, 66000);
6110 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6111
6112 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6113
6114 I915_WRITE(GEN6_RP_CONTROL,
6115 GEN6_RP_MEDIA_TURBO |
6116 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6117 GEN6_RP_MEDIA_IS_GFX |
6118 GEN6_RP_ENABLE |
6119 GEN6_RP_UP_BUSY_AVG |
6120 GEN6_RP_DOWN_IDLE_CONT);
6121
6122 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6123 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6124 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6125
3b3f1650 6126 for_each_engine(engine, dev_priv, id)
e2f80391 6127 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6128
2f0aa304 6129 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6130
6131 /* allows RC6 residency counter to work */
49798eb2 6132 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6133 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6134 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6135 VLV_MEDIA_RC6_COUNT_EN |
6136 VLV_RENDER_RC6_COUNT_EN));
31685c25 6137
dc97997a 6138 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6139 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6140
dc97997a 6141 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6142
a2b23fe0 6143 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6144
3ef62342
D		 6145 /* Setting Fixed Bias */
6146 val = VLV_OVERRIDE_EN |
6147 VLV_SOC_TDP_EN |
6148 VLV_BIAS_CPU_125_SOC_875;
6149 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6150
64936258 6151 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6152
8d40c3ae
VS		 6153 /* RPS code assumes GPLL is used */
6154 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6155
742f491d 6156 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6157 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6158
3a45b05c 6159 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6160
59bad947 6161 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6162}
6163
dde18883
ED		 6164static unsigned long intel_pxfreq(u32 vidfreq)
6165{
6166 unsigned long freq;
6167 int div = (vidfreq & 0x3f0000) >> 16;
6168 int post = (vidfreq & 0x3000) >> 12;
6169 int pre = (vidfreq & 0x7);
6170
6171 if (!pre)
6172 return 0;
6173
6174 freq = ((div * 133333) / ((1<<post) * pre));
6175
6176 return freq;
6177}
6178
eb48eb00
DV		 6179static const struct cparams {
6180 u16 i;
6181 u16 t;
6182 u16 m;
6183 u16 c;
6184} cparams[] = {
6185 { 1, 1333, 301, 28664 },
6186 { 1, 1066, 294, 24460 },
6187 { 1, 800, 294, 25192 },
6188 { 0, 1333, 276, 27605 },
6189 { 0, 1066, 276, 27605 },
6190 { 0, 800, 231, 23784 },
6191};
6192
f531dcb2 6193static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6194{
6195 u64 total_count, diff, ret;
6196 u32 count1, count2, count3, m = 0, c = 0;
6197 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6198 int i;
6199
02d71956
DV		 6200 assert_spin_locked(&mchdev_lock);
6201
20e4d407 6202 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6203
6204 /* Prevent division-by-zero if we are asking too fast.
6205 * Also, we don't get interesting results if we are polling
6206 * faster than once in 10ms, so just return the saved value
6207 * in such cases.
6208 */
6209 if (diff1 <= 10)
20e4d407 6210 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6211
6212 count1 = I915_READ(DMIEC);
6213 count2 = I915_READ(DDREC);
6214 count3 = I915_READ(CSIEC);
6215
6216 total_count = count1 + count2 + count3;
6217
6218 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6219 if (total_count < dev_priv->ips.last_count1) {
6220 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6221 diff += total_count;
6222 } else {
20e4d407 6223 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6224 }
6225
6226 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6227 if (cparams[i].i == dev_priv->ips.c_m &&
6228 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6229 m = cparams[i].m;
6230 c = cparams[i].c;
6231 break;
6232 }
6233 }
6234
6235 diff = div_u64(diff, diff1);
6236 ret = ((m * diff) + c);
6237 ret = div_u64(ret, 10);
6238
20e4d407
DV		 6239 dev_priv->ips.last_count1 = total_count;
6240 dev_priv->ips.last_time1 = now;
eb48eb00 6241
20e4d407 6242 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6243
6244 return ret;
6245}
6246
f531dcb2
CW		 6247unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6248{
6249 unsigned long val;
6250
dc97997a 6251 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6252 return 0;
6253
6254 spin_lock_irq(&mchdev_lock);
6255
6256 val = __i915_chipset_val(dev_priv);
6257
6258 spin_unlock_irq(&mchdev_lock);
6259
6260 return val;
6261}
6262
eb48eb00
DV		 6263unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6264{
6265 unsigned long m, x, b;
6266 u32 tsfs;
6267
6268 tsfs = I915_READ(TSFS);
6269
6270 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6271 x = I915_READ8(TR1);
6272
6273 b = tsfs & TSFS_INTR_MASK;
6274
6275 return ((m * x) / 127) - b;
6276}
6277
d972d6ee
MK		 6278static int _pxvid_to_vd(u8 pxvid)
6279{
6280 if (pxvid == 0)
6281 return 0;
6282
6283 if (pxvid >= 8 && pxvid < 31)
6284 pxvid = 31;
6285
6286 return (pxvid + 2) * 125;
6287}
6288
6289static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6290{
d972d6ee
MK		 6291 const int vd = _pxvid_to_vd(pxvid);
6292 const int vm = vd - 1125;
6293
dc97997a 6294 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6295 return vm > 0 ? vm : 0;
6296
6297 return vd;
eb48eb00
DV		 6298}
6299
02d71956 6300static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6301{
5ed0bdf2 6302 u64 now, diff, diffms;
eb48eb00
DV		 6303 u32 count;
6304
02d71956 6305 assert_spin_locked(&mchdev_lock);
eb48eb00 6306
5ed0bdf2
TG		 6307 now = ktime_get_raw_ns();
6308 diffms = now - dev_priv->ips.last_time2;
6309 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6310
6311 /* Don't divide by 0 */
eb48eb00
DV		 6312 if (!diffms)
6313 return;
6314
6315 count = I915_READ(GFXEC);
6316
20e4d407
DV		 6317 if (count < dev_priv->ips.last_count2) {
6318 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6319 diff += count;
6320 } else {
20e4d407 6321 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6322 }
6323
20e4d407
DV		 6324 dev_priv->ips.last_count2 = count;
6325 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6326
6327 /* More magic constants... */
6328 diff = diff * 1181;
6329 diff = div_u64(diff, diffms * 10);
20e4d407 6330 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6331}
6332
02d71956
DV		 6333void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6334{
dc97997a 6335 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6336 return;
6337
9270388e 6338 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6339
6340 __i915_update_gfx_val(dev_priv);
6341
9270388e 6342 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6343}
6344
f531dcb2 6345static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6346{
6347 unsigned long t, corr, state1, corr2, state2;
6348 u32 pxvid, ext_v;
6349
02d71956
DV		 6350 assert_spin_locked(&mchdev_lock);
6351
616847e7 6352 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6353 pxvid = (pxvid >> 24) & 0x7f;
6354 ext_v = pvid_to_extvid(dev_priv, pxvid);
6355
6356 state1 = ext_v;
6357
6358 t = i915_mch_val(dev_priv);
6359
6360 /* Revel in the empirically derived constants */
6361
6362 /* Correction factor in 1/100000 units */
6363 if (t > 80)
6364 corr = ((t * 2349) + 135940);
6365 else if (t >= 50)
6366 corr = ((t * 964) + 29317);
6367 else /* < 50 */
6368 corr = ((t * 301) + 1004);
6369
6370 corr = corr * ((150142 * state1) / 10000 - 78642);
6371 corr /= 100000;
20e4d407 6372 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6373
6374 state2 = (corr2 * state1) / 10000;
6375 state2 /= 100; /* convert to mW */
6376
02d71956 6377 __i915_update_gfx_val(dev_priv);
eb48eb00 6378
20e4d407 6379 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6380}
6381
f531dcb2
CW		 6382unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6383{
6384 unsigned long val;
6385
dc97997a 6386 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6387 return 0;
6388
6389 spin_lock_irq(&mchdev_lock);
6390
6391 val = __i915_gfx_val(dev_priv);
6392
6393 spin_unlock_irq(&mchdev_lock);
6394
6395 return val;
6396}
6397
eb48eb00
DV		 6398/**
6399 * i915_read_mch_val - return value for IPS use
6400 *
6401 * Calculate and return a value for the IPS driver to use when deciding whether
6402 * we have thermal and power headroom to increase CPU or GPU power budget.
6403 */
6404unsigned long i915_read_mch_val(void)
6405{
6406 struct drm_i915_private *dev_priv;
6407 unsigned long chipset_val, graphics_val, ret = 0;
6408
9270388e 6409 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6410 if (!i915_mch_dev)
6411 goto out_unlock;
6412 dev_priv = i915_mch_dev;
6413
f531dcb2
CW		 6414 chipset_val = __i915_chipset_val(dev_priv);
6415 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6416
6417 ret = chipset_val + graphics_val;
6418
6419out_unlock:
9270388e 6420 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6421
6422 return ret;
6423}
6424EXPORT_SYMBOL_GPL(i915_read_mch_val);
6425
6426/**
6427 * i915_gpu_raise - raise GPU frequency limit
6428 *
6429 * Raise the limit; IPS indicates we have thermal headroom.
6430 */
6431bool i915_gpu_raise(void)
6432{
6433 struct drm_i915_private *dev_priv;
6434 bool ret = true;
6435
9270388e 6436 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6437 if (!i915_mch_dev) {
6438 ret = false;
6439 goto out_unlock;
6440 }
6441 dev_priv = i915_mch_dev;
6442
20e4d407
DV		 6443 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6444 dev_priv->ips.max_delay--;
eb48eb00
DV		 6445
6446out_unlock:
9270388e 6447 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6448
6449 return ret;
6450}
6451EXPORT_SYMBOL_GPL(i915_gpu_raise);
6452
6453/**
6454 * i915_gpu_lower - lower GPU frequency limit
6455 *
6456 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6457 * frequency maximum.
6458 */
6459bool i915_gpu_lower(void)
6460{
6461 struct drm_i915_private *dev_priv;
6462 bool ret = true;
6463
9270388e 6464 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6465 if (!i915_mch_dev) {
6466 ret = false;
6467 goto out_unlock;
6468 }
6469 dev_priv = i915_mch_dev;
6470
20e4d407
DV		 6471 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6472 dev_priv->ips.max_delay++;
eb48eb00
DV		 6473
6474out_unlock:
9270388e 6475 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6476
6477 return ret;
6478}
6479EXPORT_SYMBOL_GPL(i915_gpu_lower);
6480
6481/**
6482 * i915_gpu_busy - indicate GPU business to IPS
6483 *
6484 * Tell the IPS driver whether or not the GPU is busy.
6485 */
6486bool i915_gpu_busy(void)
6487{
eb48eb00
DV		 6488 bool ret = false;
6489
9270388e 6490 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6491 if (i915_mch_dev)
6492 ret = i915_mch_dev->gt.awake;
9270388e 6493 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6494
6495 return ret;
6496}
6497EXPORT_SYMBOL_GPL(i915_gpu_busy);
6498
6499/**
6500 * i915_gpu_turbo_disable - disable graphics turbo
6501 *
6502 * Disable graphics turbo by resetting the max frequency and setting the
6503 * current frequency to the default.
6504 */
6505bool i915_gpu_turbo_disable(void)
6506{
6507 struct drm_i915_private *dev_priv;
6508 bool ret = true;
6509
9270388e 6510 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6511 if (!i915_mch_dev) {
6512 ret = false;
6513 goto out_unlock;
6514 }
6515 dev_priv = i915_mch_dev;
6516
20e4d407 6517 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6518
91d14251 6519 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6520 ret = false;
6521
6522out_unlock:
9270388e 6523 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6524
6525 return ret;
6526}
6527EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6528
6529/**
6530 * Tells the intel_ips driver that the i915 driver is now loaded, if
6531 * IPS got loaded first.
6532 *
6533 * This awkward dance is so that neither module has to depend on the
6534 * other in order for IPS to do the appropriate communication of
6535 * GPU turbo limits to i915.
6536 */
6537static void
6538ips_ping_for_i915_load(void)
6539{
6540 void (*link)(void);
6541
6542 link = symbol_get(ips_link_to_i915_driver);
6543 if (link) {
6544 link();
6545 symbol_put(ips_link_to_i915_driver);
6546 }
6547}
6548
6549void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6550{
02d71956
DV		 6551 /* We only register the i915 ips part with intel-ips once everything is
6552 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6553 spin_lock_irq(&mchdev_lock);
eb48eb00 6554 i915_mch_dev = dev_priv;
9270388e 6555 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6556
6557 ips_ping_for_i915_load();
6558}
6559
6560void intel_gpu_ips_teardown(void)
6561{
9270388e 6562 spin_lock_irq(&mchdev_lock);
eb48eb00 6563 i915_mch_dev = NULL;
9270388e 6564 spin_unlock_irq(&mchdev_lock);
eb48eb00 6565}
76c3552f 6566
dc97997a 6567static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6568{
dde18883
ED		 6569 u32 lcfuse;
6570 u8 pxw[16];
6571 int i;
6572
6573 /* Disable to program */
6574 I915_WRITE(ECR, 0);
6575 POSTING_READ(ECR);
6576
6577 /* Program energy weights for various events */
6578 I915_WRITE(SDEW, 0x15040d00);
6579 I915_WRITE(CSIEW0, 0x007f0000);
6580 I915_WRITE(CSIEW1, 0x1e220004);
6581 I915_WRITE(CSIEW2, 0x04000004);
6582
6583 for (i = 0; i < 5; i++)
616847e7 6584 I915_WRITE(PEW(i), 0);
dde18883 6585 for (i = 0; i < 3; i++)
616847e7 6586 I915_WRITE(DEW(i), 0);
dde18883
ED		 6587
6588 /* Program P-state weights to account for frequency power adjustment */
6589 for (i = 0; i < 16; i++) {
616847e7 6590 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6591 unsigned long freq = intel_pxfreq(pxvidfreq);
6592 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6593 PXVFREQ_PX_SHIFT;
6594 unsigned long val;
6595
6596 val = vid * vid;
6597 val *= (freq / 1000);
6598 val *= 255;
6599 val /= (127*127*900);
6600 if (val > 0xff)
6601 DRM_ERROR("bad pxval: %ld\n", val);
6602 pxw[i] = val;
6603 }
6604 /* Render standby states get 0 weight */
6605 pxw[14] = 0;
6606 pxw[15] = 0;
6607
6608 for (i = 0; i < 4; i++) {
6609 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6610 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6611 I915_WRITE(PXW(i), val);
dde18883
ED		 6612 }
6613
6614 /* Adjust magic regs to magic values (more experimental results) */
6615 I915_WRITE(OGW0, 0);
6616 I915_WRITE(OGW1, 0);
6617 I915_WRITE(EG0, 0x00007f00);
6618 I915_WRITE(EG1, 0x0000000e);
6619 I915_WRITE(EG2, 0x000e0000);
6620 I915_WRITE(EG3, 0x68000300);
6621 I915_WRITE(EG4, 0x42000000);
6622 I915_WRITE(EG5, 0x00140031);
6623 I915_WRITE(EG6, 0);
6624 I915_WRITE(EG7, 0);
6625
6626 for (i = 0; i < 8; i++)
616847e7 6627 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6628
6629 /* Enable PMON + select events */
6630 I915_WRITE(ECR, 0x80000019);
6631
6632 lcfuse = I915_READ(LCFUSE02);
6633
20e4d407 6634 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6635}
6636
dc97997a 6637void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6638{
b268c699
ID		 6639 /*
6640 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6641 * requirement.
6642 */
6643 if (!i915.enable_rc6) {
6644 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6645 intel_runtime_pm_get(dev_priv);
6646 }
e6069ca8 6647
b5163dbb 6648 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6649 mutex_lock(&dev_priv->rps.hw_lock);
6650
6651 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6652 if (IS_CHERRYVIEW(dev_priv))
6653 cherryview_init_gt_powersave(dev_priv);
6654 else if (IS_VALLEYVIEW(dev_priv))
6655 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6656 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6657 gen6_init_rps_frequencies(dev_priv);
6658
6659 /* Derive initial user preferences/limits from the hardware limits */
6660 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6661 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6662
6663 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6664 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6665
6666 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6667 dev_priv->rps.min_freq_softlimit =
6668 max_t(int,
6669 dev_priv->rps.efficient_freq,
6670 intel_freq_opcode(dev_priv, 450));
6671
99ac9612
CW		 6672 /* After setting max-softlimit, find the overclock max freq */
6673 if (IS_GEN6(dev_priv) ||
6674 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6675 u32 params = 0;
6676
6677 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6678 if (params & BIT(31)) { /* OC supported */
6679 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6680 (dev_priv->rps.max_freq & 0xff) * 50,
6681 (params & 0xff) * 50);
6682 dev_priv->rps.max_freq = params & 0xff;
6683 }
6684 }
6685
29ecd78d
CW		 6686 /* Finally allow us to boost to max by default */
6687 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6688
773ea9a8 6689 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6690 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6691
6692 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6693}
6694
dc97997a 6695void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6696{
8dac1e1f 6697 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6698 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6699
6700 if (!i915.enable_rc6)
6701 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6702}
6703
54b4f68f
CW		 6704/**
6705 * intel_suspend_gt_powersave - suspend PM work and helper threads
6706 * @dev_priv: i915 device
6707 *
6708 * We don't want to disable RC6 or other features here, we just want
6709 * to make sure any work we've queued has finished and won't bother
6710 * us while we're suspended.
6711 */
6712void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6713{
6714 if (INTEL_GEN(dev_priv) < 6)
6715 return;
6716
6717 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6718 intel_runtime_pm_put(dev_priv);
6719
6720 /* gen6_rps_idle() will be called later to disable interrupts */
6721}
6722
b7137e0c
CW		 6723void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6724{
6725 dev_priv->rps.enabled = true; /* force disabling */
6726 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6727
6728 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6729}
6730
dc97997a 6731void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6732{
b7137e0c
CW		 6733 if (!READ_ONCE(dev_priv->rps.enabled))
6734 return;
e494837a 6735
b7137e0c 6736 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6737
b7137e0c
CW		 6738 if (INTEL_GEN(dev_priv) >= 9) {
6739 gen9_disable_rc6(dev_priv);
6740 gen9_disable_rps(dev_priv);
6741 } else if (IS_CHERRYVIEW(dev_priv)) {
6742 cherryview_disable_rps(dev_priv);
6743 } else if (IS_VALLEYVIEW(dev_priv)) {
6744 valleyview_disable_rps(dev_priv);
6745 } else if (INTEL_GEN(dev_priv) >= 6) {
6746 gen6_disable_rps(dev_priv);
6747 } else if (IS_IRONLAKE_M(dev_priv)) {
6748 ironlake_disable_drps(dev_priv);
930ebb46 6749 }
b7137e0c
CW		 6750
6751 dev_priv->rps.enabled = false;
6752 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6753}
6754
b7137e0c 6755void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6756{
54b4f68f
CW		 6757 /* We shouldn't be disabling as we submit, so this should be less
6758 * racy than it appears!
6759 */
b7137e0c
CW		 6760 if (READ_ONCE(dev_priv->rps.enabled))
6761 return;
1a01ab3b 6762
b7137e0c
CW		 6763 /* Powersaving is controlled by the host when inside a VM */
6764 if (intel_vgpu_active(dev_priv))
6765 return;
0a073b84 6766
b7137e0c 6767 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6768
6769 if (IS_CHERRYVIEW(dev_priv)) {
6770 cherryview_enable_rps(dev_priv);
6771 } else if (IS_VALLEYVIEW(dev_priv)) {
6772 valleyview_enable_rps(dev_priv);
b7137e0c 6773 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6774 gen9_enable_rc6(dev_priv);
6775 gen9_enable_rps(dev_priv);
6776 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6777 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6778 } else if (IS_BROADWELL(dev_priv)) {
6779 gen8_enable_rps(dev_priv);
fb7404e8 6780 gen6_update_ring_freq(dev_priv);
b7137e0c 6781 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6782 gen6_enable_rps(dev_priv);
fb7404e8 6783 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6784 } else if (IS_IRONLAKE_M(dev_priv)) {
6785 ironlake_enable_drps(dev_priv);
6786 intel_init_emon(dev_priv);
0a073b84 6787 }
aed242ff
CW		 6788
6789 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6790 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6791
6792 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6793 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6794
54b4f68f 6795 dev_priv->rps.enabled = true;
b7137e0c
CW		 6796 mutex_unlock(&dev_priv->rps.hw_lock);
6797}
3cc134e3 6798
54b4f68f
CW		 6799static void __intel_autoenable_gt_powersave(struct work_struct *work)
6800{
6801 struct drm_i915_private *dev_priv =
6802 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6803 struct intel_engine_cs *rcs;
6804 struct drm_i915_gem_request *req;
6805
6806 if (READ_ONCE(dev_priv->rps.enabled))
6807 goto out;
6808
3b3f1650 6809 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6810 if (rcs->last_context)
6811 goto out;
6812
6813 if (!rcs->init_context)
6814 goto out;
6815
6816 mutex_lock(&dev_priv->drm.struct_mutex);
6817
6818 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6819 if (IS_ERR(req))
6820 goto unlock;
6821
6822 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6823 rcs->init_context(req);
6824
6825 /* Mark the device busy, calling intel_enable_gt_powersave() */
6826 i915_add_request_no_flush(req);
6827
6828unlock:
6829 mutex_unlock(&dev_priv->drm.struct_mutex);
6830out:
6831 intel_runtime_pm_put(dev_priv);
6832}
6833
6834void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6835{
6836 if (READ_ONCE(dev_priv->rps.enabled))
6837 return;
6838
6839 if (IS_IRONLAKE_M(dev_priv)) {
6840 ironlake_enable_drps(dev_priv);
54b4f68f 6841 intel_init_emon(dev_priv);
54b4f68f
CW		 6842 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6843 /*
6844 * PCU communication is slow and this doesn't need to be
6845 * done at any specific time, so do this out of our fast path
6846 * to make resume and init faster.
6847 *
6848 * We depend on the HW RC6 power context save/restore
6849 * mechanism when entering D3 through runtime PM suspend. So
6850 * disable RPM until RPS/RC6 is properly setup. We can only
6851 * get here via the driver load/system resume/runtime resume
6852 * paths, so the _noresume version is enough (and in case of
6853 * runtime resume it's necessary).
6854 */
6855 if (queue_delayed_work(dev_priv->wq,
6856 &dev_priv->rps.autoenable_work,
6857 round_jiffies_up_relative(HZ)))
6858 intel_runtime_pm_get_noresume(dev_priv);
6859 }
6860}
6861
3107bd48
DV		 6862static void ibx_init_clock_gating(struct drm_device *dev)
6863{
fac5e23e 6864 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6865
6866 /*
6867 * On Ibex Peak and Cougar Point, we need to disable clock
6868 * gating for the panel power sequencer or it will fail to
6869 * start up when no ports are active.
6870 */
6871 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6872}
6873
0e088b8f
VS		 6874static void g4x_disable_trickle_feed(struct drm_device *dev)
6875{
fac5e23e 6876 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6877 enum pipe pipe;
0e088b8f 6878
055e393f 6879 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6880 I915_WRITE(DSPCNTR(pipe),
6881 I915_READ(DSPCNTR(pipe)) |
6882 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6883
6884 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6885 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6886 }
6887}
6888
017636cc
VS		 6889static void ilk_init_lp_watermarks(struct drm_device *dev)
6890{
fac5e23e 6891 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6892
6893 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6894 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6895 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6896
6897 /*
6898 * Don't touch WM1S_LP_EN here.
6899 * Doing so could cause underruns.
6900 */
6901}
6902
1fa61106 6903static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6904{
fac5e23e 6905 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6906 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6907
f1e8fa56
DL		 6908 /*
6909 * Required for FBC
6910 * WaFbcDisableDpfcClockGating:ilk
6911 */
4d47e4f5
DL		 6912 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6913 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6914 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6915
6916 I915_WRITE(PCH_3DCGDIS0,
6917 MARIUNIT_CLOCK_GATE_DISABLE |
6918 SVSMUNIT_CLOCK_GATE_DISABLE);
6919 I915_WRITE(PCH_3DCGDIS1,
6920 VFMUNIT_CLOCK_GATE_DISABLE);
6921
6f1d69b0
ED		 6922 /*
6923 * According to the spec the following bits should be set in
6924 * order to enable memory self-refresh
6925 * The bit 22/21 of 0x42004
6926 * The bit 5 of 0x42020
6927 * The bit 15 of 0x45000
6928 */
6929 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6930 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6931 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6932 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6933 I915_WRITE(DISP_ARB_CTL,
6934 (I915_READ(DISP_ARB_CTL) |
6935 DISP_FBC_WM_DIS));
017636cc
VS		 6936
6937 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6938
6939 /*
6940 * Based on the document from hardware guys the following bits
6941 * should be set unconditionally in order to enable FBC.
6942 * The bit 22 of 0x42000
6943 * The bit 22 of 0x42004
6944 * The bit 7,8,9 of 0x42020.
6945 */
6946 if (IS_IRONLAKE_M(dev)) {
4bb35334 6947 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6948 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6949 I915_READ(ILK_DISPLAY_CHICKEN1) |
6950 ILK_FBCQ_DIS);
6951 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6952 I915_READ(ILK_DISPLAY_CHICKEN2) |
6953 ILK_DPARB_GATE);
6f1d69b0
ED		 6954 }
6955
4d47e4f5
DL		 6956 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6957
6f1d69b0
ED		 6958 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6959 I915_READ(ILK_DISPLAY_CHICKEN2) |
6960 ILK_ELPIN_409_SELECT);
6961 I915_WRITE(_3D_CHICKEN2,
6962 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6963 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6964
ecdb4eb7 6965 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6966 I915_WRITE(CACHE_MODE_0,
6967 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6968
4e04632e
AG		 6969 /* WaDisable_RenderCache_OperationalFlush:ilk */
6970 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6971
0e088b8f 6972 g4x_disable_trickle_feed(dev);
bdad2b2f 6973
3107bd48
DV		 6974 ibx_init_clock_gating(dev);
6975}
6976
6977static void cpt_init_clock_gating(struct drm_device *dev)
6978{
fac5e23e 6979 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6980 int pipe;
3f704fa2 6981 uint32_t val;
3107bd48
DV		 6982
6983 /*
6984 * On Ibex Peak and Cougar Point, we need to disable clock
6985 * gating for the panel power sequencer or it will fail to
6986 * start up when no ports are active.
6987 */
cd664078
JB		 6988 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6989 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6990 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6991 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6992 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6993 /* The below fixes the weird display corruption, a few pixels shifted
6994 * downward, on (only) LVDS of some HP laptops with IVY.
6995 */
055e393f 6996 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 6997 val = I915_READ(TRANS_CHICKEN2(pipe));
6998 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
6999 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 7000 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 7001 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7002 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7003 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7004 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7005 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7006 }
3107bd48 7007 /* WADP0ClockGatingDisable */
055e393f 7008 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7009 I915_WRITE(TRANS_CHICKEN1(pipe),
7010 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7011 }
6f1d69b0
ED		 7012}
7013
1d7aaa0c
DV		 7014static void gen6_check_mch_setup(struct drm_device *dev)
7015{
fac5e23e 7016 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7017 uint32_t tmp;
7018
7019 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7020 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7021 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7022 tmp);
1d7aaa0c
DV		 7023}
7024
1fa61106 7025static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7026{
fac5e23e 7027 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7028 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7029
231e54f6 7030 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7031
7032 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7033 I915_READ(ILK_DISPLAY_CHICKEN2) |
7034 ILK_ELPIN_409_SELECT);
7035
ecdb4eb7 7036 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7037 I915_WRITE(_3D_CHICKEN,
7038 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7039
4e04632e
AG		 7040 /* WaDisable_RenderCache_OperationalFlush:snb */
7041 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7042
8d85d272
VS		 7043 /*
7044 * BSpec recoomends 8x4 when MSAA is used,
7045 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7046 *
7047 * Note that PS/WM thread counts depend on the WIZ hashing
7048 * disable bit, which we don't touch here, but it's good
7049 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7050 */
7051 I915_WRITE(GEN6_GT_MODE,
98533251 7052 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7053
017636cc 7054 ilk_init_lp_watermarks(dev);
6f1d69b0 7055
6f1d69b0 7056 I915_WRITE(CACHE_MODE_0,
50743298 7057 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7058
7059 I915_WRITE(GEN6_UCGCTL1,
7060 I915_READ(GEN6_UCGCTL1) |
7061 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7062 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7063
7064 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7065 * gating disable must be set. Failure to set it results in
7066 * flickering pixels due to Z write ordering failures after
7067 * some amount of runtime in the Mesa "fire" demo, and Unigine
7068 * Sanctuary and Tropics, and apparently anything else with
7069 * alpha test or pixel discard.
7070 *
7071 * According to the spec, bit 11 (RCCUNIT) must also be set,
7072 * but we didn't debug actual testcases to find it out.
0f846f81 7073 *
ef59318c
VS		 7074 * WaDisableRCCUnitClockGating:snb
7075 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7076 */
7077 I915_WRITE(GEN6_UCGCTL2,
7078 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7079 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7080
5eb146dd 7081 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7082 I915_WRITE(_3D_CHICKEN3,
7083 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7084
e927ecde
VS		 7085 /*
7086 * Bspec says:
7087 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7088 * 3DSTATE_SF number of SF output attributes is more than 16."
7089 */
7090 I915_WRITE(_3D_CHICKEN3,
7091 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7092
6f1d69b0
ED		 7093 /*
7094 * According to the spec the following bits should be
7095 * set in order to enable memory self-refresh and fbc:
7096 * The bit21 and bit22 of 0x42000
7097 * The bit21 and bit22 of 0x42004
7098 * The bit5 and bit7 of 0x42020
7099 * The bit14 of 0x70180
7100 * The bit14 of 0x71180
4bb35334
DL		 7101 *
7102 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7103 */
7104 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7105 I915_READ(ILK_DISPLAY_CHICKEN1) |
7106 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7107 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7108 I915_READ(ILK_DISPLAY_CHICKEN2) |
7109 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7110 I915_WRITE(ILK_DSPCLK_GATE_D,
7111 I915_READ(ILK_DSPCLK_GATE_D) |
7112 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7113 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7114
0e088b8f 7115 g4x_disable_trickle_feed(dev);
f8f2ac9a 7116
3107bd48 7117 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7118
7119 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7120}
7121
7122static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7123{
7124 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7125
3aad9059 7126 /*
46680e0a 7127 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7128 *
7129 * This actually overrides the dispatch
7130 * mode for all thread types.
7131 */
6f1d69b0
ED		 7132 reg &= ~GEN7_FF_SCHED_MASK;
7133 reg |= GEN7_FF_TS_SCHED_HW;
7134 reg |= GEN7_FF_VS_SCHED_HW;
7135 reg |= GEN7_FF_DS_SCHED_HW;
7136
7137 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7138}
7139
17a303ec
PZ		 7140static void lpt_init_clock_gating(struct drm_device *dev)
7141{
fac5e23e 7142 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7143
7144 /*
7145 * TODO: this bit should only be enabled when really needed, then
7146 * disabled when not needed anymore in order to save power.
7147 */
c2699524 7148 if (HAS_PCH_LPT_LP(dev))
17a303ec
PZ		 7149 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7150 I915_READ(SOUTH_DSPCLK_GATE_D) |
7151 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7152
7153 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7154 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7155 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7156 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7157}
7158
7d708ee4
ID		 7159static void lpt_suspend_hw(struct drm_device *dev)
7160{
fac5e23e 7161 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7162
c2699524 7163 if (HAS_PCH_LPT_LP(dev)) {
7d708ee4
ID		 7164 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7165
7166 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7167 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7168 }
7169}
7170
450174fe
ID		 7171static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7172 int general_prio_credits,
7173 int high_prio_credits)
7174{
7175 u32 misccpctl;
7176
7177 /* WaTempDisableDOPClkGating:bdw */
7178 misccpctl = I915_READ(GEN7_MISCCPCTL);
7179 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7180
7181 I915_WRITE(GEN8_L3SQCREG1,
7182 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7183 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7184
7185 /*
7186 * Wait at least 100 clocks before re-enabling clock gating.
7187 * See the definition of L3SQCREG1 in BSpec.
7188 */
7189 POSTING_READ(GEN8_L3SQCREG1);
7190 udelay(1);
7191 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7192}
7193
9498dba7
MK		 7194static void kabylake_init_clock_gating(struct drm_device *dev)
7195{
9146f308 7196 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7197
b033bb6d 7198 gen9_init_clock_gating(dev);
9498dba7
MK		 7199
7200 /* WaDisableSDEUnitClockGating:kbl */
7201 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7202 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7203 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7204
7205 /* WaDisableGamClockGating:kbl */
7206 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7207 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7208 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7209
7210 /* WaFbcNukeOnHostModify:kbl */
7211 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7212 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7213}
7214
dc00b6a0
DV		 7215static void skylake_init_clock_gating(struct drm_device *dev)
7216{
c584e2d3 7217 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7218
b033bb6d 7219 gen9_init_clock_gating(dev);
44fff99f
MK		 7220
7221 /* WAC6entrylatency:skl */
7222 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7223 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7224
7225 /* WaFbcNukeOnHostModify:skl */
7226 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7227 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7228}
7229
47c2bd97 7230static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7231{
fac5e23e 7232 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7233 enum pipe pipe;
1020a5c2 7234
7ad0dbab 7235 ilk_init_lp_watermarks(dev);
50ed5fbd 7236
ab57fff1 7237 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7238 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7239
ab57fff1 7240 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7241 I915_WRITE(CHICKEN_PAR1_1,
7242 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7243
ab57fff1 7244 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7245 for_each_pipe(dev_priv, pipe) {
07d27e20 7246 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7247 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7248 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7249 }
63801f21 7250
ab57fff1
BW		 7251 /* WaVSRefCountFullforceMissDisable:bdw */
7252 /* WaDSRefCountFullforceMissDisable:bdw */
7253 I915_WRITE(GEN7_FF_THREAD_MODE,
7254 I915_READ(GEN7_FF_THREAD_MODE) &
7255 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7256
295e8bb7
VS		 7257 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7258 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7259
7260 /* WaDisableSDEUnitClockGating:bdw */
7261 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7262 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7263
450174fe
ID		 7264 /* WaProgramL3SqcReg1Default:bdw */
7265 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7266
6d50b065
VS		 7267 /*
7268 * WaGttCachingOffByDefault:bdw
7269 * GTT cache may not work with big pages, so if those
7270 * are ever enabled GTT cache may need to be disabled.
7271 */
7272 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7273
17e0adf0
MK		 7274 /* WaKVMNotificationOnConfigChange:bdw */
7275 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7276 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7277
89d6b2b8 7278 lpt_init_clock_gating(dev);
1020a5c2
BW		 7279}
7280
cad2a2d7
ED		 7281static void haswell_init_clock_gating(struct drm_device *dev)
7282{
fac5e23e 7283 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7284
017636cc 7285 ilk_init_lp_watermarks(dev);
cad2a2d7 7286
f3fc4884
FJ		 7287 /* L3 caching of data atomics doesn't work -- disable it. */
7288 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7289 I915_WRITE(HSW_ROW_CHICKEN3,
7290 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7291
ecdb4eb7 7292 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7293 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7294 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7295 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7296
e36ea7ff
VS		 7297 /* WaVSRefCountFullforceMissDisable:hsw */
7298 I915_WRITE(GEN7_FF_THREAD_MODE,
7299 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7300
4e04632e
AG		 7301 /* WaDisable_RenderCache_OperationalFlush:hsw */
7302 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7303
fe27c606
CW		 7304 /* enable HiZ Raw Stall Optimization */
7305 I915_WRITE(CACHE_MODE_0_GEN7,
7306 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7307
ecdb4eb7 7308 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7309 I915_WRITE(CACHE_MODE_1,
7310 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7311
a12c4967
VS		 7312 /*
7313 * BSpec recommends 8x4 when MSAA is used,
7314 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7315 *
7316 * Note that PS/WM thread counts depend on the WIZ hashing
7317 * disable bit, which we don't touch here, but it's good
7318 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7319 */
7320 I915_WRITE(GEN7_GT_MODE,
98533251 7321 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7322
94411593
KG		 7323 /* WaSampleCChickenBitEnable:hsw */
7324 I915_WRITE(HALF_SLICE_CHICKEN3,
7325 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7326
ecdb4eb7 7327 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7328 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7329
90a88643
PZ		 7330 /* WaRsPkgCStateDisplayPMReq:hsw */
7331 I915_WRITE(CHICKEN_PAR1_1,
7332 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7333
17a303ec 7334 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7335}
7336
1fa61106 7337static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7338{
fac5e23e 7339 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7340 uint32_t snpcr;
6f1d69b0 7341
017636cc 7342 ilk_init_lp_watermarks(dev);
6f1d69b0 7343
231e54f6 7344 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7345
ecdb4eb7 7346 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7347 I915_WRITE(_3D_CHICKEN3,
7348 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7349
ecdb4eb7 7350 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7351 I915_WRITE(IVB_CHICKEN3,
7352 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7353 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7354
ecdb4eb7 7355 /* WaDisablePSDDualDispatchEnable:ivb */
12f3382b
JB		 7356 if (IS_IVB_GT1(dev))
7357 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7358 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7359
4e04632e
AG		 7360 /* WaDisable_RenderCache_OperationalFlush:ivb */
7361 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7362
ecdb4eb7 7363 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7364 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7365 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7366
ecdb4eb7 7367 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7368 I915_WRITE(GEN7_L3CNTLREG1,
7369 GEN7_WA_FOR_GEN7_L3_CONTROL);
7370 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 7371 GEN7_WA_L3_CHICKEN_MODE);
7372 if (IS_IVB_GT1(dev))
7373 I915_WRITE(GEN7_ROW_CHICKEN2,
7374 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7375 else {
7376 /* must write both registers */
7377 I915_WRITE(GEN7_ROW_CHICKEN2,
7378 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7379 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7380 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7381 }
6f1d69b0 7382
ecdb4eb7 7383 /* WaForceL3Serialization:ivb */
61939d97
JB		 7384 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7385 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7386
1b80a19a 7387 /*
0f846f81 7388 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7389 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7390 */
7391 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7392 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7393
ecdb4eb7 7394 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7395 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7396 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7397 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7398
0e088b8f 7399 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7400
7401 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7402
22721343
CW		 7403 if (0) { /* causes HiZ corruption on ivb:gt1 */
7404 /* enable HiZ Raw Stall Optimization */
7405 I915_WRITE(CACHE_MODE_0_GEN7,
7406 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7407 }
116f2b6d 7408
ecdb4eb7 7409 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7410 I915_WRITE(CACHE_MODE_1,
7411 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7412
a607c1a4
VS		 7413 /*
7414 * BSpec recommends 8x4 when MSAA is used,
7415 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7416 *
7417 * Note that PS/WM thread counts depend on the WIZ hashing
7418 * disable bit, which we don't touch here, but it's good
7419 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7420 */
7421 I915_WRITE(GEN7_GT_MODE,
98533251 7422 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7423
20848223
BW		 7424 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7425 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7426 snpcr |= GEN6_MBC_SNPCR_MED;
7427 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7428
ab5c608b
BW		 7429 if (!HAS_PCH_NOP(dev))
7430 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7431
7432 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7433}
7434
1fa61106 7435static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7436{
fac5e23e 7437 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7438
ecdb4eb7 7439 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7440 I915_WRITE(_3D_CHICKEN3,
7441 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7442
ecdb4eb7 7443 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7444 I915_WRITE(IVB_CHICKEN3,
7445 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7446 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7447
fad7d36e 7448 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7449 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7450 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7451 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7452 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7453
4e04632e
AG		 7454 /* WaDisable_RenderCache_OperationalFlush:vlv */
7455 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7456
ecdb4eb7 7457 /* WaForceL3Serialization:vlv */
61939d97
JB		 7458 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7459 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7460
ecdb4eb7 7461 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7462 I915_WRITE(GEN7_ROW_CHICKEN2,
7463 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7464
ecdb4eb7 7465 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7466 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7467 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7468 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7469
46680e0a
VS		 7470 gen7_setup_fixed_func_scheduler(dev_priv);
7471
3c0edaeb 7472 /*
0f846f81 7473 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7474 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7475 */
7476 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7477 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7478
c98f5062
AG		 7479 /* WaDisableL3Bank2xClockGate:vlv
7480 * Disabling L3 clock gating- MMIO 940c[25] = 1
7481 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7482 I915_WRITE(GEN7_UCGCTL4,
7483 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7484
afd58e79
VS		 7485 /*
7486 * BSpec says this must be set, even though
7487 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7488 */
6b26c86d
DV		 7489 I915_WRITE(CACHE_MODE_1,
7490 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7491
da2518f9
VS		 7492 /*
7493 * BSpec recommends 8x4 when MSAA is used,
7494 * however in practice 16x4 seems fastest.
7495 *
7496 * Note that PS/WM thread counts depend on the WIZ hashing
7497 * disable bit, which we don't touch here, but it's good
7498 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7499 */
7500 I915_WRITE(GEN7_GT_MODE,
7501 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7502
031994ee
VS		 7503 /*
7504 * WaIncreaseL3CreditsForVLVB0:vlv
7505 * This is the hardware default actually.
7506 */
7507 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7508
2d809570 7509 /*
ecdb4eb7 7510 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7511 * Disable clock gating on th GCFG unit to prevent a delay
7512 * in the reporting of vblank events.
7513 */
7a0d1eed 7514 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7515}
7516
a4565da8
VS		 7517static void cherryview_init_clock_gating(struct drm_device *dev)
7518{
fac5e23e 7519 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7520
232ce337
VS		 7521 /* WaVSRefCountFullforceMissDisable:chv */
7522 /* WaDSRefCountFullforceMissDisable:chv */
7523 I915_WRITE(GEN7_FF_THREAD_MODE,
7524 I915_READ(GEN7_FF_THREAD_MODE) &
7525 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7526
7527 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7528 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7529 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7530
7531 /* WaDisableCSUnitClockGating:chv */
7532 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7533 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7534
7535 /* WaDisableSDEUnitClockGating:chv */
7536 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7537 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7538
450174fe
ID		 7539 /*
7540 * WaProgramL3SqcReg1Default:chv
7541 * See gfxspecs/Related Documents/Performance Guide/
7542 * LSQC Setting Recommendations.
7543 */
7544 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7545
6d50b065
VS		 7546 /*
7547 * GTT cache may not work with big pages, so if those
7548 * are ever enabled GTT cache may need to be disabled.
7549 */
7550 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7551}
7552
1fa61106 7553static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7554{
fac5e23e 7555 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7556 uint32_t dspclk_gate;
7557
7558 I915_WRITE(RENCLK_GATE_D1, 0);
7559 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7560 GS_UNIT_CLOCK_GATE_DISABLE |
7561 CL_UNIT_CLOCK_GATE_DISABLE);
7562 I915_WRITE(RAMCLK_GATE_D, 0);
7563 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7564 OVRUNIT_CLOCK_GATE_DISABLE |
7565 OVCUNIT_CLOCK_GATE_DISABLE;
7566 if (IS_GM45(dev))
7567 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7568 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7569
7570 /* WaDisableRenderCachePipelinedFlush */
7571 I915_WRITE(CACHE_MODE_0,
7572 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7573
4e04632e
AG		 7574 /* WaDisable_RenderCache_OperationalFlush:g4x */
7575 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7576
0e088b8f 7577 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7578}
7579
1fa61106 7580static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7581{
fac5e23e 7582 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7583
7584 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7585 I915_WRITE(RENCLK_GATE_D2, 0);
7586 I915_WRITE(DSPCLK_GATE_D, 0);
7587 I915_WRITE(RAMCLK_GATE_D, 0);
7588 I915_WRITE16(DEUC, 0);
20f94967
VS		 7589 I915_WRITE(MI_ARB_STATE,
7590 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7591
7592 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7593 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7594}
7595
1fa61106 7596static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7597{
fac5e23e 7598 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7599
7600 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7601 I965_RCC_CLOCK_GATE_DISABLE |
7602 I965_RCPB_CLOCK_GATE_DISABLE |
7603 I965_ISC_CLOCK_GATE_DISABLE |
7604 I965_FBC_CLOCK_GATE_DISABLE);
7605 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7606 I915_WRITE(MI_ARB_STATE,
7607 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7608
7609 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7610 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7611}
7612
1fa61106 7613static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7614{
fac5e23e 7615 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7616 u32 dstate = I915_READ(D_STATE);
7617
7618 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7619 DSTATE_DOT_CLOCK_GATING;
7620 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7621
7622 if (IS_PINEVIEW(dev))
7623 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7624
7625 /* IIR "flip pending" means done if this bit is set */
7626 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7627
7628 /* interrupts should cause a wake up from C3 */
3299254f 7629 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7630
7631 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7632 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7633
7634 I915_WRITE(MI_ARB_STATE,
7635 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7636}
7637
1fa61106 7638static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7639{
fac5e23e 7640 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7641
7642 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7643
7644 /* interrupts should cause a wake up from C3 */
7645 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7646 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7647
7648 I915_WRITE(MEM_MODE,
7649 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7650}
7651
1fa61106 7652static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7653{
fac5e23e 7654 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7655
7656 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7657
7658 I915_WRITE(MEM_MODE,
7659 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7660 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7661}
7662
6f1d69b0
ED		 7663void intel_init_clock_gating(struct drm_device *dev)
7664{
fac5e23e 7665 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7666
bb400da9 7667 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7668}
7669
7d708ee4
ID		 7670void intel_suspend_hw(struct drm_device *dev)
7671{
7672 if (HAS_PCH_LPT(dev))
7673 lpt_suspend_hw(dev);
7674}
7675
bb400da9
ID		 7676static void nop_init_clock_gating(struct drm_device *dev)
7677{
7678 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7679}
7680
7681/**
7682 * intel_init_clock_gating_hooks - setup the clock gating hooks
7683 * @dev_priv: device private
7684 *
7685 * Setup the hooks that configure which clocks of a given platform can be
7686 * gated and also apply various GT and display specific workarounds for these
7687 * platforms. Note that some GT specific workarounds are applied separately
7688 * when GPU contexts or batchbuffers start their execution.
7689 */
7690void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7691{
7692 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7693 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7694 else if (IS_KABYLAKE(dev_priv))
9498dba7 7695 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7696 else if (IS_BROXTON(dev_priv))
7697 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7698 else if (IS_BROADWELL(dev_priv))
7699 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7700 else if (IS_CHERRYVIEW(dev_priv))
7701 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7702 else if (IS_HASWELL(dev_priv))
7703 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7704 else if (IS_IVYBRIDGE(dev_priv))
7705 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7706 else if (IS_VALLEYVIEW(dev_priv))
7707 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7708 else if (IS_GEN6(dev_priv))
7709 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7710 else if (IS_GEN5(dev_priv))
7711 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7712 else if (IS_G4X(dev_priv))
7713 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7714 else if (IS_CRESTLINE(dev_priv))
7715 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7716 else if (IS_BROADWATER(dev_priv))
7717 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7718 else if (IS_GEN3(dev_priv))
7719 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7720 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7721 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7722 else if (IS_GEN2(dev_priv))
7723 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7724 else {
7725 MISSING_CASE(INTEL_DEVID(dev_priv));
7726 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7727 }
7728}
7729
1fa61106
ED		 7730/* Set up chip specific power management-related functions */
7731void intel_init_pm(struct drm_device *dev)
7732{
fac5e23e 7733 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7734
7ff0ebcc 7735 intel_fbc_init(dev_priv);
1fa61106 7736
c921aba8
DV		 7737 /* For cxsr */
7738 if (IS_PINEVIEW(dev))
7739 i915_pineview_get_mem_freq(dev);
7740 else if (IS_GEN5(dev))
7741 i915_ironlake_get_mem_freq(dev);
7742
1fa61106 7743 /* For FIFO watermark updates */
f5ed50cb 7744 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7745 skl_setup_wm_latency(dev);
2d41c0b5 7746 dev_priv->display.update_wm = skl_update_wm;
98d39494 7747 dev_priv->display.compute_global_watermarks = skl_compute_wm;
c83155a6 7748 } else if (HAS_PCH_SPLIT(dev)) {
fa50ad61 7749 ilk_setup_wm_latency(dev);
53615a5e 7750
bd602544
VS		 7751 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7752 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7753 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7754 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7755 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7756 dev_priv->display.compute_intermediate_wm =
7757 ilk_compute_intermediate_wm;
7758 dev_priv->display.initial_watermarks =
7759 ilk_initial_watermarks;
7760 dev_priv->display.optimize_watermarks =
7761 ilk_optimize_watermarks;
bd602544
VS		 7762 } else {
7763 DRM_DEBUG_KMS("Failed to read display plane latency. "
7764 "Disable CxSR\n");
7765 }
a4565da8 7766 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7767 vlv_setup_wm_latency(dev);
262cd2e1 7768 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7769 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7770 vlv_setup_wm_latency(dev);
26e1fe4f 7771 dev_priv->display.update_wm = vlv_update_wm;
1fa61106
ED		 7772 } else if (IS_PINEVIEW(dev)) {
7773 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
7774 dev_priv->is_ddr3,
7775 dev_priv->fsb_freq,
7776 dev_priv->mem_freq)) {
7777 DRM_INFO("failed to find known CxSR latency "
7778 "(found ddr%s fsb freq %d, mem freq %d), "
7779 "disabling CxSR\n",
7780 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7781 dev_priv->fsb_freq, dev_priv->mem_freq);
7782 /* Disable CxSR and never update its watermark again */
5209b1f4 7783 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7784 dev_priv->display.update_wm = NULL;
7785 } else
7786 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7787 } else if (IS_G4X(dev)) {
7788 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7789 } else if (IS_GEN4(dev)) {
7790 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7791 } else if (IS_GEN3(dev)) {
7792 dev_priv->display.update_wm = i9xx_update_wm;
7793 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7794 } else if (IS_GEN2(dev)) {
7795 if (INTEL_INFO(dev)->num_pipes == 1) {
7796 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7797 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7798 } else {
7799 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7800 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7801 }
feb56b93
DV		 7802 } else {
7803 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7804 }
7805}
7806
87660502
L		 7807static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7808{
7809 uint32_t flags =
7810 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7811
7812 switch (flags) {
7813 case GEN6_PCODE_SUCCESS:
7814 return 0;
7815 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7816 case GEN6_PCODE_ILLEGAL_CMD:
7817 return -ENXIO;
7818 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7819 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7820 return -EOVERFLOW;
7821 case GEN6_PCODE_TIMEOUT:
7822 return -ETIMEDOUT;
7823 default:
7824 MISSING_CASE(flags)
7825 return 0;
7826 }
7827}
7828
7829static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7830{
7831 uint32_t flags =
7832 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7833
7834 switch (flags) {
7835 case GEN6_PCODE_SUCCESS:
7836 return 0;
7837 case GEN6_PCODE_ILLEGAL_CMD:
7838 return -ENXIO;
7839 case GEN7_PCODE_TIMEOUT:
7840 return -ETIMEDOUT;
7841 case GEN7_PCODE_ILLEGAL_DATA:
7842 return -EINVAL;
7843 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7844 return -EOVERFLOW;
7845 default:
7846 MISSING_CASE(flags);
7847 return 0;
7848 }
7849}
7850
151a49d0 7851int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7852{
87660502
L		 7853 int status;
7854
4fc688ce 7855 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7856
3f5582dd
CW		 7857 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7858 * use te fw I915_READ variants to reduce the amount of work
7859 * required when reading/writing.
7860 */
7861
7862 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7863 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7864 return -EAGAIN;
7865 }
7866
3f5582dd
CW		 7867 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7868 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7869 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7870
3f5582dd
CW		 7871 if (intel_wait_for_register_fw(dev_priv,
7872 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7873 500)) {
42c0526c
BW		 7874 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7875 return -ETIMEDOUT;
7876 }
7877
3f5582dd
CW		 7878 *val = I915_READ_FW(GEN6_PCODE_DATA);
7879 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7880
87660502
L		 7881 if (INTEL_GEN(dev_priv) > 6)
7882 status = gen7_check_mailbox_status(dev_priv);
7883 else
7884 status = gen6_check_mailbox_status(dev_priv);
7885
7886 if (status) {
7887 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7888 status);
7889 return status;
7890 }
7891
42c0526c
BW		 7892 return 0;
7893}
7894
3f5582dd 7895int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7896 u32 mbox, u32 val)
42c0526c 7897{
87660502
L		 7898 int status;
7899
4fc688ce 7900 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7901
3f5582dd
CW		 7902 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7903 * use te fw I915_READ variants to reduce the amount of work
7904 * required when reading/writing.
7905 */
7906
7907 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7908 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7909 return -EAGAIN;
7910 }
7911
3f5582dd
CW		 7912 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7913 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7914
3f5582dd
CW		 7915 if (intel_wait_for_register_fw(dev_priv,
7916 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7917 500)) {
42c0526c
BW		 7918 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7919 return -ETIMEDOUT;
7920 }
7921
3f5582dd 7922 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7923
87660502
L		 7924 if (INTEL_GEN(dev_priv) > 6)
7925 status = gen7_check_mailbox_status(dev_priv);
7926 else
7927 status = gen6_check_mailbox_status(dev_priv);
7928
7929 if (status) {
7930 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7931 status);
7932 return status;
7933 }
7934
42c0526c
BW		 7935 return 0;
7936}
a0e4e199 7937
dd06f88c
VS		 7938static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7939{
c30fec65
VS		 7940 /*
7941 * N = val - 0xb7
7942 * Slow = Fast = GPLL ref * N
7943 */
7944 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7945}
7946
b55dd647 7947static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7948{
c30fec65 7949 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7950}
7951
b55dd647 7952static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7953{
c30fec65
VS		 7954 /*
7955 * N = val / 2
7956 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7957 */
7958 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7959}
7960
b55dd647 7961static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7962{
1c14762d 7963 /* CHV needs even values */
c30fec65 7964 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7965}
7966
616bc820 7967int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7968{
2d1fe073 7969 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7970 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7971 GEN9_FREQ_SCALER);
2d1fe073 7972 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7973 return chv_gpu_freq(dev_priv, val);
2d1fe073 7974 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7975 return byt_gpu_freq(dev_priv, val);
7976 else
7977 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7978}
7979
616bc820
VS		 7980int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7981{
2d1fe073 7982 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7983 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7984 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7985 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7986 return chv_freq_opcode(dev_priv, val);
2d1fe073 7987 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7988 return byt_freq_opcode(dev_priv, val);
7989 else
500a3d2e 7990 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7991}
22b1b2f8 7992
6ad790c0
CW		 7993struct request_boost {
7994 struct work_struct work;
eed29a5b 7995 struct drm_i915_gem_request *req;
6ad790c0
CW		 7996};
7997
7998static void __intel_rps_boost_work(struct work_struct *work)
7999{
8000 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8001 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8002
f69a02c9 8003 if (!i915_gem_request_completed(req))
c033666a 8004 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8005
e8a261ea 8006 i915_gem_request_put(req);
6ad790c0
CW		 8007 kfree(boost);
8008}
8009
91d14251 8010void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8011{
8012 struct request_boost *boost;
8013
91d14251 8014 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8015 return;
8016
f69a02c9 8017 if (i915_gem_request_completed(req))
e61b9958
CW		 8018 return;
8019
6ad790c0
CW		 8020 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8021 if (boost == NULL)
8022 return;
8023
e8a261ea 8024 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8025
8026 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8027 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8028}
8029
f742a552 8030void intel_pm_setup(struct drm_device *dev)
907b28c5 8031{
fac5e23e 8032 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8033
f742a552 8034 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8035 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8036
54b4f68f
CW		 8037 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8038 __intel_autoenable_gt_powersave);
1854d5ca 8039 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8040
33688d95 8041 dev_priv->pm.suspended = false;
1f814dac 8042 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 8043 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8044}
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