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drm/i915: Make HAS_L3_DPF only take dev_priv
[mirror_ubuntu-jammy-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
9c2f7a9d 29#include <drm/drm_plane_helper.h>
85208be0
ED		 30#include "i915_drv.h"
31#include "intel_drv.h"
eb48eb00
DV		 32#include "../../../platform/x86/intel_ips.h"
33#include <linux/module.h>
85208be0 34
dc39fff7 35/**
18afd443
JN		 36 * DOC: RC6
37 *
dc39fff7
BW		 38 * RC6 is a special power stage which allows the GPU to enter an very
39 * low-voltage mode when idle, using down to 0V while at this stage. This
40 * stage is entered automatically when the GPU is idle when RC6 support is
41 * enabled, and as soon as new workload arises GPU wakes up automatically as well.
42 *
43 * There are different RC6 modes available in Intel GPU, which differentiate
44 * among each other with the latency required to enter and leave RC6 and
45 * voltage consumed by the GPU in different states.
46 *
47 * The combination of the following flags define which states GPU is allowed
48 * to enter, while RC6 is the normal RC6 state, RC6p is the deep RC6, and
49 * RC6pp is deepest RC6. Their support by hardware varies according to the
50 * GPU, BIOS, chipset and platform. RC6 is usually the safest one and the one
51 * which brings the most power savings; deeper states save more power, but
52 * require higher latency to switch to and wake up.
53 */
54#define INTEL_RC6_ENABLE (1<<0)
55#define INTEL_RC6p_ENABLE (1<<1)
56#define INTEL_RC6pp_ENABLE (1<<2)
57
b033bb6d 58static void gen9_init_clock_gating(struct drm_device *dev)
a82abe43 59{
32608ca2
ID		 60 struct drm_i915_private *dev_priv = dev->dev_private;
61
b033bb6d 62 /* See Bspec note for PSR2_CTL bit 31, Wa#828:skl,bxt,kbl */
dc00b6a0
DV		 63 I915_WRITE(CHICKEN_PAR1_1,
64 I915_READ(CHICKEN_PAR1_1) | SKL_EDP_PSR_FIX_RDWRAP);
65
b033bb6d
MK		 66 I915_WRITE(GEN8_CONFIG0,
67 I915_READ(GEN8_CONFIG0) | GEN9_DEFAULT_FIXES);
590e8ff0
MK		 68
69 /* WaEnableChickenDCPR:skl,bxt,kbl */
70 I915_WRITE(GEN8_CHICKEN_DCPR_1,
71 I915_READ(GEN8_CHICKEN_DCPR_1) | MASK_WAKEMEM);
0f78dee6
MK		 72
73 /* WaFbcTurnOffFbcWatermark:skl,bxt,kbl */
303d4ea5
MK		 74 /* WaFbcWakeMemOn:skl,bxt,kbl */
75 I915_WRITE(DISP_ARB_CTL, I915_READ(DISP_ARB_CTL) |
76 DISP_FBC_WM_DIS |
77 DISP_FBC_MEMORY_WAKE);
d1b4eefd
MK		 78
79 /* WaFbcHighMemBwCorruptionAvoidance:skl,bxt,kbl */
80 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
81 ILK_DPFC_DISABLE_DUMMY0);
b033bb6d
MK		 82}
83
84static void bxt_init_clock_gating(struct drm_device *dev)
85{
fac5e23e 86 struct drm_i915_private *dev_priv = to_i915(dev);
b033bb6d
MK		 87
88 gen9_init_clock_gating(dev);
89
a7546159
NH		 90 /* WaDisableSDEUnitClockGating:bxt */
91 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
92 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
93
32608ca2
ID		 94 /*
95 * FIXME:
868434c5 96 * GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ applies on 3x6 GT SKUs only.
32608ca2 97 */
32608ca2 98 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
868434c5 99 GEN8_HDCUNIT_CLOCK_GATE_DISABLE_HDCREQ);
d965e7ac
ID		 100
101 /*
102 * Wa: Backlight PWM may stop in the asserted state, causing backlight
103 * to stay fully on.
104 */
105 if (IS_BXT_REVID(dev_priv, BXT_REVID_B0, REVID_FOREVER))
106 I915_WRITE(GEN9_CLKGATE_DIS_0, I915_READ(GEN9_CLKGATE_DIS_0) |
107 PWM1_GATING_DIS | PWM2_GATING_DIS);
a82abe43
ID		 108}
109
c921aba8
DV		 110static void i915_pineview_get_mem_freq(struct drm_device *dev)
111{
fac5e23e 112 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 113 u32 tmp;
114
115 tmp = I915_READ(CLKCFG);
116
117 switch (tmp & CLKCFG_FSB_MASK) {
118 case CLKCFG_FSB_533:
119 dev_priv->fsb_freq = 533; /* 133*4 */
120 break;
121 case CLKCFG_FSB_800:
122 dev_priv->fsb_freq = 800; /* 200*4 */
123 break;
124 case CLKCFG_FSB_667:
125 dev_priv->fsb_freq = 667; /* 167*4 */
126 break;
127 case CLKCFG_FSB_400:
128 dev_priv->fsb_freq = 400; /* 100*4 */
129 break;
130 }
131
132 switch (tmp & CLKCFG_MEM_MASK) {
133 case CLKCFG_MEM_533:
134 dev_priv->mem_freq = 533;
135 break;
136 case CLKCFG_MEM_667:
137 dev_priv->mem_freq = 667;
138 break;
139 case CLKCFG_MEM_800:
140 dev_priv->mem_freq = 800;
141 break;
142 }
143
144 /* detect pineview DDR3 setting */
145 tmp = I915_READ(CSHRDDR3CTL);
146 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
147}
148
149static void i915_ironlake_get_mem_freq(struct drm_device *dev)
150{
fac5e23e 151 struct drm_i915_private *dev_priv = to_i915(dev);
c921aba8
DV		 152 u16 ddrpll, csipll;
153
154 ddrpll = I915_READ16(DDRMPLL1);
155 csipll = I915_READ16(CSIPLL0);
156
157 switch (ddrpll & 0xff) {
158 case 0xc:
159 dev_priv->mem_freq = 800;
160 break;
161 case 0x10:
162 dev_priv->mem_freq = 1066;
163 break;
164 case 0x14:
165 dev_priv->mem_freq = 1333;
166 break;
167 case 0x18:
168 dev_priv->mem_freq = 1600;
169 break;
170 default:
171 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
172 ddrpll & 0xff);
173 dev_priv->mem_freq = 0;
174 break;
175 }
176
20e4d407 177 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 178
179 switch (csipll & 0x3ff) {
180 case 0x00c:
181 dev_priv->fsb_freq = 3200;
182 break;
183 case 0x00e:
184 dev_priv->fsb_freq = 3733;
185 break;
186 case 0x010:
187 dev_priv->fsb_freq = 4266;
188 break;
189 case 0x012:
190 dev_priv->fsb_freq = 4800;
191 break;
192 case 0x014:
193 dev_priv->fsb_freq = 5333;
194 break;
195 case 0x016:
196 dev_priv->fsb_freq = 5866;
197 break;
198 case 0x018:
199 dev_priv->fsb_freq = 6400;
200 break;
201 default:
202 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
203 csipll & 0x3ff);
204 dev_priv->fsb_freq = 0;
205 break;
206 }
207
208 if (dev_priv->fsb_freq == 3200) {
20e4d407 209 dev_priv->ips.c_m = 0;
c921aba8 210 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 211 dev_priv->ips.c_m = 1;
c921aba8 212 } else {
20e4d407 213 dev_priv->ips.c_m = 2;
c921aba8
DV		 214 }
215}
216
b445e3b0
ED		 217static const struct cxsr_latency cxsr_latency_table[] = {
218 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
219 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
220 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
221 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
222 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
223
224 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
225 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
226 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
227 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
228 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
229
230 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
231 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
232 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
233 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
234 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
235
236 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
237 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
238 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
239 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
240 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
241
242 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
243 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
244 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
245 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
246 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
247
248 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
249 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
250 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
251 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
252 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
253};
254
44a655ca
TU		 255static const struct cxsr_latency *intel_get_cxsr_latency(bool is_desktop,
256 bool is_ddr3,
b445e3b0
ED		 257 int fsb,
258 int mem)
259{
260 const struct cxsr_latency *latency;
261 int i;
262
263 if (fsb == 0 || mem == 0)
264 return NULL;
265
266 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
267 latency = &cxsr_latency_table[i];
268 if (is_desktop == latency->is_desktop &&
269 is_ddr3 == latency->is_ddr3 &&
270 fsb == latency->fsb_freq && mem == latency->mem_freq)
271 return latency;
272 }
273
274 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
275
276 return NULL;
277}
278
fc1ac8de
VS		 279static void chv_set_memory_dvfs(struct drm_i915_private *dev_priv, bool enable)
280{
281 u32 val;
282
283 mutex_lock(&dev_priv->rps.hw_lock);
284
285 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
286 if (enable)
287 val &= ~FORCE_DDR_HIGH_FREQ;
288 else
289 val |= FORCE_DDR_HIGH_FREQ;
290 val &= ~FORCE_DDR_LOW_FREQ;
291 val |= FORCE_DDR_FREQ_REQ_ACK;
292 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
293
294 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
295 FORCE_DDR_FREQ_REQ_ACK) == 0, 3))
296 DRM_ERROR("timed out waiting for Punit DDR DVFS request\n");
297
298 mutex_unlock(&dev_priv->rps.hw_lock);
299}
300
cfb41411
VS		 301static void chv_set_memory_pm5(struct drm_i915_private *dev_priv, bool enable)
302{
303 u32 val;
304
305 mutex_lock(&dev_priv->rps.hw_lock);
306
307 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
308 if (enable)
309 val |= DSP_MAXFIFO_PM5_ENABLE;
310 else
311 val &= ~DSP_MAXFIFO_PM5_ENABLE;
312 vlv_punit_write(dev_priv, PUNIT_REG_DSPFREQ, val);
313
314 mutex_unlock(&dev_priv->rps.hw_lock);
315}
316
f4998963
VS		 317#define FW_WM(value, plane) \
318 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK)
319
5209b1f4 320void intel_set_memory_cxsr(struct drm_i915_private *dev_priv, bool enable)
b445e3b0 321{
91c8a326 322 struct drm_device *dev = &dev_priv->drm;
5209b1f4 323 u32 val;
b445e3b0 324
666a4537 325 if (IS_VALLEYVIEW(dev) || IS_CHERRYVIEW(dev)) {
5209b1f4 326 I915_WRITE(FW_BLC_SELF_VLV, enable ? FW_CSPWRDWNEN : 0);
a7a6c498 327 POSTING_READ(FW_BLC_SELF_VLV);
852eb00d 328 dev_priv->wm.vlv.cxsr = enable;
5209b1f4
ID		 329 } else if (IS_G4X(dev) || IS_CRESTLINE(dev)) {
330 I915_WRITE(FW_BLC_SELF, enable ? FW_BLC_SELF_EN : 0);
a7a6c498 331 POSTING_READ(FW_BLC_SELF);
5209b1f4
ID		 332 } else if (IS_PINEVIEW(dev)) {
333 val = I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN;
334 val |= enable ? PINEVIEW_SELF_REFRESH_EN : 0;
335 I915_WRITE(DSPFW3, val);
a7a6c498 336 POSTING_READ(DSPFW3);
50a0bc90 337 } else if (IS_I945G(dev_priv) || IS_I945GM(dev_priv)) {
5209b1f4
ID		 338 val = enable ? _MASKED_BIT_ENABLE(FW_BLC_SELF_EN) :
339 _MASKED_BIT_DISABLE(FW_BLC_SELF_EN);
340 I915_WRITE(FW_BLC_SELF, val);
a7a6c498 341 POSTING_READ(FW_BLC_SELF);
50a0bc90 342 } else if (IS_I915GM(dev_priv)) {
acb91359
VS		 343 /*
344 * FIXME can't find a bit like this for 915G, and
345 * and yet it does have the related watermark in
346 * FW_BLC_SELF. What's going on?
347 */
5209b1f4
ID		 348 val = enable ? _MASKED_BIT_ENABLE(INSTPM_SELF_EN) :
349 _MASKED_BIT_DISABLE(INSTPM_SELF_EN);
350 I915_WRITE(INSTPM, val);
a7a6c498 351 POSTING_READ(INSTPM);
5209b1f4
ID		 352 } else {
353 return;
354 }
b445e3b0 355
5209b1f4
ID		 356 DRM_DEBUG_KMS("memory self-refresh is %s\n",
357 enable ? "enabled" : "disabled");
b445e3b0
ED		 358}
359
fc1ac8de 360
b445e3b0
ED		 361/*
362 * Latency for FIFO fetches is dependent on several factors:
363 * - memory configuration (speed, channels)
364 * - chipset
365 * - current MCH state
366 * It can be fairly high in some situations, so here we assume a fairly
367 * pessimal value. It's a tradeoff between extra memory fetches (if we
368 * set this value too high, the FIFO will fetch frequently to stay full)
369 * and power consumption (set it too low to save power and we might see
370 * FIFO underruns and display "flicker").
371 *
372 * A value of 5us seems to be a good balance; safe for very low end
373 * platforms but not overly aggressive on lower latency configs.
374 */
5aef6003 375static const int pessimal_latency_ns = 5000;
b445e3b0 376
b5004720
VS		 377#define VLV_FIFO_START(dsparb, dsparb2, lo_shift, hi_shift) \
378 ((((dsparb) >> (lo_shift)) & 0xff) | ((((dsparb2) >> (hi_shift)) & 0x1) << 8))
379
380static int vlv_get_fifo_size(struct drm_device *dev,
381 enum pipe pipe, int plane)
382{
fac5e23e 383 struct drm_i915_private *dev_priv = to_i915(dev);
b5004720
VS		 384 int sprite0_start, sprite1_start, size;
385
386 switch (pipe) {
387 uint32_t dsparb, dsparb2, dsparb3;
388 case PIPE_A:
389 dsparb = I915_READ(DSPARB);
390 dsparb2 = I915_READ(DSPARB2);
391 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 0, 0);
392 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 8, 4);
393 break;
394 case PIPE_B:
395 dsparb = I915_READ(DSPARB);
396 dsparb2 = I915_READ(DSPARB2);
397 sprite0_start = VLV_FIFO_START(dsparb, dsparb2, 16, 8);
398 sprite1_start = VLV_FIFO_START(dsparb, dsparb2, 24, 12);
399 break;
400 case PIPE_C:
401 dsparb2 = I915_READ(DSPARB2);
402 dsparb3 = I915_READ(DSPARB3);
403 sprite0_start = VLV_FIFO_START(dsparb3, dsparb2, 0, 16);
404 sprite1_start = VLV_FIFO_START(dsparb3, dsparb2, 8, 20);
405 break;
406 default:
407 return 0;
408 }
409
410 switch (plane) {
411 case 0:
412 size = sprite0_start;
413 break;
414 case 1:
415 size = sprite1_start - sprite0_start;
416 break;
417 case 2:
418 size = 512 - 1 - sprite1_start;
419 break;
420 default:
421 return 0;
422 }
423
424 DRM_DEBUG_KMS("Pipe %c %s %c FIFO size: %d\n",
425 pipe_name(pipe), plane == 0 ? "primary" : "sprite",
426 plane == 0 ? plane_name(pipe) : sprite_name(pipe, plane - 1),
427 size);
428
429 return size;
430}
431
1fa61106 432static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 433{
fac5e23e 434 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 435 uint32_t dsparb = I915_READ(DSPARB);
436 int size;
437
438 size = dsparb & 0x7f;
439 if (plane)
440 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
441
442 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
443 plane ? "B" : "A", size);
444
445 return size;
446}
447
feb56b93 448static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 449{
fac5e23e 450 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 451 uint32_t dsparb = I915_READ(DSPARB);
452 int size;
453
454 size = dsparb & 0x1ff;
455 if (plane)
456 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
457 size >>= 1; /* Convert to cachelines */
458
459 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
460 plane ? "B" : "A", size);
461
462 return size;
463}
464
1fa61106 465static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0 466{
fac5e23e 467 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 468 uint32_t dsparb = I915_READ(DSPARB);
469 int size;
470
471 size = dsparb & 0x7f;
472 size >>= 2; /* Convert to cachelines */
473
474 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
475 plane ? "B" : "A",
476 size);
477
478 return size;
479}
480
b445e3b0
ED		 481/* Pineview has different values for various configs */
482static const struct intel_watermark_params pineview_display_wm = {
e0f0273e
VS		 483 .fifo_size = PINEVIEW_DISPLAY_FIFO,
484 .max_wm = PINEVIEW_MAX_WM,
485 .default_wm = PINEVIEW_DFT_WM,
486 .guard_size = PINEVIEW_GUARD_WM,
487 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 488};
489static const struct intel_watermark_params pineview_display_hplloff_wm = {
e0f0273e
VS		 490 .fifo_size = PINEVIEW_DISPLAY_FIFO,
491 .max_wm = PINEVIEW_MAX_WM,
492 .default_wm = PINEVIEW_DFT_HPLLOFF_WM,
493 .guard_size = PINEVIEW_GUARD_WM,
494 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 495};
496static const struct intel_watermark_params pineview_cursor_wm = {
e0f0273e
VS		 497 .fifo_size = PINEVIEW_CURSOR_FIFO,
498 .max_wm = PINEVIEW_CURSOR_MAX_WM,
499 .default_wm = PINEVIEW_CURSOR_DFT_WM,
500 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
501 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 502};
503static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
e0f0273e
VS		 504 .fifo_size = PINEVIEW_CURSOR_FIFO,
505 .max_wm = PINEVIEW_CURSOR_MAX_WM,
506 .default_wm = PINEVIEW_CURSOR_DFT_WM,
507 .guard_size = PINEVIEW_CURSOR_GUARD_WM,
508 .cacheline_size = PINEVIEW_FIFO_LINE_SIZE,
b445e3b0
ED		 509};
510static const struct intel_watermark_params g4x_wm_info = {
e0f0273e
VS		 511 .fifo_size = G4X_FIFO_SIZE,
512 .max_wm = G4X_MAX_WM,
513 .default_wm = G4X_MAX_WM,
514 .guard_size = 2,
515 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0
ED		 516};
517static const struct intel_watermark_params g4x_cursor_wm_info = {
e0f0273e
VS		 518 .fifo_size = I965_CURSOR_FIFO,
519 .max_wm = I965_CURSOR_MAX_WM,
520 .default_wm = I965_CURSOR_DFT_WM,
521 .guard_size = 2,
522 .cacheline_size = G4X_FIFO_LINE_SIZE,
b445e3b0 523};
b445e3b0 524static const struct intel_watermark_params i965_cursor_wm_info = {
e0f0273e
VS		 525 .fifo_size = I965_CURSOR_FIFO,
526 .max_wm = I965_CURSOR_MAX_WM,
527 .default_wm = I965_CURSOR_DFT_WM,
528 .guard_size = 2,
529 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 530};
531static const struct intel_watermark_params i945_wm_info = {
e0f0273e
VS		 532 .fifo_size = I945_FIFO_SIZE,
533 .max_wm = I915_MAX_WM,
534 .default_wm = 1,
535 .guard_size = 2,
536 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0
ED		 537};
538static const struct intel_watermark_params i915_wm_info = {
e0f0273e
VS		 539 .fifo_size = I915_FIFO_SIZE,
540 .max_wm = I915_MAX_WM,
541 .default_wm = 1,
542 .guard_size = 2,
543 .cacheline_size = I915_FIFO_LINE_SIZE,
b445e3b0 544};
9d539105 545static const struct intel_watermark_params i830_a_wm_info = {
e0f0273e
VS		 546 .fifo_size = I855GM_FIFO_SIZE,
547 .max_wm = I915_MAX_WM,
548 .default_wm = 1,
549 .guard_size = 2,
550 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0 551};
9d539105
VS		 552static const struct intel_watermark_params i830_bc_wm_info = {
553 .fifo_size = I855GM_FIFO_SIZE,
554 .max_wm = I915_MAX_WM/2,
555 .default_wm = 1,
556 .guard_size = 2,
557 .cacheline_size = I830_FIFO_LINE_SIZE,
558};
feb56b93 559static const struct intel_watermark_params i845_wm_info = {
e0f0273e
VS		 560 .fifo_size = I830_FIFO_SIZE,
561 .max_wm = I915_MAX_WM,
562 .default_wm = 1,
563 .guard_size = 2,
564 .cacheline_size = I830_FIFO_LINE_SIZE,
b445e3b0
ED		 565};
566
b445e3b0
ED		 567/**
568 * intel_calculate_wm - calculate watermark level
569 * @clock_in_khz: pixel clock
570 * @wm: chip FIFO params
ac484963 571 * @cpp: bytes per pixel
b445e3b0
ED		 572 * @latency_ns: memory latency for the platform
573 *
574 * Calculate the watermark level (the level at which the display plane will
575 * start fetching from memory again). Each chip has a different display
576 * FIFO size and allocation, so the caller needs to figure that out and pass
577 * in the correct intel_watermark_params structure.
578 *
579 * As the pixel clock runs, the FIFO will be drained at a rate that depends
580 * on the pixel size. When it reaches the watermark level, it'll start
581 * fetching FIFO line sized based chunks from memory until the FIFO fills
582 * past the watermark point. If the FIFO drains completely, a FIFO underrun
583 * will occur, and a display engine hang could result.
584 */
585static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
586 const struct intel_watermark_params *wm,
ac484963 587 int fifo_size, int cpp,
b445e3b0
ED		 588 unsigned long latency_ns)
589{
590 long entries_required, wm_size;
591
592 /*
593 * Note: we need to make sure we don't overflow for various clock &
594 * latency values.
595 * clocks go from a few thousand to several hundred thousand.
596 * latency is usually a few thousand
597 */
ac484963 598 entries_required = ((clock_in_khz / 1000) * cpp * latency_ns) /
b445e3b0
ED		 599 1000;
600 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
601
602 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
603
604 wm_size = fifo_size - (entries_required + wm->guard_size);
605
606 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
607
608 /* Don't promote wm_size to unsigned... */
609 if (wm_size > (long)wm->max_wm)
610 wm_size = wm->max_wm;
611 if (wm_size <= 0)
612 wm_size = wm->default_wm;
d6feb196
VS		 613
614 /*
615 * Bspec seems to indicate that the value shouldn't be lower than
616 * 'burst size + 1'. Certainly 830 is quite unhappy with low values.
617 * Lets go for 8 which is the burst size since certain platforms
618 * already use a hardcoded 8 (which is what the spec says should be
619 * done).
620 */
621 if (wm_size <= 8)
622 wm_size = 8;
623
b445e3b0
ED		 624 return wm_size;
625}
626
627static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
628{
629 struct drm_crtc *crtc, *enabled = NULL;
630
70e1e0ec 631 for_each_crtc(dev, crtc) {
3490ea5d 632 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 633 if (enabled)
634 return NULL;
635 enabled = crtc;
636 }
637 }
638
639 return enabled;
640}
641
46ba614c 642static void pineview_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 643{
46ba614c 644 struct drm_device *dev = unused_crtc->dev;
fac5e23e 645 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 646 struct drm_crtc *crtc;
647 const struct cxsr_latency *latency;
648 u32 reg;
649 unsigned long wm;
650
50a0bc90
TU		 651 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
652 dev_priv->is_ddr3,
653 dev_priv->fsb_freq,
654 dev_priv->mem_freq);
b445e3b0
ED		 655 if (!latency) {
656 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
5209b1f4 657 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 658 return;
659 }
660
661 crtc = single_enabled_crtc(dev);
662 if (crtc) {
7c5f93b0 663 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
ac484963 664 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
7c5f93b0 665 int clock = adjusted_mode->crtc_clock;
b445e3b0
ED		 666
667 /* Display SR */
668 wm = intel_calculate_wm(clock, &pineview_display_wm,
669 pineview_display_wm.fifo_size,
ac484963 670 cpp, latency->display_sr);
b445e3b0
ED		 671 reg = I915_READ(DSPFW1);
672 reg &= ~DSPFW_SR_MASK;
f4998963 673 reg |= FW_WM(wm, SR);
b445e3b0
ED		 674 I915_WRITE(DSPFW1, reg);
675 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
676
677 /* cursor SR */
678 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
679 pineview_display_wm.fifo_size,
ac484963 680 cpp, latency->cursor_sr);
b445e3b0
ED		 681 reg = I915_READ(DSPFW3);
682 reg &= ~DSPFW_CURSOR_SR_MASK;
f4998963 683 reg |= FW_WM(wm, CURSOR_SR);
b445e3b0
ED		 684 I915_WRITE(DSPFW3, reg);
685
686 /* Display HPLL off SR */
687 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
688 pineview_display_hplloff_wm.fifo_size,
ac484963 689 cpp, latency->display_hpll_disable);
b445e3b0
ED		 690 reg = I915_READ(DSPFW3);
691 reg &= ~DSPFW_HPLL_SR_MASK;
f4998963 692 reg |= FW_WM(wm, HPLL_SR);
b445e3b0
ED		 693 I915_WRITE(DSPFW3, reg);
694
695 /* cursor HPLL off SR */
696 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
697 pineview_display_hplloff_wm.fifo_size,
ac484963 698 cpp, latency->cursor_hpll_disable);
b445e3b0
ED		 699 reg = I915_READ(DSPFW3);
700 reg &= ~DSPFW_HPLL_CURSOR_MASK;
f4998963 701 reg |= FW_WM(wm, HPLL_CURSOR);
b445e3b0
ED		 702 I915_WRITE(DSPFW3, reg);
703 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
704
5209b1f4 705 intel_set_memory_cxsr(dev_priv, true);
b445e3b0 706 } else {
5209b1f4 707 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 708 }
709}
710
711static bool g4x_compute_wm0(struct drm_device *dev,
712 int plane,
713 const struct intel_watermark_params *display,
714 int display_latency_ns,
715 const struct intel_watermark_params *cursor,
716 int cursor_latency_ns,
717 int *plane_wm,
718 int *cursor_wm)
719{
720 struct drm_crtc *crtc;
4fe8590a 721 const struct drm_display_mode *adjusted_mode;
ac484963 722 int htotal, hdisplay, clock, cpp;
b445e3b0
ED		 723 int line_time_us, line_count;
724 int entries, tlb_miss;
725
726 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 727 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 728 *cursor_wm = cursor->guard_size;
729 *plane_wm = display->guard_size;
730 return false;
731 }
732
6e3c9717 733 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 734 clock = adjusted_mode->crtc_clock;
fec8cba3 735 htotal = adjusted_mode->crtc_htotal;
6e3c9717 736 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 737 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 738
739 /* Use the small buffer method to calculate plane watermark */
ac484963 740 entries = ((clock * cpp / 1000) * display_latency_ns) / 1000;
b445e3b0
ED		 741 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
742 if (tlb_miss > 0)
743 entries += tlb_miss;
744 entries = DIV_ROUND_UP(entries, display->cacheline_size);
745 *plane_wm = entries + display->guard_size;
746 if (*plane_wm > (int)display->max_wm)
747 *plane_wm = display->max_wm;
748
749 /* Use the large buffer method to calculate cursor watermark */
922044c9 750 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 751 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
ac484963 752 entries = line_count * crtc->cursor->state->crtc_w * cpp;
b445e3b0
ED		 753 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
754 if (tlb_miss > 0)
755 entries += tlb_miss;
756 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
757 *cursor_wm = entries + cursor->guard_size;
758 if (*cursor_wm > (int)cursor->max_wm)
759 *cursor_wm = (int)cursor->max_wm;
760
761 return true;
762}
763
764/*
765 * Check the wm result.
766 *
767 * If any calculated watermark values is larger than the maximum value that
768 * can be programmed into the associated watermark register, that watermark
769 * must be disabled.
770 */
771static bool g4x_check_srwm(struct drm_device *dev,
772 int display_wm, int cursor_wm,
773 const struct intel_watermark_params *display,
774 const struct intel_watermark_params *cursor)
775{
776 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
777 display_wm, cursor_wm);
778
779 if (display_wm > display->max_wm) {
ae9400ca 780 DRM_DEBUG_KMS("display watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 781 display_wm, display->max_wm);
782 return false;
783 }
784
785 if (cursor_wm > cursor->max_wm) {
ae9400ca 786 DRM_DEBUG_KMS("cursor watermark is too large(%d/%u), disabling\n",
b445e3b0
ED		 787 cursor_wm, cursor->max_wm);
788 return false;
789 }
790
791 if (!(display_wm || cursor_wm)) {
792 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
793 return false;
794 }
795
796 return true;
797}
798
799static bool g4x_compute_srwm(struct drm_device *dev,
800 int plane,
801 int latency_ns,
802 const struct intel_watermark_params *display,
803 const struct intel_watermark_params *cursor,
804 int *display_wm, int *cursor_wm)
805{
806 struct drm_crtc *crtc;
4fe8590a 807 const struct drm_display_mode *adjusted_mode;
ac484963 808 int hdisplay, htotal, cpp, clock;
b445e3b0
ED		 809 unsigned long line_time_us;
810 int line_count, line_size;
811 int small, large;
812 int entries;
813
814 if (!latency_ns) {
815 *display_wm = *cursor_wm = 0;
816 return false;
817 }
818
819 crtc = intel_get_crtc_for_plane(dev, plane);
6e3c9717 820 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 821 clock = adjusted_mode->crtc_clock;
fec8cba3 822 htotal = adjusted_mode->crtc_htotal;
6e3c9717 823 hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 824 cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0 825
922044c9 826 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0 827 line_count = (latency_ns / line_time_us + 1000) / 1000;
ac484963 828 line_size = hdisplay * cpp;
b445e3b0
ED		 829
830 /* Use the minimum of the small and large buffer method for primary */
ac484963 831 small = ((clock * cpp / 1000) * latency_ns) / 1000;
b445e3b0
ED		 832 large = line_count * line_size;
833
834 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
835 *display_wm = entries + display->guard_size;
836
837 /* calculate the self-refresh watermark for display cursor */
ac484963 838 entries = line_count * cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 839 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
840 *cursor_wm = entries + cursor->guard_size;
841
842 return g4x_check_srwm(dev,
843 *display_wm, *cursor_wm,
844 display, cursor);
845}
846
15665979
VS		 847#define FW_WM_VLV(value, plane) \
848 (((value) << DSPFW_ ## plane ## _SHIFT) & DSPFW_ ## plane ## _MASK_VLV)
849
0018fda1
VS		 850static void vlv_write_wm_values(struct intel_crtc *crtc,
851 const struct vlv_wm_values *wm)
852{
853 struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
854 enum pipe pipe = crtc->pipe;
855
856 I915_WRITE(VLV_DDL(pipe),
857 (wm->ddl[pipe].cursor << DDL_CURSOR_SHIFT) |
858 (wm->ddl[pipe].sprite[1] << DDL_SPRITE_SHIFT(1)) |
859 (wm->ddl[pipe].sprite[0] << DDL_SPRITE_SHIFT(0)) |
860 (wm->ddl[pipe].primary << DDL_PLANE_SHIFT));
861
ae80152d 862 I915_WRITE(DSPFW1,
15665979
VS		 863 FW_WM(wm->sr.plane, SR) |
864 FW_WM(wm->pipe[PIPE_B].cursor, CURSORB) |
865 FW_WM_VLV(wm->pipe[PIPE_B].primary, PLANEB) |
866 FW_WM_VLV(wm->pipe[PIPE_A].primary, PLANEA));
ae80152d 867 I915_WRITE(DSPFW2,
15665979
VS		 868 FW_WM_VLV(wm->pipe[PIPE_A].sprite[1], SPRITEB) |
869 FW_WM(wm->pipe[PIPE_A].cursor, CURSORA) |
870 FW_WM_VLV(wm->pipe[PIPE_A].sprite[0], SPRITEA));
ae80152d 871 I915_WRITE(DSPFW3,
15665979 872 FW_WM(wm->sr.cursor, CURSOR_SR));
ae80152d
VS		 873
874 if (IS_CHERRYVIEW(dev_priv)) {
875 I915_WRITE(DSPFW7_CHV,
15665979
VS		 876 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
877 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 878 I915_WRITE(DSPFW8_CHV,
15665979
VS		 879 FW_WM_VLV(wm->pipe[PIPE_C].sprite[1], SPRITEF) |
880 FW_WM_VLV(wm->pipe[PIPE_C].sprite[0], SPRITEE));
ae80152d 881 I915_WRITE(DSPFW9_CHV,
15665979
VS		 882 FW_WM_VLV(wm->pipe[PIPE_C].primary, PLANEC) |
883 FW_WM(wm->pipe[PIPE_C].cursor, CURSORC));
ae80152d 884 I915_WRITE(DSPHOWM,
15665979
VS		 885 FW_WM(wm->sr.plane >> 9, SR_HI) |
886 FW_WM(wm->pipe[PIPE_C].sprite[1] >> 8, SPRITEF_HI) |
887 FW_WM(wm->pipe[PIPE_C].sprite[0] >> 8, SPRITEE_HI) |
888 FW_WM(wm->pipe[PIPE_C].primary >> 8, PLANEC_HI) |
889 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
890 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
891 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
892 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
893 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
894 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 895 } else {
896 I915_WRITE(DSPFW7,
15665979
VS		 897 FW_WM_VLV(wm->pipe[PIPE_B].sprite[1], SPRITED) |
898 FW_WM_VLV(wm->pipe[PIPE_B].sprite[0], SPRITEC));
ae80152d 899 I915_WRITE(DSPHOWM,
15665979
VS		 900 FW_WM(wm->sr.plane >> 9, SR_HI) |
901 FW_WM(wm->pipe[PIPE_B].sprite[1] >> 8, SPRITED_HI) |
902 FW_WM(wm->pipe[PIPE_B].sprite[0] >> 8, SPRITEC_HI) |
903 FW_WM(wm->pipe[PIPE_B].primary >> 8, PLANEB_HI) |
904 FW_WM(wm->pipe[PIPE_A].sprite[1] >> 8, SPRITEB_HI) |
905 FW_WM(wm->pipe[PIPE_A].sprite[0] >> 8, SPRITEA_HI) |
906 FW_WM(wm->pipe[PIPE_A].primary >> 8, PLANEA_HI));
ae80152d
VS		 907 }
908
2cb389b7
VS		 909 /* zero (unused) WM1 watermarks */
910 I915_WRITE(DSPFW4, 0);
911 I915_WRITE(DSPFW5, 0);
912 I915_WRITE(DSPFW6, 0);
913 I915_WRITE(DSPHOWM1, 0);
914
ae80152d 915 POSTING_READ(DSPFW1);
0018fda1
VS		 916}
917
15665979
VS		 918#undef FW_WM_VLV
919
6eb1a681
VS		 920enum vlv_wm_level {
921 VLV_WM_LEVEL_PM2,
922 VLV_WM_LEVEL_PM5,
923 VLV_WM_LEVEL_DDR_DVFS,
6eb1a681
VS		 924};
925
262cd2e1
VS		 926/* latency must be in 0.1us units. */
927static unsigned int vlv_wm_method2(unsigned int pixel_rate,
928 unsigned int pipe_htotal,
929 unsigned int horiz_pixels,
ac484963 930 unsigned int cpp,
262cd2e1
VS		 931 unsigned int latency)
932{
933 unsigned int ret;
934
935 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 936 ret = (ret + 1) * horiz_pixels * cpp;
262cd2e1
VS		 937 ret = DIV_ROUND_UP(ret, 64);
938
939 return ret;
940}
941
942static void vlv_setup_wm_latency(struct drm_device *dev)
943{
fac5e23e 944 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 945
946 /* all latencies in usec */
947 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM2] = 3;
948
58590c14
VS		 949 dev_priv->wm.max_level = VLV_WM_LEVEL_PM2;
950
262cd2e1
VS		 951 if (IS_CHERRYVIEW(dev_priv)) {
952 dev_priv->wm.pri_latency[VLV_WM_LEVEL_PM5] = 12;
953 dev_priv->wm.pri_latency[VLV_WM_LEVEL_DDR_DVFS] = 33;
58590c14
VS		 954
955 dev_priv->wm.max_level = VLV_WM_LEVEL_DDR_DVFS;
262cd2e1
VS		 956 }
957}
958
959static uint16_t vlv_compute_wm_level(struct intel_plane *plane,
960 struct intel_crtc *crtc,
961 const struct intel_plane_state *state,
962 int level)
963{
964 struct drm_i915_private *dev_priv = to_i915(plane->base.dev);
ac484963 965 int clock, htotal, cpp, width, wm;
262cd2e1
VS		 966
967 if (dev_priv->wm.pri_latency[level] == 0)
968 return USHRT_MAX;
969
936e71e3 970 if (!state->base.visible)
262cd2e1
VS		 971 return 0;
972
ac484963 973 cpp = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
262cd2e1
VS		 974 clock = crtc->config->base.adjusted_mode.crtc_clock;
975 htotal = crtc->config->base.adjusted_mode.crtc_htotal;
976 width = crtc->config->pipe_src_w;
977 if (WARN_ON(htotal == 0))
978 htotal = 1;
979
980 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
981 /*
982 * FIXME the formula gives values that are
983 * too big for the cursor FIFO, and hence we
984 * would never be able to use cursors. For
985 * now just hardcode the watermark.
986 */
987 wm = 63;
988 } else {
ac484963 989 wm = vlv_wm_method2(clock, htotal, width, cpp,
262cd2e1
VS		 990 dev_priv->wm.pri_latency[level] * 10);
991 }
992
993 return min_t(int, wm, USHRT_MAX);
994}
995
54f1b6e1
VS		 996static void vlv_compute_fifo(struct intel_crtc *crtc)
997{
998 struct drm_device *dev = crtc->base.dev;
999 struct vlv_wm_state *wm_state = &crtc->wm_state;
1000 struct intel_plane *plane;
1001 unsigned int total_rate = 0;
1002 const int fifo_size = 512 - 1;
1003 int fifo_extra, fifo_left = fifo_size;
1004
1005 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1006 struct intel_plane_state *state =
1007 to_intel_plane_state(plane->base.state);
1008
1009 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1010 continue;
1011
936e71e3 1012 if (state->base.visible) {
54f1b6e1
VS		 1013 wm_state->num_active_planes++;
1014 total_rate += drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1015 }
1016 }
1017
1018 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1019 struct intel_plane_state *state =
1020 to_intel_plane_state(plane->base.state);
1021 unsigned int rate;
1022
1023 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1024 plane->wm.fifo_size = 63;
1025 continue;
1026 }
1027
936e71e3 1028 if (!state->base.visible) {
54f1b6e1
VS		 1029 plane->wm.fifo_size = 0;
1030 continue;
1031 }
1032
1033 rate = drm_format_plane_cpp(state->base.fb->pixel_format, 0);
1034 plane->wm.fifo_size = fifo_size * rate / total_rate;
1035 fifo_left -= plane->wm.fifo_size;
1036 }
1037
1038 fifo_extra = DIV_ROUND_UP(fifo_left, wm_state->num_active_planes ?: 1);
1039
1040 /* spread the remainder evenly */
1041 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1042 int plane_extra;
1043
1044 if (fifo_left == 0)
1045 break;
1046
1047 if (plane->base.type == DRM_PLANE_TYPE_CURSOR)
1048 continue;
1049
1050 /* give it all to the first plane if none are active */
1051 if (plane->wm.fifo_size == 0 &&
1052 wm_state->num_active_planes)
1053 continue;
1054
1055 plane_extra = min(fifo_extra, fifo_left);
1056 plane->wm.fifo_size += plane_extra;
1057 fifo_left -= plane_extra;
1058 }
1059
1060 WARN_ON(fifo_left != 0);
1061}
1062
262cd2e1
VS		 1063static void vlv_invert_wms(struct intel_crtc *crtc)
1064{
1065 struct vlv_wm_state *wm_state = &crtc->wm_state;
1066 int level;
1067
1068 for (level = 0; level < wm_state->num_levels; level++) {
1069 struct drm_device *dev = crtc->base.dev;
1070 const int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1071 struct intel_plane *plane;
1072
1073 wm_state->sr[level].plane = sr_fifo_size - wm_state->sr[level].plane;
1074 wm_state->sr[level].cursor = 63 - wm_state->sr[level].cursor;
1075
1076 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1077 switch (plane->base.type) {
1078 int sprite;
1079 case DRM_PLANE_TYPE_CURSOR:
1080 wm_state->wm[level].cursor = plane->wm.fifo_size -
1081 wm_state->wm[level].cursor;
1082 break;
1083 case DRM_PLANE_TYPE_PRIMARY:
1084 wm_state->wm[level].primary = plane->wm.fifo_size -
1085 wm_state->wm[level].primary;
1086 break;
1087 case DRM_PLANE_TYPE_OVERLAY:
1088 sprite = plane->plane;
1089 wm_state->wm[level].sprite[sprite] = plane->wm.fifo_size -
1090 wm_state->wm[level].sprite[sprite];
1091 break;
1092 }
1093 }
1094 }
1095}
1096
26e1fe4f 1097static void vlv_compute_wm(struct intel_crtc *crtc)
262cd2e1
VS		 1098{
1099 struct drm_device *dev = crtc->base.dev;
1100 struct vlv_wm_state *wm_state = &crtc->wm_state;
1101 struct intel_plane *plane;
1102 int sr_fifo_size = INTEL_INFO(dev)->num_pipes * 512 - 1;
1103 int level;
1104
1105 memset(wm_state, 0, sizeof(*wm_state));
1106
852eb00d 1107 wm_state->cxsr = crtc->pipe != PIPE_C && crtc->wm.cxsr_allowed;
58590c14 1108 wm_state->num_levels = to_i915(dev)->wm.max_level + 1;
262cd2e1
VS		 1109
1110 wm_state->num_active_planes = 0;
262cd2e1 1111
54f1b6e1 1112 vlv_compute_fifo(crtc);
262cd2e1
VS		 1113
1114 if (wm_state->num_active_planes != 1)
1115 wm_state->cxsr = false;
1116
1117 if (wm_state->cxsr) {
1118 for (level = 0; level < wm_state->num_levels; level++) {
1119 wm_state->sr[level].plane = sr_fifo_size;
1120 wm_state->sr[level].cursor = 63;
1121 }
1122 }
1123
1124 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1125 struct intel_plane_state *state =
1126 to_intel_plane_state(plane->base.state);
1127
936e71e3 1128 if (!state->base.visible)
262cd2e1
VS		 1129 continue;
1130
1131 /* normal watermarks */
1132 for (level = 0; level < wm_state->num_levels; level++) {
1133 int wm = vlv_compute_wm_level(plane, crtc, state, level);
1134 int max_wm = plane->base.type == DRM_PLANE_TYPE_CURSOR ? 63 : 511;
1135
1136 /* hack */
1137 if (WARN_ON(level == 0 && wm > max_wm))
1138 wm = max_wm;
1139
1140 if (wm > plane->wm.fifo_size)
1141 break;
1142
1143 switch (plane->base.type) {
1144 int sprite;
1145 case DRM_PLANE_TYPE_CURSOR:
1146 wm_state->wm[level].cursor = wm;
1147 break;
1148 case DRM_PLANE_TYPE_PRIMARY:
1149 wm_state->wm[level].primary = wm;
1150 break;
1151 case DRM_PLANE_TYPE_OVERLAY:
1152 sprite = plane->plane;
1153 wm_state->wm[level].sprite[sprite] = wm;
1154 break;
1155 }
1156 }
1157
1158 wm_state->num_levels = level;
1159
1160 if (!wm_state->cxsr)
1161 continue;
1162
1163 /* maxfifo watermarks */
1164 switch (plane->base.type) {
1165 int sprite, level;
1166 case DRM_PLANE_TYPE_CURSOR:
1167 for (level = 0; level < wm_state->num_levels; level++)
1168 wm_state->sr[level].cursor =
5a37ed0a 1169 wm_state->wm[level].cursor;
262cd2e1
VS		 1170 break;
1171 case DRM_PLANE_TYPE_PRIMARY:
1172 for (level = 0; level < wm_state->num_levels; level++)
1173 wm_state->sr[level].plane =
1174 min(wm_state->sr[level].plane,
1175 wm_state->wm[level].primary);
1176 break;
1177 case DRM_PLANE_TYPE_OVERLAY:
1178 sprite = plane->plane;
1179 for (level = 0; level < wm_state->num_levels; level++)
1180 wm_state->sr[level].plane =
1181 min(wm_state->sr[level].plane,
1182 wm_state->wm[level].sprite[sprite]);
1183 break;
1184 }
1185 }
1186
1187 /* clear any (partially) filled invalid levels */
58590c14 1188 for (level = wm_state->num_levels; level < to_i915(dev)->wm.max_level + 1; level++) {
262cd2e1
VS		 1189 memset(&wm_state->wm[level], 0, sizeof(wm_state->wm[level]));
1190 memset(&wm_state->sr[level], 0, sizeof(wm_state->sr[level]));
1191 }
1192
1193 vlv_invert_wms(crtc);
1194}
1195
54f1b6e1
VS		 1196#define VLV_FIFO(plane, value) \
1197 (((value) << DSPARB_ ## plane ## _SHIFT_VLV) & DSPARB_ ## plane ## _MASK_VLV)
1198
1199static void vlv_pipe_set_fifo_size(struct intel_crtc *crtc)
1200{
1201 struct drm_device *dev = crtc->base.dev;
1202 struct drm_i915_private *dev_priv = to_i915(dev);
1203 struct intel_plane *plane;
1204 int sprite0_start = 0, sprite1_start = 0, fifo_size = 0;
1205
1206 for_each_intel_plane_on_crtc(dev, crtc, plane) {
1207 if (plane->base.type == DRM_PLANE_TYPE_CURSOR) {
1208 WARN_ON(plane->wm.fifo_size != 63);
1209 continue;
1210 }
1211
1212 if (plane->base.type == DRM_PLANE_TYPE_PRIMARY)
1213 sprite0_start = plane->wm.fifo_size;
1214 else if (plane->plane == 0)
1215 sprite1_start = sprite0_start + plane->wm.fifo_size;
1216 else
1217 fifo_size = sprite1_start + plane->wm.fifo_size;
1218 }
1219
1220 WARN_ON(fifo_size != 512 - 1);
1221
1222 DRM_DEBUG_KMS("Pipe %c FIFO split %d / %d / %d\n",
1223 pipe_name(crtc->pipe), sprite0_start,
1224 sprite1_start, fifo_size);
1225
1226 switch (crtc->pipe) {
1227 uint32_t dsparb, dsparb2, dsparb3;
1228 case PIPE_A:
1229 dsparb = I915_READ(DSPARB);
1230 dsparb2 = I915_READ(DSPARB2);
1231
1232 dsparb &= ~(VLV_FIFO(SPRITEA, 0xff) |
1233 VLV_FIFO(SPRITEB, 0xff));
1234 dsparb |= (VLV_FIFO(SPRITEA, sprite0_start) |
1235 VLV_FIFO(SPRITEB, sprite1_start));
1236
1237 dsparb2 &= ~(VLV_FIFO(SPRITEA_HI, 0x1) |
1238 VLV_FIFO(SPRITEB_HI, 0x1));
1239 dsparb2 |= (VLV_FIFO(SPRITEA_HI, sprite0_start >> 8) |
1240 VLV_FIFO(SPRITEB_HI, sprite1_start >> 8));
1241
1242 I915_WRITE(DSPARB, dsparb);
1243 I915_WRITE(DSPARB2, dsparb2);
1244 break;
1245 case PIPE_B:
1246 dsparb = I915_READ(DSPARB);
1247 dsparb2 = I915_READ(DSPARB2);
1248
1249 dsparb &= ~(VLV_FIFO(SPRITEC, 0xff) |
1250 VLV_FIFO(SPRITED, 0xff));
1251 dsparb |= (VLV_FIFO(SPRITEC, sprite0_start) |
1252 VLV_FIFO(SPRITED, sprite1_start));
1253
1254 dsparb2 &= ~(VLV_FIFO(SPRITEC_HI, 0xff) |
1255 VLV_FIFO(SPRITED_HI, 0xff));
1256 dsparb2 |= (VLV_FIFO(SPRITEC_HI, sprite0_start >> 8) |
1257 VLV_FIFO(SPRITED_HI, sprite1_start >> 8));
1258
1259 I915_WRITE(DSPARB, dsparb);
1260 I915_WRITE(DSPARB2, dsparb2);
1261 break;
1262 case PIPE_C:
1263 dsparb3 = I915_READ(DSPARB3);
1264 dsparb2 = I915_READ(DSPARB2);
1265
1266 dsparb3 &= ~(VLV_FIFO(SPRITEE, 0xff) |
1267 VLV_FIFO(SPRITEF, 0xff));
1268 dsparb3 |= (VLV_FIFO(SPRITEE, sprite0_start) |
1269 VLV_FIFO(SPRITEF, sprite1_start));
1270
1271 dsparb2 &= ~(VLV_FIFO(SPRITEE_HI, 0xff) |
1272 VLV_FIFO(SPRITEF_HI, 0xff));
1273 dsparb2 |= (VLV_FIFO(SPRITEE_HI, sprite0_start >> 8) |
1274 VLV_FIFO(SPRITEF_HI, sprite1_start >> 8));
1275
1276 I915_WRITE(DSPARB3, dsparb3);
1277 I915_WRITE(DSPARB2, dsparb2);
1278 break;
1279 default:
1280 break;
1281 }
1282}
1283
1284#undef VLV_FIFO
1285
262cd2e1
VS		 1286static void vlv_merge_wm(struct drm_device *dev,
1287 struct vlv_wm_values *wm)
1288{
1289 struct intel_crtc *crtc;
1290 int num_active_crtcs = 0;
1291
58590c14 1292 wm->level = to_i915(dev)->wm.max_level;
262cd2e1
VS		 1293 wm->cxsr = true;
1294
1295 for_each_intel_crtc(dev, crtc) {
1296 const struct vlv_wm_state *wm_state = &crtc->wm_state;
1297
1298 if (!crtc->active)
1299 continue;
1300
1301 if (!wm_state->cxsr)
1302 wm->cxsr = false;
1303
1304 num_active_crtcs++;
1305 wm->level = min_t(int, wm->level, wm_state->num_levels - 1);
1306 }
1307
1308 if (num_active_crtcs != 1)
1309 wm->cxsr = false;
1310
6f9c784b
VS		 1311 if (num_active_crtcs > 1)
1312 wm->level = VLV_WM_LEVEL_PM2;
1313
262cd2e1
VS		 1314 for_each_intel_crtc(dev, crtc) {
1315 struct vlv_wm_state *wm_state = &crtc->wm_state;
1316 enum pipe pipe = crtc->pipe;
1317
1318 if (!crtc->active)
1319 continue;
1320
1321 wm->pipe[pipe] = wm_state->wm[wm->level];
1322 if (wm->cxsr)
1323 wm->sr = wm_state->sr[wm->level];
1324
1325 wm->ddl[pipe].primary = DDL_PRECISION_HIGH | 2;
1326 wm->ddl[pipe].sprite[0] = DDL_PRECISION_HIGH | 2;
1327 wm->ddl[pipe].sprite[1] = DDL_PRECISION_HIGH | 2;
1328 wm->ddl[pipe].cursor = DDL_PRECISION_HIGH | 2;
1329 }
1330}
1331
1332static void vlv_update_wm(struct drm_crtc *crtc)
1333{
1334 struct drm_device *dev = crtc->dev;
fac5e23e 1335 struct drm_i915_private *dev_priv = to_i915(dev);
262cd2e1
VS		 1336 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
1337 enum pipe pipe = intel_crtc->pipe;
1338 struct vlv_wm_values wm = {};
1339
26e1fe4f 1340 vlv_compute_wm(intel_crtc);
262cd2e1
VS		 1341 vlv_merge_wm(dev, &wm);
1342
54f1b6e1
VS		 1343 if (memcmp(&dev_priv->wm.vlv, &wm, sizeof(wm)) == 0) {
1344 /* FIXME should be part of crtc atomic commit */
1345 vlv_pipe_set_fifo_size(intel_crtc);
262cd2e1 1346 return;
54f1b6e1 1347 }
262cd2e1
VS		 1348
1349 if (wm.level < VLV_WM_LEVEL_DDR_DVFS &&
1350 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_DDR_DVFS)
1351 chv_set_memory_dvfs(dev_priv, false);
1352
1353 if (wm.level < VLV_WM_LEVEL_PM5 &&
1354 dev_priv->wm.vlv.level >= VLV_WM_LEVEL_PM5)
1355 chv_set_memory_pm5(dev_priv, false);
1356
852eb00d 1357 if (!wm.cxsr && dev_priv->wm.vlv.cxsr)
262cd2e1 1358 intel_set_memory_cxsr(dev_priv, false);
262cd2e1 1359
54f1b6e1
VS		 1360 /* FIXME should be part of crtc atomic commit */
1361 vlv_pipe_set_fifo_size(intel_crtc);
1362
262cd2e1
VS		 1363 vlv_write_wm_values(intel_crtc, &wm);
1364
1365 DRM_DEBUG_KMS("Setting FIFO watermarks - %c: plane=%d, cursor=%d, "
1366 "sprite0=%d, sprite1=%d, SR: plane=%d, cursor=%d level=%d cxsr=%d\n",
1367 pipe_name(pipe), wm.pipe[pipe].primary, wm.pipe[pipe].cursor,
1368 wm.pipe[pipe].sprite[0], wm.pipe[pipe].sprite[1],
1369 wm.sr.plane, wm.sr.cursor, wm.level, wm.cxsr);
1370
852eb00d 1371 if (wm.cxsr && !dev_priv->wm.vlv.cxsr)
262cd2e1 1372 intel_set_memory_cxsr(dev_priv, true);
262cd2e1
VS		 1373
1374 if (wm.level >= VLV_WM_LEVEL_PM5 &&
1375 dev_priv->wm.vlv.level < VLV_WM_LEVEL_PM5)
1376 chv_set_memory_pm5(dev_priv, true);
1377
1378 if (wm.level >= VLV_WM_LEVEL_DDR_DVFS &&
1379 dev_priv->wm.vlv.level < VLV_WM_LEVEL_DDR_DVFS)
1380 chv_set_memory_dvfs(dev_priv, true);
1381
1382 dev_priv->wm.vlv = wm;
3c2777fd
VS		 1383}
1384
ae80152d
VS		 1385#define single_plane_enabled(mask) is_power_of_2(mask)
1386
46ba614c 1387static void g4x_update_wm(struct drm_crtc *crtc)
b445e3b0 1388{
46ba614c 1389 struct drm_device *dev = crtc->dev;
b445e3b0 1390 static const int sr_latency_ns = 12000;
fac5e23e 1391 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1392 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1393 int plane_sr, cursor_sr;
1394 unsigned int enabled = 0;
9858425c 1395 bool cxsr_enabled;
b445e3b0 1396
51cea1f4 1397 if (g4x_compute_wm0(dev, PIPE_A,
5aef6003
CW		 1398 &g4x_wm_info, pessimal_latency_ns,
1399 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1400 &planea_wm, &cursora_wm))
51cea1f4 1401 enabled |= 1 << PIPE_A;
b445e3b0 1402
51cea1f4 1403 if (g4x_compute_wm0(dev, PIPE_B,
5aef6003
CW		 1404 &g4x_wm_info, pessimal_latency_ns,
1405 &g4x_cursor_wm_info, pessimal_latency_ns,
b445e3b0 1406 &planeb_wm, &cursorb_wm))
51cea1f4 1407 enabled |= 1 << PIPE_B;
b445e3b0 1408
b445e3b0
ED		 1409 if (single_plane_enabled(enabled) &&
1410 g4x_compute_srwm(dev, ffs(enabled) - 1,
1411 sr_latency_ns,
1412 &g4x_wm_info,
1413 &g4x_cursor_wm_info,
52bd02d8 1414 &plane_sr, &cursor_sr)) {
9858425c 1415 cxsr_enabled = true;
52bd02d8 1416 } else {
9858425c 1417 cxsr_enabled = false;
5209b1f4 1418 intel_set_memory_cxsr(dev_priv, false);
52bd02d8
CW		 1419 plane_sr = cursor_sr = 0;
1420 }
b445e3b0 1421
a5043453
VS		 1422 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, "
1423 "B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
b445e3b0
ED		 1424 planea_wm, cursora_wm,
1425 planeb_wm, cursorb_wm,
1426 plane_sr, cursor_sr);
1427
1428 I915_WRITE(DSPFW1,
f4998963
VS		 1429 FW_WM(plane_sr, SR) |
1430 FW_WM(cursorb_wm, CURSORB) |
1431 FW_WM(planeb_wm, PLANEB) |
1432 FW_WM(planea_wm, PLANEA));
b445e3b0 1433 I915_WRITE(DSPFW2,
8c919b28 1434 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
f4998963 1435 FW_WM(cursora_wm, CURSORA));
b445e3b0
ED		 1436 /* HPLL off in SR has some issues on G4x... disable it */
1437 I915_WRITE(DSPFW3,
8c919b28 1438 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
f4998963 1439 FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1440
1441 if (cxsr_enabled)
1442 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1443}
1444
46ba614c 1445static void i965_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1446{
46ba614c 1447 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1448 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1449 struct drm_crtc *crtc;
1450 int srwm = 1;
1451 int cursor_sr = 16;
9858425c 1452 bool cxsr_enabled;
b445e3b0
ED		 1453
1454 /* Calc sr entries for one plane configs */
1455 crtc = single_enabled_crtc(dev);
1456 if (crtc) {
1457 /* self-refresh has much higher latency */
1458 static const int sr_latency_ns = 12000;
124abe07 1459 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1460 int clock = adjusted_mode->crtc_clock;
fec8cba3 1461 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1462 int hdisplay = to_intel_crtc(crtc)->config->pipe_src_w;
ac484963 1463 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1464 unsigned long line_time_us;
1465 int entries;
1466
922044c9 1467 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1468
1469 /* Use ns/us then divide to preserve precision */
1470 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1471 cpp * hdisplay;
b445e3b0
ED		 1472 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1473 srwm = I965_FIFO_SIZE - entries;
1474 if (srwm < 0)
1475 srwm = 1;
1476 srwm &= 0x1ff;
1477 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1478 entries, srwm);
1479
1480 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1481 cpp * crtc->cursor->state->crtc_w;
b445e3b0
ED		 1482 entries = DIV_ROUND_UP(entries,
1483 i965_cursor_wm_info.cacheline_size);
1484 cursor_sr = i965_cursor_wm_info.fifo_size -
1485 (entries + i965_cursor_wm_info.guard_size);
1486
1487 if (cursor_sr > i965_cursor_wm_info.max_wm)
1488 cursor_sr = i965_cursor_wm_info.max_wm;
1489
1490 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1491 "cursor %d\n", srwm, cursor_sr);
1492
9858425c 1493 cxsr_enabled = true;
b445e3b0 1494 } else {
9858425c 1495 cxsr_enabled = false;
b445e3b0 1496 /* Turn off self refresh if both pipes are enabled */
5209b1f4 1497 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1498 }
1499
1500 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1501 srwm);
1502
1503 /* 965 has limitations... */
f4998963
VS		 1504 I915_WRITE(DSPFW1, FW_WM(srwm, SR) |
1505 FW_WM(8, CURSORB) |
1506 FW_WM(8, PLANEB) |
1507 FW_WM(8, PLANEA));
1508 I915_WRITE(DSPFW2, FW_WM(8, CURSORA) |
1509 FW_WM(8, PLANEC_OLD));
b445e3b0 1510 /* update cursor SR watermark */
f4998963 1511 I915_WRITE(DSPFW3, FW_WM(cursor_sr, CURSOR_SR));
9858425c
ID		 1512
1513 if (cxsr_enabled)
1514 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1515}
1516
f4998963
VS		 1517#undef FW_WM
1518
46ba614c 1519static void i9xx_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1520{
46ba614c 1521 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1522 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0
ED		 1523 const struct intel_watermark_params *wm_info;
1524 uint32_t fwater_lo;
1525 uint32_t fwater_hi;
1526 int cwm, srwm = 1;
1527 int fifo_size;
1528 int planea_wm, planeb_wm;
1529 struct drm_crtc *crtc, *enabled = NULL;
1530
1531 if (IS_I945GM(dev))
1532 wm_info = &i945_wm_info;
1533 else if (!IS_GEN2(dev))
1534 wm_info = &i915_wm_info;
1535 else
9d539105 1536 wm_info = &i830_a_wm_info;
b445e3b0
ED		 1537
1538 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1539 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1540 if (intel_crtc_active(crtc)) {
241bfc38 1541 const struct drm_display_mode *adjusted_mode;
ac484963 1542 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1543 if (IS_GEN2(dev))
1544 cpp = 4;
1545
6e3c9717 1546 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1547 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1548 wm_info, fifo_size, cpp,
5aef6003 1549 pessimal_latency_ns);
b445e3b0 1550 enabled = crtc;
9d539105 1551 } else {
b445e3b0 1552 planea_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1553 if (planea_wm > (long)wm_info->max_wm)
1554 planea_wm = wm_info->max_wm;
1555 }
1556
1557 if (IS_GEN2(dev))
1558 wm_info = &i830_bc_wm_info;
b445e3b0
ED		 1559
1560 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1561 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1562 if (intel_crtc_active(crtc)) {
241bfc38 1563 const struct drm_display_mode *adjusted_mode;
ac484963 1564 int cpp = drm_format_plane_cpp(crtc->primary->state->fb->pixel_format, 0);
b9e0bda3
CW		 1565 if (IS_GEN2(dev))
1566 cpp = 4;
1567
6e3c9717 1568 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1569 planeb_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
b9e0bda3 1570 wm_info, fifo_size, cpp,
5aef6003 1571 pessimal_latency_ns);
b445e3b0
ED		 1572 if (enabled == NULL)
1573 enabled = crtc;
1574 else
1575 enabled = NULL;
9d539105 1576 } else {
b445e3b0 1577 planeb_wm = fifo_size - wm_info->guard_size;
9d539105
VS		 1578 if (planeb_wm > (long)wm_info->max_wm)
1579 planeb_wm = wm_info->max_wm;
1580 }
b445e3b0
ED		 1581
1582 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1583
50a0bc90 1584 if (IS_I915GM(dev_priv) && enabled) {
2ff8fde1 1585 struct drm_i915_gem_object *obj;
2ab1bc9d 1586
59bea882 1587 obj = intel_fb_obj(enabled->primary->state->fb);
2ab1bc9d
DV		 1588
1589 /* self-refresh seems busted with untiled */
3e510a8e 1590 if (!i915_gem_object_is_tiled(obj))
2ab1bc9d
DV		 1591 enabled = NULL;
1592 }
1593
b445e3b0
ED		 1594 /*
1595 * Overlay gets an aggressive default since video jitter is bad.
1596 */
1597 cwm = 2;
1598
1599 /* Play safe and disable self-refresh before adjusting watermarks. */
5209b1f4 1600 intel_set_memory_cxsr(dev_priv, false);
b445e3b0
ED		 1601
1602 /* Calc sr entries for one plane configs */
1603 if (HAS_FW_BLC(dev) && enabled) {
1604 /* self-refresh has much higher latency */
1605 static const int sr_latency_ns = 6000;
124abe07 1606 const struct drm_display_mode *adjusted_mode = &to_intel_crtc(enabled)->config->base.adjusted_mode;
241bfc38 1607 int clock = adjusted_mode->crtc_clock;
fec8cba3 1608 int htotal = adjusted_mode->crtc_htotal;
6e3c9717 1609 int hdisplay = to_intel_crtc(enabled)->config->pipe_src_w;
ac484963 1610 int cpp = drm_format_plane_cpp(enabled->primary->state->fb->pixel_format, 0);
b445e3b0
ED		 1611 unsigned long line_time_us;
1612 int entries;
1613
50a0bc90 1614 if (IS_I915GM(dev_priv) || IS_I945GM(dev_priv))
2d1b5056
VS		 1615 cpp = 4;
1616
922044c9 1617 line_time_us = max(htotal * 1000 / clock, 1);
b445e3b0
ED		 1618
1619 /* Use ns/us then divide to preserve precision */
1620 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
ac484963 1621 cpp * hdisplay;
b445e3b0
ED		 1622 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1623 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1624 srwm = wm_info->fifo_size - entries;
1625 if (srwm < 0)
1626 srwm = 1;
1627
50a0bc90 1628 if (IS_I945G(dev_priv) || IS_I945GM(dev_priv))
b445e3b0
ED		 1629 I915_WRITE(FW_BLC_SELF,
1630 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
acb91359 1631 else
b445e3b0
ED		 1632 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1633 }
1634
1635 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1636 planea_wm, planeb_wm, cwm, srwm);
1637
1638 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1639 fwater_hi = (cwm & 0x1f);
1640
1641 /* Set request length to 8 cachelines per fetch */
1642 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1643 fwater_hi = fwater_hi | (1 << 8);
1644
1645 I915_WRITE(FW_BLC, fwater_lo);
1646 I915_WRITE(FW_BLC2, fwater_hi);
1647
5209b1f4
ID		 1648 if (enabled)
1649 intel_set_memory_cxsr(dev_priv, true);
b445e3b0
ED		 1650}
1651
feb56b93 1652static void i845_update_wm(struct drm_crtc *unused_crtc)
b445e3b0 1653{
46ba614c 1654 struct drm_device *dev = unused_crtc->dev;
fac5e23e 1655 struct drm_i915_private *dev_priv = to_i915(dev);
b445e3b0 1656 struct drm_crtc *crtc;
241bfc38 1657 const struct drm_display_mode *adjusted_mode;
b445e3b0
ED		 1658 uint32_t fwater_lo;
1659 int planea_wm;
1660
1661 crtc = single_enabled_crtc(dev);
1662 if (crtc == NULL)
1663 return;
1664
6e3c9717 1665 adjusted_mode = &to_intel_crtc(crtc)->config->base.adjusted_mode;
241bfc38 1666 planea_wm = intel_calculate_wm(adjusted_mode->crtc_clock,
feb56b93 1667 &i845_wm_info,
b445e3b0 1668 dev_priv->display.get_fifo_size(dev, 0),
5aef6003 1669 4, pessimal_latency_ns);
b445e3b0
ED		 1670 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1671 fwater_lo |= (3<<8) | planea_wm;
1672
1673 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1674
1675 I915_WRITE(FW_BLC, fwater_lo);
1676}
1677
8cfb3407 1678uint32_t ilk_pipe_pixel_rate(const struct intel_crtc_state *pipe_config)
801bcfff 1679{
fd4daa9c 1680 uint32_t pixel_rate;
801bcfff 1681
8cfb3407 1682 pixel_rate = pipe_config->base.adjusted_mode.crtc_clock;
801bcfff
PZ		 1683
1684 /* We only use IF-ID interlacing. If we ever use PF-ID we'll need to
1685 * adjust the pixel_rate here. */
1686
8cfb3407 1687 if (pipe_config->pch_pfit.enabled) {
801bcfff 1688 uint64_t pipe_w, pipe_h, pfit_w, pfit_h;
8cfb3407
VS		 1689 uint32_t pfit_size = pipe_config->pch_pfit.size;
1690
1691 pipe_w = pipe_config->pipe_src_w;
1692 pipe_h = pipe_config->pipe_src_h;
801bcfff 1693
801bcfff
PZ		 1694 pfit_w = (pfit_size >> 16) & 0xFFFF;
1695 pfit_h = pfit_size & 0xFFFF;
1696 if (pipe_w < pfit_w)
1697 pipe_w = pfit_w;
1698 if (pipe_h < pfit_h)
1699 pipe_h = pfit_h;
1700
15126882
MR		 1701 if (WARN_ON(!pfit_w || !pfit_h))
1702 return pixel_rate;
1703
801bcfff
PZ		 1704 pixel_rate = div_u64((uint64_t) pixel_rate * pipe_w * pipe_h,
1705 pfit_w * pfit_h);
1706 }
1707
1708 return pixel_rate;
1709}
1710
37126462 1711/* latency must be in 0.1us units. */
ac484963 1712static uint32_t ilk_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
801bcfff
PZ		 1713{
1714 uint64_t ret;
1715
3312ba65
VS		 1716 if (WARN(latency == 0, "Latency value missing\n"))
1717 return UINT_MAX;
1718
ac484963 1719 ret = (uint64_t) pixel_rate * cpp * latency;
801bcfff
PZ		 1720 ret = DIV_ROUND_UP_ULL(ret, 64 * 10000) + 2;
1721
1722 return ret;
1723}
1724
37126462 1725/* latency must be in 0.1us units. */
23297044 1726static uint32_t ilk_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
ac484963 1727 uint32_t horiz_pixels, uint8_t cpp,
801bcfff
PZ		 1728 uint32_t latency)
1729{
1730 uint32_t ret;
1731
3312ba65
VS		 1732 if (WARN(latency == 0, "Latency value missing\n"))
1733 return UINT_MAX;
15126882
MR		 1734 if (WARN_ON(!pipe_htotal))
1735 return UINT_MAX;
3312ba65 1736
801bcfff 1737 ret = (latency * pixel_rate) / (pipe_htotal * 10000);
ac484963 1738 ret = (ret + 1) * horiz_pixels * cpp;
801bcfff
PZ		 1739 ret = DIV_ROUND_UP(ret, 64) + 2;
1740 return ret;
1741}
1742
23297044 1743static uint32_t ilk_wm_fbc(uint32_t pri_val, uint32_t horiz_pixels,
ac484963 1744 uint8_t cpp)
cca32e9a 1745{
15126882
MR		 1746 /*
1747 * Neither of these should be possible since this function shouldn't be
1748 * called if the CRTC is off or the plane is invisible. But let's be
1749 * extra paranoid to avoid a potential divide-by-zero if we screw up
1750 * elsewhere in the driver.
1751 */
ac484963 1752 if (WARN_ON(!cpp))
15126882
MR		 1753 return 0;
1754 if (WARN_ON(!horiz_pixels))
1755 return 0;
1756
ac484963 1757 return DIV_ROUND_UP(pri_val * 64, horiz_pixels * cpp) + 2;
cca32e9a
PZ		 1758}
1759
820c1980 1760struct ilk_wm_maximums {
cca32e9a
PZ		 1761 uint16_t pri;
1762 uint16_t spr;
1763 uint16_t cur;
1764 uint16_t fbc;
1765};
1766
37126462
VS		 1767/*
1768 * For both WM_PIPE and WM_LP.
1769 * mem_value must be in 0.1us units.
1770 */
7221fc33 1771static uint32_t ilk_compute_pri_wm(const struct intel_crtc_state *cstate,
43d59eda 1772 const struct intel_plane_state *pstate,
cca32e9a
PZ		 1773 uint32_t mem_value,
1774 bool is_lp)
801bcfff 1775{
ac484963
VS		 1776 int cpp = pstate->base.fb ?
1777 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
cca32e9a
PZ		 1778 uint32_t method1, method2;
1779
936e71e3 1780 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1781 return 0;
1782
ac484963 1783 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
cca32e9a
PZ		 1784
1785 if (!is_lp)
1786 return method1;
1787
7221fc33
MR		 1788 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1789 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1790 drm_rect_width(&pstate->base.dst),
ac484963 1791 cpp, mem_value);
cca32e9a
PZ		 1792
1793 return min(method1, method2);
801bcfff
PZ		 1794}
1795
37126462
VS		 1796/*
1797 * For both WM_PIPE and WM_LP.
1798 * mem_value must be in 0.1us units.
1799 */
7221fc33 1800static uint32_t ilk_compute_spr_wm(const struct intel_crtc_state *cstate,
43d59eda 1801 const struct intel_plane_state *pstate,
801bcfff
PZ		 1802 uint32_t mem_value)
1803{
ac484963
VS		 1804 int cpp = pstate->base.fb ?
1805 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
801bcfff
PZ		 1806 uint32_t method1, method2;
1807
936e71e3 1808 if (!cstate->base.active || !pstate->base.visible)
801bcfff
PZ		 1809 return 0;
1810
ac484963 1811 method1 = ilk_wm_method1(ilk_pipe_pixel_rate(cstate), cpp, mem_value);
7221fc33
MR		 1812 method2 = ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1813 cstate->base.adjusted_mode.crtc_htotal,
936e71e3 1814 drm_rect_width(&pstate->base.dst),
ac484963 1815 cpp, mem_value);
801bcfff
PZ		 1816 return min(method1, method2);
1817}
1818
37126462
VS		 1819/*
1820 * For both WM_PIPE and WM_LP.
1821 * mem_value must be in 0.1us units.
1822 */
7221fc33 1823static uint32_t ilk_compute_cur_wm(const struct intel_crtc_state *cstate,
43d59eda 1824 const struct intel_plane_state *pstate,
801bcfff
PZ		 1825 uint32_t mem_value)
1826{
b2435692
MR		 1827 /*
1828 * We treat the cursor plane as always-on for the purposes of watermark
1829 * calculation. Until we have two-stage watermark programming merged,
1830 * this is necessary to avoid flickering.
1831 */
1832 int cpp = 4;
936e71e3 1833 int width = pstate->base.visible ? pstate->base.crtc_w : 64;
43d59eda 1834
b2435692 1835 if (!cstate->base.active)
801bcfff
PZ		 1836 return 0;
1837
7221fc33
MR		 1838 return ilk_wm_method2(ilk_pipe_pixel_rate(cstate),
1839 cstate->base.adjusted_mode.crtc_htotal,
b2435692 1840 width, cpp, mem_value);
801bcfff
PZ		 1841}
1842
cca32e9a 1843/* Only for WM_LP. */
7221fc33 1844static uint32_t ilk_compute_fbc_wm(const struct intel_crtc_state *cstate,
43d59eda 1845 const struct intel_plane_state *pstate,
1fda9882 1846 uint32_t pri_val)
cca32e9a 1847{
ac484963
VS		 1848 int cpp = pstate->base.fb ?
1849 drm_format_plane_cpp(pstate->base.fb->pixel_format, 0) : 0;
43d59eda 1850
936e71e3 1851 if (!cstate->base.active || !pstate->base.visible)
cca32e9a
PZ		 1852 return 0;
1853
936e71e3 1854 return ilk_wm_fbc(pri_val, drm_rect_width(&pstate->base.dst), cpp);
cca32e9a
PZ		 1855}
1856
158ae64f
VS		 1857static unsigned int ilk_display_fifo_size(const struct drm_device *dev)
1858{
416f4727
VS		 1859 if (INTEL_INFO(dev)->gen >= 8)
1860 return 3072;
1861 else if (INTEL_INFO(dev)->gen >= 7)
158ae64f
VS		 1862 return 768;
1863 else
1864 return 512;
1865}
1866
4e975081
VS		 1867static unsigned int ilk_plane_wm_reg_max(const struct drm_device *dev,
1868 int level, bool is_sprite)
1869{
1870 if (INTEL_INFO(dev)->gen >= 8)
1871 /* BDW primary/sprite plane watermarks */
1872 return level == 0 ? 255 : 2047;
1873 else if (INTEL_INFO(dev)->gen >= 7)
1874 /* IVB/HSW primary/sprite plane watermarks */
1875 return level == 0 ? 127 : 1023;
1876 else if (!is_sprite)
1877 /* ILK/SNB primary plane watermarks */
1878 return level == 0 ? 127 : 511;
1879 else
1880 /* ILK/SNB sprite plane watermarks */
1881 return level == 0 ? 63 : 255;
1882}
1883
1884static unsigned int ilk_cursor_wm_reg_max(const struct drm_device *dev,
1885 int level)
1886{
1887 if (INTEL_INFO(dev)->gen >= 7)
1888 return level == 0 ? 63 : 255;
1889 else
1890 return level == 0 ? 31 : 63;
1891}
1892
1893static unsigned int ilk_fbc_wm_reg_max(const struct drm_device *dev)
1894{
1895 if (INTEL_INFO(dev)->gen >= 8)
1896 return 31;
1897 else
1898 return 15;
1899}
1900
158ae64f
VS		 1901/* Calculate the maximum primary/sprite plane watermark */
1902static unsigned int ilk_plane_wm_max(const struct drm_device *dev,
1903 int level,
240264f4 1904 const struct intel_wm_config *config,
158ae64f
VS		 1905 enum intel_ddb_partitioning ddb_partitioning,
1906 bool is_sprite)
1907{
1908 unsigned int fifo_size = ilk_display_fifo_size(dev);
158ae64f
VS		 1909
1910 /* if sprites aren't enabled, sprites get nothing */
240264f4 1911 if (is_sprite && !config->sprites_enabled)
158ae64f
VS		 1912 return 0;
1913
1914 /* HSW allows LP1+ watermarks even with multiple pipes */
240264f4 1915 if (level == 0 || config->num_pipes_active > 1) {
158ae64f
VS		 1916 fifo_size /= INTEL_INFO(dev)->num_pipes;
1917
1918 /*
1919 * For some reason the non self refresh
1920 * FIFO size is only half of the self
1921 * refresh FIFO size on ILK/SNB.
1922 */
1923 if (INTEL_INFO(dev)->gen <= 6)
1924 fifo_size /= 2;
1925 }
1926
240264f4 1927 if (config->sprites_enabled) {
158ae64f
VS		 1928 /* level 0 is always calculated with 1:1 split */
1929 if (level > 0 && ddb_partitioning == INTEL_DDB_PART_5_6) {
1930 if (is_sprite)
1931 fifo_size *= 5;
1932 fifo_size /= 6;
1933 } else {
1934 fifo_size /= 2;
1935 }
1936 }
1937
1938 /* clamp to max that the registers can hold */
4e975081 1939 return min(fifo_size, ilk_plane_wm_reg_max(dev, level, is_sprite));
158ae64f
VS		 1940}
1941
1942/* Calculate the maximum cursor plane watermark */
1943static unsigned int ilk_cursor_wm_max(const struct drm_device *dev,
240264f4
VS		 1944 int level,
1945 const struct intel_wm_config *config)
158ae64f
VS		 1946{
1947 /* HSW LP1+ watermarks w/ multiple pipes */
240264f4 1948 if (level > 0 && config->num_pipes_active > 1)
158ae64f
VS		 1949 return 64;
1950
1951 /* otherwise just report max that registers can hold */
4e975081 1952 return ilk_cursor_wm_reg_max(dev, level);
158ae64f
VS		 1953}
1954
d34ff9c6 1955static void ilk_compute_wm_maximums(const struct drm_device *dev,
34982fe1
VS		 1956 int level,
1957 const struct intel_wm_config *config,
1958 enum intel_ddb_partitioning ddb_partitioning,
820c1980 1959 struct ilk_wm_maximums *max)
158ae64f 1960{
240264f4
VS		 1961 max->pri = ilk_plane_wm_max(dev, level, config, ddb_partitioning, false);
1962 max->spr = ilk_plane_wm_max(dev, level, config, ddb_partitioning, true);
1963 max->cur = ilk_cursor_wm_max(dev, level, config);
4e975081 1964 max->fbc = ilk_fbc_wm_reg_max(dev);
158ae64f
VS		 1965}
1966
a3cb4048
VS		 1967static void ilk_compute_wm_reg_maximums(struct drm_device *dev,
1968 int level,
1969 struct ilk_wm_maximums *max)
1970{
1971 max->pri = ilk_plane_wm_reg_max(dev, level, false);
1972 max->spr = ilk_plane_wm_reg_max(dev, level, true);
1973 max->cur = ilk_cursor_wm_reg_max(dev, level);
1974 max->fbc = ilk_fbc_wm_reg_max(dev);
1975}
1976
d9395655 1977static bool ilk_validate_wm_level(int level,
820c1980 1978 const struct ilk_wm_maximums *max,
d9395655 1979 struct intel_wm_level *result)
a9786a11
VS		 1980{
1981 bool ret;
1982
1983 /* already determined to be invalid? */
1984 if (!result->enable)
1985 return false;
1986
1987 result->enable = result->pri_val <= max->pri &&
1988 result->spr_val <= max->spr &&
1989 result->cur_val <= max->cur;
1990
1991 ret = result->enable;
1992
1993 /*
1994 * HACK until we can pre-compute everything,
1995 * and thus fail gracefully if LP0 watermarks
1996 * are exceeded...
1997 */
1998 if (level == 0 && !result->enable) {
1999 if (result->pri_val > max->pri)
2000 DRM_DEBUG_KMS("Primary WM%d too large %u (max %u)\n",
2001 level, result->pri_val, max->pri);
2002 if (result->spr_val > max->spr)
2003 DRM_DEBUG_KMS("Sprite WM%d too large %u (max %u)\n",
2004 level, result->spr_val, max->spr);
2005 if (result->cur_val > max->cur)
2006 DRM_DEBUG_KMS("Cursor WM%d too large %u (max %u)\n",
2007 level, result->cur_val, max->cur);
2008
2009 result->pri_val = min_t(uint32_t, result->pri_val, max->pri);
2010 result->spr_val = min_t(uint32_t, result->spr_val, max->spr);
2011 result->cur_val = min_t(uint32_t, result->cur_val, max->cur);
2012 result->enable = true;
2013 }
2014
a9786a11
VS		 2015 return ret;
2016}
2017
d34ff9c6 2018static void ilk_compute_wm_level(const struct drm_i915_private *dev_priv,
43d59eda 2019 const struct intel_crtc *intel_crtc,
6f5ddd17 2020 int level,
7221fc33 2021 struct intel_crtc_state *cstate,
86c8bbbe
MR		 2022 struct intel_plane_state *pristate,
2023 struct intel_plane_state *sprstate,
2024 struct intel_plane_state *curstate,
1fd527cc 2025 struct intel_wm_level *result)
6f5ddd17
VS		 2026{
2027 uint16_t pri_latency = dev_priv->wm.pri_latency[level];
2028 uint16_t spr_latency = dev_priv->wm.spr_latency[level];
2029 uint16_t cur_latency = dev_priv->wm.cur_latency[level];
2030
2031 /* WM1+ latency values stored in 0.5us units */
2032 if (level > 0) {
2033 pri_latency *= 5;
2034 spr_latency *= 5;
2035 cur_latency *= 5;
2036 }
2037
e3bddded
ML		 2038 if (pristate) {
2039 result->pri_val = ilk_compute_pri_wm(cstate, pristate,
2040 pri_latency, level);
2041 result->fbc_val = ilk_compute_fbc_wm(cstate, pristate, result->pri_val);
2042 }
2043
2044 if (sprstate)
2045 result->spr_val = ilk_compute_spr_wm(cstate, sprstate, spr_latency);
2046
2047 if (curstate)
2048 result->cur_val = ilk_compute_cur_wm(cstate, curstate, cur_latency);
2049
6f5ddd17
VS		 2050 result->enable = true;
2051}
2052
801bcfff 2053static uint32_t
532f7a7f 2054hsw_compute_linetime_wm(const struct intel_crtc_state *cstate)
1f8eeabf 2055{
532f7a7f
VS		 2056 const struct intel_atomic_state *intel_state =
2057 to_intel_atomic_state(cstate->base.state);
ee91a159
MR		 2058 const struct drm_display_mode *adjusted_mode =
2059 &cstate->base.adjusted_mode;
85a02deb 2060 u32 linetime, ips_linetime;
1f8eeabf 2061
ee91a159
MR		 2062 if (!cstate->base.active)
2063 return 0;
2064 if (WARN_ON(adjusted_mode->crtc_clock == 0))
2065 return 0;
532f7a7f 2066 if (WARN_ON(intel_state->cdclk == 0))
801bcfff 2067 return 0;
1011d8c4 2068
1f8eeabf
ED		 2069 /* The WM are computed with base on how long it takes to fill a single
2070 * row at the given clock rate, multiplied by 8.
2071 * */
124abe07
VS		 2072 linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
2073 adjusted_mode->crtc_clock);
2074 ips_linetime = DIV_ROUND_CLOSEST(adjusted_mode->crtc_htotal * 1000 * 8,
532f7a7f 2075 intel_state->cdclk);
1f8eeabf 2076
801bcfff
PZ		 2077 return PIPE_WM_LINETIME_IPS_LINETIME(ips_linetime) |
2078 PIPE_WM_LINETIME_TIME(linetime);
1f8eeabf
ED		 2079}
2080
2af30a5c 2081static void intel_read_wm_latency(struct drm_device *dev, uint16_t wm[8])
12b134df 2082{
fac5e23e 2083 struct drm_i915_private *dev_priv = to_i915(dev);
12b134df 2084
2af30a5c
PB		 2085 if (IS_GEN9(dev)) {
2086 uint32_t val;
4f947386 2087 int ret, i;
367294be 2088 int level, max_level = ilk_wm_max_level(dev);
2af30a5c
PB		 2089
2090 /* read the first set of memory latencies[0:3] */
2091 val = 0; /* data0 to be programmed to 0 for first set */
2092 mutex_lock(&dev_priv->rps.hw_lock);
2093 ret = sandybridge_pcode_read(dev_priv,
2094 GEN9_PCODE_READ_MEM_LATENCY,
2095 &val);
2096 mutex_unlock(&dev_priv->rps.hw_lock);
2097
2098 if (ret) {
2099 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2100 return;
2101 }
2102
2103 wm[0] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2104 wm[1] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2105 GEN9_MEM_LATENCY_LEVEL_MASK;
2106 wm[2] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2107 GEN9_MEM_LATENCY_LEVEL_MASK;
2108 wm[3] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2109 GEN9_MEM_LATENCY_LEVEL_MASK;
2110
2111 /* read the second set of memory latencies[4:7] */
2112 val = 1; /* data0 to be programmed to 1 for second set */
2113 mutex_lock(&dev_priv->rps.hw_lock);
2114 ret = sandybridge_pcode_read(dev_priv,
2115 GEN9_PCODE_READ_MEM_LATENCY,
2116 &val);
2117 mutex_unlock(&dev_priv->rps.hw_lock);
2118 if (ret) {
2119 DRM_ERROR("SKL Mailbox read error = %d\n", ret);
2120 return;
2121 }
2122
2123 wm[4] = val & GEN9_MEM_LATENCY_LEVEL_MASK;
2124 wm[5] = (val >> GEN9_MEM_LATENCY_LEVEL_1_5_SHIFT) &
2125 GEN9_MEM_LATENCY_LEVEL_MASK;
2126 wm[6] = (val >> GEN9_MEM_LATENCY_LEVEL_2_6_SHIFT) &
2127 GEN9_MEM_LATENCY_LEVEL_MASK;
2128 wm[7] = (val >> GEN9_MEM_LATENCY_LEVEL_3_7_SHIFT) &
2129 GEN9_MEM_LATENCY_LEVEL_MASK;
2130
0727e40a
PZ		 2131 /*
2132 * If a level n (n > 1) has a 0us latency, all levels m (m >= n)
2133 * need to be disabled. We make sure to sanitize the values out
2134 * of the punit to satisfy this requirement.
2135 */
2136 for (level = 1; level <= max_level; level++) {
2137 if (wm[level] == 0) {
2138 for (i = level + 1; i <= max_level; i++)
2139 wm[i] = 0;
2140 break;
2141 }
2142 }
2143
367294be 2144 /*
6f97235b
DL		 2145 * WaWmMemoryReadLatency:skl
2146 *
367294be 2147 * punit doesn't take into account the read latency so we need
0727e40a
PZ		 2148 * to add 2us to the various latency levels we retrieve from the
2149 * punit when level 0 response data us 0us.
367294be 2150 */
0727e40a
PZ		 2151 if (wm[0] == 0) {
2152 wm[0] += 2;
2153 for (level = 1; level <= max_level; level++) {
2154 if (wm[level] == 0)
2155 break;
367294be 2156 wm[level] += 2;
4f947386 2157 }
0727e40a
PZ		 2158 }
2159
8652744b 2160 } else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
12b134df
VS		 2161 uint64_t sskpd = I915_READ64(MCH_SSKPD);
2162
2163 wm[0] = (sskpd >> 56) & 0xFF;
2164 if (wm[0] == 0)
2165 wm[0] = sskpd & 0xF;
e5d5019e
VS		 2166 wm[1] = (sskpd >> 4) & 0xFF;
2167 wm[2] = (sskpd >> 12) & 0xFF;
2168 wm[3] = (sskpd >> 20) & 0x1FF;
2169 wm[4] = (sskpd >> 32) & 0x1FF;
63cf9a13
VS		 2170 } else if (INTEL_INFO(dev)->gen >= 6) {
2171 uint32_t sskpd = I915_READ(MCH_SSKPD);
2172
2173 wm[0] = (sskpd >> SSKPD_WM0_SHIFT) & SSKPD_WM_MASK;
2174 wm[1] = (sskpd >> SSKPD_WM1_SHIFT) & SSKPD_WM_MASK;
2175 wm[2] = (sskpd >> SSKPD_WM2_SHIFT) & SSKPD_WM_MASK;
2176 wm[3] = (sskpd >> SSKPD_WM3_SHIFT) & SSKPD_WM_MASK;
3a88d0ac
VS		 2177 } else if (INTEL_INFO(dev)->gen >= 5) {
2178 uint32_t mltr = I915_READ(MLTR_ILK);
2179
2180 /* ILK primary LP0 latency is 700 ns */
2181 wm[0] = 7;
2182 wm[1] = (mltr >> MLTR_WM1_SHIFT) & ILK_SRLT_MASK;
2183 wm[2] = (mltr >> MLTR_WM2_SHIFT) & ILK_SRLT_MASK;
12b134df
VS		 2184 }
2185}
2186
53615a5e
VS		 2187static void intel_fixup_spr_wm_latency(struct drm_device *dev, uint16_t wm[5])
2188{
2189 /* ILK sprite LP0 latency is 1300 ns */
7e22dbbb 2190 if (IS_GEN5(dev))
53615a5e
VS		 2191 wm[0] = 13;
2192}
2193
fd6b8f43
TU		 2194static void intel_fixup_cur_wm_latency(struct drm_i915_private *dev_priv,
2195 uint16_t wm[5])
53615a5e
VS		 2196{
2197 /* ILK cursor LP0 latency is 1300 ns */
fd6b8f43 2198 if (IS_GEN5(dev_priv))
53615a5e
VS		 2199 wm[0] = 13;
2200
2201 /* WaDoubleCursorLP3Latency:ivb */
fd6b8f43 2202 if (IS_IVYBRIDGE(dev_priv))
53615a5e
VS		 2203 wm[3] *= 2;
2204}
2205
546c81fd 2206int ilk_wm_max_level(const struct drm_device *dev)
26ec971e 2207{
8652744b
TU		 2208 struct drm_i915_private *dev_priv = to_i915(dev);
2209
26ec971e 2210 /* how many WM levels are we expecting */
8652744b 2211 if (INTEL_GEN(dev_priv) >= 9)
2af30a5c 2212 return 7;
8652744b 2213 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ad0d6dc4 2214 return 4;
8652744b 2215 else if (INTEL_GEN(dev_priv) >= 6)
ad0d6dc4 2216 return 3;
26ec971e 2217 else
ad0d6dc4
VS		 2218 return 2;
2219}
7526ed79 2220
ad0d6dc4
VS		 2221static void intel_print_wm_latency(struct drm_device *dev,
2222 const char *name,
2af30a5c 2223 const uint16_t wm[8])
ad0d6dc4
VS		 2224{
2225 int level, max_level = ilk_wm_max_level(dev);
26ec971e
VS		 2226
2227 for (level = 0; level <= max_level; level++) {
2228 unsigned int latency = wm[level];
2229
2230 if (latency == 0) {
2231 DRM_ERROR("%s WM%d latency not provided\n",
2232 name, level);
2233 continue;
2234 }
2235
2af30a5c
PB		 2236 /*
2237 * - latencies are in us on gen9.
2238 * - before then, WM1+ latency values are in 0.5us units
2239 */
2240 if (IS_GEN9(dev))
2241 latency *= 10;
2242 else if (level > 0)
26ec971e
VS		 2243 latency *= 5;
2244
2245 DRM_DEBUG_KMS("%s WM%d latency %u (%u.%u usec)\n",
2246 name, level, wm[level],
2247 latency / 10, latency % 10);
2248 }
2249}
2250
e95a2f75
VS		 2251static bool ilk_increase_wm_latency(struct drm_i915_private *dev_priv,
2252 uint16_t wm[5], uint16_t min)
2253{
91c8a326 2254 int level, max_level = ilk_wm_max_level(&dev_priv->drm);
e95a2f75
VS		 2255
2256 if (wm[0] >= min)
2257 return false;
2258
2259 wm[0] = max(wm[0], min);
2260 for (level = 1; level <= max_level; level++)
2261 wm[level] = max_t(uint16_t, wm[level], DIV_ROUND_UP(min, 5));
2262
2263 return true;
2264}
2265
2266static void snb_wm_latency_quirk(struct drm_device *dev)
2267{
fac5e23e 2268 struct drm_i915_private *dev_priv = to_i915(dev);
e95a2f75
VS		 2269 bool changed;
2270
2271 /*
2272 * The BIOS provided WM memory latency values are often
2273 * inadequate for high resolution displays. Adjust them.
2274 */
2275 changed = ilk_increase_wm_latency(dev_priv, dev_priv->wm.pri_latency, 12) |
2276 ilk_increase_wm_latency(dev_priv, dev_priv->wm.spr_latency, 12) |
2277 ilk_increase_wm_latency(dev_priv, dev_priv->wm.cur_latency, 12);
2278
2279 if (!changed)
2280 return;
2281
2282 DRM_DEBUG_KMS("WM latency values increased to avoid potential underruns\n");
2283 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2284 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2285 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
2286}
2287
fa50ad61 2288static void ilk_setup_wm_latency(struct drm_device *dev)
53615a5e 2289{
fac5e23e 2290 struct drm_i915_private *dev_priv = to_i915(dev);
53615a5e
VS		 2291
2292 intel_read_wm_latency(dev, dev_priv->wm.pri_latency);
2293
2294 memcpy(dev_priv->wm.spr_latency, dev_priv->wm.pri_latency,
2295 sizeof(dev_priv->wm.pri_latency));
2296 memcpy(dev_priv->wm.cur_latency, dev_priv->wm.pri_latency,
2297 sizeof(dev_priv->wm.pri_latency));
2298
2299 intel_fixup_spr_wm_latency(dev, dev_priv->wm.spr_latency);
fd6b8f43 2300 intel_fixup_cur_wm_latency(dev_priv, dev_priv->wm.cur_latency);
26ec971e
VS		 2301
2302 intel_print_wm_latency(dev, "Primary", dev_priv->wm.pri_latency);
2303 intel_print_wm_latency(dev, "Sprite", dev_priv->wm.spr_latency);
2304 intel_print_wm_latency(dev, "Cursor", dev_priv->wm.cur_latency);
e95a2f75
VS		 2305
2306 if (IS_GEN6(dev))
2307 snb_wm_latency_quirk(dev);
53615a5e
VS		 2308}
2309
2af30a5c
PB		 2310static void skl_setup_wm_latency(struct drm_device *dev)
2311{
fac5e23e 2312 struct drm_i915_private *dev_priv = to_i915(dev);
2af30a5c
PB		 2313
2314 intel_read_wm_latency(dev, dev_priv->wm.skl_latency);
2315 intel_print_wm_latency(dev, "Gen9 Plane", dev_priv->wm.skl_latency);
2316}
2317
ed4a6a7c
MR		 2318static bool ilk_validate_pipe_wm(struct drm_device *dev,
2319 struct intel_pipe_wm *pipe_wm)
2320{
2321 /* LP0 watermark maximums depend on this pipe alone */
2322 const struct intel_wm_config config = {
2323 .num_pipes_active = 1,
2324 .sprites_enabled = pipe_wm->sprites_enabled,
2325 .sprites_scaled = pipe_wm->sprites_scaled,
2326 };
2327 struct ilk_wm_maximums max;
2328
2329 /* LP0 watermarks always use 1/2 DDB partitioning */
2330 ilk_compute_wm_maximums(dev, 0, &config, INTEL_DDB_PART_1_2, &max);
2331
2332 /* At least LP0 must be valid */
2333 if (!ilk_validate_wm_level(0, &max, &pipe_wm->wm[0])) {
2334 DRM_DEBUG_KMS("LP0 watermark invalid\n");
2335 return false;
2336 }
2337
2338 return true;
2339}
2340
0b2ae6d7 2341/* Compute new watermarks for the pipe */
e3bddded 2342static int ilk_compute_pipe_wm(struct intel_crtc_state *cstate)
0b2ae6d7 2343{
e3bddded
ML		 2344 struct drm_atomic_state *state = cstate->base.state;
2345 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
86c8bbbe 2346 struct intel_pipe_wm *pipe_wm;
e3bddded 2347 struct drm_device *dev = state->dev;
fac5e23e 2348 const struct drm_i915_private *dev_priv = to_i915(dev);
43d59eda 2349 struct intel_plane *intel_plane;
86c8bbbe 2350 struct intel_plane_state *pristate = NULL;
43d59eda 2351 struct intel_plane_state *sprstate = NULL;
86c8bbbe 2352 struct intel_plane_state *curstate = NULL;
d81f04c5 2353 int level, max_level = ilk_wm_max_level(dev), usable_level;
820c1980 2354 struct ilk_wm_maximums max;
0b2ae6d7 2355
e8f1f02e 2356 pipe_wm = &cstate->wm.ilk.optimal;
86c8bbbe 2357
43d59eda 2358 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
e3bddded
ML		 2359 struct intel_plane_state *ps;
2360
2361 ps = intel_atomic_get_existing_plane_state(state,
2362 intel_plane);
2363 if (!ps)
2364 continue;
86c8bbbe
MR		 2365
2366 if (intel_plane->base.type == DRM_PLANE_TYPE_PRIMARY)
e3bddded 2367 pristate = ps;
86c8bbbe 2368 else if (intel_plane->base.type == DRM_PLANE_TYPE_OVERLAY)
e3bddded 2369 sprstate = ps;
86c8bbbe 2370 else if (intel_plane->base.type == DRM_PLANE_TYPE_CURSOR)
e3bddded 2371 curstate = ps;
43d59eda
MR		 2372 }
2373
ed4a6a7c 2374 pipe_wm->pipe_enabled = cstate->base.active;
e3bddded 2375 if (sprstate) {
936e71e3
VS		 2376 pipe_wm->sprites_enabled = sprstate->base.visible;
2377 pipe_wm->sprites_scaled = sprstate->base.visible &&
2378 (drm_rect_width(&sprstate->base.dst) != drm_rect_width(&sprstate->base.src) >> 16 ||
2379 drm_rect_height(&sprstate->base.dst) != drm_rect_height(&sprstate->base.src) >> 16);
e3bddded
ML		 2380 }
2381
d81f04c5
ML		 2382 usable_level = max_level;
2383
7b39a0b7 2384 /* ILK/SNB: LP2+ watermarks only w/o sprites */
e3bddded 2385 if (INTEL_INFO(dev)->gen <= 6 && pipe_wm->sprites_enabled)
d81f04c5 2386 usable_level = 1;
7b39a0b7
VS		 2387
2388 /* ILK/SNB/IVB: LP1+ watermarks only w/o scaling */
ed4a6a7c 2389 if (pipe_wm->sprites_scaled)
d81f04c5 2390 usable_level = 0;
7b39a0b7 2391
86c8bbbe 2392 ilk_compute_wm_level(dev_priv, intel_crtc, 0, cstate,
71f0a626
ML		 2393 pristate, sprstate, curstate, &pipe_wm->raw_wm[0]);
2394
2395 memset(&pipe_wm->wm, 0, sizeof(pipe_wm->wm));
2396 pipe_wm->wm[0] = pipe_wm->raw_wm[0];
0b2ae6d7 2397
8652744b 2398 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
532f7a7f 2399 pipe_wm->linetime = hsw_compute_linetime_wm(cstate);
0b2ae6d7 2400
ed4a6a7c 2401 if (!ilk_validate_pipe_wm(dev, pipe_wm))
1a426d61 2402 return -EINVAL;
a3cb4048
VS		 2403
2404 ilk_compute_wm_reg_maximums(dev, 1, &max);
2405
2406 for (level = 1; level <= max_level; level++) {
71f0a626 2407 struct intel_wm_level *wm = &pipe_wm->raw_wm[level];
a3cb4048 2408
86c8bbbe 2409 ilk_compute_wm_level(dev_priv, intel_crtc, level, cstate,
d81f04c5 2410 pristate, sprstate, curstate, wm);
a3cb4048
VS		 2411
2412 /*
2413 * Disable any watermark level that exceeds the
2414 * register maximums since such watermarks are
2415 * always invalid.
2416 */
71f0a626
ML		 2417 if (level > usable_level)
2418 continue;
2419
2420 if (ilk_validate_wm_level(level, &max, wm))
2421 pipe_wm->wm[level] = *wm;
2422 else
d81f04c5 2423 usable_level = level;
a3cb4048
VS		 2424 }
2425
86c8bbbe 2426 return 0;
0b2ae6d7
VS		 2427}
2428
ed4a6a7c
MR		 2429/*
2430 * Build a set of 'intermediate' watermark values that satisfy both the old
2431 * state and the new state. These can be programmed to the hardware
2432 * immediately.
2433 */
2434static int ilk_compute_intermediate_wm(struct drm_device *dev,
2435 struct intel_crtc *intel_crtc,
2436 struct intel_crtc_state *newstate)
2437{
e8f1f02e 2438 struct intel_pipe_wm *a = &newstate->wm.ilk.intermediate;
ed4a6a7c
MR		 2439 struct intel_pipe_wm *b = &intel_crtc->wm.active.ilk;
2440 int level, max_level = ilk_wm_max_level(dev);
2441
2442 /*
2443 * Start with the final, target watermarks, then combine with the
2444 * currently active watermarks to get values that are safe both before
2445 * and after the vblank.
2446 */
e8f1f02e 2447 *a = newstate->wm.ilk.optimal;
ed4a6a7c
MR		 2448 a->pipe_enabled |= b->pipe_enabled;
2449 a->sprites_enabled |= b->sprites_enabled;
2450 a->sprites_scaled |= b->sprites_scaled;
2451
2452 for (level = 0; level <= max_level; level++) {
2453 struct intel_wm_level *a_wm = &a->wm[level];
2454 const struct intel_wm_level *b_wm = &b->wm[level];
2455
2456 a_wm->enable &= b_wm->enable;
2457 a_wm->pri_val = max(a_wm->pri_val, b_wm->pri_val);
2458 a_wm->spr_val = max(a_wm->spr_val, b_wm->spr_val);
2459 a_wm->cur_val = max(a_wm->cur_val, b_wm->cur_val);
2460 a_wm->fbc_val = max(a_wm->fbc_val, b_wm->fbc_val);
2461 }
2462
2463 /*
2464 * We need to make sure that these merged watermark values are
2465 * actually a valid configuration themselves. If they're not,
2466 * there's no safe way to transition from the old state to
2467 * the new state, so we need to fail the atomic transaction.
2468 */
2469 if (!ilk_validate_pipe_wm(dev, a))
2470 return -EINVAL;
2471
2472 /*
2473 * If our intermediate WM are identical to the final WM, then we can
2474 * omit the post-vblank programming; only update if it's different.
2475 */
e8f1f02e 2476 if (memcmp(a, &newstate->wm.ilk.optimal, sizeof(*a)) == 0)
ed4a6a7c
MR		 2477 newstate->wm.need_postvbl_update = false;
2478
2479 return 0;
2480}
2481
0b2ae6d7
VS		 2482/*
2483 * Merge the watermarks from all active pipes for a specific level.
2484 */
2485static void ilk_merge_wm_level(struct drm_device *dev,
2486 int level,
2487 struct intel_wm_level *ret_wm)
2488{
2489 const struct intel_crtc *intel_crtc;
2490
d52fea5b
VS		 2491 ret_wm->enable = true;
2492
d3fcc808 2493 for_each_intel_crtc(dev, intel_crtc) {
ed4a6a7c 2494 const struct intel_pipe_wm *active = &intel_crtc->wm.active.ilk;
fe392efd
VS		 2495 const struct intel_wm_level *wm = &active->wm[level];
2496
2497 if (!active->pipe_enabled)
2498 continue;
0b2ae6d7 2499
d52fea5b
VS		 2500 /*
2501 * The watermark values may have been used in the past,
2502 * so we must maintain them in the registers for some
2503 * time even if the level is now disabled.
2504 */
0b2ae6d7 2505 if (!wm->enable)
d52fea5b 2506 ret_wm->enable = false;
0b2ae6d7
VS		 2507
2508 ret_wm->pri_val = max(ret_wm->pri_val, wm->pri_val);
2509 ret_wm->spr_val = max(ret_wm->spr_val, wm->spr_val);
2510 ret_wm->cur_val = max(ret_wm->cur_val, wm->cur_val);
2511 ret_wm->fbc_val = max(ret_wm->fbc_val, wm->fbc_val);
2512 }
0b2ae6d7
VS		 2513}
2514
2515/*
2516 * Merge all low power watermarks for all active pipes.
2517 */
2518static void ilk_wm_merge(struct drm_device *dev,
0ba22e26 2519 const struct intel_wm_config *config,
820c1980 2520 const struct ilk_wm_maximums *max,
0b2ae6d7
VS		 2521 struct intel_pipe_wm *merged)
2522{
fac5e23e 2523 struct drm_i915_private *dev_priv = to_i915(dev);
0b2ae6d7 2524 int level, max_level = ilk_wm_max_level(dev);
d52fea5b 2525 int last_enabled_level = max_level;
0b2ae6d7 2526
0ba22e26 2527 /* ILK/SNB/IVB: LP1+ watermarks only w/ single pipe */
fd6b8f43 2528 if ((INTEL_GEN(dev_priv) <= 6 || IS_IVYBRIDGE(dev_priv)) &&
0ba22e26 2529 config->num_pipes_active > 1)
1204d5ba 2530 last_enabled_level = 0;
0ba22e26 2531
6c8b6c28
VS		 2532 /* ILK: FBC WM must be disabled always */
2533 merged->fbc_wm_enabled = INTEL_INFO(dev)->gen >= 6;
0b2ae6d7
VS		 2534
2535 /* merge each WM1+ level */
2536 for (level = 1; level <= max_level; level++) {
2537 struct intel_wm_level *wm = &merged->wm[level];
2538
2539 ilk_merge_wm_level(dev, level, wm);
2540
d52fea5b
VS		 2541 if (level > last_enabled_level)
2542 wm->enable = false;
2543 else if (!ilk_validate_wm_level(level, max, wm))
2544 /* make sure all following levels get disabled */
2545 last_enabled_level = level - 1;
0b2ae6d7
VS		 2546
2547 /*
2548 * The spec says it is preferred to disable
2549 * FBC WMs instead of disabling a WM level.
2550 */
2551 if (wm->fbc_val > max->fbc) {
d52fea5b
VS		 2552 if (wm->enable)
2553 merged->fbc_wm_enabled = false;
0b2ae6d7
VS		 2554 wm->fbc_val = 0;
2555 }
2556 }
6c8b6c28
VS		 2557
2558 /* ILK: LP2+ must be disabled when FBC WM is disabled but FBC enabled */
2559 /*
2560 * FIXME this is racy. FBC might get enabled later.
2561 * What we should check here is whether FBC can be
2562 * enabled sometime later.
2563 */
7733b49b 2564 if (IS_GEN5(dev) && !merged->fbc_wm_enabled &&
0e631adc 2565 intel_fbc_is_active(dev_priv)) {
6c8b6c28
VS		 2566 for (level = 2; level <= max_level; level++) {
2567 struct intel_wm_level *wm = &merged->wm[level];
2568
2569 wm->enable = false;
2570 }
2571 }
0b2ae6d7
VS		 2572}
2573
b380ca3c
VS		 2574static int ilk_wm_lp_to_level(int wm_lp, const struct intel_pipe_wm *pipe_wm)
2575{
2576 /* LP1,LP2,LP3 levels are either 1,2,3 or 1,3,4 */
2577 return wm_lp + (wm_lp >= 2 && pipe_wm->wm[4].enable);
2578}
2579
a68d68ee
VS		 2580/* The value we need to program into the WM_LPx latency field */
2581static unsigned int ilk_wm_lp_latency(struct drm_device *dev, int level)
2582{
fac5e23e 2583 struct drm_i915_private *dev_priv = to_i915(dev);
a68d68ee 2584
8652744b 2585 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
a68d68ee
VS		 2586 return 2 * level;
2587 else
2588 return dev_priv->wm.pri_latency[level];
2589}
2590
820c1980 2591static void ilk_compute_wm_results(struct drm_device *dev,
0362c781 2592 const struct intel_pipe_wm *merged,
609cedef 2593 enum intel_ddb_partitioning partitioning,
820c1980 2594 struct ilk_wm_values *results)
801bcfff 2595{
0b2ae6d7
VS		 2596 struct intel_crtc *intel_crtc;
2597 int level, wm_lp;
cca32e9a 2598
0362c781 2599 results->enable_fbc_wm = merged->fbc_wm_enabled;
609cedef 2600 results->partitioning = partitioning;
cca32e9a 2601
0b2ae6d7 2602 /* LP1+ register values */
cca32e9a 2603 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
1fd527cc 2604 const struct intel_wm_level *r;
801bcfff 2605
b380ca3c 2606 level = ilk_wm_lp_to_level(wm_lp, merged);
0b2ae6d7 2607
0362c781 2608 r = &merged->wm[level];
cca32e9a 2609
d52fea5b
VS		 2610 /*
2611 * Maintain the watermark values even if the level is
2612 * disabled. Doing otherwise could cause underruns.
2613 */
2614 results->wm_lp[wm_lp - 1] =
a68d68ee 2615 (ilk_wm_lp_latency(dev, level) << WM1_LP_LATENCY_SHIFT) |
416f4727
VS		 2616 (r->pri_val << WM1_LP_SR_SHIFT) |
2617 r->cur_val;
2618
d52fea5b
VS		 2619 if (r->enable)
2620 results->wm_lp[wm_lp - 1] |= WM1_LP_SR_EN;
2621
416f4727
VS		 2622 if (INTEL_INFO(dev)->gen >= 8)
2623 results->wm_lp[wm_lp - 1] |=
2624 r->fbc_val << WM1_LP_FBC_SHIFT_BDW;
2625 else
2626 results->wm_lp[wm_lp - 1] |=
2627 r->fbc_val << WM1_LP_FBC_SHIFT;
2628
d52fea5b
VS		 2629 /*
2630 * Always set WM1S_LP_EN when spr_val != 0, even if the
2631 * level is disabled. Doing otherwise could cause underruns.
2632 */
6cef2b8a
VS		 2633 if (INTEL_INFO(dev)->gen <= 6 && r->spr_val) {
2634 WARN_ON(wm_lp != 1);
2635 results->wm_lp_spr[wm_lp - 1] = WM1S_LP_EN | r->spr_val;
2636 } else
2637 results->wm_lp_spr[wm_lp - 1] = r->spr_val;
cca32e9a 2638 }
801bcfff 2639
0b2ae6d7 2640 /* LP0 register values */
d3fcc808 2641 for_each_intel_crtc(dev, intel_crtc) {
0b2ae6d7 2642 enum pipe pipe = intel_crtc->pipe;
ed4a6a7c
MR		 2643 const struct intel_wm_level *r =
2644 &intel_crtc->wm.active.ilk.wm[0];
0b2ae6d7
VS		 2645
2646 if (WARN_ON(!r->enable))
2647 continue;
2648
ed4a6a7c 2649 results->wm_linetime[pipe] = intel_crtc->wm.active.ilk.linetime;
1011d8c4 2650
0b2ae6d7
VS		 2651 results->wm_pipe[pipe] =
2652 (r->pri_val << WM0_PIPE_PLANE_SHIFT) |
2653 (r->spr_val << WM0_PIPE_SPRITE_SHIFT) |
2654 r->cur_val;
801bcfff
PZ		 2655 }
2656}
2657
861f3389
PZ		 2658/* Find the result with the highest level enabled. Check for enable_fbc_wm in
2659 * case both are at the same level. Prefer r1 in case they're the same. */
820c1980 2660static struct intel_pipe_wm *ilk_find_best_result(struct drm_device *dev,
198a1e9b
VS		 2661 struct intel_pipe_wm *r1,
2662 struct intel_pipe_wm *r2)
861f3389 2663{
198a1e9b
VS		 2664 int level, max_level = ilk_wm_max_level(dev);
2665 int level1 = 0, level2 = 0;
861f3389 2666
198a1e9b
VS		 2667 for (level = 1; level <= max_level; level++) {
2668 if (r1->wm[level].enable)
2669 level1 = level;
2670 if (r2->wm[level].enable)
2671 level2 = level;
861f3389
PZ		 2672 }
2673
198a1e9b
VS		 2674 if (level1 == level2) {
2675 if (r2->fbc_wm_enabled && !r1->fbc_wm_enabled)
861f3389
PZ		 2676 return r2;
2677 else
2678 return r1;
198a1e9b 2679 } else if (level1 > level2) {
861f3389
PZ		 2680 return r1;
2681 } else {
2682 return r2;
2683 }
2684}
2685
49a687c4
VS		 2686/* dirty bits used to track which watermarks need changes */
2687#define WM_DIRTY_PIPE(pipe) (1 << (pipe))
2688#define WM_DIRTY_LINETIME(pipe) (1 << (8 + (pipe)))
2689#define WM_DIRTY_LP(wm_lp) (1 << (15 + (wm_lp)))
2690#define WM_DIRTY_LP_ALL (WM_DIRTY_LP(1) | WM_DIRTY_LP(2) | WM_DIRTY_LP(3))
2691#define WM_DIRTY_FBC (1 << 24)
2692#define WM_DIRTY_DDB (1 << 25)
2693
055e393f 2694static unsigned int ilk_compute_wm_dirty(struct drm_i915_private *dev_priv,
820c1980
ID		 2695 const struct ilk_wm_values *old,
2696 const struct ilk_wm_values *new)
49a687c4
VS		 2697{
2698 unsigned int dirty = 0;
2699 enum pipe pipe;
2700 int wm_lp;
2701
055e393f 2702 for_each_pipe(dev_priv, pipe) {
49a687c4
VS		 2703 if (old->wm_linetime[pipe] != new->wm_linetime[pipe]) {
2704 dirty |= WM_DIRTY_LINETIME(pipe);
2705 /* Must disable LP1+ watermarks too */
2706 dirty |= WM_DIRTY_LP_ALL;
2707 }
2708
2709 if (old->wm_pipe[pipe] != new->wm_pipe[pipe]) {
2710 dirty |= WM_DIRTY_PIPE(pipe);
2711 /* Must disable LP1+ watermarks too */
2712 dirty |= WM_DIRTY_LP_ALL;
2713 }
2714 }
2715
2716 if (old->enable_fbc_wm != new->enable_fbc_wm) {
2717 dirty |= WM_DIRTY_FBC;
2718 /* Must disable LP1+ watermarks too */
2719 dirty |= WM_DIRTY_LP_ALL;
2720 }
2721
2722 if (old->partitioning != new->partitioning) {
2723 dirty |= WM_DIRTY_DDB;
2724 /* Must disable LP1+ watermarks too */
2725 dirty |= WM_DIRTY_LP_ALL;
2726 }
2727
2728 /* LP1+ watermarks already deemed dirty, no need to continue */
2729 if (dirty & WM_DIRTY_LP_ALL)
2730 return dirty;
2731
2732 /* Find the lowest numbered LP1+ watermark in need of an update... */
2733 for (wm_lp = 1; wm_lp <= 3; wm_lp++) {
2734 if (old->wm_lp[wm_lp - 1] != new->wm_lp[wm_lp - 1] ||
2735 old->wm_lp_spr[wm_lp - 1] != new->wm_lp_spr[wm_lp - 1])
2736 break;
2737 }
2738
2739 /* ...and mark it and all higher numbered LP1+ watermarks as dirty */
2740 for (; wm_lp <= 3; wm_lp++)
2741 dirty |= WM_DIRTY_LP(wm_lp);
2742
2743 return dirty;
2744}
2745
8553c18e
VS		 2746static bool _ilk_disable_lp_wm(struct drm_i915_private *dev_priv,
2747 unsigned int dirty)
801bcfff 2748{
820c1980 2749 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e 2750 bool changed = false;
801bcfff 2751
facd619b
VS		 2752 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] & WM1_LP_SR_EN) {
2753 previous->wm_lp[2] &= ~WM1_LP_SR_EN;
2754 I915_WRITE(WM3_LP_ILK, previous->wm_lp[2]);
8553c18e 2755 changed = true;
facd619b
VS		 2756 }
2757 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] & WM1_LP_SR_EN) {
2758 previous->wm_lp[1] &= ~WM1_LP_SR_EN;
2759 I915_WRITE(WM2_LP_ILK, previous->wm_lp[1]);
8553c18e 2760 changed = true;
facd619b
VS		 2761 }
2762 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] & WM1_LP_SR_EN) {
2763 previous->wm_lp[0] &= ~WM1_LP_SR_EN;
2764 I915_WRITE(WM1_LP_ILK, previous->wm_lp[0]);
8553c18e 2765 changed = true;
facd619b 2766 }
801bcfff 2767
facd619b
VS		 2768 /*
2769 * Don't touch WM1S_LP_EN here.
2770 * Doing so could cause underruns.
2771 */
6cef2b8a 2772
8553c18e
VS		 2773 return changed;
2774}
2775
2776/*
2777 * The spec says we shouldn't write when we don't need, because every write
2778 * causes WMs to be re-evaluated, expending some power.
2779 */
820c1980
ID		 2780static void ilk_write_wm_values(struct drm_i915_private *dev_priv,
2781 struct ilk_wm_values *results)
8553c18e 2782{
91c8a326 2783 struct drm_device *dev = &dev_priv->drm;
820c1980 2784 struct ilk_wm_values *previous = &dev_priv->wm.hw;
8553c18e
VS		 2785 unsigned int dirty;
2786 uint32_t val;
2787
055e393f 2788 dirty = ilk_compute_wm_dirty(dev_priv, previous, results);
8553c18e
VS		 2789 if (!dirty)
2790 return;
2791
2792 _ilk_disable_lp_wm(dev_priv, dirty);
2793
49a687c4 2794 if (dirty & WM_DIRTY_PIPE(PIPE_A))
801bcfff 2795 I915_WRITE(WM0_PIPEA_ILK, results->wm_pipe[0]);
49a687c4 2796 if (dirty & WM_DIRTY_PIPE(PIPE_B))
801bcfff 2797 I915_WRITE(WM0_PIPEB_ILK, results->wm_pipe[1]);
49a687c4 2798 if (dirty & WM_DIRTY_PIPE(PIPE_C))
801bcfff
PZ		 2799 I915_WRITE(WM0_PIPEC_IVB, results->wm_pipe[2]);
2800
49a687c4 2801 if (dirty & WM_DIRTY_LINETIME(PIPE_A))
801bcfff 2802 I915_WRITE(PIPE_WM_LINETIME(PIPE_A), results->wm_linetime[0]);
49a687c4 2803 if (dirty & WM_DIRTY_LINETIME(PIPE_B))
801bcfff 2804 I915_WRITE(PIPE_WM_LINETIME(PIPE_B), results->wm_linetime[1]);
49a687c4 2805 if (dirty & WM_DIRTY_LINETIME(PIPE_C))
801bcfff
PZ		 2806 I915_WRITE(PIPE_WM_LINETIME(PIPE_C), results->wm_linetime[2]);
2807
49a687c4 2808 if (dirty & WM_DIRTY_DDB) {
8652744b 2809 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv)) {
ac9545fd
VS		 2810 val = I915_READ(WM_MISC);
2811 if (results->partitioning == INTEL_DDB_PART_1_2)
2812 val &= ~WM_MISC_DATA_PARTITION_5_6;
2813 else
2814 val |= WM_MISC_DATA_PARTITION_5_6;
2815 I915_WRITE(WM_MISC, val);
2816 } else {
2817 val = I915_READ(DISP_ARB_CTL2);
2818 if (results->partitioning == INTEL_DDB_PART_1_2)
2819 val &= ~DISP_DATA_PARTITION_5_6;
2820 else
2821 val |= DISP_DATA_PARTITION_5_6;
2822 I915_WRITE(DISP_ARB_CTL2, val);
2823 }
1011d8c4
PZ		 2824 }
2825
49a687c4 2826 if (dirty & WM_DIRTY_FBC) {
cca32e9a
PZ		 2827 val = I915_READ(DISP_ARB_CTL);
2828 if (results->enable_fbc_wm)
2829 val &= ~DISP_FBC_WM_DIS;
2830 else
2831 val |= DISP_FBC_WM_DIS;
2832 I915_WRITE(DISP_ARB_CTL, val);
2833 }
2834
954911eb
ID		 2835 if (dirty & WM_DIRTY_LP(1) &&
2836 previous->wm_lp_spr[0] != results->wm_lp_spr[0])
2837 I915_WRITE(WM1S_LP_ILK, results->wm_lp_spr[0]);
2838
2839 if (INTEL_INFO(dev)->gen >= 7) {
6cef2b8a
VS		 2840 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp_spr[1] != results->wm_lp_spr[1])
2841 I915_WRITE(WM2S_LP_IVB, results->wm_lp_spr[1]);
2842 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp_spr[2] != results->wm_lp_spr[2])
2843 I915_WRITE(WM3S_LP_IVB, results->wm_lp_spr[2]);
2844 }
801bcfff 2845
facd619b 2846 if (dirty & WM_DIRTY_LP(1) && previous->wm_lp[0] != results->wm_lp[0])
801bcfff 2847 I915_WRITE(WM1_LP_ILK, results->wm_lp[0]);
facd619b 2848 if (dirty & WM_DIRTY_LP(2) && previous->wm_lp[1] != results->wm_lp[1])
801bcfff 2849 I915_WRITE(WM2_LP_ILK, results->wm_lp[1]);
facd619b 2850 if (dirty & WM_DIRTY_LP(3) && previous->wm_lp[2] != results->wm_lp[2])
801bcfff 2851 I915_WRITE(WM3_LP_ILK, results->wm_lp[2]);
609cedef
VS		 2852
2853 dev_priv->wm.hw = *results;
801bcfff
PZ		 2854}
2855
ed4a6a7c 2856bool ilk_disable_lp_wm(struct drm_device *dev)
8553c18e 2857{
fac5e23e 2858 struct drm_i915_private *dev_priv = to_i915(dev);
8553c18e
VS		 2859
2860 return _ilk_disable_lp_wm(dev_priv, WM_DIRTY_LP_ALL);
2861}
2862
656d1b89 2863#define SKL_SAGV_BLOCK_TIME 30 /* µs */
b9cec075 2864
024c9045
MR		 2865/*
2866 * Return the index of a plane in the SKL DDB and wm result arrays. Primary
2867 * plane is always in slot 0, cursor is always in slot I915_MAX_PLANES-1, and
2868 * other universal planes are in indices 1..n. Note that this may leave unused
2869 * indices between the top "sprite" plane and the cursor.
2870 */
2871static int
2872skl_wm_plane_id(const struct intel_plane *plane)
2873{
2874 switch (plane->base.type) {
2875 case DRM_PLANE_TYPE_PRIMARY:
2876 return 0;
2877 case DRM_PLANE_TYPE_CURSOR:
2878 return PLANE_CURSOR;
2879 case DRM_PLANE_TYPE_OVERLAY:
2880 return plane->plane + 1;
2881 default:
2882 MISSING_CASE(plane->base.type);
2883 return plane->plane;
2884 }
2885}
2886
56feca91
PZ		 2887static bool
2888intel_has_sagv(struct drm_i915_private *dev_priv)
2889{
6e3100ec
PZ		 2890 if (IS_KABYLAKE(dev_priv))
2891 return true;
2892
2893 if (IS_SKYLAKE(dev_priv) &&
2894 dev_priv->sagv_status != I915_SAGV_NOT_CONTROLLED)
2895 return true;
2896
2897 return false;
56feca91
PZ		 2898}
2899
656d1b89
L		 2900/*
2901 * SAGV dynamically adjusts the system agent voltage and clock frequencies
2902 * depending on power and performance requirements. The display engine access
2903 * to system memory is blocked during the adjustment time. Because of the
2904 * blocking time, having this enabled can cause full system hangs and/or pipe
2905 * underruns if we don't meet all of the following requirements:
2906 *
2907 * - <= 1 pipe enabled
2908 * - All planes can enable watermarks for latencies >= SAGV engine block time
2909 * - We're not using an interlaced display configuration
2910 */
2911int
16dcdc4e 2912intel_enable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2913{
2914 int ret;
2915
56feca91
PZ		 2916 if (!intel_has_sagv(dev_priv))
2917 return 0;
2918
2919 if (dev_priv->sagv_status == I915_SAGV_ENABLED)
656d1b89
L		 2920 return 0;
2921
2922 DRM_DEBUG_KMS("Enabling the SAGV\n");
2923 mutex_lock(&dev_priv->rps.hw_lock);
2924
2925 ret = sandybridge_pcode_write(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2926 GEN9_SAGV_ENABLE);
2927
2928 /* We don't need to wait for the SAGV when enabling */
2929 mutex_unlock(&dev_priv->rps.hw_lock);
2930
2931 /*
2932 * Some skl systems, pre-release machines in particular,
2933 * don't actually have an SAGV.
2934 */
6e3100ec 2935 if (IS_SKYLAKE(dev_priv) && ret == -ENXIO) {
656d1b89 2936 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2937 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2938 return 0;
2939 } else if (ret < 0) {
2940 DRM_ERROR("Failed to enable the SAGV\n");
2941 return ret;
2942 }
2943
16dcdc4e 2944 dev_priv->sagv_status = I915_SAGV_ENABLED;
656d1b89
L		 2945 return 0;
2946}
2947
2948static int
16dcdc4e 2949intel_do_sagv_disable(struct drm_i915_private *dev_priv)
656d1b89
L		 2950{
2951 int ret;
2952 uint32_t temp = GEN9_SAGV_DISABLE;
2953
2954 ret = sandybridge_pcode_read(dev_priv, GEN9_PCODE_SAGV_CONTROL,
2955 &temp);
2956 if (ret)
2957 return ret;
2958 else
2959 return temp & GEN9_SAGV_IS_DISABLED;
2960}
2961
2962int
16dcdc4e 2963intel_disable_sagv(struct drm_i915_private *dev_priv)
656d1b89
L		 2964{
2965 int ret, result;
2966
56feca91
PZ		 2967 if (!intel_has_sagv(dev_priv))
2968 return 0;
2969
2970 if (dev_priv->sagv_status == I915_SAGV_DISABLED)
656d1b89
L		 2971 return 0;
2972
2973 DRM_DEBUG_KMS("Disabling the SAGV\n");
2974 mutex_lock(&dev_priv->rps.hw_lock);
2975
2976 /* bspec says to keep retrying for at least 1 ms */
16dcdc4e 2977 ret = wait_for(result = intel_do_sagv_disable(dev_priv), 1);
656d1b89
L		 2978 mutex_unlock(&dev_priv->rps.hw_lock);
2979
2980 if (ret == -ETIMEDOUT) {
2981 DRM_ERROR("Request to disable SAGV timed out\n");
2982 return -ETIMEDOUT;
2983 }
2984
2985 /*
2986 * Some skl systems, pre-release machines in particular,
2987 * don't actually have an SAGV.
2988 */
6e3100ec 2989 if (IS_SKYLAKE(dev_priv) && result == -ENXIO) {
656d1b89 2990 DRM_DEBUG_DRIVER("No SAGV found on system, ignoring\n");
16dcdc4e 2991 dev_priv->sagv_status = I915_SAGV_NOT_CONTROLLED;
656d1b89
L		 2992 return 0;
2993 } else if (result < 0) {
2994 DRM_ERROR("Failed to disable the SAGV\n");
2995 return result;
2996 }
2997
16dcdc4e 2998 dev_priv->sagv_status = I915_SAGV_DISABLED;
656d1b89
L		 2999 return 0;
3000}
3001
16dcdc4e 3002bool intel_can_enable_sagv(struct drm_atomic_state *state)
656d1b89
L		 3003{
3004 struct drm_device *dev = state->dev;
3005 struct drm_i915_private *dev_priv = to_i915(dev);
3006 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3007 struct drm_crtc *crtc;
3008 enum pipe pipe;
3009 int level, plane;
3010
56feca91
PZ		 3011 if (!intel_has_sagv(dev_priv))
3012 return false;
3013
656d1b89
L		 3014 /*
3015 * SKL workaround: bspec recommends we disable the SAGV when we have
3016 * more then one pipe enabled
3017 *
3018 * If there are no active CRTCs, no additional checks need be performed
3019 */
3020 if (hweight32(intel_state->active_crtcs) == 0)
3021 return true;
3022 else if (hweight32(intel_state->active_crtcs) > 1)
3023 return false;
3024
3025 /* Since we're now guaranteed to only have one active CRTC... */
3026 pipe = ffs(intel_state->active_crtcs) - 1;
3027 crtc = dev_priv->pipe_to_crtc_mapping[pipe];
3028
3029 if (crtc->state->mode.flags & DRM_MODE_FLAG_INTERLACE)
3030 return false;
3031
3032 for_each_plane(dev_priv, pipe, plane) {
3033 /* Skip this plane if it's not enabled */
3034 if (intel_state->wm_results.plane[pipe][plane][0] == 0)
3035 continue;
3036
3037 /* Find the highest enabled wm level for this plane */
3038 for (level = ilk_wm_max_level(dev);
3039 intel_state->wm_results.plane[pipe][plane][level] == 0; --level)
3040 { }
3041
3042 /*
3043 * If any of the planes on this pipe don't enable wm levels
3044 * that incur memory latencies higher then 30µs we can't enable
3045 * the SAGV
3046 */
3047 if (dev_priv->wm.skl_latency[level] < SKL_SAGV_BLOCK_TIME)
3048 return false;
3049 }
3050
3051 return true;
3052}
3053
b9cec075
DL		 3054static void
3055skl_ddb_get_pipe_allocation_limits(struct drm_device *dev,
024c9045 3056 const struct intel_crtc_state *cstate,
c107acfe
MR		 3057 struct skl_ddb_entry *alloc, /* out */
3058 int *num_active /* out */)
b9cec075 3059{
c107acfe
MR		 3060 struct drm_atomic_state *state = cstate->base.state;
3061 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3062 struct drm_i915_private *dev_priv = to_i915(dev);
024c9045 3063 struct drm_crtc *for_crtc = cstate->base.crtc;
b9cec075
DL		 3064 unsigned int pipe_size, ddb_size;
3065 int nth_active_pipe;
c107acfe
MR		 3066 int pipe = to_intel_crtc(for_crtc)->pipe;
3067
a6d3460e 3068 if (WARN_ON(!state) || !cstate->base.active) {
b9cec075
DL		 3069 alloc->start = 0;
3070 alloc->end = 0;
a6d3460e 3071 *num_active = hweight32(dev_priv->active_crtcs);
b9cec075
DL		 3072 return;
3073 }
3074
a6d3460e
MR		 3075 if (intel_state->active_pipe_changes)
3076 *num_active = hweight32(intel_state->active_crtcs);
3077 else
3078 *num_active = hweight32(dev_priv->active_crtcs);
3079
6f3fff60
D		 3080 ddb_size = INTEL_INFO(dev_priv)->ddb_size;
3081 WARN_ON(ddb_size == 0);
b9cec075
DL		 3082
3083 ddb_size -= 4; /* 4 blocks for bypass path allocation */
3084
c107acfe 3085 /*
a6d3460e
MR		 3086 * If the state doesn't change the active CRTC's, then there's
3087 * no need to recalculate; the existing pipe allocation limits
3088 * should remain unchanged. Note that we're safe from racing
3089 * commits since any racing commit that changes the active CRTC
3090 * list would need to grab _all_ crtc locks, including the one
3091 * we currently hold.
c107acfe 3092 */
a6d3460e
MR		 3093 if (!intel_state->active_pipe_changes) {
3094 *alloc = dev_priv->wm.skl_hw.ddb.pipe[pipe];
3095 return;
c107acfe 3096 }
a6d3460e
MR		 3097
3098 nth_active_pipe = hweight32(intel_state->active_crtcs &
3099 (drm_crtc_mask(for_crtc) - 1));
3100 pipe_size = ddb_size / hweight32(intel_state->active_crtcs);
3101 alloc->start = nth_active_pipe * ddb_size / *num_active;
3102 alloc->end = alloc->start + pipe_size;
b9cec075
DL		 3103}
3104
c107acfe 3105static unsigned int skl_cursor_allocation(int num_active)
b9cec075 3106{
c107acfe 3107 if (num_active == 1)
b9cec075
DL		 3108 return 32;
3109
3110 return 8;
3111}
3112
a269c583
DL		 3113static void skl_ddb_entry_init_from_hw(struct skl_ddb_entry *entry, u32 reg)
3114{
3115 entry->start = reg & 0x3ff;
3116 entry->end = (reg >> 16) & 0x3ff;
16160e3d
DL		 3117 if (entry->end)
3118 entry->end += 1;
a269c583
DL		 3119}
3120
08db6652
DL		 3121void skl_ddb_get_hw_state(struct drm_i915_private *dev_priv,
3122 struct skl_ddb_allocation *ddb /* out */)
a269c583 3123{
a269c583
DL		 3124 enum pipe pipe;
3125 int plane;
3126 u32 val;
3127
b10f1b20
ML		 3128 memset(ddb, 0, sizeof(*ddb));
3129
a269c583 3130 for_each_pipe(dev_priv, pipe) {
4d800030
ID		 3131 enum intel_display_power_domain power_domain;
3132
3133 power_domain = POWER_DOMAIN_PIPE(pipe);
3134 if (!intel_display_power_get_if_enabled(dev_priv, power_domain))
b10f1b20
ML		 3135 continue;
3136
dd740780 3137 for_each_plane(dev_priv, pipe, plane) {
a269c583
DL		 3138 val = I915_READ(PLANE_BUF_CFG(pipe, plane));
3139 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][plane],
3140 val);
3141 }
3142
3143 val = I915_READ(CUR_BUF_CFG(pipe));
4969d33e
MR		 3144 skl_ddb_entry_init_from_hw(&ddb->plane[pipe][PLANE_CURSOR],
3145 val);
4d800030
ID		 3146
3147 intel_display_power_put(dev_priv, power_domain);
a269c583
DL		 3148 }
3149}
3150
9c2f7a9d
KM		 3151/*
3152 * Determines the downscale amount of a plane for the purposes of watermark calculations.
3153 * The bspec defines downscale amount as:
3154 *
3155 * """
3156 * Horizontal down scale amount = maximum[1, Horizontal source size /
3157 * Horizontal destination size]
3158 * Vertical down scale amount = maximum[1, Vertical source size /
3159 * Vertical destination size]
3160 * Total down scale amount = Horizontal down scale amount *
3161 * Vertical down scale amount
3162 * """
3163 *
3164 * Return value is provided in 16.16 fixed point form to retain fractional part.
3165 * Caller should take care of dividing & rounding off the value.
3166 */
3167static uint32_t
3168skl_plane_downscale_amount(const struct intel_plane_state *pstate)
3169{
3170 uint32_t downscale_h, downscale_w;
3171 uint32_t src_w, src_h, dst_w, dst_h;
3172
936e71e3 3173 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3174 return DRM_PLANE_HELPER_NO_SCALING;
3175
3176 /* n.b., src is 16.16 fixed point, dst is whole integer */
936e71e3
VS		 3177 src_w = drm_rect_width(&pstate->base.src);
3178 src_h = drm_rect_height(&pstate->base.src);
3179 dst_w = drm_rect_width(&pstate->base.dst);
3180 dst_h = drm_rect_height(&pstate->base.dst);
9c2f7a9d
KM		 3181 if (intel_rotation_90_or_270(pstate->base.rotation))
3182 swap(dst_w, dst_h);
3183
3184 downscale_h = max(src_h / dst_h, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3185 downscale_w = max(src_w / dst_w, (uint32_t)DRM_PLANE_HELPER_NO_SCALING);
3186
3187 /* Provide result in 16.16 fixed point */
3188 return (uint64_t)downscale_w * downscale_h >> 16;
3189}
3190
b9cec075 3191static unsigned int
024c9045
MR		 3192skl_plane_relative_data_rate(const struct intel_crtc_state *cstate,
3193 const struct drm_plane_state *pstate,
3194 int y)
b9cec075 3195{
a280f7dd 3196 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
024c9045 3197 struct drm_framebuffer *fb = pstate->fb;
8d19d7d9 3198 uint32_t down_scale_amount, data_rate;
a280f7dd 3199 uint32_t width = 0, height = 0;
a1de91e5
MR		 3200 unsigned format = fb ? fb->pixel_format : DRM_FORMAT_XRGB8888;
3201
936e71e3 3202 if (!intel_pstate->base.visible)
a1de91e5
MR		 3203 return 0;
3204 if (pstate->plane->type == DRM_PLANE_TYPE_CURSOR)
3205 return 0;
3206 if (y && format != DRM_FORMAT_NV12)
3207 return 0;
a280f7dd 3208
936e71e3
VS		 3209 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3210 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd
KM		 3211
3212 if (intel_rotation_90_or_270(pstate->rotation))
3213 swap(width, height);
2cd601c6
CK		 3214
3215 /* for planar format */
a1de91e5 3216 if (format == DRM_FORMAT_NV12) {
2cd601c6 3217 if (y) /* y-plane data rate */
8d19d7d9 3218 data_rate = width * height *
a1de91e5 3219 drm_format_plane_cpp(format, 0);
2cd601c6 3220 else /* uv-plane data rate */
8d19d7d9 3221 data_rate = (width / 2) * (height / 2) *
a1de91e5 3222 drm_format_plane_cpp(format, 1);
8d19d7d9
KM		 3223 } else {
3224 /* for packed formats */
3225 data_rate = width * height * drm_format_plane_cpp(format, 0);
2cd601c6
CK		 3226 }
3227
8d19d7d9
KM		 3228 down_scale_amount = skl_plane_downscale_amount(intel_pstate);
3229
3230 return (uint64_t)data_rate * down_scale_amount >> 16;
b9cec075
DL		 3231}
3232
3233/*
3234 * We don't overflow 32 bits. Worst case is 3 planes enabled, each fetching
3235 * a 8192x4096@32bpp framebuffer:
3236 * 3 * 4096 * 8192 * 4 < 2^32
3237 */
3238static unsigned int
9c74d826 3239skl_get_total_relative_data_rate(struct intel_crtc_state *intel_cstate)
b9cec075 3240{
9c74d826
MR		 3241 struct drm_crtc_state *cstate = &intel_cstate->base;
3242 struct drm_atomic_state *state = cstate->state;
3243 struct drm_crtc *crtc = cstate->crtc;
3244 struct drm_device *dev = crtc->dev;
3245 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
a6d3460e 3246 const struct drm_plane *plane;
024c9045 3247 const struct intel_plane *intel_plane;
a6d3460e 3248 struct drm_plane_state *pstate;
a1de91e5 3249 unsigned int rate, total_data_rate = 0;
9c74d826 3250 int id;
a6d3460e
MR		 3251 int i;
3252
3253 if (WARN_ON(!state))
3254 return 0;
b9cec075 3255
a1de91e5 3256 /* Calculate and cache data rate for each plane */
a6d3460e
MR		 3257 for_each_plane_in_state(state, plane, pstate, i) {
3258 id = skl_wm_plane_id(to_intel_plane(plane));
3259 intel_plane = to_intel_plane(plane);
3260
3261 if (intel_plane->pipe != intel_crtc->pipe)
3262 continue;
3263
3264 /* packed/uv */
3265 rate = skl_plane_relative_data_rate(intel_cstate,
3266 pstate, 0);
3267 intel_cstate->wm.skl.plane_data_rate[id] = rate;
3268
3269 /* y-plane */
3270 rate = skl_plane_relative_data_rate(intel_cstate,
3271 pstate, 1);
3272 intel_cstate->wm.skl.plane_y_data_rate[id] = rate;
a1de91e5 3273 }
024c9045 3274
a1de91e5
MR		 3275 /* Calculate CRTC's total data rate from cached values */
3276 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
3277 int id = skl_wm_plane_id(intel_plane);
024c9045 3278
a1de91e5 3279 /* packed/uv */
9c74d826
MR		 3280 total_data_rate += intel_cstate->wm.skl.plane_data_rate[id];
3281 total_data_rate += intel_cstate->wm.skl.plane_y_data_rate[id];
b9cec075
DL		 3282 }
3283
3284 return total_data_rate;
3285}
3286
cbcfd14b
KM		 3287static uint16_t
3288skl_ddb_min_alloc(const struct drm_plane_state *pstate,
3289 const int y)
3290{
3291 struct drm_framebuffer *fb = pstate->fb;
3292 struct intel_plane_state *intel_pstate = to_intel_plane_state(pstate);
3293 uint32_t src_w, src_h;
3294 uint32_t min_scanlines = 8;
3295 uint8_t plane_bpp;
3296
3297 if (WARN_ON(!fb))
3298 return 0;
3299
3300 /* For packed formats, no y-plane, return 0 */
3301 if (y && fb->pixel_format != DRM_FORMAT_NV12)
3302 return 0;
3303
3304 /* For Non Y-tile return 8-blocks */
3305 if (fb->modifier[0] != I915_FORMAT_MOD_Y_TILED &&
3306 fb->modifier[0] != I915_FORMAT_MOD_Yf_TILED)
3307 return 8;
3308
936e71e3
VS		 3309 src_w = drm_rect_width(&intel_pstate->base.src) >> 16;
3310 src_h = drm_rect_height(&intel_pstate->base.src) >> 16;
cbcfd14b
KM		 3311
3312 if (intel_rotation_90_or_270(pstate->rotation))
3313 swap(src_w, src_h);
3314
3315 /* Halve UV plane width and height for NV12 */
3316 if (fb->pixel_format == DRM_FORMAT_NV12 && !y) {
3317 src_w /= 2;
3318 src_h /= 2;
3319 }
3320
3321 if (fb->pixel_format == DRM_FORMAT_NV12 && !y)
3322 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 1);
3323 else
3324 plane_bpp = drm_format_plane_cpp(fb->pixel_format, 0);
3325
3326 if (intel_rotation_90_or_270(pstate->rotation)) {
3327 switch (plane_bpp) {
3328 case 1:
3329 min_scanlines = 32;
3330 break;
3331 case 2:
3332 min_scanlines = 16;
3333 break;
3334 case 4:
3335 min_scanlines = 8;
3336 break;
3337 case 8:
3338 min_scanlines = 4;
3339 break;
3340 default:
3341 WARN(1, "Unsupported pixel depth %u for rotation",
3342 plane_bpp);
3343 min_scanlines = 32;
3344 }
3345 }
3346
3347 return DIV_ROUND_UP((4 * src_w * plane_bpp), 512) * min_scanlines/4 + 3;
3348}
3349
c107acfe 3350static int
024c9045 3351skl_allocate_pipe_ddb(struct intel_crtc_state *cstate,
b9cec075
DL		 3352 struct skl_ddb_allocation *ddb /* out */)
3353{
c107acfe 3354 struct drm_atomic_state *state = cstate->base.state;
024c9045 3355 struct drm_crtc *crtc = cstate->base.crtc;
b9cec075
DL		 3356 struct drm_device *dev = crtc->dev;
3357 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3358 struct intel_plane *intel_plane;
c107acfe
MR		 3359 struct drm_plane *plane;
3360 struct drm_plane_state *pstate;
b9cec075 3361 enum pipe pipe = intel_crtc->pipe;
34bb56af 3362 struct skl_ddb_entry *alloc = &ddb->pipe[pipe];
b9cec075 3363 uint16_t alloc_size, start, cursor_blocks;
86a2100a
MR		 3364 uint16_t *minimum = cstate->wm.skl.minimum_blocks;
3365 uint16_t *y_minimum = cstate->wm.skl.minimum_y_blocks;
b9cec075 3366 unsigned int total_data_rate;
c107acfe
MR		 3367 int num_active;
3368 int id, i;
b9cec075 3369
5a920b85
PZ		 3370 /* Clear the partitioning for disabled planes. */
3371 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
3372 memset(ddb->y_plane[pipe], 0, sizeof(ddb->y_plane[pipe]));
3373
a6d3460e
MR		 3374 if (WARN_ON(!state))
3375 return 0;
3376
c107acfe
MR		 3377 if (!cstate->base.active) {
3378 ddb->pipe[pipe].start = ddb->pipe[pipe].end = 0;
c107acfe
MR		 3379 return 0;
3380 }
3381
a6d3460e 3382 skl_ddb_get_pipe_allocation_limits(dev, cstate, alloc, &num_active);
34bb56af 3383 alloc_size = skl_ddb_entry_size(alloc);
b9cec075
DL		 3384 if (alloc_size == 0) {
3385 memset(ddb->plane[pipe], 0, sizeof(ddb->plane[pipe]));
c107acfe 3386 return 0;
b9cec075
DL		 3387 }
3388
c107acfe 3389 cursor_blocks = skl_cursor_allocation(num_active);
4969d33e
MR		 3390 ddb->plane[pipe][PLANE_CURSOR].start = alloc->end - cursor_blocks;
3391 ddb->plane[pipe][PLANE_CURSOR].end = alloc->end;
b9cec075
DL		 3392
3393 alloc_size -= cursor_blocks;
b9cec075 3394
80958155 3395 /* 1. Allocate the mininum required blocks for each active plane */
a6d3460e
MR		 3396 for_each_plane_in_state(state, plane, pstate, i) {
3397 intel_plane = to_intel_plane(plane);
3398 id = skl_wm_plane_id(intel_plane);
c107acfe 3399
a6d3460e
MR		 3400 if (intel_plane->pipe != pipe)
3401 continue;
c107acfe 3402
936e71e3 3403 if (!to_intel_plane_state(pstate)->base.visible) {
a6d3460e
MR		 3404 minimum[id] = 0;
3405 y_minimum[id] = 0;
3406 continue;
3407 }
3408 if (plane->type == DRM_PLANE_TYPE_CURSOR) {
3409 minimum[id] = 0;
3410 y_minimum[id] = 0;
3411 continue;
c107acfe 3412 }
a6d3460e 3413
cbcfd14b
KM		 3414 minimum[id] = skl_ddb_min_alloc(pstate, 0);
3415 y_minimum[id] = skl_ddb_min_alloc(pstate, 1);
c107acfe 3416 }
80958155 3417
c107acfe
MR		 3418 for (i = 0; i < PLANE_CURSOR; i++) {
3419 alloc_size -= minimum[i];
3420 alloc_size -= y_minimum[i];
80958155
DL		 3421 }
3422
b9cec075 3423 /*
80958155
DL		 3424 * 2. Distribute the remaining space in proportion to the amount of
3425 * data each plane needs to fetch from memory.
b9cec075
DL		 3426 *
3427 * FIXME: we may not allocate every single block here.
3428 */
024c9045 3429 total_data_rate = skl_get_total_relative_data_rate(cstate);
a1de91e5 3430 if (total_data_rate == 0)
c107acfe 3431 return 0;
b9cec075 3432
34bb56af 3433 start = alloc->start;
024c9045 3434 for_each_intel_plane_on_crtc(dev, intel_crtc, intel_plane) {
2cd601c6
CK		 3435 unsigned int data_rate, y_data_rate;
3436 uint16_t plane_blocks, y_plane_blocks = 0;
024c9045 3437 int id = skl_wm_plane_id(intel_plane);
b9cec075 3438
a1de91e5 3439 data_rate = cstate->wm.skl.plane_data_rate[id];
b9cec075
DL		 3440
3441 /*
2cd601c6 3442 * allocation for (packed formats) or (uv-plane part of planar format):
b9cec075
DL		 3443 * promote the expression to 64 bits to avoid overflowing, the
3444 * result is < available as data_rate / total_data_rate < 1
3445 */
024c9045 3446 plane_blocks = minimum[id];
80958155
DL		 3447 plane_blocks += div_u64((uint64_t)alloc_size * data_rate,
3448 total_data_rate);
b9cec075 3449
c107acfe
MR		 3450 /* Leave disabled planes at (0,0) */
3451 if (data_rate) {
3452 ddb->plane[pipe][id].start = start;
3453 ddb->plane[pipe][id].end = start + plane_blocks;
3454 }
b9cec075
DL		 3455
3456 start += plane_blocks;
2cd601c6
CK		 3457
3458 /*
3459 * allocation for y_plane part of planar format:
3460 */
a1de91e5
MR		 3461 y_data_rate = cstate->wm.skl.plane_y_data_rate[id];
3462
3463 y_plane_blocks = y_minimum[id];
3464 y_plane_blocks += div_u64((uint64_t)alloc_size * y_data_rate,
3465 total_data_rate);
2cd601c6 3466
c107acfe
MR		 3467 if (y_data_rate) {
3468 ddb->y_plane[pipe][id].start = start;
3469 ddb->y_plane[pipe][id].end = start + y_plane_blocks;
3470 }
a1de91e5
MR		 3471
3472 start += y_plane_blocks;
b9cec075
DL		 3473 }
3474
c107acfe 3475 return 0;
b9cec075
DL		 3476}
3477
5cec258b 3478static uint32_t skl_pipe_pixel_rate(const struct intel_crtc_state *config)
2d41c0b5
PB		 3479{
3480 /* TODO: Take into account the scalers once we support them */
2d112de7 3481 return config->base.adjusted_mode.crtc_clock;
2d41c0b5
PB		 3482}
3483
3484/*
3485 * The max latency should be 257 (max the punit can code is 255 and we add 2us
ac484963 3486 * for the read latency) and cpp should always be <= 8, so that
2d41c0b5
PB		 3487 * should allow pixel_rate up to ~2 GHz which seems sufficient since max
3488 * 2xcdclk is 1350 MHz and the pixel rate should never exceed that.
3489*/
ac484963 3490static uint32_t skl_wm_method1(uint32_t pixel_rate, uint8_t cpp, uint32_t latency)
2d41c0b5
PB		 3491{
3492 uint32_t wm_intermediate_val, ret;
3493
3494 if (latency == 0)
3495 return UINT_MAX;
3496
ac484963 3497 wm_intermediate_val = latency * pixel_rate * cpp / 512;
2d41c0b5
PB		 3498 ret = DIV_ROUND_UP(wm_intermediate_val, 1000);
3499
3500 return ret;
3501}
3502
3503static uint32_t skl_wm_method2(uint32_t pixel_rate, uint32_t pipe_htotal,
7a1a8aed 3504 uint32_t latency, uint32_t plane_blocks_per_line)
2d41c0b5 3505{
d4c2aa60 3506 uint32_t ret;
d4c2aa60 3507 uint32_t wm_intermediate_val;
2d41c0b5
PB		 3508
3509 if (latency == 0)
3510 return UINT_MAX;
3511
2d41c0b5
PB		 3512 wm_intermediate_val = latency * pixel_rate;
3513 ret = DIV_ROUND_UP(wm_intermediate_val, pipe_htotal * 1000) *
d4c2aa60 3514 plane_blocks_per_line;
2d41c0b5
PB		 3515
3516 return ret;
3517}
3518
9c2f7a9d
KM		 3519static uint32_t skl_adjusted_plane_pixel_rate(const struct intel_crtc_state *cstate,
3520 struct intel_plane_state *pstate)
3521{
3522 uint64_t adjusted_pixel_rate;
3523 uint64_t downscale_amount;
3524 uint64_t pixel_rate;
3525
3526 /* Shouldn't reach here on disabled planes... */
936e71e3 3527 if (WARN_ON(!pstate->base.visible))
9c2f7a9d
KM		 3528 return 0;
3529
3530 /*
3531 * Adjusted plane pixel rate is just the pipe's adjusted pixel rate
3532 * with additional adjustments for plane-specific scaling.
3533 */
3534 adjusted_pixel_rate = skl_pipe_pixel_rate(cstate);
3535 downscale_amount = skl_plane_downscale_amount(pstate);
3536
3537 pixel_rate = adjusted_pixel_rate * downscale_amount >> 16;
3538 WARN_ON(pixel_rate != clamp_t(uint32_t, pixel_rate, 0, ~0));
3539
3540 return pixel_rate;
3541}
3542
55994c2c
MR		 3543static int skl_compute_plane_wm(const struct drm_i915_private *dev_priv,
3544 struct intel_crtc_state *cstate,
3545 struct intel_plane_state *intel_pstate,
3546 uint16_t ddb_allocation,
3547 int level,
3548 uint16_t *out_blocks, /* out */
3549 uint8_t *out_lines, /* out */
3550 bool *enabled /* out */)
2d41c0b5 3551{
33815fa5
MR		 3552 struct drm_plane_state *pstate = &intel_pstate->base;
3553 struct drm_framebuffer *fb = pstate->fb;
d4c2aa60
TU		 3554 uint32_t latency = dev_priv->wm.skl_latency[level];
3555 uint32_t method1, method2;
3556 uint32_t plane_bytes_per_line, plane_blocks_per_line;
3557 uint32_t res_blocks, res_lines;
3558 uint32_t selected_result;
ac484963 3559 uint8_t cpp;
a280f7dd 3560 uint32_t width = 0, height = 0;
9c2f7a9d 3561 uint32_t plane_pixel_rate;
75676ed4 3562 uint32_t y_tile_minimum, y_min_scanlines;
2d41c0b5 3563
936e71e3 3564 if (latency == 0 || !cstate->base.active || !intel_pstate->base.visible) {
55994c2c
MR		 3565 *enabled = false;
3566 return 0;
3567 }
2d41c0b5 3568
936e71e3
VS		 3569 width = drm_rect_width(&intel_pstate->base.src) >> 16;
3570 height = drm_rect_height(&intel_pstate->base.src) >> 16;
a280f7dd 3571
33815fa5 3572 if (intel_rotation_90_or_270(pstate->rotation))
a280f7dd
KM		 3573 swap(width, height);
3574
ac484963 3575 cpp = drm_format_plane_cpp(fb->pixel_format, 0);
9c2f7a9d
KM		 3576 plane_pixel_rate = skl_adjusted_plane_pixel_rate(cstate, intel_pstate);
3577
1186fa85
PZ		 3578 if (intel_rotation_90_or_270(pstate->rotation)) {
3579 int cpp = (fb->pixel_format == DRM_FORMAT_NV12) ?
3580 drm_format_plane_cpp(fb->pixel_format, 1) :
3581 drm_format_plane_cpp(fb->pixel_format, 0);
3582
3583 switch (cpp) {
3584 case 1:
3585 y_min_scanlines = 16;
3586 break;
3587 case 2:
3588 y_min_scanlines = 8;
3589 break;
1186fa85
PZ		 3590 case 4:
3591 y_min_scanlines = 4;
3592 break;
86a462bc
PZ		 3593 default:
3594 MISSING_CASE(cpp);
3595 return -EINVAL;
1186fa85
PZ		 3596 }
3597 } else {
3598 y_min_scanlines = 4;
3599 }
3600
7a1a8aed
PZ		 3601 plane_bytes_per_line = width * cpp;
3602 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3603 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3604 plane_blocks_per_line =
3605 DIV_ROUND_UP(plane_bytes_per_line * y_min_scanlines, 512);
3606 plane_blocks_per_line /= y_min_scanlines;
3607 } else if (fb->modifier[0] == DRM_FORMAT_MOD_NONE) {
3608 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512)
3609 + 1;
3610 } else {
3611 plane_blocks_per_line = DIV_ROUND_UP(plane_bytes_per_line, 512);
3612 }
3613
9c2f7a9d
KM		 3614 method1 = skl_wm_method1(plane_pixel_rate, cpp, latency);
3615 method2 = skl_wm_method2(plane_pixel_rate,
024c9045 3616 cstate->base.adjusted_mode.crtc_htotal,
1186fa85 3617 latency,
7a1a8aed 3618 plane_blocks_per_line);
2d41c0b5 3619
75676ed4
PZ		 3620 y_tile_minimum = plane_blocks_per_line * y_min_scanlines;
3621
024c9045
MR		 3622 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
3623 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
0fda6568
TU		 3624 selected_result = max(method2, y_tile_minimum);
3625 } else {
f1db3eaf
PZ		 3626 if ((cpp * cstate->base.adjusted_mode.crtc_htotal / 512 < 1) &&
3627 (plane_bytes_per_line / 512 < 1))
3628 selected_result = method2;
3629 else if ((ddb_allocation / plane_blocks_per_line) >= 1)
0fda6568
TU		 3630 selected_result = min(method1, method2);
3631 else
3632 selected_result = method1;
3633 }
2d41c0b5 3634
d4c2aa60
TU		 3635 res_blocks = selected_result + 1;
3636 res_lines = DIV_ROUND_UP(selected_result, plane_blocks_per_line);
e6d66171 3637
0fda6568 3638 if (level >= 1 && level <= 7) {
024c9045 3639 if (fb->modifier[0] == I915_FORMAT_MOD_Y_TILED ||
75676ed4
PZ		 3640 fb->modifier[0] == I915_FORMAT_MOD_Yf_TILED) {
3641 res_blocks += y_tile_minimum;
1186fa85 3642 res_lines += y_min_scanlines;
75676ed4 3643 } else {
0fda6568 3644 res_blocks++;
75676ed4 3645 }
0fda6568 3646 }
e6d66171 3647
55994c2c
MR		 3648 if (res_blocks >= ddb_allocation || res_lines > 31) {
3649 *enabled = false;
6b6bada7
MR		 3650
3651 /*
3652 * If there are no valid level 0 watermarks, then we can't
3653 * support this display configuration.
3654 */
3655 if (level) {
3656 return 0;
3657 } else {
3658 DRM_DEBUG_KMS("Requested display configuration exceeds system watermark limitations\n");
3659 DRM_DEBUG_KMS("Plane %d.%d: blocks required = %u/%u, lines required = %u/31\n",
3660 to_intel_crtc(cstate->base.crtc)->pipe,
3661 skl_wm_plane_id(to_intel_plane(pstate->plane)),
3662 res_blocks, ddb_allocation, res_lines);
3663
3664 return -EINVAL;
3665 }
55994c2c 3666 }
e6d66171
DL		 3667
3668 *out_blocks = res_blocks;
3669 *out_lines = res_lines;
55994c2c 3670 *enabled = true;
2d41c0b5 3671
55994c2c 3672 return 0;
2d41c0b5
PB		 3673}
3674
f4a96752
MR		 3675static int
3676skl_compute_wm_level(const struct drm_i915_private *dev_priv,
3677 struct skl_ddb_allocation *ddb,
3678 struct intel_crtc_state *cstate,
3679 int level,
3680 struct skl_wm_level *result)
2d41c0b5 3681{
f4a96752 3682 struct drm_atomic_state *state = cstate->base.state;
024c9045 3683 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
f4a96752 3684 struct drm_plane *plane;
024c9045 3685 struct intel_plane *intel_plane;
33815fa5 3686 struct intel_plane_state *intel_pstate;
2d41c0b5 3687 uint16_t ddb_blocks;
024c9045 3688 enum pipe pipe = intel_crtc->pipe;
55994c2c 3689 int ret;
024c9045 3690
f4a96752
MR		 3691 /*
3692 * We'll only calculate watermarks for planes that are actually
3693 * enabled, so make sure all other planes are set as disabled.
3694 */
3695 memset(result, 0, sizeof(*result));
3696
91c8a326
CW		 3697 for_each_intel_plane_mask(&dev_priv->drm,
3698 intel_plane,
3699 cstate->base.plane_mask) {
024c9045 3700 int i = skl_wm_plane_id(intel_plane);
2d41c0b5 3701
f4a96752
MR		 3702 plane = &intel_plane->base;
3703 intel_pstate = NULL;
3704 if (state)
3705 intel_pstate =
3706 intel_atomic_get_existing_plane_state(state,
3707 intel_plane);
3708
3709 /*
3710 * Note: If we start supporting multiple pending atomic commits
3711 * against the same planes/CRTC's in the future, plane->state
3712 * will no longer be the correct pre-state to use for the
3713 * calculations here and we'll need to change where we get the
3714 * 'unchanged' plane data from.
3715 *
3716 * For now this is fine because we only allow one queued commit
3717 * against a CRTC. Even if the plane isn't modified by this
3718 * transaction and we don't have a plane lock, we still have
3719 * the CRTC's lock, so we know that no other transactions are
3720 * racing with us to update it.
3721 */
3722 if (!intel_pstate)
3723 intel_pstate = to_intel_plane_state(plane->state);
3724
3725 WARN_ON(!intel_pstate->base.fb);
3726
2d41c0b5
PB		 3727 ddb_blocks = skl_ddb_entry_size(&ddb->plane[pipe][i]);
3728
55994c2c
MR		 3729 ret = skl_compute_plane_wm(dev_priv,
3730 cstate,
3731 intel_pstate,
3732 ddb_blocks,
3733 level,
3734 &result->plane_res_b[i],
3735 &result->plane_res_l[i],
3736 &result->plane_en[i]);
3737 if (ret)
3738 return ret;
2d41c0b5 3739 }
f4a96752
MR		 3740
3741 return 0;
2d41c0b5
PB		 3742}
3743
407b50f3 3744static uint32_t
024c9045 3745skl_compute_linetime_wm(struct intel_crtc_state *cstate)
407b50f3 3746{
024c9045 3747 if (!cstate->base.active)
407b50f3
DL		 3748 return 0;
3749
024c9045 3750 if (WARN_ON(skl_pipe_pixel_rate(cstate) == 0))
661abfc0 3751 return 0;
407b50f3 3752
024c9045
MR		 3753 return DIV_ROUND_UP(8 * cstate->base.adjusted_mode.crtc_htotal * 1000,
3754 skl_pipe_pixel_rate(cstate));
407b50f3
DL		 3755}
3756
024c9045 3757static void skl_compute_transition_wm(struct intel_crtc_state *cstate,
9414f563 3758 struct skl_wm_level *trans_wm /* out */)
407b50f3 3759{
024c9045 3760 struct drm_crtc *crtc = cstate->base.crtc;
9414f563 3761 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
024c9045 3762 struct intel_plane *intel_plane;
9414f563 3763
024c9045 3764 if (!cstate->base.active)
407b50f3 3765 return;
9414f563
DL		 3766
3767 /* Until we know more, just disable transition WMs */
024c9045
MR		 3768 for_each_intel_plane_on_crtc(crtc->dev, intel_crtc, intel_plane) {
3769 int i = skl_wm_plane_id(intel_plane);
3770
9414f563 3771 trans_wm->plane_en[i] = false;
024c9045 3772 }
407b50f3
DL		 3773}
3774
55994c2c
MR		 3775static int skl_build_pipe_wm(struct intel_crtc_state *cstate,
3776 struct skl_ddb_allocation *ddb,
3777 struct skl_pipe_wm *pipe_wm)
2d41c0b5 3778{
024c9045 3779 struct drm_device *dev = cstate->base.crtc->dev;
fac5e23e 3780 const struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 3781 int level, max_level = ilk_wm_max_level(dev);
55994c2c 3782 int ret;
2d41c0b5
PB		 3783
3784 for (level = 0; level <= max_level; level++) {
55994c2c
MR		 3785 ret = skl_compute_wm_level(dev_priv, ddb, cstate,
3786 level, &pipe_wm->wm[level]);
3787 if (ret)
3788 return ret;
2d41c0b5 3789 }
024c9045 3790 pipe_wm->linetime = skl_compute_linetime_wm(cstate);
2d41c0b5 3791
024c9045 3792 skl_compute_transition_wm(cstate, &pipe_wm->trans_wm);
55994c2c
MR		 3793
3794 return 0;
2d41c0b5
PB		 3795}
3796
3797static void skl_compute_wm_results(struct drm_device *dev,
2d41c0b5
PB		 3798 struct skl_pipe_wm *p_wm,
3799 struct skl_wm_values *r,
3800 struct intel_crtc *intel_crtc)
3801{
3802 int level, max_level = ilk_wm_max_level(dev);
3803 enum pipe pipe = intel_crtc->pipe;
9414f563
DL		 3804 uint32_t temp;
3805 int i;
2d41c0b5
PB		 3806
3807 for (level = 0; level <= max_level; level++) {
2d41c0b5
PB		 3808 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3809 temp = 0;
2d41c0b5
PB		 3810
3811 temp |= p_wm->wm[level].plane_res_l[i] <<
3812 PLANE_WM_LINES_SHIFT;
3813 temp |= p_wm->wm[level].plane_res_b[i];
3814 if (p_wm->wm[level].plane_en[i])
3815 temp |= PLANE_WM_EN;
3816
3817 r->plane[pipe][i][level] = temp;
2d41c0b5
PB		 3818 }
3819
3820 temp = 0;
2d41c0b5 3821
4969d33e
MR		 3822 temp |= p_wm->wm[level].plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3823 temp |= p_wm->wm[level].plane_res_b[PLANE_CURSOR];
2d41c0b5 3824
4969d33e 3825 if (p_wm->wm[level].plane_en[PLANE_CURSOR])
2d41c0b5
PB		 3826 temp |= PLANE_WM_EN;
3827
4969d33e 3828 r->plane[pipe][PLANE_CURSOR][level] = temp;
2d41c0b5
PB		 3829
3830 }
3831
9414f563
DL		 3832 /* transition WMs */
3833 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
3834 temp = 0;
3835 temp |= p_wm->trans_wm.plane_res_l[i] << PLANE_WM_LINES_SHIFT;
3836 temp |= p_wm->trans_wm.plane_res_b[i];
3837 if (p_wm->trans_wm.plane_en[i])
3838 temp |= PLANE_WM_EN;
3839
3840 r->plane_trans[pipe][i] = temp;
3841 }
3842
3843 temp = 0;
4969d33e
MR		 3844 temp |= p_wm->trans_wm.plane_res_l[PLANE_CURSOR] << PLANE_WM_LINES_SHIFT;
3845 temp |= p_wm->trans_wm.plane_res_b[PLANE_CURSOR];
3846 if (p_wm->trans_wm.plane_en[PLANE_CURSOR])
9414f563
DL		 3847 temp |= PLANE_WM_EN;
3848
4969d33e 3849 r->plane_trans[pipe][PLANE_CURSOR] = temp;
9414f563 3850
2d41c0b5
PB		 3851 r->wm_linetime[pipe] = p_wm->linetime;
3852}
3853
f0f59a00
VS		 3854static void skl_ddb_entry_write(struct drm_i915_private *dev_priv,
3855 i915_reg_t reg,
16160e3d
DL		 3856 const struct skl_ddb_entry *entry)
3857{
3858 if (entry->end)
3859 I915_WRITE(reg, (entry->end - 1) << 16 | entry->start);
3860 else
3861 I915_WRITE(reg, 0);
3862}
3863
62e0fb88
L		 3864void skl_write_plane_wm(struct intel_crtc *intel_crtc,
3865 const struct skl_wm_values *wm,
3866 int plane)
3867{
3868 struct drm_crtc *crtc = &intel_crtc->base;
3869 struct drm_device *dev = crtc->dev;
3870 struct drm_i915_private *dev_priv = to_i915(dev);
3871 int level, max_level = ilk_wm_max_level(dev);
3872 enum pipe pipe = intel_crtc->pipe;
3873
3874 for (level = 0; level <= max_level; level++) {
3875 I915_WRITE(PLANE_WM(pipe, plane, level),
3876 wm->plane[pipe][plane][level]);
3877 }
3878 I915_WRITE(PLANE_WM_TRANS(pipe, plane), wm->plane_trans[pipe][plane]);
27082493
L		 3879
3880 skl_ddb_entry_write(dev_priv, PLANE_BUF_CFG(pipe, plane),
3881 &wm->ddb.plane[pipe][plane]);
3882 skl_ddb_entry_write(dev_priv, PLANE_NV12_BUF_CFG(pipe, plane),
3883 &wm->ddb.y_plane[pipe][plane]);
62e0fb88
L		 3884}
3885
3886void skl_write_cursor_wm(struct intel_crtc *intel_crtc,
3887 const struct skl_wm_values *wm)
3888{
3889 struct drm_crtc *crtc = &intel_crtc->base;
3890 struct drm_device *dev = crtc->dev;
3891 struct drm_i915_private *dev_priv = to_i915(dev);
3892 int level, max_level = ilk_wm_max_level(dev);
3893 enum pipe pipe = intel_crtc->pipe;
3894
3895 for (level = 0; level <= max_level; level++) {
3896 I915_WRITE(CUR_WM(pipe, level),
3897 wm->plane[pipe][PLANE_CURSOR][level]);
3898 }
3899 I915_WRITE(CUR_WM_TRANS(pipe), wm->plane_trans[pipe][PLANE_CURSOR]);
5d374d96 3900
27082493
L		 3901 skl_ddb_entry_write(dev_priv, CUR_BUF_CFG(pipe),
3902 &wm->ddb.plane[pipe][PLANE_CURSOR]);
2d41c0b5
PB		 3903}
3904
27082493
L		 3905bool skl_ddb_allocation_equals(const struct skl_ddb_allocation *old,
3906 const struct skl_ddb_allocation *new,
3907 enum pipe pipe)
0e8fb7ba 3908{
27082493
L		 3909 return new->pipe[pipe].start == old->pipe[pipe].start &&
3910 new->pipe[pipe].end == old->pipe[pipe].end;
0e8fb7ba
DL		 3911}
3912
27082493
L		 3913static inline bool skl_ddb_entries_overlap(const struct skl_ddb_entry *a,
3914 const struct skl_ddb_entry *b)
0e8fb7ba 3915{
27082493 3916 return a->start < b->end && b->start < a->end;
0e8fb7ba
DL		 3917}
3918
27082493
L		 3919bool skl_ddb_allocation_overlaps(struct drm_atomic_state *state,
3920 const struct skl_ddb_allocation *old,
3921 const struct skl_ddb_allocation *new,
3922 enum pipe pipe)
0e8fb7ba 3923{
27082493
L		 3924 struct drm_device *dev = state->dev;
3925 struct intel_crtc *intel_crtc;
3926 enum pipe otherp;
0e8fb7ba 3927
27082493
L		 3928 for_each_intel_crtc(dev, intel_crtc) {
3929 otherp = intel_crtc->pipe;
0e8fb7ba 3930
27082493 3931 if (otherp == pipe)
0e8fb7ba
DL		 3932 continue;
3933
27082493
L		 3934 if (skl_ddb_entries_overlap(&new->pipe[pipe],
3935 &old->pipe[otherp]))
3936 return true;
0e8fb7ba
DL		 3937 }
3938
27082493 3939 return false;
0e8fb7ba
DL		 3940}
3941
55994c2c
MR		 3942static int skl_update_pipe_wm(struct drm_crtc_state *cstate,
3943 struct skl_ddb_allocation *ddb, /* out */
3944 struct skl_pipe_wm *pipe_wm, /* out */
3945 bool *changed /* out */)
2d41c0b5 3946{
f4a96752
MR		 3947 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->crtc);
3948 struct intel_crtc_state *intel_cstate = to_intel_crtc_state(cstate);
55994c2c 3949 int ret;
2d41c0b5 3950
55994c2c
MR		 3951 ret = skl_build_pipe_wm(intel_cstate, ddb, pipe_wm);
3952 if (ret)
3953 return ret;
2d41c0b5 3954
4e0963c7 3955 if (!memcmp(&intel_crtc->wm.active.skl, pipe_wm, sizeof(*pipe_wm)))
55994c2c
MR		 3956 *changed = false;
3957 else
3958 *changed = true;
2d41c0b5 3959
55994c2c 3960 return 0;
2d41c0b5
PB		 3961}
3962
9b613022
MR		 3963static uint32_t
3964pipes_modified(struct drm_atomic_state *state)
3965{
3966 struct drm_crtc *crtc;
3967 struct drm_crtc_state *cstate;
3968 uint32_t i, ret = 0;
3969
3970 for_each_crtc_in_state(state, crtc, cstate, i)
3971 ret |= drm_crtc_mask(crtc);
3972
3973 return ret;
3974}
3975
bb7791bd 3976static int
7f60e200
PZ		 3977skl_ddb_add_affected_planes(struct intel_crtc_state *cstate)
3978{
3979 struct drm_atomic_state *state = cstate->base.state;
3980 struct drm_device *dev = state->dev;
3981 struct drm_crtc *crtc = cstate->base.crtc;
3982 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
3983 struct drm_i915_private *dev_priv = to_i915(dev);
3984 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
3985 struct skl_ddb_allocation *new_ddb = &intel_state->wm_results.ddb;
3986 struct skl_ddb_allocation *cur_ddb = &dev_priv->wm.skl_hw.ddb;
3987 struct drm_plane_state *plane_state;
3988 struct drm_plane *plane;
3989 enum pipe pipe = intel_crtc->pipe;
3990 int id;
3991
3992 WARN_ON(!drm_atomic_get_existing_crtc_state(state, crtc));
3993
3994 drm_for_each_plane_mask(plane, dev, crtc->state->plane_mask) {
3995 id = skl_wm_plane_id(to_intel_plane(plane));
3996
3997 if (skl_ddb_entry_equal(&cur_ddb->plane[pipe][id],
3998 &new_ddb->plane[pipe][id]) &&
3999 skl_ddb_entry_equal(&cur_ddb->y_plane[pipe][id],
4000 &new_ddb->y_plane[pipe][id]))
4001 continue;
4002
4003 plane_state = drm_atomic_get_plane_state(state, plane);
4004 if (IS_ERR(plane_state))
4005 return PTR_ERR(plane_state);
4006 }
4007
4008 return 0;
4009}
4010
98d39494
MR		 4011static int
4012skl_compute_ddb(struct drm_atomic_state *state)
4013{
4014 struct drm_device *dev = state->dev;
4015 struct drm_i915_private *dev_priv = to_i915(dev);
4016 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4017 struct intel_crtc *intel_crtc;
734fa01f 4018 struct skl_ddb_allocation *ddb = &intel_state->wm_results.ddb;
9b613022 4019 uint32_t realloc_pipes = pipes_modified(state);
98d39494
MR		 4020 int ret;
4021
4022 /*
4023 * If this is our first atomic update following hardware readout,
4024 * we can't trust the DDB that the BIOS programmed for us. Let's
4025 * pretend that all pipes switched active status so that we'll
4026 * ensure a full DDB recompute.
4027 */
1b54a880
MR		 4028 if (dev_priv->wm.distrust_bios_wm) {
4029 ret = drm_modeset_lock(&dev->mode_config.connection_mutex,
4030 state->acquire_ctx);
4031 if (ret)
4032 return ret;
4033
98d39494
MR		 4034 intel_state->active_pipe_changes = ~0;
4035
1b54a880
MR		 4036 /*
4037 * We usually only initialize intel_state->active_crtcs if we
4038 * we're doing a modeset; make sure this field is always
4039 * initialized during the sanitization process that happens
4040 * on the first commit too.
4041 */
4042 if (!intel_state->modeset)
4043 intel_state->active_crtcs = dev_priv->active_crtcs;
4044 }
4045
98d39494
MR		 4046 /*
4047 * If the modeset changes which CRTC's are active, we need to
4048 * recompute the DDB allocation for *all* active pipes, even
4049 * those that weren't otherwise being modified in any way by this
4050 * atomic commit. Due to the shrinking of the per-pipe allocations
4051 * when new active CRTC's are added, it's possible for a pipe that
4052 * we were already using and aren't changing at all here to suddenly
4053 * become invalid if its DDB needs exceeds its new allocation.
4054 *
4055 * Note that if we wind up doing a full DDB recompute, we can't let
4056 * any other display updates race with this transaction, so we need
4057 * to grab the lock on *all* CRTC's.
4058 */
734fa01f 4059 if (intel_state->active_pipe_changes) {
98d39494 4060 realloc_pipes = ~0;
734fa01f
MR		 4061 intel_state->wm_results.dirty_pipes = ~0;
4062 }
98d39494 4063
5a920b85
PZ		 4064 /*
4065 * We're not recomputing for the pipes not included in the commit, so
4066 * make sure we start with the current state.
4067 */
4068 memcpy(ddb, &dev_priv->wm.skl_hw.ddb, sizeof(*ddb));
4069
98d39494
MR		 4070 for_each_intel_crtc_mask(dev, intel_crtc, realloc_pipes) {
4071 struct intel_crtc_state *cstate;
4072
4073 cstate = intel_atomic_get_crtc_state(state, intel_crtc);
4074 if (IS_ERR(cstate))
4075 return PTR_ERR(cstate);
4076
734fa01f 4077 ret = skl_allocate_pipe_ddb(cstate, ddb);
98d39494
MR		 4078 if (ret)
4079 return ret;
05a76d3d 4080
7f60e200 4081 ret = skl_ddb_add_affected_planes(cstate);
05a76d3d
L		 4082 if (ret)
4083 return ret;
98d39494
MR		 4084 }
4085
4086 return 0;
4087}
4088
2722efb9
MR		 4089static void
4090skl_copy_wm_for_pipe(struct skl_wm_values *dst,
4091 struct skl_wm_values *src,
4092 enum pipe pipe)
4093{
4094 dst->wm_linetime[pipe] = src->wm_linetime[pipe];
4095 memcpy(dst->plane[pipe], src->plane[pipe],
4096 sizeof(dst->plane[pipe]));
4097 memcpy(dst->plane_trans[pipe], src->plane_trans[pipe],
4098 sizeof(dst->plane_trans[pipe]));
4099
4100 dst->ddb.pipe[pipe] = src->ddb.pipe[pipe];
4101 memcpy(dst->ddb.y_plane[pipe], src->ddb.y_plane[pipe],
4102 sizeof(dst->ddb.y_plane[pipe]));
4103 memcpy(dst->ddb.plane[pipe], src->ddb.plane[pipe],
4104 sizeof(dst->ddb.plane[pipe]));
4105}
4106
98d39494
MR		 4107static int
4108skl_compute_wm(struct drm_atomic_state *state)
4109{
4110 struct drm_crtc *crtc;
4111 struct drm_crtc_state *cstate;
734fa01f
MR		 4112 struct intel_atomic_state *intel_state = to_intel_atomic_state(state);
4113 struct skl_wm_values *results = &intel_state->wm_results;
4114 struct skl_pipe_wm *pipe_wm;
98d39494 4115 bool changed = false;
734fa01f 4116 int ret, i;
98d39494
MR		 4117
4118 /*
4119 * If this transaction isn't actually touching any CRTC's, don't
4120 * bother with watermark calculation. Note that if we pass this
4121 * test, we're guaranteed to hold at least one CRTC state mutex,
4122 * which means we can safely use values like dev_priv->active_crtcs
4123 * since any racing commits that want to update them would need to
4124 * hold _all_ CRTC state mutexes.
4125 */
4126 for_each_crtc_in_state(state, crtc, cstate, i)
4127 changed = true;
4128 if (!changed)
4129 return 0;
4130
734fa01f
MR		 4131 /* Clear all dirty flags */
4132 results->dirty_pipes = 0;
4133
98d39494
MR		 4134 ret = skl_compute_ddb(state);
4135 if (ret)
4136 return ret;
4137
734fa01f
MR		 4138 /*
4139 * Calculate WM's for all pipes that are part of this transaction.
4140 * Note that the DDB allocation above may have added more CRTC's that
4141 * weren't otherwise being modified (and set bits in dirty_pipes) if
4142 * pipe allocations had to change.
4143 *
4144 * FIXME: Now that we're doing this in the atomic check phase, we
4145 * should allow skl_update_pipe_wm() to return failure in cases where
4146 * no suitable watermark values can be found.
4147 */
4148 for_each_crtc_in_state(state, crtc, cstate, i) {
4149 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4150 struct intel_crtc_state *intel_cstate =
4151 to_intel_crtc_state(cstate);
4152
4153 pipe_wm = &intel_cstate->wm.skl.optimal;
4154 ret = skl_update_pipe_wm(cstate, &results->ddb, pipe_wm,
4155 &changed);
4156 if (ret)
4157 return ret;
4158
4159 if (changed)
4160 results->dirty_pipes |= drm_crtc_mask(crtc);
4161
4162 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
4163 /* This pipe's WM's did not change */
4164 continue;
4165
4166 intel_cstate->update_wm_pre = true;
4167 skl_compute_wm_results(crtc->dev, pipe_wm, results, intel_crtc);
4168 }
4169
98d39494
MR		 4170 return 0;
4171}
4172
2d41c0b5
PB		 4173static void skl_update_wm(struct drm_crtc *crtc)
4174{
4175 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4176 struct drm_device *dev = crtc->dev;
fac5e23e 4177 struct drm_i915_private *dev_priv = to_i915(dev);
2d41c0b5 4178 struct skl_wm_values *results = &dev_priv->wm.skl_results;
2722efb9 4179 struct skl_wm_values *hw_vals = &dev_priv->wm.skl_hw;
4e0963c7 4180 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4181 struct skl_pipe_wm *pipe_wm = &cstate->wm.skl.optimal;
27082493 4182 enum pipe pipe = intel_crtc->pipe;
adda50b8 4183
734fa01f 4184 if ((results->dirty_pipes & drm_crtc_mask(crtc)) == 0)
2d41c0b5
PB		 4185 return;
4186
734fa01f
MR		 4187 intel_crtc->wm.active.skl = *pipe_wm;
4188
4189 mutex_lock(&dev_priv->wm.wm_mutex);
2d41c0b5 4190
2722efb9 4191 /*
27082493
L		 4192 * If this pipe isn't active already, we're going to be enabling it
4193 * very soon. Since it's safe to update a pipe's ddb allocation while
4194 * the pipe's shut off, just do so here. Already active pipes will have
4195 * their watermarks updated once we update their planes.
2722efb9 4196 */
27082493
L		 4197 if (crtc->state->active_changed) {
4198 int plane;
4199
4200 for (plane = 0; plane < intel_num_planes(intel_crtc); plane++)
4201 skl_write_plane_wm(intel_crtc, results, plane);
4202
4203 skl_write_cursor_wm(intel_crtc, results);
4204 }
4205
4206 skl_copy_wm_for_pipe(hw_vals, results, pipe);
734fa01f
MR		 4207
4208 mutex_unlock(&dev_priv->wm.wm_mutex);
2d41c0b5
PB		 4209}
4210
d890565c
VS		 4211static void ilk_compute_wm_config(struct drm_device *dev,
4212 struct intel_wm_config *config)
4213{
4214 struct intel_crtc *crtc;
4215
4216 /* Compute the currently _active_ config */
4217 for_each_intel_crtc(dev, crtc) {
4218 const struct intel_pipe_wm *wm = &crtc->wm.active.ilk;
4219
4220 if (!wm->pipe_enabled)
4221 continue;
4222
4223 config->sprites_enabled |= wm->sprites_enabled;
4224 config->sprites_scaled |= wm->sprites_scaled;
4225 config->num_pipes_active++;
4226 }
4227}
4228
ed4a6a7c 4229static void ilk_program_watermarks(struct drm_i915_private *dev_priv)
801bcfff 4230{
91c8a326 4231 struct drm_device *dev = &dev_priv->drm;
b9d5c839 4232 struct intel_pipe_wm lp_wm_1_2 = {}, lp_wm_5_6 = {}, *best_lp_wm;
820c1980 4233 struct ilk_wm_maximums max;
d890565c 4234 struct intel_wm_config config = {};
820c1980 4235 struct ilk_wm_values results = {};
77c122bc 4236 enum intel_ddb_partitioning partitioning;
261a27d1 4237
d890565c
VS		 4238 ilk_compute_wm_config(dev, &config);
4239
4240 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_1_2, &max);
4241 ilk_wm_merge(dev, &config, &max, &lp_wm_1_2);
a485bfb8
VS		 4242
4243 /* 5/6 split only in single pipe config on IVB+ */
ec98c8d1 4244 if (INTEL_INFO(dev)->gen >= 7 &&
d890565c
VS		 4245 config.num_pipes_active == 1 && config.sprites_enabled) {
4246 ilk_compute_wm_maximums(dev, 1, &config, INTEL_DDB_PART_5_6, &max);
4247 ilk_wm_merge(dev, &config, &max, &lp_wm_5_6);
0362c781 4248
820c1980 4249 best_lp_wm = ilk_find_best_result(dev, &lp_wm_1_2, &lp_wm_5_6);
861f3389 4250 } else {
198a1e9b 4251 best_lp_wm = &lp_wm_1_2;
861f3389
PZ		 4252 }
4253
198a1e9b 4254 partitioning = (best_lp_wm == &lp_wm_1_2) ?
77c122bc 4255 INTEL_DDB_PART_1_2 : INTEL_DDB_PART_5_6;
801bcfff 4256
820c1980 4257 ilk_compute_wm_results(dev, best_lp_wm, partitioning, &results);
609cedef 4258
820c1980 4259 ilk_write_wm_values(dev_priv, &results);
1011d8c4
PZ		 4260}
4261
ed4a6a7c 4262static void ilk_initial_watermarks(struct intel_crtc_state *cstate)
b9d5c839 4263{
ed4a6a7c
MR		 4264 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4265 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
b9d5c839 4266
ed4a6a7c 4267 mutex_lock(&dev_priv->wm.wm_mutex);
e8f1f02e 4268 intel_crtc->wm.active.ilk = cstate->wm.ilk.intermediate;
ed4a6a7c
MR		 4269 ilk_program_watermarks(dev_priv);
4270 mutex_unlock(&dev_priv->wm.wm_mutex);
4271}
bf220452 4272
ed4a6a7c
MR		 4273static void ilk_optimize_watermarks(struct intel_crtc_state *cstate)
4274{
4275 struct drm_i915_private *dev_priv = to_i915(cstate->base.crtc->dev);
4276 struct intel_crtc *intel_crtc = to_intel_crtc(cstate->base.crtc);
bf220452 4277
ed4a6a7c
MR		 4278 mutex_lock(&dev_priv->wm.wm_mutex);
4279 if (cstate->wm.need_postvbl_update) {
e8f1f02e 4280 intel_crtc->wm.active.ilk = cstate->wm.ilk.optimal;
ed4a6a7c
MR		 4281 ilk_program_watermarks(dev_priv);
4282 }
4283 mutex_unlock(&dev_priv->wm.wm_mutex);
b9d5c839
VS		 4284}
4285
3078999f
PB		 4286static void skl_pipe_wm_active_state(uint32_t val,
4287 struct skl_pipe_wm *active,
4288 bool is_transwm,
4289 bool is_cursor,
4290 int i,
4291 int level)
4292{
4293 bool is_enabled = (val & PLANE_WM_EN) != 0;
4294
4295 if (!is_transwm) {
4296 if (!is_cursor) {
4297 active->wm[level].plane_en[i] = is_enabled;
4298 active->wm[level].plane_res_b[i] =
4299 val & PLANE_WM_BLOCKS_MASK;
4300 active->wm[level].plane_res_l[i] =
4301 (val >> PLANE_WM_LINES_SHIFT) &
4302 PLANE_WM_LINES_MASK;
4303 } else {
4969d33e
MR		 4304 active->wm[level].plane_en[PLANE_CURSOR] = is_enabled;
4305 active->wm[level].plane_res_b[PLANE_CURSOR] =
3078999f 4306 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4307 active->wm[level].plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4308 (val >> PLANE_WM_LINES_SHIFT) &
4309 PLANE_WM_LINES_MASK;
4310 }
4311 } else {
4312 if (!is_cursor) {
4313 active->trans_wm.plane_en[i] = is_enabled;
4314 active->trans_wm.plane_res_b[i] =
4315 val & PLANE_WM_BLOCKS_MASK;
4316 active->trans_wm.plane_res_l[i] =
4317 (val >> PLANE_WM_LINES_SHIFT) &
4318 PLANE_WM_LINES_MASK;
4319 } else {
4969d33e
MR		 4320 active->trans_wm.plane_en[PLANE_CURSOR] = is_enabled;
4321 active->trans_wm.plane_res_b[PLANE_CURSOR] =
3078999f 4322 val & PLANE_WM_BLOCKS_MASK;
4969d33e 4323 active->trans_wm.plane_res_l[PLANE_CURSOR] =
3078999f
PB		 4324 (val >> PLANE_WM_LINES_SHIFT) &
4325 PLANE_WM_LINES_MASK;
4326 }
4327 }
4328}
4329
4330static void skl_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4331{
4332 struct drm_device *dev = crtc->dev;
fac5e23e 4333 struct drm_i915_private *dev_priv = to_i915(dev);
3078999f
PB		 4334 struct skl_wm_values *hw = &dev_priv->wm.skl_hw;
4335 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4336 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4337 struct skl_pipe_wm *active = &cstate->wm.skl.optimal;
3078999f
PB		 4338 enum pipe pipe = intel_crtc->pipe;
4339 int level, i, max_level;
4340 uint32_t temp;
4341
4342 max_level = ilk_wm_max_level(dev);
4343
4344 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
4345
4346 for (level = 0; level <= max_level; level++) {
4347 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4348 hw->plane[pipe][i][level] =
4349 I915_READ(PLANE_WM(pipe, i, level));
4969d33e 4350 hw->plane[pipe][PLANE_CURSOR][level] = I915_READ(CUR_WM(pipe, level));
3078999f
PB		 4351 }
4352
4353 for (i = 0; i < intel_num_planes(intel_crtc); i++)
4354 hw->plane_trans[pipe][i] = I915_READ(PLANE_WM_TRANS(pipe, i));
4969d33e 4355 hw->plane_trans[pipe][PLANE_CURSOR] = I915_READ(CUR_WM_TRANS(pipe));
3078999f 4356
3ef00284 4357 if (!intel_crtc->active)
3078999f
PB		 4358 return;
4359
2b4b9f35 4360 hw->dirty_pipes |= drm_crtc_mask(crtc);
3078999f
PB		 4361
4362 active->linetime = hw->wm_linetime[pipe];
4363
4364 for (level = 0; level <= max_level; level++) {
4365 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4366 temp = hw->plane[pipe][i][level];
4367 skl_pipe_wm_active_state(temp, active, false,
4368 false, i, level);
4369 }
4969d33e 4370 temp = hw->plane[pipe][PLANE_CURSOR][level];
3078999f
PB		 4371 skl_pipe_wm_active_state(temp, active, false, true, i, level);
4372 }
4373
4374 for (i = 0; i < intel_num_planes(intel_crtc); i++) {
4375 temp = hw->plane_trans[pipe][i];
4376 skl_pipe_wm_active_state(temp, active, true, false, i, 0);
4377 }
4378
4969d33e 4379 temp = hw->plane_trans[pipe][PLANE_CURSOR];
3078999f 4380 skl_pipe_wm_active_state(temp, active, true, true, i, 0);
4e0963c7
MR		 4381
4382 intel_crtc->wm.active.skl = *active;
3078999f
PB		 4383}
4384
4385void skl_wm_get_hw_state(struct drm_device *dev)
4386{
fac5e23e 4387 struct drm_i915_private *dev_priv = to_i915(dev);
a269c583 4388 struct skl_ddb_allocation *ddb = &dev_priv->wm.skl_hw.ddb;
3078999f
PB		 4389 struct drm_crtc *crtc;
4390
a269c583 4391 skl_ddb_get_hw_state(dev_priv, ddb);
3078999f
PB		 4392 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head)
4393 skl_pipe_wm_get_hw_state(crtc);
a1de91e5 4394
279e99d7
MR		 4395 if (dev_priv->active_crtcs) {
4396 /* Fully recompute DDB on first atomic commit */
4397 dev_priv->wm.distrust_bios_wm = true;
4398 } else {
4399 /* Easy/common case; just sanitize DDB now if everything off */
4400 memset(ddb, 0, sizeof(*ddb));
4401 }
3078999f
PB		 4402}
4403
243e6a44
VS		 4404static void ilk_pipe_wm_get_hw_state(struct drm_crtc *crtc)
4405{
4406 struct drm_device *dev = crtc->dev;
fac5e23e 4407 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4408 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44 4409 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
4e0963c7 4410 struct intel_crtc_state *cstate = to_intel_crtc_state(crtc->state);
e8f1f02e 4411 struct intel_pipe_wm *active = &cstate->wm.ilk.optimal;
243e6a44 4412 enum pipe pipe = intel_crtc->pipe;
f0f59a00 4413 static const i915_reg_t wm0_pipe_reg[] = {
243e6a44
VS		 4414 [PIPE_A] = WM0_PIPEA_ILK,
4415 [PIPE_B] = WM0_PIPEB_ILK,
4416 [PIPE_C] = WM0_PIPEC_IVB,
4417 };
4418
4419 hw->wm_pipe[pipe] = I915_READ(wm0_pipe_reg[pipe]);
8652744b 4420 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ce0e0713 4421 hw->wm_linetime[pipe] = I915_READ(PIPE_WM_LINETIME(pipe));
243e6a44 4422
15606534
VS		 4423 memset(active, 0, sizeof(*active));
4424
3ef00284 4425 active->pipe_enabled = intel_crtc->active;
2a44b76b
VS		 4426
4427 if (active->pipe_enabled) {
243e6a44
VS		 4428 u32 tmp = hw->wm_pipe[pipe];
4429
4430 /*
4431 * For active pipes LP0 watermark is marked as
4432 * enabled, and LP1+ watermaks as disabled since
4433 * we can't really reverse compute them in case
4434 * multiple pipes are active.
4435 */
4436 active->wm[0].enable = true;
4437 active->wm[0].pri_val = (tmp & WM0_PIPE_PLANE_MASK) >> WM0_PIPE_PLANE_SHIFT;
4438 active->wm[0].spr_val = (tmp & WM0_PIPE_SPRITE_MASK) >> WM0_PIPE_SPRITE_SHIFT;
4439 active->wm[0].cur_val = tmp & WM0_PIPE_CURSOR_MASK;
4440 active->linetime = hw->wm_linetime[pipe];
4441 } else {
4442 int level, max_level = ilk_wm_max_level(dev);
4443
4444 /*
4445 * For inactive pipes, all watermark levels
4446 * should be marked as enabled but zeroed,
4447 * which is what we'd compute them to.
4448 */
4449 for (level = 0; level <= max_level; level++)
4450 active->wm[level].enable = true;
4451 }
4e0963c7
MR		 4452
4453 intel_crtc->wm.active.ilk = *active;
243e6a44
VS		 4454}
4455
6eb1a681
VS		 4456#define _FW_WM(value, plane) \
4457 (((value) & DSPFW_ ## plane ## _MASK) >> DSPFW_ ## plane ## _SHIFT)
4458#define _FW_WM_VLV(value, plane) \
4459 (((value) & DSPFW_ ## plane ## _MASK_VLV) >> DSPFW_ ## plane ## _SHIFT)
4460
4461static void vlv_read_wm_values(struct drm_i915_private *dev_priv,
4462 struct vlv_wm_values *wm)
4463{
4464 enum pipe pipe;
4465 uint32_t tmp;
4466
4467 for_each_pipe(dev_priv, pipe) {
4468 tmp = I915_READ(VLV_DDL(pipe));
4469
4470 wm->ddl[pipe].primary =
4471 (tmp >> DDL_PLANE_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4472 wm->ddl[pipe].cursor =
4473 (tmp >> DDL_CURSOR_SHIFT) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4474 wm->ddl[pipe].sprite[0] =
4475 (tmp >> DDL_SPRITE_SHIFT(0)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4476 wm->ddl[pipe].sprite[1] =
4477 (tmp >> DDL_SPRITE_SHIFT(1)) & (DDL_PRECISION_HIGH | DRAIN_LATENCY_MASK);
4478 }
4479
4480 tmp = I915_READ(DSPFW1);
4481 wm->sr.plane = _FW_WM(tmp, SR);
4482 wm->pipe[PIPE_B].cursor = _FW_WM(tmp, CURSORB);
4483 wm->pipe[PIPE_B].primary = _FW_WM_VLV(tmp, PLANEB);
4484 wm->pipe[PIPE_A].primary = _FW_WM_VLV(tmp, PLANEA);
4485
4486 tmp = I915_READ(DSPFW2);
4487 wm->pipe[PIPE_A].sprite[1] = _FW_WM_VLV(tmp, SPRITEB);
4488 wm->pipe[PIPE_A].cursor = _FW_WM(tmp, CURSORA);
4489 wm->pipe[PIPE_A].sprite[0] = _FW_WM_VLV(tmp, SPRITEA);
4490
4491 tmp = I915_READ(DSPFW3);
4492 wm->sr.cursor = _FW_WM(tmp, CURSOR_SR);
4493
4494 if (IS_CHERRYVIEW(dev_priv)) {
4495 tmp = I915_READ(DSPFW7_CHV);
4496 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4497 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4498
4499 tmp = I915_READ(DSPFW8_CHV);
4500 wm->pipe[PIPE_C].sprite[1] = _FW_WM_VLV(tmp, SPRITEF);
4501 wm->pipe[PIPE_C].sprite[0] = _FW_WM_VLV(tmp, SPRITEE);
4502
4503 tmp = I915_READ(DSPFW9_CHV);
4504 wm->pipe[PIPE_C].primary = _FW_WM_VLV(tmp, PLANEC);
4505 wm->pipe[PIPE_C].cursor = _FW_WM(tmp, CURSORC);
4506
4507 tmp = I915_READ(DSPHOWM);
4508 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4509 wm->pipe[PIPE_C].sprite[1] |= _FW_WM(tmp, SPRITEF_HI) << 8;
4510 wm->pipe[PIPE_C].sprite[0] |= _FW_WM(tmp, SPRITEE_HI) << 8;
4511 wm->pipe[PIPE_C].primary |= _FW_WM(tmp, PLANEC_HI) << 8;
4512 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4513 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4514 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4515 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4516 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4517 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4518 } else {
4519 tmp = I915_READ(DSPFW7);
4520 wm->pipe[PIPE_B].sprite[1] = _FW_WM_VLV(tmp, SPRITED);
4521 wm->pipe[PIPE_B].sprite[0] = _FW_WM_VLV(tmp, SPRITEC);
4522
4523 tmp = I915_READ(DSPHOWM);
4524 wm->sr.plane |= _FW_WM(tmp, SR_HI) << 9;
4525 wm->pipe[PIPE_B].sprite[1] |= _FW_WM(tmp, SPRITED_HI) << 8;
4526 wm->pipe[PIPE_B].sprite[0] |= _FW_WM(tmp, SPRITEC_HI) << 8;
4527 wm->pipe[PIPE_B].primary |= _FW_WM(tmp, PLANEB_HI) << 8;
4528 wm->pipe[PIPE_A].sprite[1] |= _FW_WM(tmp, SPRITEB_HI) << 8;
4529 wm->pipe[PIPE_A].sprite[0] |= _FW_WM(tmp, SPRITEA_HI) << 8;
4530 wm->pipe[PIPE_A].primary |= _FW_WM(tmp, PLANEA_HI) << 8;
4531 }
4532}
4533
4534#undef _FW_WM
4535#undef _FW_WM_VLV
4536
4537void vlv_wm_get_hw_state(struct drm_device *dev)
4538{
4539 struct drm_i915_private *dev_priv = to_i915(dev);
4540 struct vlv_wm_values *wm = &dev_priv->wm.vlv;
4541 struct intel_plane *plane;
4542 enum pipe pipe;
4543 u32 val;
4544
4545 vlv_read_wm_values(dev_priv, wm);
4546
4547 for_each_intel_plane(dev, plane) {
4548 switch (plane->base.type) {
4549 int sprite;
4550 case DRM_PLANE_TYPE_CURSOR:
4551 plane->wm.fifo_size = 63;
4552 break;
4553 case DRM_PLANE_TYPE_PRIMARY:
4554 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, 0);
4555 break;
4556 case DRM_PLANE_TYPE_OVERLAY:
4557 sprite = plane->plane;
4558 plane->wm.fifo_size = vlv_get_fifo_size(dev, plane->pipe, sprite + 1);
4559 break;
4560 }
4561 }
4562
4563 wm->cxsr = I915_READ(FW_BLC_SELF_VLV) & FW_CSPWRDWNEN;
4564 wm->level = VLV_WM_LEVEL_PM2;
4565
4566 if (IS_CHERRYVIEW(dev_priv)) {
4567 mutex_lock(&dev_priv->rps.hw_lock);
4568
4569 val = vlv_punit_read(dev_priv, PUNIT_REG_DSPFREQ);
4570 if (val & DSP_MAXFIFO_PM5_ENABLE)
4571 wm->level = VLV_WM_LEVEL_PM5;
4572
58590c14
VS		 4573 /*
4574 * If DDR DVFS is disabled in the BIOS, Punit
4575 * will never ack the request. So if that happens
4576 * assume we don't have to enable/disable DDR DVFS
4577 * dynamically. To test that just set the REQ_ACK
4578 * bit to poke the Punit, but don't change the
4579 * HIGH/LOW bits so that we don't actually change
4580 * the current state.
4581 */
6eb1a681 4582 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
58590c14
VS		 4583 val |= FORCE_DDR_FREQ_REQ_ACK;
4584 vlv_punit_write(dev_priv, PUNIT_REG_DDR_SETUP2, val);
4585
4586 if (wait_for((vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2) &
4587 FORCE_DDR_FREQ_REQ_ACK) == 0, 3)) {
4588 DRM_DEBUG_KMS("Punit not acking DDR DVFS request, "
4589 "assuming DDR DVFS is disabled\n");
4590 dev_priv->wm.max_level = VLV_WM_LEVEL_PM5;
4591 } else {
4592 val = vlv_punit_read(dev_priv, PUNIT_REG_DDR_SETUP2);
4593 if ((val & FORCE_DDR_HIGH_FREQ) == 0)
4594 wm->level = VLV_WM_LEVEL_DDR_DVFS;
4595 }
6eb1a681
VS		 4596
4597 mutex_unlock(&dev_priv->rps.hw_lock);
4598 }
4599
4600 for_each_pipe(dev_priv, pipe)
4601 DRM_DEBUG_KMS("Initial watermarks: pipe %c, plane=%d, cursor=%d, sprite0=%d, sprite1=%d\n",
4602 pipe_name(pipe), wm->pipe[pipe].primary, wm->pipe[pipe].cursor,
4603 wm->pipe[pipe].sprite[0], wm->pipe[pipe].sprite[1]);
4604
4605 DRM_DEBUG_KMS("Initial watermarks: SR plane=%d, SR cursor=%d level=%d cxsr=%d\n",
4606 wm->sr.plane, wm->sr.cursor, wm->level, wm->cxsr);
4607}
4608
243e6a44
VS		 4609void ilk_wm_get_hw_state(struct drm_device *dev)
4610{
fac5e23e 4611 struct drm_i915_private *dev_priv = to_i915(dev);
820c1980 4612 struct ilk_wm_values *hw = &dev_priv->wm.hw;
243e6a44
VS		 4613 struct drm_crtc *crtc;
4614
70e1e0ec 4615 for_each_crtc(dev, crtc)
243e6a44
VS		 4616 ilk_pipe_wm_get_hw_state(crtc);
4617
4618 hw->wm_lp[0] = I915_READ(WM1_LP_ILK);
4619 hw->wm_lp[1] = I915_READ(WM2_LP_ILK);
4620 hw->wm_lp[2] = I915_READ(WM3_LP_ILK);
4621
4622 hw->wm_lp_spr[0] = I915_READ(WM1S_LP_ILK);
cfa7698b
VS		 4623 if (INTEL_INFO(dev)->gen >= 7) {
4624 hw->wm_lp_spr[1] = I915_READ(WM2S_LP_IVB);
4625 hw->wm_lp_spr[2] = I915_READ(WM3S_LP_IVB);
4626 }
243e6a44 4627
8652744b 4628 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
ac9545fd
VS		 4629 hw->partitioning = (I915_READ(WM_MISC) & WM_MISC_DATA_PARTITION_5_6) ?
4630 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
fd6b8f43 4631 else if (IS_IVYBRIDGE(dev_priv))
ac9545fd
VS		 4632 hw->partitioning = (I915_READ(DISP_ARB_CTL2) & DISP_DATA_PARTITION_5_6) ?
4633 INTEL_DDB_PART_5_6 : INTEL_DDB_PART_1_2;
243e6a44
VS		 4634
4635 hw->enable_fbc_wm =
4636 !(I915_READ(DISP_ARB_CTL) & DISP_FBC_WM_DIS);
4637}
4638
b445e3b0
ED		 4639/**
4640 * intel_update_watermarks - update FIFO watermark values based on current modes
4641 *
4642 * Calculate watermark values for the various WM regs based on current mode
4643 * and plane configuration.
4644 *
4645 * There are several cases to deal with here:
4646 * - normal (i.e. non-self-refresh)
4647 * - self-refresh (SR) mode
4648 * - lines are large relative to FIFO size (buffer can hold up to 2)
4649 * - lines are small relative to FIFO size (buffer can hold more than 2
4650 * lines), so need to account for TLB latency
4651 *
4652 * The normal calculation is:
4653 * watermark = dotclock * bytes per pixel * latency
4654 * where latency is platform & configuration dependent (we assume pessimal
4655 * values here).
4656 *
4657 * The SR calculation is:
4658 * watermark = (trunc(latency/line time)+1) * surface width *
4659 * bytes per pixel
4660 * where
4661 * line time = htotal / dotclock
4662 * surface width = hdisplay for normal plane and 64 for cursor
4663 * and latency is assumed to be high, as above.
4664 *
4665 * The final value programmed to the register should always be rounded up,
4666 * and include an extra 2 entries to account for clock crossings.
4667 *
4668 * We don't use the sprite, so we can ignore that. And on Crestline we have
4669 * to set the non-SR watermarks to 8.
4670 */
46ba614c 4671void intel_update_watermarks(struct drm_crtc *crtc)
b445e3b0 4672{
fac5e23e 4673 struct drm_i915_private *dev_priv = to_i915(crtc->dev);
b445e3b0
ED		 4674
4675 if (dev_priv->display.update_wm)
46ba614c 4676 dev_priv->display.update_wm(crtc);
b445e3b0
ED		 4677}
4678
e2828914 4679/*
9270388e 4680 * Lock protecting IPS related data structures
9270388e
DV		 4681 */
4682DEFINE_SPINLOCK(mchdev_lock);
4683
4684/* Global for IPS driver to get at the current i915 device. Protected by
4685 * mchdev_lock. */
4686static struct drm_i915_private *i915_mch_dev;
4687
91d14251 4688bool ironlake_set_drps(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4689{
2b4e57bd
ED		 4690 u16 rgvswctl;
4691
9270388e
DV		 4692 assert_spin_locked(&mchdev_lock);
4693
2b4e57bd
ED		 4694 rgvswctl = I915_READ16(MEMSWCTL);
4695 if (rgvswctl & MEMCTL_CMD_STS) {
4696 DRM_DEBUG("gpu busy, RCS change rejected\n");
4697 return false; /* still busy with another command */
4698 }
4699
4700 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
4701 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
4702 I915_WRITE16(MEMSWCTL, rgvswctl);
4703 POSTING_READ16(MEMSWCTL);
4704
4705 rgvswctl |= MEMCTL_CMD_STS;
4706 I915_WRITE16(MEMSWCTL, rgvswctl);
4707
4708 return true;
4709}
4710
91d14251 4711static void ironlake_enable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4712{
84f1b20f 4713 u32 rgvmodectl;
2b4e57bd
ED		 4714 u8 fmax, fmin, fstart, vstart;
4715
9270388e
DV		 4716 spin_lock_irq(&mchdev_lock);
4717
84f1b20f
TU		 4718 rgvmodectl = I915_READ(MEMMODECTL);
4719
2b4e57bd
ED		 4720 /* Enable temp reporting */
4721 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
4722 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
4723
4724 /* 100ms RC evaluation intervals */
4725 I915_WRITE(RCUPEI, 100000);
4726 I915_WRITE(RCDNEI, 100000);
4727
4728 /* Set max/min thresholds to 90ms and 80ms respectively */
4729 I915_WRITE(RCBMAXAVG, 90000);
4730 I915_WRITE(RCBMINAVG, 80000);
4731
4732 I915_WRITE(MEMIHYST, 1);
4733
4734 /* Set up min, max, and cur for interrupt handling */
4735 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
4736 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
4737 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
4738 MEMMODE_FSTART_SHIFT;
4739
616847e7 4740 vstart = (I915_READ(PXVFREQ(fstart)) & PXVFREQ_PX_MASK) >>
2b4e57bd
ED		 4741 PXVFREQ_PX_SHIFT;
4742
20e4d407
DV		 4743 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
4744 dev_priv->ips.fstart = fstart;
2b4e57bd 4745
20e4d407
DV		 4746 dev_priv->ips.max_delay = fstart;
4747 dev_priv->ips.min_delay = fmin;
4748 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 4749
4750 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
4751 fmax, fmin, fstart);
4752
4753 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
4754
4755 /*
4756 * Interrupts will be enabled in ironlake_irq_postinstall
4757 */
4758
4759 I915_WRITE(VIDSTART, vstart);
4760 POSTING_READ(VIDSTART);
4761
4762 rgvmodectl |= MEMMODE_SWMODE_EN;
4763 I915_WRITE(MEMMODECTL, rgvmodectl);
4764
9270388e 4765 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 4766 DRM_ERROR("stuck trying to change perf mode\n");
dd92d8de 4767 mdelay(1);
2b4e57bd 4768
91d14251 4769 ironlake_set_drps(dev_priv, fstart);
2b4e57bd 4770
7d81c3e0
VS		 4771 dev_priv->ips.last_count1 = I915_READ(DMIEC) +
4772 I915_READ(DDREC) + I915_READ(CSIEC);
20e4d407 4773 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
7d81c3e0 4774 dev_priv->ips.last_count2 = I915_READ(GFXEC);
5ed0bdf2 4775 dev_priv->ips.last_time2 = ktime_get_raw_ns();
9270388e
DV		 4776
4777 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4778}
4779
91d14251 4780static void ironlake_disable_drps(struct drm_i915_private *dev_priv)
2b4e57bd 4781{
9270388e
DV		 4782 u16 rgvswctl;
4783
4784 spin_lock_irq(&mchdev_lock);
4785
4786 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 4787
4788 /* Ack interrupts, disable EFC interrupt */
4789 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
4790 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
4791 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
4792 I915_WRITE(DEIIR, DE_PCU_EVENT);
4793 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
4794
4795 /* Go back to the starting frequency */
91d14251 4796 ironlake_set_drps(dev_priv, dev_priv->ips.fstart);
dd92d8de 4797 mdelay(1);
2b4e57bd
ED		 4798 rgvswctl |= MEMCTL_CMD_STS;
4799 I915_WRITE(MEMSWCTL, rgvswctl);
dd92d8de 4800 mdelay(1);
2b4e57bd 4801
9270388e 4802 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 4803}
4804
acbe9475
DV		 4805/* There's a funny hw issue where the hw returns all 0 when reading from
4806 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
4807 * ourselves, instead of doing a rmw cycle (which might result in us clearing
4808 * all limits and the gpu stuck at whatever frequency it is at atm).
4809 */
74ef1173 4810static u32 intel_rps_limits(struct drm_i915_private *dev_priv, u8 val)
2b4e57bd 4811{
7b9e0ae6 4812 u32 limits;
2b4e57bd 4813
20b46e59
DV		 4814 /* Only set the down limit when we've reached the lowest level to avoid
4815 * getting more interrupts, otherwise leave this clear. This prevents a
4816 * race in the hw when coming out of rc6: There's a tiny window where
4817 * the hw runs at the minimal clock before selecting the desired
4818 * frequency, if the down threshold expires in that window we will not
4819 * receive a down interrupt. */
2d1fe073 4820 if (IS_GEN9(dev_priv)) {
74ef1173
AG		 4821 limits = (dev_priv->rps.max_freq_softlimit) << 23;
4822 if (val <= dev_priv->rps.min_freq_softlimit)
4823 limits |= (dev_priv->rps.min_freq_softlimit) << 14;
4824 } else {
4825 limits = dev_priv->rps.max_freq_softlimit << 24;
4826 if (val <= dev_priv->rps.min_freq_softlimit)
4827 limits |= dev_priv->rps.min_freq_softlimit << 16;
4828 }
20b46e59
DV		 4829
4830 return limits;
4831}
4832
dd75fdc8
CW		 4833static void gen6_set_rps_thresholds(struct drm_i915_private *dev_priv, u8 val)
4834{
4835 int new_power;
8a586437
AG		 4836 u32 threshold_up = 0, threshold_down = 0; /* in % */
4837 u32 ei_up = 0, ei_down = 0;
dd75fdc8
CW		 4838
4839 new_power = dev_priv->rps.power;
4840 switch (dev_priv->rps.power) {
4841 case LOW_POWER:
a72b5623
CW		 4842 if (val > dev_priv->rps.efficient_freq + 1 &&
4843 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4844 new_power = BETWEEN;
4845 break;
4846
4847 case BETWEEN:
a72b5623
CW		 4848 if (val <= dev_priv->rps.efficient_freq &&
4849 val < dev_priv->rps.cur_freq)
dd75fdc8 4850 new_power = LOW_POWER;
a72b5623
CW		 4851 else if (val >= dev_priv->rps.rp0_freq &&
4852 val > dev_priv->rps.cur_freq)
dd75fdc8
CW		 4853 new_power = HIGH_POWER;
4854 break;
4855
4856 case HIGH_POWER:
a72b5623
CW		 4857 if (val < (dev_priv->rps.rp1_freq + dev_priv->rps.rp0_freq) >> 1 &&
4858 val < dev_priv->rps.cur_freq)
dd75fdc8
CW		 4859 new_power = BETWEEN;
4860 break;
4861 }
4862 /* Max/min bins are special */
aed242ff 4863 if (val <= dev_priv->rps.min_freq_softlimit)
dd75fdc8 4864 new_power = LOW_POWER;
aed242ff 4865 if (val >= dev_priv->rps.max_freq_softlimit)
dd75fdc8
CW		 4866 new_power = HIGH_POWER;
4867 if (new_power == dev_priv->rps.power)
4868 return;
4869
4870 /* Note the units here are not exactly 1us, but 1280ns. */
4871 switch (new_power) {
4872 case LOW_POWER:
4873 /* Upclock if more than 95% busy over 16ms */
8a586437
AG		 4874 ei_up = 16000;
4875 threshold_up = 95;
dd75fdc8
CW		 4876
4877 /* Downclock if less than 85% busy over 32ms */
8a586437
AG		 4878 ei_down = 32000;
4879 threshold_down = 85;
dd75fdc8
CW		 4880 break;
4881
4882 case BETWEEN:
4883 /* Upclock if more than 90% busy over 13ms */
8a586437
AG		 4884 ei_up = 13000;
4885 threshold_up = 90;
dd75fdc8
CW		 4886
4887 /* Downclock if less than 75% busy over 32ms */
8a586437
AG		 4888 ei_down = 32000;
4889 threshold_down = 75;
dd75fdc8
CW		 4890 break;
4891
4892 case HIGH_POWER:
4893 /* Upclock if more than 85% busy over 10ms */
8a586437
AG		 4894 ei_up = 10000;
4895 threshold_up = 85;
dd75fdc8
CW		 4896
4897 /* Downclock if less than 60% busy over 32ms */
8a586437
AG		 4898 ei_down = 32000;
4899 threshold_down = 60;
dd75fdc8
CW		 4900 break;
4901 }
4902
8a586437 4903 I915_WRITE(GEN6_RP_UP_EI,
a72b5623 4904 GT_INTERVAL_FROM_US(dev_priv, ei_up));
8a586437 4905 I915_WRITE(GEN6_RP_UP_THRESHOLD,
a72b5623
CW		 4906 GT_INTERVAL_FROM_US(dev_priv,
4907 ei_up * threshold_up / 100));
8a586437
AG		 4908
4909 I915_WRITE(GEN6_RP_DOWN_EI,
a72b5623 4910 GT_INTERVAL_FROM_US(dev_priv, ei_down));
8a586437 4911 I915_WRITE(GEN6_RP_DOWN_THRESHOLD,
a72b5623
CW		 4912 GT_INTERVAL_FROM_US(dev_priv,
4913 ei_down * threshold_down / 100));
4914
4915 I915_WRITE(GEN6_RP_CONTROL,
4916 GEN6_RP_MEDIA_TURBO |
4917 GEN6_RP_MEDIA_HW_NORMAL_MODE |
4918 GEN6_RP_MEDIA_IS_GFX |
4919 GEN6_RP_ENABLE |
4920 GEN6_RP_UP_BUSY_AVG |
4921 GEN6_RP_DOWN_IDLE_AVG);
8a586437 4922
dd75fdc8 4923 dev_priv->rps.power = new_power;
8fb55197
CW		 4924 dev_priv->rps.up_threshold = threshold_up;
4925 dev_priv->rps.down_threshold = threshold_down;
dd75fdc8
CW		 4926 dev_priv->rps.last_adj = 0;
4927}
4928
2876ce73
CW		 4929static u32 gen6_rps_pm_mask(struct drm_i915_private *dev_priv, u8 val)
4930{
4931 u32 mask = 0;
4932
4933 if (val > dev_priv->rps.min_freq_softlimit)
6f4b12f8 4934 mask |= GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_DOWN_THRESHOLD | GEN6_PM_RP_DOWN_TIMEOUT;
2876ce73 4935 if (val < dev_priv->rps.max_freq_softlimit)
6f4b12f8 4936 mask |= GEN6_PM_RP_UP_EI_EXPIRED | GEN6_PM_RP_UP_THRESHOLD;
2876ce73 4937
7b3c29f6
CW		 4938 mask &= dev_priv->pm_rps_events;
4939
59d02a1f 4940 return gen6_sanitize_rps_pm_mask(dev_priv, ~mask);
2876ce73
CW		 4941}
4942
b8a5ff8d
JM		 4943/* gen6_set_rps is called to update the frequency request, but should also be
4944 * called when the range (min_delay and max_delay) is modified so that we can
4945 * update the GEN6_RP_INTERRUPT_LIMITS register accordingly. */
dc97997a 4946static void gen6_set_rps(struct drm_i915_private *dev_priv, u8 val)
20b46e59 4947{
23eafea6 4948 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 4949 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1))
23eafea6
SAK		 4950 return;
4951
4fc688ce 4952 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4953 WARN_ON(val > dev_priv->rps.max_freq);
4954 WARN_ON(val < dev_priv->rps.min_freq);
004777cb 4955
eb64cad1
CW		 4956 /* min/max delay may still have been modified so be sure to
4957 * write the limits value.
4958 */
4959 if (val != dev_priv->rps.cur_freq) {
4960 gen6_set_rps_thresholds(dev_priv, val);
b8a5ff8d 4961
dc97997a 4962 if (IS_GEN9(dev_priv))
5704195c
AG		 4963 I915_WRITE(GEN6_RPNSWREQ,
4964 GEN9_FREQUENCY(val));
dc97997a 4965 else if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
eb64cad1
CW		 4966 I915_WRITE(GEN6_RPNSWREQ,
4967 HSW_FREQUENCY(val));
4968 else
4969 I915_WRITE(GEN6_RPNSWREQ,
4970 GEN6_FREQUENCY(val) |
4971 GEN6_OFFSET(0) |
4972 GEN6_AGGRESSIVE_TURBO);
b8a5ff8d 4973 }
7b9e0ae6 4974
7b9e0ae6
CW		 4975 /* Make sure we continue to get interrupts
4976 * until we hit the minimum or maximum frequencies.
4977 */
74ef1173 4978 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, intel_rps_limits(dev_priv, val));
2876ce73 4979 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
7b9e0ae6 4980
d5570a72
BW		 4981 POSTING_READ(GEN6_RPNSWREQ);
4982
b39fb297 4983 dev_priv->rps.cur_freq = val;
0f94592e 4984 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
2b4e57bd
ED		 4985}
4986
dc97997a 4987static void valleyview_set_rps(struct drm_i915_private *dev_priv, u8 val)
ffe02b40 4988{
ffe02b40 4989 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
aed242ff
CW		 4990 WARN_ON(val > dev_priv->rps.max_freq);
4991 WARN_ON(val < dev_priv->rps.min_freq);
ffe02b40 4992
dc97997a 4993 if (WARN_ONCE(IS_CHERRYVIEW(dev_priv) && (val & 1),
ffe02b40
VS		 4994 "Odd GPU freq value\n"))
4995 val &= ~1;
4996
cd25dd5b
D		 4997 I915_WRITE(GEN6_PMINTRMSK, gen6_rps_pm_mask(dev_priv, val));
4998
8fb55197 4999 if (val != dev_priv->rps.cur_freq) {
ffe02b40 5000 vlv_punit_write(dev_priv, PUNIT_REG_GPU_FREQ_REQ, val);
8fb55197
CW		 5001 if (!IS_CHERRYVIEW(dev_priv))
5002 gen6_set_rps_thresholds(dev_priv, val);
5003 }
ffe02b40 5004
ffe02b40
VS		 5005 dev_priv->rps.cur_freq = val;
5006 trace_intel_gpu_freq_change(intel_gpu_freq(dev_priv, val));
5007}
5008
a7f6e231 5009/* vlv_set_rps_idle: Set the frequency to idle, if Gfx clocks are down
76c3552f
D		 5010 *
5011 * * If Gfx is Idle, then
a7f6e231
D		 5012 * 1. Forcewake Media well.
5013 * 2. Request idle freq.
5014 * 3. Release Forcewake of Media well.
76c3552f
D		 5015*/
5016static void vlv_set_rps_idle(struct drm_i915_private *dev_priv)
5017{
aed242ff 5018 u32 val = dev_priv->rps.idle_freq;
5549d25f 5019
aed242ff 5020 if (dev_priv->rps.cur_freq <= val)
76c3552f
D		 5021 return;
5022
a7f6e231
D		 5023 /* Wake up the media well, as that takes a lot less
5024 * power than the Render well. */
5025 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_MEDIA);
dc97997a 5026 valleyview_set_rps(dev_priv, val);
a7f6e231 5027 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_MEDIA);
76c3552f
D		 5028}
5029
43cf3bf0
CW		 5030void gen6_rps_busy(struct drm_i915_private *dev_priv)
5031{
5032 mutex_lock(&dev_priv->rps.hw_lock);
5033 if (dev_priv->rps.enabled) {
5034 if (dev_priv->pm_rps_events & (GEN6_PM_RP_DOWN_EI_EXPIRED | GEN6_PM_RP_UP_EI_EXPIRED))
5035 gen6_rps_reset_ei(dev_priv);
5036 I915_WRITE(GEN6_PMINTRMSK,
5037 gen6_rps_pm_mask(dev_priv, dev_priv->rps.cur_freq));
2b83c4c4 5038
c33d247d
CW		 5039 gen6_enable_rps_interrupts(dev_priv);
5040
2b83c4c4
MW		 5041 /* Ensure we start at the user's desired frequency */
5042 intel_set_rps(dev_priv,
5043 clamp(dev_priv->rps.cur_freq,
5044 dev_priv->rps.min_freq_softlimit,
5045 dev_priv->rps.max_freq_softlimit));
43cf3bf0
CW		 5046 }
5047 mutex_unlock(&dev_priv->rps.hw_lock);
5048}
5049
b29c19b6
CW		 5050void gen6_rps_idle(struct drm_i915_private *dev_priv)
5051{
c33d247d
CW		 5052 /* Flush our bottom-half so that it does not race with us
5053 * setting the idle frequency and so that it is bounded by
5054 * our rpm wakeref. And then disable the interrupts to stop any
5055 * futher RPS reclocking whilst we are asleep.
5056 */
5057 gen6_disable_rps_interrupts(dev_priv);
5058
b29c19b6 5059 mutex_lock(&dev_priv->rps.hw_lock);
c0951f0c 5060 if (dev_priv->rps.enabled) {
dc97997a 5061 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
76c3552f 5062 vlv_set_rps_idle(dev_priv);
7526ed79 5063 else
dc97997a 5064 gen6_set_rps(dev_priv, dev_priv->rps.idle_freq);
c0951f0c 5065 dev_priv->rps.last_adj = 0;
12c100bf
VS		 5066 I915_WRITE(GEN6_PMINTRMSK,
5067 gen6_sanitize_rps_pm_mask(dev_priv, ~0));
c0951f0c 5068 }
8d3afd7d 5069 mutex_unlock(&dev_priv->rps.hw_lock);
1854d5ca 5070
8d3afd7d 5071 spin_lock(&dev_priv->rps.client_lock);
1854d5ca
CW		 5072 while (!list_empty(&dev_priv->rps.clients))
5073 list_del_init(dev_priv->rps.clients.next);
8d3afd7d 5074 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5075}
5076
1854d5ca 5077void gen6_rps_boost(struct drm_i915_private *dev_priv,
e61b9958
CW		 5078 struct intel_rps_client *rps,
5079 unsigned long submitted)
b29c19b6 5080{
8d3afd7d
CW		 5081 /* This is intentionally racy! We peek at the state here, then
5082 * validate inside the RPS worker.
5083 */
67d97da3 5084 if (!(dev_priv->gt.awake &&
8d3afd7d 5085 dev_priv->rps.enabled &&
29ecd78d 5086 dev_priv->rps.cur_freq < dev_priv->rps.boost_freq))
8d3afd7d 5087 return;
43cf3bf0 5088
e61b9958
CW		 5089 /* Force a RPS boost (and don't count it against the client) if
5090 * the GPU is severely congested.
5091 */
d0bc54f2 5092 if (rps && time_after(jiffies, submitted + DRM_I915_THROTTLE_JIFFIES))
e61b9958
CW		 5093 rps = NULL;
5094
8d3afd7d
CW		 5095 spin_lock(&dev_priv->rps.client_lock);
5096 if (rps == NULL || list_empty(&rps->link)) {
5097 spin_lock_irq(&dev_priv->irq_lock);
5098 if (dev_priv->rps.interrupts_enabled) {
5099 dev_priv->rps.client_boost = true;
c33d247d 5100 schedule_work(&dev_priv->rps.work);
8d3afd7d
CW		 5101 }
5102 spin_unlock_irq(&dev_priv->irq_lock);
1854d5ca 5103
2e1b8730
CW		 5104 if (rps != NULL) {
5105 list_add(&rps->link, &dev_priv->rps.clients);
5106 rps->boosts++;
1854d5ca
CW		 5107 } else
5108 dev_priv->rps.boosts++;
c0951f0c 5109 }
8d3afd7d 5110 spin_unlock(&dev_priv->rps.client_lock);
b29c19b6
CW		 5111}
5112
dc97997a 5113void intel_set_rps(struct drm_i915_private *dev_priv, u8 val)
0a073b84 5114{
dc97997a
CW		 5115 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv))
5116 valleyview_set_rps(dev_priv, val);
ffe02b40 5117 else
dc97997a 5118 gen6_set_rps(dev_priv, val);
0a073b84
JB		 5119}
5120
dc97997a 5121static void gen9_disable_rc6(struct drm_i915_private *dev_priv)
20e49366 5122{
20e49366 5123 I915_WRITE(GEN6_RC_CONTROL, 0);
38c23527 5124 I915_WRITE(GEN9_PG_ENABLE, 0);
20e49366
ZW		 5125}
5126
dc97997a 5127static void gen9_disable_rps(struct drm_i915_private *dev_priv)
2030d684 5128{
2030d684
AG		 5129 I915_WRITE(GEN6_RP_CONTROL, 0);
5130}
5131
dc97997a 5132static void gen6_disable_rps(struct drm_i915_private *dev_priv)
d20d4f0c 5133{
d20d4f0c 5134 I915_WRITE(GEN6_RC_CONTROL, 0);
44fc7d5c 5135 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2030d684 5136 I915_WRITE(GEN6_RP_CONTROL, 0);
44fc7d5c
DV		 5137}
5138
dc97997a 5139static void cherryview_disable_rps(struct drm_i915_private *dev_priv)
38807746 5140{
38807746
D		 5141 I915_WRITE(GEN6_RC_CONTROL, 0);
5142}
5143
dc97997a 5144static void valleyview_disable_rps(struct drm_i915_private *dev_priv)
44fc7d5c 5145{
98a2e5f9
D		 5146 /* we're doing forcewake before Disabling RC6,
5147 * This what the BIOS expects when going into suspend */
59bad947 5148 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
98a2e5f9 5149
44fc7d5c 5150 I915_WRITE(GEN6_RC_CONTROL, 0);
d20d4f0c 5151
59bad947 5152 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
d20d4f0c
JB		 5153}
5154
dc97997a 5155static void intel_print_rc6_info(struct drm_i915_private *dev_priv, u32 mode)
dc39fff7 5156{
dc97997a 5157 if (IS_VALLEYVIEW(dev_priv) || IS_CHERRYVIEW(dev_priv)) {
91ca689a
ID		 5158 if (mode & (GEN7_RC_CTL_TO_MODE | GEN6_RC_CTL_EI_MODE(1)))
5159 mode = GEN6_RC_CTL_RC6_ENABLE;
5160 else
5161 mode = 0;
5162 }
dc97997a 5163 if (HAS_RC6p(dev_priv))
b99d49cc
ID		 5164 DRM_DEBUG_DRIVER("Enabling RC6 states: "
5165 "RC6 %s RC6p %s RC6pp %s\n",
5166 onoff(mode & GEN6_RC_CTL_RC6_ENABLE),
5167 onoff(mode & GEN6_RC_CTL_RC6p_ENABLE),
5168 onoff(mode & GEN6_RC_CTL_RC6pp_ENABLE));
58abf1da
RV		 5169
5170 else
b99d49cc
ID		 5171 DRM_DEBUG_DRIVER("Enabling RC6 states: RC6 %s\n",
5172 onoff(mode & GEN6_RC_CTL_RC6_ENABLE));
dc39fff7
BW		 5173}
5174
dc97997a 5175static bool bxt_check_bios_rc6_setup(struct drm_i915_private *dev_priv)
274008e8 5176{
72e96d64 5177 struct i915_ggtt *ggtt = &dev_priv->ggtt;
274008e8
SAK		 5178 bool enable_rc6 = true;
5179 unsigned long rc6_ctx_base;
fc619841
ID		 5180 u32 rc_ctl;
5181 int rc_sw_target;
5182
5183 rc_ctl = I915_READ(GEN6_RC_CONTROL);
5184 rc_sw_target = (I915_READ(GEN6_RC_STATE) & RC_SW_TARGET_STATE_MASK) >>
5185 RC_SW_TARGET_STATE_SHIFT;
5186 DRM_DEBUG_DRIVER("BIOS enabled RC states: "
5187 "HW_CTRL %s HW_RC6 %s SW_TARGET_STATE %x\n",
5188 onoff(rc_ctl & GEN6_RC_CTL_HW_ENABLE),
5189 onoff(rc_ctl & GEN6_RC_CTL_RC6_ENABLE),
5190 rc_sw_target);
274008e8
SAK		 5191
5192 if (!(I915_READ(RC6_LOCATION) & RC6_CTX_IN_DRAM)) {
b99d49cc 5193 DRM_DEBUG_DRIVER("RC6 Base location not set properly.\n");
274008e8
SAK		 5194 enable_rc6 = false;
5195 }
5196
5197 /*
5198 * The exact context size is not known for BXT, so assume a page size
5199 * for this check.
5200 */
5201 rc6_ctx_base = I915_READ(RC6_CTX_BASE) & RC6_CTX_BASE_MASK;
72e96d64
JL		 5202 if (!((rc6_ctx_base >= ggtt->stolen_reserved_base) &&
5203 (rc6_ctx_base + PAGE_SIZE <= ggtt->stolen_reserved_base +
5204 ggtt->stolen_reserved_size))) {
b99d49cc 5205 DRM_DEBUG_DRIVER("RC6 Base address not as expected.\n");
274008e8
SAK		 5206 enable_rc6 = false;
5207 }
5208
5209 if (!(((I915_READ(PWRCTX_MAXCNT_RCSUNIT) & IDLE_TIME_MASK) > 1) &&
5210 ((I915_READ(PWRCTX_MAXCNT_VCSUNIT0) & IDLE_TIME_MASK) > 1) &&
5211 ((I915_READ(PWRCTX_MAXCNT_BCSUNIT) & IDLE_TIME_MASK) > 1) &&
5212 ((I915_READ(PWRCTX_MAXCNT_VECSUNIT) & IDLE_TIME_MASK) > 1))) {
b99d49cc 5213 DRM_DEBUG_DRIVER("Engine Idle wait time not set properly.\n");
274008e8
SAK		 5214 enable_rc6 = false;
5215 }
5216
fc619841
ID		 5217 if (!I915_READ(GEN8_PUSHBUS_CONTROL) ||
5218 !I915_READ(GEN8_PUSHBUS_ENABLE) ||
5219 !I915_READ(GEN8_PUSHBUS_SHIFT)) {
5220 DRM_DEBUG_DRIVER("Pushbus not setup properly.\n");
5221 enable_rc6 = false;
5222 }
5223
5224 if (!I915_READ(GEN6_GFXPAUSE)) {
5225 DRM_DEBUG_DRIVER("GFX pause not setup properly.\n");
5226 enable_rc6 = false;
5227 }
5228
5229 if (!I915_READ(GEN8_MISC_CTRL0)) {
5230 DRM_DEBUG_DRIVER("GPM control not setup properly.\n");
274008e8
SAK		 5231 enable_rc6 = false;
5232 }
5233
5234 return enable_rc6;
5235}
5236
dc97997a 5237int sanitize_rc6_option(struct drm_i915_private *dev_priv, int enable_rc6)
2b4e57bd 5238{
e7d66d89 5239 /* No RC6 before Ironlake and code is gone for ilk. */
dc97997a 5240 if (INTEL_INFO(dev_priv)->gen < 6)
e6069ca8
ID		 5241 return 0;
5242
274008e8
SAK		 5243 if (!enable_rc6)
5244 return 0;
5245
dc97997a 5246 if (IS_BROXTON(dev_priv) && !bxt_check_bios_rc6_setup(dev_priv)) {
274008e8
SAK		 5247 DRM_INFO("RC6 disabled by BIOS\n");
5248 return 0;
5249 }
5250
456470eb 5251 /* Respect the kernel parameter if it is set */
e6069ca8
ID		 5252 if (enable_rc6 >= 0) {
5253 int mask;
5254
dc97997a 5255 if (HAS_RC6p(dev_priv))
e6069ca8
ID		 5256 mask = INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE |
5257 INTEL_RC6pp_ENABLE;
5258 else
5259 mask = INTEL_RC6_ENABLE;
5260
5261 if ((enable_rc6 & mask) != enable_rc6)
b99d49cc
ID		 5262 DRM_DEBUG_DRIVER("Adjusting RC6 mask to %d "
5263 "(requested %d, valid %d)\n",
5264 enable_rc6 & mask, enable_rc6, mask);
e6069ca8
ID		 5265
5266 return enable_rc6 & mask;
5267 }
2b4e57bd 5268
dc97997a 5269 if (IS_IVYBRIDGE(dev_priv))
cca84a1f 5270 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
8bade1ad
BW		 5271
5272 return INTEL_RC6_ENABLE;
2b4e57bd
ED		 5273}
5274
dc97997a 5275static void gen6_init_rps_frequencies(struct drm_i915_private *dev_priv)
3280e8b0
BW		 5276{
5277 /* All of these values are in units of 50MHz */
773ea9a8 5278
93ee2920 5279 /* static values from HW: RP0 > RP1 > RPn (min_freq) */
dc97997a 5280 if (IS_BROXTON(dev_priv)) {
773ea9a8 5281 u32 rp_state_cap = I915_READ(BXT_RP_STATE_CAP);
35040562
BP		 5282 dev_priv->rps.rp0_freq = (rp_state_cap >> 16) & 0xff;
5283 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5284 dev_priv->rps.min_freq = (rp_state_cap >> 0) & 0xff;
5285 } else {
773ea9a8 5286 u32 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
35040562
BP		 5287 dev_priv->rps.rp0_freq = (rp_state_cap >> 0) & 0xff;
5288 dev_priv->rps.rp1_freq = (rp_state_cap >> 8) & 0xff;
5289 dev_priv->rps.min_freq = (rp_state_cap >> 16) & 0xff;
5290 }
3280e8b0 5291 /* hw_max = RP0 until we check for overclocking */
773ea9a8 5292 dev_priv->rps.max_freq = dev_priv->rps.rp0_freq;
3280e8b0 5293
93ee2920 5294 dev_priv->rps.efficient_freq = dev_priv->rps.rp1_freq;
dc97997a
CW		 5295 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv) ||
5296 IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
773ea9a8
CW		 5297 u32 ddcc_status = 0;
5298
5299 if (sandybridge_pcode_read(dev_priv,
5300 HSW_PCODE_DYNAMIC_DUTY_CYCLE_CONTROL,
5301 &ddcc_status) == 0)
93ee2920 5302 dev_priv->rps.efficient_freq =
46efa4ab
TR		 5303 clamp_t(u8,
5304 ((ddcc_status >> 8) & 0xff),
5305 dev_priv->rps.min_freq,
5306 dev_priv->rps.max_freq);
93ee2920
TR		 5307 }
5308
dc97997a 5309 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
c5e0688c 5310 /* Store the frequency values in 16.66 MHZ units, which is
773ea9a8
CW		 5311 * the natural hardware unit for SKL
5312 */
c5e0688c
AG		 5313 dev_priv->rps.rp0_freq *= GEN9_FREQ_SCALER;
5314 dev_priv->rps.rp1_freq *= GEN9_FREQ_SCALER;
5315 dev_priv->rps.min_freq *= GEN9_FREQ_SCALER;
5316 dev_priv->rps.max_freq *= GEN9_FREQ_SCALER;
5317 dev_priv->rps.efficient_freq *= GEN9_FREQ_SCALER;
5318 }
3280e8b0
BW		 5319}
5320
3a45b05c
CW		 5321static void reset_rps(struct drm_i915_private *dev_priv,
5322 void (*set)(struct drm_i915_private *, u8))
5323{
5324 u8 freq = dev_priv->rps.cur_freq;
5325
5326 /* force a reset */
5327 dev_priv->rps.power = -1;
5328 dev_priv->rps.cur_freq = -1;
5329
5330 set(dev_priv, freq);
5331}
5332
b6fef0ef 5333/* See the Gen9_GT_PM_Programming_Guide doc for the below */
dc97997a 5334static void gen9_enable_rps(struct drm_i915_private *dev_priv)
b6fef0ef 5335{
b6fef0ef
JB		 5336 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
5337
23eafea6 5338 /* WaGsvDisableTurbo: Workaround to disable turbo on BXT A* */
dc97997a 5339 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
2030d684
AG		 5340 /*
5341 * BIOS could leave the Hw Turbo enabled, so need to explicitly
5342 * clear out the Control register just to avoid inconsitency
5343 * with debugfs interface, which will show Turbo as enabled
5344 * only and that is not expected by the User after adding the
5345 * WaGsvDisableTurbo. Apart from this there is no problem even
5346 * if the Turbo is left enabled in the Control register, as the
5347 * Up/Down interrupts would remain masked.
5348 */
dc97997a 5349 gen9_disable_rps(dev_priv);
23eafea6
SAK		 5350 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5351 return;
5352 }
5353
0beb059a
AG		 5354 /* Program defaults and thresholds for RPS*/
5355 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5356 GEN9_FREQUENCY(dev_priv->rps.rp1_freq));
5357
5358 /* 1 second timeout*/
5359 I915_WRITE(GEN6_RP_DOWN_TIMEOUT,
5360 GT_INTERVAL_FROM_US(dev_priv, 1000000));
5361
b6fef0ef 5362 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 0xa);
b6fef0ef 5363
0beb059a
AG		 5364 /* Leaning on the below call to gen6_set_rps to program/setup the
5365 * Up/Down EI & threshold registers, as well as the RP_CONTROL,
5366 * RP_INTERRUPT_LIMITS & RPNSWREQ registers */
3a45b05c 5367 reset_rps(dev_priv, gen6_set_rps);
b6fef0ef
JB		 5368
5369 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
5370}
5371
dc97997a 5372static void gen9_enable_rc6(struct drm_i915_private *dev_priv)
20e49366 5373{
e2f80391 5374 struct intel_engine_cs *engine;
3b3f1650 5375 enum intel_engine_id id;
20e49366 5376 uint32_t rc6_mask = 0;
20e49366
ZW		 5377
5378 /* 1a: Software RC state - RC0 */
5379 I915_WRITE(GEN6_RC_STATE, 0);
5380
5381 /* 1b: Get forcewake during program sequence. Although the driver
5382 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5383 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5384
5385 /* 2a: Disable RC states. */
5386 I915_WRITE(GEN6_RC_CONTROL, 0);
5387
5388 /* 2b: Program RC6 thresholds.*/
63a4dec2
SAK		 5389
5390 /* WaRsDoubleRc6WrlWithCoarsePowerGating: Doubling WRL only when CPG is enabled */
dc97997a 5391 if (IS_SKYLAKE(dev_priv))
63a4dec2
SAK		 5392 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 108 << 16);
5393 else
5394 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 54 << 16);
20e49366
ZW		 5395 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5396 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5397 for_each_engine(engine, dev_priv, id)
e2f80391 5398 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
97c322e7 5399
1a3d1898 5400 if (HAS_GUC(dev_priv))
97c322e7
SAK		 5401 I915_WRITE(GUC_MAX_IDLE_COUNT, 0xA);
5402
20e49366 5403 I915_WRITE(GEN6_RC_SLEEP, 0);
20e49366 5404
38c23527
ZW		 5405 /* 2c: Program Coarse Power Gating Policies. */
5406 I915_WRITE(GEN9_MEDIA_PG_IDLE_HYSTERESIS, 25);
5407 I915_WRITE(GEN9_RENDER_PG_IDLE_HYSTERESIS, 25);
5408
20e49366 5409 /* 3a: Enable RC6 */
dc97997a 5410 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
20e49366 5411 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
87ad3212 5412 DRM_INFO("RC6 %s\n", onoff(rc6_mask & GEN6_RC_CTL_RC6_ENABLE));
4ff40a41 5413 /* WaRsUseTimeoutMode:bxt */
9fc736e8 5414 if (IS_BXT_REVID(dev_priv, 0, BXT_REVID_A1)) {
3e7732a0 5415 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us */
e3429cd2
SAK		 5416 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5417 GEN7_RC_CTL_TO_MODE |
5418 rc6_mask);
3e7732a0
SAK		 5419 } else {
5420 I915_WRITE(GEN6_RC6_THRESHOLD, 37500); /* 37.5/125ms per EI */
e3429cd2
SAK		 5421 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5422 GEN6_RC_CTL_EI_MODE(1) |
5423 rc6_mask);
3e7732a0 5424 }
20e49366 5425
cb07bae0
SK		 5426 /*
5427 * 3b: Enable Coarse Power Gating only when RC6 is enabled.
f2d2fe95 5428 * WaRsDisableCoarsePowerGating:skl,bxt - Render/Media PG need to be disabled with RC6.
cb07bae0 5429 */
dc97997a 5430 if (NEEDS_WaRsDisableCoarsePowerGating(dev_priv))
f2d2fe95
SAK		 5431 I915_WRITE(GEN9_PG_ENABLE, 0);
5432 else
5433 I915_WRITE(GEN9_PG_ENABLE, (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ?
5434 (GEN9_RENDER_PG_ENABLE | GEN9_MEDIA_PG_ENABLE) : 0);
38c23527 5435
59bad947 5436 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
20e49366
ZW		 5437}
5438
dc97997a 5439static void gen8_enable_rps(struct drm_i915_private *dev_priv)
6edee7f3 5440{
e2f80391 5441 struct intel_engine_cs *engine;
3b3f1650 5442 enum intel_engine_id id;
93ee2920 5443 uint32_t rc6_mask = 0;
6edee7f3
BW		 5444
5445 /* 1a: Software RC state - RC0 */
5446 I915_WRITE(GEN6_RC_STATE, 0);
5447
5448 /* 1c & 1d: Get forcewake during program sequence. Although the driver
5449 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 5450 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5451
5452 /* 2a: Disable RC states. */
5453 I915_WRITE(GEN6_RC_CONTROL, 0);
5454
6edee7f3
BW		 5455 /* 2b: Program RC6 thresholds.*/
5456 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
5457 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
5458 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
3b3f1650 5459 for_each_engine(engine, dev_priv, id)
e2f80391 5460 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
6edee7f3 5461 I915_WRITE(GEN6_RC_SLEEP, 0);
dc97997a 5462 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5463 I915_WRITE(GEN6_RC6_THRESHOLD, 625); /* 800us/1.28 for TO */
5464 else
5465 I915_WRITE(GEN6_RC6_THRESHOLD, 50000); /* 50/125ms per EI */
6edee7f3
BW		 5466
5467 /* 3: Enable RC6 */
dc97997a 5468 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6edee7f3 5469 rc6_mask = GEN6_RC_CTL_RC6_ENABLE;
dc97997a
CW		 5470 intel_print_rc6_info(dev_priv, rc6_mask);
5471 if (IS_BROADWELL(dev_priv))
0d68b25e
TR		 5472 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5473 GEN7_RC_CTL_TO_MODE |
5474 rc6_mask);
5475 else
5476 I915_WRITE(GEN6_RC_CONTROL, GEN6_RC_CTL_HW_ENABLE |
5477 GEN6_RC_CTL_EI_MODE(1) |
5478 rc6_mask);
6edee7f3
BW		 5479
5480 /* 4 Program defaults and thresholds for RPS*/
f9bdc585
BW		 5481 I915_WRITE(GEN6_RPNSWREQ,
5482 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
5483 I915_WRITE(GEN6_RC_VIDEO_FREQ,
5484 HSW_FREQUENCY(dev_priv->rps.rp1_freq));
7526ed79
DV		 5485 /* NB: Docs say 1s, and 1000000 - which aren't equivalent */
5486 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 100000000 / 128); /* 1 second timeout */
5487
5488 /* Docs recommend 900MHz, and 300 MHz respectively */
5489 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
5490 dev_priv->rps.max_freq_softlimit << 24 |
5491 dev_priv->rps.min_freq_softlimit << 16);
5492
5493 I915_WRITE(GEN6_RP_UP_THRESHOLD, 7600000 / 128); /* 76ms busyness per EI, 90% */
5494 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 31300000 / 128); /* 313ms busyness per EI, 70%*/
5495 I915_WRITE(GEN6_RP_UP_EI, 66000); /* 84.48ms, XXX: random? */
5496 I915_WRITE(GEN6_RP_DOWN_EI, 350000); /* 448ms, XXX: random? */
5497
5498 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6edee7f3
BW		 5499
5500 /* 5: Enable RPS */
7526ed79
DV		 5501 I915_WRITE(GEN6_RP_CONTROL,
5502 GEN6_RP_MEDIA_TURBO |
5503 GEN6_RP_MEDIA_HW_NORMAL_MODE |
5504 GEN6_RP_MEDIA_IS_GFX |
5505 GEN6_RP_ENABLE |
5506 GEN6_RP_UP_BUSY_AVG |
5507 GEN6_RP_DOWN_IDLE_AVG);
5508
5509 /* 6: Ring frequency + overclocking (our driver does this later */
5510
3a45b05c 5511 reset_rps(dev_priv, gen6_set_rps);
7526ed79 5512
59bad947 5513 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
6edee7f3
BW		 5514}
5515
dc97997a 5516static void gen6_enable_rps(struct drm_i915_private *dev_priv)
2b4e57bd 5517{
e2f80391 5518 struct intel_engine_cs *engine;
3b3f1650 5519 enum intel_engine_id id;
99ac9612 5520 u32 rc6vids, rc6_mask = 0;
2b4e57bd 5521 u32 gtfifodbg;
2b4e57bd 5522 int rc6_mode;
b4ac5afc 5523 int ret;
2b4e57bd 5524
4fc688ce 5525 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5526
2b4e57bd
ED		 5527 /* Here begins a magic sequence of register writes to enable
5528 * auto-downclocking.
5529 *
5530 * Perhaps there might be some value in exposing these to
5531 * userspace...
5532 */
5533 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 5534
5535 /* Clear the DBG now so we don't confuse earlier errors */
297b32ec
VS		 5536 gtfifodbg = I915_READ(GTFIFODBG);
5537 if (gtfifodbg) {
2b4e57bd
ED		 5538 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
5539 I915_WRITE(GTFIFODBG, gtfifodbg);
5540 }
5541
59bad947 5542 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5543
5544 /* disable the counters and set deterministic thresholds */
5545 I915_WRITE(GEN6_RC_CONTROL, 0);
5546
5547 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
5548 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
5549 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
5550 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
5551 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
5552
3b3f1650 5553 for_each_engine(engine, dev_priv, id)
e2f80391 5554 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
2b4e57bd
ED		 5555
5556 I915_WRITE(GEN6_RC_SLEEP, 0);
5557 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
dc97997a 5558 if (IS_IVYBRIDGE(dev_priv))
351aa566
SM		 5559 I915_WRITE(GEN6_RC6_THRESHOLD, 125000);
5560 else
5561 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 5562 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 5563 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
5564
5a7dc92a 5565 /* Check if we are enabling RC6 */
dc97997a 5566 rc6_mode = intel_enable_rc6();
2b4e57bd
ED		 5567 if (rc6_mode & INTEL_RC6_ENABLE)
5568 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
5569
5a7dc92a 5570 /* We don't use those on Haswell */
dc97997a 5571 if (!IS_HASWELL(dev_priv)) {
5a7dc92a
ED		 5572 if (rc6_mode & INTEL_RC6p_ENABLE)
5573 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 5574
5a7dc92a
ED		 5575 if (rc6_mode & INTEL_RC6pp_ENABLE)
5576 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
5577 }
2b4e57bd 5578
dc97997a 5579 intel_print_rc6_info(dev_priv, rc6_mask);
2b4e57bd
ED		 5580
5581 I915_WRITE(GEN6_RC_CONTROL,
5582 rc6_mask |
5583 GEN6_RC_CTL_EI_MODE(1) |
5584 GEN6_RC_CTL_HW_ENABLE);
5585
dd75fdc8
CW		 5586 /* Power down if completely idle for over 50ms */
5587 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 50000);
2b4e57bd 5588 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2b4e57bd 5589
42c0526c 5590 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
d060c169 5591 if (ret)
42c0526c 5592 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
d060c169 5593
3a45b05c 5594 reset_rps(dev_priv, gen6_set_rps);
2b4e57bd 5595
31643d54
BW		 5596 rc6vids = 0;
5597 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
dc97997a 5598 if (IS_GEN6(dev_priv) && ret) {
31643d54 5599 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
dc97997a 5600 } else if (IS_GEN6(dev_priv) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
31643d54
BW		 5601 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
5602 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
5603 rc6vids &= 0xffff00;
5604 rc6vids |= GEN6_ENCODE_RC6_VID(450);
5605 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
5606 if (ret)
5607 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
5608 }
5609
59bad947 5610 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
2b4e57bd
ED		 5611}
5612
fb7404e8 5613static void gen6_update_ring_freq(struct drm_i915_private *dev_priv)
2b4e57bd
ED		 5614{
5615 int min_freq = 15;
3ebecd07
CW		 5616 unsigned int gpu_freq;
5617 unsigned int max_ia_freq, min_ring_freq;
4c8c7743 5618 unsigned int max_gpu_freq, min_gpu_freq;
2b4e57bd 5619 int scaling_factor = 180;
eda79642 5620 struct cpufreq_policy *policy;
2b4e57bd 5621
4fc688ce 5622 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 5623
eda79642
BW		 5624 policy = cpufreq_cpu_get(0);
5625 if (policy) {
5626 max_ia_freq = policy->cpuinfo.max_freq;
5627 cpufreq_cpu_put(policy);
5628 } else {
5629 /*
5630 * Default to measured freq if none found, PCU will ensure we
5631 * don't go over
5632 */
2b4e57bd 5633 max_ia_freq = tsc_khz;
eda79642 5634 }
2b4e57bd
ED		 5635
5636 /* Convert from kHz to MHz */
5637 max_ia_freq /= 1000;
5638
153b4b95 5639 min_ring_freq = I915_READ(DCLK) & 0xf;
f6aca45c
BW		 5640 /* convert DDR frequency from units of 266.6MHz to bandwidth */
5641 min_ring_freq = mult_frac(min_ring_freq, 8, 3);
3ebecd07 5642
dc97997a 5643 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5644 /* Convert GT frequency to 50 HZ units */
5645 min_gpu_freq = dev_priv->rps.min_freq / GEN9_FREQ_SCALER;
5646 max_gpu_freq = dev_priv->rps.max_freq / GEN9_FREQ_SCALER;
5647 } else {
5648 min_gpu_freq = dev_priv->rps.min_freq;
5649 max_gpu_freq = dev_priv->rps.max_freq;
5650 }
5651
2b4e57bd
ED		 5652 /*
5653 * For each potential GPU frequency, load a ring frequency we'd like
5654 * to use for memory access. We do this by specifying the IA frequency
5655 * the PCU should use as a reference to determine the ring frequency.
5656 */
4c8c7743
AG		 5657 for (gpu_freq = max_gpu_freq; gpu_freq >= min_gpu_freq; gpu_freq--) {
5658 int diff = max_gpu_freq - gpu_freq;
3ebecd07
CW		 5659 unsigned int ia_freq = 0, ring_freq = 0;
5660
dc97997a 5661 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv)) {
4c8c7743
AG		 5662 /*
5663 * ring_freq = 2 * GT. ring_freq is in 100MHz units
5664 * No floor required for ring frequency on SKL.
5665 */
5666 ring_freq = gpu_freq;
dc97997a 5667 } else if (INTEL_INFO(dev_priv)->gen >= 8) {
46c764d4
BW		 5668 /* max(2 * GT, DDR). NB: GT is 50MHz units */
5669 ring_freq = max(min_ring_freq, gpu_freq);
dc97997a 5670 } else if (IS_HASWELL(dev_priv)) {
f6aca45c 5671 ring_freq = mult_frac(gpu_freq, 5, 4);
3ebecd07
CW		 5672 ring_freq = max(min_ring_freq, ring_freq);
5673 /* leave ia_freq as the default, chosen by cpufreq */
5674 } else {
5675 /* On older processors, there is no separate ring
5676 * clock domain, so in order to boost the bandwidth
5677 * of the ring, we need to upclock the CPU (ia_freq).
5678 *
5679 * For GPU frequencies less than 750MHz,
5680 * just use the lowest ring freq.
5681 */
5682 if (gpu_freq < min_freq)
5683 ia_freq = 800;
5684 else
5685 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
5686 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
5687 }
2b4e57bd 5688
42c0526c
BW		 5689 sandybridge_pcode_write(dev_priv,
5690 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
3ebecd07
CW		 5691 ia_freq << GEN6_PCODE_FREQ_IA_RATIO_SHIFT |
5692 ring_freq << GEN6_PCODE_FREQ_RING_RATIO_SHIFT |
5693 gpu_freq);
2b4e57bd 5694 }
2b4e57bd
ED		 5695}
5696
03af2045 5697static int cherryview_rps_max_freq(struct drm_i915_private *dev_priv)
2b6b3a09
D		 5698{
5699 u32 val, rp0;
5700
5b5929cb 5701 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
2b6b3a09 5702
43b67998 5703 switch (INTEL_INFO(dev_priv)->sseu.eu_total) {
5b5929cb
JN		 5704 case 8:
5705 /* (2 * 4) config */
5706 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS4EU_FUSE_SHIFT);
5707 break;
5708 case 12:
5709 /* (2 * 6) config */
5710 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS6EU_FUSE_SHIFT);
5711 break;
5712 case 16:
5713 /* (2 * 8) config */
5714 default:
5715 /* Setting (2 * 8) Min RP0 for any other combination */
5716 rp0 = (val >> FB_GFX_FMAX_AT_VMAX_2SS8EU_FUSE_SHIFT);
5717 break;
095acd5f 5718 }
5b5929cb
JN		 5719
5720 rp0 = (rp0 & FB_GFX_FREQ_FUSE_MASK);
5721
2b6b3a09
D		 5722 return rp0;
5723}
5724
5725static int cherryview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5726{
5727 u32 val, rpe;
5728
5729 val = vlv_punit_read(dev_priv, PUNIT_GPU_DUTYCYCLE_REG);
5730 rpe = (val >> PUNIT_GPU_DUTYCYCLE_RPE_FREQ_SHIFT) & PUNIT_GPU_DUTYCYCLE_RPE_FREQ_MASK;
5731
5732 return rpe;
5733}
5734
7707df4a
D		 5735static int cherryview_rps_guar_freq(struct drm_i915_private *dev_priv)
5736{
5737 u32 val, rp1;
5738
5b5929cb
JN		 5739 val = vlv_punit_read(dev_priv, FB_GFX_FMAX_AT_VMAX_FUSE);
5740 rp1 = (val & FB_GFX_FREQ_FUSE_MASK);
5741
7707df4a
D		 5742 return rp1;
5743}
5744
f8f2b001
D		 5745static int valleyview_rps_guar_freq(struct drm_i915_private *dev_priv)
5746{
5747 u32 val, rp1;
5748
5749 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
5750
5751 rp1 = (val & FB_GFX_FGUARANTEED_FREQ_FUSE_MASK) >> FB_GFX_FGUARANTEED_FREQ_FUSE_SHIFT;
5752
5753 return rp1;
5754}
5755
03af2045 5756static int valleyview_rps_max_freq(struct drm_i915_private *dev_priv)
0a073b84
JB		 5757{
5758 u32 val, rp0;
5759
64936258 5760 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FREQ_FUSE);
0a073b84
JB		 5761
5762 rp0 = (val & FB_GFX_MAX_FREQ_FUSE_MASK) >> FB_GFX_MAX_FREQ_FUSE_SHIFT;
5763 /* Clamp to max */
5764 rp0 = min_t(u32, rp0, 0xea);
5765
5766 return rp0;
5767}
5768
5769static int valleyview_rps_rpe_freq(struct drm_i915_private *dev_priv)
5770{
5771 u32 val, rpe;
5772
64936258 5773 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_LO);
0a073b84 5774 rpe = (val & FB_FMAX_VMIN_FREQ_LO_MASK) >> FB_FMAX_VMIN_FREQ_LO_SHIFT;
64936258 5775 val = vlv_nc_read(dev_priv, IOSF_NC_FB_GFX_FMAX_FUSE_HI);
0a073b84
JB		 5776 rpe |= (val & FB_FMAX_VMIN_FREQ_HI_MASK) << 5;
5777
5778 return rpe;
5779}
5780
03af2045 5781static int valleyview_rps_min_freq(struct drm_i915_private *dev_priv)
0a073b84 5782{
36146035
ID		 5783 u32 val;
5784
5785 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_LFM) & 0xff;
5786 /*
5787 * According to the BYT Punit GPU turbo HAS 1.1.6.3 the minimum value
5788 * for the minimum frequency in GPLL mode is 0xc1. Contrary to this on
5789 * a BYT-M B0 the above register contains 0xbf. Moreover when setting
5790 * a frequency Punit will not allow values below 0xc0. Clamp it 0xc0
5791 * to make sure it matches what Punit accepts.
5792 */
5793 return max_t(u32, val, 0xc0);
0a073b84
JB		 5794}
5795
ae48434c
ID		 5796/* Check that the pctx buffer wasn't move under us. */
5797static void valleyview_check_pctx(struct drm_i915_private *dev_priv)
5798{
5799 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5800
5801 WARN_ON(pctx_addr != dev_priv->mm.stolen_base +
5802 dev_priv->vlv_pctx->stolen->start);
5803}
5804
38807746
D		 5805
5806/* Check that the pcbr address is not empty. */
5807static void cherryview_check_pctx(struct drm_i915_private *dev_priv)
5808{
5809 unsigned long pctx_addr = I915_READ(VLV_PCBR) & ~4095;
5810
5811 WARN_ON((pctx_addr >> VLV_PCBR_ADDR_SHIFT) == 0);
5812}
5813
dc97997a 5814static void cherryview_setup_pctx(struct drm_i915_private *dev_priv)
38807746 5815{
62106b4f 5816 struct i915_ggtt *ggtt = &dev_priv->ggtt;
72e96d64 5817 unsigned long pctx_paddr, paddr;
38807746
D		 5818 u32 pcbr;
5819 int pctx_size = 32*1024;
5820
38807746
D		 5821 pcbr = I915_READ(VLV_PCBR);
5822 if ((pcbr >> VLV_PCBR_ADDR_SHIFT) == 0) {
ce611ef8 5823 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
38807746 5824 paddr = (dev_priv->mm.stolen_base +
62106b4f 5825 (ggtt->stolen_size - pctx_size));
38807746
D		 5826
5827 pctx_paddr = (paddr & (~4095));
5828 I915_WRITE(VLV_PCBR, pctx_paddr);
5829 }
ce611ef8
VS		 5830
5831 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
38807746
D		 5832}
5833
dc97997a 5834static void valleyview_setup_pctx(struct drm_i915_private *dev_priv)
c9cddffc 5835{
c9cddffc
JB		 5836 struct drm_i915_gem_object *pctx;
5837 unsigned long pctx_paddr;
5838 u32 pcbr;
5839 int pctx_size = 24*1024;
5840
5841 pcbr = I915_READ(VLV_PCBR);
5842 if (pcbr) {
5843 /* BIOS set it up already, grab the pre-alloc'd space */
5844 int pcbr_offset;
5845
5846 pcbr_offset = (pcbr & (~4095)) - dev_priv->mm.stolen_base;
91c8a326 5847 pctx = i915_gem_object_create_stolen_for_preallocated(&dev_priv->drm,
c9cddffc 5848 pcbr_offset,
190d6cd5 5849 I915_GTT_OFFSET_NONE,
c9cddffc
JB		 5850 pctx_size);
5851 goto out;
5852 }
5853
ce611ef8
VS		 5854 DRM_DEBUG_DRIVER("BIOS didn't set up PCBR, fixing up\n");
5855
c9cddffc
JB		 5856 /*
5857 * From the Gunit register HAS:
5858 * The Gfx driver is expected to program this register and ensure
5859 * proper allocation within Gfx stolen memory. For example, this
5860 * register should be programmed such than the PCBR range does not
5861 * overlap with other ranges, such as the frame buffer, protected
5862 * memory, or any other relevant ranges.
5863 */
91c8a326 5864 pctx = i915_gem_object_create_stolen(&dev_priv->drm, pctx_size);
c9cddffc
JB		 5865 if (!pctx) {
5866 DRM_DEBUG("not enough stolen space for PCTX, disabling\n");
ee504898 5867 goto out;
c9cddffc
JB		 5868 }
5869
5870 pctx_paddr = dev_priv->mm.stolen_base + pctx->stolen->start;
5871 I915_WRITE(VLV_PCBR, pctx_paddr);
5872
5873out:
ce611ef8 5874 DRM_DEBUG_DRIVER("PCBR: 0x%08x\n", I915_READ(VLV_PCBR));
c9cddffc
JB		 5875 dev_priv->vlv_pctx = pctx;
5876}
5877
dc97997a 5878static void valleyview_cleanup_pctx(struct drm_i915_private *dev_priv)
ae48434c 5879{
ae48434c
ID		 5880 if (WARN_ON(!dev_priv->vlv_pctx))
5881 return;
5882
34911fd3 5883 i915_gem_object_put_unlocked(dev_priv->vlv_pctx);
ae48434c
ID		 5884 dev_priv->vlv_pctx = NULL;
5885}
5886
c30fec65
VS		 5887static void vlv_init_gpll_ref_freq(struct drm_i915_private *dev_priv)
5888{
5889 dev_priv->rps.gpll_ref_freq =
5890 vlv_get_cck_clock(dev_priv, "GPLL ref",
5891 CCK_GPLL_CLOCK_CONTROL,
5892 dev_priv->czclk_freq);
5893
5894 DRM_DEBUG_DRIVER("GPLL reference freq: %d kHz\n",
5895 dev_priv->rps.gpll_ref_freq);
5896}
5897
dc97997a 5898static void valleyview_init_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5899{
2bb25c17 5900 u32 val;
4e80519e 5901
dc97997a 5902 valleyview_setup_pctx(dev_priv);
4e80519e 5903
c30fec65
VS		 5904 vlv_init_gpll_ref_freq(dev_priv);
5905
2bb25c17
VS		 5906 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
5907 switch ((val >> 6) & 3) {
5908 case 0:
5909 case 1:
5910 dev_priv->mem_freq = 800;
5911 break;
5912 case 2:
5913 dev_priv->mem_freq = 1066;
5914 break;
5915 case 3:
5916 dev_priv->mem_freq = 1333;
5917 break;
5918 }
80b83b62 5919 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5920
4e80519e
ID		 5921 dev_priv->rps.max_freq = valleyview_rps_max_freq(dev_priv);
5922 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5923 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5924 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
4e80519e
ID		 5925 dev_priv->rps.max_freq);
5926
5927 dev_priv->rps.efficient_freq = valleyview_rps_rpe_freq(dev_priv);
5928 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5929 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
4e80519e
ID		 5930 dev_priv->rps.efficient_freq);
5931
f8f2b001
D		 5932 dev_priv->rps.rp1_freq = valleyview_rps_guar_freq(dev_priv);
5933 DRM_DEBUG_DRIVER("RP1(Guar Freq) GPU freq: %d MHz (%u)\n",
7c59a9c1 5934 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
f8f2b001
D		 5935 dev_priv->rps.rp1_freq);
5936
4e80519e
ID		 5937 dev_priv->rps.min_freq = valleyview_rps_min_freq(dev_priv);
5938 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5939 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
4e80519e 5940 dev_priv->rps.min_freq);
4e80519e
ID		 5941}
5942
dc97997a 5943static void cherryview_init_gt_powersave(struct drm_i915_private *dev_priv)
38807746 5944{
2bb25c17 5945 u32 val;
2b6b3a09 5946
dc97997a 5947 cherryview_setup_pctx(dev_priv);
2b6b3a09 5948
c30fec65
VS		 5949 vlv_init_gpll_ref_freq(dev_priv);
5950
a580516d 5951 mutex_lock(&dev_priv->sb_lock);
c6e8f39d 5952 val = vlv_cck_read(dev_priv, CCK_FUSE_REG);
a580516d 5953 mutex_unlock(&dev_priv->sb_lock);
c6e8f39d 5954
2bb25c17 5955 switch ((val >> 2) & 0x7) {
2bb25c17 5956 case 3:
2bb25c17
VS		 5957 dev_priv->mem_freq = 2000;
5958 break;
bfa7df01 5959 default:
2bb25c17
VS		 5960 dev_priv->mem_freq = 1600;
5961 break;
5962 }
80b83b62 5963 DRM_DEBUG_DRIVER("DDR speed: %d MHz\n", dev_priv->mem_freq);
2bb25c17 5964
2b6b3a09
D		 5965 dev_priv->rps.max_freq = cherryview_rps_max_freq(dev_priv);
5966 dev_priv->rps.rp0_freq = dev_priv->rps.max_freq;
5967 DRM_DEBUG_DRIVER("max GPU freq: %d MHz (%u)\n",
7c59a9c1 5968 intel_gpu_freq(dev_priv, dev_priv->rps.max_freq),
2b6b3a09
D		 5969 dev_priv->rps.max_freq);
5970
5971 dev_priv->rps.efficient_freq = cherryview_rps_rpe_freq(dev_priv);
5972 DRM_DEBUG_DRIVER("RPe GPU freq: %d MHz (%u)\n",
7c59a9c1 5973 intel_gpu_freq(dev_priv, dev_priv->rps.efficient_freq),
2b6b3a09
D		 5974 dev_priv->rps.efficient_freq);
5975
7707df4a
D		 5976 dev_priv->rps.rp1_freq = cherryview_rps_guar_freq(dev_priv);
5977 DRM_DEBUG_DRIVER("RP1(Guar) GPU freq: %d MHz (%u)\n",
7c59a9c1 5978 intel_gpu_freq(dev_priv, dev_priv->rps.rp1_freq),
7707df4a
D		 5979 dev_priv->rps.rp1_freq);
5980
5b7c91b7
D		 5981 /* PUnit validated range is only [RPe, RP0] */
5982 dev_priv->rps.min_freq = dev_priv->rps.efficient_freq;
2b6b3a09 5983 DRM_DEBUG_DRIVER("min GPU freq: %d MHz (%u)\n",
7c59a9c1 5984 intel_gpu_freq(dev_priv, dev_priv->rps.min_freq),
2b6b3a09
D		 5985 dev_priv->rps.min_freq);
5986
1c14762d
VS		 5987 WARN_ONCE((dev_priv->rps.max_freq |
5988 dev_priv->rps.efficient_freq |
5989 dev_priv->rps.rp1_freq |
5990 dev_priv->rps.min_freq) & 1,
5991 "Odd GPU freq values\n");
38807746
D		 5992}
5993
dc97997a 5994static void valleyview_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
4e80519e 5995{
dc97997a 5996 valleyview_cleanup_pctx(dev_priv);
4e80519e
ID		 5997}
5998
dc97997a 5999static void cherryview_enable_rps(struct drm_i915_private *dev_priv)
38807746 6000{
e2f80391 6001 struct intel_engine_cs *engine;
3b3f1650 6002 enum intel_engine_id id;
2b6b3a09 6003 u32 gtfifodbg, val, rc6_mode = 0, pcbr;
38807746
D		 6004
6005 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6006
297b32ec
VS		 6007 gtfifodbg = I915_READ(GTFIFODBG) & ~(GT_FIFO_SBDEDICATE_FREE_ENTRY_CHV |
6008 GT_FIFO_FREE_ENTRIES_CHV);
38807746
D		 6009 if (gtfifodbg) {
6010 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6011 gtfifodbg);
6012 I915_WRITE(GTFIFODBG, gtfifodbg);
6013 }
6014
6015 cherryview_check_pctx(dev_priv);
6016
6017 /* 1a & 1b: Get forcewake during program sequence. Although the driver
6018 * hasn't enabled a state yet where we need forcewake, BIOS may have.*/
59bad947 6019 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
38807746 6020
160614a2
VS		 6021 /* Disable RC states. */
6022 I915_WRITE(GEN6_RC_CONTROL, 0);
6023
38807746
D		 6024 /* 2a: Program RC6 thresholds.*/
6025 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16);
6026 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000); /* 12500 * 1280ns */
6027 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25); /* 25 * 1280ns */
6028
3b3f1650 6029 for_each_engine(engine, dev_priv, id)
e2f80391 6030 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
38807746
D		 6031 I915_WRITE(GEN6_RC_SLEEP, 0);
6032
f4f71c7d
D		 6033 /* TO threshold set to 500 us ( 0x186 * 1.28 us) */
6034 I915_WRITE(GEN6_RC6_THRESHOLD, 0x186);
38807746
D		 6035
6036 /* allows RC6 residency counter to work */
6037 I915_WRITE(VLV_COUNTER_CONTROL,
6038 _MASKED_BIT_ENABLE(VLV_COUNT_RANGE_HIGH |
6039 VLV_MEDIA_RC6_COUNT_EN |
6040 VLV_RENDER_RC6_COUNT_EN));
6041
6042 /* For now we assume BIOS is allocating and populating the PCBR */
6043 pcbr = I915_READ(VLV_PCBR);
6044
38807746 6045 /* 3: Enable RC6 */
dc97997a
CW		 6046 if ((intel_enable_rc6() & INTEL_RC6_ENABLE) &&
6047 (pcbr >> VLV_PCBR_ADDR_SHIFT))
af5a75a3 6048 rc6_mode = GEN7_RC_CTL_TO_MODE;
38807746
D		 6049
6050 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
6051
2b6b3a09 6052 /* 4 Program defaults and thresholds for RPS*/
3cbdb48f 6053 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2b6b3a09
D		 6054 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6055 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6056 I915_WRITE(GEN6_RP_UP_EI, 66000);
6057 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6058
6059 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6060
6061 /* 5: Enable RPS */
6062 I915_WRITE(GEN6_RP_CONTROL,
6063 GEN6_RP_MEDIA_HW_NORMAL_MODE |
eb973a5e 6064 GEN6_RP_MEDIA_IS_GFX |
2b6b3a09
D		 6065 GEN6_RP_ENABLE |
6066 GEN6_RP_UP_BUSY_AVG |
6067 GEN6_RP_DOWN_IDLE_AVG);
6068
3ef62342
D		 6069 /* Setting Fixed Bias */
6070 val = VLV_OVERRIDE_EN |
6071 VLV_SOC_TDP_EN |
6072 CHV_BIAS_CPU_50_SOC_50;
6073 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6074
2b6b3a09
D		 6075 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
6076
8d40c3ae
VS		 6077 /* RPS code assumes GPLL is used */
6078 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6079
742f491d 6080 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
2b6b3a09
D		 6081 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6082
3a45b05c 6083 reset_rps(dev_priv, valleyview_set_rps);
2b6b3a09 6084
59bad947 6085 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
38807746
D		 6086}
6087
dc97997a 6088static void valleyview_enable_rps(struct drm_i915_private *dev_priv)
0a073b84 6089{
e2f80391 6090 struct intel_engine_cs *engine;
3b3f1650 6091 enum intel_engine_id id;
2a5913a8 6092 u32 gtfifodbg, val, rc6_mode = 0;
0a073b84
JB		 6093
6094 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
6095
ae48434c
ID		 6096 valleyview_check_pctx(dev_priv);
6097
297b32ec
VS		 6098 gtfifodbg = I915_READ(GTFIFODBG);
6099 if (gtfifodbg) {
f7d85c1e
JB		 6100 DRM_DEBUG_DRIVER("GT fifo had a previous error %x\n",
6101 gtfifodbg);
0a073b84
JB		 6102 I915_WRITE(GTFIFODBG, gtfifodbg);
6103 }
6104
c8d9a590 6105 /* If VLV, Forcewake all wells, else re-direct to regular path */
59bad947 6106 intel_uncore_forcewake_get(dev_priv, FORCEWAKE_ALL);
0a073b84 6107
160614a2
VS		 6108 /* Disable RC states. */
6109 I915_WRITE(GEN6_RC_CONTROL, 0);
6110
cad725fe 6111 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
0a073b84
JB		 6112 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
6113 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
6114 I915_WRITE(GEN6_RP_UP_EI, 66000);
6115 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
6116
6117 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
6118
6119 I915_WRITE(GEN6_RP_CONTROL,
6120 GEN6_RP_MEDIA_TURBO |
6121 GEN6_RP_MEDIA_HW_NORMAL_MODE |
6122 GEN6_RP_MEDIA_IS_GFX |
6123 GEN6_RP_ENABLE |
6124 GEN6_RP_UP_BUSY_AVG |
6125 GEN6_RP_DOWN_IDLE_CONT);
6126
6127 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 0x00280000);
6128 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
6129 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
6130
3b3f1650 6131 for_each_engine(engine, dev_priv, id)
e2f80391 6132 I915_WRITE(RING_MAX_IDLE(engine->mmio_base), 10);
0a073b84 6133
2f0aa304 6134 I915_WRITE(GEN6_RC6_THRESHOLD, 0x557);
0a073b84
JB		 6135
6136 /* allows RC6 residency counter to work */
49798eb2 6137 I915_WRITE(VLV_COUNTER_CONTROL,
31685c25
D		 6138 _MASKED_BIT_ENABLE(VLV_MEDIA_RC0_COUNT_EN |
6139 VLV_RENDER_RC0_COUNT_EN |
49798eb2
JB		 6140 VLV_MEDIA_RC6_COUNT_EN |
6141 VLV_RENDER_RC6_COUNT_EN));
31685c25 6142
dc97997a 6143 if (intel_enable_rc6() & INTEL_RC6_ENABLE)
6b88f295 6144 rc6_mode = GEN7_RC_CTL_TO_MODE | VLV_RC_CTL_CTX_RST_PARALLEL;
dc39fff7 6145
dc97997a 6146 intel_print_rc6_info(dev_priv, rc6_mode);
dc39fff7 6147
a2b23fe0 6148 I915_WRITE(GEN6_RC_CONTROL, rc6_mode);
0a073b84 6149
3ef62342
D		 6150 /* Setting Fixed Bias */
6151 val = VLV_OVERRIDE_EN |
6152 VLV_SOC_TDP_EN |
6153 VLV_BIAS_CPU_125_SOC_875;
6154 vlv_punit_write(dev_priv, VLV_TURBO_SOC_OVERRIDE, val);
6155
64936258 6156 val = vlv_punit_read(dev_priv, PUNIT_REG_GPU_FREQ_STS);
0a073b84 6157
8d40c3ae
VS		 6158 /* RPS code assumes GPLL is used */
6159 WARN_ONCE((val & GPLLENABLE) == 0, "GPLL not enabled\n");
6160
742f491d 6161 DRM_DEBUG_DRIVER("GPLL enabled? %s\n", yesno(val & GPLLENABLE));
0a073b84
JB		 6162 DRM_DEBUG_DRIVER("GPU status: 0x%08x\n", val);
6163
3a45b05c 6164 reset_rps(dev_priv, valleyview_set_rps);
0a073b84 6165
59bad947 6166 intel_uncore_forcewake_put(dev_priv, FORCEWAKE_ALL);
0a073b84
JB		 6167}
6168
dde18883
ED		 6169static unsigned long intel_pxfreq(u32 vidfreq)
6170{
6171 unsigned long freq;
6172 int div = (vidfreq & 0x3f0000) >> 16;
6173 int post = (vidfreq & 0x3000) >> 12;
6174 int pre = (vidfreq & 0x7);
6175
6176 if (!pre)
6177 return 0;
6178
6179 freq = ((div * 133333) / ((1<<post) * pre));
6180
6181 return freq;
6182}
6183
eb48eb00
DV		 6184static const struct cparams {
6185 u16 i;
6186 u16 t;
6187 u16 m;
6188 u16 c;
6189} cparams[] = {
6190 { 1, 1333, 301, 28664 },
6191 { 1, 1066, 294, 24460 },
6192 { 1, 800, 294, 25192 },
6193 { 0, 1333, 276, 27605 },
6194 { 0, 1066, 276, 27605 },
6195 { 0, 800, 231, 23784 },
6196};
6197
f531dcb2 6198static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6199{
6200 u64 total_count, diff, ret;
6201 u32 count1, count2, count3, m = 0, c = 0;
6202 unsigned long now = jiffies_to_msecs(jiffies), diff1;
6203 int i;
6204
02d71956
DV		 6205 assert_spin_locked(&mchdev_lock);
6206
20e4d407 6207 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 6208
6209 /* Prevent division-by-zero if we are asking too fast.
6210 * Also, we don't get interesting results if we are polling
6211 * faster than once in 10ms, so just return the saved value
6212 * in such cases.
6213 */
6214 if (diff1 <= 10)
20e4d407 6215 return dev_priv->ips.chipset_power;
eb48eb00
DV		 6216
6217 count1 = I915_READ(DMIEC);
6218 count2 = I915_READ(DDREC);
6219 count3 = I915_READ(CSIEC);
6220
6221 total_count = count1 + count2 + count3;
6222
6223 /* FIXME: handle per-counter overflow */
20e4d407
DV		 6224 if (total_count < dev_priv->ips.last_count1) {
6225 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 6226 diff += total_count;
6227 } else {
20e4d407 6228 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 6229 }
6230
6231 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 6232 if (cparams[i].i == dev_priv->ips.c_m &&
6233 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 6234 m = cparams[i].m;
6235 c = cparams[i].c;
6236 break;
6237 }
6238 }
6239
6240 diff = div_u64(diff, diff1);
6241 ret = ((m * diff) + c);
6242 ret = div_u64(ret, 10);
6243
20e4d407
DV		 6244 dev_priv->ips.last_count1 = total_count;
6245 dev_priv->ips.last_time1 = now;
eb48eb00 6246
20e4d407 6247 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 6248
6249 return ret;
6250}
6251
f531dcb2
CW		 6252unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
6253{
6254 unsigned long val;
6255
dc97997a 6256 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6257 return 0;
6258
6259 spin_lock_irq(&mchdev_lock);
6260
6261 val = __i915_chipset_val(dev_priv);
6262
6263 spin_unlock_irq(&mchdev_lock);
6264
6265 return val;
6266}
6267
eb48eb00
DV		 6268unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
6269{
6270 unsigned long m, x, b;
6271 u32 tsfs;
6272
6273 tsfs = I915_READ(TSFS);
6274
6275 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
6276 x = I915_READ8(TR1);
6277
6278 b = tsfs & TSFS_INTR_MASK;
6279
6280 return ((m * x) / 127) - b;
6281}
6282
d972d6ee
MK		 6283static int _pxvid_to_vd(u8 pxvid)
6284{
6285 if (pxvid == 0)
6286 return 0;
6287
6288 if (pxvid >= 8 && pxvid < 31)
6289 pxvid = 31;
6290
6291 return (pxvid + 2) * 125;
6292}
6293
6294static u32 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
eb48eb00 6295{
d972d6ee
MK		 6296 const int vd = _pxvid_to_vd(pxvid);
6297 const int vm = vd - 1125;
6298
dc97997a 6299 if (INTEL_INFO(dev_priv)->is_mobile)
d972d6ee
MK		 6300 return vm > 0 ? vm : 0;
6301
6302 return vd;
eb48eb00
DV		 6303}
6304
02d71956 6305static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00 6306{
5ed0bdf2 6307 u64 now, diff, diffms;
eb48eb00
DV		 6308 u32 count;
6309
02d71956 6310 assert_spin_locked(&mchdev_lock);
eb48eb00 6311
5ed0bdf2
TG		 6312 now = ktime_get_raw_ns();
6313 diffms = now - dev_priv->ips.last_time2;
6314 do_div(diffms, NSEC_PER_MSEC);
eb48eb00
DV		 6315
6316 /* Don't divide by 0 */
eb48eb00
DV		 6317 if (!diffms)
6318 return;
6319
6320 count = I915_READ(GFXEC);
6321
20e4d407
DV		 6322 if (count < dev_priv->ips.last_count2) {
6323 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 6324 diff += count;
6325 } else {
20e4d407 6326 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 6327 }
6328
20e4d407
DV		 6329 dev_priv->ips.last_count2 = count;
6330 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 6331
6332 /* More magic constants... */
6333 diff = diff * 1181;
6334 diff = div_u64(diff, diffms * 10);
20e4d407 6335 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 6336}
6337
02d71956
DV		 6338void i915_update_gfx_val(struct drm_i915_private *dev_priv)
6339{
dc97997a 6340 if (INTEL_INFO(dev_priv)->gen != 5)
02d71956
DV		 6341 return;
6342
9270388e 6343 spin_lock_irq(&mchdev_lock);
02d71956
DV		 6344
6345 __i915_update_gfx_val(dev_priv);
6346
9270388e 6347 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 6348}
6349
f531dcb2 6350static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 6351{
6352 unsigned long t, corr, state1, corr2, state2;
6353 u32 pxvid, ext_v;
6354
02d71956
DV		 6355 assert_spin_locked(&mchdev_lock);
6356
616847e7 6357 pxvid = I915_READ(PXVFREQ(dev_priv->rps.cur_freq));
eb48eb00
DV		 6358 pxvid = (pxvid >> 24) & 0x7f;
6359 ext_v = pvid_to_extvid(dev_priv, pxvid);
6360
6361 state1 = ext_v;
6362
6363 t = i915_mch_val(dev_priv);
6364
6365 /* Revel in the empirically derived constants */
6366
6367 /* Correction factor in 1/100000 units */
6368 if (t > 80)
6369 corr = ((t * 2349) + 135940);
6370 else if (t >= 50)
6371 corr = ((t * 964) + 29317);
6372 else /* < 50 */
6373 corr = ((t * 301) + 1004);
6374
6375 corr = corr * ((150142 * state1) / 10000 - 78642);
6376 corr /= 100000;
20e4d407 6377 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 6378
6379 state2 = (corr2 * state1) / 10000;
6380 state2 /= 100; /* convert to mW */
6381
02d71956 6382 __i915_update_gfx_val(dev_priv);
eb48eb00 6383
20e4d407 6384 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 6385}
6386
f531dcb2
CW		 6387unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
6388{
6389 unsigned long val;
6390
dc97997a 6391 if (INTEL_INFO(dev_priv)->gen != 5)
f531dcb2
CW		 6392 return 0;
6393
6394 spin_lock_irq(&mchdev_lock);
6395
6396 val = __i915_gfx_val(dev_priv);
6397
6398 spin_unlock_irq(&mchdev_lock);
6399
6400 return val;
6401}
6402
eb48eb00
DV		 6403/**
6404 * i915_read_mch_val - return value for IPS use
6405 *
6406 * Calculate and return a value for the IPS driver to use when deciding whether
6407 * we have thermal and power headroom to increase CPU or GPU power budget.
6408 */
6409unsigned long i915_read_mch_val(void)
6410{
6411 struct drm_i915_private *dev_priv;
6412 unsigned long chipset_val, graphics_val, ret = 0;
6413
9270388e 6414 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6415 if (!i915_mch_dev)
6416 goto out_unlock;
6417 dev_priv = i915_mch_dev;
6418
f531dcb2
CW		 6419 chipset_val = __i915_chipset_val(dev_priv);
6420 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 6421
6422 ret = chipset_val + graphics_val;
6423
6424out_unlock:
9270388e 6425 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6426
6427 return ret;
6428}
6429EXPORT_SYMBOL_GPL(i915_read_mch_val);
6430
6431/**
6432 * i915_gpu_raise - raise GPU frequency limit
6433 *
6434 * Raise the limit; IPS indicates we have thermal headroom.
6435 */
6436bool i915_gpu_raise(void)
6437{
6438 struct drm_i915_private *dev_priv;
6439 bool ret = true;
6440
9270388e 6441 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6442 if (!i915_mch_dev) {
6443 ret = false;
6444 goto out_unlock;
6445 }
6446 dev_priv = i915_mch_dev;
6447
20e4d407
DV		 6448 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
6449 dev_priv->ips.max_delay--;
eb48eb00
DV		 6450
6451out_unlock:
9270388e 6452 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6453
6454 return ret;
6455}
6456EXPORT_SYMBOL_GPL(i915_gpu_raise);
6457
6458/**
6459 * i915_gpu_lower - lower GPU frequency limit
6460 *
6461 * IPS indicates we're close to a thermal limit, so throttle back the GPU
6462 * frequency maximum.
6463 */
6464bool i915_gpu_lower(void)
6465{
6466 struct drm_i915_private *dev_priv;
6467 bool ret = true;
6468
9270388e 6469 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6470 if (!i915_mch_dev) {
6471 ret = false;
6472 goto out_unlock;
6473 }
6474 dev_priv = i915_mch_dev;
6475
20e4d407
DV		 6476 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
6477 dev_priv->ips.max_delay++;
eb48eb00
DV		 6478
6479out_unlock:
9270388e 6480 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6481
6482 return ret;
6483}
6484EXPORT_SYMBOL_GPL(i915_gpu_lower);
6485
6486/**
6487 * i915_gpu_busy - indicate GPU business to IPS
6488 *
6489 * Tell the IPS driver whether or not the GPU is busy.
6490 */
6491bool i915_gpu_busy(void)
6492{
eb48eb00
DV		 6493 bool ret = false;
6494
9270388e 6495 spin_lock_irq(&mchdev_lock);
dcff85c8
CW		 6496 if (i915_mch_dev)
6497 ret = i915_mch_dev->gt.awake;
9270388e 6498 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6499
6500 return ret;
6501}
6502EXPORT_SYMBOL_GPL(i915_gpu_busy);
6503
6504/**
6505 * i915_gpu_turbo_disable - disable graphics turbo
6506 *
6507 * Disable graphics turbo by resetting the max frequency and setting the
6508 * current frequency to the default.
6509 */
6510bool i915_gpu_turbo_disable(void)
6511{
6512 struct drm_i915_private *dev_priv;
6513 bool ret = true;
6514
9270388e 6515 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 6516 if (!i915_mch_dev) {
6517 ret = false;
6518 goto out_unlock;
6519 }
6520 dev_priv = i915_mch_dev;
6521
20e4d407 6522 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 6523
91d14251 6524 if (!ironlake_set_drps(dev_priv, dev_priv->ips.fstart))
eb48eb00
DV		 6525 ret = false;
6526
6527out_unlock:
9270388e 6528 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6529
6530 return ret;
6531}
6532EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
6533
6534/**
6535 * Tells the intel_ips driver that the i915 driver is now loaded, if
6536 * IPS got loaded first.
6537 *
6538 * This awkward dance is so that neither module has to depend on the
6539 * other in order for IPS to do the appropriate communication of
6540 * GPU turbo limits to i915.
6541 */
6542static void
6543ips_ping_for_i915_load(void)
6544{
6545 void (*link)(void);
6546
6547 link = symbol_get(ips_link_to_i915_driver);
6548 if (link) {
6549 link();
6550 symbol_put(ips_link_to_i915_driver);
6551 }
6552}
6553
6554void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
6555{
02d71956
DV		 6556 /* We only register the i915 ips part with intel-ips once everything is
6557 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 6558 spin_lock_irq(&mchdev_lock);
eb48eb00 6559 i915_mch_dev = dev_priv;
9270388e 6560 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 6561
6562 ips_ping_for_i915_load();
6563}
6564
6565void intel_gpu_ips_teardown(void)
6566{
9270388e 6567 spin_lock_irq(&mchdev_lock);
eb48eb00 6568 i915_mch_dev = NULL;
9270388e 6569 spin_unlock_irq(&mchdev_lock);
eb48eb00 6570}
76c3552f 6571
dc97997a 6572static void intel_init_emon(struct drm_i915_private *dev_priv)
dde18883 6573{
dde18883
ED		 6574 u32 lcfuse;
6575 u8 pxw[16];
6576 int i;
6577
6578 /* Disable to program */
6579 I915_WRITE(ECR, 0);
6580 POSTING_READ(ECR);
6581
6582 /* Program energy weights for various events */
6583 I915_WRITE(SDEW, 0x15040d00);
6584 I915_WRITE(CSIEW0, 0x007f0000);
6585 I915_WRITE(CSIEW1, 0x1e220004);
6586 I915_WRITE(CSIEW2, 0x04000004);
6587
6588 for (i = 0; i < 5; i++)
616847e7 6589 I915_WRITE(PEW(i), 0);
dde18883 6590 for (i = 0; i < 3; i++)
616847e7 6591 I915_WRITE(DEW(i), 0);
dde18883
ED		 6592
6593 /* Program P-state weights to account for frequency power adjustment */
6594 for (i = 0; i < 16; i++) {
616847e7 6595 u32 pxvidfreq = I915_READ(PXVFREQ(i));
dde18883
ED		 6596 unsigned long freq = intel_pxfreq(pxvidfreq);
6597 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
6598 PXVFREQ_PX_SHIFT;
6599 unsigned long val;
6600
6601 val = vid * vid;
6602 val *= (freq / 1000);
6603 val *= 255;
6604 val /= (127*127*900);
6605 if (val > 0xff)
6606 DRM_ERROR("bad pxval: %ld\n", val);
6607 pxw[i] = val;
6608 }
6609 /* Render standby states get 0 weight */
6610 pxw[14] = 0;
6611 pxw[15] = 0;
6612
6613 for (i = 0; i < 4; i++) {
6614 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
6615 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
616847e7 6616 I915_WRITE(PXW(i), val);
dde18883
ED		 6617 }
6618
6619 /* Adjust magic regs to magic values (more experimental results) */
6620 I915_WRITE(OGW0, 0);
6621 I915_WRITE(OGW1, 0);
6622 I915_WRITE(EG0, 0x00007f00);
6623 I915_WRITE(EG1, 0x0000000e);
6624 I915_WRITE(EG2, 0x000e0000);
6625 I915_WRITE(EG3, 0x68000300);
6626 I915_WRITE(EG4, 0x42000000);
6627 I915_WRITE(EG5, 0x00140031);
6628 I915_WRITE(EG6, 0);
6629 I915_WRITE(EG7, 0);
6630
6631 for (i = 0; i < 8; i++)
616847e7 6632 I915_WRITE(PXWL(i), 0);
dde18883
ED		 6633
6634 /* Enable PMON + select events */
6635 I915_WRITE(ECR, 0x80000019);
6636
6637 lcfuse = I915_READ(LCFUSE02);
6638
20e4d407 6639 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 6640}
6641
dc97997a 6642void intel_init_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6643{
b268c699
ID		 6644 /*
6645 * RPM depends on RC6 to save restore the GT HW context, so make RC6 a
6646 * requirement.
6647 */
6648 if (!i915.enable_rc6) {
6649 DRM_INFO("RC6 disabled, disabling runtime PM support\n");
6650 intel_runtime_pm_get(dev_priv);
6651 }
e6069ca8 6652
b5163dbb 6653 mutex_lock(&dev_priv->drm.struct_mutex);
773ea9a8
CW		 6654 mutex_lock(&dev_priv->rps.hw_lock);
6655
6656 /* Initialize RPS limits (for userspace) */
dc97997a
CW		 6657 if (IS_CHERRYVIEW(dev_priv))
6658 cherryview_init_gt_powersave(dev_priv);
6659 else if (IS_VALLEYVIEW(dev_priv))
6660 valleyview_init_gt_powersave(dev_priv);
2a13ae79 6661 else if (INTEL_GEN(dev_priv) >= 6)
773ea9a8
CW		 6662 gen6_init_rps_frequencies(dev_priv);
6663
6664 /* Derive initial user preferences/limits from the hardware limits */
6665 dev_priv->rps.idle_freq = dev_priv->rps.min_freq;
6666 dev_priv->rps.cur_freq = dev_priv->rps.idle_freq;
6667
6668 dev_priv->rps.max_freq_softlimit = dev_priv->rps.max_freq;
6669 dev_priv->rps.min_freq_softlimit = dev_priv->rps.min_freq;
6670
6671 if (IS_HASWELL(dev_priv) || IS_BROADWELL(dev_priv))
6672 dev_priv->rps.min_freq_softlimit =
6673 max_t(int,
6674 dev_priv->rps.efficient_freq,
6675 intel_freq_opcode(dev_priv, 450));
6676
99ac9612
CW		 6677 /* After setting max-softlimit, find the overclock max freq */
6678 if (IS_GEN6(dev_priv) ||
6679 IS_IVYBRIDGE(dev_priv) || IS_HASWELL(dev_priv)) {
6680 u32 params = 0;
6681
6682 sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &params);
6683 if (params & BIT(31)) { /* OC supported */
6684 DRM_DEBUG_DRIVER("Overclocking supported, max: %dMHz, overclock: %dMHz\n",
6685 (dev_priv->rps.max_freq & 0xff) * 50,
6686 (params & 0xff) * 50);
6687 dev_priv->rps.max_freq = params & 0xff;
6688 }
6689 }
6690
29ecd78d
CW		 6691 /* Finally allow us to boost to max by default */
6692 dev_priv->rps.boost_freq = dev_priv->rps.max_freq;
6693
773ea9a8 6694 mutex_unlock(&dev_priv->rps.hw_lock);
b5163dbb 6695 mutex_unlock(&dev_priv->drm.struct_mutex);
54b4f68f
CW		 6696
6697 intel_autoenable_gt_powersave(dev_priv);
ae48434c
ID		 6698}
6699
dc97997a 6700void intel_cleanup_gt_powersave(struct drm_i915_private *dev_priv)
ae48434c 6701{
8dac1e1f 6702 if (IS_VALLEYVIEW(dev_priv))
dc97997a 6703 valleyview_cleanup_gt_powersave(dev_priv);
b268c699
ID		 6704
6705 if (!i915.enable_rc6)
6706 intel_runtime_pm_put(dev_priv);
ae48434c
ID		 6707}
6708
54b4f68f
CW		 6709/**
6710 * intel_suspend_gt_powersave - suspend PM work and helper threads
6711 * @dev_priv: i915 device
6712 *
6713 * We don't want to disable RC6 or other features here, we just want
6714 * to make sure any work we've queued has finished and won't bother
6715 * us while we're suspended.
6716 */
6717void intel_suspend_gt_powersave(struct drm_i915_private *dev_priv)
6718{
6719 if (INTEL_GEN(dev_priv) < 6)
6720 return;
6721
6722 if (cancel_delayed_work_sync(&dev_priv->rps.autoenable_work))
6723 intel_runtime_pm_put(dev_priv);
6724
6725 /* gen6_rps_idle() will be called later to disable interrupts */
6726}
6727
b7137e0c
CW		 6728void intel_sanitize_gt_powersave(struct drm_i915_private *dev_priv)
6729{
6730 dev_priv->rps.enabled = true; /* force disabling */
6731 intel_disable_gt_powersave(dev_priv);
54b4f68f
CW		 6732
6733 gen6_reset_rps_interrupts(dev_priv);
156c7ca0
JB		 6734}
6735
dc97997a 6736void intel_disable_gt_powersave(struct drm_i915_private *dev_priv)
8090c6b9 6737{
b7137e0c
CW		 6738 if (!READ_ONCE(dev_priv->rps.enabled))
6739 return;
e494837a 6740
b7137e0c 6741 mutex_lock(&dev_priv->rps.hw_lock);
e534770a 6742
b7137e0c
CW		 6743 if (INTEL_GEN(dev_priv) >= 9) {
6744 gen9_disable_rc6(dev_priv);
6745 gen9_disable_rps(dev_priv);
6746 } else if (IS_CHERRYVIEW(dev_priv)) {
6747 cherryview_disable_rps(dev_priv);
6748 } else if (IS_VALLEYVIEW(dev_priv)) {
6749 valleyview_disable_rps(dev_priv);
6750 } else if (INTEL_GEN(dev_priv) >= 6) {
6751 gen6_disable_rps(dev_priv);
6752 } else if (IS_IRONLAKE_M(dev_priv)) {
6753 ironlake_disable_drps(dev_priv);
930ebb46 6754 }
b7137e0c
CW		 6755
6756 dev_priv->rps.enabled = false;
6757 mutex_unlock(&dev_priv->rps.hw_lock);
8090c6b9
DV		 6758}
6759
b7137e0c 6760void intel_enable_gt_powersave(struct drm_i915_private *dev_priv)
1a01ab3b 6761{
54b4f68f
CW		 6762 /* We shouldn't be disabling as we submit, so this should be less
6763 * racy than it appears!
6764 */
b7137e0c
CW		 6765 if (READ_ONCE(dev_priv->rps.enabled))
6766 return;
1a01ab3b 6767
b7137e0c
CW		 6768 /* Powersaving is controlled by the host when inside a VM */
6769 if (intel_vgpu_active(dev_priv))
6770 return;
0a073b84 6771
b7137e0c 6772 mutex_lock(&dev_priv->rps.hw_lock);
dc97997a
CW		 6773
6774 if (IS_CHERRYVIEW(dev_priv)) {
6775 cherryview_enable_rps(dev_priv);
6776 } else if (IS_VALLEYVIEW(dev_priv)) {
6777 valleyview_enable_rps(dev_priv);
b7137e0c 6778 } else if (INTEL_GEN(dev_priv) >= 9) {
dc97997a
CW		 6779 gen9_enable_rc6(dev_priv);
6780 gen9_enable_rps(dev_priv);
6781 if (IS_SKYLAKE(dev_priv) || IS_KABYLAKE(dev_priv))
fb7404e8 6782 gen6_update_ring_freq(dev_priv);
dc97997a
CW		 6783 } else if (IS_BROADWELL(dev_priv)) {
6784 gen8_enable_rps(dev_priv);
fb7404e8 6785 gen6_update_ring_freq(dev_priv);
b7137e0c 6786 } else if (INTEL_GEN(dev_priv) >= 6) {
dc97997a 6787 gen6_enable_rps(dev_priv);
fb7404e8 6788 gen6_update_ring_freq(dev_priv);
b7137e0c
CW		 6789 } else if (IS_IRONLAKE_M(dev_priv)) {
6790 ironlake_enable_drps(dev_priv);
6791 intel_init_emon(dev_priv);
0a073b84 6792 }
aed242ff
CW		 6793
6794 WARN_ON(dev_priv->rps.max_freq < dev_priv->rps.min_freq);
6795 WARN_ON(dev_priv->rps.idle_freq > dev_priv->rps.max_freq);
6796
6797 WARN_ON(dev_priv->rps.efficient_freq < dev_priv->rps.min_freq);
6798 WARN_ON(dev_priv->rps.efficient_freq > dev_priv->rps.max_freq);
6799
54b4f68f 6800 dev_priv->rps.enabled = true;
b7137e0c
CW		 6801 mutex_unlock(&dev_priv->rps.hw_lock);
6802}
3cc134e3 6803
54b4f68f
CW		 6804static void __intel_autoenable_gt_powersave(struct work_struct *work)
6805{
6806 struct drm_i915_private *dev_priv =
6807 container_of(work, typeof(*dev_priv), rps.autoenable_work.work);
6808 struct intel_engine_cs *rcs;
6809 struct drm_i915_gem_request *req;
6810
6811 if (READ_ONCE(dev_priv->rps.enabled))
6812 goto out;
6813
3b3f1650 6814 rcs = dev_priv->engine[RCS];
54b4f68f
CW		 6815 if (rcs->last_context)
6816 goto out;
6817
6818 if (!rcs->init_context)
6819 goto out;
6820
6821 mutex_lock(&dev_priv->drm.struct_mutex);
6822
6823 req = i915_gem_request_alloc(rcs, dev_priv->kernel_context);
6824 if (IS_ERR(req))
6825 goto unlock;
6826
6827 if (!i915.enable_execlists && i915_switch_context(req) == 0)
6828 rcs->init_context(req);
6829
6830 /* Mark the device busy, calling intel_enable_gt_powersave() */
6831 i915_add_request_no_flush(req);
6832
6833unlock:
6834 mutex_unlock(&dev_priv->drm.struct_mutex);
6835out:
6836 intel_runtime_pm_put(dev_priv);
6837}
6838
6839void intel_autoenable_gt_powersave(struct drm_i915_private *dev_priv)
6840{
6841 if (READ_ONCE(dev_priv->rps.enabled))
6842 return;
6843
6844 if (IS_IRONLAKE_M(dev_priv)) {
6845 ironlake_enable_drps(dev_priv);
54b4f68f 6846 intel_init_emon(dev_priv);
54b4f68f
CW		 6847 } else if (INTEL_INFO(dev_priv)->gen >= 6) {
6848 /*
6849 * PCU communication is slow and this doesn't need to be
6850 * done at any specific time, so do this out of our fast path
6851 * to make resume and init faster.
6852 *
6853 * We depend on the HW RC6 power context save/restore
6854 * mechanism when entering D3 through runtime PM suspend. So
6855 * disable RPM until RPS/RC6 is properly setup. We can only
6856 * get here via the driver load/system resume/runtime resume
6857 * paths, so the _noresume version is enough (and in case of
6858 * runtime resume it's necessary).
6859 */
6860 if (queue_delayed_work(dev_priv->wq,
6861 &dev_priv->rps.autoenable_work,
6862 round_jiffies_up_relative(HZ)))
6863 intel_runtime_pm_get_noresume(dev_priv);
6864 }
6865}
6866
3107bd48
DV		 6867static void ibx_init_clock_gating(struct drm_device *dev)
6868{
fac5e23e 6869 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48
DV		 6870
6871 /*
6872 * On Ibex Peak and Cougar Point, we need to disable clock
6873 * gating for the panel power sequencer or it will fail to
6874 * start up when no ports are active.
6875 */
6876 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
6877}
6878
0e088b8f
VS		 6879static void g4x_disable_trickle_feed(struct drm_device *dev)
6880{
fac5e23e 6881 struct drm_i915_private *dev_priv = to_i915(dev);
b12ce1d8 6882 enum pipe pipe;
0e088b8f 6883
055e393f 6884 for_each_pipe(dev_priv, pipe) {
0e088b8f
VS		 6885 I915_WRITE(DSPCNTR(pipe),
6886 I915_READ(DSPCNTR(pipe)) |
6887 DISPPLANE_TRICKLE_FEED_DISABLE);
b12ce1d8
VS		 6888
6889 I915_WRITE(DSPSURF(pipe), I915_READ(DSPSURF(pipe)));
6890 POSTING_READ(DSPSURF(pipe));
0e088b8f
VS		 6891 }
6892}
6893
017636cc
VS		 6894static void ilk_init_lp_watermarks(struct drm_device *dev)
6895{
fac5e23e 6896 struct drm_i915_private *dev_priv = to_i915(dev);
017636cc
VS		 6897
6898 I915_WRITE(WM3_LP_ILK, I915_READ(WM3_LP_ILK) & ~WM1_LP_SR_EN);
6899 I915_WRITE(WM2_LP_ILK, I915_READ(WM2_LP_ILK) & ~WM1_LP_SR_EN);
6900 I915_WRITE(WM1_LP_ILK, I915_READ(WM1_LP_ILK) & ~WM1_LP_SR_EN);
6901
6902 /*
6903 * Don't touch WM1S_LP_EN here.
6904 * Doing so could cause underruns.
6905 */
6906}
6907
1fa61106 6908static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0 6909{
fac5e23e 6910 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 6911 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 6912
f1e8fa56
DL		 6913 /*
6914 * Required for FBC
6915 * WaFbcDisableDpfcClockGating:ilk
6916 */
4d47e4f5
DL		 6917 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
6918 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
6919 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6920
6921 I915_WRITE(PCH_3DCGDIS0,
6922 MARIUNIT_CLOCK_GATE_DISABLE |
6923 SVSMUNIT_CLOCK_GATE_DISABLE);
6924 I915_WRITE(PCH_3DCGDIS1,
6925 VFMUNIT_CLOCK_GATE_DISABLE);
6926
6f1d69b0
ED		 6927 /*
6928 * According to the spec the following bits should be set in
6929 * order to enable memory self-refresh
6930 * The bit 22/21 of 0x42004
6931 * The bit 5 of 0x42020
6932 * The bit 15 of 0x45000
6933 */
6934 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6935 (I915_READ(ILK_DISPLAY_CHICKEN2) |
6936 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 6937 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 6938 I915_WRITE(DISP_ARB_CTL,
6939 (I915_READ(DISP_ARB_CTL) |
6940 DISP_FBC_WM_DIS));
017636cc
VS		 6941
6942 ilk_init_lp_watermarks(dev);
6f1d69b0
ED		 6943
6944 /*
6945 * Based on the document from hardware guys the following bits
6946 * should be set unconditionally in order to enable FBC.
6947 * The bit 22 of 0x42000
6948 * The bit 22 of 0x42004
6949 * The bit 7,8,9 of 0x42020.
6950 */
50a0bc90 6951 if (IS_IRONLAKE_M(dev_priv)) {
4bb35334 6952 /* WaFbcAsynchFlipDisableFbcQueue:ilk */
6f1d69b0
ED		 6953 I915_WRITE(ILK_DISPLAY_CHICKEN1,
6954 I915_READ(ILK_DISPLAY_CHICKEN1) |
6955 ILK_FBCQ_DIS);
6956 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6957 I915_READ(ILK_DISPLAY_CHICKEN2) |
6958 ILK_DPARB_GATE);
6f1d69b0
ED		 6959 }
6960
4d47e4f5
DL		 6961 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6962
6f1d69b0
ED		 6963 I915_WRITE(ILK_DISPLAY_CHICKEN2,
6964 I915_READ(ILK_DISPLAY_CHICKEN2) |
6965 ILK_ELPIN_409_SELECT);
6966 I915_WRITE(_3D_CHICKEN2,
6967 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
6968 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374 6969
ecdb4eb7 6970 /* WaDisableRenderCachePipelinedFlush:ilk */
4358a374
DV		 6971 I915_WRITE(CACHE_MODE_0,
6972 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48 6973
4e04632e
AG		 6974 /* WaDisable_RenderCache_OperationalFlush:ilk */
6975 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6976
0e088b8f 6977 g4x_disable_trickle_feed(dev);
bdad2b2f 6978
3107bd48
DV		 6979 ibx_init_clock_gating(dev);
6980}
6981
6982static void cpt_init_clock_gating(struct drm_device *dev)
6983{
fac5e23e 6984 struct drm_i915_private *dev_priv = to_i915(dev);
3107bd48 6985 int pipe;
3f704fa2 6986 uint32_t val;
3107bd48
DV		 6987
6988 /*
6989 * On Ibex Peak and Cougar Point, we need to disable clock
6990 * gating for the panel power sequencer or it will fail to
6991 * start up when no ports are active.
6992 */
cd664078
JB		 6993 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE |
6994 PCH_DPLUNIT_CLOCK_GATE_DISABLE |
6995 PCH_CPUNIT_CLOCK_GATE_DISABLE);
3107bd48
DV		 6996 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
6997 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 6998 /* The below fixes the weird display corruption, a few pixels shifted
6999 * downward, on (only) LVDS of some HP laptops with IVY.
7000 */
055e393f 7001 for_each_pipe(dev_priv, pipe) {
dc4bd2d1
PZ		 7002 val = I915_READ(TRANS_CHICKEN2(pipe));
7003 val |= TRANS_CHICKEN2_TIMING_OVERRIDE;
7004 val &= ~TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
41aa3448 7005 if (dev_priv->vbt.fdi_rx_polarity_inverted)
3f704fa2 7006 val |= TRANS_CHICKEN2_FDI_POLARITY_REVERSED;
dc4bd2d1
PZ		 7007 val &= ~TRANS_CHICKEN2_FRAME_START_DELAY_MASK;
7008 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_COUNTER;
7009 val &= ~TRANS_CHICKEN2_DISABLE_DEEP_COLOR_MODESWITCH;
3f704fa2
PZ		 7010 I915_WRITE(TRANS_CHICKEN2(pipe), val);
7011 }
3107bd48 7012 /* WADP0ClockGatingDisable */
055e393f 7013 for_each_pipe(dev_priv, pipe) {
3107bd48
DV		 7014 I915_WRITE(TRANS_CHICKEN1(pipe),
7015 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
7016 }
6f1d69b0
ED		 7017}
7018
1d7aaa0c
DV		 7019static void gen6_check_mch_setup(struct drm_device *dev)
7020{
fac5e23e 7021 struct drm_i915_private *dev_priv = to_i915(dev);
1d7aaa0c
DV		 7022 uint32_t tmp;
7023
7024 tmp = I915_READ(MCH_SSKPD);
df662a28
DV		 7025 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL)
7026 DRM_DEBUG_KMS("Wrong MCH_SSKPD value: 0x%08x This can cause underruns.\n",
7027 tmp);
1d7aaa0c
DV		 7028}
7029
1fa61106 7030static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0 7031{
fac5e23e 7032 struct drm_i915_private *dev_priv = to_i915(dev);
231e54f6 7033 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 7034
231e54f6 7035 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 7036
7037 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7038 I915_READ(ILK_DISPLAY_CHICKEN2) |
7039 ILK_ELPIN_409_SELECT);
7040
ecdb4eb7 7041 /* WaDisableHiZPlanesWhenMSAAEnabled:snb */
4283908e
DV		 7042 I915_WRITE(_3D_CHICKEN,
7043 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
7044
4e04632e
AG		 7045 /* WaDisable_RenderCache_OperationalFlush:snb */
7046 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7047
8d85d272
VS		 7048 /*
7049 * BSpec recoomends 8x4 when MSAA is used,
7050 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7051 *
7052 * Note that PS/WM thread counts depend on the WIZ hashing
7053 * disable bit, which we don't touch here, but it's good
7054 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
8d85d272
VS		 7055 */
7056 I915_WRITE(GEN6_GT_MODE,
98533251 7057 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
8d85d272 7058
017636cc 7059 ilk_init_lp_watermarks(dev);
6f1d69b0 7060
6f1d69b0 7061 I915_WRITE(CACHE_MODE_0,
50743298 7062 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 7063
7064 I915_WRITE(GEN6_UCGCTL1,
7065 I915_READ(GEN6_UCGCTL1) |
7066 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
7067 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
7068
7069 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
7070 * gating disable must be set. Failure to set it results in
7071 * flickering pixels due to Z write ordering failures after
7072 * some amount of runtime in the Mesa "fire" demo, and Unigine
7073 * Sanctuary and Tropics, and apparently anything else with
7074 * alpha test or pixel discard.
7075 *
7076 * According to the spec, bit 11 (RCCUNIT) must also be set,
7077 * but we didn't debug actual testcases to find it out.
0f846f81 7078 *
ef59318c
VS		 7079 * WaDisableRCCUnitClockGating:snb
7080 * WaDisableRCPBUnitClockGating:snb
6f1d69b0
ED		 7081 */
7082 I915_WRITE(GEN6_UCGCTL2,
7083 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
7084 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
7085
5eb146dd 7086 /* WaStripsFansDisableFastClipPerformanceFix:snb */
743b57d8
VS		 7087 I915_WRITE(_3D_CHICKEN3,
7088 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL));
6f1d69b0 7089
e927ecde
VS		 7090 /*
7091 * Bspec says:
7092 * "This bit must be set if 3DSTATE_CLIP clip mode is set to normal and
7093 * 3DSTATE_SF number of SF output attributes is more than 16."
7094 */
7095 I915_WRITE(_3D_CHICKEN3,
7096 _MASKED_BIT_ENABLE(_3D_CHICKEN3_SF_DISABLE_PIPELINED_ATTR_FETCH));
7097
6f1d69b0
ED		 7098 /*
7099 * According to the spec the following bits should be
7100 * set in order to enable memory self-refresh and fbc:
7101 * The bit21 and bit22 of 0x42000
7102 * The bit21 and bit22 of 0x42004
7103 * The bit5 and bit7 of 0x42020
7104 * The bit14 of 0x70180
7105 * The bit14 of 0x71180
4bb35334
DL		 7106 *
7107 * WaFbcAsynchFlipDisableFbcQueue:snb
6f1d69b0
ED		 7108 */
7109 I915_WRITE(ILK_DISPLAY_CHICKEN1,
7110 I915_READ(ILK_DISPLAY_CHICKEN1) |
7111 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
7112 I915_WRITE(ILK_DISPLAY_CHICKEN2,
7113 I915_READ(ILK_DISPLAY_CHICKEN2) |
7114 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 7115 I915_WRITE(ILK_DSPCLK_GATE_D,
7116 I915_READ(ILK_DSPCLK_GATE_D) |
7117 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
7118 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 7119
0e088b8f 7120 g4x_disable_trickle_feed(dev);
f8f2ac9a 7121
3107bd48 7122 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7123
7124 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7125}
7126
7127static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
7128{
7129 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
7130
3aad9059 7131 /*
46680e0a 7132 * WaVSThreadDispatchOverride:ivb,vlv
3aad9059
VS		 7133 *
7134 * This actually overrides the dispatch
7135 * mode for all thread types.
7136 */
6f1d69b0
ED		 7137 reg &= ~GEN7_FF_SCHED_MASK;
7138 reg |= GEN7_FF_TS_SCHED_HW;
7139 reg |= GEN7_FF_VS_SCHED_HW;
7140 reg |= GEN7_FF_DS_SCHED_HW;
7141
7142 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
7143}
7144
17a303ec
PZ		 7145static void lpt_init_clock_gating(struct drm_device *dev)
7146{
fac5e23e 7147 struct drm_i915_private *dev_priv = to_i915(dev);
17a303ec
PZ		 7148
7149 /*
7150 * TODO: this bit should only be enabled when really needed, then
7151 * disabled when not needed anymore in order to save power.
7152 */
4f8036a2 7153 if (HAS_PCH_LPT_LP(dev_priv))
17a303ec
PZ		 7154 I915_WRITE(SOUTH_DSPCLK_GATE_D,
7155 I915_READ(SOUTH_DSPCLK_GATE_D) |
7156 PCH_LP_PARTITION_LEVEL_DISABLE);
0a790cdb
PZ		 7157
7158 /* WADPOClockGatingDisable:hsw */
36c0d0cf
VS		 7159 I915_WRITE(TRANS_CHICKEN1(PIPE_A),
7160 I915_READ(TRANS_CHICKEN1(PIPE_A)) |
0a790cdb 7161 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
17a303ec
PZ		 7162}
7163
7d708ee4
ID		 7164static void lpt_suspend_hw(struct drm_device *dev)
7165{
fac5e23e 7166 struct drm_i915_private *dev_priv = to_i915(dev);
7d708ee4 7167
4f8036a2 7168 if (HAS_PCH_LPT_LP(dev_priv)) {
7d708ee4
ID		 7169 uint32_t val = I915_READ(SOUTH_DSPCLK_GATE_D);
7170
7171 val &= ~PCH_LP_PARTITION_LEVEL_DISABLE;
7172 I915_WRITE(SOUTH_DSPCLK_GATE_D, val);
7173 }
7174}
7175
450174fe
ID		 7176static void gen8_set_l3sqc_credits(struct drm_i915_private *dev_priv,
7177 int general_prio_credits,
7178 int high_prio_credits)
7179{
7180 u32 misccpctl;
7181
7182 /* WaTempDisableDOPClkGating:bdw */
7183 misccpctl = I915_READ(GEN7_MISCCPCTL);
7184 I915_WRITE(GEN7_MISCCPCTL, misccpctl & ~GEN7_DOP_CLOCK_GATE_ENABLE);
7185
7186 I915_WRITE(GEN8_L3SQCREG1,
7187 L3_GENERAL_PRIO_CREDITS(general_prio_credits) |
7188 L3_HIGH_PRIO_CREDITS(high_prio_credits));
7189
7190 /*
7191 * Wait at least 100 clocks before re-enabling clock gating.
7192 * See the definition of L3SQCREG1 in BSpec.
7193 */
7194 POSTING_READ(GEN8_L3SQCREG1);
7195 udelay(1);
7196 I915_WRITE(GEN7_MISCCPCTL, misccpctl);
7197}
7198
9498dba7
MK		 7199static void kabylake_init_clock_gating(struct drm_device *dev)
7200{
9146f308 7201 struct drm_i915_private *dev_priv = dev->dev_private;
9498dba7 7202
b033bb6d 7203 gen9_init_clock_gating(dev);
9498dba7
MK		 7204
7205 /* WaDisableSDEUnitClockGating:kbl */
7206 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7207 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7208 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
8aeb7f62
MK		 7209
7210 /* WaDisableGamClockGating:kbl */
7211 if (IS_KBL_REVID(dev_priv, 0, KBL_REVID_B0))
7212 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7213 GEN6_GAMUNIT_CLOCK_GATE_DISABLE);
031cd8c8
MK		 7214
7215 /* WaFbcNukeOnHostModify:kbl */
7216 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7217 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
9498dba7
MK		 7218}
7219
dc00b6a0
DV		 7220static void skylake_init_clock_gating(struct drm_device *dev)
7221{
c584e2d3 7222 struct drm_i915_private *dev_priv = dev->dev_private;
44fff99f 7223
b033bb6d 7224 gen9_init_clock_gating(dev);
44fff99f
MK		 7225
7226 /* WAC6entrylatency:skl */
7227 I915_WRITE(FBC_LLC_READ_CTRL, I915_READ(FBC_LLC_READ_CTRL) |
7228 FBC_LLC_FULLY_OPEN);
031cd8c8
MK		 7229
7230 /* WaFbcNukeOnHostModify:skl */
7231 I915_WRITE(ILK_DPFC_CHICKEN, I915_READ(ILK_DPFC_CHICKEN) |
7232 ILK_DPFC_NUKE_ON_ANY_MODIFICATION);
dc00b6a0
DV		 7233}
7234
47c2bd97 7235static void broadwell_init_clock_gating(struct drm_device *dev)
1020a5c2 7236{
fac5e23e 7237 struct drm_i915_private *dev_priv = to_i915(dev);
07d27e20 7238 enum pipe pipe;
1020a5c2 7239
7ad0dbab 7240 ilk_init_lp_watermarks(dev);
50ed5fbd 7241
ab57fff1 7242 /* WaSwitchSolVfFArbitrationPriority:bdw */
50ed5fbd 7243 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
fe4ab3ce 7244
ab57fff1 7245 /* WaPsrDPAMaskVBlankInSRD:bdw */
fe4ab3ce
BW		 7246 I915_WRITE(CHICKEN_PAR1_1,
7247 I915_READ(CHICKEN_PAR1_1) | DPA_MASK_VBLANK_SRD);
7248
ab57fff1 7249 /* WaPsrDPRSUnmaskVBlankInSRD:bdw */
055e393f 7250 for_each_pipe(dev_priv, pipe) {
07d27e20 7251 I915_WRITE(CHICKEN_PIPESL_1(pipe),
c7c65622 7252 I915_READ(CHICKEN_PIPESL_1(pipe)) |
8f670bb1 7253 BDW_DPRS_MASK_VBLANK_SRD);
fe4ab3ce 7254 }
63801f21 7255
ab57fff1
BW		 7256 /* WaVSRefCountFullforceMissDisable:bdw */
7257 /* WaDSRefCountFullforceMissDisable:bdw */
7258 I915_WRITE(GEN7_FF_THREAD_MODE,
7259 I915_READ(GEN7_FF_THREAD_MODE) &
7260 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
36075a4c 7261
295e8bb7
VS		 7262 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7263 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
4f1ca9e9
VS		 7264
7265 /* WaDisableSDEUnitClockGating:bdw */
7266 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7267 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
5d708680 7268
450174fe
ID		 7269 /* WaProgramL3SqcReg1Default:bdw */
7270 gen8_set_l3sqc_credits(dev_priv, 30, 2);
4d487cff 7271
6d50b065
VS		 7272 /*
7273 * WaGttCachingOffByDefault:bdw
7274 * GTT cache may not work with big pages, so if those
7275 * are ever enabled GTT cache may need to be disabled.
7276 */
7277 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
7278
17e0adf0
MK		 7279 /* WaKVMNotificationOnConfigChange:bdw */
7280 I915_WRITE(CHICKEN_PAR2_1, I915_READ(CHICKEN_PAR2_1)
7281 | KVM_CONFIG_CHANGE_NOTIFICATION_SELECT);
7282
89d6b2b8 7283 lpt_init_clock_gating(dev);
1020a5c2
BW		 7284}
7285
cad2a2d7
ED		 7286static void haswell_init_clock_gating(struct drm_device *dev)
7287{
fac5e23e 7288 struct drm_i915_private *dev_priv = to_i915(dev);
cad2a2d7 7289
017636cc 7290 ilk_init_lp_watermarks(dev);
cad2a2d7 7291
f3fc4884
FJ		 7292 /* L3 caching of data atomics doesn't work -- disable it. */
7293 I915_WRITE(HSW_SCRATCH1, HSW_SCRATCH1_L3_DATA_ATOMICS_DISABLE);
7294 I915_WRITE(HSW_ROW_CHICKEN3,
7295 _MASKED_BIT_ENABLE(HSW_ROW_CHICKEN3_L3_GLOBAL_ATOMICS_DISABLE));
7296
ecdb4eb7 7297 /* This is required by WaCatErrorRejectionIssue:hsw */
cad2a2d7
ED		 7298 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7299 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7300 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7301
e36ea7ff
VS		 7302 /* WaVSRefCountFullforceMissDisable:hsw */
7303 I915_WRITE(GEN7_FF_THREAD_MODE,
7304 I915_READ(GEN7_FF_THREAD_MODE) & ~GEN7_FF_VS_REF_CNT_FFME);
cad2a2d7 7305
4e04632e
AG		 7306 /* WaDisable_RenderCache_OperationalFlush:hsw */
7307 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7308
fe27c606
CW		 7309 /* enable HiZ Raw Stall Optimization */
7310 I915_WRITE(CACHE_MODE_0_GEN7,
7311 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7312
ecdb4eb7 7313 /* WaDisable4x2SubspanOptimization:hsw */
cad2a2d7
ED		 7314 I915_WRITE(CACHE_MODE_1,
7315 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 7316
a12c4967
VS		 7317 /*
7318 * BSpec recommends 8x4 when MSAA is used,
7319 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7320 *
7321 * Note that PS/WM thread counts depend on the WIZ hashing
7322 * disable bit, which we don't touch here, but it's good
7323 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a12c4967
VS		 7324 */
7325 I915_WRITE(GEN7_GT_MODE,
98533251 7326 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a12c4967 7327
94411593
KG		 7328 /* WaSampleCChickenBitEnable:hsw */
7329 I915_WRITE(HALF_SLICE_CHICKEN3,
7330 _MASKED_BIT_ENABLE(HSW_SAMPLE_C_PERFORMANCE));
7331
ecdb4eb7 7332 /* WaSwitchSolVfFArbitrationPriority:hsw */
e3dff585
BW		 7333 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
7334
90a88643
PZ		 7335 /* WaRsPkgCStateDisplayPMReq:hsw */
7336 I915_WRITE(CHICKEN_PAR1_1,
7337 I915_READ(CHICKEN_PAR1_1) | FORCE_ARB_IDLE_PLANES);
1544d9d5 7338
17a303ec 7339 lpt_init_clock_gating(dev);
cad2a2d7
ED		 7340}
7341
1fa61106 7342static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0 7343{
fac5e23e 7344 struct drm_i915_private *dev_priv = to_i915(dev);
20848223 7345 uint32_t snpcr;
6f1d69b0 7346
017636cc 7347 ilk_init_lp_watermarks(dev);
6f1d69b0 7348
231e54f6 7349 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 7350
ecdb4eb7 7351 /* WaDisableEarlyCull:ivb */
87f8020e
JB		 7352 I915_WRITE(_3D_CHICKEN3,
7353 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7354
ecdb4eb7 7355 /* WaDisableBackToBackFlipFix:ivb */
6f1d69b0
ED		 7356 I915_WRITE(IVB_CHICKEN3,
7357 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7358 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7359
ecdb4eb7 7360 /* WaDisablePSDDualDispatchEnable:ivb */
50a0bc90 7361 if (IS_IVB_GT1(dev_priv))
12f3382b
JB		 7362 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
7363 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7364
4e04632e
AG		 7365 /* WaDisable_RenderCache_OperationalFlush:ivb */
7366 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7367
ecdb4eb7 7368 /* Apply the WaDisableRHWOOptimizationForRenderHang:ivb workaround. */
6f1d69b0
ED		 7369 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
7370 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
7371
ecdb4eb7 7372 /* WaApplyL3ControlAndL3ChickenMode:ivb */
6f1d69b0
ED		 7373 I915_WRITE(GEN7_L3CNTLREG1,
7374 GEN7_WA_FOR_GEN7_L3_CONTROL);
7375 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976 7376 GEN7_WA_L3_CHICKEN_MODE);
50a0bc90 7377 if (IS_IVB_GT1(dev_priv))
8ab43976
JB		 7378 I915_WRITE(GEN7_ROW_CHICKEN2,
7379 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2
VS		 7380 else {
7381 /* must write both registers */
7382 I915_WRITE(GEN7_ROW_CHICKEN2,
7383 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
8ab43976
JB		 7384 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
7385 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
412236c2 7386 }
6f1d69b0 7387
ecdb4eb7 7388 /* WaForceL3Serialization:ivb */
61939d97
JB		 7389 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7390 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7391
1b80a19a 7392 /*
0f846f81 7393 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7394 * This implements the WaDisableRCZUnitClockGating:ivb workaround.
0f846f81
JB		 7395 */
7396 I915_WRITE(GEN6_UCGCTL2,
28acf3b2 7397 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7398
ecdb4eb7 7399 /* This is required by WaCatErrorRejectionIssue:ivb */
6f1d69b0
ED		 7400 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7401 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7402 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7403
0e088b8f 7404 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7405
7406 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f 7407
22721343
CW		 7408 if (0) { /* causes HiZ corruption on ivb:gt1 */
7409 /* enable HiZ Raw Stall Optimization */
7410 I915_WRITE(CACHE_MODE_0_GEN7,
7411 _MASKED_BIT_DISABLE(HIZ_RAW_STALL_OPT_DISABLE));
7412 }
116f2b6d 7413
ecdb4eb7 7414 /* WaDisable4x2SubspanOptimization:ivb */
97e1930f
DV		 7415 I915_WRITE(CACHE_MODE_1,
7416 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223 7417
a607c1a4
VS		 7418 /*
7419 * BSpec recommends 8x4 when MSAA is used,
7420 * however in practice 16x4 seems fastest.
c5c98a58
VS		 7421 *
7422 * Note that PS/WM thread counts depend on the WIZ hashing
7423 * disable bit, which we don't touch here, but it's good
7424 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
a607c1a4
VS		 7425 */
7426 I915_WRITE(GEN7_GT_MODE,
98533251 7427 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
a607c1a4 7428
20848223
BW		 7429 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
7430 snpcr &= ~GEN6_MBC_SNPCR_MASK;
7431 snpcr |= GEN6_MBC_SNPCR_MED;
7432 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48 7433
6e266956 7434 if (!HAS_PCH_NOP(dev_priv))
ab5c608b 7435 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 7436
7437 gen6_check_mch_setup(dev);
6f1d69b0
ED		 7438}
7439
1fa61106 7440static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0 7441{
fac5e23e 7442 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7443
ecdb4eb7 7444 /* WaDisableEarlyCull:vlv */
87f8020e
JB		 7445 I915_WRITE(_3D_CHICKEN3,
7446 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
7447
ecdb4eb7 7448 /* WaDisableBackToBackFlipFix:vlv */
6f1d69b0
ED		 7449 I915_WRITE(IVB_CHICKEN3,
7450 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
7451 CHICKEN3_DGMG_DONE_FIX_DISABLE);
7452
fad7d36e 7453 /* WaPsdDispatchEnable:vlv */
ecdb4eb7 7454 /* WaDisablePSDDualDispatchEnable:vlv */
12f3382b 7455 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 7456 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
7457 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 7458
4e04632e
AG		 7459 /* WaDisable_RenderCache_OperationalFlush:vlv */
7460 I915_WRITE(CACHE_MODE_0_GEN7, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7461
ecdb4eb7 7462 /* WaForceL3Serialization:vlv */
61939d97
JB		 7463 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
7464 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
7465
ecdb4eb7 7466 /* WaDisableDopClockGating:vlv */
8ab43976
JB		 7467 I915_WRITE(GEN7_ROW_CHICKEN2,
7468 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
7469
ecdb4eb7 7470 /* This is required by WaCatErrorRejectionIssue:vlv */
6f1d69b0
ED		 7471 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
7472 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
7473 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
7474
46680e0a
VS		 7475 gen7_setup_fixed_func_scheduler(dev_priv);
7476
3c0edaeb 7477 /*
0f846f81 7478 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
ecdb4eb7 7479 * This implements the WaDisableRCZUnitClockGating:vlv workaround.
0f846f81
JB		 7480 */
7481 I915_WRITE(GEN6_UCGCTL2,
3c0edaeb 7482 GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
0f846f81 7483
c98f5062
AG		 7484 /* WaDisableL3Bank2xClockGate:vlv
7485 * Disabling L3 clock gating- MMIO 940c[25] = 1
7486 * Set bit 25, to disable L3_BANK_2x_CLK_GATING */
7487 I915_WRITE(GEN7_UCGCTL4,
7488 I915_READ(GEN7_UCGCTL4) | GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
e3f33d46 7489
afd58e79
VS		 7490 /*
7491 * BSpec says this must be set, even though
7492 * WaDisable4x2SubspanOptimization isn't listed for VLV.
7493 */
6b26c86d
DV		 7494 I915_WRITE(CACHE_MODE_1,
7495 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 7496
da2518f9
VS		 7497 /*
7498 * BSpec recommends 8x4 when MSAA is used,
7499 * however in practice 16x4 seems fastest.
7500 *
7501 * Note that PS/WM thread counts depend on the WIZ hashing
7502 * disable bit, which we don't touch here, but it's good
7503 * to keep in mind (see 3DSTATE_PS and 3DSTATE_WM).
7504 */
7505 I915_WRITE(GEN7_GT_MODE,
7506 _MASKED_FIELD(GEN6_WIZ_HASHING_MASK, GEN6_WIZ_HASHING_16x4));
7507
031994ee
VS		 7508 /*
7509 * WaIncreaseL3CreditsForVLVB0:vlv
7510 * This is the hardware default actually.
7511 */
7512 I915_WRITE(GEN7_L3SQCREG1, VLV_B0_WA_L3SQCREG1_VALUE);
7513
2d809570 7514 /*
ecdb4eb7 7515 * WaDisableVLVClockGating_VBIIssue:vlv
2d809570
JB		 7516 * Disable clock gating on th GCFG unit to prevent a delay
7517 * in the reporting of vblank events.
7518 */
7a0d1eed 7519 I915_WRITE(VLV_GUNIT_CLOCK_GATE, GCFG_DIS);
6f1d69b0
ED		 7520}
7521
a4565da8
VS		 7522static void cherryview_init_clock_gating(struct drm_device *dev)
7523{
fac5e23e 7524 struct drm_i915_private *dev_priv = to_i915(dev);
a4565da8 7525
232ce337
VS		 7526 /* WaVSRefCountFullforceMissDisable:chv */
7527 /* WaDSRefCountFullforceMissDisable:chv */
7528 I915_WRITE(GEN7_FF_THREAD_MODE,
7529 I915_READ(GEN7_FF_THREAD_MODE) &
7530 ~(GEN8_FF_DS_REF_CNT_FFME | GEN7_FF_VS_REF_CNT_FFME));
acea6f95
VS		 7531
7532 /* WaDisableSemaphoreAndSyncFlipWait:chv */
7533 I915_WRITE(GEN6_RC_SLEEP_PSMI_CONTROL,
7534 _MASKED_BIT_ENABLE(GEN8_RC_SEMA_IDLE_MSG_DISABLE));
0846697c
VS		 7535
7536 /* WaDisableCSUnitClockGating:chv */
7537 I915_WRITE(GEN6_UCGCTL1, I915_READ(GEN6_UCGCTL1) |
7538 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
c631780f
VS		 7539
7540 /* WaDisableSDEUnitClockGating:chv */
7541 I915_WRITE(GEN8_UCGCTL6, I915_READ(GEN8_UCGCTL6) |
7542 GEN8_SDEUNIT_CLOCK_GATE_DISABLE);
6d50b065 7543
450174fe
ID		 7544 /*
7545 * WaProgramL3SqcReg1Default:chv
7546 * See gfxspecs/Related Documents/Performance Guide/
7547 * LSQC Setting Recommendations.
7548 */
7549 gen8_set_l3sqc_credits(dev_priv, 38, 2);
7550
6d50b065
VS		 7551 /*
7552 * GTT cache may not work with big pages, so if those
7553 * are ever enabled GTT cache may need to be disabled.
7554 */
7555 I915_WRITE(HSW_GTT_CACHE_EN, GTT_CACHE_EN_ALL);
a4565da8
VS		 7556}
7557
1fa61106 7558static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7559{
fac5e23e 7560 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7561 uint32_t dspclk_gate;
7562
7563 I915_WRITE(RENCLK_GATE_D1, 0);
7564 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
7565 GS_UNIT_CLOCK_GATE_DISABLE |
7566 CL_UNIT_CLOCK_GATE_DISABLE);
7567 I915_WRITE(RAMCLK_GATE_D, 0);
7568 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
7569 OVRUNIT_CLOCK_GATE_DISABLE |
7570 OVCUNIT_CLOCK_GATE_DISABLE;
50a0bc90 7571 if (IS_GM45(dev_priv))
6f1d69b0
ED		 7572 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
7573 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 7574
7575 /* WaDisableRenderCachePipelinedFlush */
7576 I915_WRITE(CACHE_MODE_0,
7577 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
de1aa629 7578
4e04632e
AG		 7579 /* WaDisable_RenderCache_OperationalFlush:g4x */
7580 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
7581
0e088b8f 7582 g4x_disable_trickle_feed(dev);
6f1d69b0
ED		 7583}
7584
1fa61106 7585static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0 7586{
fac5e23e 7587 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7588
7589 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
7590 I915_WRITE(RENCLK_GATE_D2, 0);
7591 I915_WRITE(DSPCLK_GATE_D, 0);
7592 I915_WRITE(RAMCLK_GATE_D, 0);
7593 I915_WRITE16(DEUC, 0);
20f94967
VS		 7594 I915_WRITE(MI_ARB_STATE,
7595 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7596
7597 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7598 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7599}
7600
1fa61106 7601static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0 7602{
fac5e23e 7603 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7604
7605 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
7606 I965_RCC_CLOCK_GATE_DISABLE |
7607 I965_RCPB_CLOCK_GATE_DISABLE |
7608 I965_ISC_CLOCK_GATE_DISABLE |
7609 I965_FBC_CLOCK_GATE_DISABLE);
7610 I915_WRITE(RENCLK_GATE_D2, 0);
20f94967
VS		 7611 I915_WRITE(MI_ARB_STATE,
7612 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
4e04632e
AG		 7613
7614 /* WaDisable_RenderCache_OperationalFlush:gen4 */
7615 I915_WRITE(CACHE_MODE_0, _MASKED_BIT_DISABLE(RC_OP_FLUSH_ENABLE));
6f1d69b0
ED		 7616}
7617
1fa61106 7618static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0 7619{
fac5e23e 7620 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7621 u32 dstate = I915_READ(D_STATE);
7622
7623 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
7624 DSTATE_DOT_CLOCK_GATING;
7625 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 7626
7627 if (IS_PINEVIEW(dev))
7628 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 7629
7630 /* IIR "flip pending" means done if this bit is set */
7631 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
12fabbcb
VS		 7632
7633 /* interrupts should cause a wake up from C3 */
3299254f 7634 I915_WRITE(INSTPM, _MASKED_BIT_ENABLE(INSTPM_AGPBUSY_INT_EN));
dbb42748
VS		 7635
7636 /* On GEN3 we really need to make sure the ARB C3 LP bit is set */
7637 I915_WRITE(MI_ARB_STATE, _MASKED_BIT_ENABLE(MI_ARB_C3_LP_WRITE_ENABLE));
1038392b
VS		 7638
7639 I915_WRITE(MI_ARB_STATE,
7640 _MASKED_BIT_ENABLE(MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7641}
7642
1fa61106 7643static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0 7644{
fac5e23e 7645 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7646
7647 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
54e472ae
VS		 7648
7649 /* interrupts should cause a wake up from C3 */
7650 I915_WRITE(MI_STATE, _MASKED_BIT_ENABLE(MI_AGPBUSY_INT_EN) |
7651 _MASKED_BIT_DISABLE(MI_AGPBUSY_830_MODE));
1038392b
VS		 7652
7653 I915_WRITE(MEM_MODE,
7654 _MASKED_BIT_ENABLE(MEM_DISPLAY_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7655}
7656
1fa61106 7657static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0 7658{
fac5e23e 7659 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0
ED		 7660
7661 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
1038392b
VS		 7662
7663 I915_WRITE(MEM_MODE,
7664 _MASKED_BIT_ENABLE(MEM_DISPLAY_A_TRICKLE_FEED_DISABLE) |
7665 _MASKED_BIT_ENABLE(MEM_DISPLAY_B_TRICKLE_FEED_DISABLE));
6f1d69b0
ED		 7666}
7667
6f1d69b0
ED		 7668void intel_init_clock_gating(struct drm_device *dev)
7669{
fac5e23e 7670 struct drm_i915_private *dev_priv = to_i915(dev);
6f1d69b0 7671
bb400da9 7672 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 7673}
7674
7d708ee4
ID		 7675void intel_suspend_hw(struct drm_device *dev)
7676{
6e266956 7677 if (HAS_PCH_LPT(to_i915(dev)))
7d708ee4
ID		 7678 lpt_suspend_hw(dev);
7679}
7680
bb400da9
ID		 7681static void nop_init_clock_gating(struct drm_device *dev)
7682{
7683 DRM_DEBUG_KMS("No clock gating settings or workarounds applied.\n");
7684}
7685
7686/**
7687 * intel_init_clock_gating_hooks - setup the clock gating hooks
7688 * @dev_priv: device private
7689 *
7690 * Setup the hooks that configure which clocks of a given platform can be
7691 * gated and also apply various GT and display specific workarounds for these
7692 * platforms. Note that some GT specific workarounds are applied separately
7693 * when GPU contexts or batchbuffers start their execution.
7694 */
7695void intel_init_clock_gating_hooks(struct drm_i915_private *dev_priv)
7696{
7697 if (IS_SKYLAKE(dev_priv))
dc00b6a0 7698 dev_priv->display.init_clock_gating = skylake_init_clock_gating;
bb400da9 7699 else if (IS_KABYLAKE(dev_priv))
9498dba7 7700 dev_priv->display.init_clock_gating = kabylake_init_clock_gating;
bb400da9
ID		 7701 else if (IS_BROXTON(dev_priv))
7702 dev_priv->display.init_clock_gating = bxt_init_clock_gating;
7703 else if (IS_BROADWELL(dev_priv))
7704 dev_priv->display.init_clock_gating = broadwell_init_clock_gating;
7705 else if (IS_CHERRYVIEW(dev_priv))
7706 dev_priv->display.init_clock_gating = cherryview_init_clock_gating;
7707 else if (IS_HASWELL(dev_priv))
7708 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
7709 else if (IS_IVYBRIDGE(dev_priv))
7710 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
7711 else if (IS_VALLEYVIEW(dev_priv))
7712 dev_priv->display.init_clock_gating = valleyview_init_clock_gating;
7713 else if (IS_GEN6(dev_priv))
7714 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
7715 else if (IS_GEN5(dev_priv))
7716 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
7717 else if (IS_G4X(dev_priv))
7718 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
7719 else if (IS_CRESTLINE(dev_priv))
7720 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
7721 else if (IS_BROADWATER(dev_priv))
7722 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
7723 else if (IS_GEN3(dev_priv))
7724 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
7725 else if (IS_I85X(dev_priv) || IS_I865G(dev_priv))
7726 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
7727 else if (IS_GEN2(dev_priv))
7728 dev_priv->display.init_clock_gating = i830_init_clock_gating;
7729 else {
7730 MISSING_CASE(INTEL_DEVID(dev_priv));
7731 dev_priv->display.init_clock_gating = nop_init_clock_gating;
7732 }
7733}
7734
1fa61106
ED		 7735/* Set up chip specific power management-related functions */
7736void intel_init_pm(struct drm_device *dev)
7737{
fac5e23e 7738 struct drm_i915_private *dev_priv = to_i915(dev);
1fa61106 7739
7ff0ebcc 7740 intel_fbc_init(dev_priv);
1fa61106 7741
c921aba8
DV		 7742 /* For cxsr */
7743 if (IS_PINEVIEW(dev))
7744 i915_pineview_get_mem_freq(dev);
7745 else if (IS_GEN5(dev))
7746 i915_ironlake_get_mem_freq(dev);
7747
1fa61106 7748 /* For FIFO watermark updates */
f5ed50cb 7749 if (INTEL_INFO(dev)->gen >= 9) {
2af30a5c 7750 skl_setup_wm_latency(dev);
2d41c0b5 7751 dev_priv->display.update_wm = skl_update_wm;
98d39494 7752 dev_priv->display.compute_global_watermarks = skl_compute_wm;
6e266956 7753 } else if (HAS_PCH_SPLIT(dev_priv)) {
fa50ad61 7754 ilk_setup_wm_latency(dev);
53615a5e 7755
bd602544
VS		 7756 if ((IS_GEN5(dev) && dev_priv->wm.pri_latency[1] &&
7757 dev_priv->wm.spr_latency[1] && dev_priv->wm.cur_latency[1]) ||
7758 (!IS_GEN5(dev) && dev_priv->wm.pri_latency[0] &&
7759 dev_priv->wm.spr_latency[0] && dev_priv->wm.cur_latency[0])) {
86c8bbbe 7760 dev_priv->display.compute_pipe_wm = ilk_compute_pipe_wm;
ed4a6a7c
MR		 7761 dev_priv->display.compute_intermediate_wm =
7762 ilk_compute_intermediate_wm;
7763 dev_priv->display.initial_watermarks =
7764 ilk_initial_watermarks;
7765 dev_priv->display.optimize_watermarks =
7766 ilk_optimize_watermarks;
bd602544
VS		 7767 } else {
7768 DRM_DEBUG_KMS("Failed to read display plane latency. "
7769 "Disable CxSR\n");
7770 }
a4565da8 7771 } else if (IS_CHERRYVIEW(dev)) {
262cd2e1 7772 vlv_setup_wm_latency(dev);
262cd2e1 7773 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7774 } else if (IS_VALLEYVIEW(dev)) {
26e1fe4f 7775 vlv_setup_wm_latency(dev);
26e1fe4f 7776 dev_priv->display.update_wm = vlv_update_wm;
1fa61106 7777 } else if (IS_PINEVIEW(dev)) {
50a0bc90 7778 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev_priv),
1fa61106
ED		 7779 dev_priv->is_ddr3,
7780 dev_priv->fsb_freq,
7781 dev_priv->mem_freq)) {
7782 DRM_INFO("failed to find known CxSR latency "
7783 "(found ddr%s fsb freq %d, mem freq %d), "
7784 "disabling CxSR\n",
7785 (dev_priv->is_ddr3 == 1) ? "3" : "2",
7786 dev_priv->fsb_freq, dev_priv->mem_freq);
7787 /* Disable CxSR and never update its watermark again */
5209b1f4 7788 intel_set_memory_cxsr(dev_priv, false);
1fa61106
ED		 7789 dev_priv->display.update_wm = NULL;
7790 } else
7791 dev_priv->display.update_wm = pineview_update_wm;
1fa61106
ED		 7792 } else if (IS_G4X(dev)) {
7793 dev_priv->display.update_wm = g4x_update_wm;
1fa61106
ED		 7794 } else if (IS_GEN4(dev)) {
7795 dev_priv->display.update_wm = i965_update_wm;
1fa61106
ED		 7796 } else if (IS_GEN3(dev)) {
7797 dev_priv->display.update_wm = i9xx_update_wm;
7798 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
feb56b93
DV		 7799 } else if (IS_GEN2(dev)) {
7800 if (INTEL_INFO(dev)->num_pipes == 1) {
7801 dev_priv->display.update_wm = i845_update_wm;
1fa61106 7802 dev_priv->display.get_fifo_size = i845_get_fifo_size;
feb56b93
DV		 7803 } else {
7804 dev_priv->display.update_wm = i9xx_update_wm;
1fa61106 7805 dev_priv->display.get_fifo_size = i830_get_fifo_size;
feb56b93 7806 }
feb56b93
DV		 7807 } else {
7808 DRM_ERROR("unexpected fall-through in intel_init_pm\n");
1fa61106
ED		 7809 }
7810}
7811
87660502
L		 7812static inline int gen6_check_mailbox_status(struct drm_i915_private *dev_priv)
7813{
7814 uint32_t flags =
7815 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7816
7817 switch (flags) {
7818 case GEN6_PCODE_SUCCESS:
7819 return 0;
7820 case GEN6_PCODE_UNIMPLEMENTED_CMD:
7821 case GEN6_PCODE_ILLEGAL_CMD:
7822 return -ENXIO;
7823 case GEN6_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7850d1c3 7824 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
87660502
L		 7825 return -EOVERFLOW;
7826 case GEN6_PCODE_TIMEOUT:
7827 return -ETIMEDOUT;
7828 default:
7829 MISSING_CASE(flags)
7830 return 0;
7831 }
7832}
7833
7834static inline int gen7_check_mailbox_status(struct drm_i915_private *dev_priv)
7835{
7836 uint32_t flags =
7837 I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_ERROR_MASK;
7838
7839 switch (flags) {
7840 case GEN6_PCODE_SUCCESS:
7841 return 0;
7842 case GEN6_PCODE_ILLEGAL_CMD:
7843 return -ENXIO;
7844 case GEN7_PCODE_TIMEOUT:
7845 return -ETIMEDOUT;
7846 case GEN7_PCODE_ILLEGAL_DATA:
7847 return -EINVAL;
7848 case GEN7_PCODE_MIN_FREQ_TABLE_GT_RATIO_OUT_OF_RANGE:
7849 return -EOVERFLOW;
7850 default:
7851 MISSING_CASE(flags);
7852 return 0;
7853 }
7854}
7855
151a49d0 7856int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val)
42c0526c 7857{
87660502
L		 7858 int status;
7859
4fc688ce 7860 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7861
3f5582dd
CW		 7862 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7863 * use te fw I915_READ variants to reduce the amount of work
7864 * required when reading/writing.
7865 */
7866
7867 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7868 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
7869 return -EAGAIN;
7870 }
7871
3f5582dd
CW		 7872 I915_WRITE_FW(GEN6_PCODE_DATA, *val);
7873 I915_WRITE_FW(GEN6_PCODE_DATA1, 0);
7874 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7875
3f5582dd
CW		 7876 if (intel_wait_for_register_fw(dev_priv,
7877 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7878 500)) {
42c0526c
BW		 7879 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
7880 return -ETIMEDOUT;
7881 }
7882
3f5582dd
CW		 7883 *val = I915_READ_FW(GEN6_PCODE_DATA);
7884 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7885
87660502
L		 7886 if (INTEL_GEN(dev_priv) > 6)
7887 status = gen7_check_mailbox_status(dev_priv);
7888 else
7889 status = gen6_check_mailbox_status(dev_priv);
7890
7891 if (status) {
7892 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed: %d\n",
7893 status);
7894 return status;
7895 }
7896
42c0526c
BW		 7897 return 0;
7898}
7899
3f5582dd 7900int sandybridge_pcode_write(struct drm_i915_private *dev_priv,
87660502 7901 u32 mbox, u32 val)
42c0526c 7902{
87660502
L		 7903 int status;
7904
4fc688ce 7905 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c 7906
3f5582dd
CW		 7907 /* GEN6_PCODE_* are outside of the forcewake domain, we can
7908 * use te fw I915_READ variants to reduce the amount of work
7909 * required when reading/writing.
7910 */
7911
7912 if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
42c0526c
BW		 7913 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
7914 return -EAGAIN;
7915 }
7916
3f5582dd
CW		 7917 I915_WRITE_FW(GEN6_PCODE_DATA, val);
7918 I915_WRITE_FW(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
42c0526c 7919
3f5582dd
CW		 7920 if (intel_wait_for_register_fw(dev_priv,
7921 GEN6_PCODE_MAILBOX, GEN6_PCODE_READY, 0,
7922 500)) {
42c0526c
BW		 7923 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
7924 return -ETIMEDOUT;
7925 }
7926
3f5582dd 7927 I915_WRITE_FW(GEN6_PCODE_DATA, 0);
42c0526c 7928
87660502
L		 7929 if (INTEL_GEN(dev_priv) > 6)
7930 status = gen7_check_mailbox_status(dev_priv);
7931 else
7932 status = gen6_check_mailbox_status(dev_priv);
7933
7934 if (status) {
7935 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed: %d\n",
7936 status);
7937 return status;
7938 }
7939
42c0526c
BW		 7940 return 0;
7941}
a0e4e199 7942
dd06f88c
VS		 7943static int byt_gpu_freq(struct drm_i915_private *dev_priv, int val)
7944{
c30fec65
VS		 7945 /*
7946 * N = val - 0xb7
7947 * Slow = Fast = GPLL ref * N
7948 */
7949 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * (val - 0xb7), 1000);
855ba3be
JB		 7950}
7951
b55dd647 7952static int byt_freq_opcode(struct drm_i915_private *dev_priv, int val)
855ba3be 7953{
c30fec65 7954 return DIV_ROUND_CLOSEST(1000 * val, dev_priv->rps.gpll_ref_freq) + 0xb7;
855ba3be
JB		 7955}
7956
b55dd647 7957static int chv_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7958{
c30fec65
VS		 7959 /*
7960 * N = val / 2
7961 * CU (slow) = CU2x (fast) / 2 = GPLL ref * N / 2
7962 */
7963 return DIV_ROUND_CLOSEST(dev_priv->rps.gpll_ref_freq * val, 2 * 2 * 1000);
22b1b2f8
D		 7964}
7965
b55dd647 7966static int chv_freq_opcode(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7967{
1c14762d 7968 /* CHV needs even values */
c30fec65 7969 return DIV_ROUND_CLOSEST(2 * 1000 * val, dev_priv->rps.gpll_ref_freq) * 2;
22b1b2f8
D		 7970}
7971
616bc820 7972int intel_gpu_freq(struct drm_i915_private *dev_priv, int val)
22b1b2f8 7973{
2d1fe073 7974 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7975 return DIV_ROUND_CLOSEST(val * GT_FREQUENCY_MULTIPLIER,
7976 GEN9_FREQ_SCALER);
2d1fe073 7977 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7978 return chv_gpu_freq(dev_priv, val);
2d1fe073 7979 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7980 return byt_gpu_freq(dev_priv, val);
7981 else
7982 return val * GT_FREQUENCY_MULTIPLIER;
22b1b2f8
D		 7983}
7984
616bc820
VS		 7985int intel_freq_opcode(struct drm_i915_private *dev_priv, int val)
7986{
2d1fe073 7987 if (IS_GEN9(dev_priv))
500a3d2e
MK		 7988 return DIV_ROUND_CLOSEST(val * GEN9_FREQ_SCALER,
7989 GT_FREQUENCY_MULTIPLIER);
2d1fe073 7990 else if (IS_CHERRYVIEW(dev_priv))
616bc820 7991 return chv_freq_opcode(dev_priv, val);
2d1fe073 7992 else if (IS_VALLEYVIEW(dev_priv))
616bc820
VS		 7993 return byt_freq_opcode(dev_priv, val);
7994 else
500a3d2e 7995 return DIV_ROUND_CLOSEST(val, GT_FREQUENCY_MULTIPLIER);
616bc820 7996}
22b1b2f8 7997
6ad790c0
CW		 7998struct request_boost {
7999 struct work_struct work;
eed29a5b 8000 struct drm_i915_gem_request *req;
6ad790c0
CW		 8001};
8002
8003static void __intel_rps_boost_work(struct work_struct *work)
8004{
8005 struct request_boost *boost = container_of(work, struct request_boost, work);
e61b9958 8006 struct drm_i915_gem_request *req = boost->req;
6ad790c0 8007
f69a02c9 8008 if (!i915_gem_request_completed(req))
c033666a 8009 gen6_rps_boost(req->i915, NULL, req->emitted_jiffies);
6ad790c0 8010
e8a261ea 8011 i915_gem_request_put(req);
6ad790c0
CW		 8012 kfree(boost);
8013}
8014
91d14251 8015void intel_queue_rps_boost_for_request(struct drm_i915_gem_request *req)
6ad790c0
CW		 8016{
8017 struct request_boost *boost;
8018
91d14251 8019 if (req == NULL || INTEL_GEN(req->i915) < 6)
6ad790c0
CW		 8020 return;
8021
f69a02c9 8022 if (i915_gem_request_completed(req))
e61b9958
CW		 8023 return;
8024
6ad790c0
CW		 8025 boost = kmalloc(sizeof(*boost), GFP_ATOMIC);
8026 if (boost == NULL)
8027 return;
8028
e8a261ea 8029 boost->req = i915_gem_request_get(req);
6ad790c0
CW		 8030
8031 INIT_WORK(&boost->work, __intel_rps_boost_work);
91d14251 8032 queue_work(req->i915->wq, &boost->work);
6ad790c0
CW		 8033}
8034
f742a552 8035void intel_pm_setup(struct drm_device *dev)
907b28c5 8036{
fac5e23e 8037 struct drm_i915_private *dev_priv = to_i915(dev);
907b28c5 8038
f742a552 8039 mutex_init(&dev_priv->rps.hw_lock);
8d3afd7d 8040 spin_lock_init(&dev_priv->rps.client_lock);
f742a552 8041
54b4f68f
CW		 8042 INIT_DELAYED_WORK(&dev_priv->rps.autoenable_work,
8043 __intel_autoenable_gt_powersave);
1854d5ca 8044 INIT_LIST_HEAD(&dev_priv->rps.clients);
5d584b2e 8045
33688d95 8046 dev_priv->pm.suspended = false;
1f814dac 8047 atomic_set(&dev_priv->pm.wakeref_count, 0);
2b19efeb 8048 atomic_set(&dev_priv->pm.atomic_seq, 0);
907b28c5 8049}
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