]> git.proxmox.com Git - mirror_ubuntu-hirsute-kernel.git/blame - drivers/gpu/drm/i915/intel_pm.c
projects / mirror_ubuntu-hirsute-kernel.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
drm/i915: PCH_NOP
[mirror_ubuntu-hirsute-kernel.git] / drivers / gpu / drm / i915 / intel_pm.c
CommitLineData
85208be0
ED		 1/*
2 * Copyright © 2012 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 *
23 * Authors:
24 * Eugeni Dodonov <eugeni.dodonov@intel.com>
25 *
26 */
27
2b4e57bd 28#include <linux/cpufreq.h>
85208be0
ED		 29#include "i915_drv.h"
30#include "intel_drv.h"
eb48eb00
DV		 31#include "../../../platform/x86/intel_ips.h"
32#include <linux/module.h>
85208be0 33
057d3860 34#define FORCEWAKE_ACK_TIMEOUT_MS 2
b67a4376 35
f6750b3c
ED		 36/* FBC, or Frame Buffer Compression, is a technique employed to compress the
37 * framebuffer contents in-memory, aiming at reducing the required bandwidth
38 * during in-memory transfers and, therefore, reduce the power packet.
85208be0 39 *
f6750b3c
ED		 40 * The benefits of FBC are mostly visible with solid backgrounds and
41 * variation-less patterns.
85208be0 42 *
f6750b3c
ED		 43 * FBC-related functionality can be enabled by the means of the
44 * i915.i915_enable_fbc parameter
85208be0
ED		 45 */
46
3490ea5d
CW		 47static bool intel_crtc_active(struct drm_crtc *crtc)
48{
49 /* Be paranoid as we can arrive here with only partial
50 * state retrieved from the hardware during setup.
51 */
52 return to_intel_crtc(crtc)->active && crtc->fb && crtc->mode.clock;
53}
54
1fa61106 55static void i8xx_disable_fbc(struct drm_device *dev)
85208be0
ED		 56{
57 struct drm_i915_private *dev_priv = dev->dev_private;
58 u32 fbc_ctl;
59
60 /* Disable compression */
61 fbc_ctl = I915_READ(FBC_CONTROL);
62 if ((fbc_ctl & FBC_CTL_EN) == 0)
63 return;
64
65 fbc_ctl &= ~FBC_CTL_EN;
66 I915_WRITE(FBC_CONTROL, fbc_ctl);
67
68 /* Wait for compressing bit to clear */
69 if (wait_for((I915_READ(FBC_STATUS) & FBC_STAT_COMPRESSING) == 0, 10)) {
70 DRM_DEBUG_KMS("FBC idle timed out\n");
71 return;
72 }
73
74 DRM_DEBUG_KMS("disabled FBC\n");
75}
76
1fa61106 77static void i8xx_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 78{
79 struct drm_device *dev = crtc->dev;
80 struct drm_i915_private *dev_priv = dev->dev_private;
81 struct drm_framebuffer *fb = crtc->fb;
82 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
83 struct drm_i915_gem_object *obj = intel_fb->obj;
84 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
85 int cfb_pitch;
86 int plane, i;
87 u32 fbc_ctl, fbc_ctl2;
88
89 cfb_pitch = dev_priv->cfb_size / FBC_LL_SIZE;
90 if (fb->pitches[0] < cfb_pitch)
91 cfb_pitch = fb->pitches[0];
92
93 /* FBC_CTL wants 64B units */
94 cfb_pitch = (cfb_pitch / 64) - 1;
95 plane = intel_crtc->plane == 0 ? FBC_CTL_PLANEA : FBC_CTL_PLANEB;
96
97 /* Clear old tags */
98 for (i = 0; i < (FBC_LL_SIZE / 32) + 1; i++)
99 I915_WRITE(FBC_TAG + (i * 4), 0);
100
101 /* Set it up... */
102 fbc_ctl2 = FBC_CTL_FENCE_DBL | FBC_CTL_IDLE_IMM | FBC_CTL_CPU_FENCE;
103 fbc_ctl2 |= plane;
104 I915_WRITE(FBC_CONTROL2, fbc_ctl2);
105 I915_WRITE(FBC_FENCE_OFF, crtc->y);
106
107 /* enable it... */
108 fbc_ctl = FBC_CTL_EN | FBC_CTL_PERIODIC;
109 if (IS_I945GM(dev))
110 fbc_ctl |= FBC_CTL_C3_IDLE; /* 945 needs special SR handling */
111 fbc_ctl |= (cfb_pitch & 0xff) << FBC_CTL_STRIDE_SHIFT;
112 fbc_ctl |= (interval & 0x2fff) << FBC_CTL_INTERVAL_SHIFT;
113 fbc_ctl |= obj->fence_reg;
114 I915_WRITE(FBC_CONTROL, fbc_ctl);
115
116 DRM_DEBUG_KMS("enabled FBC, pitch %d, yoff %d, plane %d, ",
117 cfb_pitch, crtc->y, intel_crtc->plane);
118}
119
1fa61106 120static bool i8xx_fbc_enabled(struct drm_device *dev)
85208be0
ED		 121{
122 struct drm_i915_private *dev_priv = dev->dev_private;
123
124 return I915_READ(FBC_CONTROL) & FBC_CTL_EN;
125}
126
1fa61106 127static void g4x_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 128{
129 struct drm_device *dev = crtc->dev;
130 struct drm_i915_private *dev_priv = dev->dev_private;
131 struct drm_framebuffer *fb = crtc->fb;
132 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
133 struct drm_i915_gem_object *obj = intel_fb->obj;
134 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
135 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
136 unsigned long stall_watermark = 200;
137 u32 dpfc_ctl;
138
139 dpfc_ctl = plane | DPFC_SR_EN | DPFC_CTL_LIMIT_1X;
140 dpfc_ctl |= DPFC_CTL_FENCE_EN | obj->fence_reg;
141 I915_WRITE(DPFC_CHICKEN, DPFC_HT_MODIFY);
142
143 I915_WRITE(DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
144 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
145 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
146 I915_WRITE(DPFC_FENCE_YOFF, crtc->y);
147
148 /* enable it... */
149 I915_WRITE(DPFC_CONTROL, I915_READ(DPFC_CONTROL) | DPFC_CTL_EN);
150
151 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
152}
153
1fa61106 154static void g4x_disable_fbc(struct drm_device *dev)
85208be0
ED		 155{
156 struct drm_i915_private *dev_priv = dev->dev_private;
157 u32 dpfc_ctl;
158
159 /* Disable compression */
160 dpfc_ctl = I915_READ(DPFC_CONTROL);
161 if (dpfc_ctl & DPFC_CTL_EN) {
162 dpfc_ctl &= ~DPFC_CTL_EN;
163 I915_WRITE(DPFC_CONTROL, dpfc_ctl);
164
165 DRM_DEBUG_KMS("disabled FBC\n");
166 }
167}
168
1fa61106 169static bool g4x_fbc_enabled(struct drm_device *dev)
85208be0
ED		 170{
171 struct drm_i915_private *dev_priv = dev->dev_private;
172
173 return I915_READ(DPFC_CONTROL) & DPFC_CTL_EN;
174}
175
176static void sandybridge_blit_fbc_update(struct drm_device *dev)
177{
178 struct drm_i915_private *dev_priv = dev->dev_private;
179 u32 blt_ecoskpd;
180
181 /* Make sure blitter notifies FBC of writes */
182 gen6_gt_force_wake_get(dev_priv);
183 blt_ecoskpd = I915_READ(GEN6_BLITTER_ECOSKPD);
184 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY <<
185 GEN6_BLITTER_LOCK_SHIFT;
186 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
187 blt_ecoskpd |= GEN6_BLITTER_FBC_NOTIFY;
188 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
189 blt_ecoskpd &= ~(GEN6_BLITTER_FBC_NOTIFY <<
190 GEN6_BLITTER_LOCK_SHIFT);
191 I915_WRITE(GEN6_BLITTER_ECOSKPD, blt_ecoskpd);
192 POSTING_READ(GEN6_BLITTER_ECOSKPD);
193 gen6_gt_force_wake_put(dev_priv);
194}
195
1fa61106 196static void ironlake_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
85208be0
ED		 197{
198 struct drm_device *dev = crtc->dev;
199 struct drm_i915_private *dev_priv = dev->dev_private;
200 struct drm_framebuffer *fb = crtc->fb;
201 struct intel_framebuffer *intel_fb = to_intel_framebuffer(fb);
202 struct drm_i915_gem_object *obj = intel_fb->obj;
203 struct intel_crtc *intel_crtc = to_intel_crtc(crtc);
204 int plane = intel_crtc->plane == 0 ? DPFC_CTL_PLANEA : DPFC_CTL_PLANEB;
205 unsigned long stall_watermark = 200;
206 u32 dpfc_ctl;
207
208 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
209 dpfc_ctl &= DPFC_RESERVED;
210 dpfc_ctl |= (plane | DPFC_CTL_LIMIT_1X);
211 /* Set persistent mode for front-buffer rendering, ala X. */
212 dpfc_ctl |= DPFC_CTL_PERSISTENT_MODE;
213 dpfc_ctl |= (DPFC_CTL_FENCE_EN | obj->fence_reg);
214 I915_WRITE(ILK_DPFC_CHICKEN, DPFC_HT_MODIFY);
215
216 I915_WRITE(ILK_DPFC_RECOMP_CTL, DPFC_RECOMP_STALL_EN |
217 (stall_watermark << DPFC_RECOMP_STALL_WM_SHIFT) |
218 (interval << DPFC_RECOMP_TIMER_COUNT_SHIFT));
219 I915_WRITE(ILK_DPFC_FENCE_YOFF, crtc->y);
220 I915_WRITE(ILK_FBC_RT_BASE, obj->gtt_offset | ILK_FBC_RT_VALID);
221 /* enable it... */
222 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl | DPFC_CTL_EN);
223
224 if (IS_GEN6(dev)) {
225 I915_WRITE(SNB_DPFC_CTL_SA,
226 SNB_CPU_FENCE_ENABLE | obj->fence_reg);
227 I915_WRITE(DPFC_CPU_FENCE_OFFSET, crtc->y);
228 sandybridge_blit_fbc_update(dev);
229 }
230
231 DRM_DEBUG_KMS("enabled fbc on plane %d\n", intel_crtc->plane);
232}
233
1fa61106 234static void ironlake_disable_fbc(struct drm_device *dev)
85208be0
ED		 235{
236 struct drm_i915_private *dev_priv = dev->dev_private;
237 u32 dpfc_ctl;
238
239 /* Disable compression */
240 dpfc_ctl = I915_READ(ILK_DPFC_CONTROL);
241 if (dpfc_ctl & DPFC_CTL_EN) {
242 dpfc_ctl &= ~DPFC_CTL_EN;
243 I915_WRITE(ILK_DPFC_CONTROL, dpfc_ctl);
244
245 DRM_DEBUG_KMS("disabled FBC\n");
246 }
247}
248
1fa61106 249static bool ironlake_fbc_enabled(struct drm_device *dev)
85208be0
ED		 250{
251 struct drm_i915_private *dev_priv = dev->dev_private;
252
253 return I915_READ(ILK_DPFC_CONTROL) & DPFC_CTL_EN;
254}
255
256bool intel_fbc_enabled(struct drm_device *dev)
257{
258 struct drm_i915_private *dev_priv = dev->dev_private;
259
260 if (!dev_priv->display.fbc_enabled)
261 return false;
262
263 return dev_priv->display.fbc_enabled(dev);
264}
265
266static void intel_fbc_work_fn(struct work_struct *__work)
267{
268 struct intel_fbc_work *work =
269 container_of(to_delayed_work(__work),
270 struct intel_fbc_work, work);
271 struct drm_device *dev = work->crtc->dev;
272 struct drm_i915_private *dev_priv = dev->dev_private;
273
274 mutex_lock(&dev->struct_mutex);
275 if (work == dev_priv->fbc_work) {
276 /* Double check that we haven't switched fb without cancelling
277 * the prior work.
278 */
279 if (work->crtc->fb == work->fb) {
280 dev_priv->display.enable_fbc(work->crtc,
281 work->interval);
282
283 dev_priv->cfb_plane = to_intel_crtc(work->crtc)->plane;
284 dev_priv->cfb_fb = work->crtc->fb->base.id;
285 dev_priv->cfb_y = work->crtc->y;
286 }
287
288 dev_priv->fbc_work = NULL;
289 }
290 mutex_unlock(&dev->struct_mutex);
291
292 kfree(work);
293}
294
295static void intel_cancel_fbc_work(struct drm_i915_private *dev_priv)
296{
297 if (dev_priv->fbc_work == NULL)
298 return;
299
300 DRM_DEBUG_KMS("cancelling pending FBC enable\n");
301
302 /* Synchronisation is provided by struct_mutex and checking of
303 * dev_priv->fbc_work, so we can perform the cancellation
304 * entirely asynchronously.
305 */
306 if (cancel_delayed_work(&dev_priv->fbc_work->work))
307 /* tasklet was killed before being run, clean up */
308 kfree(dev_priv->fbc_work);
309
310 /* Mark the work as no longer wanted so that if it does
311 * wake-up (because the work was already running and waiting
312 * for our mutex), it will discover that is no longer
313 * necessary to run.
314 */
315 dev_priv->fbc_work = NULL;
316}
317
318void intel_enable_fbc(struct drm_crtc *crtc, unsigned long interval)
319{
320 struct intel_fbc_work *work;
321 struct drm_device *dev = crtc->dev;
322 struct drm_i915_private *dev_priv = dev->dev_private;
323
324 if (!dev_priv->display.enable_fbc)
325 return;
326
327 intel_cancel_fbc_work(dev_priv);
328
329 work = kzalloc(sizeof *work, GFP_KERNEL);
330 if (work == NULL) {
331 dev_priv->display.enable_fbc(crtc, interval);
332 return;
333 }
334
335 work->crtc = crtc;
336 work->fb = crtc->fb;
337 work->interval = interval;
338 INIT_DELAYED_WORK(&work->work, intel_fbc_work_fn);
339
340 dev_priv->fbc_work = work;
341
342 DRM_DEBUG_KMS("scheduling delayed FBC enable\n");
343
344 /* Delay the actual enabling to let pageflipping cease and the
345 * display to settle before starting the compression. Note that
346 * this delay also serves a second purpose: it allows for a
347 * vblank to pass after disabling the FBC before we attempt
348 * to modify the control registers.
349 *
350 * A more complicated solution would involve tracking vblanks
351 * following the termination of the page-flipping sequence
352 * and indeed performing the enable as a co-routine and not
353 * waiting synchronously upon the vblank.
354 */
355 schedule_delayed_work(&work->work, msecs_to_jiffies(50));
356}
357
358void intel_disable_fbc(struct drm_device *dev)
359{
360 struct drm_i915_private *dev_priv = dev->dev_private;
361
362 intel_cancel_fbc_work(dev_priv);
363
364 if (!dev_priv->display.disable_fbc)
365 return;
366
367 dev_priv->display.disable_fbc(dev);
368 dev_priv->cfb_plane = -1;
369}
370
371/**
372 * intel_update_fbc - enable/disable FBC as needed
373 * @dev: the drm_device
374 *
375 * Set up the framebuffer compression hardware at mode set time. We
376 * enable it if possible:
377 * - plane A only (on pre-965)
378 * - no pixel mulitply/line duplication
379 * - no alpha buffer discard
380 * - no dual wide
381 * - framebuffer <= 2048 in width, 1536 in height
382 *
383 * We can't assume that any compression will take place (worst case),
384 * so the compressed buffer has to be the same size as the uncompressed
385 * one. It also must reside (along with the line length buffer) in
386 * stolen memory.
387 *
388 * We need to enable/disable FBC on a global basis.
389 */
390void intel_update_fbc(struct drm_device *dev)
391{
392 struct drm_i915_private *dev_priv = dev->dev_private;
393 struct drm_crtc *crtc = NULL, *tmp_crtc;
394 struct intel_crtc *intel_crtc;
395 struct drm_framebuffer *fb;
396 struct intel_framebuffer *intel_fb;
397 struct drm_i915_gem_object *obj;
398 int enable_fbc;
399
85208be0
ED		 400 if (!i915_powersave)
401 return;
402
403 if (!I915_HAS_FBC(dev))
404 return;
405
406 /*
407 * If FBC is already on, we just have to verify that we can
408 * keep it that way...
409 * Need to disable if:
410 * - more than one pipe is active
411 * - changing FBC params (stride, fence, mode)
412 * - new fb is too large to fit in compressed buffer
413 * - going to an unsupported config (interlace, pixel multiply, etc.)
414 */
415 list_for_each_entry(tmp_crtc, &dev->mode_config.crtc_list, head) {
3490ea5d
CW		 416 if (intel_crtc_active(tmp_crtc) &&
417 !to_intel_crtc(tmp_crtc)->primary_disabled) {
85208be0
ED		 418 if (crtc) {
419 DRM_DEBUG_KMS("more than one pipe active, disabling compression\n");
420 dev_priv->no_fbc_reason = FBC_MULTIPLE_PIPES;
421 goto out_disable;
422 }
423 crtc = tmp_crtc;
424 }
425 }
426
427 if (!crtc || crtc->fb == NULL) {
428 DRM_DEBUG_KMS("no output, disabling\n");
429 dev_priv->no_fbc_reason = FBC_NO_OUTPUT;
430 goto out_disable;
431 }
432
433 intel_crtc = to_intel_crtc(crtc);
434 fb = crtc->fb;
435 intel_fb = to_intel_framebuffer(fb);
436 obj = intel_fb->obj;
437
438 enable_fbc = i915_enable_fbc;
439 if (enable_fbc < 0) {
440 DRM_DEBUG_KMS("fbc set to per-chip default\n");
441 enable_fbc = 1;
442 if (INTEL_INFO(dev)->gen <= 6)
443 enable_fbc = 0;
444 }
445 if (!enable_fbc) {
446 DRM_DEBUG_KMS("fbc disabled per module param\n");
447 dev_priv->no_fbc_reason = FBC_MODULE_PARAM;
448 goto out_disable;
449 }
85208be0
ED		 450 if ((crtc->mode.flags & DRM_MODE_FLAG_INTERLACE) ||
451 (crtc->mode.flags & DRM_MODE_FLAG_DBLSCAN)) {
452 DRM_DEBUG_KMS("mode incompatible with compression, "
453 "disabling\n");
454 dev_priv->no_fbc_reason = FBC_UNSUPPORTED_MODE;
455 goto out_disable;
456 }
457 if ((crtc->mode.hdisplay > 2048) ||
458 (crtc->mode.vdisplay > 1536)) {
459 DRM_DEBUG_KMS("mode too large for compression, disabling\n");
460 dev_priv->no_fbc_reason = FBC_MODE_TOO_LARGE;
461 goto out_disable;
462 }
463 if ((IS_I915GM(dev) || IS_I945GM(dev)) && intel_crtc->plane != 0) {
464 DRM_DEBUG_KMS("plane not 0, disabling compression\n");
465 dev_priv->no_fbc_reason = FBC_BAD_PLANE;
466 goto out_disable;
467 }
468
469 /* The use of a CPU fence is mandatory in order to detect writes
470 * by the CPU to the scanout and trigger updates to the FBC.
471 */
472 if (obj->tiling_mode != I915_TILING_X ||
473 obj->fence_reg == I915_FENCE_REG_NONE) {
474 DRM_DEBUG_KMS("framebuffer not tiled or fenced, disabling compression\n");
475 dev_priv->no_fbc_reason = FBC_NOT_TILED;
476 goto out_disable;
477 }
478
479 /* If the kernel debugger is active, always disable compression */
480 if (in_dbg_master())
481 goto out_disable;
482
11be49eb
CW		 483 if (i915_gem_stolen_setup_compression(dev, intel_fb->obj->base.size)) {
484 DRM_INFO("not enough stolen space for compressed buffer (need %zd bytes), disabling\n", intel_fb->obj->base.size);
485 DRM_INFO("hint: you may be able to increase stolen memory size in the BIOS to avoid this\n");
486 DRM_DEBUG_KMS("framebuffer too large, disabling compression\n");
487 dev_priv->no_fbc_reason = FBC_STOLEN_TOO_SMALL;
488 goto out_disable;
489 }
490
85208be0
ED		 491 /* If the scanout has not changed, don't modify the FBC settings.
492 * Note that we make the fundamental assumption that the fb->obj
493 * cannot be unpinned (and have its GTT offset and fence revoked)
494 * without first being decoupled from the scanout and FBC disabled.
495 */
496 if (dev_priv->cfb_plane == intel_crtc->plane &&
497 dev_priv->cfb_fb == fb->base.id &&
498 dev_priv->cfb_y == crtc->y)
499 return;
500
501 if (intel_fbc_enabled(dev)) {
502 /* We update FBC along two paths, after changing fb/crtc
503 * configuration (modeswitching) and after page-flipping
504 * finishes. For the latter, we know that not only did
505 * we disable the FBC at the start of the page-flip
506 * sequence, but also more than one vblank has passed.
507 *
508 * For the former case of modeswitching, it is possible
509 * to switch between two FBC valid configurations
510 * instantaneously so we do need to disable the FBC
511 * before we can modify its control registers. We also
512 * have to wait for the next vblank for that to take
513 * effect. However, since we delay enabling FBC we can
514 * assume that a vblank has passed since disabling and
515 * that we can safely alter the registers in the deferred
516 * callback.
517 *
518 * In the scenario that we go from a valid to invalid
519 * and then back to valid FBC configuration we have
520 * no strict enforcement that a vblank occurred since
521 * disabling the FBC. However, along all current pipe
522 * disabling paths we do need to wait for a vblank at
523 * some point. And we wait before enabling FBC anyway.
524 */
525 DRM_DEBUG_KMS("disabling active FBC for update\n");
526 intel_disable_fbc(dev);
527 }
528
529 intel_enable_fbc(crtc, 500);
530 return;
531
532out_disable:
533 /* Multiple disables should be harmless */
534 if (intel_fbc_enabled(dev)) {
535 DRM_DEBUG_KMS("unsupported config, disabling FBC\n");
536 intel_disable_fbc(dev);
537 }
11be49eb 538 i915_gem_stolen_cleanup_compression(dev);
85208be0
ED		 539}
540
c921aba8
DV		 541static void i915_pineview_get_mem_freq(struct drm_device *dev)
542{
543 drm_i915_private_t *dev_priv = dev->dev_private;
544 u32 tmp;
545
546 tmp = I915_READ(CLKCFG);
547
548 switch (tmp & CLKCFG_FSB_MASK) {
549 case CLKCFG_FSB_533:
550 dev_priv->fsb_freq = 533; /* 133*4 */
551 break;
552 case CLKCFG_FSB_800:
553 dev_priv->fsb_freq = 800; /* 200*4 */
554 break;
555 case CLKCFG_FSB_667:
556 dev_priv->fsb_freq = 667; /* 167*4 */
557 break;
558 case CLKCFG_FSB_400:
559 dev_priv->fsb_freq = 400; /* 100*4 */
560 break;
561 }
562
563 switch (tmp & CLKCFG_MEM_MASK) {
564 case CLKCFG_MEM_533:
565 dev_priv->mem_freq = 533;
566 break;
567 case CLKCFG_MEM_667:
568 dev_priv->mem_freq = 667;
569 break;
570 case CLKCFG_MEM_800:
571 dev_priv->mem_freq = 800;
572 break;
573 }
574
575 /* detect pineview DDR3 setting */
576 tmp = I915_READ(CSHRDDR3CTL);
577 dev_priv->is_ddr3 = (tmp & CSHRDDR3CTL_DDR3) ? 1 : 0;
578}
579
580static void i915_ironlake_get_mem_freq(struct drm_device *dev)
581{
582 drm_i915_private_t *dev_priv = dev->dev_private;
583 u16 ddrpll, csipll;
584
585 ddrpll = I915_READ16(DDRMPLL1);
586 csipll = I915_READ16(CSIPLL0);
587
588 switch (ddrpll & 0xff) {
589 case 0xc:
590 dev_priv->mem_freq = 800;
591 break;
592 case 0x10:
593 dev_priv->mem_freq = 1066;
594 break;
595 case 0x14:
596 dev_priv->mem_freq = 1333;
597 break;
598 case 0x18:
599 dev_priv->mem_freq = 1600;
600 break;
601 default:
602 DRM_DEBUG_DRIVER("unknown memory frequency 0x%02x\n",
603 ddrpll & 0xff);
604 dev_priv->mem_freq = 0;
605 break;
606 }
607
20e4d407 608 dev_priv->ips.r_t = dev_priv->mem_freq;
c921aba8
DV		 609
610 switch (csipll & 0x3ff) {
611 case 0x00c:
612 dev_priv->fsb_freq = 3200;
613 break;
614 case 0x00e:
615 dev_priv->fsb_freq = 3733;
616 break;
617 case 0x010:
618 dev_priv->fsb_freq = 4266;
619 break;
620 case 0x012:
621 dev_priv->fsb_freq = 4800;
622 break;
623 case 0x014:
624 dev_priv->fsb_freq = 5333;
625 break;
626 case 0x016:
627 dev_priv->fsb_freq = 5866;
628 break;
629 case 0x018:
630 dev_priv->fsb_freq = 6400;
631 break;
632 default:
633 DRM_DEBUG_DRIVER("unknown fsb frequency 0x%04x\n",
634 csipll & 0x3ff);
635 dev_priv->fsb_freq = 0;
636 break;
637 }
638
639 if (dev_priv->fsb_freq == 3200) {
20e4d407 640 dev_priv->ips.c_m = 0;
c921aba8 641 } else if (dev_priv->fsb_freq > 3200 && dev_priv->fsb_freq <= 4800) {
20e4d407 642 dev_priv->ips.c_m = 1;
c921aba8 643 } else {
20e4d407 644 dev_priv->ips.c_m = 2;
c921aba8
DV		 645 }
646}
647
b445e3b0
ED		 648static const struct cxsr_latency cxsr_latency_table[] = {
649 {1, 0, 800, 400, 3382, 33382, 3983, 33983}, /* DDR2-400 SC */
650 {1, 0, 800, 667, 3354, 33354, 3807, 33807}, /* DDR2-667 SC */
651 {1, 0, 800, 800, 3347, 33347, 3763, 33763}, /* DDR2-800 SC */
652 {1, 1, 800, 667, 6420, 36420, 6873, 36873}, /* DDR3-667 SC */
653 {1, 1, 800, 800, 5902, 35902, 6318, 36318}, /* DDR3-800 SC */
654
655 {1, 0, 667, 400, 3400, 33400, 4021, 34021}, /* DDR2-400 SC */
656 {1, 0, 667, 667, 3372, 33372, 3845, 33845}, /* DDR2-667 SC */
657 {1, 0, 667, 800, 3386, 33386, 3822, 33822}, /* DDR2-800 SC */
658 {1, 1, 667, 667, 6438, 36438, 6911, 36911}, /* DDR3-667 SC */
659 {1, 1, 667, 800, 5941, 35941, 6377, 36377}, /* DDR3-800 SC */
660
661 {1, 0, 400, 400, 3472, 33472, 4173, 34173}, /* DDR2-400 SC */
662 {1, 0, 400, 667, 3443, 33443, 3996, 33996}, /* DDR2-667 SC */
663 {1, 0, 400, 800, 3430, 33430, 3946, 33946}, /* DDR2-800 SC */
664 {1, 1, 400, 667, 6509, 36509, 7062, 37062}, /* DDR3-667 SC */
665 {1, 1, 400, 800, 5985, 35985, 6501, 36501}, /* DDR3-800 SC */
666
667 {0, 0, 800, 400, 3438, 33438, 4065, 34065}, /* DDR2-400 SC */
668 {0, 0, 800, 667, 3410, 33410, 3889, 33889}, /* DDR2-667 SC */
669 {0, 0, 800, 800, 3403, 33403, 3845, 33845}, /* DDR2-800 SC */
670 {0, 1, 800, 667, 6476, 36476, 6955, 36955}, /* DDR3-667 SC */
671 {0, 1, 800, 800, 5958, 35958, 6400, 36400}, /* DDR3-800 SC */
672
673 {0, 0, 667, 400, 3456, 33456, 4103, 34106}, /* DDR2-400 SC */
674 {0, 0, 667, 667, 3428, 33428, 3927, 33927}, /* DDR2-667 SC */
675 {0, 0, 667, 800, 3443, 33443, 3905, 33905}, /* DDR2-800 SC */
676 {0, 1, 667, 667, 6494, 36494, 6993, 36993}, /* DDR3-667 SC */
677 {0, 1, 667, 800, 5998, 35998, 6460, 36460}, /* DDR3-800 SC */
678
679 {0, 0, 400, 400, 3528, 33528, 4255, 34255}, /* DDR2-400 SC */
680 {0, 0, 400, 667, 3500, 33500, 4079, 34079}, /* DDR2-667 SC */
681 {0, 0, 400, 800, 3487, 33487, 4029, 34029}, /* DDR2-800 SC */
682 {0, 1, 400, 667, 6566, 36566, 7145, 37145}, /* DDR3-667 SC */
683 {0, 1, 400, 800, 6042, 36042, 6584, 36584}, /* DDR3-800 SC */
684};
685
63c62275 686static const struct cxsr_latency *intel_get_cxsr_latency(int is_desktop,
b445e3b0
ED		 687 int is_ddr3,
688 int fsb,
689 int mem)
690{
691 const struct cxsr_latency *latency;
692 int i;
693
694 if (fsb == 0 || mem == 0)
695 return NULL;
696
697 for (i = 0; i < ARRAY_SIZE(cxsr_latency_table); i++) {
698 latency = &cxsr_latency_table[i];
699 if (is_desktop == latency->is_desktop &&
700 is_ddr3 == latency->is_ddr3 &&
701 fsb == latency->fsb_freq && mem == latency->mem_freq)
702 return latency;
703 }
704
705 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
706
707 return NULL;
708}
709
1fa61106 710static void pineview_disable_cxsr(struct drm_device *dev)
b445e3b0
ED		 711{
712 struct drm_i915_private *dev_priv = dev->dev_private;
713
714 /* deactivate cxsr */
715 I915_WRITE(DSPFW3, I915_READ(DSPFW3) & ~PINEVIEW_SELF_REFRESH_EN);
716}
717
718/*
719 * Latency for FIFO fetches is dependent on several factors:
720 * - memory configuration (speed, channels)
721 * - chipset
722 * - current MCH state
723 * It can be fairly high in some situations, so here we assume a fairly
724 * pessimal value. It's a tradeoff between extra memory fetches (if we
725 * set this value too high, the FIFO will fetch frequently to stay full)
726 * and power consumption (set it too low to save power and we might see
727 * FIFO underruns and display "flicker").
728 *
729 * A value of 5us seems to be a good balance; safe for very low end
730 * platforms but not overly aggressive on lower latency configs.
731 */
732static const int latency_ns = 5000;
733
1fa61106 734static int i9xx_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 735{
736 struct drm_i915_private *dev_priv = dev->dev_private;
737 uint32_t dsparb = I915_READ(DSPARB);
738 int size;
739
740 size = dsparb & 0x7f;
741 if (plane)
742 size = ((dsparb >> DSPARB_CSTART_SHIFT) & 0x7f) - size;
743
744 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
745 plane ? "B" : "A", size);
746
747 return size;
748}
749
1fa61106 750static int i85x_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 751{
752 struct drm_i915_private *dev_priv = dev->dev_private;
753 uint32_t dsparb = I915_READ(DSPARB);
754 int size;
755
756 size = dsparb & 0x1ff;
757 if (plane)
758 size = ((dsparb >> DSPARB_BEND_SHIFT) & 0x1ff) - size;
759 size >>= 1; /* Convert to cachelines */
760
761 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
762 plane ? "B" : "A", size);
763
764 return size;
765}
766
1fa61106 767static int i845_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 768{
769 struct drm_i915_private *dev_priv = dev->dev_private;
770 uint32_t dsparb = I915_READ(DSPARB);
771 int size;
772
773 size = dsparb & 0x7f;
774 size >>= 2; /* Convert to cachelines */
775
776 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
777 plane ? "B" : "A",
778 size);
779
780 return size;
781}
782
1fa61106 783static int i830_get_fifo_size(struct drm_device *dev, int plane)
b445e3b0
ED		 784{
785 struct drm_i915_private *dev_priv = dev->dev_private;
786 uint32_t dsparb = I915_READ(DSPARB);
787 int size;
788
789 size = dsparb & 0x7f;
790 size >>= 1; /* Convert to cachelines */
791
792 DRM_DEBUG_KMS("FIFO size - (0x%08x) %s: %d\n", dsparb,
793 plane ? "B" : "A", size);
794
795 return size;
796}
797
798/* Pineview has different values for various configs */
799static const struct intel_watermark_params pineview_display_wm = {
800 PINEVIEW_DISPLAY_FIFO,
801 PINEVIEW_MAX_WM,
802 PINEVIEW_DFT_WM,
803 PINEVIEW_GUARD_WM,
804 PINEVIEW_FIFO_LINE_SIZE
805};
806static const struct intel_watermark_params pineview_display_hplloff_wm = {
807 PINEVIEW_DISPLAY_FIFO,
808 PINEVIEW_MAX_WM,
809 PINEVIEW_DFT_HPLLOFF_WM,
810 PINEVIEW_GUARD_WM,
811 PINEVIEW_FIFO_LINE_SIZE
812};
813static const struct intel_watermark_params pineview_cursor_wm = {
814 PINEVIEW_CURSOR_FIFO,
815 PINEVIEW_CURSOR_MAX_WM,
816 PINEVIEW_CURSOR_DFT_WM,
817 PINEVIEW_CURSOR_GUARD_WM,
818 PINEVIEW_FIFO_LINE_SIZE,
819};
820static const struct intel_watermark_params pineview_cursor_hplloff_wm = {
821 PINEVIEW_CURSOR_FIFO,
822 PINEVIEW_CURSOR_MAX_WM,
823 PINEVIEW_CURSOR_DFT_WM,
824 PINEVIEW_CURSOR_GUARD_WM,
825 PINEVIEW_FIFO_LINE_SIZE
826};
827static const struct intel_watermark_params g4x_wm_info = {
828 G4X_FIFO_SIZE,
829 G4X_MAX_WM,
830 G4X_MAX_WM,
831 2,
832 G4X_FIFO_LINE_SIZE,
833};
834static const struct intel_watermark_params g4x_cursor_wm_info = {
835 I965_CURSOR_FIFO,
836 I965_CURSOR_MAX_WM,
837 I965_CURSOR_DFT_WM,
838 2,
839 G4X_FIFO_LINE_SIZE,
840};
841static const struct intel_watermark_params valleyview_wm_info = {
842 VALLEYVIEW_FIFO_SIZE,
843 VALLEYVIEW_MAX_WM,
844 VALLEYVIEW_MAX_WM,
845 2,
846 G4X_FIFO_LINE_SIZE,
847};
848static const struct intel_watermark_params valleyview_cursor_wm_info = {
849 I965_CURSOR_FIFO,
850 VALLEYVIEW_CURSOR_MAX_WM,
851 I965_CURSOR_DFT_WM,
852 2,
853 G4X_FIFO_LINE_SIZE,
854};
855static const struct intel_watermark_params i965_cursor_wm_info = {
856 I965_CURSOR_FIFO,
857 I965_CURSOR_MAX_WM,
858 I965_CURSOR_DFT_WM,
859 2,
860 I915_FIFO_LINE_SIZE,
861};
862static const struct intel_watermark_params i945_wm_info = {
863 I945_FIFO_SIZE,
864 I915_MAX_WM,
865 1,
866 2,
867 I915_FIFO_LINE_SIZE
868};
869static const struct intel_watermark_params i915_wm_info = {
870 I915_FIFO_SIZE,
871 I915_MAX_WM,
872 1,
873 2,
874 I915_FIFO_LINE_SIZE
875};
876static const struct intel_watermark_params i855_wm_info = {
877 I855GM_FIFO_SIZE,
878 I915_MAX_WM,
879 1,
880 2,
881 I830_FIFO_LINE_SIZE
882};
883static const struct intel_watermark_params i830_wm_info = {
884 I830_FIFO_SIZE,
885 I915_MAX_WM,
886 1,
887 2,
888 I830_FIFO_LINE_SIZE
889};
890
891static const struct intel_watermark_params ironlake_display_wm_info = {
892 ILK_DISPLAY_FIFO,
893 ILK_DISPLAY_MAXWM,
894 ILK_DISPLAY_DFTWM,
895 2,
896 ILK_FIFO_LINE_SIZE
897};
898static const struct intel_watermark_params ironlake_cursor_wm_info = {
899 ILK_CURSOR_FIFO,
900 ILK_CURSOR_MAXWM,
901 ILK_CURSOR_DFTWM,
902 2,
903 ILK_FIFO_LINE_SIZE
904};
905static const struct intel_watermark_params ironlake_display_srwm_info = {
906 ILK_DISPLAY_SR_FIFO,
907 ILK_DISPLAY_MAX_SRWM,
908 ILK_DISPLAY_DFT_SRWM,
909 2,
910 ILK_FIFO_LINE_SIZE
911};
912static const struct intel_watermark_params ironlake_cursor_srwm_info = {
913 ILK_CURSOR_SR_FIFO,
914 ILK_CURSOR_MAX_SRWM,
915 ILK_CURSOR_DFT_SRWM,
916 2,
917 ILK_FIFO_LINE_SIZE
918};
919
920static const struct intel_watermark_params sandybridge_display_wm_info = {
921 SNB_DISPLAY_FIFO,
922 SNB_DISPLAY_MAXWM,
923 SNB_DISPLAY_DFTWM,
924 2,
925 SNB_FIFO_LINE_SIZE
926};
927static const struct intel_watermark_params sandybridge_cursor_wm_info = {
928 SNB_CURSOR_FIFO,
929 SNB_CURSOR_MAXWM,
930 SNB_CURSOR_DFTWM,
931 2,
932 SNB_FIFO_LINE_SIZE
933};
934static const struct intel_watermark_params sandybridge_display_srwm_info = {
935 SNB_DISPLAY_SR_FIFO,
936 SNB_DISPLAY_MAX_SRWM,
937 SNB_DISPLAY_DFT_SRWM,
938 2,
939 SNB_FIFO_LINE_SIZE
940};
941static const struct intel_watermark_params sandybridge_cursor_srwm_info = {
942 SNB_CURSOR_SR_FIFO,
943 SNB_CURSOR_MAX_SRWM,
944 SNB_CURSOR_DFT_SRWM,
945 2,
946 SNB_FIFO_LINE_SIZE
947};
948
949
950/**
951 * intel_calculate_wm - calculate watermark level
952 * @clock_in_khz: pixel clock
953 * @wm: chip FIFO params
954 * @pixel_size: display pixel size
955 * @latency_ns: memory latency for the platform
956 *
957 * Calculate the watermark level (the level at which the display plane will
958 * start fetching from memory again). Each chip has a different display
959 * FIFO size and allocation, so the caller needs to figure that out and pass
960 * in the correct intel_watermark_params structure.
961 *
962 * As the pixel clock runs, the FIFO will be drained at a rate that depends
963 * on the pixel size. When it reaches the watermark level, it'll start
964 * fetching FIFO line sized based chunks from memory until the FIFO fills
965 * past the watermark point. If the FIFO drains completely, a FIFO underrun
966 * will occur, and a display engine hang could result.
967 */
968static unsigned long intel_calculate_wm(unsigned long clock_in_khz,
969 const struct intel_watermark_params *wm,
970 int fifo_size,
971 int pixel_size,
972 unsigned long latency_ns)
973{
974 long entries_required, wm_size;
975
976 /*
977 * Note: we need to make sure we don't overflow for various clock &
978 * latency values.
979 * clocks go from a few thousand to several hundred thousand.
980 * latency is usually a few thousand
981 */
982 entries_required = ((clock_in_khz / 1000) * pixel_size * latency_ns) /
983 1000;
984 entries_required = DIV_ROUND_UP(entries_required, wm->cacheline_size);
985
986 DRM_DEBUG_KMS("FIFO entries required for mode: %ld\n", entries_required);
987
988 wm_size = fifo_size - (entries_required + wm->guard_size);
989
990 DRM_DEBUG_KMS("FIFO watermark level: %ld\n", wm_size);
991
992 /* Don't promote wm_size to unsigned... */
993 if (wm_size > (long)wm->max_wm)
994 wm_size = wm->max_wm;
995 if (wm_size <= 0)
996 wm_size = wm->default_wm;
997 return wm_size;
998}
999
1000static struct drm_crtc *single_enabled_crtc(struct drm_device *dev)
1001{
1002 struct drm_crtc *crtc, *enabled = NULL;
1003
1004 list_for_each_entry(crtc, &dev->mode_config.crtc_list, head) {
3490ea5d 1005 if (intel_crtc_active(crtc)) {
b445e3b0
ED		 1006 if (enabled)
1007 return NULL;
1008 enabled = crtc;
1009 }
1010 }
1011
1012 return enabled;
1013}
1014
1fa61106 1015static void pineview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1016{
1017 struct drm_i915_private *dev_priv = dev->dev_private;
1018 struct drm_crtc *crtc;
1019 const struct cxsr_latency *latency;
1020 u32 reg;
1021 unsigned long wm;
1022
1023 latency = intel_get_cxsr_latency(IS_PINEVIEW_G(dev), dev_priv->is_ddr3,
1024 dev_priv->fsb_freq, dev_priv->mem_freq);
1025 if (!latency) {
1026 DRM_DEBUG_KMS("Unknown FSB/MEM found, disable CxSR\n");
1027 pineview_disable_cxsr(dev);
1028 return;
1029 }
1030
1031 crtc = single_enabled_crtc(dev);
1032 if (crtc) {
1033 int clock = crtc->mode.clock;
1034 int pixel_size = crtc->fb->bits_per_pixel / 8;
1035
1036 /* Display SR */
1037 wm = intel_calculate_wm(clock, &pineview_display_wm,
1038 pineview_display_wm.fifo_size,
1039 pixel_size, latency->display_sr);
1040 reg = I915_READ(DSPFW1);
1041 reg &= ~DSPFW_SR_MASK;
1042 reg |= wm << DSPFW_SR_SHIFT;
1043 I915_WRITE(DSPFW1, reg);
1044 DRM_DEBUG_KMS("DSPFW1 register is %x\n", reg);
1045
1046 /* cursor SR */
1047 wm = intel_calculate_wm(clock, &pineview_cursor_wm,
1048 pineview_display_wm.fifo_size,
1049 pixel_size, latency->cursor_sr);
1050 reg = I915_READ(DSPFW3);
1051 reg &= ~DSPFW_CURSOR_SR_MASK;
1052 reg |= (wm & 0x3f) << DSPFW_CURSOR_SR_SHIFT;
1053 I915_WRITE(DSPFW3, reg);
1054
1055 /* Display HPLL off SR */
1056 wm = intel_calculate_wm(clock, &pineview_display_hplloff_wm,
1057 pineview_display_hplloff_wm.fifo_size,
1058 pixel_size, latency->display_hpll_disable);
1059 reg = I915_READ(DSPFW3);
1060 reg &= ~DSPFW_HPLL_SR_MASK;
1061 reg |= wm & DSPFW_HPLL_SR_MASK;
1062 I915_WRITE(DSPFW3, reg);
1063
1064 /* cursor HPLL off SR */
1065 wm = intel_calculate_wm(clock, &pineview_cursor_hplloff_wm,
1066 pineview_display_hplloff_wm.fifo_size,
1067 pixel_size, latency->cursor_hpll_disable);
1068 reg = I915_READ(DSPFW3);
1069 reg &= ~DSPFW_HPLL_CURSOR_MASK;
1070 reg |= (wm & 0x3f) << DSPFW_HPLL_CURSOR_SHIFT;
1071 I915_WRITE(DSPFW3, reg);
1072 DRM_DEBUG_KMS("DSPFW3 register is %x\n", reg);
1073
1074 /* activate cxsr */
1075 I915_WRITE(DSPFW3,
1076 I915_READ(DSPFW3) | PINEVIEW_SELF_REFRESH_EN);
1077 DRM_DEBUG_KMS("Self-refresh is enabled\n");
1078 } else {
1079 pineview_disable_cxsr(dev);
1080 DRM_DEBUG_KMS("Self-refresh is disabled\n");
1081 }
1082}
1083
1084static bool g4x_compute_wm0(struct drm_device *dev,
1085 int plane,
1086 const struct intel_watermark_params *display,
1087 int display_latency_ns,
1088 const struct intel_watermark_params *cursor,
1089 int cursor_latency_ns,
1090 int *plane_wm,
1091 int *cursor_wm)
1092{
1093 struct drm_crtc *crtc;
1094 int htotal, hdisplay, clock, pixel_size;
1095 int line_time_us, line_count;
1096 int entries, tlb_miss;
1097
1098 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1099 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 1100 *cursor_wm = cursor->guard_size;
1101 *plane_wm = display->guard_size;
1102 return false;
1103 }
1104
1105 htotal = crtc->mode.htotal;
1106 hdisplay = crtc->mode.hdisplay;
1107 clock = crtc->mode.clock;
1108 pixel_size = crtc->fb->bits_per_pixel / 8;
1109
1110 /* Use the small buffer method to calculate plane watermark */
1111 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
1112 tlb_miss = display->fifo_size*display->cacheline_size - hdisplay * 8;
1113 if (tlb_miss > 0)
1114 entries += tlb_miss;
1115 entries = DIV_ROUND_UP(entries, display->cacheline_size);
1116 *plane_wm = entries + display->guard_size;
1117 if (*plane_wm > (int)display->max_wm)
1118 *plane_wm = display->max_wm;
1119
1120 /* Use the large buffer method to calculate cursor watermark */
1121 line_time_us = ((htotal * 1000) / clock);
1122 line_count = (cursor_latency_ns / line_time_us + 1000) / 1000;
1123 entries = line_count * 64 * pixel_size;
1124 tlb_miss = cursor->fifo_size*cursor->cacheline_size - hdisplay * 8;
1125 if (tlb_miss > 0)
1126 entries += tlb_miss;
1127 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1128 *cursor_wm = entries + cursor->guard_size;
1129 if (*cursor_wm > (int)cursor->max_wm)
1130 *cursor_wm = (int)cursor->max_wm;
1131
1132 return true;
1133}
1134
1135/*
1136 * Check the wm result.
1137 *
1138 * If any calculated watermark values is larger than the maximum value that
1139 * can be programmed into the associated watermark register, that watermark
1140 * must be disabled.
1141 */
1142static bool g4x_check_srwm(struct drm_device *dev,
1143 int display_wm, int cursor_wm,
1144 const struct intel_watermark_params *display,
1145 const struct intel_watermark_params *cursor)
1146{
1147 DRM_DEBUG_KMS("SR watermark: display plane %d, cursor %d\n",
1148 display_wm, cursor_wm);
1149
1150 if (display_wm > display->max_wm) {
1151 DRM_DEBUG_KMS("display watermark is too large(%d/%ld), disabling\n",
1152 display_wm, display->max_wm);
1153 return false;
1154 }
1155
1156 if (cursor_wm > cursor->max_wm) {
1157 DRM_DEBUG_KMS("cursor watermark is too large(%d/%ld), disabling\n",
1158 cursor_wm, cursor->max_wm);
1159 return false;
1160 }
1161
1162 if (!(display_wm || cursor_wm)) {
1163 DRM_DEBUG_KMS("SR latency is 0, disabling\n");
1164 return false;
1165 }
1166
1167 return true;
1168}
1169
1170static bool g4x_compute_srwm(struct drm_device *dev,
1171 int plane,
1172 int latency_ns,
1173 const struct intel_watermark_params *display,
1174 const struct intel_watermark_params *cursor,
1175 int *display_wm, int *cursor_wm)
1176{
1177 struct drm_crtc *crtc;
1178 int hdisplay, htotal, pixel_size, clock;
1179 unsigned long line_time_us;
1180 int line_count, line_size;
1181 int small, large;
1182 int entries;
1183
1184 if (!latency_ns) {
1185 *display_wm = *cursor_wm = 0;
1186 return false;
1187 }
1188
1189 crtc = intel_get_crtc_for_plane(dev, plane);
1190 hdisplay = crtc->mode.hdisplay;
1191 htotal = crtc->mode.htotal;
1192 clock = crtc->mode.clock;
1193 pixel_size = crtc->fb->bits_per_pixel / 8;
1194
1195 line_time_us = (htotal * 1000) / clock;
1196 line_count = (latency_ns / line_time_us + 1000) / 1000;
1197 line_size = hdisplay * pixel_size;
1198
1199 /* Use the minimum of the small and large buffer method for primary */
1200 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1201 large = line_count * line_size;
1202
1203 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1204 *display_wm = entries + display->guard_size;
1205
1206 /* calculate the self-refresh watermark for display cursor */
1207 entries = line_count * pixel_size * 64;
1208 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1209 *cursor_wm = entries + cursor->guard_size;
1210
1211 return g4x_check_srwm(dev,
1212 *display_wm, *cursor_wm,
1213 display, cursor);
1214}
1215
1216static bool vlv_compute_drain_latency(struct drm_device *dev,
1217 int plane,
1218 int *plane_prec_mult,
1219 int *plane_dl,
1220 int *cursor_prec_mult,
1221 int *cursor_dl)
1222{
1223 struct drm_crtc *crtc;
1224 int clock, pixel_size;
1225 int entries;
1226
1227 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 1228 if (!intel_crtc_active(crtc))
b445e3b0
ED		 1229 return false;
1230
1231 clock = crtc->mode.clock; /* VESA DOT Clock */
1232 pixel_size = crtc->fb->bits_per_pixel / 8; /* BPP */
1233
1234 entries = (clock / 1000) * pixel_size;
1235 *plane_prec_mult = (entries > 256) ?
1236 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1237 *plane_dl = (64 * (*plane_prec_mult) * 4) / ((clock / 1000) *
1238 pixel_size);
1239
1240 entries = (clock / 1000) * 4; /* BPP is always 4 for cursor */
1241 *cursor_prec_mult = (entries > 256) ?
1242 DRAIN_LATENCY_PRECISION_32 : DRAIN_LATENCY_PRECISION_16;
1243 *cursor_dl = (64 * (*cursor_prec_mult) * 4) / ((clock / 1000) * 4);
1244
1245 return true;
1246}
1247
1248/*
1249 * Update drain latency registers of memory arbiter
1250 *
1251 * Valleyview SoC has a new memory arbiter and needs drain latency registers
1252 * to be programmed. Each plane has a drain latency multiplier and a drain
1253 * latency value.
1254 */
1255
1256static void vlv_update_drain_latency(struct drm_device *dev)
1257{
1258 struct drm_i915_private *dev_priv = dev->dev_private;
1259 int planea_prec, planea_dl, planeb_prec, planeb_dl;
1260 int cursora_prec, cursora_dl, cursorb_prec, cursorb_dl;
1261 int plane_prec_mult, cursor_prec_mult; /* Precision multiplier is
1262 either 16 or 32 */
1263
1264 /* For plane A, Cursor A */
1265 if (vlv_compute_drain_latency(dev, 0, &plane_prec_mult, &planea_dl,
1266 &cursor_prec_mult, &cursora_dl)) {
1267 cursora_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1268 DDL_CURSORA_PRECISION_32 : DDL_CURSORA_PRECISION_16;
1269 planea_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1270 DDL_PLANEA_PRECISION_32 : DDL_PLANEA_PRECISION_16;
1271
1272 I915_WRITE(VLV_DDL1, cursora_prec |
1273 (cursora_dl << DDL_CURSORA_SHIFT) |
1274 planea_prec | planea_dl);
1275 }
1276
1277 /* For plane B, Cursor B */
1278 if (vlv_compute_drain_latency(dev, 1, &plane_prec_mult, &planeb_dl,
1279 &cursor_prec_mult, &cursorb_dl)) {
1280 cursorb_prec = (cursor_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1281 DDL_CURSORB_PRECISION_32 : DDL_CURSORB_PRECISION_16;
1282 planeb_prec = (plane_prec_mult == DRAIN_LATENCY_PRECISION_32) ?
1283 DDL_PLANEB_PRECISION_32 : DDL_PLANEB_PRECISION_16;
1284
1285 I915_WRITE(VLV_DDL2, cursorb_prec |
1286 (cursorb_dl << DDL_CURSORB_SHIFT) |
1287 planeb_prec | planeb_dl);
1288 }
1289}
1290
1291#define single_plane_enabled(mask) is_power_of_2(mask)
1292
1fa61106 1293static void valleyview_update_wm(struct drm_device *dev)
b445e3b0
ED		 1294{
1295 static const int sr_latency_ns = 12000;
1296 struct drm_i915_private *dev_priv = dev->dev_private;
1297 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1298 int plane_sr, cursor_sr;
af6c4575 1299 int ignore_plane_sr, ignore_cursor_sr;
b445e3b0
ED		 1300 unsigned int enabled = 0;
1301
1302 vlv_update_drain_latency(dev);
1303
1304 if (g4x_compute_wm0(dev, 0,
1305 &valleyview_wm_info, latency_ns,
1306 &valleyview_cursor_wm_info, latency_ns,
1307 &planea_wm, &cursora_wm))
1308 enabled |= 1;
1309
1310 if (g4x_compute_wm0(dev, 1,
1311 &valleyview_wm_info, latency_ns,
1312 &valleyview_cursor_wm_info, latency_ns,
1313 &planeb_wm, &cursorb_wm))
1314 enabled |= 2;
1315
b445e3b0
ED		 1316 if (single_plane_enabled(enabled) &&
1317 g4x_compute_srwm(dev, ffs(enabled) - 1,
1318 sr_latency_ns,
1319 &valleyview_wm_info,
1320 &valleyview_cursor_wm_info,
af6c4575
CW		 1321 &plane_sr, &ignore_cursor_sr) &&
1322 g4x_compute_srwm(dev, ffs(enabled) - 1,
1323 2*sr_latency_ns,
1324 &valleyview_wm_info,
1325 &valleyview_cursor_wm_info,
52bd02d8 1326 &ignore_plane_sr, &cursor_sr)) {
b445e3b0 1327 I915_WRITE(FW_BLC_SELF_VLV, FW_CSPWRDWNEN);
52bd02d8 1328 } else {
b445e3b0
ED		 1329 I915_WRITE(FW_BLC_SELF_VLV,
1330 I915_READ(FW_BLC_SELF_VLV) & ~FW_CSPWRDWNEN);
52bd02d8
CW		 1331 plane_sr = cursor_sr = 0;
1332 }
b445e3b0
ED		 1333
1334 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1335 planea_wm, cursora_wm,
1336 planeb_wm, cursorb_wm,
1337 plane_sr, cursor_sr);
1338
1339 I915_WRITE(DSPFW1,
1340 (plane_sr << DSPFW_SR_SHIFT) |
1341 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1342 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1343 planea_wm);
1344 I915_WRITE(DSPFW2,
8c919b28 1345 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1346 (cursora_wm << DSPFW_CURSORA_SHIFT));
1347 I915_WRITE(DSPFW3,
8c919b28
CW		 1348 (I915_READ(DSPFW3) & ~DSPFW_CURSOR_SR_MASK) |
1349 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
b445e3b0
ED		 1350}
1351
1fa61106 1352static void g4x_update_wm(struct drm_device *dev)
b445e3b0
ED		 1353{
1354 static const int sr_latency_ns = 12000;
1355 struct drm_i915_private *dev_priv = dev->dev_private;
1356 int planea_wm, planeb_wm, cursora_wm, cursorb_wm;
1357 int plane_sr, cursor_sr;
1358 unsigned int enabled = 0;
1359
1360 if (g4x_compute_wm0(dev, 0,
1361 &g4x_wm_info, latency_ns,
1362 &g4x_cursor_wm_info, latency_ns,
1363 &planea_wm, &cursora_wm))
1364 enabled |= 1;
1365
1366 if (g4x_compute_wm0(dev, 1,
1367 &g4x_wm_info, latency_ns,
1368 &g4x_cursor_wm_info, latency_ns,
1369 &planeb_wm, &cursorb_wm))
1370 enabled |= 2;
1371
b445e3b0
ED		 1372 if (single_plane_enabled(enabled) &&
1373 g4x_compute_srwm(dev, ffs(enabled) - 1,
1374 sr_latency_ns,
1375 &g4x_wm_info,
1376 &g4x_cursor_wm_info,
52bd02d8 1377 &plane_sr, &cursor_sr)) {
b445e3b0 1378 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
52bd02d8 1379 } else {
b445e3b0
ED		 1380 I915_WRITE(FW_BLC_SELF,
1381 I915_READ(FW_BLC_SELF) & ~FW_BLC_SELF_EN);
52bd02d8
CW		 1382 plane_sr = cursor_sr = 0;
1383 }
b445e3b0
ED		 1384
1385 DRM_DEBUG_KMS("Setting FIFO watermarks - A: plane=%d, cursor=%d, B: plane=%d, cursor=%d, SR: plane=%d, cursor=%d\n",
1386 planea_wm, cursora_wm,
1387 planeb_wm, cursorb_wm,
1388 plane_sr, cursor_sr);
1389
1390 I915_WRITE(DSPFW1,
1391 (plane_sr << DSPFW_SR_SHIFT) |
1392 (cursorb_wm << DSPFW_CURSORB_SHIFT) |
1393 (planeb_wm << DSPFW_PLANEB_SHIFT) |
1394 planea_wm);
1395 I915_WRITE(DSPFW2,
8c919b28 1396 (I915_READ(DSPFW2) & ~DSPFW_CURSORA_MASK) |
b445e3b0
ED		 1397 (cursora_wm << DSPFW_CURSORA_SHIFT));
1398 /* HPLL off in SR has some issues on G4x... disable it */
1399 I915_WRITE(DSPFW3,
8c919b28 1400 (I915_READ(DSPFW3) & ~(DSPFW_HPLL_SR_EN | DSPFW_CURSOR_SR_MASK)) |
b445e3b0
ED		 1401 (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1402}
1403
1fa61106 1404static void i965_update_wm(struct drm_device *dev)
b445e3b0
ED		 1405{
1406 struct drm_i915_private *dev_priv = dev->dev_private;
1407 struct drm_crtc *crtc;
1408 int srwm = 1;
1409 int cursor_sr = 16;
1410
1411 /* Calc sr entries for one plane configs */
1412 crtc = single_enabled_crtc(dev);
1413 if (crtc) {
1414 /* self-refresh has much higher latency */
1415 static const int sr_latency_ns = 12000;
1416 int clock = crtc->mode.clock;
1417 int htotal = crtc->mode.htotal;
1418 int hdisplay = crtc->mode.hdisplay;
1419 int pixel_size = crtc->fb->bits_per_pixel / 8;
1420 unsigned long line_time_us;
1421 int entries;
1422
1423 line_time_us = ((htotal * 1000) / clock);
1424
1425 /* Use ns/us then divide to preserve precision */
1426 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1427 pixel_size * hdisplay;
1428 entries = DIV_ROUND_UP(entries, I915_FIFO_LINE_SIZE);
1429 srwm = I965_FIFO_SIZE - entries;
1430 if (srwm < 0)
1431 srwm = 1;
1432 srwm &= 0x1ff;
1433 DRM_DEBUG_KMS("self-refresh entries: %d, wm: %d\n",
1434 entries, srwm);
1435
1436 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1437 pixel_size * 64;
1438 entries = DIV_ROUND_UP(entries,
1439 i965_cursor_wm_info.cacheline_size);
1440 cursor_sr = i965_cursor_wm_info.fifo_size -
1441 (entries + i965_cursor_wm_info.guard_size);
1442
1443 if (cursor_sr > i965_cursor_wm_info.max_wm)
1444 cursor_sr = i965_cursor_wm_info.max_wm;
1445
1446 DRM_DEBUG_KMS("self-refresh watermark: display plane %d "
1447 "cursor %d\n", srwm, cursor_sr);
1448
1449 if (IS_CRESTLINE(dev))
1450 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN);
1451 } else {
1452 /* Turn off self refresh if both pipes are enabled */
1453 if (IS_CRESTLINE(dev))
1454 I915_WRITE(FW_BLC_SELF, I915_READ(FW_BLC_SELF)
1455 & ~FW_BLC_SELF_EN);
1456 }
1457
1458 DRM_DEBUG_KMS("Setting FIFO watermarks - A: 8, B: 8, C: 8, SR %d\n",
1459 srwm);
1460
1461 /* 965 has limitations... */
1462 I915_WRITE(DSPFW1, (srwm << DSPFW_SR_SHIFT) |
1463 (8 << 16) | (8 << 8) | (8 << 0));
1464 I915_WRITE(DSPFW2, (8 << 8) | (8 << 0));
1465 /* update cursor SR watermark */
1466 I915_WRITE(DSPFW3, (cursor_sr << DSPFW_CURSOR_SR_SHIFT));
1467}
1468
1fa61106 1469static void i9xx_update_wm(struct drm_device *dev)
b445e3b0
ED		 1470{
1471 struct drm_i915_private *dev_priv = dev->dev_private;
1472 const struct intel_watermark_params *wm_info;
1473 uint32_t fwater_lo;
1474 uint32_t fwater_hi;
1475 int cwm, srwm = 1;
1476 int fifo_size;
1477 int planea_wm, planeb_wm;
1478 struct drm_crtc *crtc, *enabled = NULL;
1479
1480 if (IS_I945GM(dev))
1481 wm_info = &i945_wm_info;
1482 else if (!IS_GEN2(dev))
1483 wm_info = &i915_wm_info;
1484 else
1485 wm_info = &i855_wm_info;
1486
1487 fifo_size = dev_priv->display.get_fifo_size(dev, 0);
1488 crtc = intel_get_crtc_for_plane(dev, 0);
3490ea5d 1489 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1490 int cpp = crtc->fb->bits_per_pixel / 8;
1491 if (IS_GEN2(dev))
1492 cpp = 4;
1493
b445e3b0 1494 planea_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1495 wm_info, fifo_size, cpp,
b445e3b0
ED		 1496 latency_ns);
1497 enabled = crtc;
1498 } else
1499 planea_wm = fifo_size - wm_info->guard_size;
1500
1501 fifo_size = dev_priv->display.get_fifo_size(dev, 1);
1502 crtc = intel_get_crtc_for_plane(dev, 1);
3490ea5d 1503 if (intel_crtc_active(crtc)) {
b9e0bda3
CW		 1504 int cpp = crtc->fb->bits_per_pixel / 8;
1505 if (IS_GEN2(dev))
1506 cpp = 4;
1507
b445e3b0 1508 planeb_wm = intel_calculate_wm(crtc->mode.clock,
b9e0bda3 1509 wm_info, fifo_size, cpp,
b445e3b0
ED		 1510 latency_ns);
1511 if (enabled == NULL)
1512 enabled = crtc;
1513 else
1514 enabled = NULL;
1515 } else
1516 planeb_wm = fifo_size - wm_info->guard_size;
1517
1518 DRM_DEBUG_KMS("FIFO watermarks - A: %d, B: %d\n", planea_wm, planeb_wm);
1519
1520 /*
1521 * Overlay gets an aggressive default since video jitter is bad.
1522 */
1523 cwm = 2;
1524
1525 /* Play safe and disable self-refresh before adjusting watermarks. */
1526 if (IS_I945G(dev) || IS_I945GM(dev))
1527 I915_WRITE(FW_BLC_SELF, FW_BLC_SELF_EN_MASK | 0);
1528 else if (IS_I915GM(dev))
1529 I915_WRITE(INSTPM, I915_READ(INSTPM) & ~INSTPM_SELF_EN);
1530
1531 /* Calc sr entries for one plane configs */
1532 if (HAS_FW_BLC(dev) && enabled) {
1533 /* self-refresh has much higher latency */
1534 static const int sr_latency_ns = 6000;
1535 int clock = enabled->mode.clock;
1536 int htotal = enabled->mode.htotal;
1537 int hdisplay = enabled->mode.hdisplay;
1538 int pixel_size = enabled->fb->bits_per_pixel / 8;
1539 unsigned long line_time_us;
1540 int entries;
1541
1542 line_time_us = (htotal * 1000) / clock;
1543
1544 /* Use ns/us then divide to preserve precision */
1545 entries = (((sr_latency_ns / line_time_us) + 1000) / 1000) *
1546 pixel_size * hdisplay;
1547 entries = DIV_ROUND_UP(entries, wm_info->cacheline_size);
1548 DRM_DEBUG_KMS("self-refresh entries: %d\n", entries);
1549 srwm = wm_info->fifo_size - entries;
1550 if (srwm < 0)
1551 srwm = 1;
1552
1553 if (IS_I945G(dev) || IS_I945GM(dev))
1554 I915_WRITE(FW_BLC_SELF,
1555 FW_BLC_SELF_FIFO_MASK | (srwm & 0xff));
1556 else if (IS_I915GM(dev))
1557 I915_WRITE(FW_BLC_SELF, srwm & 0x3f);
1558 }
1559
1560 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d, B: %d, C: %d, SR %d\n",
1561 planea_wm, planeb_wm, cwm, srwm);
1562
1563 fwater_lo = ((planeb_wm & 0x3f) << 16) | (planea_wm & 0x3f);
1564 fwater_hi = (cwm & 0x1f);
1565
1566 /* Set request length to 8 cachelines per fetch */
1567 fwater_lo = fwater_lo | (1 << 24) | (1 << 8);
1568 fwater_hi = fwater_hi | (1 << 8);
1569
1570 I915_WRITE(FW_BLC, fwater_lo);
1571 I915_WRITE(FW_BLC2, fwater_hi);
1572
1573 if (HAS_FW_BLC(dev)) {
1574 if (enabled) {
1575 if (IS_I945G(dev) || IS_I945GM(dev))
1576 I915_WRITE(FW_BLC_SELF,
1577 FW_BLC_SELF_EN_MASK | FW_BLC_SELF_EN);
1578 else if (IS_I915GM(dev))
1579 I915_WRITE(INSTPM, I915_READ(INSTPM) | INSTPM_SELF_EN);
1580 DRM_DEBUG_KMS("memory self refresh enabled\n");
1581 } else
1582 DRM_DEBUG_KMS("memory self refresh disabled\n");
1583 }
1584}
1585
1fa61106 1586static void i830_update_wm(struct drm_device *dev)
b445e3b0
ED		 1587{
1588 struct drm_i915_private *dev_priv = dev->dev_private;
1589 struct drm_crtc *crtc;
1590 uint32_t fwater_lo;
1591 int planea_wm;
1592
1593 crtc = single_enabled_crtc(dev);
1594 if (crtc == NULL)
1595 return;
1596
1597 planea_wm = intel_calculate_wm(crtc->mode.clock, &i830_wm_info,
1598 dev_priv->display.get_fifo_size(dev, 0),
b9e0bda3 1599 4, latency_ns);
b445e3b0
ED		 1600 fwater_lo = I915_READ(FW_BLC) & ~0xfff;
1601 fwater_lo |= (3<<8) | planea_wm;
1602
1603 DRM_DEBUG_KMS("Setting FIFO watermarks - A: %d\n", planea_wm);
1604
1605 I915_WRITE(FW_BLC, fwater_lo);
1606}
1607
1608#define ILK_LP0_PLANE_LATENCY 700
1609#define ILK_LP0_CURSOR_LATENCY 1300
1610
1611/*
1612 * Check the wm result.
1613 *
1614 * If any calculated watermark values is larger than the maximum value that
1615 * can be programmed into the associated watermark register, that watermark
1616 * must be disabled.
1617 */
1618static bool ironlake_check_srwm(struct drm_device *dev, int level,
1619 int fbc_wm, int display_wm, int cursor_wm,
1620 const struct intel_watermark_params *display,
1621 const struct intel_watermark_params *cursor)
1622{
1623 struct drm_i915_private *dev_priv = dev->dev_private;
1624
1625 DRM_DEBUG_KMS("watermark %d: display plane %d, fbc lines %d,"
1626 " cursor %d\n", level, display_wm, fbc_wm, cursor_wm);
1627
1628 if (fbc_wm > SNB_FBC_MAX_SRWM) {
1629 DRM_DEBUG_KMS("fbc watermark(%d) is too large(%d), disabling wm%d+\n",
1630 fbc_wm, SNB_FBC_MAX_SRWM, level);
1631
1632 /* fbc has it's own way to disable FBC WM */
1633 I915_WRITE(DISP_ARB_CTL,
1634 I915_READ(DISP_ARB_CTL) | DISP_FBC_WM_DIS);
1635 return false;
1636 }
1637
1638 if (display_wm > display->max_wm) {
1639 DRM_DEBUG_KMS("display watermark(%d) is too large(%d), disabling wm%d+\n",
1640 display_wm, SNB_DISPLAY_MAX_SRWM, level);
1641 return false;
1642 }
1643
1644 if (cursor_wm > cursor->max_wm) {
1645 DRM_DEBUG_KMS("cursor watermark(%d) is too large(%d), disabling wm%d+\n",
1646 cursor_wm, SNB_CURSOR_MAX_SRWM, level);
1647 return false;
1648 }
1649
1650 if (!(fbc_wm || display_wm || cursor_wm)) {
1651 DRM_DEBUG_KMS("latency %d is 0, disabling wm%d+\n", level, level);
1652 return false;
1653 }
1654
1655 return true;
1656}
1657
1658/*
1659 * Compute watermark values of WM[1-3],
1660 */
1661static bool ironlake_compute_srwm(struct drm_device *dev, int level, int plane,
1662 int latency_ns,
1663 const struct intel_watermark_params *display,
1664 const struct intel_watermark_params *cursor,
1665 int *fbc_wm, int *display_wm, int *cursor_wm)
1666{
1667 struct drm_crtc *crtc;
1668 unsigned long line_time_us;
1669 int hdisplay, htotal, pixel_size, clock;
1670 int line_count, line_size;
1671 int small, large;
1672 int entries;
1673
1674 if (!latency_ns) {
1675 *fbc_wm = *display_wm = *cursor_wm = 0;
1676 return false;
1677 }
1678
1679 crtc = intel_get_crtc_for_plane(dev, plane);
1680 hdisplay = crtc->mode.hdisplay;
1681 htotal = crtc->mode.htotal;
1682 clock = crtc->mode.clock;
1683 pixel_size = crtc->fb->bits_per_pixel / 8;
1684
1685 line_time_us = (htotal * 1000) / clock;
1686 line_count = (latency_ns / line_time_us + 1000) / 1000;
1687 line_size = hdisplay * pixel_size;
1688
1689 /* Use the minimum of the small and large buffer method for primary */
1690 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
1691 large = line_count * line_size;
1692
1693 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
1694 *display_wm = entries + display->guard_size;
1695
1696 /*
1697 * Spec says:
1698 * FBC WM = ((Final Primary WM * 64) / number of bytes per line) + 2
1699 */
1700 *fbc_wm = DIV_ROUND_UP(*display_wm * 64, line_size) + 2;
1701
1702 /* calculate the self-refresh watermark for display cursor */
1703 entries = line_count * pixel_size * 64;
1704 entries = DIV_ROUND_UP(entries, cursor->cacheline_size);
1705 *cursor_wm = entries + cursor->guard_size;
1706
1707 return ironlake_check_srwm(dev, level,
1708 *fbc_wm, *display_wm, *cursor_wm,
1709 display, cursor);
1710}
1711
1fa61106 1712static void ironlake_update_wm(struct drm_device *dev)
b445e3b0
ED		 1713{
1714 struct drm_i915_private *dev_priv = dev->dev_private;
1715 int fbc_wm, plane_wm, cursor_wm;
1716 unsigned int enabled;
1717
1718 enabled = 0;
1719 if (g4x_compute_wm0(dev, 0,
1720 &ironlake_display_wm_info,
1721 ILK_LP0_PLANE_LATENCY,
1722 &ironlake_cursor_wm_info,
1723 ILK_LP0_CURSOR_LATENCY,
1724 &plane_wm, &cursor_wm)) {
1725 I915_WRITE(WM0_PIPEA_ILK,
1726 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1727 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1728 " plane %d, " "cursor: %d\n",
1729 plane_wm, cursor_wm);
1730 enabled |= 1;
1731 }
1732
1733 if (g4x_compute_wm0(dev, 1,
1734 &ironlake_display_wm_info,
1735 ILK_LP0_PLANE_LATENCY,
1736 &ironlake_cursor_wm_info,
1737 ILK_LP0_CURSOR_LATENCY,
1738 &plane_wm, &cursor_wm)) {
1739 I915_WRITE(WM0_PIPEB_ILK,
1740 (plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm);
1741 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1742 " plane %d, cursor: %d\n",
1743 plane_wm, cursor_wm);
1744 enabled |= 2;
1745 }
1746
1747 /*
1748 * Calculate and update the self-refresh watermark only when one
1749 * display plane is used.
1750 */
1751 I915_WRITE(WM3_LP_ILK, 0);
1752 I915_WRITE(WM2_LP_ILK, 0);
1753 I915_WRITE(WM1_LP_ILK, 0);
1754
1755 if (!single_plane_enabled(enabled))
1756 return;
1757 enabled = ffs(enabled) - 1;
1758
1759 /* WM1 */
1760 if (!ironlake_compute_srwm(dev, 1, enabled,
1761 ILK_READ_WM1_LATENCY() * 500,
1762 &ironlake_display_srwm_info,
1763 &ironlake_cursor_srwm_info,
1764 &fbc_wm, &plane_wm, &cursor_wm))
1765 return;
1766
1767 I915_WRITE(WM1_LP_ILK,
1768 WM1_LP_SR_EN |
1769 (ILK_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1770 (fbc_wm << WM1_LP_FBC_SHIFT) |
1771 (plane_wm << WM1_LP_SR_SHIFT) |
1772 cursor_wm);
1773
1774 /* WM2 */
1775 if (!ironlake_compute_srwm(dev, 2, enabled,
1776 ILK_READ_WM2_LATENCY() * 500,
1777 &ironlake_display_srwm_info,
1778 &ironlake_cursor_srwm_info,
1779 &fbc_wm, &plane_wm, &cursor_wm))
1780 return;
1781
1782 I915_WRITE(WM2_LP_ILK,
1783 WM2_LP_EN |
1784 (ILK_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1785 (fbc_wm << WM1_LP_FBC_SHIFT) |
1786 (plane_wm << WM1_LP_SR_SHIFT) |
1787 cursor_wm);
1788
1789 /*
1790 * WM3 is unsupported on ILK, probably because we don't have latency
1791 * data for that power state
1792 */
1793}
1794
1fa61106 1795static void sandybridge_update_wm(struct drm_device *dev)
b445e3b0
ED		 1796{
1797 struct drm_i915_private *dev_priv = dev->dev_private;
1798 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1799 u32 val;
1800 int fbc_wm, plane_wm, cursor_wm;
1801 unsigned int enabled;
1802
1803 enabled = 0;
1804 if (g4x_compute_wm0(dev, 0,
1805 &sandybridge_display_wm_info, latency,
1806 &sandybridge_cursor_wm_info, latency,
1807 &plane_wm, &cursor_wm)) {
1808 val = I915_READ(WM0_PIPEA_ILK);
1809 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1810 I915_WRITE(WM0_PIPEA_ILK, val |
1811 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1812 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1813 " plane %d, " "cursor: %d\n",
1814 plane_wm, cursor_wm);
1815 enabled |= 1;
1816 }
1817
1818 if (g4x_compute_wm0(dev, 1,
1819 &sandybridge_display_wm_info, latency,
1820 &sandybridge_cursor_wm_info, latency,
1821 &plane_wm, &cursor_wm)) {
1822 val = I915_READ(WM0_PIPEB_ILK);
1823 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1824 I915_WRITE(WM0_PIPEB_ILK, val |
1825 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1826 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1827 " plane %d, cursor: %d\n",
1828 plane_wm, cursor_wm);
1829 enabled |= 2;
1830 }
1831
c43d0188
CW		 1832 /*
1833 * Calculate and update the self-refresh watermark only when one
1834 * display plane is used.
1835 *
1836 * SNB support 3 levels of watermark.
1837 *
1838 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1839 * and disabled in the descending order
1840 *
1841 */
1842 I915_WRITE(WM3_LP_ILK, 0);
1843 I915_WRITE(WM2_LP_ILK, 0);
1844 I915_WRITE(WM1_LP_ILK, 0);
1845
1846 if (!single_plane_enabled(enabled) ||
1847 dev_priv->sprite_scaling_enabled)
1848 return;
1849 enabled = ffs(enabled) - 1;
1850
1851 /* WM1 */
1852 if (!ironlake_compute_srwm(dev, 1, enabled,
1853 SNB_READ_WM1_LATENCY() * 500,
1854 &sandybridge_display_srwm_info,
1855 &sandybridge_cursor_srwm_info,
1856 &fbc_wm, &plane_wm, &cursor_wm))
1857 return;
1858
1859 I915_WRITE(WM1_LP_ILK,
1860 WM1_LP_SR_EN |
1861 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1862 (fbc_wm << WM1_LP_FBC_SHIFT) |
1863 (plane_wm << WM1_LP_SR_SHIFT) |
1864 cursor_wm);
1865
1866 /* WM2 */
1867 if (!ironlake_compute_srwm(dev, 2, enabled,
1868 SNB_READ_WM2_LATENCY() * 500,
1869 &sandybridge_display_srwm_info,
1870 &sandybridge_cursor_srwm_info,
1871 &fbc_wm, &plane_wm, &cursor_wm))
1872 return;
1873
1874 I915_WRITE(WM2_LP_ILK,
1875 WM2_LP_EN |
1876 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1877 (fbc_wm << WM1_LP_FBC_SHIFT) |
1878 (plane_wm << WM1_LP_SR_SHIFT) |
1879 cursor_wm);
1880
1881 /* WM3 */
1882 if (!ironlake_compute_srwm(dev, 3, enabled,
1883 SNB_READ_WM3_LATENCY() * 500,
1884 &sandybridge_display_srwm_info,
1885 &sandybridge_cursor_srwm_info,
1886 &fbc_wm, &plane_wm, &cursor_wm))
1887 return;
1888
1889 I915_WRITE(WM3_LP_ILK,
1890 WM3_LP_EN |
1891 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1892 (fbc_wm << WM1_LP_FBC_SHIFT) |
1893 (plane_wm << WM1_LP_SR_SHIFT) |
1894 cursor_wm);
1895}
1896
1897static void ivybridge_update_wm(struct drm_device *dev)
1898{
1899 struct drm_i915_private *dev_priv = dev->dev_private;
1900 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
1901 u32 val;
1902 int fbc_wm, plane_wm, cursor_wm;
1903 int ignore_fbc_wm, ignore_plane_wm, ignore_cursor_wm;
1904 unsigned int enabled;
1905
1906 enabled = 0;
1907 if (g4x_compute_wm0(dev, 0,
1908 &sandybridge_display_wm_info, latency,
1909 &sandybridge_cursor_wm_info, latency,
1910 &plane_wm, &cursor_wm)) {
1911 val = I915_READ(WM0_PIPEA_ILK);
1912 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1913 I915_WRITE(WM0_PIPEA_ILK, val |
1914 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1915 DRM_DEBUG_KMS("FIFO watermarks For pipe A -"
1916 " plane %d, " "cursor: %d\n",
1917 plane_wm, cursor_wm);
1918 enabled |= 1;
1919 }
1920
1921 if (g4x_compute_wm0(dev, 1,
1922 &sandybridge_display_wm_info, latency,
1923 &sandybridge_cursor_wm_info, latency,
1924 &plane_wm, &cursor_wm)) {
1925 val = I915_READ(WM0_PIPEB_ILK);
1926 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1927 I915_WRITE(WM0_PIPEB_ILK, val |
1928 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1929 DRM_DEBUG_KMS("FIFO watermarks For pipe B -"
1930 " plane %d, cursor: %d\n",
1931 plane_wm, cursor_wm);
1932 enabled |= 2;
1933 }
1934
1935 if (g4x_compute_wm0(dev, 2,
b445e3b0
ED		 1936 &sandybridge_display_wm_info, latency,
1937 &sandybridge_cursor_wm_info, latency,
1938 &plane_wm, &cursor_wm)) {
1939 val = I915_READ(WM0_PIPEC_IVB);
1940 val &= ~(WM0_PIPE_PLANE_MASK | WM0_PIPE_CURSOR_MASK);
1941 I915_WRITE(WM0_PIPEC_IVB, val |
1942 ((plane_wm << WM0_PIPE_PLANE_SHIFT) | cursor_wm));
1943 DRM_DEBUG_KMS("FIFO watermarks For pipe C -"
1944 " plane %d, cursor: %d\n",
1945 plane_wm, cursor_wm);
1946 enabled |= 3;
1947 }
1948
1949 /*
1950 * Calculate and update the self-refresh watermark only when one
1951 * display plane is used.
1952 *
1953 * SNB support 3 levels of watermark.
1954 *
1955 * WM1/WM2/WM2 watermarks have to be enabled in the ascending order,
1956 * and disabled in the descending order
1957 *
1958 */
1959 I915_WRITE(WM3_LP_ILK, 0);
1960 I915_WRITE(WM2_LP_ILK, 0);
1961 I915_WRITE(WM1_LP_ILK, 0);
1962
1963 if (!single_plane_enabled(enabled) ||
1964 dev_priv->sprite_scaling_enabled)
1965 return;
1966 enabled = ffs(enabled) - 1;
1967
1968 /* WM1 */
1969 if (!ironlake_compute_srwm(dev, 1, enabled,
1970 SNB_READ_WM1_LATENCY() * 500,
1971 &sandybridge_display_srwm_info,
1972 &sandybridge_cursor_srwm_info,
1973 &fbc_wm, &plane_wm, &cursor_wm))
1974 return;
1975
1976 I915_WRITE(WM1_LP_ILK,
1977 WM1_LP_SR_EN |
1978 (SNB_READ_WM1_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1979 (fbc_wm << WM1_LP_FBC_SHIFT) |
1980 (plane_wm << WM1_LP_SR_SHIFT) |
1981 cursor_wm);
1982
1983 /* WM2 */
1984 if (!ironlake_compute_srwm(dev, 2, enabled,
1985 SNB_READ_WM2_LATENCY() * 500,
1986 &sandybridge_display_srwm_info,
1987 &sandybridge_cursor_srwm_info,
1988 &fbc_wm, &plane_wm, &cursor_wm))
1989 return;
1990
1991 I915_WRITE(WM2_LP_ILK,
1992 WM2_LP_EN |
1993 (SNB_READ_WM2_LATENCY() << WM1_LP_LATENCY_SHIFT) |
1994 (fbc_wm << WM1_LP_FBC_SHIFT) |
1995 (plane_wm << WM1_LP_SR_SHIFT) |
1996 cursor_wm);
1997
c43d0188 1998 /* WM3, note we have to correct the cursor latency */
b445e3b0
ED		 1999 if (!ironlake_compute_srwm(dev, 3, enabled,
2000 SNB_READ_WM3_LATENCY() * 500,
2001 &sandybridge_display_srwm_info,
2002 &sandybridge_cursor_srwm_info,
c43d0188
CW		 2003 &fbc_wm, &plane_wm, &ignore_cursor_wm) ||
2004 !ironlake_compute_srwm(dev, 3, enabled,
2005 2 * SNB_READ_WM3_LATENCY() * 500,
2006 &sandybridge_display_srwm_info,
2007 &sandybridge_cursor_srwm_info,
2008 &ignore_fbc_wm, &ignore_plane_wm, &cursor_wm))
b445e3b0
ED		 2009 return;
2010
2011 I915_WRITE(WM3_LP_ILK,
2012 WM3_LP_EN |
2013 (SNB_READ_WM3_LATENCY() << WM1_LP_LATENCY_SHIFT) |
2014 (fbc_wm << WM1_LP_FBC_SHIFT) |
2015 (plane_wm << WM1_LP_SR_SHIFT) |
2016 cursor_wm);
2017}
2018
1f8eeabf
ED		 2019static void
2020haswell_update_linetime_wm(struct drm_device *dev, int pipe,
2021 struct drm_display_mode *mode)
2022{
2023 struct drm_i915_private *dev_priv = dev->dev_private;
2024 u32 temp;
2025
2026 temp = I915_READ(PIPE_WM_LINETIME(pipe));
2027 temp &= ~PIPE_WM_LINETIME_MASK;
2028
2029 /* The WM are computed with base on how long it takes to fill a single
2030 * row at the given clock rate, multiplied by 8.
2031 * */
2032 temp |= PIPE_WM_LINETIME_TIME(
2033 ((mode->crtc_hdisplay * 1000) / mode->clock) * 8);
2034
2035 /* IPS watermarks are only used by pipe A, and are ignored by
2036 * pipes B and C. They are calculated similarly to the common
2037 * linetime values, except that we are using CD clock frequency
2038 * in MHz instead of pixel rate for the division.
2039 *
2040 * This is a placeholder for the IPS watermark calculation code.
2041 */
2042
2043 I915_WRITE(PIPE_WM_LINETIME(pipe), temp);
2044}
2045
b445e3b0
ED		 2046static bool
2047sandybridge_compute_sprite_wm(struct drm_device *dev, int plane,
2048 uint32_t sprite_width, int pixel_size,
2049 const struct intel_watermark_params *display,
2050 int display_latency_ns, int *sprite_wm)
2051{
2052 struct drm_crtc *crtc;
2053 int clock;
2054 int entries, tlb_miss;
2055
2056 crtc = intel_get_crtc_for_plane(dev, plane);
3490ea5d 2057 if (!intel_crtc_active(crtc)) {
b445e3b0
ED		 2058 *sprite_wm = display->guard_size;
2059 return false;
2060 }
2061
2062 clock = crtc->mode.clock;
2063
2064 /* Use the small buffer method to calculate the sprite watermark */
2065 entries = ((clock * pixel_size / 1000) * display_latency_ns) / 1000;
2066 tlb_miss = display->fifo_size*display->cacheline_size -
2067 sprite_width * 8;
2068 if (tlb_miss > 0)
2069 entries += tlb_miss;
2070 entries = DIV_ROUND_UP(entries, display->cacheline_size);
2071 *sprite_wm = entries + display->guard_size;
2072 if (*sprite_wm > (int)display->max_wm)
2073 *sprite_wm = display->max_wm;
2074
2075 return true;
2076}
2077
2078static bool
2079sandybridge_compute_sprite_srwm(struct drm_device *dev, int plane,
2080 uint32_t sprite_width, int pixel_size,
2081 const struct intel_watermark_params *display,
2082 int latency_ns, int *sprite_wm)
2083{
2084 struct drm_crtc *crtc;
2085 unsigned long line_time_us;
2086 int clock;
2087 int line_count, line_size;
2088 int small, large;
2089 int entries;
2090
2091 if (!latency_ns) {
2092 *sprite_wm = 0;
2093 return false;
2094 }
2095
2096 crtc = intel_get_crtc_for_plane(dev, plane);
2097 clock = crtc->mode.clock;
2098 if (!clock) {
2099 *sprite_wm = 0;
2100 return false;
2101 }
2102
2103 line_time_us = (sprite_width * 1000) / clock;
2104 if (!line_time_us) {
2105 *sprite_wm = 0;
2106 return false;
2107 }
2108
2109 line_count = (latency_ns / line_time_us + 1000) / 1000;
2110 line_size = sprite_width * pixel_size;
2111
2112 /* Use the minimum of the small and large buffer method for primary */
2113 small = ((clock * pixel_size / 1000) * latency_ns) / 1000;
2114 large = line_count * line_size;
2115
2116 entries = DIV_ROUND_UP(min(small, large), display->cacheline_size);
2117 *sprite_wm = entries + display->guard_size;
2118
2119 return *sprite_wm > 0x3ff ? false : true;
2120}
2121
1fa61106 2122static void sandybridge_update_sprite_wm(struct drm_device *dev, int pipe,
b445e3b0
ED		 2123 uint32_t sprite_width, int pixel_size)
2124{
2125 struct drm_i915_private *dev_priv = dev->dev_private;
2126 int latency = SNB_READ_WM0_LATENCY() * 100; /* In unit 0.1us */
2127 u32 val;
2128 int sprite_wm, reg;
2129 int ret;
2130
2131 switch (pipe) {
2132 case 0:
2133 reg = WM0_PIPEA_ILK;
2134 break;
2135 case 1:
2136 reg = WM0_PIPEB_ILK;
2137 break;
2138 case 2:
2139 reg = WM0_PIPEC_IVB;
2140 break;
2141 default:
2142 return; /* bad pipe */
2143 }
2144
2145 ret = sandybridge_compute_sprite_wm(dev, pipe, sprite_width, pixel_size,
2146 &sandybridge_display_wm_info,
2147 latency, &sprite_wm);
2148 if (!ret) {
2149 DRM_DEBUG_KMS("failed to compute sprite wm for pipe %d\n",
2150 pipe);
2151 return;
2152 }
2153
2154 val = I915_READ(reg);
2155 val &= ~WM0_PIPE_SPRITE_MASK;
2156 I915_WRITE(reg, val | (sprite_wm << WM0_PIPE_SPRITE_SHIFT));
2157 DRM_DEBUG_KMS("sprite watermarks For pipe %d - %d\n", pipe, sprite_wm);
2158
2159
2160 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2161 pixel_size,
2162 &sandybridge_display_srwm_info,
2163 SNB_READ_WM1_LATENCY() * 500,
2164 &sprite_wm);
2165 if (!ret) {
2166 DRM_DEBUG_KMS("failed to compute sprite lp1 wm on pipe %d\n",
2167 pipe);
2168 return;
2169 }
2170 I915_WRITE(WM1S_LP_ILK, sprite_wm);
2171
2172 /* Only IVB has two more LP watermarks for sprite */
2173 if (!IS_IVYBRIDGE(dev))
2174 return;
2175
2176 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2177 pixel_size,
2178 &sandybridge_display_srwm_info,
2179 SNB_READ_WM2_LATENCY() * 500,
2180 &sprite_wm);
2181 if (!ret) {
2182 DRM_DEBUG_KMS("failed to compute sprite lp2 wm on pipe %d\n",
2183 pipe);
2184 return;
2185 }
2186 I915_WRITE(WM2S_LP_IVB, sprite_wm);
2187
2188 ret = sandybridge_compute_sprite_srwm(dev, pipe, sprite_width,
2189 pixel_size,
2190 &sandybridge_display_srwm_info,
2191 SNB_READ_WM3_LATENCY() * 500,
2192 &sprite_wm);
2193 if (!ret) {
2194 DRM_DEBUG_KMS("failed to compute sprite lp3 wm on pipe %d\n",
2195 pipe);
2196 return;
2197 }
2198 I915_WRITE(WM3S_LP_IVB, sprite_wm);
2199}
2200
2201/**
2202 * intel_update_watermarks - update FIFO watermark values based on current modes
2203 *
2204 * Calculate watermark values for the various WM regs based on current mode
2205 * and plane configuration.
2206 *
2207 * There are several cases to deal with here:
2208 * - normal (i.e. non-self-refresh)
2209 * - self-refresh (SR) mode
2210 * - lines are large relative to FIFO size (buffer can hold up to 2)
2211 * - lines are small relative to FIFO size (buffer can hold more than 2
2212 * lines), so need to account for TLB latency
2213 *
2214 * The normal calculation is:
2215 * watermark = dotclock * bytes per pixel * latency
2216 * where latency is platform & configuration dependent (we assume pessimal
2217 * values here).
2218 *
2219 * The SR calculation is:
2220 * watermark = (trunc(latency/line time)+1) * surface width *
2221 * bytes per pixel
2222 * where
2223 * line time = htotal / dotclock
2224 * surface width = hdisplay for normal plane and 64 for cursor
2225 * and latency is assumed to be high, as above.
2226 *
2227 * The final value programmed to the register should always be rounded up,
2228 * and include an extra 2 entries to account for clock crossings.
2229 *
2230 * We don't use the sprite, so we can ignore that. And on Crestline we have
2231 * to set the non-SR watermarks to 8.
2232 */
2233void intel_update_watermarks(struct drm_device *dev)
2234{
2235 struct drm_i915_private *dev_priv = dev->dev_private;
2236
2237 if (dev_priv->display.update_wm)
2238 dev_priv->display.update_wm(dev);
2239}
2240
1f8eeabf
ED		 2241void intel_update_linetime_watermarks(struct drm_device *dev,
2242 int pipe, struct drm_display_mode *mode)
2243{
2244 struct drm_i915_private *dev_priv = dev->dev_private;
2245
2246 if (dev_priv->display.update_linetime_wm)
2247 dev_priv->display.update_linetime_wm(dev, pipe, mode);
2248}
2249
b445e3b0
ED		 2250void intel_update_sprite_watermarks(struct drm_device *dev, int pipe,
2251 uint32_t sprite_width, int pixel_size)
2252{
2253 struct drm_i915_private *dev_priv = dev->dev_private;
2254
2255 if (dev_priv->display.update_sprite_wm)
2256 dev_priv->display.update_sprite_wm(dev, pipe, sprite_width,
2257 pixel_size);
2258}
2259
2b4e57bd
ED		 2260static struct drm_i915_gem_object *
2261intel_alloc_context_page(struct drm_device *dev)
2262{
2263 struct drm_i915_gem_object *ctx;
2264 int ret;
2265
2266 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2267
2268 ctx = i915_gem_alloc_object(dev, 4096);
2269 if (!ctx) {
2270 DRM_DEBUG("failed to alloc power context, RC6 disabled\n");
2271 return NULL;
2272 }
2273
86a1ee26 2274 ret = i915_gem_object_pin(ctx, 4096, true, false);
2b4e57bd
ED		 2275 if (ret) {
2276 DRM_ERROR("failed to pin power context: %d\n", ret);
2277 goto err_unref;
2278 }
2279
2280 ret = i915_gem_object_set_to_gtt_domain(ctx, 1);
2281 if (ret) {
2282 DRM_ERROR("failed to set-domain on power context: %d\n", ret);
2283 goto err_unpin;
2284 }
2285
2286 return ctx;
2287
2288err_unpin:
2289 i915_gem_object_unpin(ctx);
2290err_unref:
2291 drm_gem_object_unreference(&ctx->base);
2b4e57bd
ED		 2292 return NULL;
2293}
2294
9270388e
DV		 2295/**
2296 * Lock protecting IPS related data structures
9270388e
DV		 2297 */
2298DEFINE_SPINLOCK(mchdev_lock);
2299
2300/* Global for IPS driver to get at the current i915 device. Protected by
2301 * mchdev_lock. */
2302static struct drm_i915_private *i915_mch_dev;
2303
2b4e57bd
ED		 2304bool ironlake_set_drps(struct drm_device *dev, u8 val)
2305{
2306 struct drm_i915_private *dev_priv = dev->dev_private;
2307 u16 rgvswctl;
2308
9270388e
DV		 2309 assert_spin_locked(&mchdev_lock);
2310
2b4e57bd
ED		 2311 rgvswctl = I915_READ16(MEMSWCTL);
2312 if (rgvswctl & MEMCTL_CMD_STS) {
2313 DRM_DEBUG("gpu busy, RCS change rejected\n");
2314 return false; /* still busy with another command */
2315 }
2316
2317 rgvswctl = (MEMCTL_CMD_CHFREQ << MEMCTL_CMD_SHIFT) |
2318 (val << MEMCTL_FREQ_SHIFT) | MEMCTL_SFCAVM;
2319 I915_WRITE16(MEMSWCTL, rgvswctl);
2320 POSTING_READ16(MEMSWCTL);
2321
2322 rgvswctl |= MEMCTL_CMD_STS;
2323 I915_WRITE16(MEMSWCTL, rgvswctl);
2324
2325 return true;
2326}
2327
8090c6b9 2328static void ironlake_enable_drps(struct drm_device *dev)
2b4e57bd
ED		 2329{
2330 struct drm_i915_private *dev_priv = dev->dev_private;
2331 u32 rgvmodectl = I915_READ(MEMMODECTL);
2332 u8 fmax, fmin, fstart, vstart;
2333
9270388e
DV		 2334 spin_lock_irq(&mchdev_lock);
2335
2b4e57bd
ED		 2336 /* Enable temp reporting */
2337 I915_WRITE16(PMMISC, I915_READ(PMMISC) | MCPPCE_EN);
2338 I915_WRITE16(TSC1, I915_READ(TSC1) | TSE);
2339
2340 /* 100ms RC evaluation intervals */
2341 I915_WRITE(RCUPEI, 100000);
2342 I915_WRITE(RCDNEI, 100000);
2343
2344 /* Set max/min thresholds to 90ms and 80ms respectively */
2345 I915_WRITE(RCBMAXAVG, 90000);
2346 I915_WRITE(RCBMINAVG, 80000);
2347
2348 I915_WRITE(MEMIHYST, 1);
2349
2350 /* Set up min, max, and cur for interrupt handling */
2351 fmax = (rgvmodectl & MEMMODE_FMAX_MASK) >> MEMMODE_FMAX_SHIFT;
2352 fmin = (rgvmodectl & MEMMODE_FMIN_MASK);
2353 fstart = (rgvmodectl & MEMMODE_FSTART_MASK) >>
2354 MEMMODE_FSTART_SHIFT;
2355
2356 vstart = (I915_READ(PXVFREQ_BASE + (fstart * 4)) & PXVFREQ_PX_MASK) >>
2357 PXVFREQ_PX_SHIFT;
2358
20e4d407
DV		 2359 dev_priv->ips.fmax = fmax; /* IPS callback will increase this */
2360 dev_priv->ips.fstart = fstart;
2b4e57bd 2361
20e4d407
DV		 2362 dev_priv->ips.max_delay = fstart;
2363 dev_priv->ips.min_delay = fmin;
2364 dev_priv->ips.cur_delay = fstart;
2b4e57bd
ED		 2365
2366 DRM_DEBUG_DRIVER("fmax: %d, fmin: %d, fstart: %d\n",
2367 fmax, fmin, fstart);
2368
2369 I915_WRITE(MEMINTREN, MEMINT_CX_SUPR_EN | MEMINT_EVAL_CHG_EN);
2370
2371 /*
2372 * Interrupts will be enabled in ironlake_irq_postinstall
2373 */
2374
2375 I915_WRITE(VIDSTART, vstart);
2376 POSTING_READ(VIDSTART);
2377
2378 rgvmodectl |= MEMMODE_SWMODE_EN;
2379 I915_WRITE(MEMMODECTL, rgvmodectl);
2380
9270388e 2381 if (wait_for_atomic((I915_READ(MEMSWCTL) & MEMCTL_CMD_STS) == 0, 10))
2b4e57bd 2382 DRM_ERROR("stuck trying to change perf mode\n");
9270388e 2383 mdelay(1);
2b4e57bd
ED		 2384
2385 ironlake_set_drps(dev, fstart);
2386
20e4d407 2387 dev_priv->ips.last_count1 = I915_READ(0x112e4) + I915_READ(0x112e8) +
2b4e57bd 2388 I915_READ(0x112e0);
20e4d407
DV		 2389 dev_priv->ips.last_time1 = jiffies_to_msecs(jiffies);
2390 dev_priv->ips.last_count2 = I915_READ(0x112f4);
2391 getrawmonotonic(&dev_priv->ips.last_time2);
9270388e
DV		 2392
2393 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2394}
2395
8090c6b9 2396static void ironlake_disable_drps(struct drm_device *dev)
2b4e57bd
ED		 2397{
2398 struct drm_i915_private *dev_priv = dev->dev_private;
9270388e
DV		 2399 u16 rgvswctl;
2400
2401 spin_lock_irq(&mchdev_lock);
2402
2403 rgvswctl = I915_READ16(MEMSWCTL);
2b4e57bd
ED		 2404
2405 /* Ack interrupts, disable EFC interrupt */
2406 I915_WRITE(MEMINTREN, I915_READ(MEMINTREN) & ~MEMINT_EVAL_CHG_EN);
2407 I915_WRITE(MEMINTRSTS, MEMINT_EVAL_CHG);
2408 I915_WRITE(DEIER, I915_READ(DEIER) & ~DE_PCU_EVENT);
2409 I915_WRITE(DEIIR, DE_PCU_EVENT);
2410 I915_WRITE(DEIMR, I915_READ(DEIMR) | DE_PCU_EVENT);
2411
2412 /* Go back to the starting frequency */
20e4d407 2413 ironlake_set_drps(dev, dev_priv->ips.fstart);
9270388e 2414 mdelay(1);
2b4e57bd
ED		 2415 rgvswctl |= MEMCTL_CMD_STS;
2416 I915_WRITE(MEMSWCTL, rgvswctl);
9270388e 2417 mdelay(1);
2b4e57bd 2418
9270388e 2419 spin_unlock_irq(&mchdev_lock);
2b4e57bd
ED		 2420}
2421
acbe9475
DV		 2422/* There's a funny hw issue where the hw returns all 0 when reading from
2423 * GEN6_RP_INTERRUPT_LIMITS. Hence we always need to compute the desired value
2424 * ourselves, instead of doing a rmw cycle (which might result in us clearing
2425 * all limits and the gpu stuck at whatever frequency it is at atm).
2426 */
65bccb5c 2427static u32 gen6_rps_limits(struct drm_i915_private *dev_priv, u8 *val)
2b4e57bd 2428{
7b9e0ae6 2429 u32 limits;
2b4e57bd 2430
7b9e0ae6 2431 limits = 0;
c6a828d3
DV		 2432
2433 if (*val >= dev_priv->rps.max_delay)
2434 *val = dev_priv->rps.max_delay;
2435 limits |= dev_priv->rps.max_delay << 24;
20b46e59
DV		 2436
2437 /* Only set the down limit when we've reached the lowest level to avoid
2438 * getting more interrupts, otherwise leave this clear. This prevents a
2439 * race in the hw when coming out of rc6: There's a tiny window where
2440 * the hw runs at the minimal clock before selecting the desired
2441 * frequency, if the down threshold expires in that window we will not
2442 * receive a down interrupt. */
c6a828d3
DV		 2443 if (*val <= dev_priv->rps.min_delay) {
2444 *val = dev_priv->rps.min_delay;
2445 limits |= dev_priv->rps.min_delay << 16;
20b46e59
DV		 2446 }
2447
2448 return limits;
2449}
2450
2451void gen6_set_rps(struct drm_device *dev, u8 val)
2452{
2453 struct drm_i915_private *dev_priv = dev->dev_private;
65bccb5c 2454 u32 limits = gen6_rps_limits(dev_priv, &val);
7b9e0ae6 2455
4fc688ce 2456 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79249636
BW		 2457 WARN_ON(val > dev_priv->rps.max_delay);
2458 WARN_ON(val < dev_priv->rps.min_delay);
004777cb 2459
c6a828d3 2460 if (val == dev_priv->rps.cur_delay)
7b9e0ae6
CW		 2461 return;
2462
92bd1bf0
RV		 2463 if (IS_HASWELL(dev))
2464 I915_WRITE(GEN6_RPNSWREQ,
2465 HSW_FREQUENCY(val));
2466 else
2467 I915_WRITE(GEN6_RPNSWREQ,
2468 GEN6_FREQUENCY(val) |
2469 GEN6_OFFSET(0) |
2470 GEN6_AGGRESSIVE_TURBO);
7b9e0ae6
CW		 2471
2472 /* Make sure we continue to get interrupts
2473 * until we hit the minimum or maximum frequencies.
2474 */
2475 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS, limits);
2476
d5570a72
BW		 2477 POSTING_READ(GEN6_RPNSWREQ);
2478
c6a828d3 2479 dev_priv->rps.cur_delay = val;
be2cde9a
DV		 2480
2481 trace_intel_gpu_freq_change(val * 50);
2b4e57bd
ED		 2482}
2483
8090c6b9 2484static void gen6_disable_rps(struct drm_device *dev)
2b4e57bd
ED		 2485{
2486 struct drm_i915_private *dev_priv = dev->dev_private;
2487
88509484 2488 I915_WRITE(GEN6_RC_CONTROL, 0);
2b4e57bd
ED		 2489 I915_WRITE(GEN6_RPNSWREQ, 1 << 31);
2490 I915_WRITE(GEN6_PMINTRMSK, 0xffffffff);
2491 I915_WRITE(GEN6_PMIER, 0);
2492 /* Complete PM interrupt masking here doesn't race with the rps work
2493 * item again unmasking PM interrupts because that is using a different
2494 * register (PMIMR) to mask PM interrupts. The only risk is in leaving
2495 * stale bits in PMIIR and PMIMR which gen6_enable_rps will clean up. */
2496
c6a828d3
DV		 2497 spin_lock_irq(&dev_priv->rps.lock);
2498 dev_priv->rps.pm_iir = 0;
2499 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2500
2501 I915_WRITE(GEN6_PMIIR, I915_READ(GEN6_PMIIR));
2502}
2503
2504int intel_enable_rc6(const struct drm_device *dev)
2505{
456470eb 2506 /* Respect the kernel parameter if it is set */
2b4e57bd
ED		 2507 if (i915_enable_rc6 >= 0)
2508 return i915_enable_rc6;
2509
6567d748
CW		 2510 /* Disable RC6 on Ironlake */
2511 if (INTEL_INFO(dev)->gen == 5)
2512 return 0;
2b4e57bd 2513
456470eb
DV		 2514 if (IS_HASWELL(dev)) {
2515 DRM_DEBUG_DRIVER("Haswell: only RC6 available\n");
4a637c2c 2516 return INTEL_RC6_ENABLE;
456470eb 2517 }
2b4e57bd 2518
456470eb 2519 /* snb/ivb have more than one rc6 state. */
2b4e57bd
ED		 2520 if (INTEL_INFO(dev)->gen == 6) {
2521 DRM_DEBUG_DRIVER("Sandybridge: deep RC6 disabled\n");
2522 return INTEL_RC6_ENABLE;
2523 }
456470eb 2524
2b4e57bd
ED		 2525 DRM_DEBUG_DRIVER("RC6 and deep RC6 enabled\n");
2526 return (INTEL_RC6_ENABLE | INTEL_RC6p_ENABLE);
2527}
2528
79f5b2c7 2529static void gen6_enable_rps(struct drm_device *dev)
2b4e57bd 2530{
79f5b2c7 2531 struct drm_i915_private *dev_priv = dev->dev_private;
b4519513 2532 struct intel_ring_buffer *ring;
7b9e0ae6
CW		 2533 u32 rp_state_cap;
2534 u32 gt_perf_status;
31643d54 2535 u32 rc6vids, pcu_mbox, rc6_mask = 0;
2b4e57bd 2536 u32 gtfifodbg;
2b4e57bd 2537 int rc6_mode;
42c0526c 2538 int i, ret;
2b4e57bd 2539
4fc688ce 2540 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2541
2b4e57bd
ED		 2542 /* Here begins a magic sequence of register writes to enable
2543 * auto-downclocking.
2544 *
2545 * Perhaps there might be some value in exposing these to
2546 * userspace...
2547 */
2548 I915_WRITE(GEN6_RC_STATE, 0);
2b4e57bd
ED		 2549
2550 /* Clear the DBG now so we don't confuse earlier errors */
2551 if ((gtfifodbg = I915_READ(GTFIFODBG))) {
2552 DRM_ERROR("GT fifo had a previous error %x\n", gtfifodbg);
2553 I915_WRITE(GTFIFODBG, gtfifodbg);
2554 }
2555
2556 gen6_gt_force_wake_get(dev_priv);
2557
7b9e0ae6
CW		 2558 rp_state_cap = I915_READ(GEN6_RP_STATE_CAP);
2559 gt_perf_status = I915_READ(GEN6_GT_PERF_STATUS);
2560
2561 /* In units of 100MHz */
c6a828d3
DV		 2562 dev_priv->rps.max_delay = rp_state_cap & 0xff;
2563 dev_priv->rps.min_delay = (rp_state_cap & 0xff0000) >> 16;
2564 dev_priv->rps.cur_delay = 0;
7b9e0ae6 2565
2b4e57bd
ED		 2566 /* disable the counters and set deterministic thresholds */
2567 I915_WRITE(GEN6_RC_CONTROL, 0);
2568
2569 I915_WRITE(GEN6_RC1_WAKE_RATE_LIMIT, 1000 << 16);
2570 I915_WRITE(GEN6_RC6_WAKE_RATE_LIMIT, 40 << 16 | 30);
2571 I915_WRITE(GEN6_RC6pp_WAKE_RATE_LIMIT, 30);
2572 I915_WRITE(GEN6_RC_EVALUATION_INTERVAL, 125000);
2573 I915_WRITE(GEN6_RC_IDLE_HYSTERSIS, 25);
2574
b4519513
CW		 2575 for_each_ring(ring, dev_priv, i)
2576 I915_WRITE(RING_MAX_IDLE(ring->mmio_base), 10);
2b4e57bd
ED		 2577
2578 I915_WRITE(GEN6_RC_SLEEP, 0);
2579 I915_WRITE(GEN6_RC1e_THRESHOLD, 1000);
2580 I915_WRITE(GEN6_RC6_THRESHOLD, 50000);
0920a487 2581 I915_WRITE(GEN6_RC6p_THRESHOLD, 150000);
2b4e57bd
ED		 2582 I915_WRITE(GEN6_RC6pp_THRESHOLD, 64000); /* unused */
2583
5a7dc92a 2584 /* Check if we are enabling RC6 */
2b4e57bd
ED		 2585 rc6_mode = intel_enable_rc6(dev_priv->dev);
2586 if (rc6_mode & INTEL_RC6_ENABLE)
2587 rc6_mask |= GEN6_RC_CTL_RC6_ENABLE;
2588
5a7dc92a
ED		 2589 /* We don't use those on Haswell */
2590 if (!IS_HASWELL(dev)) {
2591 if (rc6_mode & INTEL_RC6p_ENABLE)
2592 rc6_mask |= GEN6_RC_CTL_RC6p_ENABLE;
2b4e57bd 2593
5a7dc92a
ED		 2594 if (rc6_mode & INTEL_RC6pp_ENABLE)
2595 rc6_mask |= GEN6_RC_CTL_RC6pp_ENABLE;
2596 }
2b4e57bd
ED		 2597
2598 DRM_INFO("Enabling RC6 states: RC6 %s, RC6p %s, RC6pp %s\n",
5a7dc92a
ED		 2599 (rc6_mask & GEN6_RC_CTL_RC6_ENABLE) ? "on" : "off",
2600 (rc6_mask & GEN6_RC_CTL_RC6p_ENABLE) ? "on" : "off",
2601 (rc6_mask & GEN6_RC_CTL_RC6pp_ENABLE) ? "on" : "off");
2b4e57bd
ED		 2602
2603 I915_WRITE(GEN6_RC_CONTROL,
2604 rc6_mask |
2605 GEN6_RC_CTL_EI_MODE(1) |
2606 GEN6_RC_CTL_HW_ENABLE);
2607
92bd1bf0
RV		 2608 if (IS_HASWELL(dev)) {
2609 I915_WRITE(GEN6_RPNSWREQ,
2610 HSW_FREQUENCY(10));
2611 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2612 HSW_FREQUENCY(12));
2613 } else {
2614 I915_WRITE(GEN6_RPNSWREQ,
2615 GEN6_FREQUENCY(10) |
2616 GEN6_OFFSET(0) |
2617 GEN6_AGGRESSIVE_TURBO);
2618 I915_WRITE(GEN6_RC_VIDEO_FREQ,
2619 GEN6_FREQUENCY(12));
2620 }
2b4e57bd
ED		 2621
2622 I915_WRITE(GEN6_RP_DOWN_TIMEOUT, 1000000);
2623 I915_WRITE(GEN6_RP_INTERRUPT_LIMITS,
c6a828d3
DV		 2624 dev_priv->rps.max_delay << 24 |
2625 dev_priv->rps.min_delay << 16);
5a7dc92a 2626
1ee9ae32
DV		 2627 I915_WRITE(GEN6_RP_UP_THRESHOLD, 59400);
2628 I915_WRITE(GEN6_RP_DOWN_THRESHOLD, 245000);
2629 I915_WRITE(GEN6_RP_UP_EI, 66000);
2630 I915_WRITE(GEN6_RP_DOWN_EI, 350000);
5a7dc92a 2631
2b4e57bd
ED		 2632 I915_WRITE(GEN6_RP_IDLE_HYSTERSIS, 10);
2633 I915_WRITE(GEN6_RP_CONTROL,
2634 GEN6_RP_MEDIA_TURBO |
89ba829e 2635 GEN6_RP_MEDIA_HW_NORMAL_MODE |
2b4e57bd
ED		 2636 GEN6_RP_MEDIA_IS_GFX |
2637 GEN6_RP_ENABLE |
2638 GEN6_RP_UP_BUSY_AVG |
5a7dc92a 2639 (IS_HASWELL(dev) ? GEN7_RP_DOWN_IDLE_AVG : GEN6_RP_DOWN_IDLE_CONT));
2b4e57bd 2640
42c0526c 2641 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_MIN_FREQ_TABLE, 0);
fec46b5e 2642 if (!ret && (IS_GEN6(dev) || IS_IVYBRIDGE(dev))) {
42c0526c
BW		 2643 pcu_mbox = 0;
2644 ret = sandybridge_pcode_read(dev_priv, GEN6_READ_OC_PARAMS, &pcu_mbox);
a2b3fc01
BW		 2645 if (!ret && (pcu_mbox & (1<<31))) { /* OC supported */
2646 DRM_DEBUG_DRIVER("overclocking supported, adjusting frequency max from %dMHz to %dMHz\n",
2647 (dev_priv->rps.max_delay & 0xff) * 50,
2648 (pcu_mbox & 0xff) * 50);
42c0526c 2649 dev_priv->rps.max_delay = pcu_mbox & 0xff;
42c0526c
BW		 2650 }
2651 } else {
2652 DRM_DEBUG_DRIVER("Failed to set the min frequency\n");
2b4e57bd
ED		 2653 }
2654
7b9e0ae6 2655 gen6_set_rps(dev_priv->dev, (gt_perf_status & 0xff00) >> 8);
2b4e57bd
ED		 2656
2657 /* requires MSI enabled */
ff928261 2658 I915_WRITE(GEN6_PMIER, GEN6_PM_DEFERRED_EVENTS);
c6a828d3
DV		 2659 spin_lock_irq(&dev_priv->rps.lock);
2660 WARN_ON(dev_priv->rps.pm_iir != 0);
2b4e57bd 2661 I915_WRITE(GEN6_PMIMR, 0);
c6a828d3 2662 spin_unlock_irq(&dev_priv->rps.lock);
2b4e57bd
ED		 2663 /* enable all PM interrupts */
2664 I915_WRITE(GEN6_PMINTRMSK, 0);
2665
31643d54
BW		 2666 rc6vids = 0;
2667 ret = sandybridge_pcode_read(dev_priv, GEN6_PCODE_READ_RC6VIDS, &rc6vids);
2668 if (IS_GEN6(dev) && ret) {
2669 DRM_DEBUG_DRIVER("Couldn't check for BIOS workaround\n");
2670 } else if (IS_GEN6(dev) && (GEN6_DECODE_RC6_VID(rc6vids & 0xff) < 450)) {
2671 DRM_DEBUG_DRIVER("You should update your BIOS. Correcting minimum rc6 voltage (%dmV->%dmV)\n",
2672 GEN6_DECODE_RC6_VID(rc6vids & 0xff), 450);
2673 rc6vids &= 0xffff00;
2674 rc6vids |= GEN6_ENCODE_RC6_VID(450);
2675 ret = sandybridge_pcode_write(dev_priv, GEN6_PCODE_WRITE_RC6VIDS, rc6vids);
2676 if (ret)
2677 DRM_ERROR("Couldn't fix incorrect rc6 voltage\n");
2678 }
2679
2b4e57bd 2680 gen6_gt_force_wake_put(dev_priv);
2b4e57bd
ED		 2681}
2682
79f5b2c7 2683static void gen6_update_ring_freq(struct drm_device *dev)
2b4e57bd 2684{
79f5b2c7 2685 struct drm_i915_private *dev_priv = dev->dev_private;
2b4e57bd 2686 int min_freq = 15;
e3fef09d
JD		 2687 int gpu_freq;
2688 unsigned int ia_freq, max_ia_freq;
2b4e57bd
ED		 2689 int scaling_factor = 180;
2690
4fc688ce 2691 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
79f5b2c7 2692
2b4e57bd
ED		 2693 max_ia_freq = cpufreq_quick_get_max(0);
2694 /*
2695 * Default to measured freq if none found, PCU will ensure we don't go
2696 * over
2697 */
2698 if (!max_ia_freq)
2699 max_ia_freq = tsc_khz;
2700
2701 /* Convert from kHz to MHz */
2702 max_ia_freq /= 1000;
2703
2b4e57bd
ED		 2704 /*
2705 * For each potential GPU frequency, load a ring frequency we'd like
2706 * to use for memory access. We do this by specifying the IA frequency
2707 * the PCU should use as a reference to determine the ring frequency.
2708 */
c6a828d3 2709 for (gpu_freq = dev_priv->rps.max_delay; gpu_freq >= dev_priv->rps.min_delay;
2b4e57bd 2710 gpu_freq--) {
c6a828d3 2711 int diff = dev_priv->rps.max_delay - gpu_freq;
2b4e57bd
ED		 2712
2713 /*
2714 * For GPU frequencies less than 750MHz, just use the lowest
2715 * ring freq.
2716 */
2717 if (gpu_freq < min_freq)
2718 ia_freq = 800;
2719 else
2720 ia_freq = max_ia_freq - ((diff * scaling_factor) / 2);
2721 ia_freq = DIV_ROUND_CLOSEST(ia_freq, 100);
42c0526c 2722 ia_freq <<= GEN6_PCODE_FREQ_IA_RATIO_SHIFT;
2b4e57bd 2723
42c0526c
BW		 2724 sandybridge_pcode_write(dev_priv,
2725 GEN6_PCODE_WRITE_MIN_FREQ_TABLE,
2726 ia_freq | gpu_freq);
2b4e57bd 2727 }
2b4e57bd
ED		 2728}
2729
930ebb46 2730void ironlake_teardown_rc6(struct drm_device *dev)
2b4e57bd
ED		 2731{
2732 struct drm_i915_private *dev_priv = dev->dev_private;
2733
3e373948
DV		 2734 if (dev_priv->ips.renderctx) {
2735 i915_gem_object_unpin(dev_priv->ips.renderctx);
2736 drm_gem_object_unreference(&dev_priv->ips.renderctx->base);
2737 dev_priv->ips.renderctx = NULL;
2b4e57bd
ED		 2738 }
2739
3e373948
DV		 2740 if (dev_priv->ips.pwrctx) {
2741 i915_gem_object_unpin(dev_priv->ips.pwrctx);
2742 drm_gem_object_unreference(&dev_priv->ips.pwrctx->base);
2743 dev_priv->ips.pwrctx = NULL;
2b4e57bd
ED		 2744 }
2745}
2746
930ebb46 2747static void ironlake_disable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2748{
2749 struct drm_i915_private *dev_priv = dev->dev_private;
2750
2751 if (I915_READ(PWRCTXA)) {
2752 /* Wake the GPU, prevent RC6, then restore RSTDBYCTL */
2753 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) | RCX_SW_EXIT);
2754 wait_for(((I915_READ(RSTDBYCTL) & RSX_STATUS_MASK) == RSX_STATUS_ON),
2755 50);
2756
2757 I915_WRITE(PWRCTXA, 0);
2758 POSTING_READ(PWRCTXA);
2759
2760 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2761 POSTING_READ(RSTDBYCTL);
2762 }
2b4e57bd
ED		 2763}
2764
2765static int ironlake_setup_rc6(struct drm_device *dev)
2766{
2767 struct drm_i915_private *dev_priv = dev->dev_private;
2768
3e373948
DV		 2769 if (dev_priv->ips.renderctx == NULL)
2770 dev_priv->ips.renderctx = intel_alloc_context_page(dev);
2771 if (!dev_priv->ips.renderctx)
2b4e57bd
ED		 2772 return -ENOMEM;
2773
3e373948
DV		 2774 if (dev_priv->ips.pwrctx == NULL)
2775 dev_priv->ips.pwrctx = intel_alloc_context_page(dev);
2776 if (!dev_priv->ips.pwrctx) {
2b4e57bd
ED		 2777 ironlake_teardown_rc6(dev);
2778 return -ENOMEM;
2779 }
2780
2781 return 0;
2782}
2783
930ebb46 2784static void ironlake_enable_rc6(struct drm_device *dev)
2b4e57bd
ED		 2785{
2786 struct drm_i915_private *dev_priv = dev->dev_private;
6d90c952 2787 struct intel_ring_buffer *ring = &dev_priv->ring[RCS];
3e960501 2788 bool was_interruptible;
2b4e57bd
ED		 2789 int ret;
2790
2791 /* rc6 disabled by default due to repeated reports of hanging during
2792 * boot and resume.
2793 */
2794 if (!intel_enable_rc6(dev))
2795 return;
2796
79f5b2c7
DV		 2797 WARN_ON(!mutex_is_locked(&dev->struct_mutex));
2798
2b4e57bd 2799 ret = ironlake_setup_rc6(dev);
79f5b2c7 2800 if (ret)
2b4e57bd 2801 return;
2b4e57bd 2802
3e960501
CW		 2803 was_interruptible = dev_priv->mm.interruptible;
2804 dev_priv->mm.interruptible = false;
2805
2b4e57bd
ED		 2806 /*
2807 * GPU can automatically power down the render unit if given a page
2808 * to save state.
2809 */
6d90c952 2810 ret = intel_ring_begin(ring, 6);
2b4e57bd
ED		 2811 if (ret) {
2812 ironlake_teardown_rc6(dev);
3e960501 2813 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd
ED		 2814 return;
2815 }
2816
6d90c952
DV		 2817 intel_ring_emit(ring, MI_SUSPEND_FLUSH | MI_SUSPEND_FLUSH_EN);
2818 intel_ring_emit(ring, MI_SET_CONTEXT);
3e373948 2819 intel_ring_emit(ring, dev_priv->ips.renderctx->gtt_offset |
6d90c952
DV		 2820 MI_MM_SPACE_GTT |
2821 MI_SAVE_EXT_STATE_EN |
2822 MI_RESTORE_EXT_STATE_EN |
2823 MI_RESTORE_INHIBIT);
2824 intel_ring_emit(ring, MI_SUSPEND_FLUSH);
2825 intel_ring_emit(ring, MI_NOOP);
2826 intel_ring_emit(ring, MI_FLUSH);
2827 intel_ring_advance(ring);
2b4e57bd
ED		 2828
2829 /*
2830 * Wait for the command parser to advance past MI_SET_CONTEXT. The HW
2831 * does an implicit flush, combined with MI_FLUSH above, it should be
2832 * safe to assume that renderctx is valid
2833 */
3e960501
CW		 2834 ret = intel_ring_idle(ring);
2835 dev_priv->mm.interruptible = was_interruptible;
2b4e57bd 2836 if (ret) {
def27a58 2837 DRM_ERROR("failed to enable ironlake power savings\n");
2b4e57bd 2838 ironlake_teardown_rc6(dev);
2b4e57bd
ED		 2839 return;
2840 }
2841
3e373948 2842 I915_WRITE(PWRCTXA, dev_priv->ips.pwrctx->gtt_offset | PWRCTX_EN);
2b4e57bd 2843 I915_WRITE(RSTDBYCTL, I915_READ(RSTDBYCTL) & ~RCX_SW_EXIT);
2b4e57bd
ED		 2844}
2845
dde18883
ED		 2846static unsigned long intel_pxfreq(u32 vidfreq)
2847{
2848 unsigned long freq;
2849 int div = (vidfreq & 0x3f0000) >> 16;
2850 int post = (vidfreq & 0x3000) >> 12;
2851 int pre = (vidfreq & 0x7);
2852
2853 if (!pre)
2854 return 0;
2855
2856 freq = ((div * 133333) / ((1<<post) * pre));
2857
2858 return freq;
2859}
2860
eb48eb00
DV		 2861static const struct cparams {
2862 u16 i;
2863 u16 t;
2864 u16 m;
2865 u16 c;
2866} cparams[] = {
2867 { 1, 1333, 301, 28664 },
2868 { 1, 1066, 294, 24460 },
2869 { 1, 800, 294, 25192 },
2870 { 0, 1333, 276, 27605 },
2871 { 0, 1066, 276, 27605 },
2872 { 0, 800, 231, 23784 },
2873};
2874
f531dcb2 2875static unsigned long __i915_chipset_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 2876{
2877 u64 total_count, diff, ret;
2878 u32 count1, count2, count3, m = 0, c = 0;
2879 unsigned long now = jiffies_to_msecs(jiffies), diff1;
2880 int i;
2881
02d71956
DV		 2882 assert_spin_locked(&mchdev_lock);
2883
20e4d407 2884 diff1 = now - dev_priv->ips.last_time1;
eb48eb00
DV		 2885
2886 /* Prevent division-by-zero if we are asking too fast.
2887 * Also, we don't get interesting results if we are polling
2888 * faster than once in 10ms, so just return the saved value
2889 * in such cases.
2890 */
2891 if (diff1 <= 10)
20e4d407 2892 return dev_priv->ips.chipset_power;
eb48eb00
DV		 2893
2894 count1 = I915_READ(DMIEC);
2895 count2 = I915_READ(DDREC);
2896 count3 = I915_READ(CSIEC);
2897
2898 total_count = count1 + count2 + count3;
2899
2900 /* FIXME: handle per-counter overflow */
20e4d407
DV		 2901 if (total_count < dev_priv->ips.last_count1) {
2902 diff = ~0UL - dev_priv->ips.last_count1;
eb48eb00
DV		 2903 diff += total_count;
2904 } else {
20e4d407 2905 diff = total_count - dev_priv->ips.last_count1;
eb48eb00
DV		 2906 }
2907
2908 for (i = 0; i < ARRAY_SIZE(cparams); i++) {
20e4d407
DV		 2909 if (cparams[i].i == dev_priv->ips.c_m &&
2910 cparams[i].t == dev_priv->ips.r_t) {
eb48eb00
DV		 2911 m = cparams[i].m;
2912 c = cparams[i].c;
2913 break;
2914 }
2915 }
2916
2917 diff = div_u64(diff, diff1);
2918 ret = ((m * diff) + c);
2919 ret = div_u64(ret, 10);
2920
20e4d407
DV		 2921 dev_priv->ips.last_count1 = total_count;
2922 dev_priv->ips.last_time1 = now;
eb48eb00 2923
20e4d407 2924 dev_priv->ips.chipset_power = ret;
eb48eb00
DV		 2925
2926 return ret;
2927}
2928
f531dcb2
CW		 2929unsigned long i915_chipset_val(struct drm_i915_private *dev_priv)
2930{
2931 unsigned long val;
2932
2933 if (dev_priv->info->gen != 5)
2934 return 0;
2935
2936 spin_lock_irq(&mchdev_lock);
2937
2938 val = __i915_chipset_val(dev_priv);
2939
2940 spin_unlock_irq(&mchdev_lock);
2941
2942 return val;
2943}
2944
eb48eb00
DV		 2945unsigned long i915_mch_val(struct drm_i915_private *dev_priv)
2946{
2947 unsigned long m, x, b;
2948 u32 tsfs;
2949
2950 tsfs = I915_READ(TSFS);
2951
2952 m = ((tsfs & TSFS_SLOPE_MASK) >> TSFS_SLOPE_SHIFT);
2953 x = I915_READ8(TR1);
2954
2955 b = tsfs & TSFS_INTR_MASK;
2956
2957 return ((m * x) / 127) - b;
2958}
2959
2960static u16 pvid_to_extvid(struct drm_i915_private *dev_priv, u8 pxvid)
2961{
2962 static const struct v_table {
2963 u16 vd; /* in .1 mil */
2964 u16 vm; /* in .1 mil */
2965 } v_table[] = {
2966 { 0, 0, },
2967 { 375, 0, },
2968 { 500, 0, },
2969 { 625, 0, },
2970 { 750, 0, },
2971 { 875, 0, },
2972 { 1000, 0, },
2973 { 1125, 0, },
2974 { 4125, 3000, },
2975 { 4125, 3000, },
2976 { 4125, 3000, },
2977 { 4125, 3000, },
2978 { 4125, 3000, },
2979 { 4125, 3000, },
2980 { 4125, 3000, },
2981 { 4125, 3000, },
2982 { 4125, 3000, },
2983 { 4125, 3000, },
2984 { 4125, 3000, },
2985 { 4125, 3000, },
2986 { 4125, 3000, },
2987 { 4125, 3000, },
2988 { 4125, 3000, },
2989 { 4125, 3000, },
2990 { 4125, 3000, },
2991 { 4125, 3000, },
2992 { 4125, 3000, },
2993 { 4125, 3000, },
2994 { 4125, 3000, },
2995 { 4125, 3000, },
2996 { 4125, 3000, },
2997 { 4125, 3000, },
2998 { 4250, 3125, },
2999 { 4375, 3250, },
3000 { 4500, 3375, },
3001 { 4625, 3500, },
3002 { 4750, 3625, },
3003 { 4875, 3750, },
3004 { 5000, 3875, },
3005 { 5125, 4000, },
3006 { 5250, 4125, },
3007 { 5375, 4250, },
3008 { 5500, 4375, },
3009 { 5625, 4500, },
3010 { 5750, 4625, },
3011 { 5875, 4750, },
3012 { 6000, 4875, },
3013 { 6125, 5000, },
3014 { 6250, 5125, },
3015 { 6375, 5250, },
3016 { 6500, 5375, },
3017 { 6625, 5500, },
3018 { 6750, 5625, },
3019 { 6875, 5750, },
3020 { 7000, 5875, },
3021 { 7125, 6000, },
3022 { 7250, 6125, },
3023 { 7375, 6250, },
3024 { 7500, 6375, },
3025 { 7625, 6500, },
3026 { 7750, 6625, },
3027 { 7875, 6750, },
3028 { 8000, 6875, },
3029 { 8125, 7000, },
3030 { 8250, 7125, },
3031 { 8375, 7250, },
3032 { 8500, 7375, },
3033 { 8625, 7500, },
3034 { 8750, 7625, },
3035 { 8875, 7750, },
3036 { 9000, 7875, },
3037 { 9125, 8000, },
3038 { 9250, 8125, },
3039 { 9375, 8250, },
3040 { 9500, 8375, },
3041 { 9625, 8500, },
3042 { 9750, 8625, },
3043 { 9875, 8750, },
3044 { 10000, 8875, },
3045 { 10125, 9000, },
3046 { 10250, 9125, },
3047 { 10375, 9250, },
3048 { 10500, 9375, },
3049 { 10625, 9500, },
3050 { 10750, 9625, },
3051 { 10875, 9750, },
3052 { 11000, 9875, },
3053 { 11125, 10000, },
3054 { 11250, 10125, },
3055 { 11375, 10250, },
3056 { 11500, 10375, },
3057 { 11625, 10500, },
3058 { 11750, 10625, },
3059 { 11875, 10750, },
3060 { 12000, 10875, },
3061 { 12125, 11000, },
3062 { 12250, 11125, },
3063 { 12375, 11250, },
3064 { 12500, 11375, },
3065 { 12625, 11500, },
3066 { 12750, 11625, },
3067 { 12875, 11750, },
3068 { 13000, 11875, },
3069 { 13125, 12000, },
3070 { 13250, 12125, },
3071 { 13375, 12250, },
3072 { 13500, 12375, },
3073 { 13625, 12500, },
3074 { 13750, 12625, },
3075 { 13875, 12750, },
3076 { 14000, 12875, },
3077 { 14125, 13000, },
3078 { 14250, 13125, },
3079 { 14375, 13250, },
3080 { 14500, 13375, },
3081 { 14625, 13500, },
3082 { 14750, 13625, },
3083 { 14875, 13750, },
3084 { 15000, 13875, },
3085 { 15125, 14000, },
3086 { 15250, 14125, },
3087 { 15375, 14250, },
3088 { 15500, 14375, },
3089 { 15625, 14500, },
3090 { 15750, 14625, },
3091 { 15875, 14750, },
3092 { 16000, 14875, },
3093 { 16125, 15000, },
3094 };
3095 if (dev_priv->info->is_mobile)
3096 return v_table[pxvid].vm;
3097 else
3098 return v_table[pxvid].vd;
3099}
3100
02d71956 3101static void __i915_update_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3102{
3103 struct timespec now, diff1;
3104 u64 diff;
3105 unsigned long diffms;
3106 u32 count;
3107
02d71956 3108 assert_spin_locked(&mchdev_lock);
eb48eb00
DV		 3109
3110 getrawmonotonic(&now);
20e4d407 3111 diff1 = timespec_sub(now, dev_priv->ips.last_time2);
eb48eb00
DV		 3112
3113 /* Don't divide by 0 */
3114 diffms = diff1.tv_sec * 1000 + diff1.tv_nsec / 1000000;
3115 if (!diffms)
3116 return;
3117
3118 count = I915_READ(GFXEC);
3119
20e4d407
DV		 3120 if (count < dev_priv->ips.last_count2) {
3121 diff = ~0UL - dev_priv->ips.last_count2;
eb48eb00
DV		 3122 diff += count;
3123 } else {
20e4d407 3124 diff = count - dev_priv->ips.last_count2;
eb48eb00
DV		 3125 }
3126
20e4d407
DV		 3127 dev_priv->ips.last_count2 = count;
3128 dev_priv->ips.last_time2 = now;
eb48eb00
DV		 3129
3130 /* More magic constants... */
3131 diff = diff * 1181;
3132 diff = div_u64(diff, diffms * 10);
20e4d407 3133 dev_priv->ips.gfx_power = diff;
eb48eb00
DV		 3134}
3135
02d71956
DV		 3136void i915_update_gfx_val(struct drm_i915_private *dev_priv)
3137{
3138 if (dev_priv->info->gen != 5)
3139 return;
3140
9270388e 3141 spin_lock_irq(&mchdev_lock);
02d71956
DV		 3142
3143 __i915_update_gfx_val(dev_priv);
3144
9270388e 3145 spin_unlock_irq(&mchdev_lock);
02d71956
DV		 3146}
3147
f531dcb2 3148static unsigned long __i915_gfx_val(struct drm_i915_private *dev_priv)
eb48eb00
DV		 3149{
3150 unsigned long t, corr, state1, corr2, state2;
3151 u32 pxvid, ext_v;
3152
02d71956
DV		 3153 assert_spin_locked(&mchdev_lock);
3154
c6a828d3 3155 pxvid = I915_READ(PXVFREQ_BASE + (dev_priv->rps.cur_delay * 4));
eb48eb00
DV		 3156 pxvid = (pxvid >> 24) & 0x7f;
3157 ext_v = pvid_to_extvid(dev_priv, pxvid);
3158
3159 state1 = ext_v;
3160
3161 t = i915_mch_val(dev_priv);
3162
3163 /* Revel in the empirically derived constants */
3164
3165 /* Correction factor in 1/100000 units */
3166 if (t > 80)
3167 corr = ((t * 2349) + 135940);
3168 else if (t >= 50)
3169 corr = ((t * 964) + 29317);
3170 else /* < 50 */
3171 corr = ((t * 301) + 1004);
3172
3173 corr = corr * ((150142 * state1) / 10000 - 78642);
3174 corr /= 100000;
20e4d407 3175 corr2 = (corr * dev_priv->ips.corr);
eb48eb00
DV		 3176
3177 state2 = (corr2 * state1) / 10000;
3178 state2 /= 100; /* convert to mW */
3179
02d71956 3180 __i915_update_gfx_val(dev_priv);
eb48eb00 3181
20e4d407 3182 return dev_priv->ips.gfx_power + state2;
eb48eb00
DV		 3183}
3184
f531dcb2
CW		 3185unsigned long i915_gfx_val(struct drm_i915_private *dev_priv)
3186{
3187 unsigned long val;
3188
3189 if (dev_priv->info->gen != 5)
3190 return 0;
3191
3192 spin_lock_irq(&mchdev_lock);
3193
3194 val = __i915_gfx_val(dev_priv);
3195
3196 spin_unlock_irq(&mchdev_lock);
3197
3198 return val;
3199}
3200
eb48eb00
DV		 3201/**
3202 * i915_read_mch_val - return value for IPS use
3203 *
3204 * Calculate and return a value for the IPS driver to use when deciding whether
3205 * we have thermal and power headroom to increase CPU or GPU power budget.
3206 */
3207unsigned long i915_read_mch_val(void)
3208{
3209 struct drm_i915_private *dev_priv;
3210 unsigned long chipset_val, graphics_val, ret = 0;
3211
9270388e 3212 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3213 if (!i915_mch_dev)
3214 goto out_unlock;
3215 dev_priv = i915_mch_dev;
3216
f531dcb2
CW		 3217 chipset_val = __i915_chipset_val(dev_priv);
3218 graphics_val = __i915_gfx_val(dev_priv);
eb48eb00
DV		 3219
3220 ret = chipset_val + graphics_val;
3221
3222out_unlock:
9270388e 3223 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3224
3225 return ret;
3226}
3227EXPORT_SYMBOL_GPL(i915_read_mch_val);
3228
3229/**
3230 * i915_gpu_raise - raise GPU frequency limit
3231 *
3232 * Raise the limit; IPS indicates we have thermal headroom.
3233 */
3234bool i915_gpu_raise(void)
3235{
3236 struct drm_i915_private *dev_priv;
3237 bool ret = true;
3238
9270388e 3239 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3240 if (!i915_mch_dev) {
3241 ret = false;
3242 goto out_unlock;
3243 }
3244 dev_priv = i915_mch_dev;
3245
20e4d407
DV		 3246 if (dev_priv->ips.max_delay > dev_priv->ips.fmax)
3247 dev_priv->ips.max_delay--;
eb48eb00
DV		 3248
3249out_unlock:
9270388e 3250 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3251
3252 return ret;
3253}
3254EXPORT_SYMBOL_GPL(i915_gpu_raise);
3255
3256/**
3257 * i915_gpu_lower - lower GPU frequency limit
3258 *
3259 * IPS indicates we're close to a thermal limit, so throttle back the GPU
3260 * frequency maximum.
3261 */
3262bool i915_gpu_lower(void)
3263{
3264 struct drm_i915_private *dev_priv;
3265 bool ret = true;
3266
9270388e 3267 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3268 if (!i915_mch_dev) {
3269 ret = false;
3270 goto out_unlock;
3271 }
3272 dev_priv = i915_mch_dev;
3273
20e4d407
DV		 3274 if (dev_priv->ips.max_delay < dev_priv->ips.min_delay)
3275 dev_priv->ips.max_delay++;
eb48eb00
DV		 3276
3277out_unlock:
9270388e 3278 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3279
3280 return ret;
3281}
3282EXPORT_SYMBOL_GPL(i915_gpu_lower);
3283
3284/**
3285 * i915_gpu_busy - indicate GPU business to IPS
3286 *
3287 * Tell the IPS driver whether or not the GPU is busy.
3288 */
3289bool i915_gpu_busy(void)
3290{
3291 struct drm_i915_private *dev_priv;
f047e395 3292 struct intel_ring_buffer *ring;
eb48eb00 3293 bool ret = false;
f047e395 3294 int i;
eb48eb00 3295
9270388e 3296 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3297 if (!i915_mch_dev)
3298 goto out_unlock;
3299 dev_priv = i915_mch_dev;
3300
f047e395
CW		 3301 for_each_ring(ring, dev_priv, i)
3302 ret |= !list_empty(&ring->request_list);
eb48eb00
DV		 3303
3304out_unlock:
9270388e 3305 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3306
3307 return ret;
3308}
3309EXPORT_SYMBOL_GPL(i915_gpu_busy);
3310
3311/**
3312 * i915_gpu_turbo_disable - disable graphics turbo
3313 *
3314 * Disable graphics turbo by resetting the max frequency and setting the
3315 * current frequency to the default.
3316 */
3317bool i915_gpu_turbo_disable(void)
3318{
3319 struct drm_i915_private *dev_priv;
3320 bool ret = true;
3321
9270388e 3322 spin_lock_irq(&mchdev_lock);
eb48eb00
DV		 3323 if (!i915_mch_dev) {
3324 ret = false;
3325 goto out_unlock;
3326 }
3327 dev_priv = i915_mch_dev;
3328
20e4d407 3329 dev_priv->ips.max_delay = dev_priv->ips.fstart;
eb48eb00 3330
20e4d407 3331 if (!ironlake_set_drps(dev_priv->dev, dev_priv->ips.fstart))
eb48eb00
DV		 3332 ret = false;
3333
3334out_unlock:
9270388e 3335 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3336
3337 return ret;
3338}
3339EXPORT_SYMBOL_GPL(i915_gpu_turbo_disable);
3340
3341/**
3342 * Tells the intel_ips driver that the i915 driver is now loaded, if
3343 * IPS got loaded first.
3344 *
3345 * This awkward dance is so that neither module has to depend on the
3346 * other in order for IPS to do the appropriate communication of
3347 * GPU turbo limits to i915.
3348 */
3349static void
3350ips_ping_for_i915_load(void)
3351{
3352 void (*link)(void);
3353
3354 link = symbol_get(ips_link_to_i915_driver);
3355 if (link) {
3356 link();
3357 symbol_put(ips_link_to_i915_driver);
3358 }
3359}
3360
3361void intel_gpu_ips_init(struct drm_i915_private *dev_priv)
3362{
02d71956
DV		 3363 /* We only register the i915 ips part with intel-ips once everything is
3364 * set up, to avoid intel-ips sneaking in and reading bogus values. */
9270388e 3365 spin_lock_irq(&mchdev_lock);
eb48eb00 3366 i915_mch_dev = dev_priv;
9270388e 3367 spin_unlock_irq(&mchdev_lock);
eb48eb00
DV		 3368
3369 ips_ping_for_i915_load();
3370}
3371
3372void intel_gpu_ips_teardown(void)
3373{
9270388e 3374 spin_lock_irq(&mchdev_lock);
eb48eb00 3375 i915_mch_dev = NULL;
9270388e 3376 spin_unlock_irq(&mchdev_lock);
eb48eb00 3377}
8090c6b9 3378static void intel_init_emon(struct drm_device *dev)
dde18883
ED		 3379{
3380 struct drm_i915_private *dev_priv = dev->dev_private;
3381 u32 lcfuse;
3382 u8 pxw[16];
3383 int i;
3384
3385 /* Disable to program */
3386 I915_WRITE(ECR, 0);
3387 POSTING_READ(ECR);
3388
3389 /* Program energy weights for various events */
3390 I915_WRITE(SDEW, 0x15040d00);
3391 I915_WRITE(CSIEW0, 0x007f0000);
3392 I915_WRITE(CSIEW1, 0x1e220004);
3393 I915_WRITE(CSIEW2, 0x04000004);
3394
3395 for (i = 0; i < 5; i++)
3396 I915_WRITE(PEW + (i * 4), 0);
3397 for (i = 0; i < 3; i++)
3398 I915_WRITE(DEW + (i * 4), 0);
3399
3400 /* Program P-state weights to account for frequency power adjustment */
3401 for (i = 0; i < 16; i++) {
3402 u32 pxvidfreq = I915_READ(PXVFREQ_BASE + (i * 4));
3403 unsigned long freq = intel_pxfreq(pxvidfreq);
3404 unsigned long vid = (pxvidfreq & PXVFREQ_PX_MASK) >>
3405 PXVFREQ_PX_SHIFT;
3406 unsigned long val;
3407
3408 val = vid * vid;
3409 val *= (freq / 1000);
3410 val *= 255;
3411 val /= (127*127*900);
3412 if (val > 0xff)
3413 DRM_ERROR("bad pxval: %ld\n", val);
3414 pxw[i] = val;
3415 }
3416 /* Render standby states get 0 weight */
3417 pxw[14] = 0;
3418 pxw[15] = 0;
3419
3420 for (i = 0; i < 4; i++) {
3421 u32 val = (pxw[i*4] << 24) | (pxw[(i*4)+1] << 16) |
3422 (pxw[(i*4)+2] << 8) | (pxw[(i*4)+3]);
3423 I915_WRITE(PXW + (i * 4), val);
3424 }
3425
3426 /* Adjust magic regs to magic values (more experimental results) */
3427 I915_WRITE(OGW0, 0);
3428 I915_WRITE(OGW1, 0);
3429 I915_WRITE(EG0, 0x00007f00);
3430 I915_WRITE(EG1, 0x0000000e);
3431 I915_WRITE(EG2, 0x000e0000);
3432 I915_WRITE(EG3, 0x68000300);
3433 I915_WRITE(EG4, 0x42000000);
3434 I915_WRITE(EG5, 0x00140031);
3435 I915_WRITE(EG6, 0);
3436 I915_WRITE(EG7, 0);
3437
3438 for (i = 0; i < 8; i++)
3439 I915_WRITE(PXWL + (i * 4), 0);
3440
3441 /* Enable PMON + select events */
3442 I915_WRITE(ECR, 0x80000019);
3443
3444 lcfuse = I915_READ(LCFUSE02);
3445
20e4d407 3446 dev_priv->ips.corr = (lcfuse & LCFUSE_HIV_MASK);
dde18883
ED		 3447}
3448
8090c6b9
DV		 3449void intel_disable_gt_powersave(struct drm_device *dev)
3450{
1a01ab3b
JB		 3451 struct drm_i915_private *dev_priv = dev->dev_private;
3452
930ebb46 3453 if (IS_IRONLAKE_M(dev)) {
8090c6b9 3454 ironlake_disable_drps(dev);
930ebb46
DV		 3455 ironlake_disable_rc6(dev);
3456 } else if (INTEL_INFO(dev)->gen >= 6 && !IS_VALLEYVIEW(dev)) {
1a01ab3b 3457 cancel_delayed_work_sync(&dev_priv->rps.delayed_resume_work);
4fc688ce 3458 mutex_lock(&dev_priv->rps.hw_lock);
8090c6b9 3459 gen6_disable_rps(dev);
4fc688ce 3460 mutex_unlock(&dev_priv->rps.hw_lock);
930ebb46 3461 }
8090c6b9
DV		 3462}
3463
1a01ab3b
JB		 3464static void intel_gen6_powersave_work(struct work_struct *work)
3465{
3466 struct drm_i915_private *dev_priv =
3467 container_of(work, struct drm_i915_private,
3468 rps.delayed_resume_work.work);
3469 struct drm_device *dev = dev_priv->dev;
3470
4fc688ce 3471 mutex_lock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3472 gen6_enable_rps(dev);
3473 gen6_update_ring_freq(dev);
4fc688ce 3474 mutex_unlock(&dev_priv->rps.hw_lock);
1a01ab3b
JB		 3475}
3476
8090c6b9
DV		 3477void intel_enable_gt_powersave(struct drm_device *dev)
3478{
1a01ab3b
JB		 3479 struct drm_i915_private *dev_priv = dev->dev_private;
3480
8090c6b9
DV		 3481 if (IS_IRONLAKE_M(dev)) {
3482 ironlake_enable_drps(dev);
3483 ironlake_enable_rc6(dev);
3484 intel_init_emon(dev);
7cf50fc8 3485 } else if ((IS_GEN6(dev) || IS_GEN7(dev)) && !IS_VALLEYVIEW(dev)) {
1a01ab3b
JB		 3486 /*
3487 * PCU communication is slow and this doesn't need to be
3488 * done at any specific time, so do this out of our fast path
3489 * to make resume and init faster.
3490 */
3491 schedule_delayed_work(&dev_priv->rps.delayed_resume_work,
3492 round_jiffies_up_relative(HZ));
8090c6b9
DV		 3493 }
3494}
3495
3107bd48
DV		 3496static void ibx_init_clock_gating(struct drm_device *dev)
3497{
3498 struct drm_i915_private *dev_priv = dev->dev_private;
3499
3500 /*
3501 * On Ibex Peak and Cougar Point, we need to disable clock
3502 * gating for the panel power sequencer or it will fail to
3503 * start up when no ports are active.
3504 */
3505 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3506}
3507
1fa61106 3508static void ironlake_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3509{
3510 struct drm_i915_private *dev_priv = dev->dev_private;
231e54f6 3511 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0
ED		 3512
3513 /* Required for FBC */
4d47e4f5
DL		 3514 dspclk_gate |= ILK_DPFCRUNIT_CLOCK_GATE_DISABLE |
3515 ILK_DPFCUNIT_CLOCK_GATE_DISABLE |
3516 ILK_DPFDUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3517
3518 I915_WRITE(PCH_3DCGDIS0,
3519 MARIUNIT_CLOCK_GATE_DISABLE |
3520 SVSMUNIT_CLOCK_GATE_DISABLE);
3521 I915_WRITE(PCH_3DCGDIS1,
3522 VFMUNIT_CLOCK_GATE_DISABLE);
3523
6f1d69b0
ED		 3524 /*
3525 * According to the spec the following bits should be set in
3526 * order to enable memory self-refresh
3527 * The bit 22/21 of 0x42004
3528 * The bit 5 of 0x42020
3529 * The bit 15 of 0x45000
3530 */
3531 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3532 (I915_READ(ILK_DISPLAY_CHICKEN2) |
3533 ILK_DPARB_GATE | ILK_VSDPFD_FULL));
4d47e4f5 3534 dspclk_gate |= ILK_DPARBUNIT_CLOCK_GATE_ENABLE;
6f1d69b0
ED		 3535 I915_WRITE(DISP_ARB_CTL,
3536 (I915_READ(DISP_ARB_CTL) |
3537 DISP_FBC_WM_DIS));
3538 I915_WRITE(WM3_LP_ILK, 0);
3539 I915_WRITE(WM2_LP_ILK, 0);
3540 I915_WRITE(WM1_LP_ILK, 0);
3541
3542 /*
3543 * Based on the document from hardware guys the following bits
3544 * should be set unconditionally in order to enable FBC.
3545 * The bit 22 of 0x42000
3546 * The bit 22 of 0x42004
3547 * The bit 7,8,9 of 0x42020.
3548 */
3549 if (IS_IRONLAKE_M(dev)) {
3550 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3551 I915_READ(ILK_DISPLAY_CHICKEN1) |
3552 ILK_FBCQ_DIS);
3553 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3554 I915_READ(ILK_DISPLAY_CHICKEN2) |
3555 ILK_DPARB_GATE);
6f1d69b0
ED		 3556 }
3557
4d47e4f5
DL		 3558 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
3559
6f1d69b0
ED		 3560 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3561 I915_READ(ILK_DISPLAY_CHICKEN2) |
3562 ILK_ELPIN_409_SELECT);
3563 I915_WRITE(_3D_CHICKEN2,
3564 _3D_CHICKEN2_WM_READ_PIPELINED << 16 |
3565 _3D_CHICKEN2_WM_READ_PIPELINED);
4358a374
DV		 3566
3567 /* WaDisableRenderCachePipelinedFlush */
3568 I915_WRITE(CACHE_MODE_0,
3569 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
3107bd48
DV		 3570
3571 ibx_init_clock_gating(dev);
3572}
3573
3574static void cpt_init_clock_gating(struct drm_device *dev)
3575{
3576 struct drm_i915_private *dev_priv = dev->dev_private;
3577 int pipe;
3578
3579 /*
3580 * On Ibex Peak and Cougar Point, we need to disable clock
3581 * gating for the panel power sequencer or it will fail to
3582 * start up when no ports are active.
3583 */
3584 I915_WRITE(SOUTH_DSPCLK_GATE_D, PCH_DPLSUNIT_CLOCK_GATE_DISABLE);
3585 I915_WRITE(SOUTH_CHICKEN2, I915_READ(SOUTH_CHICKEN2) |
3586 DPLS_EDP_PPS_FIX_DIS);
335c07b7
TI		 3587 /* The below fixes the weird display corruption, a few pixels shifted
3588 * downward, on (only) LVDS of some HP laptops with IVY.
3589 */
3590 for_each_pipe(pipe)
3591 I915_WRITE(TRANS_CHICKEN2(pipe), TRANS_CHICKEN2_TIMING_OVERRIDE);
3107bd48
DV		 3592 /* WADP0ClockGatingDisable */
3593 for_each_pipe(pipe) {
3594 I915_WRITE(TRANS_CHICKEN1(pipe),
3595 TRANS_CHICKEN1_DP0UNIT_GC_DISABLE);
3596 }
6f1d69b0
ED		 3597}
3598
1d7aaa0c
DV		 3599static void gen6_check_mch_setup(struct drm_device *dev)
3600{
3601 struct drm_i915_private *dev_priv = dev->dev_private;
3602 uint32_t tmp;
3603
3604 tmp = I915_READ(MCH_SSKPD);
3605 if ((tmp & MCH_SSKPD_WM0_MASK) != MCH_SSKPD_WM0_VAL) {
3606 DRM_INFO("Wrong MCH_SSKPD value: 0x%08x\n", tmp);
3607 DRM_INFO("This can cause pipe underruns and display issues.\n");
3608 DRM_INFO("Please upgrade your BIOS to fix this.\n");
3609 }
3610}
3611
1fa61106 3612static void gen6_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3613{
3614 struct drm_i915_private *dev_priv = dev->dev_private;
3615 int pipe;
231e54f6 3616 uint32_t dspclk_gate = ILK_VRHUNIT_CLOCK_GATE_DISABLE;
6f1d69b0 3617
231e54f6 3618 I915_WRITE(ILK_DSPCLK_GATE_D, dspclk_gate);
6f1d69b0
ED		 3619
3620 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3621 I915_READ(ILK_DISPLAY_CHICKEN2) |
3622 ILK_ELPIN_409_SELECT);
3623
4283908e
DV		 3624 /* WaDisableHiZPlanesWhenMSAAEnabled */
3625 I915_WRITE(_3D_CHICKEN,
3626 _MASKED_BIT_ENABLE(_3D_CHICKEN_HIZ_PLANE_DISABLE_MSAA_4X_SNB));
3627
6547fbdb
DV		 3628 /* WaSetupGtModeTdRowDispatch */
3629 if (IS_SNB_GT1(dev))
3630 I915_WRITE(GEN6_GT_MODE,
3631 _MASKED_BIT_ENABLE(GEN6_TD_FOUR_ROW_DISPATCH_DISABLE));
3632
6f1d69b0
ED		 3633 I915_WRITE(WM3_LP_ILK, 0);
3634 I915_WRITE(WM2_LP_ILK, 0);
3635 I915_WRITE(WM1_LP_ILK, 0);
3636
6f1d69b0 3637 I915_WRITE(CACHE_MODE_0,
50743298 3638 _MASKED_BIT_DISABLE(CM0_STC_EVICT_DISABLE_LRA_SNB));
6f1d69b0
ED		 3639
3640 I915_WRITE(GEN6_UCGCTL1,
3641 I915_READ(GEN6_UCGCTL1) |
3642 GEN6_BLBUNIT_CLOCK_GATE_DISABLE |
3643 GEN6_CSUNIT_CLOCK_GATE_DISABLE);
3644
3645 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3646 * gating disable must be set. Failure to set it results in
3647 * flickering pixels due to Z write ordering failures after
3648 * some amount of runtime in the Mesa "fire" demo, and Unigine
3649 * Sanctuary and Tropics, and apparently anything else with
3650 * alpha test or pixel discard.
3651 *
3652 * According to the spec, bit 11 (RCCUNIT) must also be set,
3653 * but we didn't debug actual testcases to find it out.
0f846f81
JB		 3654 *
3655 * Also apply WaDisableVDSUnitClockGating and
3656 * WaDisableRCPBUnitClockGating.
6f1d69b0
ED		 3657 */
3658 I915_WRITE(GEN6_UCGCTL2,
0f846f81 3659 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6f1d69b0
ED		 3660 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3661 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3662
3663 /* Bspec says we need to always set all mask bits. */
26b6e44a
KG		 3664 I915_WRITE(_3D_CHICKEN3, (0xFFFF << 16) |
3665 _3D_CHICKEN3_SF_DISABLE_FASTCLIP_CULL);
6f1d69b0
ED		 3666
3667 /*
3668 * According to the spec the following bits should be
3669 * set in order to enable memory self-refresh and fbc:
3670 * The bit21 and bit22 of 0x42000
3671 * The bit21 and bit22 of 0x42004
3672 * The bit5 and bit7 of 0x42020
3673 * The bit14 of 0x70180
3674 * The bit14 of 0x71180
3675 */
3676 I915_WRITE(ILK_DISPLAY_CHICKEN1,
3677 I915_READ(ILK_DISPLAY_CHICKEN1) |
3678 ILK_FBCQ_DIS | ILK_PABSTRETCH_DIS);
3679 I915_WRITE(ILK_DISPLAY_CHICKEN2,
3680 I915_READ(ILK_DISPLAY_CHICKEN2) |
3681 ILK_DPARB_GATE | ILK_VSDPFD_FULL);
231e54f6
DL		 3682 I915_WRITE(ILK_DSPCLK_GATE_D,
3683 I915_READ(ILK_DSPCLK_GATE_D) |
3684 ILK_DPARBUNIT_CLOCK_GATE_ENABLE |
3685 ILK_DPFDUNIT_CLOCK_GATE_ENABLE);
6f1d69b0 3686
b3bf0766 3687 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3688 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3689 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3690
6f1d69b0
ED		 3691 for_each_pipe(pipe) {
3692 I915_WRITE(DSPCNTR(pipe),
3693 I915_READ(DSPCNTR(pipe)) |
3694 DISPPLANE_TRICKLE_FEED_DISABLE);
3695 intel_flush_display_plane(dev_priv, pipe);
3696 }
f8f2ac9a
BW		 3697
3698 /* The default value should be 0x200 according to docs, but the two
3699 * platforms I checked have a 0 for this. (Maybe BIOS overrides?) */
3700 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_DISABLE(0xffff));
3701 I915_WRITE(GEN6_GT_MODE, _MASKED_BIT_ENABLE(GEN6_GT_MODE_HI));
3107bd48
DV		 3702
3703 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 3704
3705 gen6_check_mch_setup(dev);
6f1d69b0
ED		 3706}
3707
3708static void gen7_setup_fixed_func_scheduler(struct drm_i915_private *dev_priv)
3709{
3710 uint32_t reg = I915_READ(GEN7_FF_THREAD_MODE);
3711
3712 reg &= ~GEN7_FF_SCHED_MASK;
3713 reg |= GEN7_FF_TS_SCHED_HW;
3714 reg |= GEN7_FF_VS_SCHED_HW;
3715 reg |= GEN7_FF_DS_SCHED_HW;
3716
41c0b3a8
BW		 3717 /* WaVSRefCountFullforceMissDisable */
3718 if (IS_HASWELL(dev_priv->dev))
3719 reg &= ~GEN7_FF_VS_REF_CNT_FFME;
3720
6f1d69b0
ED		 3721 I915_WRITE(GEN7_FF_THREAD_MODE, reg);
3722}
3723
17a303ec
PZ		 3724static void lpt_init_clock_gating(struct drm_device *dev)
3725{
3726 struct drm_i915_private *dev_priv = dev->dev_private;
3727
3728 /*
3729 * TODO: this bit should only be enabled when really needed, then
3730 * disabled when not needed anymore in order to save power.
3731 */
3732 if (dev_priv->pch_id == INTEL_PCH_LPT_LP_DEVICE_ID_TYPE)
3733 I915_WRITE(SOUTH_DSPCLK_GATE_D,
3734 I915_READ(SOUTH_DSPCLK_GATE_D) |
3735 PCH_LP_PARTITION_LEVEL_DISABLE);
3736}
3737
cad2a2d7
ED		 3738static void haswell_init_clock_gating(struct drm_device *dev)
3739{
3740 struct drm_i915_private *dev_priv = dev->dev_private;
3741 int pipe;
cad2a2d7
ED		 3742
3743 I915_WRITE(WM3_LP_ILK, 0);
3744 I915_WRITE(WM2_LP_ILK, 0);
3745 I915_WRITE(WM1_LP_ILK, 0);
3746
3747 /* According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3748 * This implements the WaDisableRCZUnitClockGating workaround.
3749 */
3750 I915_WRITE(GEN6_UCGCTL2, GEN6_RCZUNIT_CLOCK_GATE_DISABLE);
3751
cad2a2d7
ED		 3752 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3753 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3754 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3755
3756 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3757 I915_WRITE(GEN7_L3CNTLREG1,
3758 GEN7_WA_FOR_GEN7_L3_CONTROL);
3759 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
3760 GEN7_WA_L3_CHICKEN_MODE);
3761
3762 /* This is required by WaCatErrorRejectionIssue */
3763 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3764 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3765 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3766
3767 for_each_pipe(pipe) {
3768 I915_WRITE(DSPCNTR(pipe),
3769 I915_READ(DSPCNTR(pipe)) |
3770 DISPPLANE_TRICKLE_FEED_DISABLE);
3771 intel_flush_display_plane(dev_priv, pipe);
3772 }
3773
3774 gen7_setup_fixed_func_scheduler(dev_priv);
3775
3776 /* WaDisable4x2SubspanOptimization */
3777 I915_WRITE(CACHE_MODE_1,
3778 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
1544d9d5 3779
b3bf0766
PZ		 3780 /* WaMbcDriverBootEnable */
3781 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3782 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3783
e3dff585
BW		 3784 /* WaSwitchSolVfFArbitrationPriority */
3785 I915_WRITE(GAM_ECOCHK, I915_READ(GAM_ECOCHK) | HSW_ECOCHK_ARB_PRIO_SOL);
3786
1544d9d5
ED		 3787 /* XXX: This is a workaround for early silicon revisions and should be
3788 * removed later.
3789 */
3790 I915_WRITE(WM_DBG,
3791 I915_READ(WM_DBG) |
3792 WM_DBG_DISALLOW_MULTIPLE_LP |
3793 WM_DBG_DISALLOW_SPRITE |
3794 WM_DBG_DISALLOW_MAXFIFO);
3795
17a303ec 3796 lpt_init_clock_gating(dev);
cad2a2d7
ED		 3797}
3798
1fa61106 3799static void ivybridge_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3800{
3801 struct drm_i915_private *dev_priv = dev->dev_private;
3802 int pipe;
20848223 3803 uint32_t snpcr;
6f1d69b0 3804
6f1d69b0
ED		 3805 I915_WRITE(WM3_LP_ILK, 0);
3806 I915_WRITE(WM2_LP_ILK, 0);
3807 I915_WRITE(WM1_LP_ILK, 0);
3808
231e54f6 3809 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3810
87f8020e
JB		 3811 /* WaDisableEarlyCull */
3812 I915_WRITE(_3D_CHICKEN3,
3813 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3814
62cb944f 3815 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3816 I915_WRITE(IVB_CHICKEN3,
3817 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3818 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3819
12f3382b
JB		 3820 /* WaDisablePSDDualDispatchEnable */
3821 if (IS_IVB_GT1(dev))
3822 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
3823 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3824 else
3825 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1_GT2,
3826 _MASKED_BIT_ENABLE(GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
3827
6f1d69b0
ED		 3828 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3829 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3830 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3831
3832 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
3833 I915_WRITE(GEN7_L3CNTLREG1,
3834 GEN7_WA_FOR_GEN7_L3_CONTROL);
3835 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER,
8ab43976
JB		 3836 GEN7_WA_L3_CHICKEN_MODE);
3837 if (IS_IVB_GT1(dev))
3838 I915_WRITE(GEN7_ROW_CHICKEN2,
3839 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3840 else
3841 I915_WRITE(GEN7_ROW_CHICKEN2_GT2,
3842 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3843
6f1d69b0 3844
61939d97
JB		 3845 /* WaForceL3Serialization */
3846 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3847 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3848
0f846f81
JB		 3849 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3850 * gating disable must be set. Failure to set it results in
3851 * flickering pixels due to Z write ordering failures after
3852 * some amount of runtime in the Mesa "fire" demo, and Unigine
3853 * Sanctuary and Tropics, and apparently anything else with
3854 * alpha test or pixel discard.
3855 *
3856 * According to the spec, bit 11 (RCCUNIT) must also be set,
3857 * but we didn't debug actual testcases to find it out.
3858 *
3859 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3860 * This implements the WaDisableRCZUnitClockGating workaround.
3861 */
3862 I915_WRITE(GEN6_UCGCTL2,
3863 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3864 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3865
6f1d69b0
ED		 3866 /* This is required by WaCatErrorRejectionIssue */
3867 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3868 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3869 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3870
3871 for_each_pipe(pipe) {
3872 I915_WRITE(DSPCNTR(pipe),
3873 I915_READ(DSPCNTR(pipe)) |
3874 DISPPLANE_TRICKLE_FEED_DISABLE);
3875 intel_flush_display_plane(dev_priv, pipe);
3876 }
3877
b3bf0766 3878 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3879 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3880 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3881
6f1d69b0 3882 gen7_setup_fixed_func_scheduler(dev_priv);
97e1930f
DV		 3883
3884 /* WaDisable4x2SubspanOptimization */
3885 I915_WRITE(CACHE_MODE_1,
3886 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
20848223
BW		 3887
3888 snpcr = I915_READ(GEN6_MBCUNIT_SNPCR);
3889 snpcr &= ~GEN6_MBC_SNPCR_MASK;
3890 snpcr |= GEN6_MBC_SNPCR_MED;
3891 I915_WRITE(GEN6_MBCUNIT_SNPCR, snpcr);
3107bd48
DV		 3892
3893 cpt_init_clock_gating(dev);
1d7aaa0c
DV		 3894
3895 gen6_check_mch_setup(dev);
6f1d69b0
ED		 3896}
3897
1fa61106 3898static void valleyview_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 3899{
3900 struct drm_i915_private *dev_priv = dev->dev_private;
3901 int pipe;
6f1d69b0
ED		 3902
3903 I915_WRITE(WM3_LP_ILK, 0);
3904 I915_WRITE(WM2_LP_ILK, 0);
3905 I915_WRITE(WM1_LP_ILK, 0);
3906
231e54f6 3907 I915_WRITE(ILK_DSPCLK_GATE_D, ILK_VRHUNIT_CLOCK_GATE_DISABLE);
6f1d69b0 3908
87f8020e
JB		 3909 /* WaDisableEarlyCull */
3910 I915_WRITE(_3D_CHICKEN3,
3911 _MASKED_BIT_ENABLE(_3D_CHICKEN_SF_DISABLE_OBJEND_CULL));
3912
62cb944f 3913 /* WaDisableBackToBackFlipFix */
6f1d69b0
ED		 3914 I915_WRITE(IVB_CHICKEN3,
3915 CHICKEN3_DGMG_REQ_OUT_FIX_DISABLE |
3916 CHICKEN3_DGMG_DONE_FIX_DISABLE);
3917
d3bc0303 3918 /* WaDisablePSDDualDispatchEnable */
12f3382b 3919 I915_WRITE(GEN7_HALF_SLICE_CHICKEN1,
d3bc0303
JB		 3920 _MASKED_BIT_ENABLE(GEN7_MAX_PS_THREAD_DEP |
3921 GEN7_PSD_SINGLE_PORT_DISPATCH_ENABLE));
12f3382b 3922
6f1d69b0
ED		 3923 /* Apply the WaDisableRHWOOptimizationForRenderHang workaround. */
3924 I915_WRITE(GEN7_COMMON_SLICE_CHICKEN1,
3925 GEN7_CSC1_RHWO_OPT_DISABLE_IN_RCC);
3926
3927 /* WaApplyL3ControlAndL3ChickenMode requires those two on Ivy Bridge */
d0cf5ead 3928 I915_WRITE(GEN7_L3CNTLREG1, I915_READ(GEN7_L3CNTLREG1) | GEN7_L3AGDIS);
6f1d69b0
ED		 3929 I915_WRITE(GEN7_L3_CHICKEN_MODE_REGISTER, GEN7_WA_L3_CHICKEN_MODE);
3930
61939d97
JB		 3931 /* WaForceL3Serialization */
3932 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3933 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3934
8ab43976
JB		 3935 /* WaDisableDopClockGating */
3936 I915_WRITE(GEN7_ROW_CHICKEN2,
3937 _MASKED_BIT_ENABLE(DOP_CLOCK_GATING_DISABLE));
3938
5c9664d7
JB		 3939 /* WaForceL3Serialization */
3940 I915_WRITE(GEN7_L3SQCREG4, I915_READ(GEN7_L3SQCREG4) &
3941 ~L3SQ_URB_READ_CAM_MATCH_DISABLE);
3942
6f1d69b0
ED		 3943 /* This is required by WaCatErrorRejectionIssue */
3944 I915_WRITE(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG,
3945 I915_READ(GEN7_SQ_CHICKEN_MBCUNIT_CONFIG) |
3946 GEN7_SQ_CHICKEN_MBCUNIT_SQINTMOB);
3947
b3bf0766 3948 /* WaMbcDriverBootEnable */
b4ae3f22
JB		 3949 I915_WRITE(GEN6_MBCTL, I915_READ(GEN6_MBCTL) |
3950 GEN6_MBCTL_ENABLE_BOOT_FETCH);
3951
0f846f81
JB		 3952
3953 /* According to the BSpec vol1g, bit 12 (RCPBUNIT) clock
3954 * gating disable must be set. Failure to set it results in
3955 * flickering pixels due to Z write ordering failures after
3956 * some amount of runtime in the Mesa "fire" demo, and Unigine
3957 * Sanctuary and Tropics, and apparently anything else with
3958 * alpha test or pixel discard.
3959 *
3960 * According to the spec, bit 11 (RCCUNIT) must also be set,
3961 * but we didn't debug actual testcases to find it out.
3962 *
3963 * According to the spec, bit 13 (RCZUNIT) must be set on IVB.
3964 * This implements the WaDisableRCZUnitClockGating workaround.
3965 *
3966 * Also apply WaDisableVDSUnitClockGating and
3967 * WaDisableRCPBUnitClockGating.
3968 */
3969 I915_WRITE(GEN6_UCGCTL2,
3970 GEN7_VDSUNIT_CLOCK_GATE_DISABLE |
6edaa7fc 3971 GEN7_TDLUNIT_CLOCK_GATE_DISABLE |
0f846f81
JB		 3972 GEN6_RCZUNIT_CLOCK_GATE_DISABLE |
3973 GEN6_RCPBUNIT_CLOCK_GATE_DISABLE |
3974 GEN6_RCCUNIT_CLOCK_GATE_DISABLE);
3975
e3f33d46
JB		 3976 I915_WRITE(GEN7_UCGCTL4, GEN7_L3BANK2X_CLOCK_GATE_DISABLE);
3977
6f1d69b0
ED		 3978 for_each_pipe(pipe) {
3979 I915_WRITE(DSPCNTR(pipe),
3980 I915_READ(DSPCNTR(pipe)) |
3981 DISPPLANE_TRICKLE_FEED_DISABLE);
3982 intel_flush_display_plane(dev_priv, pipe);
3983 }
3984
6b26c86d
DV		 3985 I915_WRITE(CACHE_MODE_1,
3986 _MASKED_BIT_ENABLE(PIXEL_SUBSPAN_COLLECT_OPT_DISABLE));
7983117f 3987
2d809570
JB		 3988 /*
3989 * WaDisableVLVClockGating_VBIIssue
3990 * Disable clock gating on th GCFG unit to prevent a delay
3991 * in the reporting of vblank events.
3992 */
4e8c84a5
JB		 3993 I915_WRITE(VLV_GUNIT_CLOCK_GATE, 0xffffffff);
3994
3995 /* Conservative clock gating settings for now */
3996 I915_WRITE(0x9400, 0xffffffff);
3997 I915_WRITE(0x9404, 0xffffffff);
3998 I915_WRITE(0x9408, 0xffffffff);
3999 I915_WRITE(0x940c, 0xffffffff);
4000 I915_WRITE(0x9410, 0xffffffff);
4001 I915_WRITE(0x9414, 0xffffffff);
4002 I915_WRITE(0x9418, 0xffffffff);
6f1d69b0
ED		 4003}
4004
1fa61106 4005static void g4x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4006{
4007 struct drm_i915_private *dev_priv = dev->dev_private;
4008 uint32_t dspclk_gate;
4009
4010 I915_WRITE(RENCLK_GATE_D1, 0);
4011 I915_WRITE(RENCLK_GATE_D2, VF_UNIT_CLOCK_GATE_DISABLE |
4012 GS_UNIT_CLOCK_GATE_DISABLE |
4013 CL_UNIT_CLOCK_GATE_DISABLE);
4014 I915_WRITE(RAMCLK_GATE_D, 0);
4015 dspclk_gate = VRHUNIT_CLOCK_GATE_DISABLE |
4016 OVRUNIT_CLOCK_GATE_DISABLE |
4017 OVCUNIT_CLOCK_GATE_DISABLE;
4018 if (IS_GM45(dev))
4019 dspclk_gate |= DSSUNIT_CLOCK_GATE_DISABLE;
4020 I915_WRITE(DSPCLK_GATE_D, dspclk_gate);
4358a374
DV		 4021
4022 /* WaDisableRenderCachePipelinedFlush */
4023 I915_WRITE(CACHE_MODE_0,
4024 _MASKED_BIT_ENABLE(CM0_PIPELINED_RENDER_FLUSH_DISABLE));
6f1d69b0
ED		 4025}
4026
1fa61106 4027static void crestline_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4028{
4029 struct drm_i915_private *dev_priv = dev->dev_private;
4030
4031 I915_WRITE(RENCLK_GATE_D1, I965_RCC_CLOCK_GATE_DISABLE);
4032 I915_WRITE(RENCLK_GATE_D2, 0);
4033 I915_WRITE(DSPCLK_GATE_D, 0);
4034 I915_WRITE(RAMCLK_GATE_D, 0);
4035 I915_WRITE16(DEUC, 0);
4036}
4037
1fa61106 4038static void broadwater_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4039{
4040 struct drm_i915_private *dev_priv = dev->dev_private;
4041
4042 I915_WRITE(RENCLK_GATE_D1, I965_RCZ_CLOCK_GATE_DISABLE |
4043 I965_RCC_CLOCK_GATE_DISABLE |
4044 I965_RCPB_CLOCK_GATE_DISABLE |
4045 I965_ISC_CLOCK_GATE_DISABLE |
4046 I965_FBC_CLOCK_GATE_DISABLE);
4047 I915_WRITE(RENCLK_GATE_D2, 0);
4048}
4049
1fa61106 4050static void gen3_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4051{
4052 struct drm_i915_private *dev_priv = dev->dev_private;
4053 u32 dstate = I915_READ(D_STATE);
4054
4055 dstate |= DSTATE_PLL_D3_OFF | DSTATE_GFX_CLOCK_GATING |
4056 DSTATE_DOT_CLOCK_GATING;
4057 I915_WRITE(D_STATE, dstate);
13a86b85
CW		 4058
4059 if (IS_PINEVIEW(dev))
4060 I915_WRITE(ECOSKPD, _MASKED_BIT_ENABLE(ECO_GATING_CX_ONLY));
974a3b0f
DV		 4061
4062 /* IIR "flip pending" means done if this bit is set */
4063 I915_WRITE(ECOSKPD, _MASKED_BIT_DISABLE(ECO_FLIP_DONE));
6f1d69b0
ED		 4064}
4065
1fa61106 4066static void i85x_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4067{
4068 struct drm_i915_private *dev_priv = dev->dev_private;
4069
4070 I915_WRITE(RENCLK_GATE_D1, SV_CLOCK_GATE_DISABLE);
4071}
4072
1fa61106 4073static void i830_init_clock_gating(struct drm_device *dev)
6f1d69b0
ED		 4074{
4075 struct drm_i915_private *dev_priv = dev->dev_private;
4076
4077 I915_WRITE(DSPCLK_GATE_D, OVRUNIT_CLOCK_GATE_DISABLE);
4078}
4079
6f1d69b0
ED		 4080void intel_init_clock_gating(struct drm_device *dev)
4081{
4082 struct drm_i915_private *dev_priv = dev->dev_private;
4083
4084 dev_priv->display.init_clock_gating(dev);
6f1d69b0
ED		 4085}
4086
cb10799c 4087void intel_set_power_well(struct drm_device *dev, bool enable)
d0d3e513
ED		 4088{
4089 struct drm_i915_private *dev_priv = dev->dev_private;
fa42e23c
PZ		 4090 bool is_enabled, enable_requested;
4091 uint32_t tmp;
d0d3e513 4092
86d52df6 4093 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4094 return;
4095
2124b72e
PZ		 4096 if (!i915_disable_power_well && !enable)
4097 return;
4098
fa42e23c
PZ		 4099 tmp = I915_READ(HSW_PWR_WELL_DRIVER);
4100 is_enabled = tmp & HSW_PWR_WELL_STATE;
4101 enable_requested = tmp & HSW_PWR_WELL_ENABLE;
d0d3e513 4102
fa42e23c
PZ		 4103 if (enable) {
4104 if (!enable_requested)
4105 I915_WRITE(HSW_PWR_WELL_DRIVER, HSW_PWR_WELL_ENABLE);
d0d3e513 4106
fa42e23c
PZ		 4107 if (!is_enabled) {
4108 DRM_DEBUG_KMS("Enabling power well\n");
4109 if (wait_for((I915_READ(HSW_PWR_WELL_DRIVER) &
4110 HSW_PWR_WELL_STATE), 20))
4111 DRM_ERROR("Timeout enabling power well\n");
4112 }
4113 } else {
4114 if (enable_requested) {
4115 I915_WRITE(HSW_PWR_WELL_DRIVER, 0);
4116 DRM_DEBUG_KMS("Requesting to disable the power well\n");
d0d3e513
ED		 4117 }
4118 }
fa42e23c 4119}
d0d3e513 4120
fa42e23c
PZ		 4121/*
4122 * Starting with Haswell, we have a "Power Down Well" that can be turned off
4123 * when not needed anymore. We have 4 registers that can request the power well
4124 * to be enabled, and it will only be disabled if none of the registers is
4125 * requesting it to be enabled.
d0d3e513 4126 */
fa42e23c 4127void intel_init_power_well(struct drm_device *dev)
d0d3e513
ED		 4128{
4129 struct drm_i915_private *dev_priv = dev->dev_private;
d0d3e513 4130
86d52df6 4131 if (!HAS_POWER_WELL(dev))
d0d3e513
ED		 4132 return;
4133
fa42e23c
PZ		 4134 /* For now, we need the power well to be always enabled. */
4135 intel_set_power_well(dev, true);
d0d3e513 4136
fa42e23c
PZ		 4137 /* We're taking over the BIOS, so clear any requests made by it since
4138 * the driver is in charge now. */
4139 if (I915_READ(HSW_PWR_WELL_BIOS) & HSW_PWR_WELL_ENABLE)
4140 I915_WRITE(HSW_PWR_WELL_BIOS, 0);
d0d3e513
ED		 4141}
4142
1fa61106
ED		 4143/* Set up chip specific power management-related functions */
4144void intel_init_pm(struct drm_device *dev)
4145{
4146 struct drm_i915_private *dev_priv = dev->dev_private;
4147
4148 if (I915_HAS_FBC(dev)) {
4149 if (HAS_PCH_SPLIT(dev)) {
4150 dev_priv->display.fbc_enabled = ironlake_fbc_enabled;
4151 dev_priv->display.enable_fbc = ironlake_enable_fbc;
4152 dev_priv->display.disable_fbc = ironlake_disable_fbc;
4153 } else if (IS_GM45(dev)) {
4154 dev_priv->display.fbc_enabled = g4x_fbc_enabled;
4155 dev_priv->display.enable_fbc = g4x_enable_fbc;
4156 dev_priv->display.disable_fbc = g4x_disable_fbc;
4157 } else if (IS_CRESTLINE(dev)) {
4158 dev_priv->display.fbc_enabled = i8xx_fbc_enabled;
4159 dev_priv->display.enable_fbc = i8xx_enable_fbc;
4160 dev_priv->display.disable_fbc = i8xx_disable_fbc;
4161 }
4162 /* 855GM needs testing */
4163 }
4164
c921aba8
DV		 4165 /* For cxsr */
4166 if (IS_PINEVIEW(dev))
4167 i915_pineview_get_mem_freq(dev);
4168 else if (IS_GEN5(dev))
4169 i915_ironlake_get_mem_freq(dev);
4170
1fa61106
ED		 4171 /* For FIFO watermark updates */
4172 if (HAS_PCH_SPLIT(dev)) {
1fa61106
ED		 4173 if (IS_GEN5(dev)) {
4174 if (I915_READ(MLTR_ILK) & ILK_SRLT_MASK)
4175 dev_priv->display.update_wm = ironlake_update_wm;
4176 else {
4177 DRM_DEBUG_KMS("Failed to get proper latency. "
4178 "Disable CxSR\n");
4179 dev_priv->display.update_wm = NULL;
4180 }
4181 dev_priv->display.init_clock_gating = ironlake_init_clock_gating;
4182 } else if (IS_GEN6(dev)) {
4183 if (SNB_READ_WM0_LATENCY()) {
4184 dev_priv->display.update_wm = sandybridge_update_wm;
4185 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4186 } else {
4187 DRM_DEBUG_KMS("Failed to read display plane latency. "
4188 "Disable CxSR\n");
4189 dev_priv->display.update_wm = NULL;
4190 }
4191 dev_priv->display.init_clock_gating = gen6_init_clock_gating;
4192 } else if (IS_IVYBRIDGE(dev)) {
4193 /* FIXME: detect B0+ stepping and use auto training */
4194 if (SNB_READ_WM0_LATENCY()) {
c43d0188 4195 dev_priv->display.update_wm = ivybridge_update_wm;
1fa61106
ED		 4196 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
4197 } else {
4198 DRM_DEBUG_KMS("Failed to read display plane latency. "
4199 "Disable CxSR\n");
4200 dev_priv->display.update_wm = NULL;
4201 }
4202 dev_priv->display.init_clock_gating = ivybridge_init_clock_gating;
6b8a5eeb
ED		 4203 } else if (IS_HASWELL(dev)) {
4204 if (SNB_READ_WM0_LATENCY()) {
4205 dev_priv->display.update_wm = sandybridge_update_wm;
4206 dev_priv->display.update_sprite_wm = sandybridge_update_sprite_wm;
1f8eeabf 4207 dev_priv->display.update_linetime_wm = haswell_update_linetime_wm;
6b8a5eeb
ED		 4208 } else {
4209 DRM_DEBUG_KMS("Failed to read display plane latency. "
4210 "Disable CxSR\n");
4211 dev_priv->display.update_wm = NULL;
4212 }
cad2a2d7 4213 dev_priv->display.init_clock_gating = haswell_init_clock_gating;
1fa61106
ED		 4214 } else
4215 dev_priv->display.update_wm = NULL;
4216 } else if (IS_VALLEYVIEW(dev)) {
4217 dev_priv->display.update_wm = valleyview_update_wm;
4218 dev_priv->display.init_clock_gating =
4219 valleyview_init_clock_gating;
1fa61106
ED		 4220 } else if (IS_PINEVIEW(dev)) {
4221 if (!intel_get_cxsr_latency(IS_PINEVIEW_G(dev),
4222 dev_priv->is_ddr3,
4223 dev_priv->fsb_freq,
4224 dev_priv->mem_freq)) {
4225 DRM_INFO("failed to find known CxSR latency "
4226 "(found ddr%s fsb freq %d, mem freq %d), "
4227 "disabling CxSR\n",
4228 (dev_priv->is_ddr3 == 1) ? "3" : "2",
4229 dev_priv->fsb_freq, dev_priv->mem_freq);
4230 /* Disable CxSR and never update its watermark again */
4231 pineview_disable_cxsr(dev);
4232 dev_priv->display.update_wm = NULL;
4233 } else
4234 dev_priv->display.update_wm = pineview_update_wm;
4235 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4236 } else if (IS_G4X(dev)) {
4237 dev_priv->display.update_wm = g4x_update_wm;
4238 dev_priv->display.init_clock_gating = g4x_init_clock_gating;
4239 } else if (IS_GEN4(dev)) {
4240 dev_priv->display.update_wm = i965_update_wm;
4241 if (IS_CRESTLINE(dev))
4242 dev_priv->display.init_clock_gating = crestline_init_clock_gating;
4243 else if (IS_BROADWATER(dev))
4244 dev_priv->display.init_clock_gating = broadwater_init_clock_gating;
4245 } else if (IS_GEN3(dev)) {
4246 dev_priv->display.update_wm = i9xx_update_wm;
4247 dev_priv->display.get_fifo_size = i9xx_get_fifo_size;
4248 dev_priv->display.init_clock_gating = gen3_init_clock_gating;
4249 } else if (IS_I865G(dev)) {
4250 dev_priv->display.update_wm = i830_update_wm;
4251 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4252 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4253 } else if (IS_I85X(dev)) {
4254 dev_priv->display.update_wm = i9xx_update_wm;
4255 dev_priv->display.get_fifo_size = i85x_get_fifo_size;
4256 dev_priv->display.init_clock_gating = i85x_init_clock_gating;
4257 } else {
4258 dev_priv->display.update_wm = i830_update_wm;
4259 dev_priv->display.init_clock_gating = i830_init_clock_gating;
4260 if (IS_845G(dev))
4261 dev_priv->display.get_fifo_size = i845_get_fifo_size;
4262 else
4263 dev_priv->display.get_fifo_size = i830_get_fifo_size;
4264 }
4265}
4266
6590190d
ED		 4267static void __gen6_gt_wait_for_thread_c0(struct drm_i915_private *dev_priv)
4268{
4269 u32 gt_thread_status_mask;
4270
4271 if (IS_HASWELL(dev_priv->dev))
4272 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK_HSW;
4273 else
4274 gt_thread_status_mask = GEN6_GT_THREAD_STATUS_CORE_MASK;
4275
4276 /* w/a for a sporadic read returning 0 by waiting for the GT
4277 * thread to wake up.
4278 */
4279 if (wait_for_atomic_us((I915_READ_NOTRACE(GEN6_GT_THREAD_STATUS_REG) & gt_thread_status_mask) == 0, 500))
4280 DRM_ERROR("GT thread status wait timed out\n");
4281}
4282
16995a9f
CW		 4283static void __gen6_gt_force_wake_reset(struct drm_i915_private *dev_priv)
4284{
4285 I915_WRITE_NOTRACE(FORCEWAKE, 0);
4286 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
4287}
4288
6590190d
ED		 4289static void __gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4290{
ebd37ce1 4291 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1) == 0,
057d3860 4292 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4293 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4294
30771e16 4295 I915_WRITE_NOTRACE(FORCEWAKE, 1);
8dee3eea 4296 POSTING_READ(ECOBUS); /* something from same cacheline, but !FORCEWAKE */
6590190d 4297
ebd37ce1 4298 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK) & 1),
057d3860 4299 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4300 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4301
4302 __gen6_gt_wait_for_thread_c0(dev_priv);
4303}
4304
16995a9f
CW		 4305static void __gen6_gt_force_wake_mt_reset(struct drm_i915_private *dev_priv)
4306{
4307 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 4308 /* something from same cacheline, but !FORCEWAKE_MT */
4309 POSTING_READ(ECOBUS);
16995a9f
CW		 4310}
4311
6590190d
ED		 4312static void __gen6_gt_force_wake_mt_get(struct drm_i915_private *dev_priv)
4313{
4314 u32 forcewake_ack;
4315
4316 if (IS_HASWELL(dev_priv->dev))
4317 forcewake_ack = FORCEWAKE_ACK_HSW;
4318 else
4319 forcewake_ack = FORCEWAKE_MT_ACK;
4320
83983c8b 4321 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL) == 0,
057d3860 4322 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4323 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4324
c5836c27 4325 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
b5144075
JN		 4326 /* something from same cacheline, but !FORCEWAKE_MT */
4327 POSTING_READ(ECOBUS);
6590190d 4328
83983c8b 4329 if (wait_for_atomic((I915_READ_NOTRACE(forcewake_ack) & FORCEWAKE_KERNEL),
057d3860 4330 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4331 DRM_ERROR("Timed out waiting for forcewake to ack request.\n");
6590190d
ED		 4332
4333 __gen6_gt_wait_for_thread_c0(dev_priv);
4334}
4335
4336/*
4337 * Generally this is called implicitly by the register read function. However,
4338 * if some sequence requires the GT to not power down then this function should
4339 * be called at the beginning of the sequence followed by a call to
4340 * gen6_gt_force_wake_put() at the end of the sequence.
4341 */
4342void gen6_gt_force_wake_get(struct drm_i915_private *dev_priv)
4343{
4344 unsigned long irqflags;
4345
4346 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4347 if (dev_priv->forcewake_count++ == 0)
4348 dev_priv->gt.force_wake_get(dev_priv);
4349 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4350}
4351
4352void gen6_gt_check_fifodbg(struct drm_i915_private *dev_priv)
4353{
4354 u32 gtfifodbg;
4355 gtfifodbg = I915_READ_NOTRACE(GTFIFODBG);
4356 if (WARN(gtfifodbg & GT_FIFO_CPU_ERROR_MASK,
4357 "MMIO read or write has been dropped %x\n", gtfifodbg))
4358 I915_WRITE_NOTRACE(GTFIFODBG, GT_FIFO_CPU_ERROR_MASK);
4359}
4360
4361static void __gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4362{
4363 I915_WRITE_NOTRACE(FORCEWAKE, 0);
b5144075
JN		 4364 /* something from same cacheline, but !FORCEWAKE */
4365 POSTING_READ(ECOBUS);
6590190d
ED		 4366 gen6_gt_check_fifodbg(dev_priv);
4367}
4368
4369static void __gen6_gt_force_wake_mt_put(struct drm_i915_private *dev_priv)
4370{
c5836c27 4371 I915_WRITE_NOTRACE(FORCEWAKE_MT, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
b5144075
JN		 4372 /* something from same cacheline, but !FORCEWAKE_MT */
4373 POSTING_READ(ECOBUS);
6590190d
ED		 4374 gen6_gt_check_fifodbg(dev_priv);
4375}
4376
4377/*
4378 * see gen6_gt_force_wake_get()
4379 */
4380void gen6_gt_force_wake_put(struct drm_i915_private *dev_priv)
4381{
4382 unsigned long irqflags;
4383
4384 spin_lock_irqsave(&dev_priv->gt_lock, irqflags);
4385 if (--dev_priv->forcewake_count == 0)
4386 dev_priv->gt.force_wake_put(dev_priv);
4387 spin_unlock_irqrestore(&dev_priv->gt_lock, irqflags);
4388}
4389
4390int __gen6_gt_wait_for_fifo(struct drm_i915_private *dev_priv)
4391{
4392 int ret = 0;
4393
4394 if (dev_priv->gt_fifo_count < GT_FIFO_NUM_RESERVED_ENTRIES) {
4395 int loop = 500;
4396 u32 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4397 while (fifo <= GT_FIFO_NUM_RESERVED_ENTRIES && loop--) {
4398 udelay(10);
4399 fifo = I915_READ_NOTRACE(GT_FIFO_FREE_ENTRIES);
4400 }
4401 if (WARN_ON(loop < 0 && fifo <= GT_FIFO_NUM_RESERVED_ENTRIES))
4402 ++ret;
4403 dev_priv->gt_fifo_count = fifo;
4404 }
4405 dev_priv->gt_fifo_count--;
4406
4407 return ret;
4408}
4409
16995a9f
CW		 4410static void vlv_force_wake_reset(struct drm_i915_private *dev_priv)
4411{
4412 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(0xffff));
b5144075
JN		 4413 /* something from same cacheline, but !FORCEWAKE_VLV */
4414 POSTING_READ(FORCEWAKE_ACK_VLV);
16995a9f
CW		 4415}
4416
6590190d
ED		 4417static void vlv_force_wake_get(struct drm_i915_private *dev_priv)
4418{
83983c8b 4419 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL) == 0,
057d3860 4420 FORCEWAKE_ACK_TIMEOUT_MS))
8a038fd6 4421 DRM_ERROR("Timed out waiting for forcewake old ack to clear.\n");
6590190d 4422
c5836c27 4423 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 4424 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4425 _MASKED_BIT_ENABLE(FORCEWAKE_KERNEL));
6590190d 4426
83983c8b 4427 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_VLV) & FORCEWAKE_KERNEL),
057d3860 4428 FORCEWAKE_ACK_TIMEOUT_MS))
ed5de399
JB		 4429 DRM_ERROR("Timed out waiting for GT to ack forcewake request.\n");
4430
4431 if (wait_for_atomic((I915_READ_NOTRACE(FORCEWAKE_ACK_MEDIA_VLV) &
4432 FORCEWAKE_KERNEL),
4433 FORCEWAKE_ACK_TIMEOUT_MS))
4434 DRM_ERROR("Timed out waiting for media to ack forcewake request.\n");
6590190d
ED		 4435
4436 __gen6_gt_wait_for_thread_c0(dev_priv);
4437}
4438
4439static void vlv_force_wake_put(struct drm_i915_private *dev_priv)
4440{
c5836c27 4441 I915_WRITE_NOTRACE(FORCEWAKE_VLV, _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
ed5de399
JB		 4442 I915_WRITE_NOTRACE(FORCEWAKE_MEDIA_VLV,
4443 _MASKED_BIT_DISABLE(FORCEWAKE_KERNEL));
4444 /* The below doubles as a POSTING_READ */
5ab140a4 4445 gen6_gt_check_fifodbg(dev_priv);
6590190d
ED		 4446}
4447
16995a9f
CW		 4448void intel_gt_reset(struct drm_device *dev)
4449{
4450 struct drm_i915_private *dev_priv = dev->dev_private;
4451
4452 if (IS_VALLEYVIEW(dev)) {
4453 vlv_force_wake_reset(dev_priv);
4454 } else if (INTEL_INFO(dev)->gen >= 6) {
4455 __gen6_gt_force_wake_reset(dev_priv);
4456 if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev))
4457 __gen6_gt_force_wake_mt_reset(dev_priv);
4458 }
4459}
4460
6590190d
ED		 4461void intel_gt_init(struct drm_device *dev)
4462{
4463 struct drm_i915_private *dev_priv = dev->dev_private;
4464
4465 spin_lock_init(&dev_priv->gt_lock);
4466
16995a9f
CW		 4467 intel_gt_reset(dev);
4468
6590190d
ED		 4469 if (IS_VALLEYVIEW(dev)) {
4470 dev_priv->gt.force_wake_get = vlv_force_wake_get;
4471 dev_priv->gt.force_wake_put = vlv_force_wake_put;
36ec8f87
DV		 4472 } else if (IS_IVYBRIDGE(dev) || IS_HASWELL(dev)) {
4473 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_mt_get;
4474 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_mt_put;
4475 } else if (IS_GEN6(dev)) {
6590190d
ED		 4476 dev_priv->gt.force_wake_get = __gen6_gt_force_wake_get;
4477 dev_priv->gt.force_wake_put = __gen6_gt_force_wake_put;
6590190d 4478 }
1a01ab3b
JB		 4479 INIT_DELAYED_WORK(&dev_priv->rps.delayed_resume_work,
4480 intel_gen6_powersave_work);
6590190d
ED		 4481}
4482
42c0526c
BW		 4483int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u8 mbox, u32 *val)
4484{
4fc688ce 4485 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4486
4487 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4488 DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access failed\n");
4489 return -EAGAIN;
4490 }
4491
4492 I915_WRITE(GEN6_PCODE_DATA, *val);
4493 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4494
4495 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4496 500)) {
4497 DRM_ERROR("timeout waiting for pcode read (%d) to finish\n", mbox);
4498 return -ETIMEDOUT;
4499 }
4500
4501 *val = I915_READ(GEN6_PCODE_DATA);
4502 I915_WRITE(GEN6_PCODE_DATA, 0);
4503
4504 return 0;
4505}
4506
4507int sandybridge_pcode_write(struct drm_i915_private *dev_priv, u8 mbox, u32 val)
4508{
4fc688ce 4509 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
42c0526c
BW		 4510
4511 if (I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) {
4512 DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access failed\n");
4513 return -EAGAIN;
4514 }
4515
4516 I915_WRITE(GEN6_PCODE_DATA, val);
4517 I915_WRITE(GEN6_PCODE_MAILBOX, GEN6_PCODE_READY | mbox);
4518
4519 if (wait_for((I915_READ(GEN6_PCODE_MAILBOX) & GEN6_PCODE_READY) == 0,
4520 500)) {
4521 DRM_ERROR("timeout waiting for pcode write (%d) to finish\n", mbox);
4522 return -ETIMEDOUT;
4523 }
4524
4525 I915_WRITE(GEN6_PCODE_DATA, 0);
4526
4527 return 0;
4528}
a0e4e199
JB		 4529
4530static int vlv_punit_rw(struct drm_i915_private *dev_priv, u8 opcode,
4531 u8 addr, u32 *val)
4532{
4533 u32 cmd, devfn, port, be, bar;
4534
4535 bar = 0;
4536 be = 0xf;
4537 port = IOSF_PORT_PUNIT;
4538 devfn = PCI_DEVFN(2, 0);
4539
4540 cmd = (devfn << IOSF_DEVFN_SHIFT) | (opcode << IOSF_OPCODE_SHIFT) |
4541 (port << IOSF_PORT_SHIFT) | (be << IOSF_BYTE_ENABLES_SHIFT) |
4542 (bar << IOSF_BAR_SHIFT);
4543
4544 WARN_ON(!mutex_is_locked(&dev_priv->rps.hw_lock));
4545
4546 if (I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) {
4547 DRM_DEBUG_DRIVER("warning: pcode (%s) mailbox access failed\n",
4548 opcode == PUNIT_OPCODE_REG_READ ?
4549 "read" : "write");
4550 return -EAGAIN;
4551 }
4552
4553 I915_WRITE(VLV_IOSF_ADDR, addr);
4554 if (opcode == PUNIT_OPCODE_REG_WRITE)
4555 I915_WRITE(VLV_IOSF_DATA, *val);
4556 I915_WRITE(VLV_IOSF_DOORBELL_REQ, cmd);
4557
4558 if (wait_for((I915_READ(VLV_IOSF_DOORBELL_REQ) & IOSF_SB_BUSY) == 0,
4559 500)) {
4560 DRM_ERROR("timeout waiting for pcode %s (%d) to finish\n",
4561 opcode == PUNIT_OPCODE_REG_READ ? "read" : "write",
4562 addr);
4563 return -ETIMEDOUT;
4564 }
4565
4566 if (opcode == PUNIT_OPCODE_REG_READ)
4567 *val = I915_READ(VLV_IOSF_DATA);
4568 I915_WRITE(VLV_IOSF_DATA, 0);
4569
4570 return 0;
4571}
4572
4573int valleyview_punit_read(struct drm_i915_private *dev_priv, u8 addr, u32 *val)
4574{
4575 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_READ, addr, val);
4576}
4577
4578int valleyview_punit_write(struct drm_i915_private *dev_priv, u8 addr, u32 val)
4579{
4580 return vlv_punit_rw(dev_priv, PUNIT_OPCODE_REG_WRITE, addr, &val);
4581}
Ubuntu Hirsute Linux kernel mirror